Introduce the new kernel sub-tree x86 which should contain all the code

shared and generalized between our current amd64, i386 and pc98.

This is just an initial step that should lead to a more complete effort.
For the moment, a very simple porting of cpufreq modules, BIOS calls and
the whole MD specific ISA bus part is added to the sub-tree but ideally
a lot of code might be added and more shared support should grow.

Sponsored by:	Sandvine Incorporated
Reviewed by:	emaste, kib, jhb, imp
Discussed on:	arch
MFC:		3 weeks

17 files changed, 7491 insertions, 0 deletions

diff --git a/sys/x86/bios/smbios.c b/sys/x86/bios/smbios.c
new file mode 100644
index 0000000..f38d985
--- /dev/null
+++ b/sys/x86/bios/smbios.c
@@ -0,0 +1,277 @@
+/*-
+ * Copyright (c) 2003 Matthew N. Dodd <winter@jurai.net>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+
+#include <sys/module.h>
+#include <sys/bus.h>
+
+#include <machine/bus.h>
+#include <machine/resource.h>
+#include <sys/rman.h>
+
+#include <vm/vm.h>
+#include <vm/vm_param.h>
+#include <vm/pmap.h>
+#include <machine/md_var.h>
+#include <machine/pc/bios.h>
+
+/*
+ * System Management BIOS Reference Specification, v2.4 Final
+ * http://www.dmtf.org/standards/published_documents/DSP0134.pdf
+ */
+
+/*
+ * SMBIOS Entry Point Structure
+ */
+struct smbios_eps {
+	u_int8_t	Anchor[4];		/* '_SM_' */
+	u_int8_t	Checksum;
+	u_int8_t	Length;
+
+	u_int8_t	SMBIOS_Major;
+	u_int8_t	SMBIOS_Minor;
+	u_int16_t	Max_Size;
+	u_int8_t	Revision;
+	u_int8_t	Formatted_Area[5];
+
+	u_int8_t	Intermediate_Anchor[5];	/* '_DMI_' */
+	u_int8_t	Intermediate_Checksum;
+
+	u_int16_t	Structure_Table_Length;
+	u_int32_t	Structure_Table_Address;
+	u_int16_t	Structure_Count;
+
+	u_int8_t	SMBIOS_BCD_Revision;
+} __packed;
+
+struct smbios_softc {
+	device_t		dev;
+	struct resource *	res;
+	int			rid;
+
+	struct smbios_eps *	eps;
+};
+
+#define	SMBIOS_START	0xf0000
+#define	SMBIOS_STEP	0x10
+#define	SMBIOS_OFF	0
+#define	SMBIOS_LEN	4
+#define	SMBIOS_SIG	"_SM_"
+
+#define	RES2EPS(res)	((struct smbios_eps *)rman_get_virtual(res))
+#define	ADDR2EPS(addr)  ((struct smbios_eps *)BIOS_PADDRTOVADDR(addr))
+
+static devclass_t	smbios_devclass;
+
+static void	smbios_identify	(driver_t *, device_t);
+static int	smbios_probe	(device_t);
+static int	smbios_attach	(device_t);
+static int	smbios_detach	(device_t);
+static int	smbios_modevent	(module_t, int, void *);
+
+static int	smbios_cksum	(struct smbios_eps *);
+
+static void
+smbios_identify (driver_t *driver, device_t parent)
+{
+	device_t child;
+	u_int32_t addr;
+	int length;
+	int rid;
+
+	if (!device_is_alive(parent))
+		return;
+
+	addr = bios_sigsearch(SMBIOS_START, SMBIOS_SIG, SMBIOS_LEN,
+			      SMBIOS_STEP, SMBIOS_OFF);
+	if (addr != 0) {
+		rid = 0;
+		length = ADDR2EPS(addr)->Length;
+
+		if (length != 0x1f) {
+			u_int8_t major, minor;
+
+			major = ADDR2EPS(addr)->SMBIOS_Major;
+			minor = ADDR2EPS(addr)->SMBIOS_Minor;
+
+			/* SMBIOS v2.1 implementation might use 0x1e. */
+			if (length == 0x1e && major == 2 && minor == 1)
+				length = 0x1f;
+			else
+				return;
+		}
+
+		child = BUS_ADD_CHILD(parent, 5, "smbios", -1);
+		device_set_driver(child, driver);
+		bus_set_resource(child, SYS_RES_MEMORY, rid, addr, length);
+		device_set_desc(child, "System Management BIOS");
+	}
+
+	return;
+}
+
+static int
+smbios_probe (device_t dev)
+{
+	struct resource *res;
+	int rid;
+	int error;
+
+	error = 0;
+	rid = 0;
+	res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
+	if (res == NULL) {
+		device_printf(dev, "Unable to allocate memory resource.\n");
+		error = ENOMEM;
+		goto bad;
+	}
+
+	if (smbios_cksum(RES2EPS(res))) {
+		device_printf(dev, "SMBIOS checksum failed.\n");
+		error = ENXIO;
+		goto bad;
+	}
+
+bad:
+	if (res)
+		bus_release_resource(dev, SYS_RES_MEMORY, rid, res);
+	return (error);
+}
+
+static int
+smbios_attach (device_t dev)
+{
+	struct smbios_softc *sc;
+	int error;
+
+	sc = device_get_softc(dev);
+	error = 0;
+
+	sc->dev = dev;
+	sc->rid = 0;
+	sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid,
+		RF_ACTIVE);
+	if (sc->res == NULL) {
+		device_printf(dev, "Unable to allocate memory resource.\n");
+		error = ENOMEM;
+		goto bad;
+	}
+	sc->eps = RES2EPS(sc->res);
+
+	device_printf(dev, "Version: %u.%u",
+		sc->eps->SMBIOS_Major, sc->eps->SMBIOS_Minor);
+	if (bcd2bin(sc->eps->SMBIOS_BCD_Revision))
+		printf(", BCD Revision: %u.%u",
+			bcd2bin(sc->eps->SMBIOS_BCD_Revision >> 4),
+			bcd2bin(sc->eps->SMBIOS_BCD_Revision & 0x0f));
+	printf("\n");
+
+	return (0);
+bad:
+	if (sc->res)
+		bus_release_resource(dev, SYS_RES_MEMORY, sc->rid, sc->res);
+	return (error);
+}
+
+static int
+smbios_detach (device_t dev)
+{
+	struct smbios_softc *sc;
+
+	sc = device_get_softc(dev);
+
+	if (sc->res)
+		bus_release_resource(dev, SYS_RES_MEMORY, sc->rid, sc->res);
+
+	return (0);
+}
+
+static int
+smbios_modevent (mod, what, arg)
+        module_t        mod;
+        int             what;
+        void *          arg;
+{
+	device_t *	devs;
+	int		count;
+	int		i;
+
+	switch (what) {
+	case MOD_LOAD:
+		break;
+	case MOD_UNLOAD:
+		devclass_get_devices(smbios_devclass, &devs, &count);
+		for (i = 0; i < count; i++) {
+			device_delete_child(device_get_parent(devs[i]), devs[i]);
+		}
+		break;
+	default:
+		break;
+	}
+
+	return (0);
+}
+
+static device_method_t smbios_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_identify,      smbios_identify),
+	DEVMETHOD(device_probe,         smbios_probe),
+	DEVMETHOD(device_attach,        smbios_attach),
+	DEVMETHOD(device_detach,        smbios_detach),
+	{ 0, 0 }
+};
+
+static driver_t smbios_driver = {
+	"smbios",
+	smbios_methods,
+	sizeof(struct smbios_softc),
+};
+
+DRIVER_MODULE(smbios, nexus, smbios_driver, smbios_devclass, smbios_modevent, 0);
+MODULE_VERSION(smbios, 1);
+
+static int
+smbios_cksum (struct smbios_eps *e)
+{
+	u_int8_t *ptr;
+	u_int8_t cksum;
+	int i;
+
+	ptr = (u_int8_t *)e;
+	cksum = 0;
+	for (i = 0; i < e->Length; i++) {
+		cksum += ptr[i];
+	}
+
+	return (cksum);
+}
diff --git a/sys/x86/bios/vpd.c b/sys/x86/bios/vpd.c
new file mode 100644
index 0000000..246b76d
--- /dev/null
+++ b/sys/x86/bios/vpd.c
@@ -0,0 +1,297 @@
+/*-
+ * Copyright (c) 2003 Matthew N. Dodd <winter@jurai.net>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * VPD decoder for IBM systems (Thinkpads)
+ * http://www-1.ibm.com/support/docview.wss?uid=psg1MIGR-45120
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/sysctl.h>
+
+#include <sys/module.h>
+#include <sys/bus.h>
+
+#include <machine/bus.h>
+#include <machine/resource.h>
+#include <sys/rman.h>
+
+#include <vm/vm.h>
+#include <vm/vm_param.h>
+#include <vm/pmap.h>
+#include <machine/md_var.h>
+#include <machine/pc/bios.h>
+
+/*
+ * Vital Product Data
+ */
+struct vpd {
+	u_int16_t	Header;			/* 0x55AA */
+	u_int8_t	Signature[3];		/* Always 'VPD' */
+	u_int8_t	Length;			/* Sructure Length */
+
+	u_int8_t	Reserved[7];		/* Reserved */
+
+	u_int8_t	BuildID[9];		/* BIOS Build ID */
+	u_int8_t	BoxSerial[7];		/* Box Serial Number */
+	u_int8_t	PlanarSerial[11];	/* Motherboard Serial Number */
+	u_int8_t	MachType[7];		/* Machine Type/Model */
+	u_int8_t	Checksum;		/* Checksum */
+} __packed;
+
+struct vpd_softc {
+	device_t		dev;
+	struct resource *	res;
+	int			rid;
+
+	struct vpd *		vpd;
+
+	struct sysctl_ctx_list  ctx;
+
+	char		BuildID[10];
+	char		BoxSerial[8];
+	char		PlanarSerial[12];
+	char		MachineType[5];
+	char		MachineModel[4];
+};
+
+#define	VPD_START	0xf0000
+#define	VPD_STEP	0x10
+#define	VPD_OFF		2
+#define	VPD_LEN		3
+#define	VPD_SIG		"VPD"
+
+#define	RES2VPD(res)	((struct vpd *)rman_get_virtual(res))
+#define	ADDR2VPD(addr)	((struct vpd *)BIOS_PADDRTOVADDR(addr))
+
+static devclass_t vpd_devclass;
+
+static void	vpd_identify	(driver_t *, device_t);
+static int	vpd_probe	(device_t);
+static int	vpd_attach	(device_t);
+static int	vpd_detach	(device_t);
+static int	vpd_modevent	(module_t, int, void *);
+
+static int	vpd_cksum	(struct vpd *);
+
+SYSCTL_NODE(_hw, OID_AUTO, vpd, CTLFLAG_RD, NULL, NULL);
+SYSCTL_NODE(_hw_vpd, OID_AUTO, machine, CTLFLAG_RD, NULL, NULL);
+SYSCTL_NODE(_hw_vpd_machine, OID_AUTO, type, CTLFLAG_RD, NULL, NULL);
+SYSCTL_NODE(_hw_vpd_machine, OID_AUTO, model, CTLFLAG_RD, NULL, NULL);
+SYSCTL_NODE(_hw_vpd, OID_AUTO, build_id, CTLFLAG_RD, NULL, NULL);
+SYSCTL_NODE(_hw_vpd, OID_AUTO, serial, CTLFLAG_RD, NULL, NULL);
+SYSCTL_NODE(_hw_vpd_serial, OID_AUTO, box, CTLFLAG_RD, NULL, NULL);
+SYSCTL_NODE(_hw_vpd_serial, OID_AUTO, planar, CTLFLAG_RD, NULL, NULL);
+
+static void
+vpd_identify (driver_t *driver, device_t parent)
+{
+	device_t child;
+	u_int32_t addr;
+	int length;
+	int rid;
+
+	if (!device_is_alive(parent))
+		return;
+
+	addr = bios_sigsearch(VPD_START, VPD_SIG, VPD_LEN, VPD_STEP, VPD_OFF);
+	if (addr != 0) {
+		rid = 0;
+		length = ADDR2VPD(addr)->Length;
+
+		child = BUS_ADD_CHILD(parent, 5, "vpd", -1);
+		device_set_driver(child, driver);
+		bus_set_resource(child, SYS_RES_MEMORY, rid, addr, length);
+		device_set_desc(child, "Vital Product Data Area");
+	}
+		
+	return;
+}
+
+static int
+vpd_probe (device_t dev)
+{
+	struct resource *res;
+	int rid;
+	int error;
+
+	error = 0;
+	rid = 0;
+	res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
+	if (res == NULL) {
+		device_printf(dev, "Unable to allocate memory resource.\n");
+		error = ENOMEM;
+		goto bad;
+	}
+
+	if (vpd_cksum(RES2VPD(res)))
+		device_printf(dev, "VPD checksum failed.  BIOS update may be required.\n");
+
+bad:
+	if (res)
+		bus_release_resource(dev, SYS_RES_MEMORY, rid, res);
+	return (error);
+}
+
+static int
+vpd_attach (device_t dev)
+{
+	struct vpd_softc *sc;
+	char unit[4];
+	int error;
+
+	sc = device_get_softc(dev);
+	error = 0;
+
+	sc->dev = dev;
+	sc->rid = 0;
+	sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid,
+		RF_ACTIVE);
+	if (sc->res == NULL) {
+		device_printf(dev, "Unable to allocate memory resource.\n");
+		error = ENOMEM;
+		goto bad;
+	}
+	sc->vpd = RES2VPD(sc->res);
+
+	snprintf(unit, sizeof(unit), "%d", device_get_unit(sc->dev));
+	snprintf(sc->MachineType, 5, "%.4s", sc->vpd->MachType);
+	snprintf(sc->MachineModel, 4, "%.3s", sc->vpd->MachType+4);
+	snprintf(sc->BuildID, 10, "%.9s", sc->vpd->BuildID);
+	snprintf(sc->BoxSerial, 8, "%.7s", sc->vpd->BoxSerial);
+	snprintf(sc->PlanarSerial, 12, "%.11s", sc->vpd->PlanarSerial);
+
+	sysctl_ctx_init(&sc->ctx);
+	SYSCTL_ADD_STRING(&sc->ctx,
+		SYSCTL_STATIC_CHILDREN(_hw_vpd_machine_type), OID_AUTO,
+		unit, CTLFLAG_RD|CTLFLAG_DYN, sc->MachineType, 0, NULL);
+	SYSCTL_ADD_STRING(&sc->ctx,
+		SYSCTL_STATIC_CHILDREN(_hw_vpd_machine_model), OID_AUTO,
+		unit, CTLFLAG_RD|CTLFLAG_DYN, sc->MachineModel, 0, NULL);
+	SYSCTL_ADD_STRING(&sc->ctx,
+		SYSCTL_STATIC_CHILDREN(_hw_vpd_build_id), OID_AUTO,
+		unit, CTLFLAG_RD|CTLFLAG_DYN, sc->BuildID, 0, NULL);
+	SYSCTL_ADD_STRING(&sc->ctx,
+		SYSCTL_STATIC_CHILDREN(_hw_vpd_serial_box), OID_AUTO,
+		unit, CTLFLAG_RD|CTLFLAG_DYN, sc->BoxSerial, 0, NULL);
+	SYSCTL_ADD_STRING(&sc->ctx,
+		SYSCTL_STATIC_CHILDREN(_hw_vpd_serial_planar), OID_AUTO,
+		unit, CTLFLAG_RD|CTLFLAG_DYN, sc->PlanarSerial, 0, NULL);
+
+	device_printf(dev, "Machine Type: %.4s, Model: %.3s, Build ID: %.9s\n",
+		sc->MachineType, sc->MachineModel, sc->BuildID);
+	device_printf(dev, "Box Serial: %.7s, Planar Serial: %.11s\n",
+		sc->BoxSerial, sc->PlanarSerial);
+		
+	return (0);
+bad:
+	if (sc->res)
+		bus_release_resource(dev, SYS_RES_MEMORY, sc->rid, sc->res);
+	return (error);
+}
+
+static int
+vpd_detach (device_t dev)
+{
+	struct vpd_softc *sc;
+
+	sc = device_get_softc(dev);
+
+	if (sc->res)
+		bus_release_resource(dev, SYS_RES_MEMORY, sc->rid, sc->res);
+
+	sysctl_ctx_free(&sc->ctx);
+
+	return (0);
+}
+
+static int
+vpd_modevent (mod, what, arg)
+        module_t        mod;
+        int             what;
+        void *          arg;
+{
+	device_t *	devs;
+	int		count;
+	int		i;
+
+	switch (what) {
+	case MOD_LOAD:
+		break;
+	case MOD_UNLOAD:
+		devclass_get_devices(vpd_devclass, &devs, &count);
+		for (i = 0; i < count; i++) {
+			device_delete_child(device_get_parent(devs[i]), devs[i]);
+		}
+		break;
+	default:
+		break;
+	}
+
+	return (0);
+}
+
+static device_method_t vpd_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_identify,      vpd_identify),
+	DEVMETHOD(device_probe,         vpd_probe),
+	DEVMETHOD(device_attach,        vpd_attach),
+	DEVMETHOD(device_detach,        vpd_detach),
+	{ 0, 0 }
+};
+
+static driver_t vpd_driver = {
+	"vpd",
+	vpd_methods,
+	sizeof(struct vpd_softc),
+};
+
+DRIVER_MODULE(vpd, nexus, vpd_driver, vpd_devclass, vpd_modevent, 0);
+MODULE_VERSION(vpd, 1);
+
+/*
+ * Perform a checksum over the VPD structure, starting with
+ * the BuildID.  (Jean Delvare <khali@linux-fr.org>)
+ */
+static int
+vpd_cksum (struct vpd *v)
+{
+	u_int8_t *ptr;
+	u_int8_t cksum;
+	int i;
+
+	ptr = (u_int8_t *)v;
+	cksum = 0;
+	for (i = offsetof(struct vpd, BuildID); i < v->Length ; i++)
+		cksum += ptr[i];
+	return (cksum);
+}
diff --git a/sys/x86/cpufreq/est.c b/sys/x86/cpufreq/est.c
new file mode 100644
index 0000000..6a7b514
--- /dev/null
+++ b/sys/x86/cpufreq/est.c
@@ -0,0 +1,1401 @@
+/*-
+ * Copyright (c) 2004 Colin Percival
+ * Copyright (c) 2005 Nate Lawson
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted providing that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR 
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <sys/smp.h>
+#include <sys/systm.h>
+
+#include "cpufreq_if.h"
+#include <machine/clock.h>
+#include <machine/cputypes.h>
+#include <machine/md_var.h>
+#include <machine/specialreg.h>
+
+#include <contrib/dev/acpica/include/acpi.h>
+
+#include <dev/acpica/acpivar.h>
+#include "acpi_if.h"
+
+/* Status/control registers (from the IA-32 System Programming Guide). */
+#define MSR_PERF_STATUS		0x198
+#define MSR_PERF_CTL		0x199
+
+/* Register and bit for enabling SpeedStep. */
+#define MSR_MISC_ENABLE		0x1a0
+#define MSR_SS_ENABLE		(1<<16)
+
+/* Frequency and MSR control values. */
+typedef struct {
+	uint16_t	freq;
+	uint16_t	volts;
+	uint16_t	id16;
+	int		power;
+} freq_info;
+
+/* Identifying characteristics of a processor and supported frequencies. */
+typedef struct {
+	const u_int	vendor_id;
+	uint32_t	id32;
+	freq_info	*freqtab;
+} cpu_info;
+
+struct est_softc {
+	device_t	dev;
+	int		acpi_settings;
+	int		msr_settings;
+	freq_info	*freq_list;
+};
+
+/* Convert MHz and mV into IDs for passing to the MSR. */
+#define ID16(MHz, mV, bus_clk)				\
+	(((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4))
+#define ID32(MHz_hi, mV_hi, MHz_lo, mV_lo, bus_clk)	\
+	((ID16(MHz_lo, mV_lo, bus_clk) << 16) | (ID16(MHz_hi, mV_hi, bus_clk)))
+
+/* Format for storing IDs in our table. */
+#define FREQ_INFO_PWR(MHz, mV, bus_clk, mW)		\
+	{ MHz, mV, ID16(MHz, mV, bus_clk), mW }
+#define FREQ_INFO(MHz, mV, bus_clk)			\
+	FREQ_INFO_PWR(MHz, mV, bus_clk, CPUFREQ_VAL_UNKNOWN)
+#define INTEL(tab, zhi, vhi, zlo, vlo, bus_clk)		\
+	{ CPU_VENDOR_INTEL, ID32(zhi, vhi, zlo, vlo, bus_clk), tab }
+#define CENTAUR(tab, zhi, vhi, zlo, vlo, bus_clk)	\
+	{ CPU_VENDOR_CENTAUR, ID32(zhi, vhi, zlo, vlo, bus_clk), tab }
+
+static int msr_info_enabled = 0;
+TUNABLE_INT("hw.est.msr_info", &msr_info_enabled);
+static int strict = -1;
+TUNABLE_INT("hw.est.strict", &strict);
+
+/* Default bus clock value for Centrino processors. */
+#define INTEL_BUS_CLK		100
+
+/* XXX Update this if new CPUs have more settings. */
+#define EST_MAX_SETTINGS	10
+CTASSERT(EST_MAX_SETTINGS <= MAX_SETTINGS);
+
+/* Estimate in microseconds of latency for performing a transition. */
+#define EST_TRANS_LAT		1000
+
+/*
+ * Frequency (MHz) and voltage (mV) settings.  Data from the
+ * Intel Pentium M Processor Datasheet (Order Number 252612), Table 5.
+ *
+ * Dothan processors have multiple VID#s with different settings for
+ * each VID#.  Since we can't uniquely identify this info
+ * without undisclosed methods from Intel, we can't support newer
+ * processors with this table method.  If ACPI Px states are supported,
+ * we get info from them.
+ */
+static freq_info PM17_130[] = {
+	/* 130nm 1.70GHz Pentium M */
+	FREQ_INFO(1700, 1484, INTEL_BUS_CLK),
+	FREQ_INFO(1400, 1308, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1228, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1004, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  956, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM16_130[] = {
+	/* 130nm 1.60GHz Pentium M */
+	FREQ_INFO(1600, 1484, INTEL_BUS_CLK),
+	FREQ_INFO(1400, 1420, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1276, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1164, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  956, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM15_130[] = {
+	/* 130nm 1.50GHz Pentium M */
+	FREQ_INFO(1500, 1484, INTEL_BUS_CLK),
+	FREQ_INFO(1400, 1452, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1356, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1228, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1116, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  956, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM14_130[] = {
+	/* 130nm 1.40GHz Pentium M */
+	FREQ_INFO(1400, 1484, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1436, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1308, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1180, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  956, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM13_130[] = {
+	/* 130nm 1.30GHz Pentium M */
+	FREQ_INFO(1300, 1388, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1356, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1292, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1260, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  956, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM13_LV_130[] = {
+	/* 130nm 1.30GHz Low Voltage Pentium M */
+	FREQ_INFO(1300, 1180, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
+	FREQ_INFO(1100, 1100, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1020, INTEL_BUS_CLK),
+	FREQ_INFO( 900, 1004, INTEL_BUS_CLK),
+	FREQ_INFO( 800,  988, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  956, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM12_LV_130[] = {
+	/* 130 nm 1.20GHz Low Voltage Pentium M */
+	FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
+	FREQ_INFO(1100, 1164, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
+	FREQ_INFO( 900, 1020, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1004, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  956, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM11_LV_130[] = {
+	/* 130 nm 1.10GHz Low Voltage Pentium M */
+	FREQ_INFO(1100, 1180, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1164, INTEL_BUS_CLK),
+	FREQ_INFO( 900, 1100, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  956, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM11_ULV_130[] = {
+	/* 130 nm 1.10GHz Ultra Low Voltage Pentium M */
+	FREQ_INFO(1100, 1004, INTEL_BUS_CLK),
+	FREQ_INFO(1000,  988, INTEL_BUS_CLK),
+	FREQ_INFO( 900,  972, INTEL_BUS_CLK),
+	FREQ_INFO( 800,  956, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  844, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM10_ULV_130[] = {
+	/* 130 nm 1.00GHz Ultra Low Voltage Pentium M */
+	FREQ_INFO(1000, 1004, INTEL_BUS_CLK),
+	FREQ_INFO( 900,  988, INTEL_BUS_CLK),
+	FREQ_INFO( 800,  972, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  844, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+
+/*
+ * Data from "Intel Pentium M Processor on 90nm Process with
+ * 2-MB L2 Cache Datasheet", Order Number 302189, Table 5.
+ */
+static freq_info PM_765A_90[] = {
+	/* 90 nm 2.10GHz Pentium M, VID #A */
+	FREQ_INFO(2100, 1340, INTEL_BUS_CLK),
+	FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
+	FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
+	FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  988, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_765B_90[] = {
+	/* 90 nm 2.10GHz Pentium M, VID #B */
+	FREQ_INFO(2100, 1324, INTEL_BUS_CLK),
+	FREQ_INFO(1800, 1260, INTEL_BUS_CLK),
+	FREQ_INFO(1600, 1212, INTEL_BUS_CLK),
+	FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  988, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_765C_90[] = {
+	/* 90 nm 2.10GHz Pentium M, VID #C */
+	FREQ_INFO(2100, 1308, INTEL_BUS_CLK),
+	FREQ_INFO(1800, 1244, INTEL_BUS_CLK),
+	FREQ_INFO(1600, 1212, INTEL_BUS_CLK),
+	FREQ_INFO(1400, 1164, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1116, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  988, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_765E_90[] = {
+	/* 90 nm 2.10GHz Pentium M, VID #E */
+	FREQ_INFO(2100, 1356, INTEL_BUS_CLK),
+	FREQ_INFO(1800, 1292, INTEL_BUS_CLK),
+	FREQ_INFO(1600, 1244, INTEL_BUS_CLK),
+	FREQ_INFO(1400, 1196, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  988, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_755A_90[] = {
+	/* 90 nm 2.00GHz Pentium M, VID #A */
+	FREQ_INFO(2000, 1340, INTEL_BUS_CLK),
+	FREQ_INFO(1800, 1292, INTEL_BUS_CLK),
+	FREQ_INFO(1600, 1244, INTEL_BUS_CLK),
+	FREQ_INFO(1400, 1196, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  988, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_755B_90[] = {
+	/* 90 nm 2.00GHz Pentium M, VID #B */
+	FREQ_INFO(2000, 1324, INTEL_BUS_CLK),
+	FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
+	FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
+	FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  988, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_755C_90[] = {
+	/* 90 nm 2.00GHz Pentium M, VID #C */
+	FREQ_INFO(2000, 1308, INTEL_BUS_CLK),
+	FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
+	FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
+	FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  988, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_755D_90[] = {
+	/* 90 nm 2.00GHz Pentium M, VID #D */
+	FREQ_INFO(2000, 1276, INTEL_BUS_CLK),
+	FREQ_INFO(1800, 1244, INTEL_BUS_CLK),
+	FREQ_INFO(1600, 1196, INTEL_BUS_CLK),
+	FREQ_INFO(1400, 1164, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1116, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  988, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_745A_90[] = {
+	/* 90 nm 1.80GHz Pentium M, VID #A */
+	FREQ_INFO(1800, 1340, INTEL_BUS_CLK),
+	FREQ_INFO(1600, 1292, INTEL_BUS_CLK),
+	FREQ_INFO(1400, 1228, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  988, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_745B_90[] = {
+	/* 90 nm 1.80GHz Pentium M, VID #B */
+	FREQ_INFO(1800, 1324, INTEL_BUS_CLK),
+	FREQ_INFO(1600, 1276, INTEL_BUS_CLK),
+	FREQ_INFO(1400, 1212, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  988, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_745C_90[] = {
+	/* 90 nm 1.80GHz Pentium M, VID #C */
+	FREQ_INFO(1800, 1308, INTEL_BUS_CLK),
+	FREQ_INFO(1600, 1260, INTEL_BUS_CLK),
+	FREQ_INFO(1400, 1212, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  988, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_745D_90[] = {
+	/* 90 nm 1.80GHz Pentium M, VID #D */
+	FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
+	FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
+	FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  988, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_735A_90[] = {
+	/* 90 nm 1.70GHz Pentium M, VID #A */
+	FREQ_INFO(1700, 1340, INTEL_BUS_CLK),
+	FREQ_INFO(1400, 1244, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  988, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_735B_90[] = {
+	/* 90 nm 1.70GHz Pentium M, VID #B */
+	FREQ_INFO(1700, 1324, INTEL_BUS_CLK),
+	FREQ_INFO(1400, 1244, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  988, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_735C_90[] = {
+	/* 90 nm 1.70GHz Pentium M, VID #C */
+	FREQ_INFO(1700, 1308, INTEL_BUS_CLK),
+	FREQ_INFO(1400, 1228, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  988, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_735D_90[] = {
+	/* 90 nm 1.70GHz Pentium M, VID #D */
+	FREQ_INFO(1700, 1276, INTEL_BUS_CLK),
+	FREQ_INFO(1400, 1212, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  988, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_725A_90[] = {
+	/* 90 nm 1.60GHz Pentium M, VID #A */
+	FREQ_INFO(1600, 1340, INTEL_BUS_CLK),
+	FREQ_INFO(1400, 1276, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1212, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1132, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  988, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_725B_90[] = {
+	/* 90 nm 1.60GHz Pentium M, VID #B */
+	FREQ_INFO(1600, 1324, INTEL_BUS_CLK),
+	FREQ_INFO(1400, 1260, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1196, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1132, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  988, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_725C_90[] = {
+	/* 90 nm 1.60GHz Pentium M, VID #C */
+	FREQ_INFO(1600, 1308, INTEL_BUS_CLK),
+	FREQ_INFO(1400, 1244, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  988, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_725D_90[] = {
+	/* 90 nm 1.60GHz Pentium M, VID #D */
+	FREQ_INFO(1600, 1276, INTEL_BUS_CLK),
+	FREQ_INFO(1400, 1228, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  988, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_715A_90[] = {
+	/* 90 nm 1.50GHz Pentium M, VID #A */
+	FREQ_INFO(1500, 1340, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1228, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1148, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  988, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_715B_90[] = {
+	/* 90 nm 1.50GHz Pentium M, VID #B */
+	FREQ_INFO(1500, 1324, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1212, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1148, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  988, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_715C_90[] = {
+	/* 90 nm 1.50GHz Pentium M, VID #C */
+	FREQ_INFO(1500, 1308, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1212, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1132, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  988, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_715D_90[] = {
+	/* 90 nm 1.50GHz Pentium M, VID #D */
+	FREQ_INFO(1500, 1276, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  988, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_778_90[] = {
+	/* 90 nm 1.60GHz Low Voltage Pentium M */
+	FREQ_INFO(1600, 1116, INTEL_BUS_CLK),
+	FREQ_INFO(1500, 1116, INTEL_BUS_CLK),
+	FREQ_INFO(1400, 1100, INTEL_BUS_CLK),
+	FREQ_INFO(1300, 1084, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1068, INTEL_BUS_CLK),
+	FREQ_INFO(1100, 1052, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1052, INTEL_BUS_CLK),
+	FREQ_INFO( 900, 1036, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  988, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_758_90[] = {
+	/* 90 nm 1.50GHz Low Voltage Pentium M */
+	FREQ_INFO(1500, 1116, INTEL_BUS_CLK),
+	FREQ_INFO(1400, 1116, INTEL_BUS_CLK),
+	FREQ_INFO(1300, 1100, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1084, INTEL_BUS_CLK),
+	FREQ_INFO(1100, 1068, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1052, INTEL_BUS_CLK),
+	FREQ_INFO( 900, 1036, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  988, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_738_90[] = {
+	/* 90 nm 1.40GHz Low Voltage Pentium M */
+	FREQ_INFO(1400, 1116, INTEL_BUS_CLK),
+	FREQ_INFO(1300, 1116, INTEL_BUS_CLK),
+	FREQ_INFO(1200, 1100, INTEL_BUS_CLK),
+	FREQ_INFO(1100, 1068, INTEL_BUS_CLK),
+	FREQ_INFO(1000, 1052, INTEL_BUS_CLK),
+	FREQ_INFO( 900, 1036, INTEL_BUS_CLK),
+	FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  988, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_773G_90[] = {
+	/* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #G */
+	FREQ_INFO(1300,  956, INTEL_BUS_CLK),
+	FREQ_INFO(1200,  940, INTEL_BUS_CLK),
+	FREQ_INFO(1100,  924, INTEL_BUS_CLK),
+	FREQ_INFO(1000,  908, INTEL_BUS_CLK),
+	FREQ_INFO( 900,  876, INTEL_BUS_CLK),
+	FREQ_INFO( 800,  860, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  812, INTEL_BUS_CLK),
+};
+static freq_info PM_773H_90[] = {
+	/* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #H */
+	FREQ_INFO(1300,  940, INTEL_BUS_CLK),
+	FREQ_INFO(1200,  924, INTEL_BUS_CLK),
+	FREQ_INFO(1100,  908, INTEL_BUS_CLK),
+	FREQ_INFO(1000,  892, INTEL_BUS_CLK),
+	FREQ_INFO( 900,  876, INTEL_BUS_CLK),
+	FREQ_INFO( 800,  860, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  812, INTEL_BUS_CLK),
+};
+static freq_info PM_773I_90[] = {
+	/* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #I */
+	FREQ_INFO(1300,  924, INTEL_BUS_CLK),
+	FREQ_INFO(1200,  908, INTEL_BUS_CLK),
+	FREQ_INFO(1100,  892, INTEL_BUS_CLK),
+	FREQ_INFO(1000,  876, INTEL_BUS_CLK),
+	FREQ_INFO( 900,  860, INTEL_BUS_CLK),
+	FREQ_INFO( 800,  844, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  812, INTEL_BUS_CLK),
+};
+static freq_info PM_773J_90[] = {
+	/* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #J */
+	FREQ_INFO(1300,  908, INTEL_BUS_CLK),
+	FREQ_INFO(1200,  908, INTEL_BUS_CLK),
+	FREQ_INFO(1100,  892, INTEL_BUS_CLK),
+	FREQ_INFO(1000,  876, INTEL_BUS_CLK),
+	FREQ_INFO( 900,  860, INTEL_BUS_CLK),
+	FREQ_INFO( 800,  844, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  812, INTEL_BUS_CLK),
+};
+static freq_info PM_773K_90[] = {
+	/* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #K */
+	FREQ_INFO(1300,  892, INTEL_BUS_CLK),
+	FREQ_INFO(1200,  892, INTEL_BUS_CLK),
+	FREQ_INFO(1100,  876, INTEL_BUS_CLK),
+	FREQ_INFO(1000,  860, INTEL_BUS_CLK),
+	FREQ_INFO( 900,  860, INTEL_BUS_CLK),
+	FREQ_INFO( 800,  844, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  812, INTEL_BUS_CLK),
+};
+static freq_info PM_773L_90[] = {
+	/* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #L */
+	FREQ_INFO(1300,  876, INTEL_BUS_CLK),
+	FREQ_INFO(1200,  876, INTEL_BUS_CLK),
+	FREQ_INFO(1100,  860, INTEL_BUS_CLK),
+	FREQ_INFO(1000,  860, INTEL_BUS_CLK),
+	FREQ_INFO( 900,  844, INTEL_BUS_CLK),
+	FREQ_INFO( 800,  844, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  812, INTEL_BUS_CLK),
+};
+static freq_info PM_753G_90[] = {
+	/* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #G */
+	FREQ_INFO(1200,  956, INTEL_BUS_CLK),
+	FREQ_INFO(1100,  940, INTEL_BUS_CLK),
+	FREQ_INFO(1000,  908, INTEL_BUS_CLK),
+	FREQ_INFO( 900,  892, INTEL_BUS_CLK),
+	FREQ_INFO( 800,  860, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  812, INTEL_BUS_CLK),
+};
+static freq_info PM_753H_90[] = {
+	/* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #H */
+	FREQ_INFO(1200,  940, INTEL_BUS_CLK),
+	FREQ_INFO(1100,  924, INTEL_BUS_CLK),
+	FREQ_INFO(1000,  908, INTEL_BUS_CLK),
+	FREQ_INFO( 900,  876, INTEL_BUS_CLK),
+	FREQ_INFO( 800,  860, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  812, INTEL_BUS_CLK),
+};
+static freq_info PM_753I_90[] = {
+	/* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #I */
+	FREQ_INFO(1200,  924, INTEL_BUS_CLK),
+	FREQ_INFO(1100,  908, INTEL_BUS_CLK),
+	FREQ_INFO(1000,  892, INTEL_BUS_CLK),
+	FREQ_INFO( 900,  876, INTEL_BUS_CLK),
+	FREQ_INFO( 800,  860, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  812, INTEL_BUS_CLK),
+};
+static freq_info PM_753J_90[] = {
+	/* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #J */
+	FREQ_INFO(1200,  908, INTEL_BUS_CLK),
+	FREQ_INFO(1100,  892, INTEL_BUS_CLK),
+	FREQ_INFO(1000,  876, INTEL_BUS_CLK),
+	FREQ_INFO( 900,  860, INTEL_BUS_CLK),
+	FREQ_INFO( 800,  844, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  812, INTEL_BUS_CLK),
+};
+static freq_info PM_753K_90[] = {
+	/* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #K */
+	FREQ_INFO(1200,  892, INTEL_BUS_CLK),
+	FREQ_INFO(1100,  892, INTEL_BUS_CLK),
+	FREQ_INFO(1000,  876, INTEL_BUS_CLK),
+	FREQ_INFO( 900,  860, INTEL_BUS_CLK),
+	FREQ_INFO( 800,  844, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  812, INTEL_BUS_CLK),
+};
+static freq_info PM_753L_90[] = {
+	/* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #L */
+	FREQ_INFO(1200,  876, INTEL_BUS_CLK),
+	FREQ_INFO(1100,  876, INTEL_BUS_CLK),
+	FREQ_INFO(1000,  860, INTEL_BUS_CLK),
+	FREQ_INFO( 900,  844, INTEL_BUS_CLK),
+	FREQ_INFO( 800,  844, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  812, INTEL_BUS_CLK),
+};
+
+static freq_info PM_733JG_90[] = {
+	/* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #G */
+	FREQ_INFO(1100,  956, INTEL_BUS_CLK),
+	FREQ_INFO(1000,  940, INTEL_BUS_CLK),
+	FREQ_INFO( 900,  908, INTEL_BUS_CLK),
+	FREQ_INFO( 800,  876, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  812, INTEL_BUS_CLK),
+};
+static freq_info PM_733JH_90[] = {
+	/* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #H */
+	FREQ_INFO(1100,  940, INTEL_BUS_CLK),
+	FREQ_INFO(1000,  924, INTEL_BUS_CLK),
+	FREQ_INFO( 900,  892, INTEL_BUS_CLK),
+	FREQ_INFO( 800,  876, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  812, INTEL_BUS_CLK),
+};
+static freq_info PM_733JI_90[] = {
+	/* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #I */
+	FREQ_INFO(1100,  924, INTEL_BUS_CLK),
+	FREQ_INFO(1000,  908, INTEL_BUS_CLK),
+	FREQ_INFO( 900,  892, INTEL_BUS_CLK),
+	FREQ_INFO( 800,  860, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  812, INTEL_BUS_CLK),
+};
+static freq_info PM_733JJ_90[] = {
+	/* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #J */
+	FREQ_INFO(1100,  908, INTEL_BUS_CLK),
+	FREQ_INFO(1000,  892, INTEL_BUS_CLK),
+	FREQ_INFO( 900,  876, INTEL_BUS_CLK),
+	FREQ_INFO( 800,  860, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  812, INTEL_BUS_CLK),
+};
+static freq_info PM_733JK_90[] = {
+	/* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #K */
+	FREQ_INFO(1100,  892, INTEL_BUS_CLK),
+	FREQ_INFO(1000,  876, INTEL_BUS_CLK),
+	FREQ_INFO( 900,  860, INTEL_BUS_CLK),
+	FREQ_INFO( 800,  844, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  812, INTEL_BUS_CLK),
+};
+static freq_info PM_733JL_90[] = {
+	/* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #L */
+	FREQ_INFO(1100,  876, INTEL_BUS_CLK),
+	FREQ_INFO(1000,  876, INTEL_BUS_CLK),
+	FREQ_INFO( 900,  860, INTEL_BUS_CLK),
+	FREQ_INFO( 800,  844, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  812, INTEL_BUS_CLK),
+};
+static freq_info PM_733_90[] = {
+	/* 90 nm 1.10GHz Ultra Low Voltage Pentium M */
+	FREQ_INFO(1100,  940, INTEL_BUS_CLK),
+	FREQ_INFO(1000,  924, INTEL_BUS_CLK),
+	FREQ_INFO( 900,  892, INTEL_BUS_CLK),
+	FREQ_INFO( 800,  876, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  812, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+static freq_info PM_723_90[] = {
+	/* 90 nm 1.00GHz Ultra Low Voltage Pentium M */
+	FREQ_INFO(1000,  940, INTEL_BUS_CLK),
+	FREQ_INFO( 900,  908, INTEL_BUS_CLK),
+	FREQ_INFO( 800,  876, INTEL_BUS_CLK),
+	FREQ_INFO( 600,  812, INTEL_BUS_CLK),
+	FREQ_INFO(   0,    0, 1),
+};
+
+/*
+ * VIA C7-M 500 MHz FSB, 400 MHz FSB, and ULV variants.
+ * Data from the "VIA C7-M Processor BIOS Writer's Guide (v2.17)" datasheet.
+ */
+static freq_info C7M_795[] = {
+	/* 2.00GHz Centaur C7-M 533 Mhz FSB */
+	FREQ_INFO_PWR(2000, 1148, 133, 20000),
+	FREQ_INFO_PWR(1867, 1132, 133, 18000),
+	FREQ_INFO_PWR(1600, 1100, 133, 15000),
+	FREQ_INFO_PWR(1467, 1052, 133, 13000),
+	FREQ_INFO_PWR(1200, 1004, 133, 10000),
+	FREQ_INFO_PWR( 800,  844, 133,  7000),
+	FREQ_INFO_PWR( 667,  844, 133,  6000),
+	FREQ_INFO_PWR( 533,  844, 133,  5000),
+	FREQ_INFO(0, 0, 1),
+};
+static freq_info C7M_785[] = {
+	/* 1.80GHz Centaur C7-M 533 Mhz FSB */
+	FREQ_INFO_PWR(1867, 1148, 133, 18000),
+	FREQ_INFO_PWR(1600, 1100, 133, 15000),
+	FREQ_INFO_PWR(1467, 1052, 133, 13000),
+	FREQ_INFO_PWR(1200, 1004, 133, 10000),
+	FREQ_INFO_PWR( 800,  844, 133,  7000),
+	FREQ_INFO_PWR( 667,  844, 133,  6000),
+	FREQ_INFO_PWR( 533,  844, 133,  5000),
+	FREQ_INFO(0, 0, 1),
+};
+static freq_info C7M_765[] = {
+	/* 1.60GHz Centaur C7-M 533 Mhz FSB */
+	FREQ_INFO_PWR(1600, 1084, 133, 15000),
+	FREQ_INFO_PWR(1467, 1052, 133, 13000),
+	FREQ_INFO_PWR(1200, 1004, 133, 10000),
+	FREQ_INFO_PWR( 800,  844, 133,  7000),
+	FREQ_INFO_PWR( 667,  844, 133,  6000),
+	FREQ_INFO_PWR( 533,  844, 133,  5000),
+	FREQ_INFO(0, 0, 1),
+};
+
+static freq_info C7M_794[] = {
+	/* 2.00GHz Centaur C7-M 400 Mhz FSB */
+	FREQ_INFO_PWR(2000, 1148, 100, 20000),
+	FREQ_INFO_PWR(1800, 1132, 100, 18000),
+	FREQ_INFO_PWR(1600, 1100, 100, 15000),
+	FREQ_INFO_PWR(1400, 1052, 100, 13000),
+	FREQ_INFO_PWR(1000, 1004, 100, 10000),
+	FREQ_INFO_PWR( 800,  844, 100,  7000),
+	FREQ_INFO_PWR( 600,  844, 100,  6000),
+	FREQ_INFO_PWR( 400,  844, 100,  5000),
+	FREQ_INFO(0, 0, 1),
+};
+static freq_info C7M_784[] = {
+	/* 1.80GHz Centaur C7-M 400 Mhz FSB */
+	FREQ_INFO_PWR(1800, 1148, 100, 18000),
+	FREQ_INFO_PWR(1600, 1100, 100, 15000),
+	FREQ_INFO_PWR(1400, 1052, 100, 13000),
+	FREQ_INFO_PWR(1000, 1004, 100, 10000),
+	FREQ_INFO_PWR( 800,  844, 100,  7000),
+	FREQ_INFO_PWR( 600,  844, 100,  6000),
+	FREQ_INFO_PWR( 400,  844, 100,  5000),
+	FREQ_INFO(0, 0, 1),
+};
+static freq_info C7M_764[] = {
+	/* 1.60GHz Centaur C7-M 400 Mhz FSB */
+	FREQ_INFO_PWR(1600, 1084, 100, 15000),
+	FREQ_INFO_PWR(1400, 1052, 100, 13000),
+	FREQ_INFO_PWR(1000, 1004, 100, 10000),
+	FREQ_INFO_PWR( 800,  844, 100,  7000),
+	FREQ_INFO_PWR( 600,  844, 100,  6000),
+	FREQ_INFO_PWR( 400,  844, 100,  5000),
+	FREQ_INFO(0, 0, 1),
+};
+static freq_info C7M_754[] = {
+	/* 1.50GHz Centaur C7-M 400 Mhz FSB */
+	FREQ_INFO_PWR(1500, 1004, 100, 12000),
+	FREQ_INFO_PWR(1400,  988, 100, 11000),
+	FREQ_INFO_PWR(1000,  940, 100,  9000),
+	FREQ_INFO_PWR( 800,  844, 100,  7000),
+	FREQ_INFO_PWR( 600,  844, 100,  6000),
+	FREQ_INFO_PWR( 400,  844, 100,  5000),
+	FREQ_INFO(0, 0, 1),
+};
+static freq_info C7M_771[] = {
+	/* 1.20GHz Centaur C7-M 400 Mhz FSB */
+	FREQ_INFO_PWR(1200,  860, 100,  7000),
+	FREQ_INFO_PWR(1000,  860, 100,  6000),
+	FREQ_INFO_PWR( 800,  844, 100,  5500),
+	FREQ_INFO_PWR( 600,  844, 100,  5000),
+	FREQ_INFO_PWR( 400,  844, 100,  4000),
+	FREQ_INFO(0, 0, 1),
+};
+
+static freq_info C7M_775_ULV[] = {
+	/* 1.50GHz Centaur C7-M ULV */
+	FREQ_INFO_PWR(1500,  956, 100,  7500),
+	FREQ_INFO_PWR(1400,  940, 100,  6000),
+	FREQ_INFO_PWR(1000,  860, 100,  5000),
+	FREQ_INFO_PWR( 800,  828, 100,  2800),
+	FREQ_INFO_PWR( 600,  796, 100,  2500),
+	FREQ_INFO_PWR( 400,  796, 100,  2000),
+	FREQ_INFO(0, 0, 1),
+};
+static freq_info C7M_772_ULV[] = {
+	/* 1.20GHz Centaur C7-M ULV */
+	FREQ_INFO_PWR(1200,  844, 100,  5000),
+	FREQ_INFO_PWR(1000,  844, 100,  4000),
+	FREQ_INFO_PWR( 800,  828, 100,  2800),
+	FREQ_INFO_PWR( 600,  796, 100,  2500),
+	FREQ_INFO_PWR( 400,  796, 100,  2000),
+	FREQ_INFO(0, 0, 1),
+};
+static freq_info C7M_779_ULV[] = {
+	/* 1.00GHz Centaur C7-M ULV */
+	FREQ_INFO_PWR(1000,  796, 100,  3500),
+	FREQ_INFO_PWR( 800,  796, 100,  2800),
+	FREQ_INFO_PWR( 600,  796, 100,  2500),
+	FREQ_INFO_PWR( 400,  796, 100,  2000),
+	FREQ_INFO(0, 0, 1),
+};
+static freq_info C7M_770_ULV[] = {
+	/* 1.00GHz Centaur C7-M ULV */
+	FREQ_INFO_PWR(1000,  844, 100,  5000),
+	FREQ_INFO_PWR( 800,  796, 100,  2800),
+	FREQ_INFO_PWR( 600,  796, 100,  2500),
+	FREQ_INFO_PWR( 400,  796, 100,  2000),
+	FREQ_INFO(0, 0, 1),
+};
+
+static cpu_info ESTprocs[] = {
+	INTEL(PM17_130,		1700, 1484, 600, 956, INTEL_BUS_CLK),
+	INTEL(PM16_130,		1600, 1484, 600, 956, INTEL_BUS_CLK),
+	INTEL(PM15_130,		1500, 1484, 600, 956, INTEL_BUS_CLK),
+	INTEL(PM14_130,		1400, 1484, 600, 956, INTEL_BUS_CLK),
+	INTEL(PM13_130,		1300, 1388, 600, 956, INTEL_BUS_CLK),
+	INTEL(PM13_LV_130,	1300, 1180, 600, 956, INTEL_BUS_CLK),
+	INTEL(PM12_LV_130,	1200, 1180, 600, 956, INTEL_BUS_CLK),
+	INTEL(PM11_LV_130,	1100, 1180, 600, 956, INTEL_BUS_CLK),
+	INTEL(PM11_ULV_130,	1100, 1004, 600, 844, INTEL_BUS_CLK),
+	INTEL(PM10_ULV_130,	1000, 1004, 600, 844, INTEL_BUS_CLK),
+	INTEL(PM_765A_90,	2100, 1340, 600, 988, INTEL_BUS_CLK),
+	INTEL(PM_765B_90,	2100, 1324, 600, 988, INTEL_BUS_CLK),
+	INTEL(PM_765C_90,	2100, 1308, 600, 988, INTEL_BUS_CLK),
+	INTEL(PM_765E_90,	2100, 1356, 600, 988, INTEL_BUS_CLK),
+	INTEL(PM_755A_90,	2000, 1340, 600, 988, INTEL_BUS_CLK),
+	INTEL(PM_755B_90,	2000, 1324, 600, 988, INTEL_BUS_CLK),
+	INTEL(PM_755C_90,	2000, 1308, 600, 988, INTEL_BUS_CLK),
+	INTEL(PM_755D_90,	2000, 1276, 600, 988, INTEL_BUS_CLK),
+	INTEL(PM_745A_90,	1800, 1340, 600, 988, INTEL_BUS_CLK),
+	INTEL(PM_745B_90,	1800, 1324, 600, 988, INTEL_BUS_CLK),
+	INTEL(PM_745C_90,	1800, 1308, 600, 988, INTEL_BUS_CLK),
+	INTEL(PM_745D_90,	1800, 1276, 600, 988, INTEL_BUS_CLK),
+	INTEL(PM_735A_90,	1700, 1340, 600, 988, INTEL_BUS_CLK),
+	INTEL(PM_735B_90,	1700, 1324, 600, 988, INTEL_BUS_CLK),
+	INTEL(PM_735C_90,	1700, 1308, 600, 988, INTEL_BUS_CLK),
+	INTEL(PM_735D_90,	1700, 1276, 600, 988, INTEL_BUS_CLK),
+	INTEL(PM_725A_90,	1600, 1340, 600, 988, INTEL_BUS_CLK),
+	INTEL(PM_725B_90,	1600, 1324, 600, 988, INTEL_BUS_CLK),
+	INTEL(PM_725C_90,	1600, 1308, 600, 988, INTEL_BUS_CLK),
+	INTEL(PM_725D_90,	1600, 1276, 600, 988, INTEL_BUS_CLK),
+	INTEL(PM_715A_90,	1500, 1340, 600, 988, INTEL_BUS_CLK),
+	INTEL(PM_715B_90,	1500, 1324, 600, 988, INTEL_BUS_CLK),
+	INTEL(PM_715C_90,	1500, 1308, 600, 988, INTEL_BUS_CLK),
+	INTEL(PM_715D_90,	1500, 1276, 600, 988, INTEL_BUS_CLK),
+	INTEL(PM_778_90,	1600, 1116, 600, 988, INTEL_BUS_CLK),
+	INTEL(PM_758_90,	1500, 1116, 600, 988, INTEL_BUS_CLK),
+	INTEL(PM_738_90,	1400, 1116, 600, 988, INTEL_BUS_CLK),
+	INTEL(PM_773G_90,	1300,  956, 600, 812, INTEL_BUS_CLK),
+	INTEL(PM_773H_90,	1300,  940, 600, 812, INTEL_BUS_CLK),
+	INTEL(PM_773I_90,	1300,  924, 600, 812, INTEL_BUS_CLK),
+	INTEL(PM_773J_90,	1300,  908, 600, 812, INTEL_BUS_CLK),
+	INTEL(PM_773K_90,	1300,  892, 600, 812, INTEL_BUS_CLK),
+	INTEL(PM_773L_90,	1300,  876, 600, 812, INTEL_BUS_CLK),
+	INTEL(PM_753G_90,	1200,  956, 600, 812, INTEL_BUS_CLK),
+	INTEL(PM_753H_90,	1200,  940, 600, 812, INTEL_BUS_CLK),
+	INTEL(PM_753I_90,	1200,  924, 600, 812, INTEL_BUS_CLK),
+	INTEL(PM_753J_90,	1200,  908, 600, 812, INTEL_BUS_CLK),
+	INTEL(PM_753K_90,	1200,  892, 600, 812, INTEL_BUS_CLK),
+	INTEL(PM_753L_90,	1200,  876, 600, 812, INTEL_BUS_CLK),
+	INTEL(PM_733JG_90,	1100,  956, 600, 812, INTEL_BUS_CLK),
+	INTEL(PM_733JH_90,	1100,  940, 600, 812, INTEL_BUS_CLK),
+	INTEL(PM_733JI_90,	1100,  924, 600, 812, INTEL_BUS_CLK),
+	INTEL(PM_733JJ_90,	1100,  908, 600, 812, INTEL_BUS_CLK),
+	INTEL(PM_733JK_90,	1100,  892, 600, 812, INTEL_BUS_CLK),
+	INTEL(PM_733JL_90,	1100,  876, 600, 812, INTEL_BUS_CLK),
+	INTEL(PM_733_90,	1100,  940, 600, 812, INTEL_BUS_CLK),
+	INTEL(PM_723_90,	1000,  940, 600, 812, INTEL_BUS_CLK),
+
+	CENTAUR(C7M_795,	2000, 1148, 533, 844, 133),
+	CENTAUR(C7M_794,	2000, 1148, 400, 844, 100),
+	CENTAUR(C7M_785,	1867, 1148, 533, 844, 133),
+	CENTAUR(C7M_784,	1800, 1148, 400, 844, 100),
+	CENTAUR(C7M_765,	1600, 1084, 533, 844, 133),
+	CENTAUR(C7M_764,	1600, 1084, 400, 844, 100),
+	CENTAUR(C7M_754,	1500, 1004, 400, 844, 100),
+	CENTAUR(C7M_775_ULV,	1500,  956, 400, 796, 100),
+	CENTAUR(C7M_771,	1200,  860, 400, 844, 100),
+	CENTAUR(C7M_772_ULV,	1200,  844, 400, 796, 100),
+	CENTAUR(C7M_779_ULV,	1000,  796, 400, 796, 100),
+	CENTAUR(C7M_770_ULV,	1000,  844, 400, 796, 100),
+	{ 0, 0, NULL },
+};
+
+static void	est_identify(driver_t *driver, device_t parent);
+static int	est_features(driver_t *driver, u_int *features);
+static int	est_probe(device_t parent);
+static int	est_attach(device_t parent);
+static int	est_detach(device_t parent);
+static int	est_get_info(device_t dev);
+static int	est_acpi_info(device_t dev, freq_info **freqs);
+static int	est_table_info(device_t dev, uint64_t msr, freq_info **freqs);
+static int	est_msr_info(device_t dev, uint64_t msr, freq_info **freqs);
+static freq_info *est_get_current(freq_info *freq_list);
+static int	est_settings(device_t dev, struct cf_setting *sets, int *count);
+static int	est_set(device_t dev, const struct cf_setting *set);
+static int	est_get(device_t dev, struct cf_setting *set);
+static int	est_type(device_t dev, int *type);
+static int	est_set_id16(device_t dev, uint16_t id16, int need_check);
+static void	est_get_id16(uint16_t *id16_p);
+
+static device_method_t est_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_identify,	est_identify),
+	DEVMETHOD(device_probe,		est_probe),
+	DEVMETHOD(device_attach,	est_attach),
+	DEVMETHOD(device_detach,	est_detach),
+
+	/* cpufreq interface */
+	DEVMETHOD(cpufreq_drv_set,	est_set),
+	DEVMETHOD(cpufreq_drv_get,	est_get),
+	DEVMETHOD(cpufreq_drv_type,	est_type),
+	DEVMETHOD(cpufreq_drv_settings,	est_settings),
+
+	/* ACPI interface */
+	DEVMETHOD(acpi_get_features,	est_features),
+
+	{0, 0}
+};
+
+static driver_t est_driver = {
+	"est",
+	est_methods,
+	sizeof(struct est_softc),
+};
+
+static devclass_t est_devclass;
+DRIVER_MODULE(est, cpu, est_driver, est_devclass, 0, 0);
+
+static int
+est_features(driver_t *driver, u_int *features)
+{
+
+	/* Notify the ACPI CPU that we support direct access to MSRs */
+	*features = ACPI_CAP_PERF_MSRS;
+	return (0);
+}
+
+static void
+est_identify(driver_t *driver, device_t parent)
+{
+	device_t child;
+
+	/* Make sure we're not being doubly invoked. */
+	if (device_find_child(parent, "est", -1) != NULL)
+		return;
+
+	/* Check that CPUID is supported and the vendor is Intel.*/
+	if (cpu_high == 0 || (cpu_vendor_id != CPU_VENDOR_INTEL &&
+	    cpu_vendor_id != CPU_VENDOR_CENTAUR))
+		return;
+
+	/*
+	 * Check if the CPU supports EST.
+	 */
+	if (!(cpu_feature2 & CPUID2_EST))
+		return;
+
+	/*
+	 * We add a child for each CPU since settings must be performed
+	 * on each CPU in the SMP case.
+	 */
+	child = BUS_ADD_CHILD(parent, 10, "est", -1);
+	if (child == NULL)
+		device_printf(parent, "add est child failed\n");
+}
+
+static int
+est_probe(device_t dev)
+{
+	device_t perf_dev;
+	uint64_t msr;
+	int error, type;
+        
+	if (resource_disabled("est", 0))
+		return (ENXIO);
+
+	/*
+	 * If the ACPI perf driver has attached and is not just offering
+	 * info, let it manage things.
+	 */
+	perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
+	if (perf_dev && device_is_attached(perf_dev)) {
+		error = CPUFREQ_DRV_TYPE(perf_dev, &type);
+		if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0)
+			return (ENXIO);
+	}
+
+	/* Attempt to enable SpeedStep if not currently enabled. */
+	msr = rdmsr(MSR_MISC_ENABLE);
+	if ((msr & MSR_SS_ENABLE) == 0) {
+		wrmsr(MSR_MISC_ENABLE, msr | MSR_SS_ENABLE);
+		if (bootverbose)
+			device_printf(dev, "enabling SpeedStep\n");
+
+		/* Check if the enable failed. */
+		msr = rdmsr(MSR_MISC_ENABLE);
+		if ((msr & MSR_SS_ENABLE) == 0) {
+			device_printf(dev, "failed to enable SpeedStep\n");
+			return (ENXIO);
+		}
+	}
+
+	device_set_desc(dev, "Enhanced SpeedStep Frequency Control");
+	return (0);
+}
+
+static int
+est_attach(device_t dev)
+{
+	struct est_softc *sc;
+
+	sc = device_get_softc(dev);
+	sc->dev = dev;
+
+	/* On SMP system we can't guarantie independent freq setting. */
+	if (strict == -1 && mp_ncpus > 1)
+		strict = 0;
+	/* Check CPU for supported settings. */
+	if (est_get_info(dev))
+		return (ENXIO);
+
+	cpufreq_register(dev);
+	return (0);
+}
+
+static int
+est_detach(device_t dev)
+{
+	struct est_softc *sc;
+	int error;
+
+	error = cpufreq_unregister(dev);
+	if (error)
+		return (error);
+
+	sc = device_get_softc(dev);
+	if (sc->acpi_settings || sc->msr_settings)
+		free(sc->freq_list, M_DEVBUF);
+	return (0);
+}
+
+/*
+ * Probe for supported CPU settings.  First, check our static table of
+ * settings.  If no match, try using the ones offered by acpi_perf
+ * (i.e., _PSS).  We use ACPI second because some systems (IBM R/T40
+ * series) export both legacy SMM IO-based access and direct MSR access
+ * but the direct access specifies invalid values for _PSS.
+ */
+static int
+est_get_info(device_t dev)
+{
+	struct est_softc *sc;
+	uint64_t msr;
+	int error;
+
+	sc = device_get_softc(dev);
+	msr = rdmsr(MSR_PERF_STATUS);
+	error = est_table_info(dev, msr, &sc->freq_list);
+	if (error)
+		error = est_acpi_info(dev, &sc->freq_list);
+	if (error)
+		error = est_msr_info(dev, msr, &sc->freq_list);
+
+	if (error) {
+		printf(
+	"est: CPU supports Enhanced Speedstep, but is not recognized.\n"
+	"est: cpu_vendor %s, msr %0jx\n", cpu_vendor, msr);
+		return (ENXIO);
+	}
+
+	return (0);
+}
+
+static int
+est_acpi_info(device_t dev, freq_info **freqs)
+{
+	struct est_softc *sc;
+	struct cf_setting *sets;
+	freq_info *table;
+	device_t perf_dev;
+	int count, error, i, j;
+	uint16_t saved_id16;
+
+	perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
+	if (perf_dev == NULL || !device_is_attached(perf_dev))
+		return (ENXIO);
+
+	/* Fetch settings from acpi_perf. */
+	sc = device_get_softc(dev);
+	table = NULL;
+	sets = malloc(MAX_SETTINGS * sizeof(*sets), M_TEMP, M_NOWAIT);
+	if (sets == NULL)
+		return (ENOMEM);
+	count = MAX_SETTINGS;
+	error = CPUFREQ_DRV_SETTINGS(perf_dev, sets, &count);
+	if (error)
+		goto out;
+
+	/* Parse settings into our local table format. */
+	table = malloc((count + 1) * sizeof(freq_info), M_DEVBUF, M_NOWAIT);
+	if (table == NULL) {
+		error = ENOMEM;
+		goto out;
+	}
+	est_get_id16(&saved_id16);
+	for (i = 0, j = 0; i < count; i++) {
+		/*
+		 * Confirm id16 value is correct.
+		 */
+		if (sets[i].freq > 0) {
+			error = est_set_id16(dev, sets[i].spec[0], 1);
+			if (error != 0 && strict) {
+				if (bootverbose) 
+					device_printf(dev, "Invalid freq %u, "
+					    "ignored.\n", sets[i].freq);
+				continue;
+			} else if (error != 0 && bootverbose) {
+				device_printf(dev, "Can't check freq %u, "
+				    "it may be invalid\n",
+				    sets[i].freq);
+			}
+			table[j].freq = sets[i].freq;
+			table[j].volts = sets[i].volts;
+			table[j].id16 = sets[i].spec[0];
+			table[j].power = sets[i].power;
+			++j;
+		}
+	}
+	/* restore saved setting */
+	est_set_id16(dev, saved_id16, 0);
+
+	/* Mark end of table with a terminator. */
+	bzero(&table[j], sizeof(freq_info));
+
+	sc->acpi_settings = TRUE;
+	*freqs = table;
+	error = 0;
+
+out:
+	if (sets)
+		free(sets, M_TEMP);
+	if (error && table)
+		free(table, M_DEVBUF);
+	return (error);
+}
+
+static int
+est_table_info(device_t dev, uint64_t msr, freq_info **freqs)
+{
+	cpu_info *p;
+	uint32_t id;
+
+	/* Find a table which matches (vendor, id32). */
+	id = msr >> 32;
+	for (p = ESTprocs; p->id32 != 0; p++) {
+		if (p->vendor_id == cpu_vendor_id && p->id32 == id)
+			break;
+	}
+	if (p->id32 == 0)
+		return (EOPNOTSUPP);
+
+	/* Make sure the current setpoint is valid. */
+	if (est_get_current(p->freqtab) == NULL) {
+		device_printf(dev, "current setting not found in table\n");
+		return (EOPNOTSUPP);
+	}
+
+	*freqs = p->freqtab;
+	return (0);
+}
+
+static int
+bus_speed_ok(int bus)
+{
+
+	switch (bus) {
+	case 100:
+	case 133:
+	case 333:
+		return (1);
+	default:
+		return (0);
+	}
+}
+
+/*
+ * Flesh out a simple rate table containing the high and low frequencies
+ * based on the current clock speed and the upper 32 bits of the MSR.
+ */
+static int
+est_msr_info(device_t dev, uint64_t msr, freq_info **freqs)
+{
+	struct est_softc *sc;
+	freq_info *fp;
+	int bus, freq, volts;
+	uint16_t id;
+
+	if (!msr_info_enabled)
+		return (EOPNOTSUPP);
+
+	/* Figure out the bus clock. */
+	freq = tsc_freq / 1000000;
+	id = msr >> 32;
+	bus = freq / (id >> 8);
+	device_printf(dev, "Guessed bus clock (high) of %d MHz\n", bus);
+	if (!bus_speed_ok(bus)) {
+		/* We may be running on the low frequency. */
+		id = msr >> 48;
+		bus = freq / (id >> 8);
+		device_printf(dev, "Guessed bus clock (low) of %d MHz\n", bus);
+		if (!bus_speed_ok(bus))
+			return (EOPNOTSUPP);
+		
+		/* Calculate high frequency. */
+		id = msr >> 32;
+		freq = ((id >> 8) & 0xff) * bus;
+	}
+
+	/* Fill out a new freq table containing just the high and low freqs. */
+	sc = device_get_softc(dev);
+	fp = malloc(sizeof(freq_info) * 3, M_DEVBUF, M_WAITOK | M_ZERO);
+
+	/* First, the high frequency. */
+	volts = id & 0xff;
+	if (volts != 0) {
+		volts <<= 4;
+		volts += 700;
+	}
+	fp[0].freq = freq;
+	fp[0].volts = volts;
+	fp[0].id16 = id;
+	fp[0].power = CPUFREQ_VAL_UNKNOWN;
+	device_printf(dev, "Guessed high setting of %d MHz @ %d Mv\n", freq,
+	    volts);
+
+	/* Second, the low frequency. */
+	id = msr >> 48;
+	freq = ((id >> 8) & 0xff) * bus;
+	volts = id & 0xff;
+	if (volts != 0) {
+		volts <<= 4;
+		volts += 700;
+	}
+	fp[1].freq = freq;
+	fp[1].volts = volts;
+	fp[1].id16 = id;
+	fp[1].power = CPUFREQ_VAL_UNKNOWN;
+	device_printf(dev, "Guessed low setting of %d MHz @ %d Mv\n", freq,
+	    volts);
+
+	/* Table is already terminated due to M_ZERO. */
+	sc->msr_settings = TRUE;
+	*freqs = fp;
+	return (0);
+}
+
+static void
+est_get_id16(uint16_t *id16_p)
+{
+	*id16_p = rdmsr(MSR_PERF_STATUS) & 0xffff;
+}
+
+static int
+est_set_id16(device_t dev, uint16_t id16, int need_check)
+{
+	uint64_t msr;
+	uint16_t new_id16;
+	int ret = 0;
+
+	/* Read the current register, mask out the old, set the new id. */
+	msr = rdmsr(MSR_PERF_CTL);
+	msr = (msr & ~0xffff) | id16;
+	wrmsr(MSR_PERF_CTL, msr);
+	
+	/* Wait a short while for the new setting.  XXX Is this necessary? */
+	DELAY(EST_TRANS_LAT);
+	
+	if  (need_check) {
+		est_get_id16(&new_id16);		
+		if (new_id16 != id16) {
+			if (bootverbose) 
+				device_printf(dev, "Invalid id16 (set, cur) "
+				    "= (%u, %u)\n", id16, new_id16);
+			ret = ENXIO;
+		}
+	}
+	return (ret);
+}
+
+static freq_info *
+est_get_current(freq_info *freq_list)
+{
+	freq_info *f;
+	int i;
+	uint16_t id16;
+
+	/*
+	 * Try a few times to get a valid value.  Sometimes, if the CPU
+	 * is in the middle of an asynchronous transition (i.e., P4TCC),
+	 * we get a temporary invalid result.
+	 */
+	for (i = 0; i < 5; i++) {
+		est_get_id16(&id16);
+		for (f = freq_list; f->id16 != 0; f++) {
+			if (f->id16 == id16)
+				return (f);
+		}
+		DELAY(100);
+	}
+	return (NULL);
+}
+
+static int
+est_settings(device_t dev, struct cf_setting *sets, int *count)
+{
+	struct est_softc *sc;
+	freq_info *f;
+	int i;
+
+	sc = device_get_softc(dev);
+	if (*count < EST_MAX_SETTINGS)
+		return (E2BIG);
+
+	i = 0;
+	for (f = sc->freq_list; f->freq != 0; f++, i++) {
+		sets[i].freq = f->freq;
+		sets[i].volts = f->volts;
+		sets[i].power = f->power;
+		sets[i].lat = EST_TRANS_LAT;
+		sets[i].dev = dev;
+	}
+	*count = i;
+
+	return (0);
+}
+
+static int
+est_set(device_t dev, const struct cf_setting *set)
+{
+	struct est_softc *sc;
+	freq_info *f;
+
+	/* Find the setting matching the requested one. */
+	sc = device_get_softc(dev);
+	for (f = sc->freq_list; f->freq != 0; f++) {
+		if (f->freq == set->freq)
+			break;
+	}
+	if (f->freq == 0)
+		return (EINVAL);
+
+	/* Read the current register, mask out the old, set the new id. */
+	est_set_id16(dev, f->id16, 0);
+
+	return (0);
+}
+
+static int
+est_get(device_t dev, struct cf_setting *set)
+{
+	struct est_softc *sc;
+	freq_info *f;
+
+	sc = device_get_softc(dev);
+	f = est_get_current(sc->freq_list);
+	if (f == NULL)
+		return (ENXIO);
+
+	set->freq = f->freq;
+	set->volts = f->volts;
+	set->power = f->power;
+	set->lat = EST_TRANS_LAT;
+	set->dev = dev;
+	return (0);
+}
+
+static int
+est_type(device_t dev, int *type)
+{
+
+	if (type == NULL)
+		return (EINVAL);
+
+	*type = CPUFREQ_TYPE_ABSOLUTE;
+	return (0);
+}
diff --git a/sys/x86/cpufreq/hwpstate.c b/sys/x86/cpufreq/hwpstate.c
new file mode 100644
index 0000000..3790b76
--- /dev/null
+++ b/sys/x86/cpufreq/hwpstate.c
@@ -0,0 +1,507 @@
+/*-
+ * Copyright (c) 2005 Nate Lawson
+ * Copyright (c) 2004 Colin Percival
+ * Copyright (c) 2004-2005 Bruno Durcot
+ * Copyright (c) 2004 FUKUDA Nobuhiko
+ * Copyright (c) 2009 Michael Reifenberger
+ * Copyright (c) 2009 Norikatsu Shigemura
+ * Copyright (c) 2008-2009 Gen Otsuji
+ *
+ * This code is depending on kern_cpu.c, est.c, powernow.c, p4tcc.c, smist.c
+ * in various parts. The authors of these files are Nate Lawson,
+ * Colin Percival, Bruno Durcot, and FUKUDA Nobuhiko.
+ * This code contains patches by Michael Reifenberger and Norikatsu Shigemura.
+ * Thank you.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted providing that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * For more info:
+ * BIOS and Kernel Developer's Guide(BKDG) for AMD Family 10h Processors
+ * 31116 Rev 3.20  February 04, 2009
+ * BIOS and Kernel Developer's Guide(BKDG) for AMD Family 11h Processors
+ * 41256 Rev 3.00 - July 07, 2008
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/malloc.h>
+#include <sys/proc.h>
+#include <sys/pcpu.h>
+#include <sys/smp.h>
+#include <sys/sched.h>
+
+#include <machine/md_var.h>
+#include <machine/cputypes.h>
+#include <machine/specialreg.h>
+
+#include <contrib/dev/acpica/include/acpi.h>
+
+#include <dev/acpica/acpivar.h>
+
+#include "acpi_if.h"
+#include "cpufreq_if.h"
+
+#define	MSR_AMD_10H_11H_LIMIT	0xc0010061
+#define	MSR_AMD_10H_11H_CONTROL	0xc0010062
+#define	MSR_AMD_10H_11H_STATUS	0xc0010063
+#define	MSR_AMD_10H_11H_CONFIG	0xc0010064
+
+#define	AMD_10H_11H_MAX_STATES	16
+
+/* for MSR_AMD_10H_11H_LIMIT C001_0061 */
+#define	AMD_10H_11H_GET_PSTATE_MAX_VAL(msr)	(((msr) >> 4) & 0x7)
+#define	AMD_10H_11H_GET_PSTATE_LIMIT(msr)	(((msr)) & 0x7)
+/* for MSR_AMD_10H_11H_CONFIG 10h:C001_0064:68 / 11h:C001_0064:6B */
+#define	AMD_10H_11H_CUR_VID(msr)		(((msr) >> 9) & 0x7F)
+#define	AMD_10H_11H_CUR_DID(msr)		(((msr) >> 6) & 0x07)
+#define	AMD_10H_11H_CUR_FID(msr)		((msr) & 0x3F)
+
+#define	HWPSTATE_DEBUG(dev, msg...)			\
+	do{						\
+		if(hwpstate_verbose)			\
+			device_printf(dev, msg);	\
+	}while(0)
+
+struct hwpstate_setting {
+	int	freq;		/* CPU clock in Mhz or 100ths of a percent. */
+	int	volts;		/* Voltage in mV. */
+	int	power;		/* Power consumed in mW. */
+	int	lat;		/* Transition latency in us. */
+	int	pstate_id;	/* P-State id */
+};
+
+struct hwpstate_softc {
+	device_t		dev;
+	struct hwpstate_setting	hwpstate_settings[AMD_10H_11H_MAX_STATES];
+	int			cfnum;
+};
+
+static void	hwpstate_identify(driver_t *driver, device_t parent);
+static int	hwpstate_probe(device_t dev);
+static int	hwpstate_attach(device_t dev);
+static int	hwpstate_detach(device_t dev);
+static int	hwpstate_set(device_t dev, const struct cf_setting *cf);
+static int	hwpstate_get(device_t dev, struct cf_setting *cf);
+static int	hwpstate_settings(device_t dev, struct cf_setting *sets, int *count);
+static int	hwpstate_type(device_t dev, int *type);
+static int	hwpstate_shutdown(device_t dev);
+static int	hwpstate_features(driver_t *driver, u_int *features);
+static int	hwpstate_get_info_from_acpi_perf(device_t dev, device_t perf_dev);
+static int	hwpstate_get_info_from_msr(device_t dev);
+static int	hwpstate_goto_pstate(device_t dev, int pstate_id);
+
+static int	hwpstate_verbose = 0;
+SYSCTL_INT(_debug, OID_AUTO, hwpstate_verbose, CTLFLAG_RDTUN,
+       &hwpstate_verbose, 0, "Debug hwpstate");
+
+static device_method_t hwpstate_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_identify,	hwpstate_identify),
+	DEVMETHOD(device_probe,		hwpstate_probe),
+	DEVMETHOD(device_attach,	hwpstate_attach),
+	DEVMETHOD(device_detach,	hwpstate_detach),
+	DEVMETHOD(device_shutdown,	hwpstate_shutdown),
+
+	/* cpufreq interface */
+	DEVMETHOD(cpufreq_drv_set,	hwpstate_set),
+	DEVMETHOD(cpufreq_drv_get,	hwpstate_get),
+	DEVMETHOD(cpufreq_drv_settings,	hwpstate_settings),
+	DEVMETHOD(cpufreq_drv_type,	hwpstate_type),
+
+	/* ACPI interface */
+	DEVMETHOD(acpi_get_features,	hwpstate_features),
+
+	{0, 0}
+};
+
+static devclass_t hwpstate_devclass;
+static driver_t hwpstate_driver = {
+	"hwpstate",
+	hwpstate_methods,
+	sizeof(struct hwpstate_softc),
+};
+
+DRIVER_MODULE(hwpstate, cpu, hwpstate_driver, hwpstate_devclass, 0, 0);
+
+/*
+ * Go to Px-state on all cpus considering the limit.
+ */
+static int
+hwpstate_goto_pstate(device_t dev, int pstate)
+{
+	struct pcpu *pc;
+	int i;
+	uint64_t msr;
+	int j;
+	int limit;
+	int id = pstate;
+	int error;
+	
+	/* get the current pstate limit */
+	msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
+	limit = AMD_10H_11H_GET_PSTATE_LIMIT(msr);
+	if(limit > id)
+		id = limit;
+
+	error = 0;
+	/*
+	 * We are going to the same Px-state on all cpus.
+	 */
+	for (i = 0; i < mp_ncpus; i++) {
+		/* Find each cpu. */
+		pc = pcpu_find(i);
+		if (pc == NULL)
+			return (ENXIO);
+		thread_lock(curthread);
+		/* Bind to each cpu. */
+		sched_bind(curthread, pc->pc_cpuid);
+		thread_unlock(curthread);
+		HWPSTATE_DEBUG(dev, "setting P%d-state on cpu%d\n",
+			id, PCPU_GET(cpuid));
+		/* Go To Px-state */
+		wrmsr(MSR_AMD_10H_11H_CONTROL, id);
+		/* wait loop (100*100 usec is enough ?) */
+		for(j = 0; j < 100; j++){
+			msr = rdmsr(MSR_AMD_10H_11H_STATUS);
+			if(msr == id){
+				break;
+			}
+			DELAY(100);
+		}
+		/* get the result. not assure msr=id */
+		msr = rdmsr(MSR_AMD_10H_11H_STATUS);
+		HWPSTATE_DEBUG(dev, "result  P%d-state on cpu%d\n",
+		    (int)msr, PCPU_GET(cpuid));
+		if (msr != id) {
+			HWPSTATE_DEBUG(dev, "error: loop is not enough.\n");
+			error = ENXIO;
+		}
+		thread_lock(curthread);
+		sched_unbind(curthread);
+		thread_unlock(curthread);
+	}
+	return (error);
+}
+
+static int
+hwpstate_set(device_t dev, const struct cf_setting *cf)
+{
+	struct hwpstate_softc *sc;
+	struct hwpstate_setting *set;
+	int i;
+
+	if (cf == NULL)
+		return (EINVAL);
+	sc = device_get_softc(dev);
+	set = sc->hwpstate_settings;
+	for (i = 0; i < sc->cfnum; i++)
+		if (CPUFREQ_CMP(cf->freq, set[i].freq))
+			break;
+	if (i == sc->cfnum)
+		return (EINVAL);
+
+	return (hwpstate_goto_pstate(dev, set[i].pstate_id));
+}
+
+static int
+hwpstate_get(device_t dev, struct cf_setting *cf)
+{
+	struct hwpstate_softc *sc;
+	struct hwpstate_setting set;
+	uint64_t msr;
+
+	sc = device_get_softc(dev);
+	if (cf == NULL)
+		return (EINVAL);
+	msr = rdmsr(MSR_AMD_10H_11H_STATUS);
+	if(msr >= sc->cfnum)
+		return (EINVAL);
+	set = sc->hwpstate_settings[msr];
+
+	cf->freq = set.freq;
+	cf->volts = set.volts;
+	cf->power = set.power;
+	cf->lat = set.lat;
+	cf->dev = dev;
+	return (0);
+}
+
+static int
+hwpstate_settings(device_t dev, struct cf_setting *sets, int *count)
+{
+	struct hwpstate_softc *sc;
+	struct hwpstate_setting set;
+	int i;
+
+	if (sets == NULL || count == NULL)
+		return (EINVAL);
+	sc = device_get_softc(dev);
+	if (*count < sc->cfnum)
+		return (E2BIG);
+	for (i = 0; i < sc->cfnum; i++, sets++) {
+		set = sc->hwpstate_settings[i];
+		sets->freq = set.freq;
+		sets->volts = set.volts;
+		sets->power = set.power;
+		sets->lat = set.lat;
+		sets->dev = dev;
+	}
+	*count = sc->cfnum;
+
+	return (0);
+}
+
+static int
+hwpstate_type(device_t dev, int *type)
+{
+
+	if (type == NULL)
+		return (EINVAL);
+
+	*type = CPUFREQ_TYPE_ABSOLUTE;
+	return (0);
+}
+
+static void
+hwpstate_identify(driver_t *driver, device_t parent)
+{
+
+	if (device_find_child(parent, "hwpstate", -1) != NULL)
+		return;
+
+	if (cpu_vendor_id != CPU_VENDOR_AMD || CPUID_TO_FAMILY(cpu_id) < 0x10)
+		return;
+
+	/*
+	 * Check if hardware pstate enable bit is set.
+	 */
+	if ((amd_pminfo & AMDPM_HW_PSTATE) == 0) {
+		HWPSTATE_DEBUG(parent, "hwpstate enable bit is not set.\n");
+		return;
+	}
+
+	if (resource_disabled("hwpstate", 0))
+		return;
+
+	if (BUS_ADD_CHILD(parent, 10, "hwpstate", -1) == NULL)
+		device_printf(parent, "hwpstate: add child failed\n");
+}
+
+static int
+hwpstate_probe(device_t dev)
+{
+	struct hwpstate_softc *sc;
+	device_t perf_dev;
+	uint64_t msr;
+	int error, type;
+
+	/*
+	 * Only hwpstate0.
+	 * It goes well with acpi_throttle.
+	 */
+	if (device_get_unit(dev) != 0)
+		return (ENXIO);
+
+	sc = device_get_softc(dev);
+	sc->dev = dev;
+
+	/*
+	 * Check if acpi_perf has INFO only flag.
+	 */
+	perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
+	error = TRUE;
+	if (perf_dev && device_is_attached(perf_dev)) {
+		error = CPUFREQ_DRV_TYPE(perf_dev, &type);
+		if (error == 0) {
+			if ((type & CPUFREQ_FLAG_INFO_ONLY) == 0) {
+				/*
+				 * If acpi_perf doesn't have INFO_ONLY flag,
+				 * it will take care of pstate transitions.
+				 */
+				HWPSTATE_DEBUG(dev, "acpi_perf will take care of pstate transitions.\n");
+				return (ENXIO);
+			} else {
+				/*
+				 * If acpi_perf has INFO_ONLY flag, (_PCT has FFixedHW)
+				 * we can get _PSS info from acpi_perf
+				 * without going into ACPI.
+				 */
+				HWPSTATE_DEBUG(dev, "going to fetch info from acpi_perf\n");
+				error = hwpstate_get_info_from_acpi_perf(dev, perf_dev);
+			}
+		}
+	}
+
+	if (error == 0) {
+		/*
+		 * Now we get _PSS info from acpi_perf without error.
+		 * Let's check it.
+		 */
+		msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
+		if (sc->cfnum != 1 + AMD_10H_11H_GET_PSTATE_MAX_VAL(msr)) {
+			HWPSTATE_DEBUG(dev, "msr and acpi _PSS count mismatch.\n");
+			error = TRUE;
+		}
+	}
+
+	/*
+	 * If we cannot get info from acpi_perf,
+	 * Let's get info from MSRs.
+	 */
+	if (error)
+		error = hwpstate_get_info_from_msr(dev);
+	if (error)
+		return (error);
+
+	device_set_desc(dev, "Cool`n'Quiet 2.0");
+	return (0);
+}
+
+static int
+hwpstate_attach(device_t dev)
+{
+
+	return (cpufreq_register(dev));
+}
+
+static int
+hwpstate_get_info_from_msr(device_t dev)
+{
+	struct hwpstate_softc *sc;
+	struct hwpstate_setting *hwpstate_set;
+	uint64_t msr;
+	int family, i, fid, did;
+
+	family = CPUID_TO_FAMILY(cpu_id);
+	sc = device_get_softc(dev);
+	/* Get pstate count */
+	msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
+	sc->cfnum = 1 + AMD_10H_11H_GET_PSTATE_MAX_VAL(msr);
+	hwpstate_set = sc->hwpstate_settings;
+	for (i = 0; i < sc->cfnum; i++) {
+		msr = rdmsr(MSR_AMD_10H_11H_CONFIG + i);
+		if ((msr & ((uint64_t)1 << 63)) != ((uint64_t)1 << 63)) {
+			HWPSTATE_DEBUG(dev, "msr is not valid.\n");
+			return (ENXIO);
+		}
+		did = AMD_10H_11H_CUR_DID(msr);
+		fid = AMD_10H_11H_CUR_FID(msr);
+		switch(family) {
+		case 0x11:
+			/* fid/did to frequency */
+			hwpstate_set[i].freq = 100 * (fid + 0x08) / (1 << did);
+			break;
+		case 0x10:
+			/* fid/did to frequency */
+			hwpstate_set[i].freq = 100 * (fid + 0x10) / (1 << did);
+			break;
+		default:
+			HWPSTATE_DEBUG(dev, "get_info_from_msr: AMD family %d CPU's are not implemented yet. sorry.\n", family);
+			return (ENXIO);
+			break;
+		}
+		hwpstate_set[i].pstate_id = i;
+		/* There was volts calculation, but deleted it. */
+		hwpstate_set[i].volts = CPUFREQ_VAL_UNKNOWN;
+		hwpstate_set[i].power = CPUFREQ_VAL_UNKNOWN;
+		hwpstate_set[i].lat = CPUFREQ_VAL_UNKNOWN;
+	}
+	return (0);
+}
+
+static int
+hwpstate_get_info_from_acpi_perf(device_t dev, device_t perf_dev)
+{
+	struct hwpstate_softc *sc;
+	struct cf_setting *perf_set;
+	struct hwpstate_setting *hwpstate_set;
+	int count, error, i;
+
+	perf_set = malloc(MAX_SETTINGS * sizeof(*perf_set), M_TEMP, M_NOWAIT);
+	if (perf_set == NULL) {
+		HWPSTATE_DEBUG(dev, "nomem\n");
+		return (ENOMEM);
+	}
+	/*
+	 * Fetch settings from acpi_perf.
+	 * Now it is attached, and has info only flag.
+	 */
+	count = MAX_SETTINGS;
+	error = CPUFREQ_DRV_SETTINGS(perf_dev, perf_set, &count);
+	if (error) {
+		HWPSTATE_DEBUG(dev, "error: CPUFREQ_DRV_SETTINGS.\n");
+		goto out;
+	}
+	sc = device_get_softc(dev);
+	sc->cfnum = count;
+	hwpstate_set = sc->hwpstate_settings;
+	for (i = 0; i < count; i++) {
+		if (i == perf_set[i].spec[0]) {
+			hwpstate_set[i].pstate_id = i;
+			hwpstate_set[i].freq = perf_set[i].freq;
+			hwpstate_set[i].volts = perf_set[i].volts;
+			hwpstate_set[i].power = perf_set[i].power;
+			hwpstate_set[i].lat = perf_set[i].lat;
+		} else {
+			HWPSTATE_DEBUG(dev, "ACPI _PSS object mismatch.\n");
+			error = ENXIO;
+			goto out;
+		}
+	}
+out:
+	if (perf_set)
+		free(perf_set, M_TEMP);
+	return (error);
+}
+
+static int
+hwpstate_detach(device_t dev)
+{
+
+	hwpstate_goto_pstate(dev, 0);
+	return (cpufreq_unregister(dev));
+}
+
+static int
+hwpstate_shutdown(device_t dev)
+{
+
+	/* hwpstate_goto_pstate(dev, 0); */
+	return (0);
+}
+
+static int
+hwpstate_features(driver_t *driver, u_int *features)
+{
+
+	/* Notify the ACPI CPU that we support direct access to MSRs */
+	*features = ACPI_CAP_PERF_MSRS;
+	return (0);
+}
diff --git a/sys/x86/cpufreq/p4tcc.c b/sys/x86/cpufreq/p4tcc.c
new file mode 100644
index 0000000..29279e3
--- /dev/null
+++ b/sys/x86/cpufreq/p4tcc.c
@@ -0,0 +1,327 @@
+/*-
+ * Copyright (c) 2005 Nate Lawson
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Throttle clock frequency by using the thermal control circuit.  This
+ * operates independently of SpeedStep and ACPI throttling and is supported
+ * on Pentium 4 and later models (feature TM).
+ *
+ * Reference:  Intel Developer's manual v.3 #245472-012
+ *
+ * The original version of this driver was written by Ted Unangst for
+ * OpenBSD and imported by Maxim Sobolev.  It was rewritten by Nate Lawson
+ * for use with the cpufreq framework.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+
+#include <machine/md_var.h>
+#include <machine/specialreg.h>
+
+#include "cpufreq_if.h"
+
+#include <contrib/dev/acpica/include/acpi.h>
+
+#include <dev/acpica/acpivar.h>
+#include "acpi_if.h"
+ 
+struct p4tcc_softc {
+	device_t	dev;
+	int		set_count;
+	int		lowest_val;
+	int		auto_mode;
+};
+
+#define TCC_NUM_SETTINGS	8
+
+#define TCC_ENABLE_ONDEMAND	(1<<4)
+#define TCC_REG_OFFSET		1
+#define TCC_SPEED_PERCENT(x)	((10000 * (x)) / TCC_NUM_SETTINGS)
+
+static int	p4tcc_features(driver_t *driver, u_int *features);
+static void	p4tcc_identify(driver_t *driver, device_t parent);
+static int	p4tcc_probe(device_t dev);
+static int	p4tcc_attach(device_t dev);
+static int	p4tcc_settings(device_t dev, struct cf_setting *sets,
+		    int *count);
+static int	p4tcc_set(device_t dev, const struct cf_setting *set);
+static int	p4tcc_get(device_t dev, struct cf_setting *set);
+static int	p4tcc_type(device_t dev, int *type);
+
+static device_method_t p4tcc_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_identify,	p4tcc_identify),
+	DEVMETHOD(device_probe,		p4tcc_probe),
+	DEVMETHOD(device_attach,	p4tcc_attach),
+
+	/* cpufreq interface */
+	DEVMETHOD(cpufreq_drv_set,	p4tcc_set),
+	DEVMETHOD(cpufreq_drv_get,	p4tcc_get),
+	DEVMETHOD(cpufreq_drv_type,	p4tcc_type),
+	DEVMETHOD(cpufreq_drv_settings,	p4tcc_settings),
+
+	/* ACPI interface */
+	DEVMETHOD(acpi_get_features,	p4tcc_features),
+
+	{0, 0}
+};
+
+static driver_t p4tcc_driver = {
+	"p4tcc",
+	p4tcc_methods,
+	sizeof(struct p4tcc_softc),
+};
+
+static devclass_t p4tcc_devclass;
+DRIVER_MODULE(p4tcc, cpu, p4tcc_driver, p4tcc_devclass, 0, 0);
+
+static int
+p4tcc_features(driver_t *driver, u_int *features)
+{
+
+	/* Notify the ACPI CPU that we support direct access to MSRs */
+	*features = ACPI_CAP_THR_MSRS;
+	return (0);
+}
+
+static void
+p4tcc_identify(driver_t *driver, device_t parent)
+{
+
+	if ((cpu_feature & (CPUID_ACPI | CPUID_TM)) != (CPUID_ACPI | CPUID_TM))
+		return;
+
+	/* Make sure we're not being doubly invoked. */
+	if (device_find_child(parent, "p4tcc", -1) != NULL)
+		return;
+
+	/*
+	 * We attach a p4tcc child for every CPU since settings need to
+	 * be performed on every CPU in the SMP case.  See section 13.15.3
+	 * of the IA32 Intel Architecture Software Developer's Manual,
+	 * Volume 3, for more info.
+	 */
+	if (BUS_ADD_CHILD(parent, 10, "p4tcc", -1) == NULL)
+		device_printf(parent, "add p4tcc child failed\n");
+}
+
+static int
+p4tcc_probe(device_t dev)
+{
+
+	if (resource_disabled("p4tcc", 0))
+		return (ENXIO);
+
+	device_set_desc(dev, "CPU Frequency Thermal Control");
+	return (0);
+}
+
+static int
+p4tcc_attach(device_t dev)
+{
+	struct p4tcc_softc *sc;
+	struct cf_setting set;
+
+	sc = device_get_softc(dev);
+	sc->dev = dev;
+	sc->set_count = TCC_NUM_SETTINGS;
+
+	/*
+	 * On boot, the TCC is usually in Automatic mode where reading the
+	 * current performance level is likely to produce bogus results.
+	 * We record that state here and don't trust the contents of the
+	 * status MSR until we've set it ourselves.
+	 */
+	sc->auto_mode = TRUE;
+
+	/*
+	 * XXX: After a cursory glance at various Intel specification
+	 * XXX: updates it seems like these tests for errata is bogus.
+	 * XXX: As far as I can tell, the failure mode is benign, in
+	 * XXX: that cpus with no errata will have their bottom two
+	 * XXX: STPCLK# rates disabled, so rather than waste more time
+	 * XXX: hunting down intel docs, just document it and punt. /phk
+	 */
+	switch (cpu_id & 0xff) {
+	case 0x22:
+	case 0x24:
+	case 0x25:
+	case 0x27:
+	case 0x29:
+		/*
+		 * These CPU models hang when set to 12.5%.
+		 * See Errata O50, P44, and Z21.
+		 */
+		sc->set_count -= 1;
+		break;
+	case 0x07:	/* errata N44 and P18 */
+	case 0x0a:
+	case 0x12:
+	case 0x13:
+	case 0x62:	/* Pentium D B1: errata AA21 */
+	case 0x64:	/* Pentium D C1: errata AA21 */
+	case 0x65:	/* Pentium D D0: errata AA21 */
+		/*
+		 * These CPU models hang when set to 12.5% or 25%.
+		 * See Errata N44, P18l and AA21.
+		 */
+		sc->set_count -= 2;
+		break;
+	}
+	sc->lowest_val = TCC_NUM_SETTINGS - sc->set_count + 1;
+
+	/*
+	 * Before we finish attach, switch to 100%.  It's possible the BIOS
+	 * set us to a lower rate.  The user can override this after boot.
+	 */
+	set.freq = 10000;
+	p4tcc_set(dev, &set);
+
+	cpufreq_register(dev);
+	return (0);
+}
+
+static int
+p4tcc_settings(device_t dev, struct cf_setting *sets, int *count)
+{
+	struct p4tcc_softc *sc;
+	int i, val;
+
+	sc = device_get_softc(dev);
+	if (sets == NULL || count == NULL)
+		return (EINVAL);
+	if (*count < sc->set_count)
+		return (E2BIG);
+
+	/* Return a list of valid settings for this driver. */
+	memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->set_count);
+	val = TCC_NUM_SETTINGS;
+	for (i = 0; i < sc->set_count; i++, val--) {
+		sets[i].freq = TCC_SPEED_PERCENT(val);
+		sets[i].dev = dev;
+	}
+	*count = sc->set_count;
+
+	return (0);
+}
+
+static int
+p4tcc_set(device_t dev, const struct cf_setting *set)
+{
+	struct p4tcc_softc *sc;
+	uint64_t mask, msr;
+	int val;
+
+	if (set == NULL)
+		return (EINVAL);
+	sc = device_get_softc(dev);
+
+	/*
+	 * Validate requested state converts to a setting that is an integer
+	 * from [sc->lowest_val .. TCC_NUM_SETTINGS].
+	 */
+	val = set->freq * TCC_NUM_SETTINGS / 10000;
+	if (val * 10000 != set->freq * TCC_NUM_SETTINGS ||
+	    val < sc->lowest_val || val > TCC_NUM_SETTINGS)
+		return (EINVAL);
+
+	/*
+	 * Read the current register and mask off the old setting and
+	 * On-Demand bit.  If the new val is < 100%, set it and the On-Demand
+	 * bit, otherwise just return to Automatic mode.
+	 */
+	msr = rdmsr(MSR_THERM_CONTROL);
+	mask = (TCC_NUM_SETTINGS - 1) << TCC_REG_OFFSET;
+	msr &= ~(mask | TCC_ENABLE_ONDEMAND);
+	if (val < TCC_NUM_SETTINGS)
+		msr |= (val << TCC_REG_OFFSET) | TCC_ENABLE_ONDEMAND;
+	wrmsr(MSR_THERM_CONTROL, msr);
+
+	/*
+	 * Record whether we're now in Automatic or On-Demand mode.  We have
+	 * to cache this since there is no reliable way to check if TCC is in
+	 * Automatic mode (i.e., at 100% or possibly 50%).  Reading bit 4 of
+	 * the ACPI Thermal Monitor Control Register produces 0 no matter
+	 * what the current mode.
+	 */
+	if (msr & TCC_ENABLE_ONDEMAND)
+		sc->auto_mode = TRUE;
+	else
+		sc->auto_mode = FALSE;
+
+	return (0);
+}
+
+static int
+p4tcc_get(device_t dev, struct cf_setting *set)
+{
+	struct p4tcc_softc *sc;
+	uint64_t msr;
+	int val;
+
+	if (set == NULL)
+		return (EINVAL);
+	sc = device_get_softc(dev);
+
+	/*
+	 * Read the current register and extract the current setting.  If
+	 * in automatic mode, assume we're at TCC_NUM_SETTINGS (100%).
+	 *
+	 * XXX This is not completely reliable since at high temperatures
+	 * the CPU may be automatically throttling to 50% but it's the best
+	 * we can do.
+	 */
+	if (!sc->auto_mode) {
+		msr = rdmsr(MSR_THERM_CONTROL);
+		val = (msr >> TCC_REG_OFFSET) & (TCC_NUM_SETTINGS - 1);
+	} else
+		val = TCC_NUM_SETTINGS;
+
+	memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set));
+	set->freq = TCC_SPEED_PERCENT(val);
+	set->dev = dev;
+
+	return (0);
+}
+
+static int
+p4tcc_type(device_t dev, int *type)
+{
+
+	if (type == NULL)
+		return (EINVAL);
+
+	*type = CPUFREQ_TYPE_RELATIVE;
+	return (0);
+}
diff --git a/sys/x86/cpufreq/powernow.c b/sys/x86/cpufreq/powernow.c
new file mode 100644
index 0000000..b248cc8
--- /dev/null
+++ b/sys/x86/cpufreq/powernow.c
@@ -0,0 +1,970 @@
+/*-
+ * Copyright (c) 2004-2005 Bruno Ducrot
+ * Copyright (c) 2004 FUKUDA Nobuhiko <nfukuda@spa.is.uec.ac.jp>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Many thanks to Nate Lawson for his helpful comments on this driver and
+ * to Jung-uk Kim for testing.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <sys/pcpu.h>
+#include <sys/systm.h>
+
+#include <machine/pc/bios.h>
+#include <machine/md_var.h>
+#include <machine/specialreg.h>
+#include <machine/cputypes.h>
+#include <machine/vmparam.h>
+#include <sys/rman.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+
+#include "cpufreq_if.h"
+
+#define PN7_TYPE	0
+#define PN8_TYPE	1
+
+/* Flags for some hardware bugs. */
+#define A0_ERRATA	0x1	/* Bugs for the rev. A0 of Athlon (K7):
+				 * Interrupts must be disabled and no half
+				 * multipliers are allowed */
+#define PENDING_STUCK	0x2	/* With some buggy chipset and some newer AMD64
+				 * processor (Rev. G?):
+				 * the pending bit from the msr FIDVID_STATUS
+				 * is set forever.  No workaround :( */
+
+/* Legacy configuration via BIOS table PSB. */
+#define PSB_START	0
+#define PSB_STEP	0x10
+#define PSB_SIG		"AMDK7PNOW!"
+#define PSB_LEN		10
+#define PSB_OFF		0
+
+struct psb_header {
+	char		 signature[10];
+	uint8_t		 version;
+	uint8_t		 flags;
+	uint16_t	 settlingtime;
+	uint8_t		 res1;
+	uint8_t		 numpst;
+} __packed;
+
+struct pst_header {
+	uint32_t	 cpuid;
+	uint8_t		 fsb;
+	uint8_t		 maxfid;
+	uint8_t		 startvid;
+	uint8_t		 numpstates;
+} __packed;
+
+/*
+ * MSRs and bits used by Powernow technology
+ */
+#define MSR_AMDK7_FIDVID_CTL		0xc0010041
+#define MSR_AMDK7_FIDVID_STATUS		0xc0010042
+
+/* Bitfields used by K7 */
+
+#define PN7_CTR_FID(x)			((x) & 0x1f)
+#define PN7_CTR_VID(x)			(((x) & 0x1f) << 8)
+#define PN7_CTR_FIDC			0x00010000
+#define PN7_CTR_VIDC			0x00020000
+#define PN7_CTR_FIDCHRATIO		0x00100000
+#define PN7_CTR_SGTC(x)			(((uint64_t)(x) & 0x000fffff) << 32)
+
+#define PN7_STA_CFID(x)			((x) & 0x1f)
+#define PN7_STA_SFID(x)			(((x) >> 8) & 0x1f)
+#define PN7_STA_MFID(x)			(((x) >> 16) & 0x1f)
+#define PN7_STA_CVID(x)			(((x) >> 32) & 0x1f)
+#define PN7_STA_SVID(x)			(((x) >> 40) & 0x1f)
+#define PN7_STA_MVID(x)			(((x) >> 48) & 0x1f)
+
+/* ACPI ctr_val status register to powernow k7 configuration */
+#define ACPI_PN7_CTRL_TO_FID(x)		((x) & 0x1f)
+#define ACPI_PN7_CTRL_TO_VID(x)		(((x) >> 5) & 0x1f)
+#define ACPI_PN7_CTRL_TO_SGTC(x)	(((x) >> 10) & 0xffff)
+
+/* Bitfields used by K8 */
+
+#define PN8_CTR_FID(x)			((x) & 0x3f)
+#define PN8_CTR_VID(x)			(((x) & 0x1f) << 8)
+#define PN8_CTR_PENDING(x)		(((x) & 1) << 32)
+
+#define PN8_STA_CFID(x)			((x) & 0x3f)
+#define PN8_STA_SFID(x)			(((x) >> 8) & 0x3f)
+#define PN8_STA_MFID(x)			(((x) >> 16) & 0x3f)
+#define PN8_STA_PENDING(x)		(((x) >> 31) & 0x01)
+#define PN8_STA_CVID(x)			(((x) >> 32) & 0x1f)
+#define PN8_STA_SVID(x)			(((x) >> 40) & 0x1f)
+#define PN8_STA_MVID(x)			(((x) >> 48) & 0x1f)
+
+/* Reserved1 to powernow k8 configuration */
+#define PN8_PSB_TO_RVO(x)		((x) & 0x03)
+#define PN8_PSB_TO_IRT(x)		(((x) >> 2) & 0x03)
+#define PN8_PSB_TO_MVS(x)		(((x) >> 4) & 0x03)
+#define PN8_PSB_TO_BATT(x)		(((x) >> 6) & 0x03)
+
+/* ACPI ctr_val status register to powernow k8 configuration */
+#define ACPI_PN8_CTRL_TO_FID(x)		((x) & 0x3f)
+#define ACPI_PN8_CTRL_TO_VID(x)		(((x) >> 6) & 0x1f)
+#define ACPI_PN8_CTRL_TO_VST(x)		(((x) >> 11) & 0x1f)
+#define ACPI_PN8_CTRL_TO_MVS(x)		(((x) >> 18) & 0x03)
+#define ACPI_PN8_CTRL_TO_PLL(x)		(((x) >> 20) & 0x7f)
+#define ACPI_PN8_CTRL_TO_RVO(x)		(((x) >> 28) & 0x03)
+#define ACPI_PN8_CTRL_TO_IRT(x)		(((x) >> 30) & 0x03)
+
+
+#define WRITE_FIDVID(fid, vid, ctrl)	\
+	wrmsr(MSR_AMDK7_FIDVID_CTL,	\
+	    (((ctrl) << 32) | (1ULL << 16) | ((vid) << 8) | (fid)))
+
+#define COUNT_OFF_IRT(irt)	DELAY(10 * (1 << (irt)))
+#define COUNT_OFF_VST(vst)	DELAY(20 * (vst))
+
+#define FID_TO_VCO_FID(fid)	\
+	(((fid) < 8) ? (8 + ((fid) << 1)) : (fid))
+
+/*
+ * Divide each value by 10 to get the processor multiplier.
+ * Some of those tables are the same as the Linux powernow-k7
+ * implementation by Dave Jones.
+ */
+static int pn7_fid_to_mult[32] = {
+	110, 115, 120, 125, 50, 55, 60, 65,
+	70, 75, 80, 85, 90, 95, 100, 105,
+	30, 190, 40, 200, 130, 135, 140, 210,
+	150, 225, 160, 165, 170, 180, 0, 0,
+};
+
+
+static int pn8_fid_to_mult[64] = {
+	40, 45, 50, 55, 60, 65, 70, 75,
+	80, 85, 90, 95, 100, 105, 110, 115,
+	120, 125, 130, 135, 140, 145, 150, 155,
+	160, 165, 170, 175, 180, 185, 190, 195,
+	200, 205, 210, 215, 220, 225, 230, 235,
+	240, 245, 250, 255, 260, 265, 270, 275,
+	280, 285, 290, 295, 300, 305, 310, 315,
+	320, 325, 330, 335, 340, 345, 350, 355,
+};
+
+/*
+ * Units are in mV.
+ */
+/* Mobile VRM (K7) */
+static int pn7_mobile_vid_to_volts[] = {
+	2000, 1950, 1900, 1850, 1800, 1750, 1700, 1650,
+	1600, 1550, 1500, 1450, 1400, 1350, 1300, 0,
+	1275, 1250, 1225, 1200, 1175, 1150, 1125, 1100,
+	1075, 1050, 1025, 1000, 975, 950, 925, 0,
+};
+/* Desktop VRM (K7) */
+static int pn7_desktop_vid_to_volts[] = {
+	2000, 1950, 1900, 1850, 1800, 1750, 1700, 1650,
+	1600, 1550, 1500, 1450, 1400, 1350, 1300, 0,
+	1275, 1250, 1225, 1200, 1175, 1150, 1125, 1100,
+	1075, 1050, 1025, 1000, 975, 950, 925, 0,
+};
+/* Desktop and Mobile VRM (K8) */
+static int pn8_vid_to_volts[] = {
+	1550, 1525, 1500, 1475, 1450, 1425, 1400, 1375,
+	1350, 1325, 1300, 1275, 1250, 1225, 1200, 1175,
+	1150, 1125, 1100, 1075, 1050, 1025, 1000, 975,
+	950, 925, 900, 875, 850, 825, 800, 0,
+};
+
+#define POWERNOW_MAX_STATES		16
+
+struct powernow_state {
+	int freq;
+	int power;
+	int fid;
+	int vid;
+};
+
+struct pn_softc {
+	device_t		 dev;
+	int			 pn_type;
+	struct powernow_state	 powernow_states[POWERNOW_MAX_STATES];
+	u_int			 fsb;
+	u_int			 sgtc;
+	u_int			 vst;
+	u_int			 mvs;
+	u_int			 pll;
+	u_int			 rvo;
+	u_int			 irt;
+	int			 low;
+	int			 powernow_max_states;
+	u_int			 powernow_state;
+	u_int			 errata;
+	int			*vid_to_volts;
+};
+
+/*
+ * Offsets in struct cf_setting array for private values given by
+ * acpi_perf driver.
+ */
+#define PX_SPEC_CONTROL		0
+#define PX_SPEC_STATUS		1
+
+static void	pn_identify(driver_t *driver, device_t parent);
+static int	pn_probe(device_t dev);
+static int	pn_attach(device_t dev);
+static int	pn_detach(device_t dev);
+static int	pn_set(device_t dev, const struct cf_setting *cf);
+static int	pn_get(device_t dev, struct cf_setting *cf);
+static int	pn_settings(device_t dev, struct cf_setting *sets,
+		    int *count);
+static int	pn_type(device_t dev, int *type);
+
+static device_method_t pn_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_identify, pn_identify),
+	DEVMETHOD(device_probe, pn_probe),
+	DEVMETHOD(device_attach, pn_attach),
+	DEVMETHOD(device_detach, pn_detach),
+
+	/* cpufreq interface */
+	DEVMETHOD(cpufreq_drv_set, pn_set),
+	DEVMETHOD(cpufreq_drv_get, pn_get),
+	DEVMETHOD(cpufreq_drv_settings, pn_settings),
+	DEVMETHOD(cpufreq_drv_type, pn_type),
+
+	{0, 0}
+};
+
+static devclass_t pn_devclass;
+static driver_t pn_driver = {
+	"powernow",
+	pn_methods,
+	sizeof(struct pn_softc),
+};
+
+DRIVER_MODULE(powernow, cpu, pn_driver, pn_devclass, 0, 0);
+
+static int
+pn7_setfidvid(struct pn_softc *sc, int fid, int vid)
+{
+	int cfid, cvid;
+	uint64_t status, ctl;
+
+	status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
+	cfid = PN7_STA_CFID(status);
+	cvid = PN7_STA_CVID(status);
+
+	/* We're already at the requested level. */
+	if (fid == cfid && vid == cvid)
+		return (0);
+
+	ctl = rdmsr(MSR_AMDK7_FIDVID_CTL) & PN7_CTR_FIDCHRATIO;
+
+	ctl |= PN7_CTR_FID(fid);
+	ctl |= PN7_CTR_VID(vid);
+	ctl |= PN7_CTR_SGTC(sc->sgtc);
+
+	if (sc->errata & A0_ERRATA)
+		disable_intr();
+
+	if (pn7_fid_to_mult[fid] < pn7_fid_to_mult[cfid]) {
+		wrmsr(MSR_AMDK7_FIDVID_CTL, ctl | PN7_CTR_FIDC);
+		if (vid != cvid)
+			wrmsr(MSR_AMDK7_FIDVID_CTL, ctl | PN7_CTR_VIDC);
+	} else {
+		wrmsr(MSR_AMDK7_FIDVID_CTL, ctl | PN7_CTR_VIDC);
+		if (fid != cfid)
+			wrmsr(MSR_AMDK7_FIDVID_CTL, ctl | PN7_CTR_FIDC);
+	}
+
+	if (sc->errata & A0_ERRATA)
+		enable_intr();
+
+	return (0);
+}
+
+static int
+pn8_read_pending_wait(uint64_t *status)
+{
+	int i = 10000;
+
+	do
+		*status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
+	while (PN8_STA_PENDING(*status) && --i);
+
+	return (i == 0 ? ENXIO : 0);
+}
+
+static int
+pn8_write_fidvid(u_int fid, u_int vid, uint64_t ctrl, uint64_t *status)
+{
+	int i = 100;
+
+	do
+		WRITE_FIDVID(fid, vid, ctrl);
+	while (pn8_read_pending_wait(status) && --i);
+
+	return (i == 0 ? ENXIO : 0);
+}
+
+static int
+pn8_setfidvid(struct pn_softc *sc, int fid, int vid)
+{
+	uint64_t status;
+	int cfid, cvid;
+	int rvo;
+	int rv;
+	u_int val;
+
+	rv = pn8_read_pending_wait(&status);
+	if (rv)
+		return (rv);
+
+	cfid = PN8_STA_CFID(status);
+	cvid = PN8_STA_CVID(status);
+
+	if (fid == cfid && vid == cvid)
+		return (0);
+
+	/*
+	 * Phase 1: Raise core voltage to requested VID if frequency is
+	 * going up.
+	 */
+	while (cvid > vid) {
+		val = cvid - (1 << sc->mvs);
+		rv = pn8_write_fidvid(cfid, (val > 0) ? val : 0, 1ULL, &status);
+		if (rv) {
+			sc->errata |= PENDING_STUCK;
+			return (rv);
+		}
+		cvid = PN8_STA_CVID(status);
+		COUNT_OFF_VST(sc->vst);
+	}
+
+	/* ... then raise to voltage + RVO (if required) */
+	for (rvo = sc->rvo; rvo > 0 && cvid > 0; --rvo) {
+		/* XXX It's not clear from spec if we have to do that
+		 * in 0.25 step or in MVS.  Therefore do it as it's done
+		 * under Linux */
+		rv = pn8_write_fidvid(cfid, cvid - 1, 1ULL, &status);
+		if (rv) {
+			sc->errata |= PENDING_STUCK;
+			return (rv);
+		}
+		cvid = PN8_STA_CVID(status);
+		COUNT_OFF_VST(sc->vst);
+	}
+
+	/* Phase 2: change to requested core frequency */
+	if (cfid != fid) {
+		u_int vco_fid, vco_cfid, fid_delta;
+
+		vco_fid = FID_TO_VCO_FID(fid);
+		vco_cfid = FID_TO_VCO_FID(cfid);
+
+		while (abs(vco_fid - vco_cfid) > 2) {
+			fid_delta = (vco_cfid & 1) ? 1 : 2;
+			if (fid > cfid) {
+				if (cfid > 7)
+					val = cfid + fid_delta;
+				else
+					val = FID_TO_VCO_FID(cfid) + fid_delta;
+			} else
+				val = cfid - fid_delta;
+			rv = pn8_write_fidvid(val, cvid,
+			    sc->pll * (uint64_t) sc->fsb,
+			    &status);
+			if (rv) {
+				sc->errata |= PENDING_STUCK;
+				return (rv);
+			}
+			cfid = PN8_STA_CFID(status);
+			COUNT_OFF_IRT(sc->irt);
+
+			vco_cfid = FID_TO_VCO_FID(cfid);
+		}
+
+		rv = pn8_write_fidvid(fid, cvid,
+		    sc->pll * (uint64_t) sc->fsb,
+		    &status);
+		if (rv) {
+			sc->errata |= PENDING_STUCK;
+			return (rv);
+		}
+		cfid = PN8_STA_CFID(status);
+		COUNT_OFF_IRT(sc->irt);
+	}
+
+	/* Phase 3: change to requested voltage */
+	if (cvid != vid) {
+		rv = pn8_write_fidvid(cfid, vid, 1ULL, &status);
+		cvid = PN8_STA_CVID(status);
+		COUNT_OFF_VST(sc->vst);
+	}
+
+	/* Check if transition failed. */
+	if (cfid != fid || cvid != vid)
+		rv = ENXIO;
+
+	return (rv);
+}
+
+static int
+pn_set(device_t dev, const struct cf_setting *cf)
+{
+	struct pn_softc *sc;
+	int fid, vid;
+	int i;
+	int rv;
+
+	if (cf == NULL)
+		return (EINVAL);
+	sc = device_get_softc(dev);
+
+	if (sc->errata & PENDING_STUCK)
+		return (ENXIO);
+
+	for (i = 0; i < sc->powernow_max_states; ++i)
+		if (CPUFREQ_CMP(sc->powernow_states[i].freq / 1000, cf->freq))
+			break;
+
+	fid = sc->powernow_states[i].fid;
+	vid = sc->powernow_states[i].vid;
+
+	rv = ENODEV;
+
+	switch (sc->pn_type) {
+	case PN7_TYPE:
+		rv = pn7_setfidvid(sc, fid, vid);
+		break;
+	case PN8_TYPE:
+		rv = pn8_setfidvid(sc, fid, vid);
+		break;
+	}
+
+	return (rv);
+}
+
+static int
+pn_get(device_t dev, struct cf_setting *cf)
+{
+	struct pn_softc *sc;
+	u_int cfid = 0, cvid = 0;
+	int i;
+	uint64_t status;
+
+	if (cf == NULL)
+		return (EINVAL);
+	sc = device_get_softc(dev);
+	if (sc->errata & PENDING_STUCK)
+		return (ENXIO);
+
+	status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
+
+	switch (sc->pn_type) {
+	case PN7_TYPE:
+		cfid = PN7_STA_CFID(status);
+		cvid = PN7_STA_CVID(status);
+		break;
+	case PN8_TYPE:
+		cfid = PN8_STA_CFID(status);
+		cvid = PN8_STA_CVID(status);
+		break;
+	}
+	for (i = 0; i < sc->powernow_max_states; ++i)
+		if (cfid == sc->powernow_states[i].fid &&
+		    cvid == sc->powernow_states[i].vid)
+			break;
+
+	if (i < sc->powernow_max_states) {
+		cf->freq = sc->powernow_states[i].freq / 1000;
+		cf->power = sc->powernow_states[i].power;
+		cf->lat = 200;
+		cf->volts = sc->vid_to_volts[cvid];
+		cf->dev = dev;
+	} else {
+		memset(cf, CPUFREQ_VAL_UNKNOWN, sizeof(*cf));
+		cf->dev = NULL;
+	}
+
+	return (0);
+}
+
+static int
+pn_settings(device_t dev, struct cf_setting *sets, int *count)
+{
+	struct pn_softc *sc;
+	int i;
+
+	if (sets == NULL|| count == NULL)
+		return (EINVAL);
+	sc = device_get_softc(dev);
+	if (*count < sc->powernow_max_states)
+		return (E2BIG);
+	for (i = 0; i < sc->powernow_max_states; ++i) {
+		sets[i].freq = sc->powernow_states[i].freq / 1000;
+		sets[i].power = sc->powernow_states[i].power;
+		sets[i].lat = 200;
+		sets[i].volts = sc->vid_to_volts[sc->powernow_states[i].vid];
+		sets[i].dev = dev;
+	}
+	*count = sc->powernow_max_states;
+
+	return (0);
+}
+
+static int
+pn_type(device_t dev, int *type)
+{
+	if (type == NULL)
+		return (EINVAL);
+
+	*type = CPUFREQ_TYPE_ABSOLUTE;
+
+	return (0);
+}
+
+/*
+ * Given a set of pair of fid/vid, and number of performance states,
+ * compute powernow_states via an insertion sort.
+ */
+static int
+decode_pst(struct pn_softc *sc, uint8_t *p, int npstates)
+{
+	int i, j, n;
+	struct powernow_state state;
+
+	for (i = 0; i < POWERNOW_MAX_STATES; ++i)
+		sc->powernow_states[i].freq = CPUFREQ_VAL_UNKNOWN;
+
+	for (n = 0, i = 0; i < npstates; ++i) {
+		state.fid = *p++;
+		state.vid = *p++;
+		state.power = CPUFREQ_VAL_UNKNOWN;
+
+		switch (sc->pn_type) {
+		case PN7_TYPE:
+			state.freq = 100 * pn7_fid_to_mult[state.fid] * sc->fsb;
+			if ((sc->errata & A0_ERRATA) &&
+			    (pn7_fid_to_mult[state.fid] % 10) == 5)
+				continue;
+			break;
+		case PN8_TYPE:
+			state.freq = 100 * pn8_fid_to_mult[state.fid] * sc->fsb;
+			break;
+		}
+
+		j = n;
+		while (j > 0 && sc->powernow_states[j - 1].freq < state.freq) {
+			memcpy(&sc->powernow_states[j],
+			    &sc->powernow_states[j - 1],
+			    sizeof(struct powernow_state));
+			--j;
+		}
+		memcpy(&sc->powernow_states[j], &state,
+		    sizeof(struct powernow_state));
+		++n;
+	}
+
+	/*
+	 * Fix powernow_max_states, if errata a0 give us less states
+	 * than expected.
+	 */
+	sc->powernow_max_states = n;
+
+	if (bootverbose)
+		for (i = 0; i < sc->powernow_max_states; ++i) {
+			int fid = sc->powernow_states[i].fid;
+			int vid = sc->powernow_states[i].vid;
+
+			printf("powernow: %2i %8dkHz FID %02x VID %02x\n",
+			    i,
+			    sc->powernow_states[i].freq,
+			    fid,
+			    vid);
+		}
+
+	return (0);
+}
+
+static int
+cpuid_is_k7(u_int cpuid)
+{
+
+	switch (cpuid) {
+	case 0x760:
+	case 0x761:
+	case 0x762:
+	case 0x770:
+	case 0x771:
+	case 0x780:
+	case 0x781:
+	case 0x7a0:
+		return (TRUE);
+	}
+	return (FALSE);
+}
+
+static int
+pn_decode_pst(device_t dev)
+{
+	int maxpst;
+	struct pn_softc *sc;
+	u_int cpuid, maxfid, startvid;
+	u_long sig;
+	struct psb_header *psb;
+	uint8_t *p;
+	u_int regs[4];
+	uint64_t status;
+
+	sc = device_get_softc(dev);
+
+	do_cpuid(0x80000001, regs);
+	cpuid = regs[0];
+
+	if ((cpuid & 0xfff) == 0x760)
+		sc->errata |= A0_ERRATA;
+
+	status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
+
+	switch (sc->pn_type) {
+	case PN7_TYPE:
+		maxfid = PN7_STA_MFID(status);
+		startvid = PN7_STA_SVID(status);
+		break;
+	case PN8_TYPE:
+		maxfid = PN8_STA_MFID(status);
+		/*
+		 * we should actually use a variable named 'maxvid' if K8,
+		 * but why introducing a new variable for that?
+		 */
+		startvid = PN8_STA_MVID(status);
+		break;
+	default:
+		return (ENODEV);
+	}
+
+	if (bootverbose) {
+		device_printf(dev, "STATUS: 0x%jx\n", status);
+		device_printf(dev, "STATUS: maxfid: 0x%02x\n", maxfid);
+		device_printf(dev, "STATUS: %s: 0x%02x\n",
+		    sc->pn_type == PN7_TYPE ? "startvid" : "maxvid",
+		    startvid);
+	}
+
+	sig = bios_sigsearch(PSB_START, PSB_SIG, PSB_LEN, PSB_STEP, PSB_OFF);
+	if (sig) {
+		struct pst_header *pst;
+
+		psb = (struct psb_header*)(uintptr_t)BIOS_PADDRTOVADDR(sig);
+
+		switch (psb->version) {
+		default:
+			return (ENODEV);
+		case 0x14:
+			/*
+			 * We can't be picky about numpst since at least
+			 * some systems have a value of 1 and some have 2.
+			 * We trust that cpuid_is_k7() will be better at
+			 * catching that we're on a K8 anyway.
+			 */
+			if (sc->pn_type != PN8_TYPE)
+				return (EINVAL);
+			sc->vst = psb->settlingtime;
+			sc->rvo = PN8_PSB_TO_RVO(psb->res1),
+			sc->irt = PN8_PSB_TO_IRT(psb->res1),
+			sc->mvs = PN8_PSB_TO_MVS(psb->res1),
+			sc->low = PN8_PSB_TO_BATT(psb->res1);
+			if (bootverbose) {
+				device_printf(dev, "PSB: VST: %d\n",
+				    psb->settlingtime);
+				device_printf(dev, "PSB: RVO %x IRT %d "
+				    "MVS %d BATT %d\n",
+				    sc->rvo,
+				    sc->irt,
+				    sc->mvs,
+				    sc->low);
+			}
+			break;
+		case 0x12:
+			if (sc->pn_type != PN7_TYPE)
+				return (EINVAL);
+			sc->sgtc = psb->settlingtime * sc->fsb;
+			if (sc->sgtc < 100 * sc->fsb)
+				sc->sgtc = 100 * sc->fsb;
+			break;
+		}
+
+		p = ((uint8_t *) psb) + sizeof(struct psb_header);
+		pst = (struct pst_header*) p;
+
+		maxpst = 200;
+
+		do {
+			struct pst_header *pst = (struct pst_header*) p;
+
+			if (cpuid == pst->cpuid &&
+			    maxfid == pst->maxfid &&
+			    startvid == pst->startvid) {
+				sc->powernow_max_states = pst->numpstates;
+				switch (sc->pn_type) {
+				case PN7_TYPE:
+					if (abs(sc->fsb - pst->fsb) > 5)
+						continue;
+					break;
+				case PN8_TYPE:
+					break;
+				}
+				return (decode_pst(sc,
+				    p + sizeof(struct pst_header),
+				    sc->powernow_max_states));
+			}
+
+			p += sizeof(struct pst_header) + (2 * pst->numpstates);
+		} while (cpuid_is_k7(pst->cpuid) && maxpst--);
+
+		device_printf(dev, "no match for extended cpuid %.3x\n", cpuid);
+	}
+
+	return (ENODEV);
+}
+
+static int
+pn_decode_acpi(device_t dev, device_t perf_dev)
+{
+	int i, j, n;
+	uint64_t status;
+	uint32_t ctrl;
+	u_int cpuid;
+	u_int regs[4];
+	struct pn_softc *sc;
+	struct powernow_state state;
+	struct cf_setting sets[POWERNOW_MAX_STATES];
+	int count = POWERNOW_MAX_STATES;
+	int type;
+	int rv;
+
+	if (perf_dev == NULL)
+		return (ENXIO);
+
+	rv = CPUFREQ_DRV_SETTINGS(perf_dev, sets, &count);
+	if (rv)
+		return (ENXIO);
+	rv = CPUFREQ_DRV_TYPE(perf_dev, &type);
+	if (rv || (type & CPUFREQ_FLAG_INFO_ONLY) == 0)
+		return (ENXIO);
+
+	sc = device_get_softc(dev);
+
+	do_cpuid(0x80000001, regs);
+	cpuid = regs[0];
+	if ((cpuid & 0xfff) == 0x760)
+		sc->errata |= A0_ERRATA;
+
+	ctrl = 0;
+	sc->sgtc = 0;
+	for (n = 0, i = 0; i < count; ++i) {
+		ctrl = sets[i].spec[PX_SPEC_CONTROL];
+		switch (sc->pn_type) {
+		case PN7_TYPE:
+			state.fid = ACPI_PN7_CTRL_TO_FID(ctrl);
+			state.vid = ACPI_PN7_CTRL_TO_VID(ctrl);
+			if ((sc->errata & A0_ERRATA) &&
+			    (pn7_fid_to_mult[state.fid] % 10) == 5)
+				continue;
+			state.freq = 100 * pn7_fid_to_mult[state.fid] * sc->fsb;
+			break;
+		case PN8_TYPE:
+			state.fid = ACPI_PN8_CTRL_TO_FID(ctrl);
+			state.vid = ACPI_PN8_CTRL_TO_VID(ctrl);
+			state.freq = 100 * pn8_fid_to_mult[state.fid] * sc->fsb;
+			break;
+		}
+
+		state.power = sets[i].power;
+
+		j = n;
+		while (j > 0 && sc->powernow_states[j - 1].freq < state.freq) {
+			memcpy(&sc->powernow_states[j],
+			    &sc->powernow_states[j - 1],
+			    sizeof(struct powernow_state));
+			--j;
+		}
+		memcpy(&sc->powernow_states[j], &state,
+		    sizeof(struct powernow_state));
+		++n;
+	}
+
+	sc->powernow_max_states = n;
+	state = sc->powernow_states[0];
+	status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
+
+	switch (sc->pn_type) {
+	case PN7_TYPE:
+		sc->sgtc = ACPI_PN7_CTRL_TO_SGTC(ctrl);
+		/*
+		 * XXX Some bios forget the max frequency!
+		 * This maybe indicates we have the wrong tables.  Therefore,
+		 * don't implement a quirk, but fallback to BIOS legacy
+		 * tables instead.
+		 */
+		if (PN7_STA_MFID(status) != state.fid) {
+			device_printf(dev, "ACPI MAX frequency not found\n");
+			return (EINVAL);
+		}
+		break;
+	case PN8_TYPE:
+		sc->vst = ACPI_PN8_CTRL_TO_VST(ctrl),
+		sc->mvs = ACPI_PN8_CTRL_TO_MVS(ctrl),
+		sc->pll = ACPI_PN8_CTRL_TO_PLL(ctrl),
+		sc->rvo = ACPI_PN8_CTRL_TO_RVO(ctrl),
+		sc->irt = ACPI_PN8_CTRL_TO_IRT(ctrl);
+		sc->low = 0; /* XXX */
+
+		/*
+		 * powernow k8 supports only one low frequency.
+		 */
+		if (sc->powernow_max_states >= 2 &&
+		    (sc->powernow_states[sc->powernow_max_states - 2].fid < 8))
+			return (EINVAL);
+		break;
+	}
+
+	return (0);
+}
+
+static void
+pn_identify(driver_t *driver, device_t parent)
+{
+
+	if ((amd_pminfo & AMDPM_FID) == 0 || (amd_pminfo & AMDPM_VID) == 0)
+		return;
+	switch (cpu_id & 0xf00) {
+	case 0x600:
+	case 0xf00:
+		break;
+	default:
+		return;
+	}
+	if (device_find_child(parent, "powernow", -1) != NULL)
+		return;
+	if (BUS_ADD_CHILD(parent, 10, "powernow", -1) == NULL)
+		device_printf(parent, "powernow: add child failed\n");
+}
+
+static int
+pn_probe(device_t dev)
+{
+	struct pn_softc *sc;
+	uint64_t status;
+	uint64_t rate;
+	struct pcpu *pc;
+	u_int sfid, mfid, cfid;
+
+	sc = device_get_softc(dev);
+	sc->errata = 0;
+	status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
+
+	pc = cpu_get_pcpu(dev);
+	if (pc == NULL)
+		return (ENODEV);
+
+	cpu_est_clockrate(pc->pc_cpuid, &rate);
+
+	switch (cpu_id & 0xf00) {
+	case 0x600:
+		sfid = PN7_STA_SFID(status);
+		mfid = PN7_STA_MFID(status);
+		cfid = PN7_STA_CFID(status);
+		sc->pn_type = PN7_TYPE;
+		sc->fsb = rate / 100000 / pn7_fid_to_mult[cfid];
+
+		/*
+		 * If start FID is different to max FID, then it is a
+		 * mobile processor.  If not, it is a low powered desktop
+		 * processor.
+		 */
+		if (PN7_STA_SFID(status) != PN7_STA_MFID(status)) {
+			sc->vid_to_volts = pn7_mobile_vid_to_volts;
+			device_set_desc(dev, "PowerNow! K7");
+		} else {
+			sc->vid_to_volts = pn7_desktop_vid_to_volts;
+			device_set_desc(dev, "Cool`n'Quiet K7");
+		}
+		break;
+
+	case 0xf00:
+		sfid = PN8_STA_SFID(status);
+		mfid = PN8_STA_MFID(status);
+		cfid = PN8_STA_CFID(status);
+		sc->pn_type = PN8_TYPE;
+		sc->vid_to_volts = pn8_vid_to_volts;
+		sc->fsb = rate / 100000 / pn8_fid_to_mult[cfid];
+
+		if (PN8_STA_SFID(status) != PN8_STA_MFID(status))
+			device_set_desc(dev, "PowerNow! K8");
+		else
+			device_set_desc(dev, "Cool`n'Quiet K8");
+		break;
+	default:
+		return (ENODEV);
+	}
+
+	return (0);
+}
+
+static int
+pn_attach(device_t dev)
+{
+	int rv;
+	device_t child;
+
+	child = device_find_child(device_get_parent(dev), "acpi_perf", -1);
+	if (child) {
+		rv = pn_decode_acpi(dev, child);
+		if (rv)
+			rv = pn_decode_pst(dev);
+	} else
+		rv = pn_decode_pst(dev);
+
+	if (rv != 0)
+		return (ENXIO);
+	cpufreq_register(dev);
+	return (0);
+}
+
+static int
+pn_detach(device_t dev)
+{
+
+	return (cpufreq_unregister(dev));
+}
diff --git a/sys/x86/cpufreq/smist.c b/sys/x86/cpufreq/smist.c
new file mode 100644
index 0000000..5cfd72b
--- /dev/null
+++ b/sys/x86/cpufreq/smist.c
@@ -0,0 +1,514 @@
+/*-
+ * Copyright (c) 2005 Bruno Ducrot
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This driver is based upon information found by examining speedstep-0.5
+ * from Marc Lehman, which includes all the reverse engineering effort of
+ * Malik Martin (function 1 and 2 of the GSI).
+ *
+ * The correct way for the OS to take ownership from the BIOS was found by
+ * Hiroshi Miura (function 0 of the GSI).
+ *
+ * Finally, the int 15h call interface was (partially) documented by Intel.
+ *
+ * Many thanks to Jon Noack for testing and debugging this driver.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/systm.h>
+
+#include <machine/bus.h>
+#include <machine/cputypes.h>
+#include <machine/md_var.h>
+#include <machine/vm86.h>
+
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcireg.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+
+#include "cpufreq_if.h"
+
+#if 0
+#define DPRINT(dev, x...)	device_printf(dev, x)
+#else
+#define DPRINT(dev, x...)
+#endif
+
+struct smist_softc {
+	device_t		 dev;
+	int			 smi_cmd;
+	int			 smi_data;
+	int			 command;
+	int			 flags;
+	struct cf_setting	 sets[2];	/* Only two settings. */
+};
+
+static char smist_magic[] = "Copyright (c) 1999 Intel Corporation";
+
+static void	smist_identify(driver_t *driver, device_t parent);
+static int	smist_probe(device_t dev);
+static int	smist_attach(device_t dev);
+static int	smist_detach(device_t dev);
+static int	smist_settings(device_t dev, struct cf_setting *sets,
+		    int *count);
+static int	smist_set(device_t dev, const struct cf_setting *set);
+static int	smist_get(device_t dev, struct cf_setting *set);
+static int	smist_type(device_t dev, int *type);
+
+static device_method_t smist_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_identify,	smist_identify),
+	DEVMETHOD(device_probe,		smist_probe),
+	DEVMETHOD(device_attach,	smist_attach),
+	DEVMETHOD(device_detach,	smist_detach),
+
+	/* cpufreq interface */
+	DEVMETHOD(cpufreq_drv_set,	smist_set),
+	DEVMETHOD(cpufreq_drv_get,	smist_get),
+	DEVMETHOD(cpufreq_drv_type,	smist_type),
+	DEVMETHOD(cpufreq_drv_settings,	smist_settings),
+
+	{0, 0}
+};
+
+static driver_t smist_driver = {
+	"smist", smist_methods, sizeof(struct smist_softc)
+};
+static devclass_t smist_devclass;
+DRIVER_MODULE(smist, cpu, smist_driver, smist_devclass, 0, 0);
+
+struct piix4_pci_device {
+	uint16_t		 vendor;
+	uint16_t		 device;
+	char			*desc;
+};
+
+static struct piix4_pci_device piix4_pci_devices[] = {
+	{0x8086, 0x7113, "Intel PIIX4 ISA bridge"},
+	{0x8086, 0x719b, "Intel PIIX4 ISA bridge (embedded in MX440 chipset)"},
+
+	{0, 0, NULL},
+};
+
+#define SET_OWNERSHIP		0
+#define GET_STATE		1
+#define SET_STATE		2
+
+static int
+int15_gsic_call(int *sig, int *smi_cmd, int *command, int *smi_data, int *flags)
+{
+	struct vm86frame vmf;
+
+	bzero(&vmf, sizeof(vmf));
+	vmf.vmf_eax = 0x0000E980;	/* IST support */
+	vmf.vmf_edx = 0x47534943;	/* 'GSIC' in ASCII */
+	vm86_intcall(0x15, &vmf);
+
+	if (vmf.vmf_eax == 0x47534943) {
+		*sig = vmf.vmf_eax;
+		*smi_cmd = vmf.vmf_ebx & 0xff;
+		*command = (vmf.vmf_ebx >> 16) & 0xff;
+		*smi_data = vmf.vmf_ecx;
+		*flags = vmf.vmf_edx;
+	} else {
+		*sig = -1;
+		*smi_cmd = -1;
+		*command = -1;
+		*smi_data = -1;
+		*flags = -1;
+	}
+
+	return (0);
+}
+
+/* Temporary structure to hold mapped page and status. */
+struct set_ownership_data {
+	int	smi_cmd;
+	int	command;
+	int	result;
+	void	*buf;
+};
+
+/* Perform actual SMI call to enable SpeedStep. */
+static void
+set_ownership_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
+{
+	struct set_ownership_data *data;
+
+	data = arg;
+	if (error) {
+		data->result = error;
+		return;
+	}
+
+	/* Copy in the magic string and send it by writing to the SMI port. */
+	strlcpy(data->buf, smist_magic, PAGE_SIZE);
+	__asm __volatile(
+	    "movl $-1, %%edi\n\t"
+	    "out %%al, (%%dx)\n"
+	    : "=D" (data->result)
+	    : "a" (data->command),
+	      "b" (0),
+	      "c" (0),
+	      "d" (data->smi_cmd),
+	      "S" ((uint32_t)segs[0].ds_addr)
+	);
+}
+
+static int
+set_ownership(device_t dev)
+{
+	struct smist_softc *sc;
+	struct set_ownership_data cb_data;
+	bus_dma_tag_t tag;
+	bus_dmamap_t map;
+
+	/*
+	 * Specify the region to store the magic string.  Since its address is
+	 * passed to the BIOS in a 32-bit register, we have to make sure it is
+	 * located in a physical page below 4 GB (i.e., for PAE.)
+	 */
+	sc = device_get_softc(dev);
+	if (bus_dma_tag_create(/*parent*/ NULL,
+	    /*alignment*/ PAGE_SIZE, /*no boundary*/ 0,
+	    /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, /*highaddr*/ BUS_SPACE_MAXADDR,
+	    NULL, NULL, /*maxsize*/ PAGE_SIZE, /*segments*/ 1,
+	    /*maxsegsize*/ PAGE_SIZE, 0, busdma_lock_mutex, &Giant,
+	    &tag) != 0) {
+		device_printf(dev, "can't create mem tag\n");
+		return (ENXIO);
+	}
+	if (bus_dmamem_alloc(tag, &cb_data.buf, BUS_DMA_NOWAIT, &map) != 0) {
+		bus_dma_tag_destroy(tag);
+		device_printf(dev, "can't alloc mapped mem\n");
+		return (ENXIO);
+	}
+
+	/* Load the physical page map and take ownership in the callback. */
+	cb_data.smi_cmd = sc->smi_cmd;
+	cb_data.command = sc->command;
+	if (bus_dmamap_load(tag, map, cb_data.buf, PAGE_SIZE, set_ownership_cb,
+	    &cb_data, BUS_DMA_NOWAIT) != 0) {
+		bus_dmamem_free(tag, cb_data.buf, map);
+		bus_dma_tag_destroy(tag);
+		device_printf(dev, "can't load mem\n");
+		return (ENXIO);
+	};
+	DPRINT(dev, "taking ownership over BIOS return %d\n", cb_data.result);
+	bus_dmamap_unload(tag, map);
+	bus_dmamem_free(tag, cb_data.buf, map);
+	bus_dma_tag_destroy(tag);
+	return (cb_data.result ? ENXIO : 0);
+}
+
+static int
+getset_state(struct smist_softc *sc, int *state, int function)
+{
+	int new_state;
+	int result;
+	int eax;
+
+	if (!sc)
+		return (ENXIO);
+
+	if (function != GET_STATE && function != SET_STATE)
+		return (EINVAL);
+
+	DPRINT(sc->dev, "calling GSI\n");
+
+	__asm __volatile(
+	     "movl $-1, %%edi\n\t"
+	     "out %%al, (%%dx)\n"
+	   : "=a" (eax),
+	     "=b" (new_state),
+	     "=D" (result)
+	   : "a" (sc->command),
+	     "b" (function),
+	     "c" (*state),
+	     "d" (sc->smi_cmd)
+	);
+
+	DPRINT(sc->dev, "GSI returned: eax %.8x ebx %.8x edi %.8x\n",
+	    eax, new_state, result);
+
+	*state = new_state & 1;
+
+	switch (function) {
+	case GET_STATE:
+		if (eax)
+			return (ENXIO);
+		break;
+	case SET_STATE:
+		if (result)
+			return (ENXIO);
+		break;
+	}
+	return (0);
+}
+
+static void
+smist_identify(driver_t *driver, device_t parent)
+{
+	struct piix4_pci_device *id;
+	device_t piix4 = NULL;
+
+	if (resource_disabled("ichst", 0))
+		return;
+
+	/* Check for a supported processor */
+	if (cpu_vendor_id != CPU_VENDOR_INTEL)
+		return;
+	switch (cpu_id & 0xff0) {
+	case 0x680:	/* Pentium III [coppermine] */
+	case 0x6a0:	/* Pentium III [Tualatin] */
+		break;
+	default:
+		return;
+	}
+
+	/* Check for a supported PCI-ISA bridge */
+	for (id = piix4_pci_devices; id->desc != NULL; ++id) {
+		if ((piix4 = pci_find_device(id->vendor, id->device)) != NULL)
+			break;
+	}
+	if (!piix4)
+		return;
+
+	if (bootverbose)
+		printf("smist: found supported isa bridge %s\n", id->desc);
+
+	if (device_find_child(parent, "smist", -1) != NULL)
+		return;
+	if (BUS_ADD_CHILD(parent, 30, "smist", -1) == NULL)
+		device_printf(parent, "smist: add child failed\n");
+}
+
+static int
+smist_probe(device_t dev)
+{
+	struct smist_softc *sc;
+	device_t ichss_dev, perf_dev;
+	int sig, smi_cmd, command, smi_data, flags;
+	int type;
+	int rv;
+
+	if (resource_disabled("smist", 0))
+		return (ENXIO);
+
+	sc = device_get_softc(dev);
+
+	/*
+	 * If the ACPI perf or ICH SpeedStep drivers have attached and not
+	 * just offering info, let them manage things.
+	 */
+	perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
+	if (perf_dev && device_is_attached(perf_dev)) {
+		rv = CPUFREQ_DRV_TYPE(perf_dev, &type);
+		if (rv == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0)
+			return (ENXIO);
+	}
+	ichss_dev = device_find_child(device_get_parent(dev), "ichss", -1);
+	if (ichss_dev && device_is_attached(ichss_dev))
+		return (ENXIO);
+
+	int15_gsic_call(&sig, &smi_cmd, &command, &smi_data, &flags);
+	if (bootverbose)
+		device_printf(dev, "sig %.8x smi_cmd %.4x command %.2x "
+		    "smi_data %.4x flags %.8x\n",
+		    sig, smi_cmd, command, smi_data, flags);
+
+	if (sig != -1) {
+		sc->smi_cmd = smi_cmd;
+		sc->smi_data = smi_data;
+
+		/*
+		 * Sometimes int 15h 'GSIC' returns 0x80 for command, when
+		 * it is actually 0x82.  The Windows driver will overwrite
+		 * this value given by the registry.
+		 */
+		if (command == 0x80) {
+			device_printf(dev,
+			    "GSIC returned cmd 0x80, should be 0x82\n");
+			command = 0x82;
+		}
+		sc->command = (sig & 0xffffff00) | (command & 0xff);
+		sc->flags = flags;
+	} else {
+		/* Give some default values */
+		sc->smi_cmd = 0xb2;
+		sc->smi_data = 0xb3;
+		sc->command = 0x47534982;
+		sc->flags = 0;
+	}
+
+	device_set_desc(dev, "SpeedStep SMI");
+
+	return (-1500);
+}
+
+static int
+smist_attach(device_t dev)
+{
+	struct smist_softc *sc;
+
+	sc = device_get_softc(dev);
+	sc->dev = dev;
+
+	/* If we can't take ownership over BIOS, then bail out */
+	if (set_ownership(dev) != 0)
+		return (ENXIO);
+
+	/* Setup some defaults for our exported settings. */
+	sc->sets[0].freq = CPUFREQ_VAL_UNKNOWN;
+	sc->sets[0].volts = CPUFREQ_VAL_UNKNOWN;
+	sc->sets[0].power = CPUFREQ_VAL_UNKNOWN;
+	sc->sets[0].lat = 1000;
+	sc->sets[0].dev = dev;
+	sc->sets[1] = sc->sets[0];
+
+	cpufreq_register(dev);
+
+	return (0);
+}
+
+static int
+smist_detach(device_t dev)
+{
+
+	return (cpufreq_unregister(dev));
+}
+
+static int
+smist_settings(device_t dev, struct cf_setting *sets, int *count)
+{
+	struct smist_softc *sc;
+	struct cf_setting set;
+	int first, i;
+
+	if (sets == NULL || count == NULL)
+		return (EINVAL);
+	if (*count < 2) {
+		*count = 2;
+		return (E2BIG);
+	}
+	sc = device_get_softc(dev);
+
+	/*
+	 * Estimate frequencies for both levels, temporarily switching to
+	 * the other one if we haven't calibrated it yet.
+	 */
+	for (i = 0; i < 2; i++) {
+		if (sc->sets[i].freq == CPUFREQ_VAL_UNKNOWN) {
+			first = (i == 0) ? 1 : 0;
+			smist_set(dev, &sc->sets[i]);
+			smist_get(dev, &set);
+			smist_set(dev, &sc->sets[first]);
+		}
+	}
+
+	bcopy(sc->sets, sets, sizeof(sc->sets));
+	*count = 2;
+
+	return (0);
+}
+
+static int
+smist_set(device_t dev, const struct cf_setting *set)
+{
+	struct smist_softc *sc;
+	int rv, state, req_state, try;
+
+	/* Look up appropriate bit value based on frequency. */
+	sc = device_get_softc(dev);
+	if (CPUFREQ_CMP(set->freq, sc->sets[0].freq))
+		req_state = 0;
+	else if (CPUFREQ_CMP(set->freq, sc->sets[1].freq))
+		req_state = 1;
+	else
+		return (EINVAL);
+
+	DPRINT(dev, "requested setting %d\n", req_state);
+
+	rv = getset_state(sc, &state, GET_STATE);
+	if (state == req_state)
+		return (0);
+
+	try = 3;
+	do {
+		rv = getset_state(sc, &req_state, SET_STATE);
+
+		/* Sleep for 200 microseconds.  This value is just a guess. */
+		if (rv)
+			DELAY(200);
+	} while (rv && --try);
+	DPRINT(dev, "set_state return %d, tried %d times\n",
+	    rv, 4 - try);
+
+	return (rv);
+}
+
+static int
+smist_get(device_t dev, struct cf_setting *set)
+{
+	struct smist_softc *sc;
+	uint64_t rate;
+	int state;
+	int rv;
+
+	sc = device_get_softc(dev);
+	rv = getset_state(sc, &state, GET_STATE);
+	if (rv != 0)
+		return (rv);
+
+	/* If we haven't changed settings yet, estimate the current value. */
+	if (sc->sets[state].freq == CPUFREQ_VAL_UNKNOWN) {
+		cpu_est_clockrate(0, &rate);
+		sc->sets[state].freq = rate / 1000000;
+		DPRINT(dev, "get calibrated new rate of %d\n",
+		    sc->sets[state].freq);
+	}
+	*set = sc->sets[state];
+
+	return (0);
+}
+
+static int
+smist_type(device_t dev, int *type)
+{
+
+	if (type == NULL)
+		return (EINVAL);
+
+	*type = CPUFREQ_TYPE_ABSOLUTE;
+	return (0);
+}
diff --git a/sys/x86/isa/atpic.c b/sys/x86/isa/atpic.c
new file mode 100644
index 0000000..d17153c
--- /dev/null
+++ b/sys/x86/isa/atpic.c
@@ -0,0 +1,686 @@
+/*-
+ * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * PIC driver for the 8259A Master and Slave PICs in PC/AT machines.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include "opt_auto_eoi.h"
+#include "opt_isa.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/interrupt.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/module.h>
+
+#include <machine/cpufunc.h>
+#include <machine/frame.h>
+#include <machine/intr_machdep.h>
+#include <machine/md_var.h>
+#include <machine/resource.h>
+#include <machine/segments.h>
+
+#include <dev/ic/i8259.h>
+#include <x86/isa/icu.h>
+#ifdef PC98
+#include <pc98/cbus/cbus.h>
+#else
+#include <x86/isa/isa.h>
+#endif
+#include <isa/isavar.h>
+
+#ifdef __amd64__
+#define	SDT_ATPIC	SDT_SYSIGT
+#define	GSEL_ATPIC	0
+#else
+#define	SDT_ATPIC	SDT_SYS386IGT
+#define	GSEL_ATPIC	GSEL(GCODE_SEL, SEL_KPL)
+#endif
+
+#define	MASTER	0
+#define	SLAVE	1
+
+/*
+ * PC-98 machines wire the slave 8259A to pin 7 on the master PIC, and
+ * PC-AT machines wire the slave PIC to pin 2 on the master PIC.
+ */
+#ifdef PC98
+#define	ICU_SLAVEID	7
+#else
+#define	ICU_SLAVEID	2
+#endif
+
+/*
+ * Determine the base master and slave modes not including auto EOI support.
+ * All machines that FreeBSD supports use 8086 mode.
+ */
+#ifdef PC98
+/*
+ * PC-98 machines do not support auto EOI on the second PIC.  Also, it
+ * seems that PC-98 machine PICs use buffered mode, and the master PIC
+ * uses special fully nested mode.
+ */
+#define	BASE_MASTER_MODE	(ICW4_SFNM | ICW4_BUF | ICW4_MS | ICW4_8086)
+#define	BASE_SLAVE_MODE		(ICW4_BUF | ICW4_8086)
+#else
+#define	BASE_MASTER_MODE	ICW4_8086
+#define	BASE_SLAVE_MODE		ICW4_8086
+#endif
+
+/* Enable automatic EOI if requested. */
+#ifdef AUTO_EOI_1
+#define	MASTER_MODE		(BASE_MASTER_MODE | ICW4_AEOI)
+#else
+#define	MASTER_MODE		BASE_MASTER_MODE
+#endif
+#ifdef AUTO_EOI_2
+#define	SLAVE_MODE		(BASE_SLAVE_MODE | ICW4_AEOI)
+#else
+#define	SLAVE_MODE		BASE_SLAVE_MODE
+#endif
+
+#define	IRQ_MASK(irq)		(1 << (irq))
+#define	IMEN_MASK(ai)		(IRQ_MASK((ai)->at_irq))
+
+#define	NUM_ISA_IRQS		16
+
+static void	atpic_init(void *dummy);
+
+unsigned int imen;	/* XXX */
+
+inthand_t
+	IDTVEC(atpic_intr0), IDTVEC(atpic_intr1), IDTVEC(atpic_intr2),
+	IDTVEC(atpic_intr3), IDTVEC(atpic_intr4), IDTVEC(atpic_intr5),
+	IDTVEC(atpic_intr6), IDTVEC(atpic_intr7), IDTVEC(atpic_intr8),
+	IDTVEC(atpic_intr9), IDTVEC(atpic_intr10), IDTVEC(atpic_intr11),
+	IDTVEC(atpic_intr12), IDTVEC(atpic_intr13), IDTVEC(atpic_intr14),
+	IDTVEC(atpic_intr15);
+
+#define	IRQ(ap, ai)	((ap)->at_irqbase + (ai)->at_irq)
+
+#define	ATPIC(io, base, eoi, imenptr)					\
+     	{ { atpic_enable_source, atpic_disable_source, (eoi),		\
+	    atpic_enable_intr, atpic_disable_intr, atpic_vector,	\
+	    atpic_source_pending, NULL,	atpic_resume, atpic_config_intr,\
+	    atpic_assign_cpu }, (io), (base), IDT_IO_INTS + (base),	\
+	    (imenptr) }
+
+#define	INTSRC(irq)							\
+	{ { &atpics[(irq) / 8].at_pic }, IDTVEC(atpic_intr ## irq ),	\
+	    (irq) % 8 }
+
+struct atpic {
+	struct pic at_pic;
+	int	at_ioaddr;
+	int	at_irqbase;
+	uint8_t	at_intbase;
+	uint8_t	*at_imen;
+};
+
+struct atpic_intsrc {
+	struct intsrc at_intsrc;
+	inthand_t *at_intr;
+	int	at_irq;			/* Relative to PIC base. */
+	enum intr_trigger at_trigger;
+	u_long	at_count;
+	u_long	at_straycount;
+};
+
+static void atpic_enable_source(struct intsrc *isrc);
+static void atpic_disable_source(struct intsrc *isrc, int eoi);
+static void atpic_eoi_master(struct intsrc *isrc);
+static void atpic_eoi_slave(struct intsrc *isrc);
+static void atpic_enable_intr(struct intsrc *isrc);
+static void atpic_disable_intr(struct intsrc *isrc);
+static int atpic_vector(struct intsrc *isrc);
+static void atpic_resume(struct pic *pic);
+static int atpic_source_pending(struct intsrc *isrc);
+static int atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
+    enum intr_polarity pol);
+static int atpic_assign_cpu(struct intsrc *isrc, u_int apic_id);
+static void i8259_init(struct atpic *pic, int slave);
+
+static struct atpic atpics[] = {
+	ATPIC(IO_ICU1, 0, atpic_eoi_master, (uint8_t *)&imen),
+	ATPIC(IO_ICU2, 8, atpic_eoi_slave, ((uint8_t *)&imen) + 1)
+};
+
+static struct atpic_intsrc atintrs[] = {
+	INTSRC(0),
+	INTSRC(1),
+	INTSRC(2),
+	INTSRC(3),
+	INTSRC(4),
+	INTSRC(5),
+	INTSRC(6),
+	INTSRC(7),
+	INTSRC(8),
+	INTSRC(9),
+	INTSRC(10),
+	INTSRC(11),
+	INTSRC(12),
+	INTSRC(13),
+	INTSRC(14),
+	INTSRC(15),
+};
+
+CTASSERT(sizeof(atintrs) / sizeof(atintrs[0]) == NUM_ISA_IRQS);
+
+static __inline void
+_atpic_eoi_master(struct intsrc *isrc)
+{
+
+	KASSERT(isrc->is_pic == &atpics[MASTER].at_pic,
+	    ("%s: mismatched pic", __func__));
+#ifndef AUTO_EOI_1
+	outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
+#endif
+}
+
+/*
+ * The data sheet says no auto-EOI on slave, but it sometimes works.
+ * So, if AUTO_EOI_2 is enabled, we use it.
+ */
+static __inline void
+_atpic_eoi_slave(struct intsrc *isrc)
+{
+
+	KASSERT(isrc->is_pic == &atpics[SLAVE].at_pic,
+	    ("%s: mismatched pic", __func__));
+#ifndef AUTO_EOI_2
+	outb(atpics[SLAVE].at_ioaddr, OCW2_EOI);
+#ifndef AUTO_EOI_1
+	outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
+#endif
+#endif
+}
+
+static void
+atpic_enable_source(struct intsrc *isrc)
+{
+	struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
+	struct atpic *ap = (struct atpic *)isrc->is_pic;
+
+	spinlock_enter();
+	if (*ap->at_imen & IMEN_MASK(ai)) {
+		*ap->at_imen &= ~IMEN_MASK(ai);
+		outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen);
+	}
+	spinlock_exit();
+}
+
+static void
+atpic_disable_source(struct intsrc *isrc, int eoi)
+{
+	struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
+	struct atpic *ap = (struct atpic *)isrc->is_pic;
+
+	spinlock_enter();
+	if (ai->at_trigger != INTR_TRIGGER_EDGE) {
+		*ap->at_imen |= IMEN_MASK(ai);
+		outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen);
+	}
+
+	/*
+	 * Take care to call these functions directly instead of through
+	 * a function pointer.  All of the referenced variables should
+	 * still be hot in the cache.
+	 */
+	if (eoi == PIC_EOI) {
+		if (isrc->is_pic == &atpics[MASTER].at_pic)
+			_atpic_eoi_master(isrc);
+		else
+			_atpic_eoi_slave(isrc);
+	}
+
+	spinlock_exit();
+}
+
+static void
+atpic_eoi_master(struct intsrc *isrc)
+{
+#ifndef AUTO_EOI_1
+	spinlock_enter();
+	_atpic_eoi_master(isrc);
+	spinlock_exit();
+#endif
+}
+
+static void
+atpic_eoi_slave(struct intsrc *isrc)
+{
+#ifndef AUTO_EOI_2
+	spinlock_enter();
+	_atpic_eoi_slave(isrc);
+	spinlock_exit();
+#endif
+}
+
+static void
+atpic_enable_intr(struct intsrc *isrc)
+{
+}
+
+static void
+atpic_disable_intr(struct intsrc *isrc)
+{
+}
+
+
+static int
+atpic_vector(struct intsrc *isrc)
+{
+	struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
+	struct atpic *ap = (struct atpic *)isrc->is_pic;
+
+	return (IRQ(ap, ai));
+}
+
+static int
+atpic_source_pending(struct intsrc *isrc)
+{
+	struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
+	struct atpic *ap = (struct atpic *)isrc->is_pic;
+
+	return (inb(ap->at_ioaddr) & IMEN_MASK(ai));
+}
+
+static void
+atpic_resume(struct pic *pic)
+{
+	struct atpic *ap = (struct atpic *)pic;
+
+	i8259_init(ap, ap == &atpics[SLAVE]);
+#ifndef PC98
+	if (ap == &atpics[SLAVE] && elcr_found)
+		elcr_resume();
+#endif
+}
+
+static int
+atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
+    enum intr_polarity pol)
+{
+	struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
+	u_int vector;
+
+	/* Map conforming values to edge/hi and sanity check the values. */
+	if (trig == INTR_TRIGGER_CONFORM)
+		trig = INTR_TRIGGER_EDGE;
+	if (pol == INTR_POLARITY_CONFORM)
+		pol = INTR_POLARITY_HIGH;
+	vector = atpic_vector(isrc);
+	if ((trig == INTR_TRIGGER_EDGE && pol == INTR_POLARITY_LOW) ||
+	    (trig == INTR_TRIGGER_LEVEL && pol == INTR_POLARITY_HIGH)) {
+		printf(
+		"atpic: Mismatched config for IRQ%u: trigger %s, polarity %s\n",
+		    vector, trig == INTR_TRIGGER_EDGE ? "edge" : "level",
+		    pol == INTR_POLARITY_HIGH ? "high" : "low");
+		return (EINVAL);
+	}
+
+	/* If there is no change, just return. */
+	if (ai->at_trigger == trig)
+		return (0);
+
+#ifdef PC98
+	if ((vector == 0 || vector == 1 || vector == 7 || vector == 8) &&
+	    trig == INTR_TRIGGER_LEVEL) {
+		if (bootverbose)
+			printf(
+		"atpic: Ignoring invalid level/low configuration for IRQ%u\n",
+			    vector);
+		return (EINVAL);
+	}
+	return (ENXIO);
+#else
+	/*
+	 * Certain IRQs can never be level/lo, so don't try to set them
+	 * that way if asked.  At least some ELCR registers ignore setting
+	 * these bits as well.
+	 */
+	if ((vector == 0 || vector == 1 || vector == 2 || vector == 13) &&
+	    trig == INTR_TRIGGER_LEVEL) {
+		if (bootverbose)
+			printf(
+		"atpic: Ignoring invalid level/low configuration for IRQ%u\n",
+			    vector);
+		return (EINVAL);
+	}
+	if (!elcr_found) {
+		if (bootverbose)
+			printf("atpic: No ELCR to configure IRQ%u as %s\n",
+			    vector, trig == INTR_TRIGGER_EDGE ? "edge/high" :
+			    "level/low");
+		return (ENXIO);
+	}
+	if (bootverbose)
+		printf("atpic: Programming IRQ%u as %s\n", vector,
+		    trig == INTR_TRIGGER_EDGE ? "edge/high" : "level/low");
+	spinlock_enter();
+	elcr_write_trigger(atpic_vector(isrc), trig);
+	ai->at_trigger = trig;
+	spinlock_exit();
+	return (0);
+#endif /* PC98 */
+}
+
+static int
+atpic_assign_cpu(struct intsrc *isrc, u_int apic_id)
+{
+
+	/*
+	 * 8259A's are only used in UP in which case all interrupts always
+	 * go to the sole CPU and this function shouldn't even be called.
+	 */
+	panic("%s: bad cookie", __func__);
+}
+
+static void
+i8259_init(struct atpic *pic, int slave)
+{
+	int imr_addr;
+
+	/* Reset the PIC and program with next four bytes. */
+	spinlock_enter();
+#ifdef DEV_MCA
+	/* MCA uses level triggered interrupts. */
+	if (MCA_system)
+		outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4 | ICW1_LTIM);
+	else
+#endif
+		outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4);
+	imr_addr = pic->at_ioaddr + ICU_IMR_OFFSET;
+
+	/* Start vector. */
+	outb(imr_addr, pic->at_intbase);
+
+	/*
+	 * Setup slave links.  For the master pic, indicate what line
+	 * the slave is configured on.  For the slave indicate
+	 * which line on the master we are connected to.
+	 */
+	if (slave)
+		outb(imr_addr, ICU_SLAVEID);
+	else
+		outb(imr_addr, IRQ_MASK(ICU_SLAVEID));
+
+	/* Set mode. */
+	if (slave)
+		outb(imr_addr, SLAVE_MODE);
+	else
+		outb(imr_addr, MASTER_MODE);
+
+	/* Set interrupt enable mask. */
+	outb(imr_addr, *pic->at_imen);
+
+	/* Reset is finished, default to IRR on read. */
+	outb(pic->at_ioaddr, OCW3_SEL | OCW3_RR);
+
+#ifndef PC98
+	/* OCW2_L1 sets priority order to 3-7, 0-2 (com2 first). */
+	if (!slave)
+		outb(pic->at_ioaddr, OCW2_R | OCW2_SL | OCW2_L1);
+#endif
+	spinlock_exit();
+}
+
+void
+atpic_startup(void)
+{
+	struct atpic_intsrc *ai;
+	int i;
+
+	/* Start off with all interrupts disabled. */
+	imen = 0xffff;
+	i8259_init(&atpics[MASTER], 0);
+	i8259_init(&atpics[SLAVE], 1);
+	atpic_enable_source((struct intsrc *)&atintrs[ICU_SLAVEID]);
+
+	/* Install low-level interrupt handlers for all of our IRQs. */
+	for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
+		if (i == ICU_SLAVEID)
+			continue;
+		ai->at_intsrc.is_count = &ai->at_count;
+		ai->at_intsrc.is_straycount = &ai->at_straycount;
+		setidt(((struct atpic *)ai->at_intsrc.is_pic)->at_intbase +
+		    ai->at_irq, ai->at_intr, SDT_ATPIC, SEL_KPL, GSEL_ATPIC);
+	}
+
+#ifdef DEV_MCA
+	/* For MCA systems, all interrupts are level triggered. */
+	if (MCA_system)
+		for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
+			ai->at_trigger = INTR_TRIGGER_LEVEL;
+	else
+#endif
+
+#ifdef PC98
+	for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
+		switch (i) {
+		case 0:
+		case 1:
+		case 7:
+		case 8:
+			ai->at_trigger = INTR_TRIGGER_EDGE;
+			break;
+		default:
+			ai->at_trigger = INTR_TRIGGER_LEVEL;
+			break;
+		}
+#else
+	/*
+	 * Look for an ELCR.  If we find one, update the trigger modes.
+	 * If we don't find one, assume that IRQs 0, 1, 2, and 13 are
+	 * edge triggered and that everything else is level triggered.
+	 * We only use the trigger information to reprogram the ELCR if
+	 * we have one and as an optimization to avoid masking edge
+	 * triggered interrupts.  For the case that we don't have an ELCR,
+	 * it doesn't hurt to mask an edge triggered interrupt, so we
+	 * assume level trigger for any interrupt that we aren't sure is
+	 * edge triggered.
+	 */
+	if (elcr_found) {
+		for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
+			ai->at_trigger = elcr_read_trigger(i);
+	} else {
+		for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
+			switch (i) {
+			case 0:
+			case 1:
+			case 2:
+			case 8:
+			case 13:
+				ai->at_trigger = INTR_TRIGGER_EDGE;
+				break;
+			default:
+				ai->at_trigger = INTR_TRIGGER_LEVEL;
+				break;
+			}
+	}
+#endif /* PC98 */
+}
+
+static void
+atpic_init(void *dummy __unused)
+{
+	struct atpic_intsrc *ai;
+	int i;
+
+	/*
+	 * Register our PICs, even if we aren't going to use any of their
+	 * pins so that they are suspended and resumed.
+	 */
+	if (intr_register_pic(&atpics[0].at_pic) != 0 ||
+	    intr_register_pic(&atpics[1].at_pic) != 0)
+		panic("Unable to register ATPICs");
+
+	/*
+	 * If any of the ISA IRQs have an interrupt source already, then
+	 * assume that the APICs are being used and don't register any
+	 * of our interrupt sources.  This makes sure we don't accidentally
+	 * use mixed mode.  The "accidental" use could otherwise occur on
+	 * machines that route the ACPI SCI interrupt to a different ISA
+	 * IRQ (at least one machines routes it to IRQ 13) thus disabling
+	 * that APIC ISA routing and allowing the ATPIC source for that IRQ
+	 * to leak through.  We used to depend on this feature for routing
+	 * IRQ0 via mixed mode, but now we don't use mixed mode at all.
+	 */
+	for (i = 0; i < NUM_ISA_IRQS; i++)
+		if (intr_lookup_source(i) != NULL)
+			return;
+
+	/* Loop through all interrupt sources and add them. */
+	for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
+		if (i == ICU_SLAVEID)
+			continue;
+		intr_register_source(&ai->at_intsrc);
+	}
+}
+SYSINIT(atpic_init, SI_SUB_INTR, SI_ORDER_SECOND + 1, atpic_init, NULL);
+
+void
+atpic_handle_intr(u_int vector, struct trapframe *frame)
+{
+	struct intsrc *isrc;
+
+	KASSERT(vector < NUM_ISA_IRQS, ("unknown int %u\n", vector));
+	isrc = &atintrs[vector].at_intsrc;
+
+	/*
+	 * If we don't have an event, see if this is a spurious
+	 * interrupt.
+	 */
+	if (isrc->is_event == NULL && (vector == 7 || vector == 15)) {
+		int port, isr;
+
+		/*
+		 * Read the ISR register to see if IRQ 7/15 is really
+		 * pending.  Reset read register back to IRR when done.
+		 */
+		port = ((struct atpic *)isrc->is_pic)->at_ioaddr;
+		spinlock_enter();
+		outb(port, OCW3_SEL | OCW3_RR | OCW3_RIS);
+		isr = inb(port);
+		outb(port, OCW3_SEL | OCW3_RR);
+		spinlock_exit();
+		if ((isr & IRQ_MASK(7)) == 0)
+			return;
+	}
+	intr_execute_handlers(isrc, frame);
+}
+
+#ifdef DEV_ISA
+/*
+ * Bus attachment for the ISA PIC.
+ */
+static struct isa_pnp_id atpic_ids[] = {
+	{ 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
+	{ 0 }
+};
+
+static int
+atpic_probe(device_t dev)
+{
+	int result;
+	
+	result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids);
+	if (result <= 0)
+		device_quiet(dev);
+	return (result);
+}
+
+/*
+ * We might be granted IRQ 2, as this is typically consumed by chaining
+ * between the two PIC components.  If we're using the APIC, however,
+ * this may not be the case, and as such we should free the resource.
+ * (XXX untested)
+ *
+ * The generic ISA attachment code will handle allocating any other resources
+ * that we don't explicitly claim here.
+ */
+static int
+atpic_attach(device_t dev)
+{
+	struct resource *res;
+	int rid;
+
+	/* Try to allocate our IRQ and then free it. */
+	rid = 0;
+	res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 0);
+	if (res != NULL)
+		bus_release_resource(dev, SYS_RES_IRQ, rid, res);
+	return (0);
+}
+
+static device_method_t atpic_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		atpic_probe),
+	DEVMETHOD(device_attach,	atpic_attach),
+	DEVMETHOD(device_detach,	bus_generic_detach),
+	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
+	DEVMETHOD(device_suspend,	bus_generic_suspend),
+	DEVMETHOD(device_resume,	bus_generic_resume),
+	{ 0, 0 }
+};
+
+static driver_t atpic_driver = {
+	"atpic",
+	atpic_methods,
+	1,		/* no softc */
+};
+
+static devclass_t atpic_devclass;
+
+DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0);
+#ifndef PC98
+DRIVER_MODULE(atpic, acpi, atpic_driver, atpic_devclass, 0, 0);
+#endif
+
+/*
+ * Return a bitmap of the current interrupt requests.  This is 8259-specific
+ * and is only suitable for use at probe time.
+ */
+intrmask_t
+isa_irq_pending(void)
+{
+	u_char irr1;
+	u_char irr2;
+
+	irr1 = inb(IO_ICU1);
+	irr2 = inb(IO_ICU2);
+	return ((irr2 << 8) | irr1);
+}
+#endif /* DEV_ISA */
diff --git a/sys/x86/isa/atrtc.c b/sys/x86/isa/atrtc.c
new file mode 100644
index 0000000..777c720
--- /dev/null
+++ b/sys/x86/isa/atrtc.c
@@ -0,0 +1,331 @@
+/*-
+ * Copyright (c) 2008 Poul-Henning Kamp
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include "opt_isa.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/clock.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+
+#include <isa/rtc.h>
+#ifdef DEV_ISA
+#include <isa/isareg.h>
+#include <isa/isavar.h>
+#endif
+
+#define	RTC_LOCK	mtx_lock_spin(&clock_lock)
+#define	RTC_UNLOCK	mtx_unlock_spin(&clock_lock)
+
+int	atrtcclock_disable = 0;
+
+static	int	rtc_reg = -1;
+static	u_char	rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
+static	u_char	rtc_statusb = RTCSB_24HR;
+
+/*
+ * RTC support routines
+ */
+
+int
+rtcin(int reg)
+{
+	u_char val;
+
+	RTC_LOCK;
+	if (rtc_reg != reg) {
+		inb(0x84);
+		outb(IO_RTC, reg);
+		rtc_reg = reg;
+		inb(0x84);
+	}
+	val = inb(IO_RTC + 1);
+	RTC_UNLOCK;
+	return (val);
+}
+
+void
+writertc(int reg, u_char val)
+{
+
+	RTC_LOCK;
+	if (rtc_reg != reg) {
+		inb(0x84);
+		outb(IO_RTC, reg);
+		rtc_reg = reg;
+		inb(0x84);
+	}
+	outb(IO_RTC + 1, val);
+	inb(0x84);
+	RTC_UNLOCK;
+}
+
+static __inline int
+readrtc(int port)
+{
+	return(bcd2bin(rtcin(port)));
+}
+
+void
+atrtc_start(void)
+{
+
+	writertc(RTC_STATUSA, rtc_statusa);
+	writertc(RTC_STATUSB, RTCSB_24HR);
+}
+
+void
+atrtc_rate(unsigned rate)
+{
+
+	rtc_statusa = RTCSA_DIVIDER | rate;
+	writertc(RTC_STATUSA, rtc_statusa);
+}
+
+void
+atrtc_enable_intr(void)
+{
+
+	rtc_statusb |= RTCSB_PINTR;
+	writertc(RTC_STATUSB, rtc_statusb);
+	rtcin(RTC_INTR);
+}
+
+void
+atrtc_restore(void)
+{
+
+	/* Restore all of the RTC's "status" (actually, control) registers. */
+	rtcin(RTC_STATUSA);	/* dummy to get rtc_reg set */
+	writertc(RTC_STATUSB, RTCSB_24HR);
+	writertc(RTC_STATUSA, rtc_statusa);
+	writertc(RTC_STATUSB, rtc_statusb);
+	rtcin(RTC_INTR);
+}
+
+int
+atrtc_setup_clock(void)
+{
+	int diag;
+
+	if (atrtcclock_disable)
+		return (0);
+
+	diag = rtcin(RTC_DIAG);
+	if (diag != 0) {
+		printf("RTC BIOS diagnostic error %b\n",
+		    diag, RTCDG_BITS);
+		return (0);
+	}
+
+	stathz = RTC_NOPROFRATE;
+	profhz = RTC_PROFRATE;
+
+	return (1);
+}
+
+/**********************************************************************
+ * RTC driver for subr_rtc
+ */
+
+#include "clock_if.h"
+
+#include <sys/rman.h>
+
+struct atrtc_softc {
+	int port_rid, intr_rid;
+	struct resource *port_res;
+	struct resource *intr_res;
+};
+
+/*
+ * Attach to the ISA PnP descriptors for the timer and realtime clock.
+ */
+static struct isa_pnp_id atrtc_ids[] = {
+	{ 0x000bd041 /* PNP0B00 */, "AT realtime clock" },
+	{ 0 }
+};
+
+static int
+atrtc_probe(device_t dev)
+{
+	int result;
+	
+	device_set_desc(dev, "AT Real Time Clock");
+	result = ISA_PNP_PROBE(device_get_parent(dev), dev, atrtc_ids);
+	/* ENXIO if wrong PnP-ID, ENOENT ifno PnP-ID, zero if good PnP-iD */
+	if (result != ENOENT)
+		return(result);
+	/* All PC's have an RTC, and we're hosed without it, so... */
+	return (BUS_PROBE_LOW_PRIORITY);
+}
+
+static int
+atrtc_attach(device_t dev)
+{
+	struct atrtc_softc *sc;
+	int i;
+
+	/*
+	 * Not that we need them or anything, but grab our resources
+	 * so they show up, correctly attributed, in the big picture.
+	 */
+	
+	sc = device_get_softc(dev);
+	if (!(sc->port_res = bus_alloc_resource(dev, SYS_RES_IOPORT,
+	    &sc->port_rid, IO_RTC, IO_RTC + 1, 2, RF_ACTIVE)))
+		device_printf(dev,"Warning: Couldn't map I/O.\n");
+	if (!(sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ,
+	    &sc->intr_rid, 8, 8, 1, RF_ACTIVE)))
+		device_printf(dev,"Warning: Couldn't map Interrupt.\n");
+	clock_register(dev, 1000000);
+	if (resource_int_value("atrtc", 0, "clock", &i) == 0 && i == 0)
+		atrtcclock_disable = 1;
+	return(0);
+}
+
+static int
+atrtc_resume(device_t dev)
+{
+
+	atrtc_restore();
+	return(0);
+}
+
+static int
+atrtc_settime(device_t dev __unused, struct timespec *ts)
+{
+	struct clocktime ct;
+
+	clock_ts_to_ct(ts, &ct);
+
+	/* Disable RTC updates and interrupts. */
+	writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
+
+	writertc(RTC_SEC, bin2bcd(ct.sec)); 		/* Write back Seconds */
+	writertc(RTC_MIN, bin2bcd(ct.min)); 		/* Write back Minutes */
+	writertc(RTC_HRS, bin2bcd(ct.hour));		/* Write back Hours   */
+
+	writertc(RTC_WDAY, ct.dow + 1);			/* Write back Weekday */
+	writertc(RTC_DAY, bin2bcd(ct.day));		/* Write back Day */
+	writertc(RTC_MONTH, bin2bcd(ct.mon));           /* Write back Month   */
+	writertc(RTC_YEAR, bin2bcd(ct.year % 100));	/* Write back Year    */
+#ifdef USE_RTC_CENTURY
+	writertc(RTC_CENTURY, bin2bcd(ct.year / 100));	/* ... and Century    */
+#endif
+
+	/* Reenable RTC updates and interrupts. */
+	writertc(RTC_STATUSB, rtc_statusb);
+	rtcin(RTC_INTR);
+	return (0);
+}
+
+static int
+atrtc_gettime(device_t dev, struct timespec *ts)
+{
+	struct clocktime ct;
+	int s;
+
+	/* Look if we have a RTC present and the time is valid */
+	if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) {
+		device_printf(dev, "WARNING: Battery failure indication\n");
+		return (EINVAL);
+	}
+
+	/* wait for time update to complete */
+	/* If RTCSA_TUP is zero, we have at least 244us before next update */
+	s = splhigh();
+	while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
+		splx(s);
+		s = splhigh();
+	}
+	ct.nsec = 0;
+	ct.sec = readrtc(RTC_SEC);
+	ct.min = readrtc(RTC_MIN);
+	ct.hour = readrtc(RTC_HRS);
+	ct.day = readrtc(RTC_DAY);
+	ct.dow = readrtc(RTC_WDAY) - 1;
+	ct.mon = readrtc(RTC_MONTH);
+	ct.year = readrtc(RTC_YEAR);
+#ifdef USE_RTC_CENTURY
+	ct.year += readrtc(RTC_CENTURY) * 100;
+#else
+	ct.year += 2000;
+#endif
+	/* Set dow = -1 because some clocks don't set it correctly. */
+	ct.dow = -1;
+	return (clock_ct_to_ts(&ct, ts));
+}
+
+static device_method_t atrtc_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		atrtc_probe),
+	DEVMETHOD(device_attach,	atrtc_attach),
+	DEVMETHOD(device_detach,	bus_generic_detach),
+	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
+	DEVMETHOD(device_suspend,	bus_generic_suspend),
+		/* XXX stop statclock? */
+	DEVMETHOD(device_resume,	atrtc_resume),
+
+	/* clock interface */
+	DEVMETHOD(clock_gettime,	atrtc_gettime),
+	DEVMETHOD(clock_settime,	atrtc_settime),
+
+	{ 0, 0 }
+};
+
+static driver_t atrtc_driver = {
+	"atrtc",
+	atrtc_methods,
+	sizeof(struct atrtc_softc),
+};
+
+static devclass_t atrtc_devclass;
+
+DRIVER_MODULE(atrtc, isa, atrtc_driver, atrtc_devclass, 0, 0);
+DRIVER_MODULE(atrtc, acpi, atrtc_driver, atrtc_devclass, 0, 0);
+
+#include "opt_ddb.h"
+#ifdef DDB
+#include <ddb/ddb.h>
+
+DB_SHOW_COMMAND(rtc, rtc)
+{
+	printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
+		rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
+		rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
+		rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
+}
+#endif /* DDB */
diff --git a/sys/x86/isa/clock.c b/sys/x86/isa/clock.c
new file mode 100644
index 0000000..6ced537
--- /dev/null
+++ b/sys/x86/isa/clock.c
@@ -0,0 +1,719 @@
+/*-
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz and Don Ahn.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	from: @(#)clock.c	7.2 (Berkeley) 5/12/91
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * Routines to handle clock hardware.
+ */
+
+#ifndef __amd64__
+#include "opt_apic.h"
+#endif
+#include "opt_clock.h"
+#include "opt_kdtrace.h"
+#include "opt_isa.h"
+#include "opt_mca.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/lock.h>
+#include <sys/kdb.h>
+#include <sys/mutex.h>
+#include <sys/proc.h>
+#include <sys/timetc.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/sched.h>
+#include <sys/smp.h>
+#include <sys/sysctl.h>
+
+#include <machine/clock.h>
+#include <machine/cpu.h>
+#include <machine/intr_machdep.h>
+#include <machine/md_var.h>
+#include <machine/apicvar.h>
+#include <machine/ppireg.h>
+#include <machine/timerreg.h>
+#include <machine/smp.h>
+
+#include <isa/rtc.h>
+#ifdef DEV_ISA
+#include <isa/isareg.h>
+#include <isa/isavar.h>
+#endif
+
+#ifdef DEV_MCA
+#include <i386/bios/mca_machdep.h>
+#endif
+
+#ifdef KDTRACE_HOOKS
+#include <sys/dtrace_bsd.h>
+#endif
+
+#define	TIMER_DIV(x) ((i8254_freq + (x) / 2) / (x))
+
+int	clkintr_pending;
+static int pscnt = 1;
+static int psdiv = 1;
+#ifndef TIMER_FREQ
+#define TIMER_FREQ   1193182
+#endif
+u_int	i8254_freq = TIMER_FREQ;
+TUNABLE_INT("hw.i8254.freq", &i8254_freq);
+int	i8254_max_count;
+static int i8254_real_max_count;
+
+struct mtx clock_lock;
+static	struct intsrc *i8254_intsrc;
+static	u_int32_t i8254_lastcount;
+static	u_int32_t i8254_offset;
+static	int	(*i8254_pending)(struct intsrc *);
+static	int	i8254_ticked;
+static	int	using_atrtc_timer;
+static	enum lapic_clock using_lapic_timer = LAPIC_CLOCK_NONE;
+
+/* Values for timerX_state: */
+#define	RELEASED	0
+#define	RELEASE_PENDING	1
+#define	ACQUIRED	2
+#define	ACQUIRE_PENDING	3
+
+static	u_char	timer2_state;
+
+static	unsigned i8254_get_timecount(struct timecounter *tc);
+static	unsigned i8254_simple_get_timecount(struct timecounter *tc);
+static	void	set_i8254_freq(u_int freq, int intr_freq);
+
+static struct timecounter i8254_timecounter = {
+	i8254_get_timecount,	/* get_timecount */
+	0,			/* no poll_pps */
+	~0u,			/* counter_mask */
+	0,			/* frequency */
+	"i8254",		/* name */
+	0			/* quality */
+};
+
+int
+hardclockintr(struct trapframe *frame)
+{
+
+	if (PCPU_GET(cpuid) == 0)
+		hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
+	else
+		hardclock_cpu(TRAPF_USERMODE(frame));
+	return (FILTER_HANDLED);
+}
+
+int
+statclockintr(struct trapframe *frame)
+{
+
+	profclockintr(frame);
+	statclock(TRAPF_USERMODE(frame));
+	return (FILTER_HANDLED);
+}
+
+int
+profclockintr(struct trapframe *frame)
+{
+
+	if (!using_atrtc_timer)
+		hardclockintr(frame);
+	if (profprocs != 0)
+		profclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
+	return (FILTER_HANDLED);
+}
+
+static int
+clkintr(struct trapframe *frame)
+{
+
+	if (timecounter->tc_get_timecount == i8254_get_timecount) {
+		mtx_lock_spin(&clock_lock);
+		if (i8254_ticked)
+			i8254_ticked = 0;
+		else {
+			i8254_offset += i8254_max_count;
+			i8254_lastcount = 0;
+		}
+		clkintr_pending = 0;
+		mtx_unlock_spin(&clock_lock);
+	}
+	KASSERT(using_lapic_timer == LAPIC_CLOCK_NONE,
+	    ("clk interrupt enabled with lapic timer"));
+
+#ifdef KDTRACE_HOOKS
+	/*
+	 * If the DTrace hooks are configured and a callback function
+	 * has been registered, then call it to process the high speed
+	 * timers.
+	 */
+	int cpu = PCPU_GET(cpuid);
+	if (lapic_cyclic_clock_func[cpu] != NULL)
+		(*lapic_cyclic_clock_func[cpu])(frame);
+#endif
+
+	if (using_atrtc_timer) {
+#ifdef SMP
+		if (smp_started)
+			ipi_all_but_self(IPI_HARDCLOCK);
+#endif
+		hardclockintr(frame);
+	} else {
+		if (--pscnt <= 0) {
+			pscnt = psratio;
+#ifdef SMP
+			if (smp_started)
+				ipi_all_but_self(IPI_STATCLOCK);
+#endif
+			statclockintr(frame);
+		} else {
+#ifdef SMP
+			if (smp_started)
+				ipi_all_but_self(IPI_PROFCLOCK);
+#endif
+			profclockintr(frame);
+		}
+	}
+
+#ifdef DEV_MCA
+	/* Reset clock interrupt by asserting bit 7 of port 0x61 */
+	if (MCA_system)
+		outb(0x61, inb(0x61) | 0x80);
+#endif
+	return (FILTER_HANDLED);
+}
+
+int
+timer_spkr_acquire(void)
+{
+	int mode;
+
+	mode = TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT;
+
+	if (timer2_state != RELEASED)
+		return (-1);
+	timer2_state = ACQUIRED;
+
+	/*
+	 * This access to the timer registers is as atomic as possible
+	 * because it is a single instruction.  We could do better if we
+	 * knew the rate.  Use of splclock() limits glitches to 10-100us,
+	 * and this is probably good enough for timer2, so we aren't as
+	 * careful with it as with timer0.
+	 */
+	outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
+	ppi_spkr_on();		/* enable counter2 output to speaker */
+	return (0);
+}
+
+int
+timer_spkr_release(void)
+{
+
+	if (timer2_state != ACQUIRED)
+		return (-1);
+	timer2_state = RELEASED;
+	outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
+	ppi_spkr_off();		/* disable counter2 output to speaker */
+	return (0);
+}
+
+void
+timer_spkr_setfreq(int freq)
+{
+
+	freq = i8254_freq / freq;
+	mtx_lock_spin(&clock_lock);
+	outb(TIMER_CNTR2, freq & 0xff);
+	outb(TIMER_CNTR2, freq >> 8);
+	mtx_unlock_spin(&clock_lock);
+}
+
+/*
+ * This routine receives statistical clock interrupts from the RTC.
+ * As explained above, these occur at 128 interrupts per second.
+ * When profiling, we receive interrupts at a rate of 1024 Hz.
+ *
+ * This does not actually add as much overhead as it sounds, because
+ * when the statistical clock is active, the hardclock driver no longer
+ * needs to keep (inaccurate) statistics on its own.  This decouples
+ * statistics gathering from scheduling interrupts.
+ *
+ * The RTC chip requires that we read status register C (RTC_INTR)
+ * to acknowledge an interrupt, before it will generate the next one.
+ * Under high interrupt load, rtcintr() can be indefinitely delayed and
+ * the clock can tick immediately after the read from RTC_INTR.  In this
+ * case, the mc146818A interrupt signal will not drop for long enough
+ * to register with the 8259 PIC.  If an interrupt is missed, the stat
+ * clock will halt, considerably degrading system performance.  This is
+ * why we use 'while' rather than a more straightforward 'if' below.
+ * Stat clock ticks can still be lost, causing minor loss of accuracy
+ * in the statistics, but the stat clock will no longer stop.
+ */
+static int
+rtcintr(struct trapframe *frame)
+{
+	int flag = 0;
+
+	while (rtcin(RTC_INTR) & RTCIR_PERIOD) {
+		flag = 1;
+		if (--pscnt <= 0) {
+			pscnt = psdiv;
+#ifdef SMP
+			if (smp_started)
+				ipi_all_but_self(IPI_STATCLOCK);
+#endif
+			statclockintr(frame);
+		} else {
+#ifdef SMP
+			if (smp_started)
+				ipi_all_but_self(IPI_PROFCLOCK);
+#endif
+			profclockintr(frame);
+		}
+	}
+	return(flag ? FILTER_HANDLED : FILTER_STRAY);
+}
+
+static int
+getit(void)
+{
+	int high, low;
+
+	mtx_lock_spin(&clock_lock);
+
+	/* Select timer0 and latch counter value. */
+	outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
+
+	low = inb(TIMER_CNTR0);
+	high = inb(TIMER_CNTR0);
+
+	mtx_unlock_spin(&clock_lock);
+	return ((high << 8) | low);
+}
+
+/*
+ * Wait "n" microseconds.
+ * Relies on timer 1 counting down from (i8254_freq / hz)
+ * Note: timer had better have been programmed before this is first used!
+ */
+void
+DELAY(int n)
+{
+	int delta, prev_tick, tick, ticks_left;
+
+#ifdef DELAYDEBUG
+	int getit_calls = 1;
+	int n1;
+	static int state = 0;
+#endif
+
+	if (tsc_freq != 0 && !tsc_is_broken) {
+		uint64_t start, end, now;
+
+		sched_pin();
+		start = rdtsc();
+		end = start + (tsc_freq * n) / 1000000;
+		do {
+			cpu_spinwait();
+			now = rdtsc();
+		} while (now < end || (now > start && end < start));
+		sched_unpin();
+		return;
+	}
+#ifdef DELAYDEBUG
+	if (state == 0) {
+		state = 1;
+		for (n1 = 1; n1 <= 10000000; n1 *= 10)
+			DELAY(n1);
+		state = 2;
+	}
+	if (state == 1)
+		printf("DELAY(%d)...", n);
+#endif
+	/*
+	 * Read the counter first, so that the rest of the setup overhead is
+	 * counted.  Guess the initial overhead is 20 usec (on most systems it
+	 * takes about 1.5 usec for each of the i/o's in getit().  The loop
+	 * takes about 6 usec on a 486/33 and 13 usec on a 386/20.  The
+	 * multiplications and divisions to scale the count take a while).
+	 *
+	 * However, if ddb is active then use a fake counter since reading
+	 * the i8254 counter involves acquiring a lock.  ddb must not do
+	 * locking for many reasons, but it calls here for at least atkbd
+	 * input.
+	 */
+#ifdef KDB
+	if (kdb_active)
+		prev_tick = 1;
+	else
+#endif
+		prev_tick = getit();
+	n -= 0;			/* XXX actually guess no initial overhead */
+	/*
+	 * Calculate (n * (i8254_freq / 1e6)) without using floating point
+	 * and without any avoidable overflows.
+	 */
+	if (n <= 0)
+		ticks_left = 0;
+	else if (n < 256)
+		/*
+		 * Use fixed point to avoid a slow division by 1000000.
+		 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest.
+		 * 2^15 is the first power of 2 that gives exact results
+		 * for n between 0 and 256.
+		 */
+		ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15;
+	else
+		/*
+		 * Don't bother using fixed point, although gcc-2.7.2
+		 * generates particularly poor code for the long long
+		 * division, since even the slow way will complete long
+		 * before the delay is up (unless we're interrupted).
+		 */
+		ticks_left = ((u_int)n * (long long)i8254_freq + 999999)
+			     / 1000000;
+
+	while (ticks_left > 0) {
+#ifdef KDB
+		if (kdb_active) {
+			inb(0x84);
+			tick = prev_tick - 1;
+			if (tick <= 0)
+				tick = i8254_max_count;
+		} else
+#endif
+			tick = getit();
+#ifdef DELAYDEBUG
+		++getit_calls;
+#endif
+		delta = prev_tick - tick;
+		prev_tick = tick;
+		if (delta < 0) {
+			delta += i8254_max_count;
+			/*
+			 * Guard against i8254_max_count being wrong.
+			 * This shouldn't happen in normal operation,
+			 * but it may happen if set_i8254_freq() is
+			 * traced.
+			 */
+			if (delta < 0)
+				delta = 0;
+		}
+		ticks_left -= delta;
+	}
+#ifdef DELAYDEBUG
+	if (state == 1)
+		printf(" %d calls to getit() at %d usec each\n",
+		       getit_calls, (n + 5) / getit_calls);
+#endif
+}
+
+static void
+set_i8254_freq(u_int freq, int intr_freq)
+{
+	int new_i8254_real_max_count;
+
+	i8254_timecounter.tc_frequency = freq;
+	mtx_lock_spin(&clock_lock);
+	i8254_freq = freq;
+	if (using_lapic_timer != LAPIC_CLOCK_NONE)
+		new_i8254_real_max_count = 0x10000;
+	else
+		new_i8254_real_max_count = TIMER_DIV(intr_freq);
+	if (new_i8254_real_max_count != i8254_real_max_count) {
+		i8254_real_max_count = new_i8254_real_max_count;
+		if (i8254_real_max_count == 0x10000)
+			i8254_max_count = 0xffff;
+		else
+			i8254_max_count = i8254_real_max_count;
+		outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
+		outb(TIMER_CNTR0, i8254_real_max_count & 0xff);
+		outb(TIMER_CNTR0, i8254_real_max_count >> 8);
+	}
+	mtx_unlock_spin(&clock_lock);
+}
+
+static void
+i8254_restore(void)
+{
+
+	mtx_lock_spin(&clock_lock);
+	outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
+	outb(TIMER_CNTR0, i8254_real_max_count & 0xff);
+	outb(TIMER_CNTR0, i8254_real_max_count >> 8);
+	mtx_unlock_spin(&clock_lock);
+}
+
+#ifndef __amd64__
+/*
+ * Restore all the timers non-atomically (XXX: should be atomically).
+ *
+ * This function is called from pmtimer_resume() to restore all the timers.
+ * This should not be necessary, but there are broken laptops that do not
+ * restore all the timers on resume.
+ * As long as pmtimer is not part of amd64 suport, skip this for the amd64
+ * case.
+ */
+void
+timer_restore(void)
+{
+
+	i8254_restore();		/* restore i8254_freq and hz */
+	atrtc_restore();		/* reenable RTC interrupts */
+}
+#endif
+
+/* This is separate from startrtclock() so that it can be called early. */
+void
+i8254_init(void)
+{
+
+	mtx_init(&clock_lock, "clk", NULL, MTX_SPIN | MTX_NOPROFILE);
+	set_i8254_freq(i8254_freq, hz);
+}
+
+void
+startrtclock()
+{
+
+	atrtc_start();
+
+	set_i8254_freq(i8254_freq, hz);
+	tc_init(&i8254_timecounter);
+
+	init_TSC();
+}
+
+/*
+ * Start both clocks running.
+ */
+void
+cpu_initclocks()
+{
+
+#if defined(__amd64__) || defined(DEV_APIC)
+	using_lapic_timer = lapic_setup_clock();
+#endif
+	/*
+	 * If we aren't using the local APIC timer to drive the kernel
+	 * clocks, setup the interrupt handler for the 8254 timer 0 so
+	 * that it can drive hardclock().  Otherwise, change the 8254
+	 * timecounter to user a simpler algorithm.
+	 */
+	if (using_lapic_timer == LAPIC_CLOCK_NONE) {
+		intr_add_handler("clk", 0, (driver_filter_t *)clkintr, NULL,
+		    NULL, INTR_TYPE_CLK, NULL);
+		i8254_intsrc = intr_lookup_source(0);
+		if (i8254_intsrc != NULL)
+			i8254_pending =
+			    i8254_intsrc->is_pic->pic_source_pending;
+	} else {
+		i8254_timecounter.tc_get_timecount =
+		    i8254_simple_get_timecount;
+		i8254_timecounter.tc_counter_mask = 0xffff;
+		set_i8254_freq(i8254_freq, hz);
+	}
+
+	/* Initialize RTC. */
+	atrtc_start();
+
+	/*
+	 * If the separate statistics clock hasn't been explicility disabled
+	 * and we aren't already using the local APIC timer to drive the
+	 * kernel clocks, then setup the RTC to periodically interrupt to
+	 * drive statclock() and profclock().
+	 */
+	if (using_lapic_timer != LAPIC_CLOCK_ALL) {
+		using_atrtc_timer = atrtc_setup_clock();
+		if (using_atrtc_timer) {
+			/* Enable periodic interrupts from the RTC. */
+			intr_add_handler("rtc", 8,
+			    (driver_filter_t *)rtcintr, NULL, NULL,
+			    INTR_TYPE_CLK, NULL);
+			atrtc_enable_intr();
+		} else {
+			profhz = hz;
+			if (hz < 128)
+				stathz = hz;
+			else
+				stathz = hz / (hz / 128);
+		}
+	}
+
+	init_TSC_tc();
+}
+
+void
+cpu_startprofclock(void)
+{
+
+	if (using_lapic_timer == LAPIC_CLOCK_ALL || !using_atrtc_timer)
+		return;
+	atrtc_rate(RTCSA_PROF);
+	psdiv = pscnt = psratio;
+}
+
+void
+cpu_stopprofclock(void)
+{
+
+	if (using_lapic_timer == LAPIC_CLOCK_ALL || !using_atrtc_timer)
+		return;
+	atrtc_rate(RTCSA_NOPROF);
+	psdiv = pscnt = 1;
+}
+
+static int
+sysctl_machdep_i8254_freq(SYSCTL_HANDLER_ARGS)
+{
+	int error;
+	u_int freq;
+
+	/*
+	 * Use `i8254' instead of `timer' in external names because `timer'
+	 * is is too generic.  Should use it everywhere.
+	 */
+	freq = i8254_freq;
+	error = sysctl_handle_int(oidp, &freq, 0, req);
+	if (error == 0 && req->newptr != NULL)
+		set_i8254_freq(freq, hz);
+	return (error);
+}
+
+SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW,
+    0, sizeof(u_int), sysctl_machdep_i8254_freq, "IU", "");
+
+static unsigned
+i8254_simple_get_timecount(struct timecounter *tc)
+{
+
+	return (i8254_max_count - getit());
+}
+
+static unsigned
+i8254_get_timecount(struct timecounter *tc)
+{
+	register_t flags;
+	u_int count;
+	u_int high, low;
+
+#ifdef __amd64__
+	flags = read_rflags();
+#else
+	flags = read_eflags();
+#endif
+	mtx_lock_spin(&clock_lock);
+
+	/* Select timer0 and latch counter value. */
+	outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
+
+	low = inb(TIMER_CNTR0);
+	high = inb(TIMER_CNTR0);
+	count = i8254_max_count - ((high << 8) | low);
+	if (count < i8254_lastcount ||
+	    (!i8254_ticked && (clkintr_pending ||
+	    ((count < 20 || (!(flags & PSL_I) &&
+	    count < i8254_max_count / 2u)) &&
+	    i8254_pending != NULL && i8254_pending(i8254_intsrc))))) {
+		i8254_ticked = 1;
+		i8254_offset += i8254_max_count;
+	}
+	i8254_lastcount = count;
+	count += i8254_offset;
+	mtx_unlock_spin(&clock_lock);
+	return (count);
+}
+
+#ifdef DEV_ISA
+/*
+ * Attach to the ISA PnP descriptors for the timer
+ */
+static struct isa_pnp_id attimer_ids[] = {
+	{ 0x0001d041 /* PNP0100 */, "AT timer" },
+	{ 0 }
+};
+
+static int
+attimer_probe(device_t dev)
+{
+	int result;
+	
+	result = ISA_PNP_PROBE(device_get_parent(dev), dev, attimer_ids);
+	if (result <= 0)
+		device_quiet(dev);
+	return(result);
+}
+
+static int
+attimer_attach(device_t dev)
+{
+	return(0);
+}
+
+static int
+attimer_resume(device_t dev)
+{
+
+	i8254_restore();
+	return (0);
+}
+
+static device_method_t attimer_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		attimer_probe),
+	DEVMETHOD(device_attach,	attimer_attach),
+	DEVMETHOD(device_detach,	bus_generic_detach),
+	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
+	DEVMETHOD(device_suspend,	bus_generic_suspend),
+	DEVMETHOD(device_resume,	attimer_resume),
+	{ 0, 0 }
+};
+
+static driver_t attimer_driver = {
+	"attimer",
+	attimer_methods,
+	1,		/* no softc */
+};
+
+static devclass_t attimer_devclass;
+
+DRIVER_MODULE(attimer, isa, attimer_driver, attimer_devclass, 0, 0);
+DRIVER_MODULE(attimer, acpi, attimer_driver, attimer_devclass, 0, 0);
+
+#endif /* DEV_ISA */
diff --git a/sys/x86/isa/elcr.c b/sys/x86/isa/elcr.c
new file mode 100644
index 0000000..266d783
--- /dev/null
+++ b/sys/x86/isa/elcr.c
@@ -0,0 +1,139 @@
+/*-
+ * Copyright (c) 2004 John Baldwin <jhb@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * The ELCR is a register that controls the trigger mode and polarity of
+ * EISA and ISA interrupts.  In FreeBSD 3.x and 4.x, the ELCR was only
+ * consulted for determining the appropriate trigger mode of EISA
+ * interrupts when using an APIC.  However, it seems that almost all
+ * systems that include PCI also include an ELCR that manages the ISA
+ * IRQs 0 through 15.  Thus, we check for the presence of an ELCR on
+ * every machine by checking to see if the values found at bootup are
+ * sane.  Note that the polarity of ISA and EISA IRQs are linked to the
+ * trigger mode.  All edge triggered IRQs use active-hi polarity, and
+ * all level triggered interrupts use active-lo polarity.
+ *
+ * The format of the ELCR is simple: it is a 16-bit bitmap where bit 0
+ * controls IRQ 0, bit 1 controls IRQ 1, etc.  If the bit is zero, the
+ * associated IRQ is edge triggered.  If the bit is one, the IRQ is
+ * level triggered.
+ */
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/systm.h>
+#include <machine/intr_machdep.h>
+
+#define	ELCR_PORT	0x4d0
+#define	ELCR_MASK(irq)	(1 << (irq))
+
+static int elcr_status;
+int elcr_found;
+
+/*
+ * Check to see if we have what looks like a valid ELCR.  We do this by
+ * verifying that IRQs 0, 1, 2, and 13 are all edge triggered.
+ */
+int
+elcr_probe(void)
+{
+	int i;
+
+	elcr_status = inb(ELCR_PORT) | inb(ELCR_PORT + 1) << 8;
+	if ((elcr_status & (ELCR_MASK(0) | ELCR_MASK(1) | ELCR_MASK(2) |
+	    ELCR_MASK(8) | ELCR_MASK(13))) != 0)
+		return (ENXIO);
+	if (bootverbose) {
+		printf("ELCR Found.  ISA IRQs programmed as:\n");
+		for (i = 0; i < 16; i++)
+			printf(" %2d", i);
+		printf("\n");
+		for (i = 0; i < 16; i++)
+			if (elcr_status & ELCR_MASK(i))
+				printf("  L");
+			else
+				printf("  E");
+		printf("\n");
+	}
+	if (resource_disabled("elcr", 0))
+		return (ENXIO);
+	elcr_found = 1;
+	return (0);
+}
+
+/*
+ * Returns 1 for level trigger, 0 for edge.
+ */
+enum intr_trigger
+elcr_read_trigger(u_int irq)
+{
+
+	KASSERT(elcr_found, ("%s: no ELCR was found!", __func__));
+	KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq));
+	if (elcr_status & ELCR_MASK(irq))
+		return (INTR_TRIGGER_LEVEL);
+	else
+		return (INTR_TRIGGER_EDGE);
+}
+
+/*
+ * Set the trigger mode for a specified IRQ.  Mode of 0 means edge triggered,
+ * and a mode of 1 means level triggered.
+ */
+void
+elcr_write_trigger(u_int irq, enum intr_trigger trigger)
+{
+	int new_status;
+
+	KASSERT(elcr_found, ("%s: no ELCR was found!", __func__));
+	KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq));
+	if (trigger == INTR_TRIGGER_LEVEL)
+		new_status = elcr_status | ELCR_MASK(irq);
+	else
+		new_status = elcr_status & ~ELCR_MASK(irq);
+	if (new_status == elcr_status)
+		return;
+	elcr_status = new_status;
+	if (irq >= 8)
+		outb(ELCR_PORT + 1, elcr_status >> 8);
+	else
+		outb(ELCR_PORT, elcr_status & 0xff);
+}
+
+void
+elcr_resume(void)
+{
+
+	KASSERT(elcr_found, ("%s: no ELCR was found!", __func__));
+	outb(ELCR_PORT, elcr_status & 0xff);
+	outb(ELCR_PORT + 1, elcr_status >> 8);
+}
diff --git a/sys/x86/isa/icu.h b/sys/x86/isa/icu.h
new file mode 100644
index 0000000..d7cd87a
--- /dev/null
+++ b/sys/x86/isa/icu.h
@@ -0,0 +1,53 @@
+/*-
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	from: @(#)icu.h	5.6 (Berkeley) 5/9/91
+ * $FreeBSD$
+ */
+
+/*
+ * AT/386 Interrupt Control constants
+ * W. Jolitz 8/89
+ */
+
+#ifndef _X86_ISA_ICU_H_
+#define	_X86_ISA_ICU_H_
+
+#ifdef PC98
+#define	ICU_IMR_OFFSET	2
+#else
+#define	ICU_IMR_OFFSET	1
+#endif
+
+void	atpic_handle_intr(u_int vector, struct trapframe *frame);
+void	atpic_startup(void);
+
+#endif /* !_X86_ISA_ICU_H_ */
diff --git a/sys/x86/isa/isa.c b/sys/x86/isa/isa.c
new file mode 100644
index 0000000..7b2982a
--- /dev/null
+++ b/sys/x86/isa/isa.c
@@ -0,0 +1,265 @@
+/*-
+ * Copyright (c) 1998 Doug Rabson
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*-
+ * Modifications for Intel architecture by Garrett A. Wollman.
+ * Copyright 1998 Massachusetts Institute of Technology
+ *
+ * Permission to use, copy, modify, and distribute this software and
+ * its documentation for any purpose and without fee is hereby
+ * granted, provided that both the above copyright notice and this
+ * permission notice appear in all copies, that both the above
+ * copyright notice and this permission notice appear in all
+ * supporting documentation, and that the name of M.I.T. not be used
+ * in advertising or publicity pertaining to distribution of the
+ * software without specific, written prior permission.  M.I.T. makes
+ * no representations about the suitability of this software for any
+ * purpose.  It is provided "as is" without express or implied
+ * warranty.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''.  M.I.T. DISCLAIMS
+ * ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
+ * SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <machine/bus.h>
+#include <sys/rman.h>
+#ifdef PC98
+#include <sys/systm.h>
+#endif
+
+#include <machine/resource.h>
+
+#include <isa/isavar.h>
+#include <isa/isa_common.h>
+
+void
+isa_init(device_t dev)
+{
+}
+
+/*
+ * This implementation simply passes the request up to the parent
+ * bus, which in our case is the special i386 nexus, substituting any
+ * configured values if the caller defaulted.  We can get away with
+ * this because there is no special mapping for ISA resources on an Intel
+ * platform.  When porting this code to another architecture, it may be
+ * necessary to interpose a mapping layer here.
+ */
+struct resource *
+isa_alloc_resource(device_t bus, device_t child, int type, int *rid,
+		   u_long start, u_long end, u_long count, u_int flags)
+{
+	/*
+	 * Consider adding a resource definition.
+	 */
+	int passthrough = (device_get_parent(child) != bus);
+	int isdefault = (start == 0UL && end == ~0UL);
+	struct isa_device* idev = DEVTOISA(child);
+	struct resource_list *rl = &idev->id_resources;
+	struct resource_list_entry *rle;
+	
+	if (!passthrough && !isdefault) {
+		rle = resource_list_find(rl, type, *rid);
+		if (!rle) {
+			if (*rid < 0)
+				return 0;
+			switch (type) {
+			case SYS_RES_IRQ:
+				if (*rid >= ISA_NIRQ)
+					return 0;
+				break;
+			case SYS_RES_DRQ:
+				if (*rid >= ISA_NDRQ)
+					return 0;
+				break;
+			case SYS_RES_MEMORY:
+				if (*rid >= ISA_NMEM)
+					return 0;
+				break;
+			case SYS_RES_IOPORT:
+				if (*rid >= ISA_NPORT)
+					return 0;
+				break;
+			default:
+				return 0;
+			}
+			resource_list_add(rl, type, *rid, start, end, count);
+		}
+	}
+
+	return resource_list_alloc(rl, bus, child, type, rid,
+				   start, end, count, flags);
+}
+
+#ifdef PC98
+/*
+ * Indirection support.  The type of bus_space_handle_t is
+ * defined in sys/i386/include/bus_pc98.h.
+ */
+struct resource *
+isa_alloc_resourcev(device_t child, int type, int *rid,
+		    bus_addr_t *res, bus_size_t count, u_int flags)
+{
+	struct isa_device* idev = DEVTOISA(child);
+	struct resource_list *rl = &idev->id_resources;
+
+	device_t	bus = device_get_parent(child);
+	bus_addr_t	start;
+	bus_space_handle_t bh;
+	struct resource *re;
+	struct resource	**bsre;
+	int		i, j, k, linear_cnt, ressz, bsrid;
+
+	start = bus_get_resource_start(child, type, *rid);
+
+	linear_cnt = count;
+	ressz = 1;
+	for (i = 1; i < count; ++i) {
+		if (res[i] != res[i - 1] + 1) {
+			if (i < linear_cnt)
+				linear_cnt = i;
+			++ressz;
+		}
+	}
+
+	re = isa_alloc_resource(bus, child, type, rid,
+				start + res[0], start + res[linear_cnt - 1],
+				linear_cnt, flags);
+	if (re == NULL)
+		return NULL;
+
+	bsre = malloc(sizeof (struct resource *) * ressz, M_DEVBUF, M_NOWAIT);
+	if (bsre == NULL) {
+		resource_list_release(rl, bus, child, type, *rid, re);
+		return NULL;
+	}
+	bsre[0] = re;
+
+	for (i = linear_cnt, k = 1; i < count; i = j, k++) {
+		for (j = i + 1; j < count; j++) {
+			if (res[j] != res[j - 1] + 1)
+				break;
+		}
+		bsrid = *rid + k;
+		bsre[k] = isa_alloc_resource(bus, child, type, &bsrid,
+			start + res[i], start + res[j - 1], j - i, flags);
+		if (bsre[k] == NULL) {
+			for (k--; k >= 0; k--)
+				resource_list_release(rl, bus, child, type,
+						      *rid + k, bsre[k]);
+			free(bsre, M_DEVBUF);
+			return NULL;
+		}
+	}
+
+	bh = rman_get_bushandle(re);
+	bh->bsh_res = bsre;
+	bh->bsh_ressz = ressz;
+
+	return re;
+}
+
+int
+isa_load_resourcev(struct resource *re, bus_addr_t *res, bus_size_t count)
+{
+
+	return bus_space_map_load(rman_get_bustag(re), rman_get_bushandle(re),
+				  count, res, 0);
+}
+#endif	/* PC98 */
+
+int
+isa_release_resource(device_t bus, device_t child, int type, int rid,
+		     struct resource *r)
+{
+	struct isa_device* idev = DEVTOISA(child);
+	struct resource_list *rl = &idev->id_resources;
+#ifdef PC98
+	/*
+	 * Indirection support.  The type of bus_space_handle_t is
+	 * defined in sys/i386/include/bus_pc98.h.
+	 */
+	int	i;
+	bus_space_handle_t bh;
+
+	if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) {
+		bh = rman_get_bushandle(r);
+		if (bh != NULL) {
+			for (i = 1; i < bh->bsh_ressz; i++)
+				resource_list_release(rl, bus, child, type,
+						      rid + i, bh->bsh_res[i]);
+			if (bh->bsh_res != NULL)
+				free(bh->bsh_res, M_DEVBUF);
+		}
+	}
+#endif
+	return resource_list_release(rl, bus, child, type, rid, r);
+}
+
+/*
+ * We can't use the bus_generic_* versions of these methods because those
+ * methods always pass the bus param as the requesting device, and we need
+ * to pass the child (the i386 nexus knows about this and is prepared to
+ * deal).
+ */
+int
+isa_setup_intr(device_t bus, device_t child, struct resource *r, int flags,
+	       driver_filter_t *filter, void (*ihand)(void *), void *arg,
+	       void **cookiep)
+{
+	return (BUS_SETUP_INTR(device_get_parent(bus), child, r, flags,
+			       filter, ihand, arg, cookiep));
+}
+
+int
+isa_teardown_intr(device_t bus, device_t child, struct resource *r,
+		  void *cookie)
+{
+	return (BUS_TEARDOWN_INTR(device_get_parent(bus), child, r, cookie));
+}
+
+/*
+ * On this platform, isa can also attach to the legacy bus.
+ */
+DRIVER_MODULE(isa, legacy, isa_driver, isa_devclass, 0, 0);
diff --git a/sys/x86/isa/isa.h b/sys/x86/isa/isa.h
new file mode 100644
index 0000000..78bd956
--- /dev/null
+++ b/sys/x86/isa/isa.h
@@ -0,0 +1,102 @@
+/*-
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	from: @(#)isa.h	5.7 (Berkeley) 5/9/91
+ * $FreeBSD$
+ */
+
+#ifdef PC98
+#error isa.h is included from PC-9801 source
+#endif
+
+#ifndef _X86_ISA_ISA_H_
+#define	_X86_ISA_ISA_H_
+
+/* BEWARE:  Included in both assembler and C code */
+
+/*
+ * ISA Bus conventions
+ */
+
+/*
+ * Input / Output Port Assignments
+ */
+#ifndef IO_ISABEGIN
+#define	IO_ISABEGIN	0x000		/* 0x000 - Beginning of I/O Registers */
+
+		/* CPU Board */
+#define	IO_ICU1		0x020		/* 8259A Interrupt Controller #1 */
+#define	IO_PMP1		0x026		/* 82347 Power Management Peripheral */
+#define	IO_KBD		0x060		/* 8042 Keyboard */
+#define	IO_RTC		0x070		/* RTC */
+#define	IO_NMI		IO_RTC		/* NMI Control */
+#define	IO_ICU2		0x0A0		/* 8259A Interrupt Controller #2 */
+
+		/* Cards */
+#define	IO_VGA		0x3C0		/* E/VGA Ports */
+#define	IO_CGA		0x3D0		/* CGA Ports */
+#define	IO_MDA		0x3B0		/* Monochome Adapter */
+
+#define	IO_ISAEND	0x3FF		/* End (actually Max) of I/O Regs */
+#endif /* !IO_ISABEGIN */
+
+/*
+ * Input / Output Port Sizes - these are from several sources, and tend
+ * to be the larger of what was found.
+ */
+#ifndef	IO_ISASIZES
+#define	IO_ISASIZES
+
+#define	IO_CGASIZE	12		/* CGA controllers */
+#define	IO_MDASIZE	12		/* Monochrome display controllers */
+#define	IO_VGASIZE	16		/* VGA controllers */
+
+#endif /* !IO_ISASIZES */
+
+/*
+ * Input / Output Memory Physical Addresses
+ */
+#ifndef	IOM_BEGIN
+#define	IOM_BEGIN	0x0A0000	/* Start of I/O Memory "hole" */
+#define	IOM_END		0x100000	/* End of I/O Memory "hole" */
+#define	IOM_SIZE	(IOM_END - IOM_BEGIN)
+#endif /* !IOM_BEGIN */
+
+/*
+ * RAM Physical Address Space (ignoring the above mentioned "hole")
+ */
+#ifndef	RAM_BEGIN
+#define	RAM_BEGIN	0x0000000	/* Start of RAM Memory */
+#define	RAM_END		0x1000000	/* End of RAM Memory */
+#define	RAM_SIZE	(RAM_END - RAM_BEGIN)
+#endif /* !RAM_BEGIN */
+
+#endif /* !_X86_ISA_ISA_H_ */
diff --git a/sys/x86/isa/isa_dma.c b/sys/x86/isa/isa_dma.c
new file mode 100644
index 0000000..cbc9959
--- /dev/null
+++ b/sys/x86/isa/isa_dma.c
@@ -0,0 +1,611 @@
+/*-
+ * Copyright (c) 1991 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	from: @(#)isa.c	7.2 (Berkeley) 5/13/91
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * code to manage AT bus
+ *
+ * 92/08/18  Frank P. MacLachlan (fpm@crash.cts.com):
+ * Fixed uninitialized variable problem and added code to deal
+ * with DMA page boundaries in isa_dmarangecheck().  Fixed word
+ * mode DMA count compution and reorganized DMA setup code in
+ * isa_dmastart()
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/lock.h>
+#include <sys/proc.h>
+#include <sys/mutex.h>
+#include <sys/module.h>
+#include <vm/vm.h>
+#include <vm/vm_param.h>
+#include <vm/pmap.h>
+#include <isa/isareg.h>
+#include <isa/isavar.h>
+#include <isa/isa_dmareg.h>
+
+#define	ISARAM_END	RAM_END
+
+static int isa_dmarangecheck(caddr_t va, u_int length, int chan);
+
+static caddr_t	dma_bouncebuf[8];
+static u_int	dma_bouncebufsize[8];
+static u_int8_t	dma_bounced = 0;
+static u_int8_t	dma_busy = 0;		/* Used in isa_dmastart() */
+static u_int8_t	dma_inuse = 0;		/* User for acquire/release */
+static u_int8_t dma_auto_mode = 0;
+static struct mtx isa_dma_lock;
+MTX_SYSINIT(isa_dma_lock, &isa_dma_lock, "isa DMA lock", MTX_DEF);
+
+#define VALID_DMA_MASK (7)
+
+/* high byte of address is stored in this port for i-th dma channel */
+static int dmapageport[8] = { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a };
+
+/*
+ * Setup a DMA channel's bounce buffer.
+ */
+int
+isa_dma_init(int chan, u_int bouncebufsize, int flag)
+{
+	void *buf;
+	int contig;
+
+#ifdef DIAGNOSTIC
+	if (chan & ~VALID_DMA_MASK)
+		panic("isa_dma_init: channel out of range");
+#endif
+
+
+	/* Try malloc() first.  It works better if it works. */
+	buf = malloc(bouncebufsize, M_DEVBUF, flag);
+	if (buf != NULL) {
+		if (isa_dmarangecheck(buf, bouncebufsize, chan) != 0) {
+			free(buf, M_DEVBUF);
+			buf = NULL;
+		}
+		contig = 0;
+	}
+
+	if (buf == NULL) {
+		buf = contigmalloc(bouncebufsize, M_DEVBUF, flag, 0ul, 0xfffffful,
+			   1ul, chan & 4 ? 0x20000ul : 0x10000ul);
+		contig = 1;
+	}
+
+	if (buf == NULL)
+		return (ENOMEM);
+
+	mtx_lock(&isa_dma_lock);
+	/*
+	 * If a DMA channel is shared, both drivers have to call isa_dma_init
+	 * since they don't know that the other driver will do it.
+	 * Just return if we're already set up good.
+	 * XXX: this only works if they agree on the bouncebuf size.  This
+	 * XXX: is typically the case since they are multiple instances of
+	 * XXX: the same driver.
+	 */
+	if (dma_bouncebuf[chan] != NULL) {
+		if (contig)
+			contigfree(buf, bouncebufsize, M_DEVBUF);
+		else
+			free(buf, M_DEVBUF);
+		mtx_unlock(&isa_dma_lock);
+		return (0);
+	}
+
+	dma_bouncebufsize[chan] = bouncebufsize;
+	dma_bouncebuf[chan] = buf;
+
+	mtx_unlock(&isa_dma_lock);
+
+	return (0);
+}
+
+/*
+ * Register a DMA channel's usage.  Usually called from a device driver
+ * in open() or during its initialization.
+ */
+int
+isa_dma_acquire(chan)
+	int chan;
+{
+#ifdef DIAGNOSTIC
+	if (chan & ~VALID_DMA_MASK)
+		panic("isa_dma_acquire: channel out of range");
+#endif
+
+	mtx_lock(&isa_dma_lock);
+	if (dma_inuse & (1 << chan)) {
+		printf("isa_dma_acquire: channel %d already in use\n", chan);
+		mtx_unlock(&isa_dma_lock);
+		return (EBUSY);
+	}
+	dma_inuse |= (1 << chan);
+	dma_auto_mode &= ~(1 << chan);
+	mtx_unlock(&isa_dma_lock);
+
+	return (0);
+}
+
+/*
+ * Unregister a DMA channel's usage.  Usually called from a device driver
+ * during close() or during its shutdown.
+ */
+void
+isa_dma_release(chan)
+	int chan;
+{
+#ifdef DIAGNOSTIC
+	if (chan & ~VALID_DMA_MASK)
+		panic("isa_dma_release: channel out of range");
+
+	mtx_lock(&isa_dma_lock);
+	if ((dma_inuse & (1 << chan)) == 0)
+		printf("isa_dma_release: channel %d not in use\n", chan);
+#else
+	mtx_lock(&isa_dma_lock);
+#endif
+
+	if (dma_busy & (1 << chan)) {
+		dma_busy &= ~(1 << chan);
+		/* 
+		 * XXX We should also do "dma_bounced &= (1 << chan);"
+		 * because we are acting on behalf of isa_dmadone() which
+		 * was not called to end the last DMA operation.  This does
+		 * not matter now, but it may in the future.
+		 */
+	}
+
+	dma_inuse &= ~(1 << chan);
+	dma_auto_mode &= ~(1 << chan);
+
+	mtx_unlock(&isa_dma_lock);
+}
+
+/*
+ * isa_dmacascade(): program 8237 DMA controller channel to accept
+ * external dma control by a board.
+ */
+void
+isa_dmacascade(chan)
+	int chan;
+{
+#ifdef DIAGNOSTIC
+	if (chan & ~VALID_DMA_MASK)
+		panic("isa_dmacascade: channel out of range");
+#endif
+
+	mtx_lock(&isa_dma_lock);
+	/* set dma channel mode, and set dma channel mode */
+	if ((chan & 4) == 0) {
+		outb(DMA1_MODE, DMA37MD_CASCADE | chan);
+		outb(DMA1_SMSK, chan);
+	} else {
+		outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3));
+		outb(DMA2_SMSK, chan & 3);
+	}
+	mtx_unlock(&isa_dma_lock);
+}
+
+/*
+ * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment
+ * problems by using a bounce buffer.
+ */
+void
+isa_dmastart(int flags, caddr_t addr, u_int nbytes, int chan)
+{
+	vm_paddr_t phys;
+	int waport;
+	caddr_t newaddr;
+	int dma_range_checked;
+
+	/* translate to physical */
+	phys = pmap_extract(kernel_pmap, (vm_offset_t)addr);
+	dma_range_checked = isa_dmarangecheck(addr, nbytes, chan);
+
+#ifdef DIAGNOSTIC
+	if (chan & ~VALID_DMA_MASK)
+		panic("isa_dmastart: channel out of range");
+
+	if ((chan < 4 && nbytes > (1<<16))
+	    || (chan >= 4 && (nbytes > (1<<17) || (uintptr_t)addr & 1)))
+		panic("isa_dmastart: impossible request");
+
+	mtx_lock(&isa_dma_lock);
+	if ((dma_inuse & (1 << chan)) == 0)
+		printf("isa_dmastart: channel %d not acquired\n", chan);
+#else
+	mtx_lock(&isa_dma_lock);
+#endif
+
+#if 0
+	/*
+	 * XXX This should be checked, but drivers like ad1848 only call
+	 * isa_dmastart() once because they use Auto DMA mode.  If we
+	 * leave this in, drivers that do this will print this continuously.
+	 */
+	if (dma_busy & (1 << chan))
+		printf("isa_dmastart: channel %d busy\n", chan);
+#endif
+
+	dma_busy |= (1 << chan);
+
+	if (dma_range_checked) {
+		if (dma_bouncebuf[chan] == NULL
+		    || dma_bouncebufsize[chan] < nbytes)
+			panic("isa_dmastart: bad bounce buffer"); 
+		dma_bounced |= (1 << chan);
+		newaddr = dma_bouncebuf[chan];
+
+		/* copy bounce buffer on write */
+		if (!(flags & ISADMA_READ))
+			bcopy(addr, newaddr, nbytes);
+		addr = newaddr;
+	}
+
+	if (flags & ISADMA_RAW) {
+	    dma_auto_mode |= (1 << chan);
+	} else { 
+	    dma_auto_mode &= ~(1 << chan);
+	}
+
+	if ((chan & 4) == 0) {
+		/*
+		 * Program one of DMA channels 0..3.  These are
+		 * byte mode channels.
+		 */
+		/* set dma channel mode, and reset address ff */
+
+		/* If ISADMA_RAW flag is set, then use autoinitialise mode */
+		if (flags & ISADMA_RAW) {
+		  if (flags & ISADMA_READ)
+			outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_WRITE|chan);
+		  else
+			outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_READ|chan);
+		}
+		else
+		if (flags & ISADMA_READ)
+			outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan);
+		else
+			outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan);
+		outb(DMA1_FFC, 0);
+
+		/* send start address */
+		waport =  DMA1_CHN(chan);
+		outb(waport, phys);
+		outb(waport, phys>>8);
+		outb(dmapageport[chan], phys>>16);
+
+		/* send count */
+		outb(waport + 1, --nbytes);
+		outb(waport + 1, nbytes>>8);
+
+		/* unmask channel */
+		outb(DMA1_SMSK, chan);
+	} else {
+		/*
+		 * Program one of DMA channels 4..7.  These are
+		 * word mode channels.
+		 */
+		/* set dma channel mode, and reset address ff */
+
+		/* If ISADMA_RAW flag is set, then use autoinitialise mode */
+		if (flags & ISADMA_RAW) {
+		  if (flags & ISADMA_READ)
+			outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_WRITE|(chan&3));
+		  else
+			outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_READ|(chan&3));
+		}
+		else
+		if (flags & ISADMA_READ)
+			outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3));
+		else
+			outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3));
+		outb(DMA2_FFC, 0);
+
+		/* send start address */
+		waport = DMA2_CHN(chan - 4);
+		outb(waport, phys>>1);
+		outb(waport, phys>>9);
+		outb(dmapageport[chan], phys>>16);
+
+		/* send count */
+		nbytes >>= 1;
+		outb(waport + 2, --nbytes);
+		outb(waport + 2, nbytes>>8);
+
+		/* unmask channel */
+		outb(DMA2_SMSK, chan & 3);
+	}
+	mtx_unlock(&isa_dma_lock);
+}
+
+void
+isa_dmadone(int flags, caddr_t addr, int nbytes, int chan)
+{  
+#ifdef DIAGNOSTIC
+	if (chan & ~VALID_DMA_MASK)
+		panic("isa_dmadone: channel out of range");
+
+	if ((dma_inuse & (1 << chan)) == 0)
+		printf("isa_dmadone: channel %d not acquired\n", chan);
+#endif
+
+	mtx_lock(&isa_dma_lock);
+	if (((dma_busy & (1 << chan)) == 0) && 
+	    (dma_auto_mode & (1 << chan)) == 0 )
+		printf("isa_dmadone: channel %d not busy\n", chan);
+
+	if ((dma_auto_mode & (1 << chan)) == 0)
+		outb(chan & 4 ? DMA2_SMSK : DMA1_SMSK, (chan & 3) | 4);
+
+	if (dma_bounced & (1 << chan)) {
+		/* copy bounce buffer on read */
+		if (flags & ISADMA_READ)
+			bcopy(dma_bouncebuf[chan], addr, nbytes);
+
+		dma_bounced &= ~(1 << chan);
+	}
+	dma_busy &= ~(1 << chan);
+	mtx_unlock(&isa_dma_lock);
+}
+
+/*
+ * Check for problems with the address range of a DMA transfer
+ * (non-contiguous physical pages, outside of bus address space,
+ * crossing DMA page boundaries).
+ * Return true if special handling needed.
+ */
+
+static int
+isa_dmarangecheck(caddr_t va, u_int length, int chan)
+{
+	vm_paddr_t phys, priorpage = 0;
+	vm_offset_t endva;
+	u_int dma_pgmsk = (chan & 4) ?  ~(128*1024-1) : ~(64*1024-1);
+
+	endva = (vm_offset_t)round_page((vm_offset_t)va + length);
+	for (; va < (caddr_t) endva ; va += PAGE_SIZE) {
+		phys = trunc_page(pmap_extract(kernel_pmap, (vm_offset_t)va));
+		if (phys == 0)
+			panic("isa_dmacheck: no physical page present");
+		if (phys >= ISARAM_END)
+			return (1);
+		if (priorpage) {
+			if (priorpage + PAGE_SIZE != phys)
+				return (1);
+			/* check if crossing a DMA page boundary */
+			if (((u_int)priorpage ^ (u_int)phys) & dma_pgmsk)
+				return (1);
+		}
+		priorpage = phys;
+	}
+	return (0);
+}
+
+/*
+ * Query the progress of a transfer on a DMA channel.
+ *
+ * To avoid having to interrupt a transfer in progress, we sample
+ * each of the high and low databytes twice, and apply the following
+ * logic to determine the correct count.
+ *
+ * Reads are performed with interrupts disabled, thus it is to be
+ * expected that the time between reads is very small.  At most
+ * one rollover in the low count byte can be expected within the
+ * four reads that are performed.
+ *
+ * There are three gaps in which a rollover can occur :
+ *
+ * - read low1
+ *              gap1
+ * - read high1
+ *              gap2
+ * - read low2
+ *              gap3
+ * - read high2
+ *
+ * If a rollover occurs in gap1 or gap2, the low2 value will be
+ * greater than the low1 value.  In this case, low2 and high2 are a
+ * corresponding pair. 
+ *
+ * In any other case, low1 and high1 can be considered to be correct.
+ *
+ * The function returns the number of bytes remaining in the transfer,
+ * or -1 if the channel requested is not active.
+ *
+ */
+static int
+isa_dmastatus_locked(int chan)
+{
+	u_long	cnt = 0;
+	int	ffport, waport;
+	u_long	low1, high1, low2, high2;
+
+	mtx_assert(&isa_dma_lock, MA_OWNED);
+
+	/* channel active? */
+	if ((dma_inuse & (1 << chan)) == 0) {
+		printf("isa_dmastatus: channel %d not active\n", chan);
+		return(-1);
+	}
+	/* channel busy? */
+
+	if (((dma_busy & (1 << chan)) == 0) &&
+	    (dma_auto_mode & (1 << chan)) == 0 ) {
+	    printf("chan %d not busy\n", chan);
+	    return -2 ;
+	}	
+	if (chan < 4) {			/* low DMA controller */
+		ffport = DMA1_FFC;
+		waport = DMA1_CHN(chan) + 1;
+	} else {			/* high DMA controller */
+		ffport = DMA2_FFC;
+		waport = DMA2_CHN(chan - 4) + 2;
+	}
+
+	disable_intr();			/* no interrupts Mr Jones! */
+	outb(ffport, 0);		/* clear register LSB flipflop */
+	low1 = inb(waport);
+	high1 = inb(waport);
+	outb(ffport, 0);		/* clear again */
+	low2 = inb(waport);
+	high2 = inb(waport);
+	enable_intr();			/* enable interrupts again */
+
+	/* 
+	 * Now decide if a wrap has tried to skew our results.
+	 * Note that after TC, the count will read 0xffff, while we want 
+	 * to return zero, so we add and then mask to compensate.
+	 */
+	if (low1 >= low2) {
+		cnt = (low1 + (high1 << 8) + 1) & 0xffff;
+	} else {
+		cnt = (low2 + (high2 << 8) + 1) & 0xffff;
+	}
+
+	if (chan >= 4)			/* high channels move words */
+		cnt *= 2;
+	return(cnt);
+}
+
+int
+isa_dmastatus(int chan)
+{
+	int status;
+
+	mtx_lock(&isa_dma_lock);
+	status = isa_dmastatus_locked(chan);
+	mtx_unlock(&isa_dma_lock);
+
+	return (status);
+}
+
+/*
+ * Reached terminal count yet ?
+ */
+int
+isa_dmatc(int chan)
+{
+
+	if (chan < 4)
+		return(inb(DMA1_STATUS) & (1 << chan));
+	else
+		return(inb(DMA2_STATUS) & (1 << (chan & 3)));
+}
+
+/*
+ * Stop a DMA transfer currently in progress.
+ */
+int
+isa_dmastop(int chan) 
+{
+	int status;
+
+	mtx_lock(&isa_dma_lock);
+	if ((dma_inuse & (1 << chan)) == 0)
+		printf("isa_dmastop: channel %d not acquired\n", chan);  
+
+	if (((dma_busy & (1 << chan)) == 0) &&
+	    ((dma_auto_mode & (1 << chan)) == 0)) {
+		printf("chan %d not busy\n", chan);
+		mtx_unlock(&isa_dma_lock);
+		return -2 ;
+	}
+    
+	if ((chan & 4) == 0) {
+		outb(DMA1_SMSK, (chan & 3) | 4 /* disable mask */);
+	} else {
+		outb(DMA2_SMSK, (chan & 3) | 4 /* disable mask */);
+	}
+
+	status = isa_dmastatus_locked(chan);
+
+	mtx_unlock(&isa_dma_lock);
+
+	return (status);
+}
+
+/*
+ * Attach to the ISA PnP descriptor for the AT DMA controller
+ */
+static struct isa_pnp_id atdma_ids[] = {
+	{ 0x0002d041 /* PNP0200 */, "AT DMA controller" },
+	{ 0 }
+};
+
+static int
+atdma_probe(device_t dev)
+{
+	int result;
+	
+	if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, atdma_ids)) <= 0)
+		device_quiet(dev);
+	return(result);
+}
+
+static int
+atdma_attach(device_t dev)
+{
+	return(0);
+}
+
+static device_method_t atdma_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		atdma_probe),
+	DEVMETHOD(device_attach,	atdma_attach),
+	DEVMETHOD(device_detach,	bus_generic_detach),
+	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
+	DEVMETHOD(device_suspend,	bus_generic_suspend),
+	DEVMETHOD(device_resume,	bus_generic_resume),
+	{ 0, 0 }
+};
+
+static driver_t atdma_driver = {
+	"atdma",
+	atdma_methods,
+	1,		/* no softc */
+};
+
+static devclass_t atdma_devclass;
+
+DRIVER_MODULE(atdma, isa, atdma_driver, atdma_devclass, 0, 0);
+DRIVER_MODULE(atdma, acpi, atdma_driver, atdma_devclass, 0, 0);
diff --git a/sys/x86/isa/nmi.c b/sys/x86/isa/nmi.c
new file mode 100644
index 0000000..db5550c
--- /dev/null
+++ b/sys/x86/isa/nmi.c
@@ -0,0 +1,107 @@
+/*-
+ * Copyright (c) 1991 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	from: @(#)isa.c	7.2 (Berkeley) 5/13/91
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include "opt_mca.h"
+
+#include <sys/types.h>
+#include <sys/syslog.h>
+#include <sys/systm.h>
+
+#include <machine/md_var.h>
+
+#ifdef DEV_MCA
+#include <i386/bios/mca_machdep.h>
+#endif
+
+#define NMI_PARITY (1 << 7)
+#define NMI_IOCHAN (1 << 6)
+#define ENMI_WATCHDOG (1 << 7)
+#define ENMI_BUSTIMER (1 << 6)
+#define ENMI_IOSTATUS (1 << 5)
+
+/*
+ * Handle a NMI, possibly a machine check.
+ * return true to panic system, false to ignore.
+ */
+int
+isa_nmi(int cd)
+{
+	int retval = 0;
+	int isa_port = inb(0x61);
+	int eisa_port = inb(0x461);
+
+	log(LOG_CRIT, "NMI ISA %x, EISA %x\n", isa_port, eisa_port);
+#ifdef DEV_MCA
+	if (MCA_system && mca_bus_nmi())
+		return(0);
+#endif
+	
+	if (isa_port & NMI_PARITY) {
+		log(LOG_CRIT, "RAM parity error, likely hardware failure.");
+		retval = 1;
+	}
+
+	if (isa_port & NMI_IOCHAN) {
+		log(LOG_CRIT, "I/O channel check, likely hardware failure.");
+		retval = 1;
+	}
+
+	/*
+	 * On a real EISA machine, this will never happen.  However it can
+	 * happen on ISA machines which implement XT style floating point
+	 * error handling (very rare).  Save them from a meaningless panic.
+	 */
+	if (eisa_port == 0xff)
+		return(retval);
+
+	if (eisa_port & ENMI_WATCHDOG) {
+		log(LOG_CRIT, "EISA watchdog timer expired, likely hardware failure.");
+		retval = 1;
+	}
+
+	if (eisa_port & ENMI_BUSTIMER) {
+		log(LOG_CRIT, "EISA bus timeout, likely hardware failure.");
+		retval = 1;
+	}
+
+	if (eisa_port & ENMI_IOSTATUS) {
+		log(LOG_CRIT, "EISA I/O port status error.");
+		retval = 1;
+	}
+
+	return(retval);
+}
diff --git a/sys/x86/isa/orm.c b/sys/x86/isa/orm.c
new file mode 100644
index 0000000..f25312f
--- /dev/null
+++ b/sys/x86/isa/orm.c
@@ -0,0 +1,185 @@
+/*-
+ * Copyright (c) 2000 Nikolai Saoukh
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * Driver to take care of holes in ISA I/O memory occupied
+ * by option rom(s)
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+
+#include <sys/module.h>
+#include <sys/bus.h>
+
+#include <machine/bus.h>
+#include <machine/resource.h>
+#include <sys/rman.h>
+
+#include <isa/isavar.h>
+#include <isa/pnpvar.h>
+
+#define	IOMEM_START	0x0a0000
+#define	IOMEM_STEP	0x000800
+#define	IOMEM_END	0x100000
+
+#define	ORM_ID	0x00004d3e
+
+static struct isa_pnp_id orm_ids[] = {
+	{ ORM_ID,	NULL },		/* ORM0000 */
+	{ 0,		NULL },
+};
+
+#define MAX_ROMS	16
+
+struct orm_softc {
+	int		rnum;
+	int		rid[MAX_ROMS];
+	struct resource *res[MAX_ROMS];
+};
+
+static int
+orm_probe(device_t dev)
+{
+	return (ISA_PNP_PROBE(device_get_parent(dev), dev, orm_ids));
+}
+
+static int
+orm_attach(device_t dev)
+{
+	return (0);
+}
+
+static void
+orm_identify(driver_t* driver, device_t parent)
+{
+	bus_space_handle_t	bh;
+	bus_space_tag_t		bt;
+	device_t		child;
+	u_int32_t		chunk = IOMEM_START;
+	struct resource		*res;
+	int			rid;
+	u_int32_t		rom_size;
+	struct orm_softc	*sc;
+	u_int8_t		buf[3];
+
+	child = BUS_ADD_CHILD(parent, ISA_ORDER_SENSITIVE, "orm", -1);
+	device_set_driver(child, driver);
+	isa_set_logicalid(child, ORM_ID);
+	isa_set_vendorid(child, ORM_ID);
+	sc = device_get_softc(child);
+	sc->rnum = 0;
+	while (chunk < IOMEM_END) {
+		bus_set_resource(child, SYS_RES_MEMORY, sc->rnum, chunk,
+		    IOMEM_STEP);
+		rid = sc->rnum;
+		res = bus_alloc_resource_any(child, SYS_RES_MEMORY, &rid,
+		    RF_ACTIVE);
+		if (res == NULL) {
+			bus_delete_resource(child, SYS_RES_MEMORY, sc->rnum);
+			chunk += IOMEM_STEP;
+			continue;
+		}
+		bt = rman_get_bustag(res);
+		bh = rman_get_bushandle(res);
+		bus_space_read_region_1(bt, bh, 0, buf, sizeof(buf));
+
+		/*
+		 * We need to release and delete the resource since we're
+		 * changing its size, or the rom isn't there.  There
+		 * is a checksum field in the ROM to prevent false
+		 * positives.  However, some common hardware (IBM thinkpads)
+		 * neglects to put a valid checksum in the ROM, so we do
+		 * not double check the checksum here.  On the ISA bus
+		 * areas that have no hardware read back as 0xff, so the
+		 * tests to see if we have 0x55 followed by 0xaa are
+		 * generally sufficient.
+		 */
+		bus_release_resource(child, SYS_RES_MEMORY, rid, res);
+		bus_delete_resource(child, SYS_RES_MEMORY, sc->rnum);
+		if (buf[0] != 0x55 || buf[1] != 0xAA || (buf[2] & 0x03) != 0) {
+			chunk += IOMEM_STEP;
+			continue;
+		}
+		rom_size = buf[2] << 9;
+		bus_set_resource(child, SYS_RES_MEMORY, sc->rnum, chunk,
+		    rom_size);
+		rid = sc->rnum;
+		res = bus_alloc_resource_any(child, SYS_RES_MEMORY, &rid, 0);
+		if (res == NULL) {
+			bus_delete_resource(child, SYS_RES_MEMORY, sc->rnum);
+			chunk += IOMEM_STEP;
+			continue;
+		}
+		sc->rid[sc->rnum] = rid;
+		sc->res[sc->rnum] = res;
+		sc->rnum++;
+		chunk += rom_size;
+	}
+
+	if (sc->rnum == 0)
+		device_delete_child(parent, child);
+	else if (sc->rnum == 1)
+		device_set_desc(child, "ISA Option ROM");
+	else
+		device_set_desc(child, "ISA Option ROMs");
+}
+
+static int
+orm_detach(device_t dev)
+{
+	int			i;
+	struct orm_softc	*sc = device_get_softc(dev);
+	
+	for (i = 0; i < sc->rnum; i++)
+		bus_release_resource(dev, SYS_RES_MEMORY, sc->rid[i],
+		    sc->res[i]);
+	return (0);
+}
+
+static device_method_t orm_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_identify,	orm_identify),
+	DEVMETHOD(device_probe,		orm_probe),
+	DEVMETHOD(device_attach,	orm_attach),
+	DEVMETHOD(device_detach,	orm_detach),
+	{ 0, 0 }
+};
+
+static driver_t orm_driver = {
+	"orm",
+	orm_methods,
+	sizeof (struct orm_softc)
+};
+
+static devclass_t orm_devclass;
+
+DRIVER_MODULE(orm, isa, orm_driver, orm_devclass, 0, 0);