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author | gnn <gnn@FreeBSD.org> | 2010-03-03 15:05:58 +0000 |
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committer | gnn <gnn@FreeBSD.org> | 2010-03-03 15:05:58 +0000 |
commit | acf511e4d0cb788a9a050ea1aefef0548aa329ab (patch) | |
tree | 42725ebf07ce966c74facdca56635db531cdc299 /sys/sys/pmc.h | |
parent | 8fcfbfddca984ab42754b8807ddd5edfd7de8fbf (diff) | |
download | FreeBSD-src-acf511e4d0cb788a9a050ea1aefef0548aa329ab.zip FreeBSD-src-acf511e4d0cb788a9a050ea1aefef0548aa329ab.tar.gz |
Add support for hwpmc(4) on the MIPS 24K, 32 bit, embedded processor.
Add macros for properly accessing coprocessor 0 registers that
support performance counters.
Reviewed by: jkoshy rpaulo fabien imp
MFC after: 1 month
Diffstat (limited to 'sys/sys/pmc.h')
-rw-r--r-- | sys/sys/pmc.h | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/sys/sys/pmc.h b/sys/sys/pmc.h index f4a29ce..a689a9b 100644 --- a/sys/sys/pmc.h +++ b/sys/sys/pmc.h @@ -84,8 +84,9 @@ __PMC_CPU(INTEL_CORE2, 0x88, "Intel Core2") \ __PMC_CPU(INTEL_CORE2EXTREME, 0x89, "Intel Core2 Extreme") \ __PMC_CPU(INTEL_ATOM, 0x8A, "Intel Atom") \ - __PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7") \ - __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") + __PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7") \ + __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \ + __PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") enum pmc_cputype { #undef __PMC_CPU @@ -94,7 +95,7 @@ enum pmc_cputype { }; #define PMC_CPU_FIRST PMC_CPU_AMD_K7 -#define PMC_CPU_LAST PMC_CPU_INTEL_XSCALE +#define PMC_CPU_LAST PMC_CPU_MIPS_24K /* * Classes of PMCs @@ -108,8 +109,9 @@ enum pmc_cputype { __PMC_CLASS(P6) /* Intel Pentium Pro counters */ \ __PMC_CLASS(P4) /* Intel Pentium-IV counters */ \ __PMC_CLASS(IAF) /* Intel Core2/Atom, fixed function */ \ - __PMC_CLASS(IAP) /* Intel Core...Atom, programmable */ \ - __PMC_CLASS(XSCALE) /* Intel XScale counters */ + __PMC_CLASS(IAP) /* Intel Core...Atom, programmable */ \ + __PMC_CLASS(XSCALE) /* Intel XScale counters */ \ + __PMC_CLASS(MIPS24K) /* MIPS 24K */ enum pmc_class { #undef __PMC_CLASS @@ -118,7 +120,7 @@ enum pmc_class { }; #define PMC_CLASS_FIRST PMC_CLASS_TSC -#define PMC_CLASS_LAST PMC_CLASS_XSCALE +#define PMC_CLASS_LAST PMC_CLASS_MIPS24K /* * A PMC can be in the following states: |