- Sparsely number enumerations 'pmc_cputype' and 'pmc_event' in order to

  reduce ABI disruptions when new cpu types and new PMC events are added
  in the future.
- Support alternate spellings for PMC events.  Derive the canonical
  spelling of an event name from its enumeration name in 'enum pmc_event'.
- Provide a way for users to disambiguate between identically named events
  supported by multiple classes of PMCs in a CPU.
- Change libpmc's machine-dependent event specifier parsing code to
  better support CPUs containing two or more classes of PMC resources.

1 files changed, 26 insertions, 21 deletions

diff --git a/sys/sys/pmc.h b/sys/sys/pmc.h
index e33f431..d367946 100644
--- a/sys/sys/pmc.h
+++ b/sys/sys/pmc.h
@@ -62,31 +62,36 @@
 	PMC_VERSION_MINOR << 16 | PMC_VERSION_PATCH)
 
 /*
- * Kinds of CPUs known
+ * Kinds of CPUs known.
+ *
+ * We keep track of CPU variants that need to be distinguished in
+ * some way for PMC operations.  CPU names are grouped by manufacturer
+ * and numbered sparsely in order to minimize changes to the ABI involved
+ * when new CPUs are added.
  */
 
-#define	__PMC_CPUS()					\
-	__PMC_CPU(AMD_K7,     "AMD K7")			\
-	__PMC_CPU(AMD_K8,     "AMD K8")			\
-	__PMC_CPU(INTEL_P5,   "Intel Pentium")		\
-	__PMC_CPU(INTEL_P6,   "Intel Pentium Pro")	\
-	__PMC_CPU(INTEL_CL,   "Intel Celeron")		\
-	__PMC_CPU(INTEL_PII,  "Intel Pentium II")	\
-	__PMC_CPU(INTEL_PIII, "Intel Pentium III")	\
-	__PMC_CPU(INTEL_PM,   "Intel Pentium M")	\
-	__PMC_CPU(INTEL_PIV,  "Intel Pentium IV")	\
-	__PMC_CPU(INTEL_CORE, "Intel Core Solo/Duo")	\
-	__PMC_CPU(INTEL_CORE2,"Intel Core2")		\
-	__PMC_CPU(INTEL_ATOM, "Intel Atom")
+#define	__PMC_CPUS()						\
+	__PMC_CPU(AMD_K7,	0x00,	"AMD K7")		\
+	__PMC_CPU(AMD_K8,	0x01,	"AMD K8")		\
+	__PMC_CPU(INTEL_P5,	0x80,	"Intel Pentium")	\
+	__PMC_CPU(INTEL_P6,	0x81,	"Intel Pentium Pro")	\
+	__PMC_CPU(INTEL_CL,	0x82,	"Intel Celeron")	\
+	__PMC_CPU(INTEL_PII,	0x83,	"Intel Pentium II")	\
+	__PMC_CPU(INTEL_PIII,	0x84,	"Intel Pentium III")	\
+	__PMC_CPU(INTEL_PM,	0x85,	"Intel Pentium M")	\
+	__PMC_CPU(INTEL_PIV,	0x86,	"Intel Pentium IV")	\
+	__PMC_CPU(INTEL_CORE,	0x87,	"Intel Core Solo/Duo")	\
+	__PMC_CPU(INTEL_CORE2,	0x88,	"Intel Core2")		\
+	__PMC_CPU(INTEL_ATOM,	0x8A,	"Intel Atom")
 
 enum pmc_cputype {
 #undef	__PMC_CPU
-#define	__PMC_CPU(S,D)	PMC_CPU_##S ,
+#define	__PMC_CPU(S,V,D)	PMC_CPU_##S = V,
 	__PMC_CPUS()
 };
 
 #define	PMC_CPU_FIRST	PMC_CPU_AMD_K7
-#define	PMC_CPU_LAST	PMC_CPU_INTEL_PIV
+#define	PMC_CPU_LAST	PMC_CPU_INTEL_ATOM
 
 /*
  * Classes of PMCs
@@ -109,7 +114,7 @@ enum pmc_class {
 };
 
 #define	PMC_CLASS_FIRST	PMC_CLASS_TSC
-#define	PMC_CLASS_LAST	PMC_CLASS_P4
+#define	PMC_CLASS_LAST	PMC_CLASS_IAP
 
 /*
  * A PMC can be in the following states:
@@ -257,13 +262,12 @@ enum pmc_caps
 
 enum pmc_event {
 #undef	__PMC_EV
-#define	__PMC_EV(C,N,D) PMC_EV_ ## C ## _ ## N ,
+#undef	__PMC_EV_BLOCK
+#define	__PMC_EV_BLOCK(C,V)	PMC_EV_ ## C ## __BLOCK_START = (V) - 1 ,
+#define	__PMC_EV(C,N)		PMC_EV_ ## C ## _ ## N ,
 	__PMC_EVENTS()
 };
 
-#define	PMC_EVENT_FIRST	PMC_EV_TSC_TSC
-#define	PMC_EVENT_LAST	PMC_EV_P5_LAST
-
 /*
  * PMC SYSCALL INTERFACE
  */
@@ -291,6 +295,7 @@ enum pmc_event {
 	__PMC_OP(PMCSTOP, "Start a PMC")				\
 	__PMC_OP(WRITELOG, "Write a cookie to the log file")
 
+
 enum pmc_ops {
 #undef	__PMC_OP
 #define	__PMC_OP(N, D)	PMC_OP_##N,