diff options
| author | tmm <tmm@FreeBSD.org> | 2003-09-04 15:25:10 +0000 |
|---|---|---|
| committer | tmm <tmm@FreeBSD.org> | 2003-09-04 15:25:10 +0000 |
| commit | 6b36b31ebad4a971f11b826046ecd62def189631 (patch) | |
| tree | 221fca05089ec419b6bffd5afd6a0c121220ea23 /sys/sparc64 | |
| parent | 82aeb9fc856d7c45903f5b5a6a613167c959ac57 (diff) | |
| download | FreeBSD-src-6b36b31ebad4a971f11b826046ecd62def189631.zip FreeBSD-src-6b36b31ebad4a971f11b826046ecd62def189631.tar.gz | |
- Clear the CE AFSR bits which indicate the error condition when handling
a correctable DMA error. Failing to do so can cause the error interrupt
to be triggered over and over again.
- Clean up the comments for UEAFSR_* constants, fix a typo (UEAFSR_BLK is
(1 << 23), not (1 << 22)), and add two more. Also, add similar constants
for the CE AFSR bits.
Diffstat (limited to 'sys/sparc64')
| -rw-r--r-- | sys/sparc64/pci/psycho.c | 4 | ||||
| -rw-r--r-- | sys/sparc64/pci/psychoreg.h | 29 |
2 files changed, 25 insertions, 8 deletions
diff --git a/sys/sparc64/pci/psycho.c b/sys/sparc64/pci/psycho.c index 2752ca4..b6cbfbe 100644 --- a/sys/sparc64/pci/psycho.c +++ b/sys/sparc64/pci/psycho.c @@ -745,12 +745,14 @@ psycho_ce(void *arg) struct psycho_softc *sc = (struct psycho_softc *)arg; u_int64_t afar, afsr; - PSYCHO_WRITE8(sc, PSR_CE_INT_CLR, 0); afar = PSYCHO_READ8(sc, PSR_CE_AFA); afsr = PSYCHO_READ8(sc, PSR_CE_AFS); /* It's correctable. Dump the regs and continue. */ device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx " "AFSR %#lx\n", (u_long)afar, (u_long)afsr); + /* Clear the error bits that we caught. */ + PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr & CEAFSR_ERRMASK); + PSYCHO_WRITE8(sc, PSR_CE_INT_CLR, 0); } static void diff --git a/sys/sparc64/pci/psychoreg.h b/sys/sparc64/pci/psychoreg.h index ad13acd..2973c06 100644 --- a/sys/sparc64/pci/psychoreg.h +++ b/sys/sparc64/pci/psychoreg.h @@ -232,13 +232,28 @@ #define PCICTL_6ENABLE 0x000000000000003f /* enable 6 PCI slots */ /* Uncorrectable error asynchronous fault status registers */ -#define UEAFSR_BLK (1UL << 22) /* pri. error caused by read */ -#define UEAFSR_P_DTE (1UL << 56) /* pri. DMA translation error */ -#define UEAFSR_S_DTE (1UL << 57) /* sec. DMA translation error */ -#define UEAFSR_S_DWR (1UL << 58) /* sec. error during write */ -#define UEAFSR_S_DRD (1UL << 59) /* sec. error during read */ -#define UEAFSR_P_DWR (1UL << 61) /* pri. error during write */ -#define UEAFSR_P_DRD (1UL << 62) /* pri. error during read */ +#define UEAFSR_BLK (1UL << 23) /* Error caused by block transaction. */ +#define UEAFSR_P_DTE (1UL << 56) /* Pri. DVMA translation error. */ +#define UEAFSR_S_DTE (1UL << 57) /* Sec. DVMA translation error. */ +#define UEAFSR_S_DWR (1UL << 58) /* Sec. error during DVMA write. */ +#define UEAFSR_S_DRD (1UL << 59) /* Sec. error during DVMA read. */ +#define UEAFSR_S_PIO (1UL << 60) /* Sec. error during PIO access. */ +#define UEAFSR_P_DWR (1UL << 61) /* Pri. error during DVMA write. */ +#define UEAFSR_P_DRD (1UL << 62) /* Pri. error during DVMA read. */ +#define UEAFSR_P_PIO (1UL << 63) /* Pri. error during PIO access. */ + +/* Correctable error asynchronous fault status registers */ +#define CEAFSR_BLK (1UL << 23) /* Error caused by block transaction. */ +#define CEAFSR_S_DWR (1UL << 58) /* Sec. error caused by DVMA write. */ +#define CEAFSR_S_DRD (1UL << 59) /* Sec. error caused by DVMA read. */ +#define CEAFSR_S_PIO (1UL << 60) /* Sec. error caused by PIO access. */ +#define CEAFSR_P_DWR (1UL << 61) /* Pri. error caused by DVMA write. */ +#define CEAFSR_P_DRD (1UL << 62) /* Pri. error caused by DVMA read. */ +#define CEAFSR_P_PIO (1UL << 63) /* Pri. error caused by PIO access. */ + +#define CEAFSR_ERRMASK \ + (CEAFSR_P_PIO | CEAFSR_P_DRD | CEAFSR_P_DWR | \ + CEAFSR_S_PIO | CEAFSR_S_DRD | CEAFSR_S_DWR) /* Definitions for the target address space register. */ #define PCITAS_ADDR_SHIFT 29 |
