Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs).

Use explicit bus space accesses instead of mapping the device memory
into kva.
Fix support for psycho pairs, and catch up with iommu code changes.

1 files changed, 147 insertions, 302 deletions

diff --git a/sys/sparc64/pci/psychoreg.h b/sys/sparc64/pci/psychoreg.h
index 9be0205..9de6272 100644
--- a/sys/sparc64/pci/psychoreg.h
+++ b/sys/sparc64/pci/psychoreg.h
@@ -45,23 +45,146 @@
  * PSYCHO implements two PCI buses, A and B.
  */
 
-struct psychoreg {
-	struct upareg {
-		/* UPA port ID register */		/* 1fe.0000.0000 */
-		u_int64_t	upa_portid;
-		/* UPA config register */		/* 1fe.0000.0008 */
-		u_int64_t	upa_config;
-	} sys_upa;
+/*
+ * psycho register offset.s
+ *
+ * NB: FFB0 and FFB1 intr map regs also appear at 0x6000 and 0x8000
+ * respectively.
+ */
+#define	PSR_UPA_PORTID		0x0000	/* UPA port ID register */
+#define	PSR_UPA_CONFIG		0x0008	/* UPA config register */
+#define	PSR_CS			0x0010	/* PSYCHO control/status register */
+#define	PSR_ECCC		0x0020	/* ECC control register */
+#define	PSR_UE_AFS		0x0030	/* Uncorrectable Error AFSR */
+#define	PSR_UE_AFA		0x0038	/* Uncorrectable Error AFAR */
+#define	PSR_CE_AFS		0x0040	/* Correctable Error AFSR */
+#define	PSR_CE_AFA		0x0048	/* Correctable Error AFAR */
+#define	PSR_PM_CTL		0x0100	/* Performance monitor control reg */
+#define	PSR_PM_COUNT		0x0108	/* Performance monitor counter reg */
+#define	PSR_IOMMU		0x0200	/* IOMMU registers. */
+#define	PSR_PCIA0_INT_MAP	0x0c00	/* PCI bus a slot 0 irq map reg */
+#define	PSR_PCIA1_INT_MAP	0x0c08	/* PCI bus a slot 1 irq map reg */
+#define	PSR_PCIA2_INT_MAP	0x0c10	/* PCI bus a slot 2 irq map reg (IIi) */
+#define	PSR_PCIA3_INT_MAP	0x0c18	/* PCI bus a slot 3 irq map reg (IIi) */
+#define	PSR_PCIB0_INT_MAP	0x0c20	/* PCI bus b slot 0 irq map reg */
+#define	PSR_PCIB1_INT_MAP	0x0c28	/* PCI bus b slot 1 irq map reg */
+#define	PSR_PCIB2_INT_MAP	0x0c30	/* PCI bus b slot 2 irq map reg */
+#define	PSR_PCIB3_INT_MAP	0x0c38	/* PCI bus b slot 3 irq map reg */
+#define	PSR_SCSI_INT_MAP	0x1000	/* SCSI interrupt map reg */
+#define	PSR_ETHER_INT_MAP	0x1008	/* ethernet interrupt map reg */
+#define	PSR_BPP_INT_MAP		0x1010	/* parallel interrupt map reg */
+#define	PSR_AUDIOR_INT_MAP	0x1018	/* audio record interrupt map reg */
+#define	PSR_AUDIOP_INT_MAP	0x1020	/* audio playback interrupt map reg */
+#define	PSR_POWER_INT_MAP	0x1028	/* power fail interrupt map reg */
+#define	PSR_SKBDMS_INT_MAP	0x1030	/* serial/kbd/mouse interrupt map reg */
+#define	PSR_FD_INT_MAP		0x1038	/* floppy interrupt map reg */
+#define	PSR_SPARE_INT_MAP	0x1040	/* spare interrupt map reg */
+#define	PSR_KBD_INT_MAP		0x1048	/* kbd [unused] interrupt map reg */
+#define	PSR_MOUSE_INT_MAP	0x1050	/* mouse [unused] interrupt map reg */
+#define	PSR_SERIAL_INT_MAP	0x1058	/* second serial interrupt map reg */
+#define	PSR_TIMER0_INT_MAP	0x1060	/* timer 0 interrupt map reg */
+#define	PSR_TIMER1_INT_MAP	0x1068	/* timer 1 interrupt map reg */
+#define	PSR_UE_INT_MAP		0x1070	/* UE interrupt map reg */
+#define	PSR_CE_INT_MAP		0x1078	/* CE interrupt map reg */
+#define	PSR_PCIAERR_INT_MAP	0x1080	/* PCI bus a error interrupt map reg */
+#define	PSR_PCIBERR_INT_MAP	0x1088	/* PCI bus b error interrupt map reg */
+#define	PSR_PWRMGT_INT_MAP	0x1090	/* power mgmt wake interrupt map reg */
+#define	PSR_FFB0_INT_MAP	0x1098	/* FFB0 graphics interrupt map reg */
+#define	PSR_FFB1_INT_MAP	0x10a0	/* FFB1 graphics interrupt map reg */
+/* Note: clear interrupt 0 registers are not really used */
+#define	PSR_PCIA0_INT_CLR	0x1400	/* PCI a slot 0 clear int regs 0..3 */
+#define	PSR_PCIA1_INT_CLR	0x1420	/* PCI a slot 1 clear int regs 0..3 */
+#define	PSR_PCIA2_INT_CLR	0x1440	/* PCI a slot 1 clear int regs 0..3 */
+#define	PSR_PCIA3_INT_CLR	0x1460	/* PCI a slot 1 clear int regs 0..3 */
+#define	PSR_PCIB0_INT_CLR	0x1480	/* PCI b slot 0 clear int regs 0..3 */
+#define	PSR_PCIB1_INT_CLR	0x14a0	/* PCI b slot 1 clear int regs 0..3 */
+#define	PSR_PCIB2_INT_CLR	0x14c0	/* PCI b slot 2 clear int regs 0..3 */
+#define	PSR_PCIB3_INT_CLR	0x14d0	/* PCI b slot 3 clear int regs 0..3 */
+#define	PSR_SCSI_INT_CLR	0x1800	/* SCSI clear int reg */
+#define	PSR_ETHER_INT_CLR	0x1808	/* ethernet clear int reg */
+#define	PSR_BPP_INT_CLR		0x1810	/* parallel clear int reg */
+#define	PSR_AUDIOR_INT_CLR	0x1818	/* audio record clear int reg */
+#define	PSR_AUDIOP_INT_CLR	0x1820	/* audio playback clear int reg */
+#define	PSR_POWER_INT_CLR	0x1828	/* power fail clear int reg */
+#define	PSR_SKBDMS_INT_CLR	0x1830	/* serial/kbd/mouse clear int reg */
+#define	PSR_FD_INT_CLR		0x1838	/* floppy clear int reg */
+#define	PSR_SPARE_INT_CLR	0x1840	/* spare clear int reg */
+#define	PSR_KBD_INT_CLR		0x1848	/* kbd [unused] clear int reg */
+#define	PSR_MOUSE_INT_CLR	0x1850	/* mouse [unused] clear int reg */
+#define	PSR_SERIAL_INT_CLR	0x1858	/* second serial clear int reg */
+#define	PSR_TIMER0_INT_CLR	0x1860	/* timer 0 clear int reg */
+#define	PSR_TIMER1_INT_CLR	0x1868	/* timer 1 clear int reg */
+#define	PSR_UE_INT_CLR		0x1870	/* UE clear int reg */
+#define	PSR_CE_INT_CLR		0x1878	/* CE clear int reg */
+#define	PSR_PCIAERR_INT_CLR	0x1880	/* PCI bus a error clear int reg */
+#define	PSR_PCIBERR_INT_CLR	0x1888	/* PCI bus b error clear int reg */
+#define	PSR_PWRMGT_INT_CLR	0x1890	/* power mgmt wake clr interrupt reg */
+#define	PSR_INTR_RETRY_TIM	0x1a00	/* interrupt retry timer */
+#define	PSR_TC0			0x1c00	/* timer/counter 0 */
+#define	PSR_TC1			0x1c10	/* timer/counter 1 */
+#define	PSR_DMA_WRITE_SYNC	0x1c20	/* PCI DMA write sync register (IIi) */
+#define	PSR_PCICTL0		0x2000	/* PCICTL registers for 1st psycho. */
+#define	PSR_PCICTL1		0x4000	/* PCICTL registers for 2nd psycho. */
+#define	PSR_DMA_SCB_DIAG0	0xa000	/* DMA scoreboard diag reg 0 */
+#define	PSR_DMA_SCB_DIAG1	0xa008	/* DMA scoreboard diag reg 1 */
+#define	PSR_IOMMU_SVADIAG	0xa400	/* IOMMU virtual addr diag reg */
+#define	PSR_IOMMU_TLB_CMP_DIAG	0xa408	/* IOMMU TLB tag compare diag reg */
+#define	PSR_IOMMU_QUEUE_DIAG	0xa500	/* IOMMU LRU queue diag regs 0..15 */
+#define	PSR_IOMMU_TLB_TAG_DIAG	0xa580	/* TLB tag diag regs 0..15 */
+#define	PSR_IOMMU_TLB_DATA_DIAG	0xa600	/* TLB data RAM diag regs 0..15 */
+#define	PSR_PCI_INT_DIAG	0xa800	/* PCI int state diag reg */
+#define	PSR_OBIO_INT_DIAG	0xa808	/* OBIO and misc int state diag reg */
+#define	PSR_STRBUF_DIAG		0xb000	/* Streaming buffer diag regs */
+/*
+ * Here is the rest of the map, which we're not specifying:
+ *
+ * 1fe.0100.0000 - 1fe.01ff.ffff	PCI configuration space
+ * 1fe.0100.0000 - 1fe.0100.00ff	PCI B configuration header
+ * 1fe.0101.0000 - 1fe.0101.00ff	PCI A configuration header
+ * 1fe.0200.0000 - 1fe.0200.ffff	PCI A I/O space
+ * 1fe.0201.0000 - 1fe.0201.ffff	PCI B I/O space
+ * 1ff.0000.0000 - 1ff.7fff.ffff	PCI A memory space
+ * 1ff.8000.0000 - 1ff.ffff.ffff	PCI B memory space
+ *
+ * NB: config and I/O space can use 1-4 byte accesses, not 8 byte
+ * accesses.  Memory space can use any sized accesses.
+ *
+ * Note that the SUNW,sabre/SUNW,simba combinations found on the
+ * Ultra5 and Ultra10 machines uses slightly differrent addresses
+ * than the above.  This is mostly due to the fact that the APB is
+ * a multi-function PCI device with two PCI bridges, and the U2P is
+ * two separate PCI bridges.  It uses the same PCI configuration
+ * space, though the configuration header for each PCI bus is
+ * located differently due to the SUNW,simba PCI busses being
+ * function 0 and function 1 of the APB, whereas the psycho's are
+ * each their own PCI device.  The I/O and memory spaces are each
+ * split into 8 equally sized areas (8x2MB blocks for I/O space,
+ * and 8x512MB blocks for memory space).  These are allocated in to
+ * either PCI A or PCI B, or neither in the APB's `I/O Address Map
+ * Register A/B' (0xde) and `Memory Address Map Register A/B' (0xdf)
+ * registers of each simba.  We must ensure that both of the
+ * following are correct (the prom should do this for us):
+ *
+ *    (PCI A Memory Address Map) & (PCI B Memory Address Map) == 0
+ *
+ *    (PCI A I/O Address Map) & (PCI B I/O Address Map) == 0
+ *
+ * 1fe.0100.0000 - 1fe.01ff.ffff	PCI configuration space
+ * 1fe.0100.0800 - 1fe.0100.08ff	PCI B configuration header
+ * 1fe.0100.0900 - 1fe.0100.09ff	PCI A configuration header
+ * 1fe.0200.0000 - 1fe.02ff.ffff	PCI I/O space (divided)
+ * 1ff.0000.0000 - 1ff.ffff.ffff	PCI memory space (divided)
+ */
 
-	/* PSYCHO control/status register */		/* 1fe.0000.0010 */
-	u_int64_t	psy_csr;
-	/* 
-	 * 63     59     55     50     45     4        3       2     1      0
-	 * +------+------+------+------+--//---+--------+-------+-----+------+
-	 * | IMPL | VERS | MID  | IGN  |  xxx  | APCKEN | APERR | IAP | MODE |
-	 * +------+------+------+------+--//---+--------+-------+-----+------+
-	 *
-	 */
+/*
+ * PSR_CS defines:
+ *
+ * 63     59     55     50     45     4        3       2     1      0
+ * +------+------+------+------+--//---+--------+-------+-----+------+
+ * | IMPL | VERS | MID  | IGN  |  xxx  | APCKEN | APERR | IAP | MODE |
+ * +------+------+------+------+--//---+--------+-------+-----+------+
+ *
+ */
 #define PSYCHO_GCSR_IMPL(csr)	((u_int)(((csr) >> 60) & 0xf))
 #define PSYCHO_GCSR_VERS(csr)	((u_int)(((csr) >> 56) & 0xf))
 #define PSYCHO_GCSR_MID(csr)	((u_int)(((csr) >> 51) & 0x1f))
@@ -71,293 +194,15 @@ struct psychoreg {
 #define PSYCHO_CSR_IAP		2	/* invert UPA address parity */
 #define PSYCHO_CSR_MODE		1	/* UPA/PCI handshake */
 
-	u_int64_t	pad0;
-	/* ECC control register */			/* 1fe.0000.0020 */
-	u_int64_t	psy_ecccr;
-							/* 1fe.0000.0028 */
-	u_int64_t	reserved;
-	/* Uncorrectable Error AFSR */			/* 1fe.0000.0030 */
-	u_int64_t	psy_ue_afsr;
-	/* Uncorrectable Error AFAR */			/* 1fe.0000.0038 */
-	u_int64_t	psy_ue_afar;
-	/* Correctable Error AFSR */			/* 1fe.0000.0040 */
-	u_int64_t	psy_ce_afsr;
-	/* Correctable Error AFAR */			/* 1fe.0000.0048 */
-	u_int64_t	psy_ce_afar;
-
-	u_int64_t	pad1[22];
-
-	struct perfmon {
-		/* Performance monitor control reg */	/* 1fe.0000.0100 */		
-		u_int64_t	pm_cr;
-		/* Performance monitor counter reg */	/* 1fe.0000.0108 */
-		u_int64_t	pm_count;
-	} psy_pm;
-
-	u_int64_t	pad2[30];
-
-							/* 1fe.0000.0200,0210 */
-	struct iommureg psy_iommu;
-
-	u_int64_t	pad3[317];
-
-	/* PCI bus a slot 0 irq map reg */		/* 1fe.0000.0c00 */
-	u_int64_t	pcia0_int_map;
-	/* PCI bus a slot 1 irq map reg */		/* 1fe.0000.0c08 */
-	u_int64_t	pcia1_int_map;
-	/* PCI bus a slot 2 irq map reg (IIi) */	/* 1fe.0000.0c10 */	
-	u_int64_t	pcia2_int_map;
-	/* PCI bus a slot 3 irq map reg (IIi) */	/* 1fe.0000.0c18 */
-	u_int64_t	pcia3_int_map;
-	/* PCI bus b slot 0 irq map reg */		/* 1fe.0000.0c20 */
-	u_int64_t	pcib0_int_map;
-	/* PCI bus b slot 1 irq map reg */		/* 1fe.0000.0c28 */
-	u_int64_t	pcib1_int_map;
-	/* PCI bus b slot 2 irq map reg */		/* 1fe.0000.0c30 */
-	u_int64_t	pcib2_int_map;
-	/* PCI bus b slot 3 irq map reg */		/* 1fe.0000.0c38 */
-	u_int64_t	pcib3_int_map;
-
-	u_int64_t	pad4[120];
-
-	/* SCSI interrupt map reg */			/* 1fe.0000.1000 */
-	u_int64_t	scsi_int_map;
-	/* ethernet interrupt map reg */		/* 1fe.0000.1008 */
-	u_int64_t	ether_int_map;
-	/* parallel interrupt map reg */		/* 1fe.0000.1010 */
-	u_int64_t	bpp_int_map;
-	/* audio record interrupt map reg */		/* 1fe.0000.1018 */
-	u_int64_t	audior_int_map;
-	/* audio playback interrupt map reg */		/* 1fe.0000.1020 */
-	u_int64_t	audiop_int_map;
-	/* power fail interrupt map reg */		/* 1fe.0000.1028 */
-	u_int64_t	power_int_map;
-	/* serial/kbd/mouse interrupt map reg */	/* 1fe.0000.1030 */
-	u_int64_t	ser_kbd_ms_int_map;
-	/* floppy interrupt map reg */			/* 1fe.0000.1038 */
-	u_int64_t	fd_int_map;
-	/* spare interrupt map reg */			/* 1fe.0000.1040 */
-	u_int64_t	spare_int_map;
-	/* kbd [unused] interrupt map reg */		/* 1fe.0000.1048 */
-	u_int64_t	kbd_int_map;
-	/* mouse [unused] interrupt map reg */		/* 1fe.0000.1050 */
-	u_int64_t	mouse_int_map;
-	/* second serial interrupt map reg */		/* 1fe.0000.1058 */
-	u_int64_t	serial_int_map;
-	/* timer 0 interrupt map reg */			/* 1fe.0000.1060 */
-	u_int64_t	timer0_int_map;
-	/* timer 1 interrupt map reg */			/* 1fe.0000.1068 */
-	u_int64_t	timer1_int_map;
-	/* UE interrupt map reg */			/* 1fe.0000.1070 */
-	u_int64_t	ue_int_map;
-	/* CE interrupt map reg */			/* 1fe.0000.1078 */
-	u_int64_t	ce_int_map;
-	/* PCI bus a error interrupt map reg */		/* 1fe.0000.1080 */
-	u_int64_t	pciaerr_int_map;
-	/* PCI bus b error interrupt map reg */		/* 1fe.0000.1088 */
-	u_int64_t	pciberr_int_map;	
-	/* power mgmt wake interrupt map reg */		/* 1fe.0000.1090 */
-	u_int64_t	pwrmgt_int_map;
-	/* FFB0 graphics interrupt map reg */		/* 1fe.0000.1098 */
-	u_int64_t	ffb0_int_map;
-	/* FFB1 graphics interrupt map reg */		/* 1fe.0000.10a0 */
-	u_int64_t	ffb1_int_map;
-	
-	u_int64_t	pad5[107];
-
-	/* Note: clear interrupt 0 registers are not really used */
-
-	/* PCI a slot 0 clear int regs 0..7 */		/* 1fe.0000.1400-1418 */
-	u_int64_t	pcia0_int_clr[4];
-	/* PCI a slot 1 clear int regs 0..7 */		/* 1fe.0000.1420-1438 */
-	u_int64_t	pcia1_int_clr[4];
-	/* PCI a slot 2 clear int regs 0..7 */		/* 1fe.0000.1440-1458 */
-	u_int64_t	pcia2_int_clr[4];
-	/* PCI a slot 3 clear int regs 0..7 */		/* 1fe.0000.1480-1478 */
-	u_int64_t	pcia3_int_clr[4];
-	/* PCI b slot 0 clear int regs 0..7 */		/* 1fe.0000.1480-1498 */
-	u_int64_t	pcib0_int_clr[4];
-	/* PCI b slot 1 clear int regs 0..7 */		/* 1fe.0000.14a0-14b8 */
-	u_int64_t	pcib1_int_clr[4];
-	/* PCI b slot 2 clear int regs 0..7 */		/* 1fe.0000.14c0-14d8 */
-	u_int64_t	pcib2_int_clr[4];
-	/* PCI b slot 3 clear int regs 0..7 */		/* 1fe.0000.14d0-14f8 */
-	u_int64_t	pcib3_int_clr[4];
-
-	u_int64_t	pad6[96];
-
-	/* SCSI clear int reg */			/* 1fe.0000.1800 */
-	u_int64_t	scsi_int_clr;
-	/* ethernet clear int reg */			/* 1fe.0000.1808 */
-	u_int64_t	ether_int_clr;
-	/* parallel clear int reg */			/* 1fe.0000.1810 */
-	u_int64_t	bpp_int_clr;
-	/* audio record clear int reg */		/* 1fe.0000.1818 */
-	u_int64_t	audior_int_clr;
-	/* audio playback clear int reg */		/* 1fe.0000.1820 */
-	u_int64_t	audiop_int_clr;
-	/* power fail clear int reg */			/* 1fe.0000.1828 */
-	u_int64_t	power_int_clr;
-	/* serial/kbd/mouse clear int reg */		/* 1fe.0000.1830 */
-	u_int64_t	ser_kb_ms_int_clr;
-	/* floppy clear int reg */			/* 1fe.0000.1838 */
-	u_int64_t	fd_int_clr;
-	/* spare clear int reg */			/* 1fe.0000.1840 */
-	u_int64_t	spare_int_clr;
-	/* kbd [unused] clear int reg */		/* 1fe.0000.1848 */
-	u_int64_t	kbd_int_clr;
-	/* mouse [unused] clear int reg */		/* 1fe.0000.1850 */
-	u_int64_t	mouse_int_clr;
-	/* second serial clear int reg */		/* 1fe.0000.1858 */
-	u_int64_t	serial_clr;
-	/* timer 0 clear int reg */			/* 1fe.0000.1860 */
-	u_int64_t	timer0_int_clr;
-	/* timer 1 clear int reg */			/* 1fe.0000.1868 */
-	u_int64_t	timer1_int_clr;
-	/* UE clear int reg */				/* 1fe.0000.1870 */
-	u_int64_t	ue_int_clr;
-	/* CE clear int reg */				/* 1fe.0000.1878 */
-	u_int64_t	ce_int_clr;
-	/* PCI bus a error clear int reg */		/* 1fe.0000.1880 */
-	u_int64_t	pciaerr_int_clr;
-	/* PCI bus b error clear int reg */		/* 1fe.0000.1888 */
-	u_int64_t	pciberr_int_clr;
-	/* power mgmt wake clr interrupt reg */		/* 1fe.0000.1890 */
-	u_int64_t	pwrmgt_int_clr;
-
-	u_int64_t	pad7[45];
-
-	/* interrupt retry timer */			/* 1fe.0000.1a00 */
-	u_int64_t	intr_retry_timer;
-
-	u_int64_t	pad8[63];
-
-	struct timer_counter {
-		/* timer/counter 0/1 count register */	/* 1fe.0000.1c00,1c10 */
-		u_int64_t	tc_count;
-		/* timer/counter 0/1 limit register */	/* 1fe.0000.1c08,1c18 */
-		u_int64_t	tc_limit;
-	} tc[2];
-
-	/* PCI DMA write sync register (IIi) */		/* 1fe.0000.1c20 */
-	u_int64_t	pci_dma_write_sync;
-
-	u_int64_t	pad9[123];
-
-	struct pci_ctl {
-		/* PCI a/b control/status register */	/* 1fe.0000.2000,4000 */
-		u_int64_t	pci_csr;
-		u_int64_t	pad10;
-		/* PCI a/b AFSR register */		/* 1fe.0000.2010,4010 */
-		u_int64_t	pci_afsr;
-		/* PCI a/b AFAR register */		/* 1fe.0000.2018,4018 */
-		u_int64_t	pci_afar;
-		/* PCI a/b diagnostic register */	/* 1fe.0000.2020,4020 */
-		u_int64_t	pci_diag;
-		/* PCI target address space reg (IIi)*/	/* 1fe.0000.2028,4028 */
-		u_int64_t	pci_tasr;
-
-		u_int64_t	pad11[250];
-
-		/* This is really the IOMMU's, not the PCI bus's */
-							/* 1fe.0000.2800-210 */
-		struct iommu_strbuf pci_strbuf;
-#define psy_iommu_strbuf psy_pcictl[0].pci_strbuf
-		
-		u_int64_t	pad12[765];
-	} psy_pcictl[2];				/* For PCI a and b */
-
-	/*
-	 * NB: FFB0 and FFB1 intr map regs also appear at 1fe.0000.6000 and
-	 * 1fe.0000.8000 respectively
-	 */
-	u_int64_t	pad13[2048];
-
-	/* DMA scoreboard diag reg 0 */			/* 1fe.0000.a000 */
-	u_int64_t	dma_scb_diag0;
-	/* DMA scoreboard diag reg 1 */			/* 1fe.0000.a008 */
-	u_int64_t	dma_scb_diag1;
-
-	u_int64_t	pad14[126];
-
-	/* IOMMU virtual addr diag reg */		/* 1fe.0000.a400 */
-	u_int64_t	iommu_svadiag;
-	/* IOMMU TLB tag compare diag reg */		/* 1fe.0000.a408 */
-	u_int64_t	iommu_tlb_comp_diag;
-	
-	u_int64_t	pad15[30];
-
-	/* IOMMU LRU queue diag */			/* 1fe.0000.a500-a578 */
-	u_int64_t	iommu_queue_diag[16];
-	/* TLB tag diag */				/* 1fe.0000.a580-a5f8 */
-	u_int64_t	tlb_tag_diag[16];
-	/* TLB data RAM diag */				/* 1fe.0000.a600-a678 */
-	u_int64_t	tlb_data_diag[16];
-
-	u_int64_t	pad16[48];
-
-	/* PCI int state diag reg */			/* 1fe.0000.a800 */
-	u_int64_t	pci_int_diag;
-	/* OBIO and misc int state diag reg */		/* 1fe.0000.a808 */
-	u_int64_t	obio_int_diag;
-
-	u_int64_t	pad17[254];
-
-	struct strbuf_diag {
-		/* streaming buffer data RAM diag */	/* 1fe.0000.b000-b3f8 */
-		u_int64_t	strbuf_data_diag[128];
-		/* streaming buffer error status diag *//* 1fe.0000.b400-b7f8 */
-		u_int64_t	strbuf_error_diag[128];
-		/* streaming buffer page tag diag */	/* 1fe.0000.b800-b878 */
-		u_int64_t	strbuf_pg_tag_diag[16];
-		u_int64_t	pad18[16];
-		/* streaming buffer line tag diag */	/* 1fe.0000.b900-b978 */
-		u_int64_t	strbuf_ln_tag_diag[16];
-		u_int64_t	pad19[208];
-	} psy_strbufdiag[2];				/* For PCI a and b */
-
-	/* 
-	 * Here is the rest of the map, which we're not specifying:
-	 *
-	 * 1fe.0100.0000 - 1fe.01ff.ffff	PCI configuration space
-	 * 1fe.0100.0000 - 1fe.0100.00ff	PCI B configuration header
-	 * 1fe.0101.0000 - 1fe.0101.00ff	PCI A configuration header
-	 * 1fe.0200.0000 - 1fe.0200.ffff	PCI A I/O space
-	 * 1fe.0201.0000 - 1fe.0201.ffff	PCI B I/O space
-	 * 1ff.0000.0000 - 1ff.7fff.ffff	PCI A memory space
-	 * 1ff.8000.0000 - 1ff.ffff.ffff	PCI B memory space
-	 *
-	 * NB: config and I/O space can use 1-4 byte accesses, not 8 byte
-	 * accesses.  Memory space can use any sized accesses.
-	 *
-	 * Note that the SUNW,sabre/SUNW,simba combinations found on the
-	 * Ultra5 and Ultra10 machines uses slightly differrent addresses
-	 * than the above.  This is mostly due to the fact that the APB is
-	 * a multi-function PCI device with two PCI bridges, and the U2P is
-	 * two separate PCI bridges.  It uses the same PCI configuration
-	 * space, though the configuration header for each PCI bus is
-	 * located differently due to the SUNW,simba PCI busses being
-	 * function 0 and function 1 of the APB, whereas the psycho's are
-	 * each their own PCI device.  The I/O and memory spaces are each
-	 * split into 8 equally sized areas (8x2MB blocks for I/O space,
-	 * and 8x512MB blocks for memory space).  These are allocated in to
-	 * either PCI A or PCI B, or neither in the APB's `I/O Address Map
-	 * Register A/B' (0xde) and `Memory Address Map Register A/B' (0xdf)
-	 * registers of each simba.  We must ensure that both of the
-	 * following are correct (the prom should do this for us):
-	 *
-	 *    (PCI A Memory Address Map) & (PCI B Memory Address Map) == 0
-	 *
-	 *    (PCI A I/O Address Map) & (PCI B I/O Address Map) == 0
-	 *
-	 * 1fe.0100.0000 - 1fe.01ff.ffff	PCI configuration space
-	 * 1fe.0100.0800 - 1fe.0100.08ff	PCI B configuration header
-	 * 1fe.0100.0900 - 1fe.0100.09ff	PCI A configuration header
-	 * 1fe.0200.0000 - 1fe.02ff.ffff	PCI I/O space (divided)
-	 * 1ff.0000.0000 - 1ff.ffff.ffff	PCI memory space (divided) 
-	 */
-};
+/* Offsets into the PSR_PCICTL* register block. */
+#define	PCR_CS			0x0000	/* PCI control/status register */
+#define	PCR_AFS			0x0010	/* PCI AFSR register */
+#define	PCR_AFA			0x0018	/* PCI AFAR register */
+#define	PCR_DIAG		0x0020	/* PCI diagnostic register */
+#define	PCR_TAS			0x0028	/* PCI target address space reg (IIi) */
+#define	PCR_STRBUF		0x0800	/* IOMMU streaming buffer registers. */
 
+/* Device space defines. */
 #define	PSYCHO_CONF_SIZE	0x1000000
 #define	PSYCHO_CONF_BUS_SHIFT	16
 #define	PSYCHO_CONF_DEV_SHIFT	11