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authortmm <tmm@FreeBSD.org>2002-06-12 19:20:57 +0000
committertmm <tmm@FreeBSD.org>2002-06-12 19:20:57 +0000
commit0d05c0dd9cf4ae0953ba607bcf41e2abafebb77d (patch)
tree98a711dedb0135a584c0316111043e98d41cfdd7 /sys/sparc64/pci/psychoreg.h
parentc580ba61b3d5ce3f74c50c463c50afc556dd8d7a (diff)
downloadFreeBSD-src-0d05c0dd9cf4ae0953ba607bcf41e2abafebb77d.zip
FreeBSD-src-0d05c0dd9cf4ae0953ba607bcf41e2abafebb77d.tar.gz
Add PCI bus enumeration and latency timer setup to the sparc64 MD PCI
code. Both tasks are not always performed completely by the firmware. The former is required to get some e450 models to boot; the latter fixes the repeated fifo underruns with hme(4)s and gem(4)s observed on some machines (and probably performance problems with other peripherals as well).
Diffstat (limited to 'sys/sparc64/pci/psychoreg.h')
-rw-r--r--sys/sparc64/pci/psychoreg.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/sys/sparc64/pci/psychoreg.h b/sys/sparc64/pci/psychoreg.h
index 7de9c62..412a217 100644
--- a/sys/sparc64/pci/psychoreg.h
+++ b/sys/sparc64/pci/psychoreg.h
@@ -240,6 +240,14 @@
#define UEAFSR_P_DWR (1UL << 61) /* pri. error during write */
#define UEAFSR_P_DRD (1UL << 62) /* pri. error during read */
+/* Definitions for the psycho configuration space */
+#define PCS_DEVICE 0 /* Device number of psycho CS entry */
+#define PCS_FUNC 0 /* Function number of psycho CS entry */
+
+/* Non-Standard registers in the configration space */
+#define PCSR_SECBUS 0x40 /* Secondary bus number register */
+#define PCSR_SUBBUS 0x41 /* Subordinate bus number register */
+
/*
* these are the PROM structures we grovel
*/
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