On sparc64 machines with multiple host-PCI-bridges these bridges

have separate configuration spaces so by definition they implement
different PCI domains. Thus change psycho(4) to use PCI domains
instead of reenumerating all PCI busses so they have globally unique
bus numbers and drop support for reenumerating busses in the OFW PCI
code.
According to CVS history reenumeration was also required in order to
get some E450 to boot but given that no other open source kernel
changes the PCI bus numbers assigned by the firmware I believe the
real problem was that the old code used the bus number as the device
number for the PCI busses and unlike most of the other machines the
firmwares of the problematic ones don't use disjoint PCI bus numbers
across the host-PCI-bridges.

MFC after:	1 month

1 files changed, 0 insertions, 39 deletions

diff --git a/sys/sparc64/pci/ofw_pcib_subr.c b/sys/sparc64/pci/ofw_pcib_subr.c
index 7cc867b..9996b7e 100644
--- a/sys/sparc64/pci/ofw_pcib_subr.c
+++ b/sys/sparc64/pci/ofw_pcib_subr.c
@@ -52,33 +52,13 @@ void
 ofw_pcib_gen_setup(device_t bridge)
 {
 	struct ofw_pcib_gen_softc *sc;
-#ifndef SUN4V
-	int secbus;
 
-#endif
 	sc = device_get_softc(bridge);
 	sc->ops_pcib_sc.dev = bridge;
 	sc->ops_node = ofw_bus_get_node(bridge);
 	KASSERT(sc->ops_node != 0,
 	    ("ofw_pcib_gen_setup: no ofw pci parent bus!"));
 
-	/*
-	 * Setup the secondary bus number register, if supported, by
-	 * allocating a new unique bus number for it; the firmware
-	 * preset does not always seem to be correct in that case.
-	 */
-#ifndef SUN4V
-	secbus = OFW_PCI_ALLOC_BUSNO(bridge);
-	if (secbus != -1) {
-		pci_write_config(bridge, PCIR_PRIBUS_1, pci_get_bus(bridge), 1);
-		pci_write_config(bridge, PCIR_SECBUS_1, secbus, 1);
-		pci_write_config(bridge, PCIR_SUBBUS_1, secbus, 1);
-		sc->ops_pcib_sc.subbus = sc->ops_pcib_sc.secbus = secbus;
-		/* Notify parent bridges. */
-		OFW_PCI_ADJUST_BUSRANGE(device_get_parent(bridge), secbus);
-	}
-
-#endif
 	ofw_bus_setup_iinfo(sc->ops_node, &sc->ops_iinfo,
 	    sizeof(ofw_pci_intr_t));
 }
@@ -126,22 +106,3 @@ ofw_pcib_gen_get_node(device_t bridge, device_t dev)
 	sc = device_get_softc(bridge);
 	return (sc->ops_node);
 }
-
-void
-ofw_pcib_gen_adjust_busrange(device_t bridge, u_int subbus)
-{
-	struct ofw_pcib_gen_softc *sc;
-
-	sc = device_get_softc(bridge);
-	if (subbus > sc->ops_pcib_sc.subbus) {
-#ifdef OFW_PCI_DEBUG
-		device_printf(bridge,
-		    "adjusting subordinate bus number from %d to %d\n",
-		    sc->ops_pcib_sc.subbus, subbus);
-#endif
-		pci_write_config(bridge, PCIR_SUBBUS_1, subbus, 1);
-		sc->ops_pcib_sc.subbus = subbus;
-		/* Notify parent bridges. */
-		OFW_PCI_ADJUST_BUSRANGE(device_get_parent(bridge), subbus);
-	}
-}