- Search the whole OFW device tree instead of only the children of the

  root nexus device for the CPUs as starting with UltraSPARC IV the 'cpu'
  nodes hang off of from 'cmp' (chip multi-threading processor) or 'core'
  or combinations thereof. Also in large UltraSPARC III based machines
  the 'cpu' nodes hang off of 'ssm' (scalable shared memory) nodes which
  group snooping-coherency domains together instead of directly from the
  nexus.
  It would be great if we could use newbus to deal with the different ways
  the 'cpu' devices can hang off of pseudo ones but unfortunately both
  cpu_mp_setmaxid() and sparc64_init() have to work prior to regular device
  probing.
- Add support for UltraSPARC IV and IV+ CPUs. Due to the fact that these
  are multi-core each CPU has two Fireplane config registers and thus the
  module/target ID has to be determined differently so the one specific
  to a certain core is used. Similarly, starting with UltraSPARC IV the
  individual cores use a different property in the OFW device tree to
  indicate the CPU/core ID as it no longer is in coincidence with the
  shared slot/socket ID.
  This involves changing the MD KTR code to not directly read the UPA
  module ID either. We use the MID stored in the per-CPU data instead of
  calling cpu_get_mid() as a replacement in order prevent clobbering any
  registers as side-effect in the assembler version. This requires CATR()
  invocations from mp_startup() prior to mapping the per-CPU pages to be
  removed though.
  While at it additionally distinguish between CPUs with Fireplane and
  JBus interconnects as these also use slightly different sizes for the
  JBus/agent/module/target IDs.
- Make sparc64_shutdown_final() static as it's not used outside of
  machdep.c.

3 files changed, 7 insertions, 16 deletions

diff --git a/sys/sparc64/include/ktr.h b/sys/sparc64/include/ktr.h
index 0b7e96a..5948ba2 100644
--- a/sys/sparc64/include/ktr.h
+++ b/sys/sparc64/include/ktr.h
@@ -34,11 +34,9 @@
 
 #include <sys/ktr.h>
 
-#include <machine/upa.h>
-
 #ifndef LOCORE
 
-#define	KTR_CPU	UPA_CR_GET_MID(ldxa(0, ASI_UPA_CONFIG_REG))
+#define	KTR_CPU	PCPU_GET(mid)
 
 #else
 
@@ -74,7 +72,7 @@ l2:	add	r2, 1, r3 ; \
 	add	r1, r2, r1 ; \
 	rd	%tick, r2 ; \
 	stx	r2, [r1 + KTR_TIMESTAMP] ; \
-	UPA_GET_MID(r2) ; \
+	lduw	[PCPU(MID)], r2 ; \
 	stw	r2, [r1 + KTR_CPU] ; \
 	stw	%g0, [r1 + KTR_LINE] ; \
 	stx	%g0, [r1 + KTR_FILE] ; \
@@ -84,7 +82,7 @@ l2:	add	r2, 1, r3 ; \
 #define CATR(mask, desc, r1, r2, r3, l1, l2, l3) \
 	set	mask, r1 ; \
 	TEST(ktr_mask, r1, r2, r2, l3) ; \
-	UPA_GET_MID(r1) ; \
+	lduw	[PCPU(MID)], r1 ; \
 	mov	1, r2 ; \
 	sllx	r2, r1, r1 ; \
 	TEST(ktr_cpumask, r1, r2, r3, l3) ; \
diff --git a/sys/sparc64/include/md_var.h b/sys/sparc64/include/md_var.h
index 69c6d69..592d980 100644
--- a/sys/sparc64/include/md_var.h
+++ b/sys/sparc64/include/md_var.h
@@ -47,6 +47,8 @@ extern	vm_paddr_t kstack0_phys;
 struct	pcpu;
 struct	md_utrap;
 
+const char *cpu_cpuid_prop(void);
+uint32_t cpu_get_mid(void);
 void	cpu_identify(u_long vers, u_int clock, u_int id);
 void	cpu_setregs(struct pcpu *pc);
 int	is_physical_memory(vm_paddr_t addr);
diff --git a/sys/sparc64/include/upa.h b/sys/sparc64/include/upa.h
index 3e56917..43531cf 100644
--- a/sys/sparc64/include/upa.h
+++ b/sys/sparc64/include/upa.h
@@ -26,25 +26,16 @@
  */
 
 #ifndef _MACHINE_UPA_H_
-#define _MACHINE_UPA_H_
+#define	_MACHINE_UPA_H_
 
 #define	UPA_MEMSTART	0x1c000000000UL
 #define	UPA_MEMEND	0x1ffffffffffUL
 
 #define	UPA_CR_MID_SHIFT	(17)
 #define	UPA_CR_MID_SIZE		(5)
-#define	UPA_CR_MID_MASK \
+#define	UPA_CR_MID_MASK							\
 	(((1 << UPA_CR_MID_SIZE) - 1) << UPA_CR_MID_SHIFT)
 
 #define	UPA_CR_GET_MID(cr)	((cr & UPA_CR_MID_MASK) >> UPA_CR_MID_SHIFT)
 
-#ifdef LOCORE
-
-#define	UPA_GET_MID(r1) \
-	ldxa	[%g0] ASI_UPA_CONFIG_REG, r1 ; \
-	srlx	r1, UPA_CR_MID_SHIFT, r1 ; \
-	and	r1, (1 << UPA_CR_MID_SIZE) - 1, r1
-
-#endif
-
 #endif /* _MACHINE_UPA_H_ */