Welcome the RISC-V 64-bit kernel.

This is the final step required allowing to compile and to run RISC-V
kernel and userland from HEAD.

RISC-V is a completely open ISA that is freely available to academia
and industry.

Thanks to all the people involved! Special thanks to Andrew Turner,
David Chisnall, Ed Maste, Konstantin Belousov, John Baldwin and
Arun Thomas for their help.
Thanks to Robert Watson for organizing this project.

This project sponsored by UK Higher Education Innovation Fund (HEIF5) and
DARPA CTSRD project at the University of Cambridge Computer Laboratory.

FreeBSD/RISC-V project home: https://wiki.freebsd.org/riscv

Reviewed by:	andrew, emaste, kib
Relnotes:	Yes
Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
Differential Revision:	https://reviews.freebsd.org/D4982

1 files changed, 149 insertions, 0 deletions

diff --git a/sys/riscv/riscv/identcpu.c b/sys/riscv/riscv/identcpu.c
new file mode 100644
index 0000000..dd1f2ba
--- /dev/null
+++ b/sys/riscv/riscv/identcpu.c
@@ -0,0 +1,149 @@
+/*-
+ * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
+ * All rights reserved.
+ *
+ * Portions of this software were developed by SRI International and the
+ * University of Cambridge Computer Laboratory under DARPA/AFRL contract
+ * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
+ *
+ * Portions of this software were developed by the University of Cambridge
+ * Computer Laboratory as part of the CTSRD Project, with support from the
+ * UK Higher Education Innovation Fund (HEIF).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/pcpu.h>
+#include <sys/sysctl.h>
+#include <sys/systm.h>
+
+#include <machine/cpu.h>
+#include <machine/cpufunc.h>
+#include <machine/trap.h>
+
+char machine[] = "riscv";
+
+SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0,
+    "Machine class");
+
+struct cpu_desc {
+	u_int		cpu_impl;
+	u_int		cpu_part_num;
+	const char	*cpu_impl_name;
+	const char	*cpu_part_name;
+};
+
+struct cpu_desc cpu_desc[MAXCPU];
+
+struct cpu_parts {
+	u_int		part_id;
+	const char	*part_name;
+};
+#define	CPU_PART_NONE	{ -1, "Unknown Processor" }
+
+struct cpu_implementers {
+	u_int			impl_id;
+	const char		*impl_name;
+	/*
+	 * Part number is implementation defined
+	 * so each vendor will have its own set of values and names.
+	 */
+	const struct cpu_parts	*cpu_parts;
+};
+#define	CPU_IMPLEMENTER_NONE	{ 0, "Unknown Implementer", cpu_parts_none }
+
+/*
+ * Per-implementer table of (PartNum, CPU Name) pairs.
+ */
+/* UC Berkeley */
+static const struct cpu_parts cpu_parts_ucb[] = {
+	{ CPU_PART_RV32I,	"RV32I" },
+	{ CPU_PART_RV32E,	"RV32E" },
+	{ CPU_PART_RV64I,	"RV64I" },
+	{ CPU_PART_RV128I,	"RV128I" },
+	CPU_PART_NONE,
+};
+
+/* Unknown */
+static const struct cpu_parts cpu_parts_none[] = {
+	CPU_PART_NONE,
+};
+
+/*
+ * Implementers table.
+ */
+const struct cpu_implementers cpu_implementers[] = {
+	{ CPU_IMPL_UCB_ROCKET,	"UC Berkeley Rocket",	cpu_parts_ucb },
+	CPU_IMPLEMENTER_NONE,
+};
+
+void
+identify_cpu(void)
+{
+	const struct cpu_parts *cpu_partsp;
+	uint32_t part_id;
+	uint32_t impl_id;
+	uint64_t mimpid;
+	uint64_t mcpuid;
+	u_int cpu;
+	size_t i;
+
+	cpu_partsp = NULL;
+
+	mimpid = machine_command(ECALL_MIMPID_GET, 0);
+	mcpuid = machine_command(ECALL_MCPUID_GET, 0);
+
+	/* SMPTODO: use mhartid ? */
+	cpu = PCPU_GET(cpuid);
+
+	impl_id	= CPU_IMPL(mimpid);
+	for (i = 0; i < nitems(cpu_implementers); i++) {
+		if (impl_id == cpu_implementers[i].impl_id ||
+		    cpu_implementers[i].impl_id == 0) {
+			cpu_desc[cpu].cpu_impl = impl_id;
+			cpu_desc[cpu].cpu_impl_name = cpu_implementers[i].impl_name;
+			cpu_partsp = cpu_implementers[i].cpu_parts;
+			break;
+		}
+	}
+
+	part_id = CPU_PART(mcpuid);
+	for (i = 0; &cpu_partsp[i] != NULL; i++) {
+		if (part_id == cpu_partsp[i].part_id ||
+		    cpu_partsp[i].part_id == -1) {
+			cpu_desc[cpu].cpu_part_num = part_id;
+			cpu_desc[cpu].cpu_part_name = cpu_partsp[i].part_name;
+			break;
+		}
+	}
+
+	/* Print details for boot CPU or if we want verbose output */
+	if (cpu == 0 || bootverbose) {
+		printf("CPU(%d): %s %s\n", cpu,
+		    cpu_desc[cpu].cpu_impl_name,
+		    cpu_desc[cpu].cpu_part_name);
+	}
+}