Add support for ddb(4).

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5

4 files changed, 216 insertions, 4 deletions

diff --git a/sys/riscv/include/db_machdep.h b/sys/riscv/include/db_machdep.h
index a9890d9..7dfd902 100644
--- a/sys/riscv/include/db_machdep.h
+++ b/sys/riscv/include/db_machdep.h
@@ -1,5 +1,5 @@
 /*-
- * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
+ * Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com>
  * All rights reserved.
  *
  * Portions of this software were developed by SRI International and the
@@ -41,7 +41,51 @@
 #include <machine/frame.h>
 #include <machine/trap.h>
 
+#define	T_BREAKPOINT	(EXCP_INSTR_BREAKPOINT)
+#define	T_WATCHPOINT	(0)
+
 typedef vm_offset_t	db_addr_t;
 typedef long		db_expr_t;
 
+#define	PC_REGS()	((db_addr_t)kdb_thrctx->pcb_sepc)
+
+#define	BKPT_INST	(0x00100073)
+#define	BKPT_SIZE	(INSN_SIZE)
+#define	BKPT_SET(inst)	(BKPT_INST)
+
+#define	BKPT_SKIP do {				\
+	kdb_frame->tf_sepc += BKPT_SIZE;	\
+} while (0)
+
+#define	db_clear_single_step	kdb_cpu_clear_singlestep
+#define	db_set_single_step	kdb_cpu_set_singlestep
+
+#define	IS_BREAKPOINT_TRAP(type, code)	(type == T_BREAKPOINT)
+#define	IS_WATCHPOINT_TRAP(type, code)	(type == T_WATCHPOINT)
+
+#define	inst_trap_return(ins)	(ins == 0x10000073)	/* eret */
+#define	inst_return(ins)	(ins == 0x00008067)	/* ret */
+#define	inst_call(ins)		(((ins) & 0x7f) == 111 || \
+				 ((ins) & 0x7f) == 103) /* jal, jalr */
+
+#define	inst_load(ins) ({							\
+	uint32_t tmp_instr = db_get_value(PC_REGS(), sizeof(uint32_t), FALSE);	\
+	is_load_instr(tmp_instr);						\
+})
+
+#define	inst_store(ins) ({							\
+	uint32_t tmp_instr = db_get_value(PC_REGS(), sizeof(uint32_t), FALSE);	\
+	is_store_instr(tmp_instr);						\
+})
+
+#define	is_load_instr(ins)	(((ins) & 0x7f) == 3)
+#define	is_store_instr(ins)	(((ins) & 0x7f) == 35)
+
+#define	next_instr_address(pc, bd)	((bd) ? (pc) : ((pc) + 4))
+
+#define	DB_SMALL_VALUE_MAX	(0x7fffffff)
+#define	DB_SMALL_VALUE_MIN	(-0x40001)
+
+#define	DB_ELFSIZE		64
+
 #endif /* !_MACHINE_DB_MACHDEP_H_ */
diff --git a/sys/riscv/include/riscv_opcode.h b/sys/riscv/include/riscv_opcode.h
new file mode 100644
index 0000000..b346588
--- /dev/null
+++ b/sys/riscv/include/riscv_opcode.h
@@ -0,0 +1,116 @@
+/*-
+ * Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
+ * All rights reserved.
+ *
+ * Portions of this software were developed by SRI International and the
+ * University of Cambridge Computer Laboratory under DARPA/AFRL contract
+ * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
+ *
+ * Portions of this software were developed by the University of Cambridge
+ * Computer Laboratory as part of the CTSRD Project, with support from the
+ * UK Higher Education Innovation Fund (HEIF).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _MACHINE_RISCV_OPCODE_H_
+#define	_MACHINE_RISCV_OPCODE_H_
+
+/*
+ * Define the instruction formats and opcode values for the
+ * RISC-V instruction set.
+ */
+#include <machine/endian.h>
+
+/*
+ * Define the instruction formats.
+ */
+typedef union {
+	unsigned word;
+
+	struct {
+		unsigned opcode: 7;
+		unsigned rd: 5;
+		unsigned funct3: 3;
+		unsigned rs1: 5;
+		unsigned rs2: 5;
+		unsigned funct7: 7;
+	} RType;
+
+	struct {
+		unsigned opcode: 7;
+		unsigned rd: 5;
+		unsigned funct3: 3;
+		unsigned rs1: 5;
+		unsigned rs2: 6;
+		unsigned funct7: 6;
+	} R2Type;
+
+	struct {
+		unsigned opcode: 7;
+		unsigned rd: 5;
+		unsigned funct3: 3;
+		unsigned rs1: 5;
+		unsigned imm: 12;
+	} IType;
+
+	struct {
+		unsigned opcode: 7;
+		unsigned imm0_4: 5;
+		unsigned funct3: 3;
+		unsigned rs1: 5;
+		unsigned rs2: 5;
+		unsigned imm5_11: 7;
+	} SType;
+
+	struct {
+		unsigned opcode: 7;
+		unsigned imm11: 1;
+		unsigned imm1_4: 4;
+		unsigned funct3: 3;
+		unsigned rs1: 5;
+		unsigned rs2: 5;
+		unsigned imm5_10: 6;
+		unsigned imm12: 1;
+	} SBType;
+
+	struct {
+		unsigned opcode: 7;
+		unsigned rd: 5;
+		unsigned imm12_31: 20;
+	} UType;
+
+	struct {
+		unsigned opcode: 7;
+		unsigned rd: 5;
+		unsigned imm12_19: 8;
+		unsigned imm11: 1;
+		unsigned imm1_10: 10;
+		unsigned imm20: 1;
+	} UJType;
+} InstFmt;
+
+#define	RISCV_OPCODE(r)		(r & 0x7f)
+
+#endif /* !_MACHINE_RISCV_OPCODE_H_ */
diff --git a/sys/riscv/include/riscvreg.h b/sys/riscv/include/riscvreg.h
index 76cba49..b411e18 100644
--- a/sys/riscv/include/riscvreg.h
+++ b/sys/riscv/include/riscvreg.h
@@ -117,9 +117,10 @@
 #define	SIP_SSIP	(1 << 1)
 #define	SIP_STIP	(1 << 5)
 
-#define	NCSRS	4096
-#define	CSR_IPI	0x783
-#define	XLEN	8
+#define	NCSRS		4096
+#define	CSR_IPI		0x783
+#define	XLEN		8
+#define	INSN_SIZE	4
 
 #define	CSR_ZIMM(val)							\
 	(__builtin_constant_p(val) && ((u_long)(val) < 32))
diff --git a/sys/riscv/include/stack.h b/sys/riscv/include/stack.h
new file mode 100644
index 0000000..7f4be068
--- /dev/null
+++ b/sys/riscv/include/stack.h
@@ -0,0 +1,51 @@
+/*-
+ * Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
+ * All rights reserved.
+ *
+ * Portions of this software were developed by SRI International and the
+ * University of Cambridge Computer Laboratory under DARPA/AFRL contract
+ * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
+ *
+ * Portions of this software were developed by the University of Cambridge
+ * Computer Laboratory as part of the CTSRD Project, with support from the
+ * UK Higher Education Innovation Fund (HEIF).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _MACHINE_STACK_H_
+#define	_MACHINE_STACK_H_
+
+#define	INKERNEL(va)	((va) >= VM_MIN_KERNEL_ADDRESS && \
+			 (va) <= VM_MAX_KERNEL_ADDRESS)
+
+struct unwind_state {
+	uint64_t fp;
+	uint64_t sp;
+	uint64_t pc;
+};
+
+int unwind_frame(struct unwind_state *);
+
+#endif /* !_MACHINE_STACK_H_ */