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author | jhibbits <jhibbits@FreeBSD.org> | 2015-07-04 18:16:41 +0000 |
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committer | jhibbits <jhibbits@FreeBSD.org> | 2015-07-04 18:16:41 +0000 |
commit | 6dd57f17e180efd0911bacad91de647fb9dcc783 (patch) | |
tree | c59ce866ad41aa86a47c0db17ffbb1cae99ba671 /sys/powerpc/include | |
parent | b3145369510fe53cf9fec393cef3674218687e82 (diff) | |
download | FreeBSD-src-6dd57f17e180efd0911bacad91de647fb9dcc783.zip FreeBSD-src-6dd57f17e180efd0911bacad91de647fb9dcc783.tar.gz |
Add machine check register printing
This will print out the Memory Subsystem Status Register on MPC745x (G4+ class),
and the Machine Check Status Register on Book-E class CPUs, to aid in debugging
machine checks. Other relevant registers, for other CPUs, can be added in the
future.
Diffstat (limited to 'sys/powerpc/include')
-rw-r--r-- | sys/powerpc/include/spr.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/sys/powerpc/include/spr.h b/sys/powerpc/include/spr.h index a352025..c753f5e 100644 --- a/sys/powerpc/include/spr.h +++ b/sys/powerpc/include/spr.h @@ -527,6 +527,14 @@ #define MSSCR0_ABD 0x00100000 /* 11: address bus driven (read-only) */ #define MSSCR0_MBZ 0x000fffff /* 12-31: must be zero */ #define MSSCR0_L2PFE 0x00000003 /* 30-31: L2 prefetch enable */ +#define SPR_MSSSR0 0x3f7 /* .6. Memory Subsystem Status Register (MPC745x) */ +#define MSSSR0_L2TAG 0x00040000 /* 13: L2 tag parity error */ +#define MSSSR0_L2DAT 0x00020000 /* 14: L2 data parity error */ +#define MSSSR0_L3TAG 0x00010000 /* 15: L3 tag parity error */ +#define MSSSR0_L3DAT 0x00008000 /* 16: L3 data parity error */ +#define MSSSR0_APE 0x00004000 /* 17: Address parity error */ +#define MSSSR0_DPE 0x00002000 /* 18: Data parity error */ +#define MSSSR0_TEA 0x00001000 /* 19: Bus transfer error acknowledge */ #define SPR_LDSTCR 0x3f8 /* .6. Load/Store Control Register */ #define SPR_L2PM 0x3f8 /* .6. L2 Private Memory Control Register */ #define SPR_L2CR 0x3f9 /* .6. L2 Control Register */ |