This commit adds device driver support for Adaptec Duralink PCI fast

ethernet controllers based on the AIC-6915 "Starfire" controller chip.
There are single port, dual port and quad port cards, plus one 100baseFX
card. All are 64-bit PCI devices, except one single port model.

The Starfire would be a very nice chip were it not for the fact that
receive buffers have to be longword aligned. This requires buffer
copying in order to achieve proper payload alignment on the alpha.
Payload alignment is enforced on both the alpha and x86 platforms.
The Starfire has several different DMA descriptor formats and transfer
mechanisms. This driver uses frame descriptors for transmission which
can address up to 14 packet fragments, and a single fragment descriptor
for receive. It also uses the producer/consumer model and completion
queues for both transmit and receive. The transmit ring has 128
descriptors and the receive ring has 256.

This driver supports both FreeBSD/i386 and FreeBSD/alpha, and uses newbus
so that it can be compiled as a loadable kernel module. Support for BPF
and hardware multicast filtering is included.

2 files changed, 3008 insertions, 0 deletions

diff --git a/sys/pci/if_sf.c b/sys/pci/if_sf.c
new file mode 100644
index 0000000..685d0f9
--- /dev/null
+++ b/sys/pci/if_sf.c
@@ -0,0 +1,1837 @@
+/*
+ * Copyright (c) 1997, 1998, 1999
+ *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *	$Id: if_sf.c,v 1.11 1999/07/24 21:13:38 wpaul Exp $
+ */
+
+/*
+ * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD.
+ * Programming manual is available from www.adaptec.com.
+ *
+ * Written by Bill Paul <wpaul@ctr.columbia.edu>
+ * Department of Electical Engineering
+ * Columbia University, New York City
+ */
+
+/*
+ * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet
+ * controller designed with flexibility and reducing CPU load in mind.
+ * The Starfire offers high and low priority buffer queues, a
+ * producer/consumer index mechanism and several different buffer
+ * queue and completion queue descriptor types. Any one of a number
+ * of different driver designs can be used, depending on system and
+ * OS requirements. This driver makes use of type0 transmit frame
+ * descriptors (since BSD fragments packets across an mbuf chain)
+ * and two RX buffer queues prioritized on size (one queue for small
+ * frames that will fit into a single mbuf, another with full size
+ * mbuf clusters for everything else). The producer/consumer indexes
+ * and completion queues are also used.
+ *
+ * One downside to the Starfire has to do with alignment: buffer
+ * queues must be aligned on 256-byte boundaries, and receive buffers
+ * must be aligned on longword boundaries. The receive buffer alignment
+ * causes problems on the Alpha platform, where the packet payload
+ * should be longword aligned. There is no simple way around this.
+ *
+ * For receive filtering, the Starfire offers 16 perfect filter slots
+ * and a 512-bit hash table.
+ *
+ * The Starfire has no internal transceiver, relying instead on an
+ * external MII-based transceiver. Accessing registers on external
+ * PHYs is done through a special register map rather than with the
+ * usual bitbang MDIO method.
+ *
+ * Acesssing the registers on the Starfire is a little tricky. The
+ * Starfire has a 512K internal register space. When programmed for
+ * PCI memory mapped mode, the entire register space can be accessed
+ * directly. However in I/O space mode, only 256 bytes are directly
+ * mapped into PCI I/O space. The other registers can be accessed
+ * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA
+ * registers inside the 256-byte I/O window.
+ */
+
+#include "bpf.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/ethernet.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+
+#if NBPF > 0
+#include <net/bpf.h>
+#endif
+
+#include <vm/vm.h>              /* for vtophys */
+#include <vm/pmap.h>            /* for vtophys */
+#include <machine/clock.h>      /* for DELAY */
+#include <machine/bus_pio.h>
+#include <machine/bus_memio.h>
+#include <machine/bus.h>
+#include <machine/resource.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+
+#include <pci/pcireg.h>
+#include <pci/pcivar.h>
+
+#define SF_USEIOSPACE
+
+/* #define SF_BACKGROUND_AUTONEG */
+
+#include <pci/if_sfreg.h>
+
+#ifndef lint
+static const char rcsid[] =
+	"$Id: if_sf.c,v 1.11 1999/07/24 21:13:38 wpaul Exp $";
+#endif
+
+static struct sf_type sf_devs[] = {
+	{ AD_VENDORID, AD_DEVICEID_STARFIRE,
+		"Adaptec AIC-6915 10/100BaseTX" },
+	{ 0, 0, NULL }
+};
+
+static struct sf_type sf_phys[] = {
+	{ 0, 0, "<MII-compliant physical interface>" }
+};
+
+static int sf_probe		__P((device_t));
+static int sf_attach		__P((device_t));
+static int sf_detach		__P((device_t));
+static void sf_intr		__P((void *));
+static void sf_stats_update	__P((void *));
+static void sf_rxeof		__P((struct sf_softc *));
+static void sf_txeof		__P((struct sf_softc *));
+static int sf_encap		__P((struct sf_softc *,
+					struct sf_tx_bufdesc_type0 *,
+					struct mbuf *));
+static void sf_start		__P((struct ifnet *));
+static int sf_ioctl		__P((struct ifnet *, u_long, caddr_t));
+static void sf_init		__P((void *));
+static void sf_stop		__P((struct sf_softc *));
+static void sf_watchdog		__P((struct ifnet *));
+static void sf_shutdown		__P((device_t));
+static int sf_ifmedia_upd	__P((struct ifnet *));
+static void sf_ifmedia_sts	__P((struct ifnet *, struct ifmediareq *));
+static void sf_reset		__P((struct sf_softc *));
+static int sf_init_rx_ring	__P((struct sf_softc *));
+static void sf_init_tx_ring	__P((struct sf_softc *));
+static int sf_newbuf		__P((struct sf_softc *,
+					struct sf_rx_bufdesc_type0 *,
+					struct mbuf *));
+static void sf_setmulti		__P((struct sf_softc *));
+static int sf_setperf		__P((struct sf_softc *, int, caddr_t));
+static int sf_sethash		__P((struct sf_softc *, caddr_t, int));
+#ifdef notdef
+static int sf_setvlan		__P((struct sf_softc *, int, u_int32_t));
+#endif
+
+static u_int8_t sf_read_eeprom	__P((struct sf_softc *, int));
+static u_int32_t sf_calchash	__P((caddr_t));
+
+static int sf_phy_readreg	__P((struct sf_softc *, int));
+static void sf_phy_writereg	__P((struct sf_softc *, int, int));
+static void sf_autoneg_xmit	__P((struct sf_softc *));
+static void sf_autoneg_mii	__P((struct sf_softc *, int, int));
+static void sf_getmode_mii	__P((struct sf_softc *));
+static void sf_setmode_mii	__P((struct sf_softc *, int));
+
+static u_int32_t csr_read_4	__P((struct sf_softc *, int));
+static void csr_write_4		__P((struct sf_softc *, int, u_int32_t));
+
+#ifdef SF_USEIOSPACE
+#define SF_RES			SYS_RES_IOPORT
+#define SF_RID			SF_PCI_LOIO
+#else
+#define SF_RES			SYS_RES_MEMORY
+#define SF_RID			SF_PCI_LOMEM
+#endif
+
+static device_method_t sf_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		sf_probe),
+	DEVMETHOD(device_attach,	sf_attach),
+	DEVMETHOD(device_detach,	sf_detach),
+	DEVMETHOD(device_shutdown,	sf_shutdown),
+	{ 0, 0 }
+};
+
+static driver_t sf_driver = {
+	"sf",
+	sf_methods,
+	sizeof(struct sf_softc),
+};
+
+static devclass_t sf_devclass;
+
+DRIVER_MODULE(sf, pci, sf_driver, sf_devclass, 0, 0);
+
+#define SF_SETBIT(sc, reg, x)	\
+	csr_write_4(sc, reg, csr_read_4(sc, reg) | x)
+
+#define SF_CLRBIT(sc, reg, x)				\
+	csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x)
+
+static u_int32_t csr_read_4(sc, reg)
+	struct sf_softc		*sc;
+	int			reg;
+{
+	u_int32_t		val;
+
+#ifdef SF_USEIOSPACE
+	CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
+	val = CSR_READ_4(sc, SF_INDIRECTIO_DATA);
+#else
+	val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE));
+#endif
+
+	return(val);
+}
+
+static u_int8_t sf_read_eeprom(sc, reg)
+	struct sf_softc		*sc;
+	int			reg;
+{
+	u_int8_t		val;
+
+	val = (csr_read_4(sc, SF_EEADDR_BASE +
+	    (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF;
+
+	return(val);
+}
+
+static void csr_write_4(sc, reg, val)
+	struct sf_softc		*sc;
+	int			reg;
+	u_int32_t		val;
+{
+#ifdef SF_USEIOSPACE
+	CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
+	CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val);
+#else
+	CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val);
+#endif
+	return;
+}
+
+static u_int32_t sf_calchash(addr)
+	caddr_t			addr;
+{
+	u_int32_t		crc, carry;
+	int			i, j;
+	u_int8_t		c;
+
+	/* Compute CRC for the address value. */
+	crc = 0xFFFFFFFF; /* initial value */
+
+	for (i = 0; i < 6; i++) {
+		c = *(addr + i);
+		for (j = 0; j < 8; j++) {
+			carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
+			crc <<= 1;
+			c >>= 1;
+			if (carry)
+				crc = (crc ^ 0x04c11db6) | carry;
+		}
+	}
+
+	/* return the filter bit position */
+	return(crc >> 23 & 0x1FF);
+}
+
+/*
+ * Copy the address 'mac' into the perfect RX filter entry at
+ * offset 'idx.' The perfect filter only has 16 entries so do
+ * some sanity tests.
+ */
+static int sf_setperf(sc, idx, mac)
+	struct sf_softc		*sc;
+	int			idx;
+	caddr_t			mac;
+{
+	u_int16_t		*p;
+
+	if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT)
+		return(EINVAL);
+
+	if (mac == NULL)
+		return(EINVAL);
+
+	p = (u_int16_t *)mac;
+
+	csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
+	    (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2]));
+	csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
+	    (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1]));
+	csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
+	    (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0]));
+
+	return(0);
+}
+
+/*
+ * Set the bit in the 512-bit hash table that corresponds to the
+ * specified mac address 'mac.' If 'prio' is nonzero, update the
+ * priority hash table instead of the filter hash table.
+ */
+static int sf_sethash(sc, mac, prio)
+	struct sf_softc		*sc;
+	caddr_t			mac;
+	int			prio;
+{
+	u_int32_t		h = 0;
+
+	if (mac == NULL)
+		return(EINVAL);
+
+	h = sf_calchash(mac);
+
+	if (prio) {
+		SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF +
+		    (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
+	} else {
+		SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF +
+		    (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
+	}
+
+	return(0);
+}
+
+#ifdef notdef
+/*
+ * Set a VLAN tag in the receive filter.
+ */
+static int sf_setvlan(sc, idx, vlan)
+	struct sf_softc		*sc;
+	int			idx;
+	u_int32_t		vlan;
+{
+	if (idx < 0 || idx >> SF_RXFILT_HASH_CNT)
+		return(EINVAL);
+
+	csr_write_4(sc, SF_RXFILT_HASH_BASE +
+	    (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan);
+
+	return(0);
+}
+#endif
+
+static int sf_phy_readreg(sc, reg)
+	struct sf_softc		*sc;
+	int			reg;
+{
+	int			i;
+	u_int32_t		val = 0;
+
+	for (i = 0; i < SF_TIMEOUT; i++) {
+		val = csr_read_4(sc, SF_PHY_REG(sc->sf_phy_addr, reg));
+		if (val & SF_MII_DATAVALID)
+			break;
+	}
+
+	if (i == SF_TIMEOUT)
+		return(0);
+
+	if ((val & 0x0000FFFF) == 0xFFFF)
+		return(0);
+
+	return(val & 0x0000FFFF);
+}
+
+static void sf_phy_writereg(sc, reg, val)
+	struct sf_softc		*sc;
+	int			reg, val;
+{
+	int			i;
+	int			busy;
+
+	csr_write_4(sc, SF_PHY_REG(sc->sf_phy_addr, reg), val);
+
+	for (i = 0; i < SF_TIMEOUT; i++) {
+		busy = csr_read_4(sc, SF_PHY_REG(sc->sf_phy_addr, reg));
+		if (!(busy & SF_MII_BUSY))
+			break;
+	}
+
+	return;
+}
+
+static void sf_setmulti(sc)
+	struct sf_softc		*sc;
+{
+	struct ifnet		*ifp;
+	int			i;
+	struct ifmultiaddr	*ifma;
+	u_int8_t		dummy[] = { 0, 0, 0, 0, 0, 0 };
+
+	ifp = &sc->arpcom.ac_if;
+
+	/* First zot all the existing filters. */
+	for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++)
+		sf_setperf(sc, i, (char *)&dummy);
+	for (i = SF_RXFILT_HASH_BASE;
+	    i < (SF_RXFILT_HASH_MAX + 1); i += 4)
+		csr_write_4(sc, i, 0);
+	SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
+
+	/* Now program new ones. */
+	if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
+		SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
+	} else {
+		i = 1;
+		/* First find the tail of the list. */
+		for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
+					ifma = ifma->ifma_link.le_next) {
+			if (ifma->ifma_link.le_next == NULL)
+				break;
+		}
+		/* Now traverse the list backwards. */
+		for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
+			ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
+			if (ifma->ifma_addr->sa_family != AF_LINK)
+				continue;
+			/*
+			 * Program the first 15 multicast groups
+			 * into the perfect filter. For all others,
+			 * use the hash table.
+			 */
+			if (i < SF_RXFILT_PERFECT_CNT) {
+				sf_setperf(sc, i,
+			LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
+				i++;
+				continue;
+			}
+
+			sf_sethash(sc,
+			    LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0);
+		}
+	}
+
+	return;
+}
+
+/*
+ * Initiate an autonegotiation session.
+ */
+static void sf_autoneg_xmit(sc)
+	struct sf_softc		*sc;
+{
+	u_int16_t		phy_sts;
+
+	sf_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
+	DELAY(500);
+	while(sf_phy_readreg(sc, PHY_BMCR)
+			& PHY_BMCR_RESET);
+
+	phy_sts = sf_phy_readreg(sc, PHY_BMCR);
+	phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR;
+	sf_phy_writereg(sc, PHY_BMCR, phy_sts);
+
+	return;
+}
+
+/*
+ * Invoke autonegotiation on a PHY.
+ */
+static void sf_autoneg_mii(sc, flag, verbose)
+	struct sf_softc		*sc;
+	int			flag;
+	int			verbose;
+{
+	u_int16_t		phy_sts = 0, media, advert, ability;
+	struct ifnet		*ifp;
+	struct ifmedia		*ifm;
+
+	ifm = &sc->ifmedia;
+	ifp = &sc->arpcom.ac_if;
+
+	ifm->ifm_media = IFM_ETHER | IFM_AUTO;
+
+#ifndef FORCE_AUTONEG_TFOUR
+	/*
+	 * First, see if autoneg is supported. If not, there's
+	 * no point in continuing.
+	 */
+	phy_sts = sf_phy_readreg(sc, PHY_BMSR);
+	if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
+		if (verbose)
+			printf("sf%d: autonegotiation not supported\n",
+							sc->sf_unit);
+		ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;	
+		return;
+	}
+#endif
+
+	switch (flag) {
+	case SF_FLAG_FORCEDELAY:
+		/*
+	 	 * XXX Never use this option anywhere but in the probe
+	 	 * routine: making the kernel stop dead in its tracks
+ 		 * for three whole seconds after we've gone multi-user
+		 * is really bad manners.
+	 	 */
+		sf_autoneg_xmit(sc);
+		DELAY(5000000);
+		break;
+	case SF_FLAG_SCHEDDELAY:
+		/*
+		 * Wait for the transmitter to go idle before starting
+		 * an autoneg session, otherwise sf_start() may clobber
+	 	 * our timeout, and we don't want to allow transmission
+		 * during an autoneg session since that can screw it up.
+	 	 */
+		if (sc->sf_tx_cnt) {
+			sc->sf_want_auto = 1;
+			return;
+		}
+		sf_autoneg_xmit(sc);
+		ifp->if_timer = 5;
+		sc->sf_autoneg = 1;
+		sc->sf_want_auto = 0;
+		return;
+		break;
+	case SF_FLAG_DELAYTIMEO:
+		ifp->if_timer = 0;
+		sc->sf_autoneg = 0;
+		break;
+	default:
+		printf("sf%d: invalid autoneg flag: %d\n", sc->sf_unit, flag);
+		return;
+	}
+
+	if (sf_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
+		if (verbose)
+			printf("sf%d: autoneg complete, ", sc->sf_unit);
+		phy_sts = sf_phy_readreg(sc, PHY_BMSR);
+	} else {
+		if (verbose)
+			printf("sf%d: autoneg not complete, ", sc->sf_unit);
+	}
+
+	media = sf_phy_readreg(sc, PHY_BMCR);
+
+	/* Link is good. Report modes and set duplex mode. */
+	if (sf_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
+		if (verbose)
+			printf("link status good ");
+		advert = sf_phy_readreg(sc, PHY_ANAR);
+		ability = sf_phy_readreg(sc, PHY_LPAR);
+
+		if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
+			ifm->ifm_media = IFM_ETHER|IFM_100_T4;
+			media |= PHY_BMCR_SPEEDSEL;
+			media &= ~PHY_BMCR_DUPLEX;
+			printf("(100baseT4)\n");
+		} else if (advert & PHY_ANAR_100BTXFULL &&
+			ability & PHY_ANAR_100BTXFULL) {
+			ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
+			media |= PHY_BMCR_SPEEDSEL;
+			media |= PHY_BMCR_DUPLEX;
+			printf("(full-duplex, 100Mbps)\n");
+		} else if (advert & PHY_ANAR_100BTXHALF &&
+			ability & PHY_ANAR_100BTXHALF) {
+			ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
+			media |= PHY_BMCR_SPEEDSEL;
+			media &= ~PHY_BMCR_DUPLEX;
+			printf("(half-duplex, 100Mbps)\n");
+		} else if (advert & PHY_ANAR_10BTFULL &&
+			ability & PHY_ANAR_10BTFULL) {
+			ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
+			media &= ~PHY_BMCR_SPEEDSEL;
+			media |= PHY_BMCR_DUPLEX;
+			printf("(full-duplex, 10Mbps)\n");
+		} else if (advert & PHY_ANAR_10BTHALF &&
+			ability & PHY_ANAR_10BTHALF) {
+			ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
+			media &= ~PHY_BMCR_SPEEDSEL;
+			media &= ~PHY_BMCR_DUPLEX;
+			printf("(half-duplex, 10Mbps)\n");
+		}
+
+		media &= ~PHY_BMCR_AUTONEGENBL;
+
+		/* Set ASIC's duplex mode to match the PHY. */
+		sf_phy_writereg(sc, PHY_BMCR, media);
+		if ((media & IFM_GMASK) == IFM_FDX) {
+			SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
+		} else {
+			SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
+		}
+	} else {
+		if (verbose)
+			printf("no carrier\n");
+	}
+
+	sf_init(sc);
+
+	if (sc->sf_tx_pend) {
+		sc->sf_autoneg = 0;
+		sc->sf_tx_pend = 0;
+		sf_start(ifp);
+	}
+
+	return;
+}
+
+static void sf_getmode_mii(sc)
+	struct sf_softc		*sc;
+{
+	u_int16_t		bmsr;
+	struct ifnet		*ifp;
+
+	ifp = &sc->arpcom.ac_if;
+
+	bmsr = sf_phy_readreg(sc, PHY_BMSR);
+	if (bootverbose)
+		printf("sf%d: PHY status word: %x\n", sc->sf_unit, bmsr);
+
+	/* fallback */
+	sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
+
+	if (bmsr & PHY_BMSR_10BTHALF) {
+		if (bootverbose)
+			printf("sf%d: 10Mbps half-duplex mode supported\n",
+								sc->sf_unit);
+		ifmedia_add(&sc->ifmedia,
+			IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
+		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
+	}
+
+	if (bmsr & PHY_BMSR_10BTFULL) {
+		if (bootverbose)
+			printf("sf%d: 10Mbps full-duplex mode supported\n",
+								sc->sf_unit);
+		ifmedia_add(&sc->ifmedia,
+			IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
+		sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
+	}
+
+	if (bmsr & PHY_BMSR_100BTXHALF) {
+		if (bootverbose)
+			printf("sf%d: 100Mbps half-duplex mode supported\n",
+								sc->sf_unit);
+		ifp->if_baudrate = 100000000;
+		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
+		ifmedia_add(&sc->ifmedia,
+			IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
+		sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
+	}
+
+	if (bmsr & PHY_BMSR_100BTXFULL) {
+		if (bootverbose)
+			printf("sf%d: 100Mbps full-duplex mode supported\n",
+								sc->sf_unit);
+		ifp->if_baudrate = 100000000;
+		ifmedia_add(&sc->ifmedia,
+			IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
+		sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
+	}
+
+	/* Some also support 100BaseT4. */
+	if (bmsr & PHY_BMSR_100BT4) {
+		if (bootverbose)
+			printf("sf%d: 100baseT4 mode supported\n", sc->sf_unit);
+		ifp->if_baudrate = 100000000;
+		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL);
+		sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_T4;
+#ifdef FORCE_AUTONEG_TFOUR
+		if (bootverbose)
+			printf("sf%d: forcing on autoneg support for BT4\n",
+							 sc->sf_unit);
+		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0 NULL):
+		sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
+#endif
+	}
+
+	if (bmsr & PHY_BMSR_CANAUTONEG) {
+		if (bootverbose)
+			printf("sf%d: autoneg supported\n", sc->sf_unit);
+		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
+		sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
+	}
+
+	return;
+}
+
+/*
+ * Set speed and duplex mode.
+ */
+static void sf_setmode_mii(sc, media)
+	struct sf_softc		*sc;
+	int			media;
+{
+	u_int16_t		bmcr;
+	struct ifnet		*ifp;
+
+	ifp = &sc->arpcom.ac_if;
+
+	/*
+	 * If an autoneg session is in progress, stop it.
+	 */
+	if (sc->sf_autoneg) {
+		printf("sf%d: canceling autoneg session\n", sc->sf_unit);
+		ifp->if_timer = sc->sf_autoneg = sc->sf_want_auto = 0;
+		bmcr = sf_phy_readreg(sc, PHY_BMCR);
+		bmcr &= ~PHY_BMCR_AUTONEGENBL;
+		sf_phy_writereg(sc, PHY_BMCR, bmcr);
+	}
+
+	printf("sf%d: selecting MII, ", sc->sf_unit);
+
+	bmcr = sf_phy_readreg(sc, PHY_BMCR);
+
+	bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL|
+			PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK);
+
+	if (IFM_SUBTYPE(media) == IFM_100_T4) {
+		printf("100Mbps/T4, half-duplex\n");
+		bmcr |= PHY_BMCR_SPEEDSEL;
+		bmcr &= ~PHY_BMCR_DUPLEX;
+	}
+
+	if (IFM_SUBTYPE(media) == IFM_100_TX) {
+		printf("100Mbps, ");
+		bmcr |= PHY_BMCR_SPEEDSEL;
+	}
+
+	if (IFM_SUBTYPE(media) == IFM_10_T) {
+		printf("10Mbps, ");
+		bmcr &= ~PHY_BMCR_SPEEDSEL;
+	}
+
+	if ((media & IFM_GMASK) == IFM_FDX) {
+		printf("full duplex\n");
+		bmcr |= PHY_BMCR_DUPLEX;
+		SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
+	} else {
+		printf("half duplex\n");
+		bmcr &= ~PHY_BMCR_DUPLEX;
+		SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
+	}
+
+	sf_phy_writereg(sc, PHY_BMCR, bmcr);
+
+	return;
+}
+
+/*
+ * Set media options.
+ */
+static int sf_ifmedia_upd(ifp)
+	struct ifnet		*ifp;
+{
+	struct sf_softc		*sc;
+	struct ifmedia		*ifm;
+
+	sc = ifp->if_softc;
+	ifm = &sc->ifmedia;
+
+	if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
+		return(EINVAL);
+
+	if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
+		sf_autoneg_mii(sc, SF_FLAG_SCHEDDELAY, 1);
+	else {
+		sf_setmode_mii(sc, ifm->ifm_media);
+	}
+
+	return(0);
+}
+
+/*
+ * Report current media status.
+ */
+static void sf_ifmedia_sts(ifp, ifmr)
+	struct ifnet		*ifp;
+	struct ifmediareq	*ifmr;
+{
+	struct sf_softc		*sc;
+	u_int16_t		advert = 0, ability = 0;
+
+	sc = ifp->if_softc;
+
+	ifmr->ifm_active = IFM_ETHER;
+
+	if (!(sf_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
+		if (sf_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
+			ifmr->ifm_active = IFM_ETHER|IFM_100_TX;
+		else
+			ifmr->ifm_active = IFM_ETHER|IFM_10_T;
+		if (sf_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
+			ifmr->ifm_active |= IFM_FDX;
+		else
+			ifmr->ifm_active |= IFM_HDX;
+		return;
+	}
+
+	ability = sf_phy_readreg(sc, PHY_LPAR);
+	advert = sf_phy_readreg(sc, PHY_ANAR);
+	if (advert & PHY_ANAR_100BT4 &&
+		ability & PHY_ANAR_100BT4) {
+		ifmr->ifm_active = IFM_ETHER|IFM_100_T4;
+	} else if (advert & PHY_ANAR_100BTXFULL &&
+		ability & PHY_ANAR_100BTXFULL) {
+		ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_FDX;
+	} else if (advert & PHY_ANAR_100BTXHALF &&
+		ability & PHY_ANAR_100BTXHALF) {
+		ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_HDX;
+	} else if (advert & PHY_ANAR_10BTFULL &&
+		ability & PHY_ANAR_10BTFULL) {
+		ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_FDX;
+	} else if (advert & PHY_ANAR_10BTHALF &&
+		ability & PHY_ANAR_10BTHALF) {
+		ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_HDX;
+	}
+
+	return;
+}
+
+static int sf_ioctl(ifp, command, data)
+	struct ifnet		*ifp;
+	u_long			command;
+	caddr_t			data;
+{
+	struct sf_softc		*sc = ifp->if_softc;
+	struct ifreq		*ifr = (struct ifreq *) data;
+	int			s, error = 0;
+
+	s = splimp();
+
+	switch(command) {
+	case SIOCSIFADDR:
+	case SIOCGIFADDR:
+	case SIOCSIFMTU:
+		error = ether_ioctl(ifp, command, data);
+		break;
+	case SIOCSIFFLAGS:
+		if (ifp->if_flags & IFF_UP) {
+			sf_init(sc);
+		} else {
+			if (ifp->if_flags & IFF_RUNNING)
+				sf_stop(sc);
+		}
+		error = 0;
+		break;
+	case SIOCADDMULTI:
+	case SIOCDELMULTI:
+		sf_setmulti(sc);
+		error = 0;
+		break;
+	case SIOCGIFMEDIA:
+	case SIOCSIFMEDIA:
+		error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
+		break;
+	default:
+		error = EINVAL;
+		break;
+	}
+
+	(void)splx(s);
+
+	return(error);
+}
+
+static void sf_reset(sc)
+	struct sf_softc		*sc;
+{
+	register int		i;
+
+	csr_write_4(sc, SF_GEN_ETH_CTL, 0);
+	SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
+	DELAY(1000);
+	SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
+
+	SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET);
+
+	for (i = 0; i < SF_TIMEOUT; i++) {
+		DELAY(10);
+		if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET))
+			break;
+	}
+
+	if (i == SF_TIMEOUT)
+		printf("sf%d: reset never completed!\n", sc->sf_unit);
+
+	/* Wait a little while for the chip to get its brains in order. */
+	DELAY(1000);
+	return;
+}
+
+/*
+ * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device
+ * IDs against our list and return a device name if we find a match.
+ * We also check the subsystem ID so that we can identify exactly which
+ * NIC has been found, if possible.
+ */
+static int sf_probe(dev)
+	device_t		dev;
+{
+	struct sf_type		*t;
+
+	t = sf_devs;
+
+	while(t->sf_name != NULL) {
+		if ((pci_get_vendor(dev) == t->sf_vid) &&
+		    (pci_get_device(dev) == t->sf_did)) {
+			switch(pci_read_config(dev,
+			    SF_PCI_SUBVEN_ID >> 16, 4) & 0x8FFF) {
+			case AD_SUBSYSID_62011_REV0:
+			case AD_SUBSYSID_62011_REV1:
+				device_set_desc(dev,
+				    "Adaptec ANA-62011 10/100BaseTX");
+				return(0);
+				break;
+			case AD_SUBSYSID_62022:
+				device_set_desc(dev,
+				    "Adaptec ANA-62022 10/100BaseTX");
+				return(0);
+				break;
+			case AD_SUBSYSID_62044:
+				device_set_desc(dev,
+				    "Adaptec ANA-62044 10/100BaseTX");
+				return(0);
+				break;
+			case AD_SUBSYSID_62020:
+				device_set_desc(dev,
+				    "Adaptec ANA-62020 10/100BaseFX");
+				return(0);
+				break;
+			case AD_SUBSYSID_69011:
+				device_set_desc(dev,
+				    "Adaptec ANA-69011 10/100BaseTX");
+				return(0);
+				break;
+			default:
+				device_set_desc(dev, t->sf_name);
+				return(0);
+				break;
+			}
+		}
+		t++;
+	}
+
+	return(ENXIO);
+}
+
+/*
+ * Attach the interface. Allocate softc structures, do ifmedia
+ * setup and ethernet/BPF attach.
+ */
+static int sf_attach(dev)
+	device_t		dev;
+{
+	int			s, i;
+	u_int32_t		command;
+	struct sf_softc		*sc;
+	struct ifnet		*ifp;
+	int			media = IFM_ETHER|IFM_100_TX|IFM_FDX;
+	struct sf_type		*p;
+	u_int16_t		phy_vid, phy_did, phy_sts;
+	int			unit, rid, error = 0;
+
+	s = splimp();
+
+	sc = device_get_softc(dev);
+	unit = device_get_unit(dev);
+	bzero(sc, sizeof(struct sf_softc));
+
+	/*
+	 * Handle power management nonsense.
+	 */
+	command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF;
+	if (command == 0x01) {
+
+		command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4);
+		if (command & SF_PSTATE_MASK) {
+			u_int32_t		iobase, membase, irq;
+
+			/* Save important PCI config data. */
+			iobase = pci_read_config(dev, SF_PCI_LOIO, 4);
+			membase = pci_read_config(dev, SF_PCI_LOMEM, 4);
+			irq = pci_read_config(dev, SF_PCI_INTLINE, 4);
+
+			/* Reset the power state. */
+			printf("sf%d: chip is in D%d power mode "
+			"-- setting to D0\n", unit, command & SF_PSTATE_MASK);
+			command &= 0xFFFFFFFC;
+			pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4);
+
+			/* Restore PCI config data. */
+			pci_write_config(dev, SF_PCI_LOIO, iobase, 4);
+			pci_write_config(dev, SF_PCI_LOMEM, membase, 4);
+			pci_write_config(dev, SF_PCI_INTLINE, irq, 4);
+		}
+	}
+
+	/*
+	 * Map control/status registers.
+	 */
+	command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4);
+	command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
+	pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4);
+	command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4);
+
+#ifdef SF_USEIOSPACE
+	if (!(command & PCIM_CMD_PORTEN)) {
+		printf("sf%d: failed to enable I/O ports!\n", unit);
+		error = ENXIO;
+		goto fail;
+	}
+#else
+	if (!(command & PCIM_CMD_MEMEN)) {
+		printf("sf%d: failed to enable memory mapping!\n", unit);
+		error = ENXIO;
+		goto fail;
+	}
+#endif
+
+	rid = SF_RID;
+	sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid,
+	    0, ~0, 1, RF_ACTIVE);
+
+	if (sc->sf_res == NULL) {
+		printf ("sf%d: couldn't map ports\n", unit);
+		error = ENXIO;
+		goto fail;
+	}
+
+	sc->sf_btag = rman_get_bustag(sc->sf_res);
+	sc->sf_bhandle = rman_get_bushandle(sc->sf_res);
+
+	/* Allocate interrupt */
+	rid = 0;
+	sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
+	    RF_SHAREABLE | RF_ACTIVE);
+
+	if (sc->sf_irq == NULL) {
+		printf("sf%d: couldn't map interrupt\n", unit);
+		bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
+		error = ENXIO;
+		goto fail;
+	}
+
+	error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET,
+	    sf_intr, sc, &sc->sf_intrhand);
+
+	if (error) {
+		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res);
+		bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
+		printf("sf%d: couldn't set up irq\n", unit);
+		goto fail;
+	}
+
+	callout_handle_init(&sc->sf_stat_ch);
+
+	/* Reset the adapter. */
+	sf_reset(sc);
+
+	/*
+	 * Get station address from the EEPROM.
+	 */
+	for (i = 0; i < ETHER_ADDR_LEN; i++)
+		sc->arpcom.ac_enaddr[i] =
+		    sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i);
+
+	/*
+	 * An Adaptec chip was detected. Inform the world.
+	 */
+	printf("sf%d: Ethernet address: %6D\n", unit,
+	    sc->arpcom.ac_enaddr, ":");
+
+	sc->sf_unit = unit;
+
+	/* Allocate the descriptor queues. */
+	sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF,
+	    M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0);
+
+	if (sc->sf_ldata == NULL) {
+		printf("sf%d: no memory for list buffers!\n", unit);
+		bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
+		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
+		bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
+		error = ENXIO;
+		goto fail;
+	}
+
+	bzero(sc->sf_ldata, sizeof(struct sf_list_data));
+
+	if (bootverbose)
+		printf("sf%d: probing for a PHY\n", sc->sf_unit);
+	for (i = SF_PHYADDR_MIN; i < SF_PHYADDR_MAX + 1; i++) {
+		if (bootverbose)
+			printf("sf%d: checking address: %d\n",
+						sc->sf_unit, i);
+		sc->sf_phy_addr = i;
+		sf_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
+		DELAY(500);
+		while(sf_phy_readreg(sc, PHY_BMCR)
+				& PHY_BMCR_RESET);
+		if ((phy_sts = sf_phy_readreg(sc, PHY_BMSR)))
+			break;
+	}
+	if (phy_sts) {
+		phy_vid = sf_phy_readreg(sc, PHY_VENID);
+		phy_did = sf_phy_readreg(sc, PHY_DEVID);
+		if (bootverbose)
+			printf("sf%d: found PHY at address %d, ",
+				sc->sf_unit, sc->sf_phy_addr);
+		if (bootverbose)
+			printf("vendor id: %x device id: %x\n",
+			phy_vid, phy_did);
+		p = sf_phys;
+		while(p->sf_vid) {
+			if (phy_vid == p->sf_vid &&
+				(phy_did | 0x000F) == p->sf_did) {
+				sc->sf_pinfo = p;
+				break;
+			}
+			p++;
+		}
+		if (sc->sf_pinfo == NULL)
+			sc->sf_pinfo = &sf_phys[PHY_UNKNOWN];
+		if (bootverbose)
+			printf("sf%d: PHY type: %s\n",
+				sc->sf_unit, sc->sf_pinfo->sf_name);
+	} else {
+		printf("sf%d: MII without any phy!\n", sc->sf_unit);
+		free(sc->sf_ldata, M_DEVBUF);
+		bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
+		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
+		bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
+		error = ENXIO;
+		goto fail;
+	}
+
+	ifp = &sc->arpcom.ac_if;
+	ifp->if_softc = sc;
+	ifp->if_unit = unit;
+	ifp->if_name = "sf";
+	ifp->if_mtu = ETHERMTU;
+	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+	ifp->if_ioctl = sf_ioctl;
+	ifp->if_output = ether_output;
+	ifp->if_start = sf_start;
+	ifp->if_watchdog = sf_watchdog;
+	ifp->if_init = sf_init;
+	ifp->if_baudrate = 10000000;
+	ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1;
+
+	/*
+	 * Do ifmedia setup.
+	 */
+	ifmedia_init(&sc->ifmedia, 0, sf_ifmedia_upd, sf_ifmedia_sts);
+
+	sf_getmode_mii(sc);
+	if (cold) {
+		sf_autoneg_mii(sc, SF_FLAG_FORCEDELAY, 1);
+		sf_stop(sc);
+	} else {
+		sf_init(sc);
+		sf_autoneg_mii(sc, SF_FLAG_SCHEDDELAY, 1);
+	}
+
+	media = sc->ifmedia.ifm_media;
+	ifmedia_set(&sc->ifmedia, media);
+
+	/*
+	 * Call MI attach routines.
+	 */
+	if_attach(ifp);
+	ether_ifattach(ifp);
+
+#if NBPF > 0
+	bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
+#endif
+
+fail:
+	splx(s);
+	return(error);
+}
+
+static int sf_detach(dev)
+	device_t		dev;
+{
+	struct sf_softc		*sc;
+	struct ifnet		*ifp;
+	int			s;
+
+	s = splimp();
+
+	sc = device_get_softc(dev);
+	ifp = &sc->arpcom.ac_if;
+
+	if_detach(ifp);
+	sf_stop(sc);
+
+	bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
+	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
+	bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
+
+	free(sc->sf_ldata, M_DEVBUF);
+	ifmedia_removeall(&sc->ifmedia);
+
+	splx(s);
+
+	return(0);
+}
+
+static int sf_init_rx_ring(sc)
+	struct sf_softc		*sc;
+{
+	struct sf_list_data	*ld;
+	int			i;
+
+	ld = sc->sf_ldata;
+
+	bzero((char *)ld->sf_rx_dlist_big,
+	    sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT);
+	bzero((char *)ld->sf_rx_clist,
+	    sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT);
+
+	for (i = 0; i < SF_RX_DLIST_CNT; i++) {
+		if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS)
+			return(ENOBUFS);
+	}
+
+	return(0);
+}
+
+static void sf_init_tx_ring(sc)
+	struct sf_softc		*sc;
+{
+	struct sf_list_data	*ld;
+	int			i;
+
+	ld = sc->sf_ldata;
+
+	bzero((char *)ld->sf_tx_dlist,
+	    sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT);
+	bzero((char *)ld->sf_tx_clist,
+	    sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT);
+
+	for (i = 0; i < SF_TX_DLIST_CNT; i++)
+		ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID;
+	for (i = 0; i < SF_TX_CLIST_CNT; i++)
+		ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX;
+
+	ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1;
+	sc->sf_tx_cnt = 0;
+
+	return;
+}
+
+static int sf_newbuf(sc, c, m)
+	struct sf_softc		*sc;
+	struct sf_rx_bufdesc_type0	*c;
+	struct mbuf		*m;
+{
+	struct mbuf		*m_new = NULL;
+
+	if (m == NULL) {
+		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
+		if (m_new == NULL) {
+			printf("sf%d: no memory for rx list -- "
+			    "packet dropped!\n", sc->sf_unit);
+			return(ENOBUFS);
+		}
+
+		MCLGET(m_new, M_DONTWAIT);
+		if (!(m_new->m_flags & M_EXT)) {
+			printf("sf%d: no memory for rx list -- "
+			    "packet dropped!\n", sc->sf_unit);
+			m_freem(m_new);
+			return(ENOBUFS);
+		}
+		m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
+	} else {
+		m_new = m;
+		m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
+		m_new->m_data = m_new->m_ext.ext_buf;
+	}
+
+	m_adj(m_new, sizeof(u_int64_t));
+
+	c->sf_mbuf = m_new;
+	c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t)));
+	c->sf_valid = 1;
+
+	return(0);
+}
+
+/*
+ * The starfire is programmed to use 'normal' mode for packet reception,
+ * which means we use the consumer/producer model for both the buffer
+ * descriptor queue and the completion descriptor queue. The only problem
+ * with this is that it involves a lot of register accesses: we have to
+ * read the RX completion consumer and producer indexes and the RX buffer
+ * producer index, plus the RX completion consumer and RX buffer producer
+ * indexes have to be updated. It would have been easier if Adaptec had
+ * put each index in a separate register, especially given that the damn
+ * NIC has a 512K register space.
+ *
+ * In spite of all the lovely features that Adaptec crammed into the 6915,
+ * it is marred by one truly stupid design flaw, which is that receive
+ * buffer addresses must be aligned on a longword boundary. This forces
+ * the packet payload to be unaligned, which is suboptimal on the x86 and
+ * completely unuseable on the Alpha. Our only recourse is to copy received
+ * packets into properly aligned buffers before handing them off.
+ */
+
+static void sf_rxeof(sc)
+	struct sf_softc		*sc;
+{
+	struct ether_header	*eh;
+	struct mbuf		*m;
+	struct ifnet		*ifp;
+	struct sf_rx_bufdesc_type0	*desc;
+	struct sf_rx_cmpdesc_type3	*cur_rx;
+	u_int32_t		rxcons, rxprod;
+	int			cmpprodidx, cmpconsidx, bufprodidx;
+
+	ifp = &sc->arpcom.ac_if;
+
+	rxcons = csr_read_4(sc, SF_CQ_CONSIDX);
+	rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1);
+	cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX));
+	cmpconsidx = SF_IDX_LO(rxcons);
+	bufprodidx = SF_IDX_LO(rxprod);
+
+	while (cmpconsidx != cmpprodidx) {
+		struct mbuf		*m0;
+
+		cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx];
+		desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx];
+		m = desc->sf_mbuf;
+		SF_INC(cmpconsidx, SF_RX_CLIST_CNT);
+		SF_INC(bufprodidx, SF_RX_DLIST_CNT);
+
+		if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) {
+			ifp->if_ierrors++;
+			sf_newbuf(sc, desc, m);
+			continue;
+		}
+
+		m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
+		    cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL);
+		sf_newbuf(sc, desc, m);
+		if (m0 == NULL) {
+			ifp->if_ierrors++;
+			continue;
+		}
+		m_adj(m0, ETHER_ALIGN);
+		m = m0;
+
+		eh = mtod(m, struct ether_header *);
+		ifp->if_ipackets++;
+
+#if NBPF > 0
+		if (ifp->if_bpf) {
+			bpf_mtap(ifp, m);
+			if (ifp->if_flags & IFF_PROMISC &&
+			    (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
+			    ETHER_ADDR_LEN) && !(eh->ether_dhost[0] & 1))) {
+				m_freem(m);
+				continue;
+			}
+		}
+#endif
+
+		/* Remove header from mbuf and pass it on. */
+		m_adj(m, sizeof(struct ether_header));
+		ether_input(ifp, eh, m);
+
+	}
+
+	csr_write_4(sc, SF_CQ_CONSIDX,
+	    (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx);
+	csr_write_4(sc, SF_RXDQ_PTR_Q1,
+	    (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx);
+
+	return;
+}
+
+/*
+ * Read the transmit status from the completion queue and release
+ * mbufs. Note that the buffer descriptor index in the completion
+ * descriptor is an offset from the start of the transmit buffer
+ * descriptor list in bytes. This is important because the manual
+ * gives the impression that it should match the producer/consumer
+ * index, which is the offset in 8 byte blocks.
+ */
+static void sf_txeof(sc)
+	struct sf_softc		*sc;
+{
+	int			txcons, cmpprodidx, cmpconsidx;
+	struct sf_tx_cmpdesc_type1 *cur_cmp;
+	struct sf_tx_bufdesc_type0 *cur_tx;
+	struct ifnet		*ifp;
+
+	ifp = &sc->arpcom.ac_if;
+
+	txcons = csr_read_4(sc, SF_CQ_CONSIDX);
+	cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX));
+	cmpconsidx = SF_IDX_HI(txcons);
+
+	while (cmpconsidx != cmpprodidx) {
+		cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx];
+		cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7];
+		SF_INC(cmpconsidx, SF_TX_CLIST_CNT);
+
+		if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK)
+			ifp->if_opackets++;
+		else
+			ifp->if_oerrors++;
+
+		sc->sf_tx_cnt--;
+		if (cur_tx->sf_mbuf != NULL) {
+			m_freem(cur_tx->sf_mbuf);
+			cur_tx->sf_mbuf = NULL;
+		}
+	}
+
+	ifp->if_timer = 0;
+	ifp->if_flags &= ~IFF_OACTIVE;
+
+	csr_write_4(sc, SF_CQ_CONSIDX,
+	    (txcons & ~SF_CQ_CONSIDX_TXQ) |
+	    ((cmpconsidx << 16) & 0xFFFF0000));
+
+	return;
+}
+
+static void sf_intr(arg)
+	void			*arg;
+{
+	struct sf_softc		*sc;
+	struct ifnet		*ifp;
+	u_int32_t		status;
+
+	sc = arg;
+	ifp = &sc->arpcom.ac_if;
+
+	if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED))
+		return;
+
+	/* Disable interrupts. */
+	csr_write_4(sc, SF_IMR, 0x00000000);
+
+	for (;;) {
+		status = csr_read_4(sc, SF_ISR);
+		if (status)
+			csr_write_4(sc, SF_ISR, status);
+
+		if (!(status & SF_INTRS))
+			break;
+
+		if (status & SF_ISR_RXDQ1_DMADONE)
+			sf_rxeof(sc);
+
+		if (status & SF_ISR_TX_TXDONE)
+			sf_txeof(sc);
+
+		if (status & SF_ISR_ABNORMALINTR) {
+			if (status & SF_ISR_STATSOFLOW) {
+				untimeout(sf_stats_update, sc,
+				    sc->sf_stat_ch);
+				sf_stats_update(sc);
+			} else
+				sf_init(sc);
+		}
+	}
+
+	/* Re-enable interrupts. */
+	csr_write_4(sc, SF_IMR, SF_INTRS);
+
+	if (ifp->if_snd.ifq_head != NULL)
+		sf_start(ifp);
+
+	return;
+}
+
+static void sf_init(xsc)
+	void			*xsc;
+{
+	struct sf_softc		*sc;
+	struct ifnet		*ifp;
+	int			i, s;
+
+	s = splimp();
+
+	sc = xsc;
+	ifp = &sc->arpcom.ac_if;
+
+	sf_stop(sc);
+	sf_reset(sc);
+
+	/* Init all the receive filter registers */
+	for (i = SF_RXFILT_PERFECT_BASE;
+	    i < (SF_RXFILT_HASH_MAX + 1); i += 4)
+		csr_write_4(sc, i, 0);
+
+	/* Empty stats counter registers. */
+	for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++)
+		csr_write_4(sc, SF_STATS_BASE +
+		    (i + sizeof(u_int32_t)), 0);
+
+	/* Init our MAC address */
+	csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
+	csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
+	sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr);
+
+	if (sf_init_rx_ring(sc) == ENOBUFS) {
+		printf("sf%d: initialization failed: no "
+		    "memory for rx buffers\n", sc->sf_unit);
+		(void)splx(s);
+		return;
+	}
+
+	sf_init_tx_ring(sc);
+
+	csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN);
+
+	/* If we want promiscuous mode, set the allframes bit. */
+	if (ifp->if_flags & IFF_PROMISC) {
+		SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
+	} else {
+		SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
+	}
+
+	if (ifp->if_flags & IFF_BROADCAST) {
+		SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
+	} else {
+		SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
+	}
+
+	/* Init the completion queue indexes */
+	csr_write_4(sc, SF_CQ_CONSIDX, 0);
+	csr_write_4(sc, SF_CQ_PRODIDX, 0);
+
+	/* Init the RX completion queue */
+	csr_write_4(sc, SF_RXCQ_CTL_1,
+	    vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR);
+	SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3);
+
+	/* Init RX DMA control. */
+	SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS);
+
+	/* Init the RX buffer descriptor queue. */
+	csr_write_4(sc, SF_RXDQ_ADDR_Q1,
+	    vtophys(sc->sf_ldata->sf_rx_dlist_big));
+	csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES);
+	csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1);
+
+	/* Init the TX completion queue */
+	csr_write_4(sc, SF_TXCQ_CTL,
+	    vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR);
+
+	/* Init the TX buffer descriptor queue. */
+	csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO,
+		vtophys(sc->sf_ldata->sf_tx_dlist));
+	SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX);
+	csr_write_4(sc, SF_TXDQ_CTL,
+	    SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES);
+	SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP);
+
+	/* Enable autopadding of short TX frames. */
+	SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD);
+
+	/* Make sure the duplex mode is set correctly. */
+	if ((sc->ifmedia.ifm_media & IFM_GMASK) == IFM_FDX) {
+		SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
+	} else {
+		SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
+	}       
+
+	/* Enable interrupts. */
+	csr_write_4(sc, SF_IMR, SF_INTRS);
+	SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB);
+
+	/* Enable the RX and TX engines. */
+	SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB);
+	SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB);
+
+	ifp->if_flags |= IFF_RUNNING;
+	ifp->if_flags &= ~IFF_OACTIVE;
+
+	sc->sf_stat_ch = timeout(sf_stats_update, sc, hz);
+
+	splx(s);
+
+	return;
+}
+
+static int sf_encap(sc, c, m_head)
+	struct sf_softc		*sc;
+	struct sf_tx_bufdesc_type0 *c;
+	struct mbuf		*m_head;
+{
+	int			frag = 0;
+	struct sf_frag		*f = NULL;
+	struct mbuf		*m;
+
+	m = m_head;
+
+	for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
+		if (m->m_len != 0) {
+			if (frag == SF_MAXFRAGS)
+				break;
+			f = &c->sf_frags[frag];
+			if (frag == 0)
+				f->sf_pktlen = m_head->m_pkthdr.len;
+			f->sf_fraglen = m->m_len;
+			f->sf_addr = vtophys(mtod(m, vm_offset_t));
+			frag++;
+		}
+	}
+
+	if (m != NULL) {
+		struct mbuf		*m_new = NULL;
+
+		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
+		if (m_new == NULL) {
+			printf("sf%d: no memory for tx list", sc->sf_unit);
+			return(1);
+		}
+
+		if (m_head->m_pkthdr.len > MHLEN) {
+			MCLGET(m_new, M_DONTWAIT);
+			if (!(m_new->m_flags & M_EXT)) {
+				m_freem(m_new);
+				printf("sf%d: no memory for tx list",
+				    sc->sf_unit);
+				return(1);
+			}
+		}
+		m_copydata(m_head, 0, m_head->m_pkthdr.len,
+		    mtod(m_new, caddr_t));
+		m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
+		m_freem(m_head);
+		m_head = m_new;
+		f = &c->sf_frags[0];
+		f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len;
+		f->sf_addr = vtophys(mtod(m_head, caddr_t));
+		frag = 1;
+	}
+
+	c->sf_mbuf = m_head;
+	c->sf_id = SF_TX_BUFDESC_ID;
+	c->sf_fragcnt = frag;
+	c->sf_intr = 1;
+	c->sf_caltcp = 0;
+	c->sf_crcen = 1;
+
+	return(0);
+}
+
+static void sf_start(ifp)
+	struct ifnet		*ifp;
+{
+	struct sf_softc		*sc;
+	struct sf_tx_bufdesc_type0 *cur_tx = NULL;
+	struct mbuf		*m_head = NULL;
+	int			i, txprod;
+
+	sc = ifp->if_softc;
+
+	if (ifp->if_flags & IFF_OACTIVE)
+		return;
+
+	if (sc->sf_autoneg) {
+		sc->sf_tx_pend = 1;
+		return;
+	}
+
+	txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
+	i = SF_IDX_HI(txprod) >> 4;
+
+	while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) {
+		IF_DEQUEUE(&ifp->if_snd, m_head);
+		if (m_head == NULL)
+			break;
+
+		cur_tx = &sc->sf_ldata->sf_tx_dlist[i];
+		sf_encap(sc, cur_tx, m_head);
+
+		/*
+		 * If there's a BPF listener, bounce a copy of this frame
+		 * to him.
+		 */
+#if NBPF > 0
+		if (ifp->if_bpf)
+			bpf_mtap(ifp, m_head);
+#endif
+		SF_INC(i, SF_TX_DLIST_CNT);
+		sc->sf_tx_cnt++;
+		if (sc->sf_tx_cnt == (SF_TX_DLIST_CNT - 2))
+			break;
+	}
+
+	if (cur_tx == NULL)
+		return;
+
+	/* Transmit */
+	csr_write_4(sc, SF_TXDQ_PRODIDX,
+	    (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) |
+	    ((i << 20) & 0xFFFF0000));
+
+	ifp->if_timer = 5;
+
+	return;
+}
+
+static void sf_stop(sc)
+	struct sf_softc		*sc;
+{
+	int			i;
+
+	untimeout(sf_stats_update, sc, sc->sf_stat_ch);
+
+	csr_write_4(sc, SF_GEN_ETH_CTL, 0);
+	csr_write_4(sc, SF_CQ_CONSIDX, 0);
+	csr_write_4(sc, SF_CQ_PRODIDX, 0);
+	csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0);
+	csr_write_4(sc, SF_RXDQ_CTL_1, 0);
+	csr_write_4(sc, SF_RXDQ_PTR_Q1, 0);
+	csr_write_4(sc, SF_TXCQ_CTL, 0);
+	csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0);
+	csr_write_4(sc, SF_TXDQ_CTL, 0);
+	sf_reset(sc);
+
+	for (i = 0; i < SF_RX_DLIST_CNT; i++) {
+		if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) {
+			m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf);
+			sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL;
+		}
+	}
+
+	for (i = 0; i < SF_TX_DLIST_CNT; i++) {
+		if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
+			m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf);
+			sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL;
+		}
+	}
+
+	return;
+}
+
+/*
+ * Note: it is important that this function not be interrupted. We
+ * use a two-stage register access scheme: if we are interrupted in
+ * between setting the indirect address register and reading from the
+ * indirect data register, the contents of the address register could
+ * be changed out from under us.
+ */     
+static void sf_stats_update(xsc)
+	void			*xsc;
+{
+	struct sf_softc		*sc;
+	struct ifnet		*ifp;
+	struct sf_stats		stats;
+	u_int32_t		*ptr;
+	int			i, s;
+
+	s = splimp();
+
+	sc = xsc;
+	ifp = &sc->arpcom.ac_if;
+
+	ptr = (u_int32_t *)&stats;
+	for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
+		ptr[i] = csr_read_4(sc, SF_STATS_BASE +
+		    (i + sizeof(u_int32_t)));
+
+	for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
+		csr_write_4(sc, SF_STATS_BASE +
+		    (i + sizeof(u_int32_t)), 0);
+
+	ifp->if_collisions += stats.sf_tx_single_colls +
+	    stats.sf_tx_multi_colls + stats.sf_tx_excess_colls;
+
+	sc->sf_stat_ch = timeout(sf_stats_update, sc, hz);
+
+	splx(s);
+
+	return;
+}
+
+static void sf_watchdog(ifp)
+	struct ifnet		*ifp;
+{
+	struct sf_softc		*sc;
+
+	sc = ifp->if_softc;
+
+	if (sc->sf_autoneg) {
+		sf_autoneg_mii(sc, SF_FLAG_DELAYTIMEO, 1);
+		if (!(ifp->if_flags & IFF_UP))
+			sf_stop(sc);
+		return;
+	}
+
+	ifp->if_oerrors++;
+	printf("sf%d: watchdog timeout\n", sc->sf_unit);
+
+	if (sc->sf_pinfo != NULL) {
+		if (!(sf_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
+			printf("sf%d: no carrier - transceiver "
+			    "cable problem?\n", sc->sf_unit);
+	}
+
+	sf_stop(sc);
+	sf_reset(sc);
+	sf_init(sc);
+
+	if (ifp->if_snd.ifq_head != NULL)
+		sf_start(ifp);
+
+	return;
+}
+
+static void sf_shutdown(dev)
+	device_t		dev;
+{
+	struct sf_softc		*sc;
+
+	sc = device_get_softc(dev);
+
+	sf_stop(sc);
+
+	return;
+}
diff --git a/sys/pci/if_sfreg.h b/sys/pci/if_sfreg.h
new file mode 100644
index 0000000..4ead870
--- /dev/null
+++ b/sys/pci/if_sfreg.h
@@ -0,0 +1,1171 @@
+/*
+ * Copyright (c) 1997, 1998, 1999
+ *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *	$Id: if_sfreg.h,v 1.4 1999/07/21 03:44:25 wpaul Exp $
+ */
+
+/*
+ * Registers for the Adaptec AIC-6915 Starfire. The Starfire has a 512K
+ * register space. These registers can be accessed in the following way:
+ * - PCI config registers are always accessible through PCI config space
+ * - Full 512K space mapped into memory using PCI memory mapped access
+ * - 256-byte I/O space mapped through PCI I/O access
+ * - Full 512K space mapped through indirect I/O using PCI I/O access
+ * It's possible to use either memory mapped mode or I/O mode to access
+ * the registers, but memory mapped is usually the easiest. All registers
+ * are 32 bits wide and must be accessed using 32-bit operations.
+ */
+
+/*
+ * Adaptec PCI vendor ID.
+ */
+#define AD_VENDORID		0x9004
+
+/*
+ * AIC-6915 PCI device ID.
+ */
+#define AD_DEVICEID_STARFIRE	0x6915
+
+/*
+ * AIC-6915 subsystem IDs. Adaptec uses the subsystem ID to identify
+ * the exact kind of NIC on which the ASIC is mounted. Currently there
+ * are six different variations. Note: the Adaptec manual lists code 0x28
+ * for two different NICs: the 62044 and the 69011/TX. This is a typo:
+ * the code for the 62044 is really 0x18.
+ */
+#define AD_SUBSYSID_62011_REV0	0x0008	/* single port 10/100baseTX 64-bit */
+#define AD_SUBSYSID_62011_REV1	0x0009	/* single port 10/100baseTX 64-bit */
+#define AD_SUBSYSID_62022	0x0010	/* dual port 10/100baseTX 64-bit */
+#define AD_SUBSYSID_62044	0x0018	/* quad port 10/100baseTX 64-bit */
+#define AD_SUBSYSID_62020	0x0020	/* single port 10/100baseFX 64-bit */
+#define AD_SUBSYSID_69011	0x0028	/* single port 10/100baseTX 32-bit */
+
+/*
+ * Starfire internal register space map. The entire register space
+ * is available using PCI memory mapped mode. The SF_RMAP_INTREG
+ * space is available using PCI I/O mode. The entire space can be
+ * accessed using indirect I/O using the indirect I/O addr and
+ * indirect I/O data registers located within the SF_RMAP_INTREG space.
+ */
+#define SF_RMAP_ROMADDR_BASE	0x00000	/* Expansion ROM space */
+#define SF_RMAP_ROMADDR_MAX	0x3FFFF
+
+#define SF_RMAP_EXGPIO_BASE	0x40000 /* External general purpose regs */
+#define SF_RMAP_EXGPIO_MAX	0x3FFFF
+
+#define SF_RMAP_INTREG_BASE	0x50000 /* Internal functional registers */
+#define SF_RMAP_INTREG_MAX	0x500FF
+#define SF_RMAP_GENREG_BASE	0x50100 /* General purpose registers */
+#define SF_RMAP_GENREG_MAX	0x5FFFF
+
+#define SF_RMAP_FIFO_BASE	0x60000
+#define SF_RMAP_FIFO_MAX	0x6FFFF
+
+#define SF_RMAP_STS_BASE	0x70000
+#define SF_RMAP_STS_MAX		0x70083
+
+#define SF_RMAP_RSVD_BASE	0x70084
+#define SF_RMAP_RSVD_MAX	0x7FFFF
+
+/*
+ * PCI config header registers, 0x0000 to 0x003F
+ */
+#define SF_PCI_VENDOR_ID	0x0000
+#define SF_PCI_DEVICE_ID	0x0002
+#define SF_PCI_COMMAND		0x0004
+#define SF_PCI_STATUS		0x0006
+#define SF_PCI_REVID		0x0008
+#define SF_PCI_CLASSCODE	0x0009
+#define SF_PCI_CACHELEN		0x000C
+#define SF_PCI_LATENCY_TIMER	0x000D
+#define SF_PCI_HEADER_TYPE	0x000E
+#define SF_PCI_LOMEM		0x0010
+#define SF_PCI_LOIO		0x0014
+#define SF_PCI_SUBVEN_ID	0x002C
+#define SF_PCI_SYBSYS_ID	0x002E
+#define SF_PCI_BIOSROM		0x0030
+#define SF_PCI_INTLINE		0x003C
+#define SF_PCI_INTPIN		0x003D
+#define SF_PCI_MINGNT		0x003E
+#define SF_PCI_MINLAT		0x003F
+
+/*
+ * PCI registers, 0x0040 to 0x006F
+ */
+#define SF_PCI_DEVCFG		0x0040
+#define SF_BACCTL		0x0044
+#define SF_PCI_MON1		0x0048
+#define SF_PCI_MON2		0x004C
+#define SF_PCI_CAPID		0x0050 /* 8 bits */
+#define SF_PCI_NEXTPTR		0x0051 /* 8 bits */
+#define SF_PCI_PWRMGMTCAP	0x0052 /* 16 bits */
+#define SF_PCI_PWRMGMTCTRL	0x0054 /* 16 bits */
+#define SF_PCI_PME_EVENT	0x0058
+#define SF_PCI_EECTL		0x0060
+#define SF_PCI_COMPLIANCE	0x0064
+#define SF_INDIRECTIO_ADDR	0x0068
+#define SF_INDIRECTIO_DATA	0x006C
+
+#define SF_PCIDEVCFG_RESET	0x00000001
+#define SF_PCIDEVCFG_FORCE64	0x00000002
+#define SF_PCIDEVCFG_SYSTEM64	0x00000004
+#define SF_PCIDEVCFG_RSVD0	0x00000008
+#define SF_PCIDEVCFG_INCR_INB	0x00000010
+#define SF_PCIDEVCFG_ABTONPERR	0x00000020
+#define SF_PCIDEVCFG_STPONPERR	0x00000040
+#define SF_PCIDEVCFG_MR_ENB	0x00000080
+#define SF_PCIDEVCFG_FIFOTHR	0x00000F00
+#define SF_PCIDEVCFG_STPONCA	0x00001000
+#define SF_PCIDEVCFG_PCIMEN	0x00002000	/* enable PCI bus master */
+#define SF_PCIDEVCFG_LATSTP	0x00004000
+#define SF_PCIDEVCFG_BYTE_ENB	0x00008000
+#define SF_PCIDEVCFG_EECSWIDTH	0x00070000
+#define SF_PCIDEVCFG_STPMWCA	0x00080000
+#define SF_PCIDEVCFG_REGCSWIDTH	0x00700000
+#define SF_PCIDEVCFG_INTR_ENB	0x00800000
+#define SF_PCIDEVCFG_DPR_ENB	0x01000000
+#define SF_PCIDEVCFG_RSVD1	0x02000000
+#define SF_PCIDEVCFG_RSVD2	0x04000000
+#define SF_PCIDEVCFG_STA_ENB	0x08000000
+#define SF_PCIDEVCFG_RTA_ENB	0x10000000
+#define SF_PCIDEVCFG_RMA_ENB	0x20000000
+#define SF_PCIDEVCFG_SSE_ENB	0x40000000
+#define SF_PCIDEVCFG_DPE_ENB	0x80000000
+
+#define SF_BACCTL_BACDMA_ENB	0x00000001
+#define SF_BACCTL_PREFER_RXDMA	0x00000002
+#define SF_BACCTL_PREFER_TXDMA	0x00000004
+#define SF_BACCTL_SINGLE_DMA	0x00000008
+#define SF_BACCTL_SWAPMODE_DATA	0x00000030
+#define SF_BACCTL_SWAPMODE_DESC	0x000000C0
+
+#define SF_SWAPMODE_LE		0x00000000
+#define SF_SWAPMODE_BE		0x00000010
+
+#define SF_PSTATE_MASK		0x0003
+#define SF_PSTATE_D0		0x0000
+#define SF_PSTATE_D1		0x0001
+#define SF_PSTATE_D2		0x0002
+#define SF_PSTATE_D3		0x0003
+#define SF_PME_EN		0x0010
+#define SF_PME_STATUS		0x8000
+
+
+/*
+ * Ethernet registers 0x0070 to 0x00FF
+ */
+#define SF_GEN_ETH_CTL		0x0070
+#define SF_TIMER_CTL		0x0074
+#define SF_CURTIME		0x0078
+#define SF_ISR			0x0080
+#define SF_ISR_SHADOW		0x0084
+#define SF_IMR			0x0088
+#define SF_GPIO			0x008C
+#define SF_TXDQ_CTL		0x0090
+#define SF_TXDQ_ADDR_HIPRIO	0x0094
+#define SF_TXDQ_ADDR_LOPRIO	0x0098
+#define SF_TXDQ_ADDR_HIADDR	0x009C
+#define SF_TXDQ_PRODIDX		0x00A0
+#define SF_TXDQ_CONSIDX		0x00A4
+#define SF_TXDMA_STS1		0x00A8
+#define SF_TXDMA_STS2		0x00AC
+#define SF_TX_FRAMCTL		0x00B0
+#define SF_TXCQ_ADDR_HI		0x00B4
+#define SF_TXCQ_CTL		0x00B8
+#define SF_RXCQ_CTL_1		0x00BC
+#define SF_RXCQ_CTL_2		0x00C0
+#define SF_CQ_CONSIDX		0x00C4
+#define SF_CQ_PRODIDX		0x00C8
+#define SF_CQ_RXQ2		0x00CC
+#define SF_RXDMA_CTL		0x00D0
+#define SF_RXDQ_CTL_1		0x00D4
+#define SF_RXDQ_CTL_2		0x00D8
+#define SF_RXDQ_ADDR_HIADDR	0x00DC
+#define SF_RXDQ_ADDR_Q1		0x00E0
+#define SF_RXDQ_ADDR_Q2		0x00E4
+#define SF_RXDQ_PTR_Q1		0x00E8
+#define SF_RXDQ_PTR_Q2		0x00EC
+#define SF_RXDMA_STS		0x00F0
+#define SF_RXFILT		0x00F4
+#define SF_RX_FRAMETEST_OUT	0x00F8
+
+/* Ethernet control register */
+#define SF_ETHCTL_RX_ENB	0x00000001
+#define SF_ETHCTL_TX_ENB	0x00000002
+#define SF_ETHCTL_RXDMA_ENB	0x00000004
+#define SF_ETHCTL_TXDMA_ENB	0x00000008
+#define SF_ETHCTL_RXGFP_ENB	0x00000010
+#define SF_ETHCTL_TXGFP_ENB	0x00000020
+#define SF_ETHCTL_SOFTINTR	0x00000800
+
+/* Timer control register */
+#define SF_TIMER_IMASK_INTERVAL	0x0000001F
+#define SF_TIMER_IMASK_MODE	0x00000060
+#define SF_TIMER_SMALLFRAME_BYP	0x00000100
+#define SF_TIMER_SMALLRX_FRAME	0x00000600
+#define SF_TIMER_TIMES_TEN	0x00000800
+#define SF_TIMER_RXHIPRIO_BYP	0x00001000
+#define SF_TIMER_TX_DMADONE_DLY	0x00002000
+#define SF_TIMER_TX_QDONE_DLY	0x00004000
+#define SF_TIMER_TX_FRDONE_DLY	0x00008000
+#define SF_TIMER_GENTIMER	0x00FF0000
+#define SF_TIMER_ONESHOT	0x01000000
+#define SF_TIMER_GENTIMER_RES	0x02000000
+#define SF_TIMER_TIMEST_RES	0x04000000
+#define SF_TIMER_RXQ2DONE_DLY	0x10000000
+#define SF_TIMER_EARLYRX2_DLY	0x20000000
+#define SF_TIMER_RXQ1DONE_DLY	0x40000000
+#define SF_TIMER_EARLYRX1_DLY	0x80000000
+
+/* Interrupt status register */
+#define SF_ISR_PCIINT_ASSERTED	0x00000001
+#define SF_ISR_GFP_TX		0x00000002
+#define SF_ISR_GFP_RX		0x00000004
+#define SF_ISR_TX_BADID_HIPRIO	0x00000008
+#define SF_ISR_TX_BADID_LOPRIO	0x00000010
+#define SF_ISR_NO_TX_CSUM	0x00000020
+#define SF_ISR_RXDQ2_NOBUFS	0x00000040
+#define SF_ISR_RXGFP_NORESP	0x00000080
+#define SF_ISR_RXDQ1_DMADONE	0x00000100
+#define SF_ISR_RXDQ2_DMADONE	0x00000200
+#define SF_ISR_RXDQ1_EARLY	0x00000400
+#define SF_ISR_RXDQ2_EARLY	0x00000800
+#define SF_ISR_TX_QUEUEDONE	0x00001000
+#define SF_ISR_TX_DMADONE	0x00002000
+#define SF_ISR_TX_TXDONE	0x00004000
+#define SF_ISR_NORMALINTR	0x00008000
+#define SF_ISR_RXDQ1_NOBUFS	0x00010000
+#define SF_ISR_RXCQ2_NOBUFS	0x00020000
+#define SF_ISR_TX_LOFIFO	0x00040000
+#define SF_ISR_DMAERR		0x00080000
+#define SF_ISR_PCIINT		0x00100000
+#define SF_ISR_TXCQ_NOBUFS	0x00200000
+#define SF_ISR_RXCQ1_NOBUFS	0x00400000
+#define SF_ISR_SOFTINTR		0x00800000
+#define SF_ISR_GENTIMER		0x01000000
+#define SF_ISR_ABNORMALINTR	0x02000000
+#define SF_ISR_RSVD0		0x04000000
+#define SF_ISR_STATSOFLOW	0x08000000
+#define SF_ISR_GPIO		0xF0000000
+
+/*
+ * Shadow interrupt status register. Unlike the normal IRQ register,
+ * reading bits here does not automatically cause them to reset.
+ */
+#define SF_SISR_PCIINT_ASSERTED	0x00000001
+#define SF_SISR_GFP_TX		0x00000002
+#define SF_SISR_GFP_RX		0x00000004
+#define SF_SISR_TX_BADID_HIPRIO	0x00000008
+#define SF_SISR_TX_BADID_LOPRIO	0x00000010
+#define SF_SISR_NO_TX_CSUM	0x00000020
+#define SF_SISR_RXDQ2_NOBUFS	0x00000040
+#define SF_SISR_RXGFP_NORESP	0x00000080
+#define SF_SISR_RXDQ1_DMADONE	0x00000100
+#define SF_SISR_RXDQ2_DMADONE	0x00000200
+#define SF_SISR_RXDQ1_EARLY	0x00000400
+#define SF_SISR_RXDQ2_EARLY	0x00000800
+#define SF_SISR_TX_QUEUEDONE	0x00001000
+#define SF_SISR_TX_DMADONE	0x00002000
+#define SF_SISR_TX_TXDONE	0x00004000
+#define SF_SISR_NORMALINTR	0x00008000
+#define SF_SISR_RXDQ1_NOBUFS	0x00010000
+#define SF_SISR_RXCQ2_NOBUFS	0x00020000
+#define SF_SISR_TX_LOFIFO	0x00040000
+#define SF_SISR_DMAERR		0x00080000
+#define SF_SISR_PCIINT		0x00100000
+#define SF_SISR_TXCQ_NOBUFS	0x00200000
+#define SF_SISR_RXCQ1_NOBUFS	0x00400000
+#define SF_SISR_SOFTINTR	0x00800000
+#define SF_SISR_GENTIMER	0x01000000
+#define SF_SISR_ABNORMALINTR	0x02000000
+#define SF_SISR_RSVD0		0x04000000
+#define SF_SISR_STATSOFLOW	0x08000000
+#define SF_SISR_GPIO		0xF0000000
+
+/* Interrupt mask register */
+#define SF_IMR_PCIINT_ASSERTED	0x00000001
+#define SF_IMR_GFP_TX		0x00000002
+#define SF_IMR_GFP_RX		0x00000004
+#define SF_IMR_TX_BADID_HIPRIO	0x00000008
+#define SF_IMR_TX_BADID_LOPRIO	0x00000010
+#define SF_IMR_NO_TX_CSUM	0x00000020
+#define SF_IMR_RXDQ2_NOBUFS	0x00000040
+#define SF_IMR_RXGFP_NORESP	0x00000080
+#define SF_IMR_RXDQ1_DMADONE	0x00000100
+#define SF_IMR_RXDQ2_DMADONE	0x00000200
+#define SF_IMR_RXDQ1_EARLY	0x00000400
+#define SF_IMR_RXDQ2_EARLY	0x00000800
+#define SF_IMR_TX_QUEUEDONE	0x00001000
+#define SF_IMR_TX_DMADONE	0x00002000
+#define SF_IMR_TX_TXDONE	0x00004000
+#define SF_IMR_NORMALINTR	0x00008000
+#define SF_IMR_RXDQ1_NOBUFS	0x00010000
+#define SF_IMR_RXCQ2_NOBUFS	0x00020000
+#define SF_IMR_TX_LOFIFO	0x00040000
+#define SF_IMR_DMAERR		0x00080000
+#define SF_IMR_PCIINT		0x00100000
+#define SF_IMR_TXCQ_NOBUFS	0x00200000
+#define SF_IMR_RXCQ1_NOBUFS	0x00400000
+#define SF_IMR_SOFTINTR		0x00800000
+#define SF_IMR_GENTIMER		0x01000000
+#define SF_IMR_ABNORMALINTR	0x02000000
+#define SF_IMR_RSVD0		0x04000000
+#define SF_IMR_STATSOFLOW	0x08000000
+#define SF_IMR_GPIO		0xF0000000
+
+#define SF_INTRS	\
+	(SF_IMR_RXDQ2_NOBUFS|SF_IMR_RXDQ1_DMADONE|SF_IMR_RXDQ2_DMADONE|	\
+	 SF_IMR_TX_TXDONE|SF_IMR_RXDQ1_NOBUFS|SF_IMR_RXDQ2_DMADONE|	\
+	 SF_IMR_NORMALINTR|SF_IMR_ABNORMALINTR|SF_IMR_TXCQ_NOBUFS|	\
+	 SF_IMR_RXCQ1_NOBUFS|SF_IMR_RXCQ2_NOBUFS|SF_IMR_STATSOFLOW)
+
+/* TX descriptor queue control registers */
+#define SF_TXDQCTL_DESCTYPE	0x00000007
+#define SF_TXDQCTL_NODMACMP	0x00000008
+#define SF_TXDQCTL_MINSPACE	0x00000070
+#define SF_TXDQCTL_64BITADDR	0x00000080
+#define SF_TXDQCTL_BURSTLEN	0x00003F00
+#define SF_TXDQCTL_SKIPLEN	0x001F0000
+#define SF_TXDQCTL_HIPRIOTHRESH	0xFF000000
+
+#define SF_TXBUFDESC_TYPE0	0x00000000
+#define SF_TXBUFDESC_TYPE1	0x00000001
+#define SF_TXBUFDESC_TYPE2	0x00000002
+#define SF_TXBUFDESC_TYPE3	0x00000003
+#define SF_TXBUFDESC_TYPE4	0x00000004
+
+#define SF_TXMINSPACE_UNLIMIT	0x00000000
+#define SF_TXMINSPACE_32BYTES	0x00000010
+#define SF_TXMINSPACE_64BYTES	0x00000020
+#define SF_TXMINSPACE_128BYTES	0x00000030
+#define SF_TXMINSPACE_256BYTES	0x00000040
+
+#define SF_TXSKIPLEN_0BYTES	0x00000000
+#define SF_TXSKIPLEN_8BYTES	0x00010000
+#define SF_TXSKIPLEN_16BYTES	0x00020000
+#define SF_TXSKIPLEN_24BYTES	0x00030000
+#define SF_TXSKIPLEN_32BYTES	0x00040000
+
+/* TX frame control register */
+#define SF_TXFRMCTL_TXTHRESH	0x000000FF
+#define SF_TXFRMCTL_CPLAFTERTX	0x00000100
+#define SF_TXFRMCRL_DEBUG	0x0000FE00
+#define SF_TXFRMCTL_STATUS	0x01FF0000
+#define SF_TXFRMCTL_MAC_TXIF	0xFE000000
+
+/* TX completion queue control register */
+#define SF_TXCQ_THRESH		0x0000000F
+#define SF_TXCQ_COMMON		0x00000010
+#define SF_TXCQ_SIZE		0x00000020
+#define SF_TXCQ_WRITEENB	0x00000040
+#define SF_TXCQ_USE_64BIT	0x00000080
+#define SF_TXCQ_ADDR		0xFFFFFF00
+
+/* RX completion queue control register */
+#define SF_RXCQ_THRESH		0x0000000F
+#define SF_RXCQ_TYPE		0x00000030
+#define SF_RXCQ_WRITEENB	0x00000040
+#define SF_RXCQ_USE_64BIT	0x00000080
+#define SF_RXCQ_ADDR		0xFFFFFF00
+
+#define SF_RXCQTYPE_0		0x00000000
+#define SF_RXCQTYPE_1		0x00000010
+#define SF_RXCQTYPE_2		0x00000020
+#define SF_RXCQTYPE_3		0x00000030
+
+/* TX descriptor queue producer index register */
+#define SF_TXDQ_PRODIDX_LOPRIO	0x000007FF
+#define SF_TXDQ_PRODIDX_HIPRIO	0x07FF0000
+
+/* TX descriptor queue consumer index register */
+#define SF_TXDQ_CONSIDX_LOPRIO	0x000007FF
+#define SF_TXDQ_CONSIDX_HIPRIO	0x07FF0000
+
+/* Completion queue consumer index register */
+#define SF_CQ_CONSIDX_RXQ1	0x000003FF
+#define SF_CQ_CONSIDX_RXTHRMODE	0x00008000
+#define SF_CQ_CONSIDX_TXQ	0x03FF0000
+#define SF_CQ_CONSIDX_TXTHRMODE	0x80000000
+
+/* Completion queue producer index register */
+#define SF_CQ_PRODIDX_RXQ1	0x000003FF
+#define SF_CQ_PRODIDX_TXQ	0x03FF0000
+
+/* RX completion queue 2 consumer/producer index register */
+#define SF_CQ_RXQ2_CONSIDX	0x000003FF
+#define SF_CQ_RXQ2_RXTHRMODE	0x00008000
+#define SF_CQ_RXQ2_PRODIDX	0x03FF0000
+
+#define SF_CQ_RXTHRMODE_INT_ON	0x00008000
+#define SF_CQ_RXTHRMODE_INT_OFF	0x00000000
+#define SF_CQ_TXTHRMODE_INT_ON	0x80000000
+#define SF_CQ_TXTHRMODE_INT_OFF	0x00000000
+
+#define SF_IDX_LO(x)		((x) & 0x000007FF)
+#define SF_IDX_HI(x)		(((x) >> 16) & 0x000007FF)
+
+/* RX DMA control register */
+#define SF_RXDMA_BURSTSIZE	0x0000007F
+#define SF_RXDMA_FPTESTMODE	0x00000080
+#define SF_RXDMA_HIPRIOTHRESH	0x00000F00
+#define SF_RXDMA_RXEARLYTHRESH	0x0001F000
+#define SF_RXDMA_DMACRC		0x00040000
+#define SF_RXDMA_USEBKUPQUEUE	0x00080000
+#define SF_RXDMA_QUEUEMODE	0x00700000
+#define SF_RXDMA_RXCQ2_ON	0x00800000
+#define SF_RXDMA_CSUMMODE	0x03000000
+#define SF_RXDMA_DMAPAUSEPKTS	0x04000000
+#define SF_RXDMA_DMACTLPKTS	0x08000000
+#define SF_RXDMA_DMACRXERRPKTS	0x10000000
+#define SF_RXDMA_DMABADPKTS	0x20000000
+#define SF_RXDMA_DMARUNTS	0x40000000
+#define SF_RXDMA_REPORTBADPKTS	0x80000000
+
+#define SF_RXDQMODE_Q1ONLY	0x00100000
+#define SF_RXDQMODE_Q2_ON_FP	0x00200000
+#define SF_RXDQMODE_Q2_ON_SHORT	0x00300000
+#define SF_RXDQMODE_Q2_ON_PRIO	0x00400000
+#define SF_RXDQMODE_SPLITHDR	0x00500000
+
+#define SF_RXCSUMMODE_IGNORE	0x00000000
+#define SF_RXCSUMMODE_REJECT_BAD_TCP	0x01000000
+#define SF_RXCSUMMODE_REJECT_BAD_TCPUDP	0x02000000
+#define SF_RXCSUMMODE_RSVD	0x03000000
+
+/* RX descriptor queue control registers */
+#define SF_RXDQCTL_MINDESCTHR	0x0000007F
+#define SF_RXDQCTL_Q1_WE	0x00000080
+#define SF_RXDQCTL_DESCSPACE	0x00000700
+#define SF_RXDQCTL_64BITDADDR	0x00000800
+#define SF_RXDQCTL_64BITBADDR	0x00001000
+#define SF_RXDQCTL_VARIABLE	0x00002000
+#define SF_RXDQCTL_ENTRIES	0x00004000
+#define SF_RXDQCTL_PREFETCH	0x00008000
+#define SF_RXDQCTL_BUFLEN	0xFFFF0000
+
+#define SF_DESCSPACE_4BYTES	0x00000000
+#define SF_DESCSPACE_8BYTES	0x00000100
+#define SF_DESCSPACE_16BYTES	0x00000200
+#define SF_DESCSPACE_32BYTES	0x00000300
+#define SF_DESCSPACE_64BYTES	0x00000400
+#define SF_DESCSPACE_128_BYTES	0x00000500
+
+/* RX buffer consumer/producer index registers */
+#define SF_RXDQ_PRODIDX		0x000007FF
+#define SF_RXDQ_CONSIDX		0x07FF0000
+
+/* RX filter control register */
+#define SF_RXFILT_PROMISC	0x00000001
+#define SF_RXFILT_ALLMULTI	0x00000002
+#define SF_RXFILT_BROAD		0x00000004
+#define SF_RXFILT_HASHPRIO	0x00000008
+#define SF_RXFILT_HASHMODE	0x00000030
+#define SF_RXFILT_PERFMODE	0x000000C0
+#define SF_RXFILT_VLANMODE	0x00000300
+#define SF_RXFILT_WAKEMODE	0x00000C00
+#define SF_RXFILT_MULTI_NOBROAD	0x00001000
+#define SF_RXFILT_MIN_VLANPRIO	0x0000E000
+#define SF_RXFILT_PEFECTPRIO	0xFFFF0000
+
+/* Hash filtering mode */
+#define SF_HASHMODE_OFF		0x00000000
+#define SF_HASHMODE_WITHVLAN	0x00000010
+#define SF_HASHMODE_ANYVLAN	0x00000020
+#define SF_HASHMODE_ANY		0x00000030
+
+/* Perfect filtering mode */
+#define SF_PERFMODE_OFF		0x00000000
+#define SF_PERFMODE_NORMAL	0x00000040
+#define SF_PERFMODE_INVERSE	0x00000080
+#define SF_PERFMODE_VLAN	0x000000C0
+
+/* VLAN mode */
+#define SF_VLANMODE_OFF		0x00000000
+#define SF_VLANMODE_NOSTRIP	0x00000100
+#define SF_VLANMODE_STRIP	0x00000200
+#define SF_VLANMODE_RSVD	0x00000300
+
+/* Wakeup mode */
+#define SF_WAKEMODE_OFF		0x00000000
+#define SF_WAKEMODE_FILTER	0x00000400
+#define SF_WAKEMODE_FP		0x00000800
+#define SF_WAKEMODE_HIPRIO	0x00000C00
+
+/*
+ * Extra PCI registers 0x0100 to 0x0FFF
+ */
+#define SF_PCI_TARGSTAT		0x0100
+#define SF_PCI_MASTSTAT1	0x0104
+#define SF_PCI_MASTSTAT2	0x0108
+#define SF_PCI_DMAHOSTADDR_LO	0x010C
+#define SF_BAC_DMADIAG0		0x0110
+#define SF_BAC_DMADIAG1		0x0114
+#define SF_BAC_DMADIAG2		0x0118
+#define SF_BAC_DMADIAG3		0x011C
+#define SF_PAR0			0x0120
+#define SF_PAR1			0x0124
+#define SF_PCICB_FUNCEVENT	0x0130
+#define SF_PCICB_FUNCEVENT_MASK	0x0134
+#define SF_PCICB_FUNCSTATE	0x0138
+#define SF_PCICB_FUNCFORCE	0x013C
+
+/*
+ * Serial EEPROM registers 0x1000 to 0x1FFF
+ * Presumeably the EEPROM is mapped into this 8K window.
+ */
+#define SF_EEADDR_BASE		0x1000
+#define SF_EEADDR_MAX		0x1FFF
+
+#define SF_EE_NODEADDR		14
+
+/*
+ * MII registers registers 0x2000 to 0x3FFF
+ * There are 32 sets of 32 registers, one set for each possible
+ * PHY address. Each 32 bit register is split into a 16-bit data
+ * port and a couple of status bits.
+ */
+
+#define SF_MIIADDR_BASE		0x2000
+#define SF_MIIADDR_MAX		0x3FFF
+#define SF_MII_BLOCKS		32
+
+#define SF_MII_DATAVALID	0x80000000
+#define SF_MII_BUSY		0x40000000
+#define SF_MII_DATAPORT		0x0000FFFF
+
+#define SF_PHY_REG(phy, reg)						\
+	(SF_MIIADDR_BASE + (phy * SF_MII_BLOCKS * sizeof(u_int32_t)) +	\
+	(reg * sizeof(u_int32_t)))
+
+/*
+ * Ethernet extra registers 0x4000 to 0x4FFF
+ */
+#define SF_TESTMODE		0x4000
+#define SF_RX_FRAMEPROC_CTL	0x4004
+#define SF_TX_FRAMEPROC_CTL	0x4008
+
+/*
+ * MAC registers 0x5000 to 0x5FFF
+ */
+#define SF_MACCFG_1		0x5000
+#define SF_MACCFG_2		0x5004
+#define SF_BKTOBKIPG		0x5008
+#define SF_NONBKTOBKIPG		0x500C
+#define SF_COLRETRY		0x5010
+#define SF_MAXLEN		0x5014
+#define SF_TXNIBBLECNT		0x5018
+#define SF_TXBYTECNT		0x501C
+#define SF_RETXCNT		0x5020
+#define SF_RANDNUM		0x5024
+#define SF_RANDNUM_MASK		0x5028
+#define SF_TOTALTXCNT		0x5034
+#define SF_RXBYTECNT		0x5040
+#define SF_TXPAUSETIMER		0x5060
+#define SF_VLANTYPE		0x5064
+#define SF_MIISTATUS		0x5070
+
+#define SF_MACCFG1_HUGEFRAMES	0x00000001
+#define SF_MACCFG1_FULLDUPLEX	0x00000002
+#define SF_MACCFG1_AUTOPAD	0x00000004
+#define SF_MACCFG1_HDJAM	0x00000008
+#define SF_MACCFG1_DELAYCRC	0x00000010
+#define SF_MACCFG1_NOBACKOFF	0x00000020
+#define SF_MACCFG1_LENGTHCHECK	0x00000040
+#define SF_MACCFG1_PUREPREAMBLE	0x00000080
+#define SF_MACCFG1_PASSALLRX	0x00000100
+#define SF_MACCFG1_PREAM_DETCNT	0x00000200
+#define SF_MACCFG1_RX_FLOWENB	0x00000400
+#define SF_MACCFG1_TX_FLOWENB	0x00000800
+#define SF_MACCFG1_TESTMODE	0x00003000
+#define SF_MACCFG1_MIILOOPBK	0x00004000
+#define SF_MACCFG1_SOFTRESET	0x00008000
+
+/*
+ * RX filter registers 0x6000 to 0x6FFF
+ */
+#define SF_RXFILT_PERFECT_BASE	0x6000
+#define SF_RXFILT_PERFECT_MAX	0x60FF
+#define SF_RXFILT_PERFECT_SKIP	0x0010
+#define SF_RXFILT_PERFECT_CNT	0x0010
+
+#define SF_RXFILT_HASH_BASE	0x6100
+#define SF_RXFILT_HASH_MAX	0x62FF
+#define SF_RXFILT_HASH_SKIP	0x0010
+#define SF_RXFILT_HASH_CNT	0x001F
+#define SF_RXFILT_HASH_ADDROFF	0x0000
+#define SF_RXFILT_HASH_PRIOOFF	0x0004
+#define SF_RXFILT_HASH_VLANOFF	0x0008
+
+/*
+ * Statistics registers 0x7000 to 0x7FFF
+ */
+#define SF_STATS_BASE		0x7000
+#define SF_STATS_END		0x7FFF
+
+/*
+ * TX frame processor instruction space 0x8000 to 0x9FFF
+ */
+
+/*
+ * RX frame processor instruction space 0xA000 to 0xBFFF
+ */
+
+/*
+ * Ethernet FIFO access space 0xC000 to 0xDFFF
+ */
+
+/*
+ * Reserved 0xE000 to 0xFFFF
+ */
+
+/*
+ * Descriptor data structures.
+ */
+
+
+/* Receive descriptor formats. */
+#define SF_RX_MINSPACING	8
+#define SF_RX_DLIST_CNT		256
+#define SF_RX_CLIST_CNT		1024
+#define SF_RX_HOSTADDR(x)	(((x) >> 2) & 0x3FFFFFFF)
+
+/*
+ * RX buffer descriptor type 0, 32-bit addressing. Note that we
+ * program the RX buffer queue control register(s) to allow a
+ * descriptor spacing of 16 bytes, which leaves room after each
+ * descriptor to store a pointer to the mbuf for each buffer.
+ */
+struct sf_rx_bufdesc_type0 {
+	u_int32_t		sf_valid:1,
+				sf_end:1,
+				sf_addrlo:30;
+	u_int32_t		sf_pad0;
+#ifdef __i386__
+	u_int32_t		sf_pad1;
+#endif
+	struct mbuf		*sf_mbuf;
+};
+
+/*
+ * RX buffer descriptor type 0, 64-bit addressing.
+ */
+struct sf_rx_bufdesc_type1 {
+	u_int32_t		sf_valid:1,
+				sf_end:1,
+				sf_addrlo:30;
+	u_int32_t		sf_addrhi;
+#ifdef __i386__
+	u_int32_t		sf_pad;
+#endif
+	struct mbuf		*sf_mbuf;
+};
+
+/*
+ * RX completion descriptor, type 0 (short).
+ */
+struct sf_rx_cmpdesc_type0 {
+	u_int32_t		sf_len:16,
+				sf_endidx:11,
+				sf_status1:3,
+				sf_id:2;
+};
+
+/*
+ * RX completion descriptor, type 1 (basic). Includes vlan ID
+ * if this is a vlan-addressed packet, plus extended status.
+ */
+struct sf_rx_cmpdesc_type1 {
+	u_int32_t		sf_len:16,
+				sf_endidx:11,
+				sf_status1:3,
+				sf_id:2;
+	u_int16_t		sf_status2;
+	u_int16_t		sf_vlanid;
+};
+
+/*
+ * RX completion descriptor, type 2 (checksum). Includes partial TCP/IP
+ * checksum instead of vlan tag, plus extended status.
+ */
+struct sf_rx_cmpdesc_type2 {
+	u_int32_t		sf_len:16,
+				sf_endidx:11,
+				sf_status1:3,
+				sf_id:2;
+	u_int16_t		sf_status2;
+	u_int16_t		sf_cksum;
+};
+
+/*
+ * RX completion descriptor type 3 (full). Includes timestamp, partial
+ * TCP/IP checksum, vlan tag plus priority, two extended status fields.
+ */
+struct sf_rx_cmpdesc_type3 {
+	u_int32_t		sf_len:16,
+				sf_endidx:11,
+				sf_status1:3,
+				sf_id:2;
+	u_int32_t		sf_startidx:10,
+				sf_status3:6,
+				sf_status2:16;
+	u_int16_t		sf_cksum;
+	u_int16_t		sf_vlanid_prio;
+	u_int32_t		sf_timestamp;
+};
+
+#define SF_RXSTAT1_QUEUE	0x1
+#define SF_RXSTAT1_FIFOFULL	0x2
+#define SF_RXSTAT1_OK		0x4
+
+					/* 0=unknown,5=unsupported */
+#define SF_RXSTAT2_FRAMETYPE	0x0007	/* 1=IPv4,2=IPv2,3=IPX,4=ICMP */
+#define SF_RXSTAT2_UDP		0x0008
+#define SF_RXSTAT2_TCP		0x0010
+#define SF_RXSTAT2_FRAG		0x0020
+#define SF_RXSTAT2_PCSUM_OK	0x0040	/* partial checksum ok */
+#define SF_RXSTAT2_CSUM_BAD	0x0080	/* TCP/IP checksum bad */
+#define SF_RXSTAT2_CSUM_OK	0x0100	/* TCP/IP checksum ok */
+#define SF_RXSTAT2_VLAN		0x0200
+#define SF_RXSTAT2_BADRXCODE	0x0400
+#define SF_RXSTAT2_DRIBBLE	0x0800
+#define SF_RXSTAT2_ISL_CRCERR	0x1000
+#define SF_RXSTAT2_CRCERR	0x2000
+#define SF_RXSTAT2_HASH		0x4000
+#define SF_RXSTAT2_PERFECT	0x8000
+
+#define SF_RXSTAT3_TRAILER	0x01
+#define SF_RXSTAT3_HEADER	0x02
+#define SF_RXSTAT3_CONTROL	0x04
+#define SF_RXSTAT3_PAUSE	0x08
+#define SF_RXSTAT3_ISL		0x10
+
+/*
+ * Transmit descriptor formats.
+ * Each transmit descriptor type allows for a skip field at the
+ * start of each structure. The size of the skip field can vary,
+ * however we always set it for 8 bytes, which is enough to hold
+ * a pointer (32 bits on x86, 64-bits on alpha) that we can use
+ * to hold the address of the head of the mbuf chain for the
+ * frame or fragment associated with the descriptor. This saves
+ * us from having to create a separate pointer array to hold
+ * the mbuf addresses.
+ */
+#define SF_TX_BUFDESC_ID		0xB
+#define SF_MAXFRAGS			14
+#define SF_TX_MINSPACING		128
+#define SF_TX_DLIST_CNT			128
+#define SF_TX_DLIST_SIZE		16384
+#define SF_TX_SKIPLEN			1
+#define SF_TX_CLIST_CNT			1024
+
+struct sf_frag {
+	u_int32_t		sf_addr;
+	u_int16_t		sf_fraglen;
+	u_int16_t		sf_pktlen;
+};
+
+struct sf_frag_msdos {
+	u_int16_t		sf_pktlen;
+	u_int16_t		sf_fraglen;
+	u_int32_t		sf_addr;
+};
+
+/*
+ * TX frame descriptor type 0, 32-bit addressing. One descriptor can
+ * be used to map multiple packet fragments. We use this format since
+ * BSD networking fragments packet data across mbuf chains. Note that
+ * the number of fragments can be variable depending on how the descriptor
+ * spacing is specified in the TX descriptor queue control register.
+ * We always use a spacing of 128 bytes, and a skipfield length of 8
+ * bytes: this means 16 bytes for the descriptor, including the skipfield,
+ * with 121 bytes left for fragment maps. Each fragment requires 8 bytes,
+ * which allows for 14 fragments per descriptor. The total size of the
+ * transmit buffer queue is limited to 16384 bytes, so with a spacing of
+ * 128 bytes per descriptor, we have room for 128 descriptors in the queue.
+ */
+struct sf_tx_bufdesc_type0 {
+#ifdef __i386__
+	u_int32_t		sf_pad;
+#endif
+	struct mbuf		*sf_mbuf;
+	u_int32_t		sf_rsvd0:24,
+				sf_crcen:1,
+				sf_caltcp:1,
+				sf_end:1,
+				sf_intr:1,
+				sf_id:4;
+	u_int8_t		sf_fragcnt;
+	u_int8_t		sf_rsvd2;
+	u_int16_t		sf_rsvd1;
+	struct sf_frag		sf_frags[14];
+};
+
+/*
+ * TX buffer descriptor type 1, 32-bit addressing. Each descriptor
+ * maps a single fragment.
+ */
+struct sf_tx_bufdesc_type1 {
+#ifdef __i386__
+	u_int32_t		sf_pad;
+#endif
+	struct mbuf		*sf_mbuf;
+	u_int32_t		sf_fraglen:16,
+				sf_fragcnt:8,
+				sf_crcen:1,
+				sf_caltcp:1,
+				sf_end:1,
+				sf_intr:1,
+				sf_id:4;
+	u_int32_t		sf_addr;
+};
+
+/*
+ * TX buffer descriptor type 2, 64-bit addressing. Each descriptor
+ * maps a single fragment.
+ */
+struct sf_tx_bufdesc_type2 {
+#ifdef __i386__
+	u_int32_t		sf_pad;
+#endif
+	struct mbuf		*sf_mbuf;
+	u_int32_t		sf_fraglen:16,
+				sf_fragcnt:8,
+				sf_crcen:1,
+				sf_caltcp:1,
+				sf_end:1,
+				sf_intr:1,
+				sf_id:4;
+	u_int32_t		sf_addrlo;
+	u_int32_t		sf_addrhi;
+};
+
+/* TX buffer descriptor type 3 is not defined. */
+
+/*
+ * TX frame descriptor type 4, 32-bit addressing. This is a special
+ * case of the type 0 descriptor, identical except that the fragment
+ * address and length fields are ordered differently. This is done
+ * to optimize copies in MS-DOS and OS/2 drivers.
+ */
+struct sf_tx_bufdesc_type4 {
+#ifdef __i386__
+	u_int32_t		sf_pad;
+#endif
+	struct mbuf		*sf_mbuf;
+	u_int32_t		sf_rsvd0:24,
+				sf_crcen:1,
+				sf_caltcp:1,
+				sf_end:1,
+				sf_intr:1,
+				sf_id:4;
+	u_int8_t		sf_fragcnt;
+	u_int8_t		sf_rsvd2;
+	u_int16_t		sf_rsvd1;
+	struct sf_frag_msdos	sf_frags[14];
+};
+
+/*
+ * Transmit completion queue descriptor formats.
+ */
+
+/*
+ * Transmit DMA completion descriptor, type 0.
+ */
+#define SF_TXCMPTYPE_DMA	0x4
+struct sf_tx_cmpdesc_type0 {
+	u_int32_t		sf_index:15,
+				sf_priority:1,
+				sf_timestamp:13,
+				sf_type:3;
+};
+
+/*
+ * Transmit completion descriptor, type 1.
+ */
+#define SF_TXCMPTYPE_TX		0x5
+struct sf_tx_cmpdesc_type1 {
+	u_int32_t		sf_index:15,
+				sf_priority:1,
+				sf_txstat:13,
+				sf_type:3;
+};
+
+#define SF_TXSTAT_CRCERR	0x0001
+#define SF_TXSTAT_LENCHECKERR	0x0002
+#define SF_TXSTAT_LENRANGEERR	0x0004
+#define SF_TXSTAT_TX_OK		0x0008
+#define SF_TXSTAT_TX_DEFERED	0x0010
+#define SF_TXSTAT_EXCESS_DEFER	0x0020
+#define SF_TXSTAT_EXCESS_COLL	0x0040
+#define SF_TXSTAT_LATE_COLL	0x0080
+#define SF_TXSTAT_TOOBIG	0x0100
+#define SF_TXSTAT_TX_UNDERRUN	0x0200
+#define SF_TXSTAT_CTLFRAME_OK	0x0400
+#define SF_TXSTAT_PAUSEFRAME_OK	0x0800
+#define SF_TXSTAT_PAUSED	0x1000
+
+/* Statistics counters. */
+struct sf_stats {
+	u_int32_t		sf_tx_frames;
+	u_int32_t		sf_tx_single_colls;
+	u_int32_t		sf_tx_multi_colls;
+	u_int32_t		sf_tx_crcerrs;
+	u_int32_t		sf_tx_bytes;
+	u_int32_t		sf_tx_defered;
+	u_int32_t		sf_tx_late_colls;
+	u_int32_t		sf_tx_pause_frames;
+	u_int32_t		sf_tx_control_frames;
+	u_int32_t		sf_tx_excess_colls;
+	u_int32_t		sf_tx_excess_defer;
+	u_int32_t		sf_tx_mcast_frames;
+	u_int32_t		sf_tx_bcast_frames;
+	u_int32_t		sf_tx_frames_lost;
+	u_int32_t		sf_rx_rx_frames;
+	u_int32_t		sf_rx_crcerrs;
+	u_int32_t		sf_rx_alignerrs;
+	u_int32_t		sf_rx_bytes;
+	u_int32_t		sf_rx_control_frames;
+	u_int32_t		sf_rx_unsup_control_frames;
+	u_int32_t		sf_rx_giants;
+	u_int32_t		sf_rx_runts;
+	u_int32_t		sf_rx_jabbererrs;
+	u_int32_t		sf_rx_pkts_64;
+	u_int32_t		sf_rx_pkts_65_127;
+	u_int32_t		sf_rx_pkts_128_255;
+	u_int32_t		sf_rx_pkts_256_511;
+	u_int32_t		sf_rx_pkts_512_1023;
+	u_int32_t		sf_rx_pkts_1024_1518;
+	u_int32_t		sf_rx_frames_lost;
+	u_int16_t		sf_tx_underruns;
+	u_int16_t		sf_pad;
+};
+
+/*
+ * register space access macros
+ */
+#define CSR_WRITE_4(sc, reg, val)	\
+	bus_space_write_4(sc->sf_btag, sc->sf_bhandle, reg, val)
+
+#define CSR_READ_4(sc, reg)		\
+	bus_space_read_4(sc->sf_btag, sc->sf_bhandle, reg)
+
+#define CSR_READ_1(sc, reg)		\
+	bus_space_read_1(sc->sf_btag, sc->sf_bhandle, reg)
+
+
+struct sf_type {
+	u_int16_t		sf_vid;
+	u_int16_t		sf_did;
+	char			*sf_name;
+};
+
+#define SF_INC(x, y)	(x) = (x + 1) % y
+
+#define ETHER_ALIGN 2
+
+/*
+ * Note: alignment is important here: each list must be aligned to
+ * a 256-byte boundary. It turns out that each ring is some multiple
+ * of 4K in length, so we can stack them all on top of each other
+ * and just worry about aligning the whole mess. There's one transmit
+ * buffer ring and two receive buffer rings: one RX ring is for small
+ * packets and the other is for large packets. Each buffer ring also
+ * has a companion completion queue.
+ */
+struct sf_list_data {
+	struct sf_tx_bufdesc_type0	sf_tx_dlist[SF_TX_DLIST_CNT];
+	struct sf_tx_cmpdesc_type1	sf_tx_clist[SF_TX_CLIST_CNT];
+	struct sf_rx_bufdesc_type0	sf_rx_dlist_big[SF_RX_DLIST_CNT];
+	struct sf_rx_bufdesc_type0	sf_rx_dlist_small[SF_RX_DLIST_CNT];
+	struct sf_rx_cmpdesc_type3	sf_rx_clist[SF_RX_CLIST_CNT];
+};
+
+struct sf_softc {
+	struct arpcom		arpcom;		/* interface info */
+	struct ifmedia		ifmedia;	/* media info */
+	bus_space_handle_t	sf_bhandle;	/* bus space handle */
+	bus_space_tag_t		sf_btag;	/* bus space tag */
+	void			*sf_intrhand;	/* interrupt handler cookie */
+	struct resource		*sf_irq;	/* irq resource descriptor */
+	struct resource		*sf_res;	/* mem/ioport resource */
+	struct sf_type		*sf_info;	/* Starfire adapter info */
+	struct sf_type		*sf_pinfo;	/* phy info */
+	u_int8_t		sf_unit;	/* interface number */
+	u_int8_t		sf_type;
+	u_int8_t		sf_phy_addr;	/* PHY address */
+	u_int8_t		sf_tx_pend;	/* TX pending */
+	u_int8_t		sf_want_auto;
+	u_int8_t		sf_autoneg;
+	struct sf_list_data	*sf_ldata;
+	int			sf_tx_cnt;
+	struct callout_handle	sf_stat_ch;
+};
+
+#define SF_TIMEOUT	1000
+
+#define SF_FLAG_FORCEDELAY	1
+#define SF_FLAG_SCHEDDELAY	2
+#define SF_FLAG_DELAYTIMEO	3
+
+/*
+ * Texas Instruments PHY identifiers
+ */
+#define TI_PHY_VENDORID		0x4000
+#define TI_PHY_10BT		0x501F
+#define TI_PHY_100VGPMI		0x502F
+
+/*
+ * These ID values are for the NS DP83840A 10/100 PHY
+ */
+#define NS_PHY_VENDORID		0x2000
+#define NS_PHY_83840A		0x5C0F
+
+/*
+ * Level 1 10/100 PHY
+ */
+#define LEVEL1_PHY_VENDORID	0x7810
+#define LEVEL1_PHY_LXT970	0x000F
+
+/*
+ * Intel 82555 10/100 PHY
+ */
+#define INTEL_PHY_VENDORID	0x0A28
+#define INTEL_PHY_82555		0x015F
+
+/*
+ * SEEQ 80220 10/100 PHY
+ */
+#define SEEQ_PHY_VENDORID	0x0016
+#define SEEQ_PHY_80220		0xF83F
+
+#define PHY_UNKNOWN		6
+
+#define SF_PHYADDR_MIN		0x00
+#define SF_PHYADDR_MAX		0x1F
+
+#define PHY_BMCR		0x00
+#define PHY_BMSR		0x01
+#define PHY_VENID		0x02
+#define PHY_DEVID		0x03
+#define PHY_ANAR		0x04
+#define PHY_LPAR		0x05
+#define PHY_ANEXP		0x06
+
+#define PHY_ANAR_NEXTPAGE	0x8000
+#define PHY_ANAR_RSVD0		0x4000
+#define PHY_ANAR_TLRFLT		0x2000
+#define PHY_ANAR_RSVD1		0x1000
+#define PHY_ANAR_RSVD2		0x0800
+#define PHY_ANAR_RSVD3		0x0400
+#define PHY_ANAR_100BT4		0x0200
+#define PHY_ANAR_100BTXFULL	0x0100
+#define PHY_ANAR_100BTXHALF	0x0080
+#define PHY_ANAR_10BTFULL	0x0040
+#define PHY_ANAR_10BTHALF	0x0020
+#define PHY_ANAR_PROTO4		0x0010
+#define PHY_ANAR_PROTO3		0x0008
+#define PHY_ANAR_PROTO2		0x0004
+#define PHY_ANAR_PROTO1		0x0002
+#define PHY_ANAR_PROTO0		0x0001
+
+/*
+ * These are the register definitions for the PHY (physical layer
+ * interface chip).
+ */
+/*
+ * PHY BMCR Basic Mode Control Register
+ */
+#define PHY_BMCR_RESET			0x8000
+#define PHY_BMCR_LOOPBK			0x4000
+#define PHY_BMCR_SPEEDSEL		0x2000
+#define PHY_BMCR_AUTONEGENBL		0x1000
+#define PHY_BMCR_RSVD0			0x0800	/* write as zero */
+#define PHY_BMCR_ISOLATE		0x0400
+#define PHY_BMCR_AUTONEGRSTR		0x0200
+#define PHY_BMCR_DUPLEX			0x0100
+#define PHY_BMCR_COLLTEST		0x0080
+#define PHY_BMCR_RSVD1			0x0040	/* write as zero, don't care */
+#define PHY_BMCR_RSVD2			0x0020	/* write as zero, don't care */
+#define PHY_BMCR_RSVD3			0x0010	/* write as zero, don't care */
+#define PHY_BMCR_RSVD4			0x0008	/* write as zero, don't care */
+#define PHY_BMCR_RSVD5			0x0004	/* write as zero, don't care */
+#define PHY_BMCR_RSVD6			0x0002	/* write as zero, don't care */
+#define PHY_BMCR_RSVD7			0x0001	/* write as zero, don't care */
+/*
+ * RESET: 1 == software reset, 0 == normal operation
+ * Resets status and control registers to default values.
+ * Relatches all hardware config values.
+ *
+ * LOOPBK: 1 == loopback operation enabled, 0 == normal operation
+ *
+ * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
+ * Link speed is selected byt his bit or if auto-negotiation if bit
+ * 12 (AUTONEGENBL) is set (in which case the value of this register
+ * is ignored).
+ *
+ * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
+ * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
+ * determine speed and mode. Should be cleared and then set if PHY configured
+ * for no autoneg on startup.
+ *
+ * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
+ *
+ * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
+ *
+ * DUPLEX: 1 == full duplex mode, 0 == half duplex mode
+ *
+ * COLLTEST: 1 == collision test enabled, 0 == normal operation
+ */
+
+/* 
+ * PHY, BMSR Basic Mode Status Register 
+ */   
+#define PHY_BMSR_100BT4			0x8000
+#define PHY_BMSR_100BTXFULL		0x4000
+#define PHY_BMSR_100BTXHALF		0x2000
+#define PHY_BMSR_10BTFULL		0x1000
+#define PHY_BMSR_10BTHALF		0x0800
+#define PHY_BMSR_RSVD1			0x0400	/* write as zero, don't care */
+#define PHY_BMSR_RSVD2			0x0200	/* write as zero, don't care */
+#define PHY_BMSR_RSVD3			0x0100	/* write as zero, don't care */
+#define PHY_BMSR_RSVD4			0x0080	/* write as zero, don't care */
+#define PHY_BMSR_MFPRESUP		0x0040
+#define PHY_BMSR_AUTONEGCOMP		0x0020
+#define PHY_BMSR_REMFAULT		0x0010
+#define PHY_BMSR_CANAUTONEG		0x0008
+#define PHY_BMSR_LINKSTAT		0x0004
+#define PHY_BMSR_JABBER			0x0002
+#define PHY_BMSR_EXTENDED		0x0001
+
+#ifdef __alpha__
+#undef vtophys
+#define vtophys(va)		alpha_XXX_dmamap((vm_offset_t)va)
+#endif