More fully initialize cardbus bridges. We now call the new generic

cardbus bridge init routine for all cardbuses.  This routine attempts
to compensate for BIOSes that do not setup the cardbus bridge into
legacy mode.  Since this is becoming more common, and cardbus pci
cards have appeared on the market, this makes sense.

Do some TI113x specific initialization.  This came in as part of the
patch.  Report TI1[1234]XX specific config registers protected by
bootverbose.

Minor code cleanup while I'm here.  I've also removed the unused code
present in the original patches, and cleaned it up slightly in places
as well.

The original patches supported more than one card, but these patches
support just one.  We should likely revisit this in the future.

This makes the Compaq card that Walnut Creek CD purchased for me work
in my bouncer box.

This is a MFC candidate.  However, I'd like to get some airtime on
these patches on as many laptops as possible before doing the MFC.  It
does change things somewhat.  In theory, apart from the minor TI
tweaks, this shouldn't change anything if the bridge is in legacy mode
already.

Submitted by: sanpei@sanpei.org (MIHIRA Yoshiro)

1 files changed, 79 insertions, 0 deletions

diff --git a/sys/pci/pcic_p.h b/sys/pci/pcic_p.h
index 0193a11..a6966a8 100644
--- a/sys/pci/pcic_p.h
+++ b/sys/pci/pcic_p.h
@@ -69,3 +69,82 @@
 #define	CLPD6832_NUM_REGS		2
 
 /* End of CL-PD6832 defines */
+/* Texas Instruments PCI-1130/1131 CardBus Controller */
+#define TI113X_PCI_SYSTEM_CONTROL	0x80	/* System Control */
+#define TI113X_PCI_RETRY_STATUS		0x90	/* Retry Status */
+#define TI113X_PCI_CARD_CONTROL		0x91	/* Card Control */
+#define TI113X_PCI_DEVICE_CONTROL	0x92	/* Device Control */
+#define TI113X_PCI_BUFFER_CONTROL	0x93	/* Buffer Control */
+#define TI113X_PCI_SOCKET_DMA0		0x94	/* Socket DMA Register 0 */
+#define TI113X_PCI_SOCKET_DMA1		0x98	/* Socket DMA Register 1 */
+
+/* Card control register (TI113X_SYSTEM_CONTROL == 0x80) */
+#define TI113X_SYSCNTL_VCC_PROTECT	0x00200000u
+#define TI113X_SYSCNTL_CLKRUN_SEL	0x00000080u
+#define	TI113X_SYSCNTL_PWRSAVINGS	0x00000040u
+#define TI113X_SYSCNTL_KEEP_CLK		0x00000002u
+#define TI113X_SYSCNTL_CLKRUN_ENA	0x00000001u
+
+/* Card control register (TI113X_CARD_CONTROL == 0x91) */
+#define TI113X_CARDCNTL_RING_ENA	0x80u
+#define TI113X_CARDCNTL_ZOOM_VIDEO	0x40u
+#define TI113X_CARDCNTL_PCI_IRQ_ENA	0x20u
+#define TI113X_CARDCNTL_PCI_IREQ	0x10u
+#define TI113X_CARDCNTL_PCI_CSC		0x08u
+#define	TI113X_CARDCNTL_MASK		(TI113X_CARDCNTL_PCI_IRQ_ENA | TI113X_CARDCNTL_PCI_IREQ | TI113X_CARDCNTL_PCI_CSC)
+#define	TI113X_FUNC0_VALID		TI113X_CARDCNTL_MASK
+#define	TI113X_FUNC1_VALID		(TI113X_CARDCNTL_PCI_IREQ | TI113X_CARDCNTL_PCI_CSC)
+/* Reserved bit				0x04u */
+#define TI113X_CARDCNTL_SPKR_ENA	0x02u
+#define TI113X_CARDCNTL_INT		0x01u
+
+/* Device control register (TI113X_DEVICE_CONTROL == 0x92) */
+#define	TI113X_DEVCNTL_5V_SOCKET	0x40u
+#define	TI113X_DEVCNTL_3V_SOCKET	0x20u
+#define	TI113X_DEVCNTL_INTR_MASK	0x06u
+#define	TI113X_DEVCNTL_INTR_NONE	0x00u
+#define	TI113X_DEVCNTL_INTR_ISA		0x02u
+#define	TI113X_DEVCNTL_INTR_SERIAL	0x04u
+/* TI112X specific code */
+#define	TI12XX_DEVCNTL_INTR_ALLSERIAL	0x06u
+/* Texas Instruments PCI-1130/1131 CardBus Controller */
+#define	TI113X_ExCA_IO_OFFSET0		0x36	/* Offset of I/O window */
+#define	TI113X_ExCA_IO_OFFSET1		0x38	/* Offset of I/O window */
+#define	TI113X_ExCA_MEM_WINDOW_PAGE	0x3C	/* Memory Window Page */
+
+/* sanpei */
+
+/* For Bridge Control register (CB_PCI_BRIDGE_CTRL) */
+#define CB_BCR_CB_RESET		0x0040
+#define CB_BCR_INT_EXCA		0x0080
+/* PCI Configuration Registers (common) */
+#define	CB_PCI_VENDOR_ID	0x00	/* vendor ID */
+#define	CB_PCI_DEVICE_ID	0x02	/* device ID */
+#define	CB_PCI_COMMAND		0x04	/* PCI command */
+#define	CB_PCI_STATUS		0x06	/* PCI status */
+#define	CB_PCI_REVISION_ID	0x08	/* PCI revision ID */
+#define	CB_PCI_CLASS		0x09	/* PCI class code */
+#define	CB_PCI_CACHE_LINE_SIZE	0x0c	/* Cache line size */
+#define	CB_PCI_LATENCY		0x0d	/* PCI latency timer */
+#define	CB_PCI_HEADER_TYPE	0x0e	/* PCI header type */
+#define	CB_PCI_BIST		0x0f	/* Built-in self test */
+#define	CB_PCI_SOCKET_BASE	0x10	/* Socket/ExCA base address reg. */
+#define	CB_PCI_CB_STATUS	0x16	/* CardBus Status */
+#define	CB_PCI_PCI_BUS_NUM	0x18	/* PCI bus number */
+#define	CB_PCI_CB_BUS_NUM	0x19	/* CardBus bus number */
+#define	CB_PCI_CB_SUB_BUS_NUM	0x1A	/* Subordinate CardBus bus number */
+#define	CB_PCI_CB_LATENCY	0x1A	/* CardBus latency timer */
+#define	CB_PCI_MEMBASE0		0x1C	/* Memory base register 0 */
+#define	CB_PCI_MEMLIMIT0	0x20	/* Memory limit register 0 */
+#define	CB_PCI_MEMBASE1		0x24	/* Memory base register 1 */
+#define	CB_PCI_MEMLIMIT1	0x28	/* Memory limit register 1 */
+#define	CB_PCI_IOBASE0		0x2C	/* I/O base register 0 */
+#define	CB_PCI_IOLIMIT0		0x30	/* I/O limit register 0 */
+#define	CB_PCI_IOBASE1		0x34	/* I/O base register 1 */
+#define	CB_PCI_IOLIMIT1		0x38	/* I/O limit register 1 */
+#define	CB_PCI_INT_LINE		0x3C	/* Interrupt Line */
+#define	CB_PCI_INT_PIN		0x3D	/* Interrupt Pin */
+#define	CB_PCI_BRIDGE_CTRL	0x3E	/* Bridge Control */
+#define	CB_PCI_SUBSYS_VENDOR_ID	0x40	/* Subsystem Vendor ID */
+#define	CB_PCI_SUBSYS_ID	0x42	/* Subsystem ID */
+#define	CB_PCI_LEGACY16_IOADDR	0x44	/* Legacy 16bit I/O address */