Convert the 3Com XL driver to miibus. This one is a little tricky

due to the fact that there are non-MII cards supported by the same
driver and I don't have all of the cards available for testing. There's
also the 3c905B-COMBO which has MII, AUI and BNC media ports all in one
package. Supporting the COMBO is difficult because we have to add the
10base5 and 10base2 media types to the same ifmedia struct as the
MII-attached types, however there is no way to force the miibus and
child PHYs into existence before xl_attach() completes, so there is
no ifmedia struct available in xl_attach(). What we do inistead is
use the mediainit method as a callback: when a child PHY is attached,
it calls the miibus mediainit routine which selects a default media.
This routing also calls the NIC driver's mediainit method (if it
implements one) at which point we can safely add the other media
types.

1 files changed, 1 insertions, 154 deletions

diff --git a/sys/pci/if_xlreg.h b/sys/pci/if_xlreg.h
index b50f068..3bdf32d 100644
--- a/sys/pci/if_xlreg.h
+++ b/sys/pci/if_xlreg.h
@@ -532,10 +532,6 @@ struct xl_mii_frame {
 #define XL_TYPE_905B	1
 #define XL_TYPE_90X	2
 
-#define XL_FLAG_FORCEDELAY	1
-#define XL_FLAG_SCHEDDELAY	2
-#define XL_FLAG_DELAYTIMEO	3	
-
 struct xl_softc {
 	struct arpcom		arpcom;		/* interface info */
 	struct ifmedia		ifmedia;	/* media info */
@@ -544,17 +540,13 @@ struct xl_softc {
 	void			*xl_intrhand;
 	struct resource		*xl_irq;
 	struct resource		*xl_res;
+	device_t		xl_miibus;
 	struct xl_type		*xl_info;	/* 3Com adapter info */
-	struct xl_type		*xl_pinfo;	/* phy info */
 	u_int8_t		xl_unit;	/* interface number */
 	u_int8_t		xl_type;
-	u_int8_t		xl_phy_addr;	/* PHY address */
 	u_int32_t		xl_xcvr;
 	u_int16_t		xl_media;
 	u_int16_t		xl_caps;
-	u_int8_t		xl_tx_pend;	/* TX pending */
-	u_int8_t		xl_want_auto;
-	u_int8_t		xl_autoneg;
 	u_int8_t		xl_stats_no_timeout;
 	u_int16_t		xl_tx_thresh;
 	caddr_t			xl_ldata_ptr;
@@ -633,50 +625,6 @@ struct xl_stats {
 #define TC_DEVICEID_HURRICANE_SOHO100TX		0x7646
 
 /*
- * Texas Instruments PHY identifiers
- *
- * The ThunderLAN manual has a curious and confusing error in it.
- * In chapter 7, which describes PHYs, it says that TI PHYs have
- * the following ID codes, where xx denotes a revision:
- *
- * 0x4000501xx			internal 10baseT PHY
- * 0x4000502xx			TNETE211 100VG-AnyLan PMI
- *
- * The problem here is that these are not valid 32-bit hex numbers:
- * there's one digit too many. My guess is that they mean the internal
- * 10baseT PHY is 0x4000501x and the TNETE211 is 0x4000502x since these
- * are the only numbers that make sense.
- */
-#define TI_PHY_VENDORID		0x4000
-#define TI_PHY_10BT		0x501F
-#define TI_PHY_100VGPMI		0x502F
-
-/*
- * These ID values are for the NS DP83840A 10/100 PHY
- */
-#define NS_PHY_VENDORID		0x2000
-#define NS_PHY_83840A		0x5C0F
-
-/*
- * Level 1 10/100 PHY
- */
-#define LEVEL1_PHY_VENDORID	0x7810
-#define LEVEL1_PHY_LXT970	0x000F
-
-/*
- * Intel 82555 10/100 PHY
- */
-#define INTEL_PHY_VENDORID	0x0A28
-#define INTEL_PHY_82555		0x015F
-
-/*
- * SEEQ 80220 10/100 PHY
- */
-#define SEEQ_PHY_VENDORID	0x0016
-#define SEEQ_PHY_80220		0xF83F
-
-
-/*
  * PCI low memory base and low I/O base register, and
  * other PCI registers. Note: some are only available on
  * the 3c905B, in particular those that related to power management.
@@ -713,107 +661,6 @@ struct xl_stats {
 #define XL_PME_EN		0x0010
 #define XL_PME_STATUS		0x8000
 
-#define PHY_UNKNOWN		6
-
-#define XL_PHYADDR_MIN		0x00
-#define XL_PHYADDR_MAX		0x1F
-
-#define XL_PHY_GENCTL		0x00
-#define XL_PHY_GENSTS		0x01
-#define XL_PHY_VENID		0x02
-#define XL_PHY_DEVID		0x03
-#define XL_PHY_ANAR		0x04
-#define XL_PHY_LPAR		0x05
-#define XL_PHY_ANEXP		0x06
-
-#define PHY_ANAR_NEXTPAGE	0x8000
-#define PHY_ANAR_RSVD0		0x4000
-#define PHY_ANAR_TLRFLT		0x2000
-#define PHY_ANAR_RSVD1		0x1000
-#define PHY_ANAR_RSVD2		0x0800
-#define PHY_ANAR_RSVD3		0x0400
-#define PHY_ANAR_100BT4		0x0200
-#define PHY_ANAR_100BTXFULL	0x0100
-#define PHY_ANAR_100BTXHALF	0x0080
-#define PHY_ANAR_10BTFULL	0x0040
-#define PHY_ANAR_10BTHALF	0x0020
-#define PHY_ANAR_PROTO4		0x0010
-#define PHY_ANAR_PROTO3		0x0008
-#define PHY_ANAR_PROTO2		0x0004
-#define PHY_ANAR_PROTO1		0x0002
-#define PHY_ANAR_PROTO0		0x0001
-
-/*
- * These are the register definitions for the PHY (physical layer
- * interface chip).
- */
-/*
- * PHY BMCR Basic Mode Control Register
- */
-#define PHY_BMCR			0x00
-#define PHY_BMCR_RESET			0x8000
-#define PHY_BMCR_LOOPBK			0x4000
-#define PHY_BMCR_SPEEDSEL		0x2000
-#define PHY_BMCR_AUTONEGENBL		0x1000
-#define PHY_BMCR_RSVD0			0x0800	/* write as zero */
-#define PHY_BMCR_ISOLATE		0x0400
-#define PHY_BMCR_AUTONEGRSTR		0x0200
-#define PHY_BMCR_DUPLEX			0x0100
-#define PHY_BMCR_COLLTEST		0x0080
-#define PHY_BMCR_RSVD1			0x0040	/* write as zero, don't care */
-#define PHY_BMCR_RSVD2			0x0020	/* write as zero, don't care */
-#define PHY_BMCR_RSVD3			0x0010	/* write as zero, don't care */
-#define PHY_BMCR_RSVD4			0x0008	/* write as zero, don't care */
-#define PHY_BMCR_RSVD5			0x0004	/* write as zero, don't care */
-#define PHY_BMCR_RSVD6			0x0002	/* write as zero, don't care */
-#define PHY_BMCR_RSVD7			0x0001	/* write as zero, don't care */
-/*
- * RESET: 1 == software reset, 0 == normal operation
- * Resets status and control registers to default values.
- * Relatches all hardware config values.
- *
- * LOOPBK: 1 == loopback operation enabled, 0 == normal operation
- *
- * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
- * Link speed is selected byt his bit or if auto-negotiation if bit
- * 12 (AUTONEGENBL) is set (in which case the value of this register
- * is ignored).
- *
- * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
- * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
- * determine speed and mode. Should be cleared and then set if PHY configured
- * for no autoneg on startup.
- *
- * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
- *
- * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
- *
- * DUPLEX: 1 == full duplex mode, 0 == half duplex mode
- *
- * COLLTEST: 1 == collision test enabled, 0 == normal operation
- */
-
-/* 
- * PHY, BMSR Basic Mode Status Register 
- */   
-#define PHY_BMSR			0x01
-#define PHY_BMSR_100BT4			0x8000
-#define PHY_BMSR_100BTXFULL		0x4000
-#define PHY_BMSR_100BTXHALF		0x2000
-#define PHY_BMSR_10BTFULL		0x1000
-#define PHY_BMSR_10BTHALF		0x0800
-#define PHY_BMSR_RSVD1			0x0400	/* write as zero, don't care */
-#define PHY_BMSR_RSVD2			0x0200	/* write as zero, don't care */
-#define PHY_BMSR_RSVD3			0x0100	/* write as zero, don't care */
-#define PHY_BMSR_RSVD4			0x0080	/* write as zero, don't care */
-#define PHY_BMSR_MFPRESUP		0x0040
-#define PHY_BMSR_AUTONEGCOMP		0x0020
-#define PHY_BMSR_REMFAULT		0x0010
-#define PHY_BMSR_CANAUTONEG		0x0008
-#define PHY_BMSR_LINKSTAT		0x0004
-#define PHY_BMSR_JABBER			0x0002
-#define PHY_BMSR_EXTENDED		0x0001
-
 #ifdef __alpha__
 #undef vtophys
 #define vtophys(va)		alpha_XXX_dmamap((vm_offset_t)va)