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author | marius <marius@FreeBSD.org> | 2006-11-28 01:33:17 +0000 |
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committer | marius <marius@FreeBSD.org> | 2006-11-28 01:33:17 +0000 |
commit | afd1d490a36553dd8602bec755aa243b0243287f (patch) | |
tree | 875ba3786f2575b0a24e543acf8d7b333097a1df /sys/pci/if_pcnreg.h | |
parent | 90cd17ca93f04a8bbe97d57bf53d0a4cf497bafd (diff) | |
download | FreeBSD-src-afd1d490a36553dd8602bec755aa243b0243287f.zip FreeBSD-src-afd1d490a36553dd8602bec755aa243b0243287f.tar.gz |
- Clear the PCN_MISC_ASEL bit so the media port can be actually set
via the PCN_CSR_MODE register. Along with sys/dev/mii/nsphy.c 1.26
this fixes the case of certain Am79c971-based HP cards and on-board
ones in IBM machines reporting link but not actually passing any
traffic. [1]
- Add support for the internal 10baseT PHY, which actually is used on
at least said HP cards (together with an external DP83840A in a
multiple PHYs configuration). With cards that don't make use of this
internal PHY it'll also show up in FreeBSD but not cause any harm.
This is still missing support for multiple PHYs configuration using
the internal 100baseTX and/or HomePNA PHYs together with external
PHYs or multiple external PHYs though.
- In pcn_ifmedia_upd() call pcn_reset() as otherwise the Am79C971 of
at least said HP cards can wedge when switching from the internal
10baseT PHY to the external PHY. This means that we need to also
initialize and possibly start the chip again in pcn_ifmedia_upd(),
which isn't that bad though as for setting the media port the chip
has to be powered down or stopped anyway and unlike documented
doesn't take effect until the next initialization.
PR: 27995, 25959, 72966 (likely) [1]
MFC after: 2 weeks
Diffstat (limited to 'sys/pci/if_pcnreg.h')
-rw-r--r-- | sys/pci/if_pcnreg.h | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/sys/pci/if_pcnreg.h b/sys/pci/if_pcnreg.h index da7e567..406d438 100644 --- a/sys/pci/if_pcnreg.h +++ b/sys/pci/if_pcnreg.h @@ -206,7 +206,7 @@ #define PCN_MODE_RXNOBROAD 0x4000 #define PCN_MODE_PROMISC 0x8000 -/* Settings for PCN_MODE_PORTSEL when ASEL (BCR2[1] is 0 */ +/* Settings for PCN_MODE_PORTSEL when ASEL (BCR2[1]) is 0 */ #define PCN_PORT_AUI 0x0000 #define PCN_PORT_10BASET 0x0080 #define PCN_PORT_GPSI 0x0100 @@ -339,7 +339,11 @@ * MII address register (BCR33) */ #define PCN_MIIADDR_REGAD 0x001F -#define PCN_MIIADDR_PHYADD 0x03E0 +#define PCN_MIIADDR_PHYAD 0x03E0 + +/* addresses of internal PHYs */ +#define PCN_PHYAD_100BTX 30 +#define PCN_PHYAD_10BT 31 /* * MII data register (BCR34) @@ -453,7 +457,8 @@ struct pcn_softc { void *pcn_intrhand; device_t pcn_miibus; u_int8_t pcn_link; - u_int8_t pcn_phyaddr; + int8_t pcn_extphyaddr; + int8_t pcn_inst_10bt; int pcn_if_flags; int pcn_type; struct pcn_list_data *pcn_ldata; @@ -481,7 +486,6 @@ struct pcn_softc { #define CSR_READ_2(sc, reg) \ bus_space_read_2(sc->pcn_btag, sc->pcn_bhandle, reg) - #define PCN_TIMEOUT 1000 #define ETHER_ALIGN 2 #define PCN_RXLEN 1536 |