Bug fixes that I've put together while working on a project in the office:

if_vr: handle the case where vr_encap() returns failure: bust out of the
       packet sending loop instead of panicking. Also add some missing
       newlines to some printf()s.

if_dc: The miibus_read and miibus_write methods keep swapping in and
       out of MII mode by fiddling with CSR6 for cards with MII PHYs.
       This is a hack to support the original Macronix 98713 card which
       has built-in NWAY that uses an MII-like management interface
       even though it uses serial transceivers. Conditionalize this
       so that we only do this on 98713 chips, since it does bad things
       to genuine tulip chips (and maybe other clones).

1 files changed, 12 insertions, 6 deletions

diff --git a/sys/pci/if_dc.c b/sys/pci/if_dc.c
index 3b5e91a..c27a45e 100644
--- a/sys/pci/if_dc.c
+++ b/sys/pci/if_dc.c
@@ -799,10 +799,13 @@ static int dc_miibus_readreg(dev, phy, reg)
 
 	frame.mii_phyaddr = phy;
 	frame.mii_regaddr = reg;
-	phy_reg = CSR_READ_4(sc, DC_NETCFG);
-	CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
+	if (sc->dc_type == DC_TYPE_98713) {
+		phy_reg = CSR_READ_4(sc, DC_NETCFG);
+		CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
+	}
 	dc_mii_readreg(sc, &frame);
-	CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
+	if (sc->dc_type == DC_TYPE_98713)
+		CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
 
 	return(frame.mii_data);
 }
@@ -869,10 +872,13 @@ static int dc_miibus_writereg(dev, phy, reg, data)
 	frame.mii_regaddr = reg;
 	frame.mii_data = data;
 
-	phy_reg = CSR_READ_4(sc, DC_NETCFG);
-	CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
+	if (sc->dc_type == DC_TYPE_98713) {
+		phy_reg = CSR_READ_4(sc, DC_NETCFG);
+		CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
+	}
 	dc_mii_writereg(sc, &frame);
-	CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
+	if (sc->dc_type == DC_TYPE_98713)
+		CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
 
 	return(0);
 }