- Style police

- Updated some comments using data from the most recent PAO release.

Obtained (partially) from:	PAO-970616

1 files changed, 9 insertions, 9 deletions

diff --git a/sys/pccard/i82365.h b/sys/pccard/i82365.h
index 5940f1f..93f5047 100644
--- a/sys/pccard/i82365.h
+++ b/sys/pccard/i82365.h
@@ -38,13 +38,13 @@
 #define	PCIC_VLSI	2		/* VLSI chip */
 #define	PCIC_PD672X	3		/* Cirrus logic 627x */
 #define	PCIC_PD6710	4		/* Cirrus logic 6710 */
-#define	PCIC_CL6729	5
-#define	PCIC_VG468	6
-#define	PCIC_VG469	7
+#define	PCIC_CL6729	5		/* Cirrus logic 6729 */
+#define	PCIC_VG468	6		/* Vadem 468 */
+#define	PCIC_VG469	7		/* Vadem 469 */
 #define	PCIC_RF5C396	8		/* Ricoh RF5C396 */
 #define	PCIC_IBM_KING	9		/* IBM KING PCMCIA Controller */
-#define	PCIC_PC98	10
-#define PCIC_TI1130	11		/* TI PCI1130 CardBus */
+#define	PCIC_PC98	10		/* NEC PC98 PCMCIA Controller */
+#define	PCIC_TI1130	11		/* TI PCI1130 CardBus */
 
 /*
  *	Address of the controllers. Each controller can manage
@@ -57,10 +57,10 @@
  *	identify the port number, and the lower 6 bits
  *	select one of the 64 possible data registers.
  */
-#define PCIC_INDEX_0	0x3E0	/* index reg, chips 0 and 1 */
-#define PCIC_DATA_0	0x3E1	/* data register, chips 0 and 1 */
-#define PCIC_INDEX_1	0x3E2	/* index reg, chips 2 and 3 */
-#define PCIC_DATA_1	0x3E3	/* data register, chips 2 and 3 */
+#define PCIC_INDEX_0	0x3E0			/* index reg, chips 0 and 1 */
+#define PCIC_DATA_0	(PCIC_INDEX_0 + 1)	/* data reg, chips 0 and 1 */
+#define PCIC_INDEX_1	(PCIC_INDEX_0 + 2)	/* index reg, chips 2 and 3 */
+#define PCIC_DATA_1	(PCIC_INDEX_1 + 1)	/* data reg, chips 2 and 3 */
 /*
  *	Register index addresses.
  */