Add AP121 ethernet / switch PHY support.

* arge0 is MII
* arge1 is GMII
* the MDIO bus is on arge1, not arge0
* the default switch config is to have ports 0-3 as the switch group,
  with port 4 being an external PHY dedicated to arge0 (ie, 'cpu' port.)

Whilst I'm here, remove unused bits and pieces from the config.

Tested:

* AP121, ping on both arge0 and arge1
* Tested switch port detection using etherswitchcfg

2 files changed, 28 insertions, 34 deletions

diff --git a/sys/mips/conf/AP121 b/sys/mips/conf/AP121
index 9c933a1..ac4a3b6 100644
--- a/sys/mips/conf/AP121
+++ b/sys/mips/conf/AP121
@@ -18,7 +18,7 @@ ident           AP121
 hints           "AP121.hints"
 
 # Force the board memory - the base AP121 only has 16MB RAM
-options         AR71XX_REALMEM=16*1024*1024
+options         AR71XX_REALMEM=(16*1024*1024)
 
 # i2c GPIO bus
 #device		gpioiic
@@ -26,11 +26,12 @@ options         AR71XX_REALMEM=16*1024*1024
 #device		iicbus
 #device		iic
 
-# ethernet switch device
-#device		etherswitch
+# Options required for miiproxy and mdiobus
+options 	ARGE_MDIO	# Export an MDIO bus separate from arge
+device		miiproxy	# MDIO bus <-> MII PHY rendezvous
 
-# RTL8366RB support
-#device		rtl8366rb
+device		etherswitch
+device		arswitch
 
 # read MSDOS formatted disks - USB
 #options		MSDOSFS
diff --git a/sys/mips/conf/AP121.hints b/sys/mips/conf/AP121.hints
index f6c3d14..940e871 100644
--- a/sys/mips/conf/AP121.hints
+++ b/sys/mips/conf/AP121.hints
@@ -3,21 +3,28 @@
 #
 # $FreeBSD$
 
-# Hard-code the PHY for now, until there's switch phy support.
-# hint.arge.0.phymask=0x000c
-hint.arge.0.phymask=0x0000
-hint.arge.0.media=1000
-hint.arge.0.fduplex=1
-# Where is the MAC address stored in flash for this particular unit.
-hint.arge.0.eeprommac=0x1f01fc00
-
-# This isn't used, but configure it anyway.
-# This should eventually just not be configured, but the if then
-# needs to be properly disabled or spurious interrupts occur.
-hint.arge.1.phymask=0x0
-
-# Where the ART is
-# hint.ath.0.eepromaddr=0x1fff1000
+# mdiobus on arge1
+hint.argemdio.0.at="nexus0"
+hint.argemdio.0.maddr=0x1a000000
+hint.argemdio.0.msize=0x1000
+hint.argemdio.0.order=0
+
+# Embedded Atheros Switch
+hint.arswitch.0.at="mdio0"
+hint.arswitch.0.is_7240=1
+hint.arswitch.0.numphys=4
+hint.arswitch.0.phy4cpu=1	# phy 4 is a "CPU" separate PHY
+hint.arswitch.0.is_rgmii=0
+hint.arswitch.0.is_gmii=1	# arge1 <-> switch PHY is GMII
+
+# arge0 - MII, autoneg, phy(4)
+hint.arge.0.phymask=0x10	# PHY4
+hint.arge.0.mdio=mdioproxy1	# .. off of the switch mdiobus
+
+# arge1 - GMII, 1000/full
+hint.arge.1.phymask=0x0		# No directly mapped PHYs
+hint.arge.1.media=1000
+hint.arge.1.fduplex=1
 
 # The AP121 4MB flash layout:
 #
@@ -114,17 +121,3 @@ hint.gpio.0.pinmask=0x0
 #hint.gpioled.3.at="gpiobus0"
 #hint.gpioled.3.name="wlan"
 #hint.gpioled.3.pins=0x0200
-
-# GPIO I2C bus
-#hint.gpioiic.0.at="gpiobus0"
-#hint.gpioiic.0.pins=0xc0000
-#hint.gpioiic.0.scl=1
-#hint.gpioiic.0.sda=0
-
-# I2C bus
-# Don't be strict about I2C protocol - the relaxed semantics are required
-# by the realtek switch PHY.
-# hint.iicbus.0.strict=0
-
-# Bit bang bus - override default delay
-#hint.iicbb.0.udelay=3