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author | jchandra <jchandra@FreeBSD.org> | 2011-09-05 10:45:29 +0000 |
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committer | jchandra <jchandra@FreeBSD.org> | 2011-09-05 10:45:29 +0000 |
commit | 566ec163bd941bb5c3387c736651a924e9048110 (patch) | |
tree | 7989173ba2dfac9cf472373f9095dd74f8688618 /sys/mips/nlm/xlp.h | |
parent | cb24e9343dfdd2c90611cefacb0016af3e769349 (diff) | |
download | FreeBSD-src-566ec163bd941bb5c3387c736651a924e9048110.zip FreeBSD-src-566ec163bd941bb5c3387c736651a924e9048110.tar.gz |
MIPS XLP platform code update.
* Update the hardware access register definitions and functions to bring
them in line with other Netlogic software.
* Update the platform bus to use PCI even for on-chip devices. Add a dummy
PCI driver to ignore on-chip devices which do not need driver.
* Provide memory and IRQ resource allocation code for on-chip devices
which cannot get it from PCI config.
* add support for on-chip PCI and USB interfaces.
* update conf files, enable pci and retain old MAXCPU until we can support
>32 cpus.
Approved by: re(kib), jmallett
Diffstat (limited to 'sys/mips/nlm/xlp.h')
-rw-r--r-- | sys/mips/nlm/xlp.h | 114 |
1 files changed, 56 insertions, 58 deletions
diff --git a/sys/mips/nlm/xlp.h b/sys/mips/nlm/xlp.h index 5c79aaf..b400891 100644 --- a/sys/mips/nlm/xlp.h +++ b/sys/mips/nlm/xlp.h @@ -25,25 +25,25 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * + * NETLOGIC_BSD * $FreeBSD$ - * NETLOGIC_BSD */ + */ #ifndef __NLM_XLP_H__ #define __NLM_XLP_H__ #include <mips/nlm/hal/pic.h> -#define XLP_PIC_IRT_UART0_IRQ 9 -#define XLP_PIC_IRT_UART1_IRQ 10 - -#define XLP_PIC_IRT_PCIE0_IRQ 11 -#define XLP_PIC_IRT_PCIE1_IRQ 12 -#define XLP_PIC_IRT_PCIE2_IRQ 13 -#define XLP_PIC_IRT_PCIE3_IRQ 14 +#define PIC_UART_0_IRQ 9 +#define PIC_UART_1_IRQ 10 -#define XLP_PIC_IRT_EHCI0_IRQ 39 -#define XLP_PIC_IRT_EHCI1_IRQ 42 -#define XLP_PIC_IRT_MMC_IRQ 43 +#define PIC_PCIE_0_IRQ 11 +#define PIC_PCIE_1_IRQ 12 +#define PIC_PCIE_2_IRQ 13 +#define PIC_PCIE_3_IRQ 14 +#define PIC_EHCI_0_IRQ 39 +#define PIC_EHCI_1_IRQ 42 +#define PIC_MMC_IRQ 43 #ifndef LOCORE /* @@ -59,30 +59,28 @@ extern int xlp_hwtid_to_cpuid[]; extern void xlp_enable_threads(int code); #endif -extern uint64_t xlp_pic_base; /* TODO just for node 0 now */ - static __inline__ int xlp_irt_to_irq(int irt) { switch (irt) { - case XLP_PIC_IRT_MMC_INDEX : - return XLP_PIC_IRT_MMC_IRQ; - case XLP_PIC_IRT_EHCI0_INDEX : - return XLP_PIC_IRT_EHCI0_IRQ; - case XLP_PIC_IRT_EHCI1_INDEX : - return XLP_PIC_IRT_EHCI1_IRQ; - case XLP_PIC_IRT_UART0_INDEX : - return XLP_PIC_IRT_UART0_IRQ; - case XLP_PIC_IRT_UART1_INDEX : - return XLP_PIC_IRT_UART1_IRQ; - case XLP_PIC_IRT_PCIE_LINK0_INDEX : - return XLP_PIC_IRT_PCIE0_IRQ; - case XLP_PIC_IRT_PCIE_LINK1_INDEX : - return XLP_PIC_IRT_PCIE1_IRQ; - case XLP_PIC_IRT_PCIE_LINK2_INDEX : - return XLP_PIC_IRT_PCIE2_IRQ; - case XLP_PIC_IRT_PCIE_LINK3_INDEX : - return XLP_PIC_IRT_PCIE3_IRQ; + case PIC_IRT_MMC_INDEX : + return PIC_MMC_IRQ; + case PIC_IRT_EHCI_0_INDEX : + return PIC_EHCI_0_IRQ; + case PIC_IRT_EHCI_1_INDEX : + return PIC_EHCI_1_IRQ; + case PIC_IRT_UART_0_INDEX : + return PIC_UART_0_IRQ; + case PIC_IRT_UART_1_INDEX : + return PIC_UART_1_IRQ; + case PIC_IRT_PCIE_LINK_0_INDEX : + return PIC_PCIE_0_IRQ; + case PIC_IRT_PCIE_LINK_1_INDEX : + return PIC_PCIE_1_IRQ; + case PIC_IRT_PCIE_LINK_2_INDEX : + return PIC_PCIE_2_IRQ; + case PIC_IRT_PCIE_LINK_3_INDEX : + return PIC_PCIE_3_IRQ; default: panic("Bad IRT %d\n", irt); } } @@ -91,24 +89,24 @@ static __inline__ int xlp_irq_to_irt(int irq) { switch (irq) { - case XLP_PIC_IRT_MMC_IRQ : - return XLP_PIC_IRT_MMC_INDEX; - case XLP_PIC_IRT_EHCI0_IRQ : - return XLP_PIC_IRT_EHCI0_INDEX; - case XLP_PIC_IRT_EHCI1_IRQ : - return XLP_PIC_IRT_EHCI1_INDEX; - case XLP_PIC_IRT_UART0_IRQ : - return XLP_PIC_IRT_UART0_INDEX; - case XLP_PIC_IRT_UART1_IRQ : - return XLP_PIC_IRT_UART1_INDEX; - case XLP_PIC_IRT_PCIE0_IRQ : - return XLP_PIC_IRT_PCIE_LINK0_INDEX; - case XLP_PIC_IRT_PCIE1_IRQ : - return XLP_PIC_IRT_PCIE_LINK1_INDEX; - case XLP_PIC_IRT_PCIE2_IRQ : - return XLP_PIC_IRT_PCIE_LINK2_INDEX; - case XLP_PIC_IRT_PCIE3_IRQ : - return XLP_PIC_IRT_PCIE_LINK3_INDEX; + case PIC_MMC_IRQ : + return PIC_IRT_MMC_INDEX; + case PIC_EHCI_0_IRQ : + return PIC_IRT_EHCI_0_INDEX; + case PIC_EHCI_1_IRQ : + return PIC_IRT_EHCI_1_INDEX; + case PIC_UART_0_IRQ : + return PIC_IRT_UART_0_INDEX; + case PIC_UART_1_IRQ : + return PIC_IRT_UART_1_INDEX; + case PIC_PCIE_0_IRQ : + return PIC_IRT_PCIE_LINK_0_INDEX; + case PIC_PCIE_1_IRQ : + return PIC_IRT_PCIE_LINK_1_INDEX; + case PIC_PCIE_2_IRQ : + return PIC_IRT_PCIE_LINK_2_INDEX; + case PIC_PCIE_3_IRQ : + return PIC_IRT_PCIE_LINK_3_INDEX; default: panic("Bad IRQ %d\n", irq); } } @@ -117,15 +115,15 @@ static __inline__ int xlp_irq_is_picintr(int irq) { switch (irq) { - case XLP_PIC_IRT_MMC_IRQ : return 1; - case XLP_PIC_IRT_EHCI0_IRQ : return 1; - case XLP_PIC_IRT_EHCI1_IRQ : return 1; - case XLP_PIC_IRT_UART0_IRQ : return 1; - case XLP_PIC_IRT_UART1_IRQ : return 1; - case XLP_PIC_IRT_PCIE0_IRQ : return 1; - case XLP_PIC_IRT_PCIE1_IRQ : return 1; - case XLP_PIC_IRT_PCIE2_IRQ : return 1; - case XLP_PIC_IRT_PCIE3_IRQ : return 1; + case PIC_MMC_IRQ : return 1; + case PIC_EHCI_0_IRQ : return 1; + case PIC_EHCI_1_IRQ : return 1; + case PIC_UART_0_IRQ : return 1; + case PIC_UART_1_IRQ : return 1; + case PIC_PCIE_0_IRQ : return 1; + case PIC_PCIE_1_IRQ : return 1; + case PIC_PCIE_2_IRQ : return 1; + case PIC_PCIE_3_IRQ : return 1; default: return 0; } } |