MIPS XLP platform code update.

* Update the hardware access register definitions and functions to bring
  them in line with other Netlogic software.
* Update the platform bus to use PCI even for on-chip devices. Add a dummy
  PCI driver to ignore on-chip devices which do not need driver.
* Provide memory and IRQ resource allocation code for on-chip devices
  which cannot get it from PCI config.
* add support for on-chip PCI and USB interfaces.
* update conf files, enable pci and retain old MAXCPU until we can support
  >32 cpus.

Approved by:	re(kib), jmallett

1 files changed, 154 insertions, 32 deletions

diff --git a/sys/mips/nlm/hal/cpucontrol.h b/sys/mips/nlm/hal/cpucontrol.h
index 0bc0f5b..715cd53 100644
--- a/sys/mips/nlm/hal/cpucontrol.h
+++ b/sys/mips/nlm/hal/cpucontrol.h
@@ -25,46 +25,168 @@
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGE.
  *
+ * NETLOGIC_BSD
  * $FreeBSD$
- * NETLOGIC_BSD */
+ */
 
-#ifndef __NLM_CPUCONTROL_H__
-#define __NLM_CPUCONTROL_H__
+#ifndef __NLM_HAL_CPUCONTROL_H__
+#define __NLM_HAL_CPUCONTROL_H__
 
-#define XLP_CPU_BLOCKID_IFU	0
-#define XLP_CPU_BLOCKID_ICU	1
+#define CPU_BLOCKID_IFU		0
+#define CPU_BLOCKID_ICU		1
+#define CPU_BLOCKID_IEU		2
+#define CPU_BLOCKID_LSU		3
+#define CPU_BLOCKID_MMU		4
+#define CPU_BLOCKID_PRF		5
+#define CPU_BLOCKID_SCH		7
+#define CPU_BLOCKID_SCU		8
+#define CPU_BLOCKID_FPU		9
+#define CPU_BLOCKID_MAP		10
 
-#define XLP_CPU_BLOCKID_IEU	2
-#define XLP_CPU_BLOCKID_LSU	3
-#define XLP_LSU_DEFEATURE	0x304
-#define XLP_LSU_CERRLOG_REGID 	0x09
+#define LSU_DEFEATURE		0x304
+#define LSU_CERRLOG_REGID	0x09
+#define SCHED_DEFEATURE		0x700
 
-#define XLP_CPU_BLOCKID_MMU	4
-#define XLP_CPU_BLOCKID_PRF	5
+/* Offsets of interest from the 'MAP' Block */
+#define MAP_THREADMODE			0x00
+#define MAP_EXT_EBASE_ENABLE		0x04
+#define MAP_CCDI_CONFIG			0x08
+#define MAP_THRD0_CCDI_STATUS		0x0c
+#define MAP_THRD1_CCDI_STATUS		0x10
+#define MAP_THRD2_CCDI_STATUS		0x14
+#define MAP_THRD3_CCDI_STATUS		0x18
+#define MAP_THRD0_DEBUG_MODE		0x1c
+#define MAP_THRD1_DEBUG_MODE		0x20
+#define MAP_THRD2_DEBUG_MODE		0x24
+#define MAP_THRD3_DEBUG_MODE		0x28
+#define MAP_MISC_STATE			0x60
+#define MAP_DEBUG_READ_CTL		0x64
+#define MAP_DEBUG_READ_REG0		0x68
+#define MAP_DEBUG_READ_REG1		0x6c
 
-#define XLP_CPU_BLOCKID_SCH	7
-#define XLP_SCHED_DEFEATURE	0x700
+#define MMU_SETUP		0x400
+#define MMU_LFSRSEED		0x401
+#define MMU_HPW_NUM_PAGE_LVL	0x410
+#define MMU_PGWKR_PGDBASE	0x411
+#define MMU_PGWKR_PGDSHFT	0x412
+#define MMU_PGWKR_PGDMASK	0x413
+#define MMU_PGWKR_PUDSHFT	0x414
+#define MMU_PGWKR_PUDMASK	0x415
+#define MMU_PGWKR_PMDSHFT	0x416
+#define MMU_PGWKR_PMDMASK	0x417
+#define MMU_PGWKR_PTESHFT	0x418
+#define MMU_PGWKR_PTEMASK	0x419
 
-#define XLP_CPU_BLOCKID_SCU	8
-#define XLP_CPU_BLOCKID_FPU	9
 
-#define XLP_CPU_BLOCKID_MAP	10
+#if !defined(LOCORE) && !defined(__ASSEMBLY__)
+#if defined(__mips_n64) || defined(__mips_n32)
+static __inline uint64_t
+nlm_mfcr(uint32_t reg)
+{
+	uint64_t res;
 
-/* Offsets of interest from the 'MAP' Block */
-#define XLP_BLKID_MAP_THREADMODE                    0x00
-#define XLP_BLKID_MAP_EXT_EBASE_ENABLE              0x04
-#define XLP_BLKID_MAP_CCDI_CONFIG                   0x08
-#define XLP_BLKID_MAP_THRD0_CCDI_STATUS             0x0c
-#define XLP_BLKID_MAP_THRD1_CCDI_STATUS             0x10
-#define XLP_BLKID_MAP_THRD2_CCDI_STATUS             0x14
-#define XLP_BLKID_MAP_THRD3_CCDI_STATUS             0x18
-#define XLP_BLKID_MAP_THRD0_DEBUG_MODE              0x1c
-#define XLP_BLKID_MAP_THRD1_DEBUG_MODE              0x20
-#define XLP_BLKID_MAP_THRD2_DEBUG_MODE              0x24
-#define XLP_BLKID_MAP_THRD3_DEBUG_MODE              0x28
-#define XLP_BLKID_MAP_MISC_STATE                    0x60
-#define XLP_BLKID_MAP_DEBUG_READ_CTL                0x64
-#define XLP_BLKID_MAP_DEBUG_READ_REG0               0x68
-#define XLP_BLKID_MAP_DEBUG_READ_REG1               0x6c
+	__asm__ __volatile__(
+	    ".set	push\n\t"
+	    ".set	noreorder\n\t"
+	    "move	$9, %1\n\t"
+	    ".word	0x71280018\n\t"  /* mfcr $8, $9 */
+	    "move	%0, $8\n\t"
+	    ".set	pop\n"
+	    : "=r" (res) : "r"(reg)
+	    : "$8", "$9"
+	);
+	return (res);
+}
+
+static __inline void
+nlm_mtcr(uint32_t reg, uint64_t value)
+{
+	__asm__ __volatile__(
+	    ".set	push\n\t"
+	    ".set	noreorder\n\t"
+	    "move	$8, %0\n"
+	    "move	$9, %1\n"
+	    ".word	0x71280019\n"    /* mtcr $8, $9  */
+	    ".set	pop\n"
+	    :
+	    : "r" (value), "r" (reg)
+	    : "$8", "$9"
+	);
+}
+
+#else /* !(defined(__mips_n64) || defined(__mips_n32)) */
+
+static __inline__  uint64_t
+nlm_mfcr(uint32_t reg)
+{
+	uint32_t hi, lo;
+
+	__asm__ __volatile__ (
+	    ".set push\n"
+	    ".set mips64\n"
+	    "move   $8, %2\n"
+	    ".word  0x71090018\n"
+	    "nop	\n"
+	    "dsra32 %0, $9, 0\n"
+	    "sll    %1, $9, 0\n"
+	    ".set pop\n"
+	    : "=r"(hi), "=r"(lo)
+	    : "r"(reg) : "$8", "$9");
+
+	return (((uint64_t)hi) << 32) | lo;
+}
+
+static __inline__  void
+nlm_mtcr(uint32_t reg, uint64_t val)
+{
+	uint32_t hi, lo;
+
+	hi = val >> 32;
+	lo = val & 0xffffffff;
+
+	__asm__ __volatile__ (
+	    ".set push\n"
+	    ".set mips64\n"
+	    "move   $9, %0\n"
+	    "dsll32 $9, %1, 0\n"
+	    "dsll32 $8, %0, 0\n"
+	    "dsrl32 $9, $9, 0\n"
+	    "or     $9, $9, $8\n"
+	    "move   $8, %2\n"
+	    ".word  0x71090019\n"
+	    "nop	\n"
+	    ".set pop\n"
+	    : :"r"(hi), "r"(lo), "r"(reg)
+	    : "$8", "$9");
+}
+#endif /* (defined(__mips_n64) || defined(__mips_n32)) */
+
+/* hashindex_en = 1 to enable hash mode, hashindex_en=0 to disable
+ * global_mode = 1 to enable global mode, global_mode=0 to disable
+ * clk_gating = 0 to enable clock gating, clk_gating=1 to disable
+ */
+static __inline__ void nlm_mmu_setup(int hashindex_en, int global_mode,
+		int clk_gating)
+{
+	uint32_t mmusetup = 0;
+
+	mmusetup |= (hashindex_en << 13);
+	mmusetup |= (clk_gating << 3);
+	mmusetup |= (global_mode << 0);
+	nlm_mtcr(MMU_SETUP, mmusetup);
+}
+
+static __inline__ void nlm_mmu_lfsr_seed (int thr0_seed, int thr1_seed,
+		int thr2_seed, int thr3_seed)
+{
+	uint32_t seed = nlm_mfcr(MMU_LFSRSEED);
+
+	seed |= ((thr3_seed & 0x7f) << 23);
+	seed |= ((thr2_seed & 0x7f) << 16);
+	seed |= ((thr1_seed & 0x7f) << 7);
+	seed |= ((thr0_seed & 0x7f) << 0);
+	nlm_mtcr(MMU_LFSRSEED, seed);
+}
 
+#endif /* __ASSEMBLY__ */
 #endif /* __NLM_CPUCONTROL_H__ */