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authoradrian <adrian@FreeBSD.org>2012-04-20 08:26:05 +0000
committeradrian <adrian@FreeBSD.org>2012-04-20 08:26:05 +0000
commit6152dc39f23cf9b5f8db831ea0d2de2e59e9feea (patch)
treeba57b3f3aab8e5919d290c7481fe4840bc6a74f4 /sys/mips/atheros/files.ar71xx
parentd9895ac1fe988335e2619f56d942d954d835bb07 (diff)
downloadFreeBSD-src-6152dc39f23cf9b5f8db831ea0d2de2e59e9feea.zip
FreeBSD-src-6152dc39f23cf9b5f8db831ea0d2de2e59e9feea.tar.gz
Introduce the matching PCI ath(4) fixup code from ar71xx_pci into
ar724x_pci.c. * Move out the code which populates the firmware into ar71xx_fixup.c * Shuffle around the ar724x fixup code to match what the ar71xx fixup code does. I've validated this on an AR7240 with AR9285 on-board NIC. It doesn't yet load, as the AR9285 EEPROM code needs to be made "flash aware." TODO: * Validate that I haven't broken AR71xx * Test AR9285/AR9287 onboard NICs, complete with EEPROM code changes * Port over the needed BAR hacks for AR7240, AR7241 and AR7242 from Linux OpenWRT. The current WAR has only been tested on the AR7240 and I'm not sure the way the BAR register is treated is "right". The "fixup" method here is right when setting the BAR for local access - ie, the BAR address is either 0xffff (AR7240) or 0x1000ffff (AR7241/AR7242), but the ath9k-fixup.c code (Linux OpenWRT) does this when setting the initial "fixup" BAR. It then restores the original BAR. I'll have to read the ar724x PCI bus glue to see what other special cases await.
Diffstat (limited to 'sys/mips/atheros/files.ar71xx')
-rw-r--r--sys/mips/atheros/files.ar71xx1
1 files changed, 1 insertions, 0 deletions
diff --git a/sys/mips/atheros/files.ar71xx b/sys/mips/atheros/files.ar71xx
index 86de7f1..cd090db 100644
--- a/sys/mips/atheros/files.ar71xx
+++ b/sys/mips/atheros/files.ar71xx
@@ -21,5 +21,6 @@ mips/atheros/ar71xx_setup.c standard
mips/atheros/ar71xx_chip.c standard
mips/atheros/ar724x_chip.c standard
mips/atheros/ar91xx_chip.c standard
+mips/atheros/ar71xx_fixup.c optional ar71xx_ath_eeprom
dev/hwpmc/hwpmc_mips24k.c optional hwpmc
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