Reshuffle all of the DDR flush operations into a single switch/mux,

and start teaching subsystems about it.

The Atheros MIPS platforms don't guarantee any kind of FIFO consistency
with interrupts in hardware.  So software needs to do a flush when it
receives an interrupt and before it calls the interrupt handler.

There are new ones for the QCA934x and QCA955x, so do a few things:

* Get rid of the individual ones (for ethernet and IP2);
* Create a mux and enum listing all the variations on DDR flushes;
* replace the uses of IP2 with the relevant one (which will typically
  be "PCI" here);
* call the USB DDR flush before calling the real USB interrupt handlers;
* call the ethernet one upon receiving an interrupt that's for us,
  rather than never calling it during operation.

Tested:

* QCA9558 (TP-Link archer c7 v2)
* AR9331 (Carambola 2)

TODO:

* PCI, USB, ethernet, etc need to do a double-check to see if the
  interrupt was truely for them before doing the DDR.  For now I
  prefer "correct" over "fast".

1 files changed, 2 insertions, 2 deletions

diff --git a/sys/mips/atheros/ar71xx_pci.c b/sys/mips/atheros/ar71xx_pci.c
index 476dba2..7ef0e155 100644
--- a/sys/mips/atheros/ar71xx_pci.c
+++ b/sys/mips/atheros/ar71xx_pci.c
@@ -637,8 +637,8 @@ ar71xx_pci_intr(void *arg)
 				continue;
 			}
 
-			/* Flush DDR FIFO for IP2 */
-			ar71xx_device_ddr_flush_ip2();
+			/* Flush DDR FIFO for PCI/PCIe */
+			ar71xx_device_flush_ddr(AR71XX_CPU_DDR_FLUSH_PCIE);
 
 			/* TODO: frame instead of NULL? */
 			intr_event_handle(event, NULL);