Some code churn:

o   Eliminate IA64_PHYS_TO_RR6 and change all places where the macro is used
    by calling either bus_space_map() or pmap_mapdev().
o   Implement bus_space_map() in terms of pmap_mapdev() and implement
    bus_space_unmap() in terms of pmap_unmapdev().
o   Have ia64_pib hold the uncached virtual address of the processor interrupt
    block throughout the kernel's life and access the elements of the PIB
    through this structure pointer.

This is a non-functional change with the exception of using ia64_ld1() and
ia64_st8() to write to the PIB. We were still using assignments, for which
the compiler generates semaphore reads -- which cause undefined behaviour
for uncacheable memory. Note also that the memory barriers in ipi_send() are
critical for proper functioning.

With all the mapping of uncached memory done by pmap_mapdev(), we can keep
track of the translations and wire them in the CPU. This then eliminates
the need to reserve a whole region for uncached I/O and it eliminates
translation traps for device I/O accesses.

5 files changed, 26 insertions, 43 deletions

diff --git a/sys/ia64/include/bus.h b/sys/ia64/include/bus.h
index a2a02a0..bad4f85 100644
--- a/sys/ia64/include/bus.h
+++ b/sys/ia64/include/bus.h
@@ -132,28 +132,14 @@
 
 
 /*
- * Map a region of device bus space into CPU virtual address space.
+ * Map and unmap a region of device bus space into CPU virtual address space.
  */
-static __inline int
-bus_space_map(bus_space_tag_t bst, bus_addr_t addr, bus_size_t size __unused,
-    int flags __unused, bus_space_handle_t *bshp)
-{
-
-	*bshp = (__predict_false(bst == IA64_BUS_SPACE_IO))
-	    ? addr : IA64_PHYS_TO_RR6(addr);
-	return (0);
-}
-
-
-/*
- * Unmap a region of device bus space.
- */
-static __inline void
-bus_space_unmap(bus_space_tag_t bst __unused, bus_space_handle_t bsh __unused,
-    bus_size_t size __unused)
-{
-}
+int
+bus_space_map(bus_space_tag_t, bus_addr_t, bus_size_t, int,
+    bus_space_handle_t *);
 
+void
+bus_space_unmap(bus_space_tag_t, bus_space_handle_t, bus_size_t size);
 
 /*
  * Get a new handle for a subregion of an already-mapped area of bus space.
diff --git a/sys/ia64/include/intr.h b/sys/ia64/include/intr.h
index 7d59ef2..8651fda 100644
--- a/sys/ia64/include/intr.h
+++ b/sys/ia64/include/intr.h
@@ -1,4 +1,5 @@
 /*-
+ * Copyright (c) 2007-2010 Marcel Moolenaar
  * Copyright (c) 1998 Doug Rabson
  * All rights reserved.
  *
@@ -27,26 +28,23 @@
  */
 
 #ifndef _MACHINE_INTR_H_
-#define _MACHINE_INTR_H_
+#define	_MACHINE_INTR_H_
 
 /*
  * Layout of the Processor Interrupt Block.
  */
-struct ia64_interrupt_block
+struct ia64_pib
 {
-	u_int64_t	ib_ipi[0x20000];	/* 1Mb of IPI interrupts */
-	u_int8_t	ib_reserved1[0xe0000];
-	u_int8_t	ib_inta;		/* Generate INTA cycle */
-	u_int8_t	ib_reserved2[7];
-	u_int8_t	ib_xtp;			/* XTP cycle */
-	u_int8_t	ib_reserved3[7];
-	u_int8_t	ib_reserved4[0x1fff0];
+	uint64_t	ib_ipi[65536][2];	/* 64K-way IPIs (1MB area). */
+	uint8_t		_rsvd1[0xe0000];
+	uint8_t		ib_inta;		/* Generate INTA cycle. */
+	uint8_t		_rsvd2[7];
+	uint8_t		ib_xtp;			/* External Task Priority. */
+	uint8_t		_rsvd3[7];
+	uint8_t		_rsvd4[0x1fff0];
 };
 
-extern u_int64_t ia64_lapic_address;
-
-#define IA64_INTERRUPT_BLOCK	\
-	(struct ia64_interrupt_block *)IA64_PHYS_TO_RR6(ia64_lapic_address)
+extern struct ia64_pib *ia64_pib;
 
 int ia64_setup_intr(const char *name, int irq, driver_filter_t filter,
     driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep);
diff --git a/sys/ia64/include/md_var.h b/sys/ia64/include/md_var.h
index 7fdcb2d..9a2f92a 100644
--- a/sys/ia64/include/md_var.h
+++ b/sys/ia64/include/md_var.h
@@ -49,7 +49,7 @@ struct ia64_fdesc {
 #define	IA64_CFM_RRB_FR(x)	(((x) >> 25) & 0x7f)
 #define	IA64_CFM_RRB_PR(x)	(((x) >> 32) & 0x3f)
 
-/* Concenience function (inline) to adjust backingstore pointers. */
+/* Convenience function (inline) to adjust backingstore pointers. */
 static __inline uint64_t
 ia64_bsp_adjust(uint64_t bsp, int nslots)
 {
@@ -60,22 +60,22 @@ ia64_bsp_adjust(uint64_t bsp, int nslots)
 
 #ifdef _KERNEL
 
-extern	char	sigcode[];
-extern	char	esigcode[];
-extern	int	szsigcode;
-extern	long	Maxmem;
-
 struct _special;
-struct fpreg;
-struct reg;
 struct thread;
 struct trapframe;
 
+/*
+ * Return value from ia64_init. Describes stack to switch to.
+ */
 struct ia64_init_return {
 	uint64_t	bspstore;
 	uint64_t	sp;
 };
 
+extern uint64_t ia64_lapic_addr;
+
+extern long Maxmem;
+
 void	busdma_swi(void);
 int	copyout_regstack(struct thread *, uint64_t *, uint64_t *);
 void	cpu_mp_add(u_int, u_int, u_int);
diff --git a/sys/ia64/include/pmap.h b/sys/ia64/include/pmap.h
index f878d27..e40d647 100644
--- a/sys/ia64/include/pmap.h
+++ b/sys/ia64/include/pmap.h
@@ -132,7 +132,7 @@ vm_paddr_t pmap_kextract(vm_offset_t va);
 void	pmap_kremove(vm_offset_t);
 void	pmap_setdevram(unsigned long long basea, vm_offset_t sizea);
 int	pmap_uses_prom_console(void);
-void	*pmap_mapdev(vm_offset_t, vm_size_t);
+void	*pmap_mapdev(vm_paddr_t, vm_size_t);
 void	pmap_unmapdev(vm_offset_t, vm_size_t);
 unsigned *pmap_pte(pmap_t, vm_offset_t) __pure2;
 void	pmap_set_opt	(unsigned *);
diff --git a/sys/ia64/include/vmparam.h b/sys/ia64/include/vmparam.h
index 9e65ea8..e040e9a 100644
--- a/sys/ia64/include/vmparam.h
+++ b/sys/ia64/include/vmparam.h
@@ -132,7 +132,6 @@
 #define IA64_RR_BASE(n)         (((u_int64_t) (n)) << 61)
 #define IA64_RR_MASK(x)         ((x) & ((1L << 61) - 1))
 
-#define IA64_PHYS_TO_RR6(x)     ((x) | IA64_RR_BASE(6))
 #define IA64_PHYS_TO_RR7(x)     ((x) | IA64_RR_BASE(7))
 
 /*