Switch to C99 exact-width types.

5 files changed, 77 insertions, 78 deletions

diff --git a/sys/ia64/include/ia64_cpu.h b/sys/ia64/include/ia64_cpu.h
index 0a5a115..d75fb1e 100644
--- a/sys/ia64/include/ia64_cpu.h
+++ b/sys/ia64/include/ia64_cpu.h
@@ -192,13 +192,13 @@ ia64_mf_a(void)
  * Flush Cache.
  */
 static __inline void
-ia64_fc(u_int64_t va)
+ia64_fc(uint64_t va)
 {
 	__asm __volatile("fc %0" :: "r"(va));
 }
 
 static __inline void
-ia64_fc_i(u_int64_t va)
+ia64_fc_i(uint64_t va)
 {
 	__asm __volatile("fc.i %0" :: "r"(va));
 }
@@ -215,10 +215,10 @@ ia64_sync_i(void)
 /*
  * Calculate address in VHPT for va.
  */
-static __inline u_int64_t
-ia64_thash(u_int64_t va)
+static __inline uint64_t
+ia64_thash(uint64_t va)
 {
-	u_int64_t result;
+	uint64_t result;
 	__asm __volatile("thash %0=%1" : "=r" (result) : "r" (va));
 	return result;
 }
@@ -226,10 +226,10 @@ ia64_thash(u_int64_t va)
 /*
  * Calculate VHPT tag for va.
  */
-static __inline u_int64_t
-ia64_ttag(u_int64_t va)
+static __inline uint64_t
+ia64_ttag(uint64_t va)
 {
-	u_int64_t result;
+	uint64_t result;
 	__asm __volatile("ttag %0=%1" : "=r" (result) : "r" (va));
 	return result;
 }
@@ -237,10 +237,10 @@ ia64_ttag(u_int64_t va)
 /*
  * Convert virtual address to physical.
  */
-static __inline u_int64_t
-ia64_tpa(u_int64_t va)
+static __inline uint64_t
+ia64_tpa(uint64_t va)
 {
-	u_int64_t result;
+	uint64_t result;
 	__asm __volatile("tpa %0=%1" : "=r" (result) : "r" (va));
 	return result;
 }
@@ -249,7 +249,7 @@ ia64_tpa(u_int64_t va)
  * Generate a ptc.e instruction.
  */
 static __inline void
-ia64_ptc_e(u_int64_t v)
+ia64_ptc_e(uint64_t v)
 {
 	__asm __volatile("ptc.e %0;; srlz.i;;" :: "r"(v));
 }
@@ -258,7 +258,7 @@ ia64_ptc_e(u_int64_t v)
  * Generate a ptc.g instruction.
  */
 static __inline void
-ia64_ptc_g(u_int64_t va, u_int64_t log2size)
+ia64_ptc_g(uint64_t va, uint64_t log2size)
 {
 	__asm __volatile("ptc.g %0,%1;; srlz.i;;" :: "r"(va), "r"(log2size));
 }
@@ -267,7 +267,7 @@ ia64_ptc_g(u_int64_t va, u_int64_t log2size)
  * Generate a ptc.ga instruction.
  */
 static __inline void
-ia64_ptc_ga(u_int64_t va, u_int64_t log2size)
+ia64_ptc_ga(uint64_t va, uint64_t log2size)
 {
 	__asm __volatile("ptc.ga %0,%1;; srlz.i;;" :: "r"(va), "r"(log2size));
 }
@@ -276,7 +276,7 @@ ia64_ptc_ga(u_int64_t va, u_int64_t log2size)
  * Generate a ptc.l instruction.
  */
 static __inline void
-ia64_ptc_l(u_int64_t va, u_int64_t log2size)
+ia64_ptc_l(uint64_t va, uint64_t log2size)
 {
 	__asm __volatile("ptc.l %0,%1;; srlz.i;;" :: "r"(va), "r"(log2size));
 }
@@ -352,10 +352,10 @@ ia64_st8(uint64_t *p, uint64_t v)
 /*
  * Read the value of psr.
  */
-static __inline u_int64_t
+static __inline uint64_t
 ia64_get_psr(void)
 {
-	u_int64_t result;
+	uint64_t result;
 	__asm __volatile("mov %0=psr;;" : "=r" (result));
 	return result;
 }
@@ -366,16 +366,16 @@ ia64_get_psr(void)
 
 #define IA64_AR(name)						\
 								\
-static __inline u_int64_t					\
+static __inline uint64_t					\
 ia64_get_##name(void)						\
 {								\
-	u_int64_t result;					\
+	uint64_t result;					\
 	__asm __volatile("mov %0=ar." #name : "=r" (result));	\
 	return result;						\
 }								\
 								\
 static __inline void						\
-ia64_set_##name(u_int64_t v)					\
+ia64_set_##name(uint64_t v)					\
 {								\
 	__asm __volatile("mov ar." #name "=%0;;" :: "r" (v));	\
 }
@@ -422,16 +422,16 @@ IA64_AR(ec)
 
 #define IA64_CR(name)						\
 								\
-static __inline u_int64_t					\
+static __inline uint64_t					\
 ia64_get_##name(void)						\
 {								\
-	u_int64_t result;					\
+	uint64_t result;					\
 	__asm __volatile("mov %0=cr." #name : "=r" (result));	\
 	return result;						\
 }								\
 								\
 static __inline void						\
-ia64_set_##name(u_int64_t v)					\
+ia64_set_##name(uint64_t v)					\
 {								\
 	__asm __volatile("mov cr." #name "=%0;;" :: "r" (v));	\
 }
@@ -472,7 +472,7 @@ IA64_CR(lrr1)
  * Write a region register.
  */
 static __inline void
-ia64_set_rr(u_int64_t rrbase, u_int64_t v)
+ia64_set_rr(uint64_t rrbase, uint64_t v)
 {
 	__asm __volatile("mov rr[%0]=%1"
 			 :: "r"(rrbase), "r"(v) : "memory");
@@ -481,10 +481,10 @@ ia64_set_rr(u_int64_t rrbase, u_int64_t v)
 /*
  * Read a CPUID register.
  */
-static __inline u_int64_t
+static __inline uint64_t
 ia64_get_cpuid(int i)
 {
-	u_int64_t result;
+	uint64_t result;
 	__asm __volatile("mov %0=cpuid[%1]"
 			 : "=r" (result) : "r"(i));
 	return result;
diff --git a/sys/ia64/include/pmap.h b/sys/ia64/include/pmap.h
index ff059fd..31418b6 100644
--- a/sys/ia64/include/pmap.h
+++ b/sys/ia64/include/pmap.h
@@ -75,7 +75,7 @@ struct md_page {
 struct pmap {
 	struct mtx		pm_mtx;
 	TAILQ_HEAD(,pv_entry)	pm_pvlist;	/* list of mappings in pmap */
-	u_int32_t		pm_rid[5];	/* base RID for pmap */
+	uint32_t		pm_rid[5];	/* base RID for pmap */
 	struct pmap_statistics	pm_stats;	/* pmap statistics */
 	uint32_t		pm_gen_count;	/* generation count (pmap lock dropped) */
 	u_int			pm_retries;
diff --git a/sys/ia64/include/runq.h b/sys/ia64/include/runq.h
index f5189a1..c2486d1 100644
--- a/sys/ia64/include/runq.h
+++ b/sys/ia64/include/runq.h
@@ -41,12 +41,12 @@
 /*
  * Type of run queue status word.
  */
-typedef	u_int64_t	rqb_word_t;
+typedef	uint64_t	rqb_word_t;
 
-static __inline u_int64_t
-__popcnt(u_int64_t bits)
+static __inline uint64_t
+__popcnt(uint64_t bits)
 {
-        u_int64_t result;
+        uint64_t result;
 
 	__asm __volatile("popcnt %0=%1" : "=r" (result) : "r" (bits));
 	return result;
diff --git a/sys/ia64/include/sal.h b/sys/ia64/include/sal.h
index 759cc9f..4857464 100644
--- a/sys/ia64/include/sal.h
+++ b/sys/ia64/include/sal.h
@@ -32,68 +32,68 @@
 struct sal_system_table {
 	char		sal_signature[4];
 #define	SAL_SIGNATURE	"SST_"
-	u_int32_t	sal_length;
-	u_int8_t	sal_rev[2];
-	u_int16_t	sal_entry_count;
-	u_int8_t	sal_checksum;
-	u_int8_t	sal_reserved1[7];
-	u_int8_t	sal_a_version[2];
-	u_int8_t	sal_b_version[2];
+	uint32_t	sal_length;
+	uint8_t		sal_rev[2];
+	uint16_t	sal_entry_count;
+	uint8_t		sal_checksum;
+	uint8_t		sal_reserved1[7];
+	uint8_t		sal_a_version[2];
+	uint8_t		sal_b_version[2];
 	char		sal_oem_id[32];
 	char		sal_product_id[32];
-	u_int8_t	sal_reserved2[8];
+	uint8_t		sal_reserved2[8];
 };
 
 struct sal_entrypoint_descriptor {
-	u_int8_t	sale_type;	/* == 0 */
-	u_int8_t	sale_reserved1[7];
-	u_int64_t	sale_pal_proc;
-	u_int64_t	sale_sal_proc;
-	u_int64_t	sale_sal_gp;
-	u_int8_t	sale_reserved2[16];
+	uint8_t		sale_type;	/* == 0 */
+	uint8_t		sale_reserved1[7];
+	uint64_t	sale_pal_proc;
+	uint64_t	sale_sal_proc;
+	uint64_t	sale_sal_gp;
+	uint8_t		sale_reserved2[16];
 };
 
 struct sal_memory_descriptor {
-	u_int8_t	sale_type;	/* == 1 */
-	u_int8_t	sale_need_virtual;
-	u_int8_t	sale_current_attribute;
-	u_int8_t	sale_access_rights;
-	u_int8_t	sale_supported_attributes;
-	u_int8_t	sale_reserved1;
-	u_int8_t	sale_memory_type[2];
-	u_int64_t	sale_physical_address;
-	u_int32_t	sale_length;
-	u_int8_t	sale_reserved2[12];
+	uint8_t		sale_type;	/* == 1 */
+	uint8_t		sale_need_virtual;
+	uint8_t		sale_current_attribute;
+	uint8_t		sale_access_rights;
+	uint8_t		sale_supported_attributes;
+	uint8_t		sale_reserved1;
+	uint8_t		sale_memory_type[2];
+	uint64_t	sale_physical_address;
+	uint32_t	sale_length;
+	uint8_t		sale_reserved2[12];
 };
 
 struct sal_platform_descriptor {
-	u_int8_t	sale_type;	/* == 2 */
-	u_int8_t	sale_features;
-	u_int8_t	sale_reserved[14];
+	uint8_t		sale_type;	/* == 2 */
+	uint8_t		sale_features;
+	uint8_t		sale_reserved[14];
 };
 
 struct sal_tr_descriptor {
-	u_int8_t	sale_type;	/* == 3 */
-	u_int8_t	sale_register_type;
-	u_int8_t	sale_register_number;
-	u_int8_t	sale_reserved1[5];
-	u_int64_t	sale_virtual_address;
-	u_int64_t	sale_page_size;
-	u_int8_t	sale_reserved2[8];
+	uint8_t		sale_type;	/* == 3 */
+	uint8_t		sale_register_type;
+	uint8_t		sale_register_number;
+	uint8_t		sale_reserved1[5];
+	uint64_t	sale_virtual_address;
+	uint64_t	sale_page_size;
+	uint8_t		sale_reserved2[8];
 };
 
 struct sal_ptc_cache_descriptor {
-	u_int8_t	sale_type;	/* == 4 */
-	u_int8_t	sale_reserved[3];
-	u_int32_t	sale_domains;
-	u_int64_t	sale_address;
+	uint8_t		sale_type;	/* == 4 */
+	uint8_t		sale_reserved[3];
+	uint32_t	sale_domains;
+	uint64_t	sale_address;
 };
 
 struct sal_ap_wakeup_descriptor {
-	u_int8_t	sale_type;	/* == 5 */
-	u_int8_t	sale_mechanism;
-	u_int8_t	sale_reserved[6];
-	u_int64_t	sale_vector;
+	uint8_t		sale_type;	/* == 5 */
+	uint8_t		sale_mechanism;
+	uint8_t		sale_reserved[6];
+	uint64_t	sale_vector;
 };
 
 /*
@@ -128,12 +128,11 @@ struct sal_ap_wakeup_descriptor {
 
 struct ia64_sal_result {
 	int64_t		sal_status;
-	u_int64_t	sal_result[3];
+	uint64_t	sal_result[3];
 };
 
-typedef struct ia64_sal_result sal_entry_t
-	(u_int64_t, u_int64_t, u_int64_t, u_int64_t,
-	 u_int64_t, u_int64_t, u_int64_t, u_int64_t);
+typedef struct ia64_sal_result sal_entry_t(uint64_t, uint64_t, uint64_t,
+    uint64_t, uint64_t, uint64_t, uint64_t, uint64_t);
 
 extern sal_entry_t *ia64_sal_entry;
 
diff --git a/sys/ia64/include/vmparam.h b/sys/ia64/include/vmparam.h
index e040e9a..2a0f061 100644
--- a/sys/ia64/include/vmparam.h
+++ b/sys/ia64/include/vmparam.h
@@ -129,7 +129,7 @@
 /*
  * Manipulating region bits of an address.
  */
-#define IA64_RR_BASE(n)         (((u_int64_t) (n)) << 61)
+#define IA64_RR_BASE(n)         (((uint64_t) (n)) << 61)
 #define IA64_RR_MASK(x)         ((x) & ((1L << 61) - 1))
 
 #define IA64_PHYS_TO_RR7(x)     ((x) | IA64_RR_BASE(7))