diff options
| author | imp <imp@FreeBSD.org> | 2014-09-04 20:48:16 +0000 |
|---|---|---|
| committer | imp <imp@FreeBSD.org> | 2014-09-04 20:48:16 +0000 |
| commit | e47626077f4efb90b2e9dd4b29f11ad783859bc1 (patch) | |
| tree | a6d994da0472b810a32fe252b54aa51b1bcb2626 /sys/gnu | |
| parent | 85476ebca219574af0a98734510231a227be59b7 (diff) | |
| parent | 61531e4eb16f2abfb991218c26fba5840d04f0f0 (diff) | |
| download | FreeBSD-src-e47626077f4efb90b2e9dd4b29f11ad783859bc1.zip FreeBSD-src-e47626077f4efb90b2e9dd4b29f11ad783859bc1.tar.gz | |
Update bindings to latest vendor branch representing 3.17-rc2 level of
Linux DTS API.
Diffstat (limited to 'sys/gnu')
68 files changed, 4836 insertions, 44 deletions
diff --git a/sys/gnu/dts/include/dt-bindings/clk/ti-dra7-atl.h b/sys/gnu/dts/include/dt-bindings/clk/ti-dra7-atl.h new file mode 100644 index 0000000..42dd416 --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clk/ti-dra7-atl.h @@ -0,0 +1,40 @@ +/* + * This header provides constants for DRA7 ATL (Audio Tracking Logic) + * + * The constants defined in this header are used in dts files + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * Peter Ujfalusi <peter.ujfalusi@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_DRA7_ATL_H +#define _DT_BINDINGS_CLK_DRA7_ATL_H + +#define DRA7_ATL_WS_MCASP1_FSR 0 +#define DRA7_ATL_WS_MCASP1_FSX 1 +#define DRA7_ATL_WS_MCASP2_FSR 2 +#define DRA7_ATL_WS_MCASP2_FSX 3 +#define DRA7_ATL_WS_MCASP3_FSX 4 +#define DRA7_ATL_WS_MCASP4_FSX 5 +#define DRA7_ATL_WS_MCASP5_FSX 6 +#define DRA7_ATL_WS_MCASP6_FSX 7 +#define DRA7_ATL_WS_MCASP7_FSX 8 +#define DRA7_ATL_WS_MCASP8_FSX 9 +#define DRA7_ATL_WS_MCASP8_AHCLKX 10 +#define DRA7_ATL_WS_XREF_CLK3 11 +#define DRA7_ATL_WS_XREF_CLK0 12 +#define DRA7_ATL_WS_XREF_CLK1 13 +#define DRA7_ATL_WS_XREF_CLK2 14 +#define DRA7_ATL_WS_OSC1_X1 15 + +#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/at91.h b/sys/gnu/dts/include/dt-bindings/clock/at91.h new file mode 100644 index 0000000..0b4cb99 --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/at91.h @@ -0,0 +1,22 @@ +/* + * This header provides constants for AT91 pmc status. + * + * The constants defined in this header are being used in dts. + * + * Licensed under GPLv2 or later. + */ + +#ifndef _DT_BINDINGS_CLK_AT91_H +#define _DT_BINDINGS_CLK_AT91_H + +#define AT91_PMC_MOSCS 0 /* MOSCS Flag */ +#define AT91_PMC_LOCKA 1 /* PLLA Lock */ +#define AT91_PMC_LOCKB 2 /* PLLB Lock */ +#define AT91_PMC_MCKRDY 3 /* Master Clock */ +#define AT91_PMC_LOCKU 6 /* UPLL Lock */ +#define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */ +#define AT91_PMC_MOSCSELS 16 /* Main Oscillator Selection */ +#define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */ +#define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */ + +#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/bcm21664.h b/sys/gnu/dts/include/dt-bindings/clock/bcm21664.h new file mode 100644 index 0000000..5a7f0e4 --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/bcm21664.h @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2013 Broadcom Corporation + * Copyright 2013 Linaro Limited + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CLOCK_BCM21664_H +#define _CLOCK_BCM21664_H + +/* + * This file defines the values used to specify clocks provided by + * the clock control units (CCUs) on Broadcom BCM21664 family SoCs. + */ + +/* bcm21664 CCU device tree "compatible" strings */ +#define BCM21664_DT_ROOT_CCU_COMPAT "brcm,bcm21664-root-ccu" +#define BCM21664_DT_AON_CCU_COMPAT "brcm,bcm21664-aon-ccu" +#define BCM21664_DT_MASTER_CCU_COMPAT "brcm,bcm21664-master-ccu" +#define BCM21664_DT_SLAVE_CCU_COMPAT "brcm,bcm21664-slave-ccu" + +/* root CCU clock ids */ + +#define BCM21664_ROOT_CCU_FRAC_1M 0 +#define BCM21664_ROOT_CCU_CLOCK_COUNT 1 + +/* aon CCU clock ids */ + +#define BCM21664_AON_CCU_HUB_TIMER 0 +#define BCM21664_AON_CCU_CLOCK_COUNT 1 + +/* master CCU clock ids */ + +#define BCM21664_MASTER_CCU_SDIO1 0 +#define BCM21664_MASTER_CCU_SDIO2 1 +#define BCM21664_MASTER_CCU_SDIO3 2 +#define BCM21664_MASTER_CCU_SDIO4 3 +#define BCM21664_MASTER_CCU_SDIO1_SLEEP 4 +#define BCM21664_MASTER_CCU_SDIO2_SLEEP 5 +#define BCM21664_MASTER_CCU_SDIO3_SLEEP 6 +#define BCM21664_MASTER_CCU_SDIO4_SLEEP 7 +#define BCM21664_MASTER_CCU_CLOCK_COUNT 8 + +/* slave CCU clock ids */ + +#define BCM21664_SLAVE_CCU_UARTB 0 +#define BCM21664_SLAVE_CCU_UARTB2 1 +#define BCM21664_SLAVE_CCU_UARTB3 2 +#define BCM21664_SLAVE_CCU_BSC1 3 +#define BCM21664_SLAVE_CCU_BSC2 4 +#define BCM21664_SLAVE_CCU_BSC3 5 +#define BCM21664_SLAVE_CCU_BSC4 6 +#define BCM21664_SLAVE_CCU_CLOCK_COUNT 7 + +#endif /* _CLOCK_BCM21664_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/bcm281xx.h b/sys/gnu/dts/include/dt-bindings/clock/bcm281xx.h new file mode 100644 index 0000000..a763460 --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/bcm281xx.h @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2013 Broadcom Corporation + * Copyright 2013 Linaro Limited + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CLOCK_BCM281XX_H +#define _CLOCK_BCM281XX_H + +/* + * This file defines the values used to specify clocks provided by + * the clock control units (CCUs) on Broadcom BCM281XX family SoCs. + */ + +/* + * These are the bcm281xx CCU device tree "compatible" strings. + * We're stuck with using "bcm11351" in the string because wild + * cards aren't allowed, and that name was the first one defined + * in this family of devices. + */ +#define BCM281XX_DT_ROOT_CCU_COMPAT "brcm,bcm11351-root-ccu" +#define BCM281XX_DT_AON_CCU_COMPAT "brcm,bcm11351-aon-ccu" +#define BCM281XX_DT_HUB_CCU_COMPAT "brcm,bcm11351-hub-ccu" +#define BCM281XX_DT_MASTER_CCU_COMPAT "brcm,bcm11351-master-ccu" +#define BCM281XX_DT_SLAVE_CCU_COMPAT "brcm,bcm11351-slave-ccu" + +/* root CCU clock ids */ + +#define BCM281XX_ROOT_CCU_FRAC_1M 0 +#define BCM281XX_ROOT_CCU_CLOCK_COUNT 1 + +/* aon CCU clock ids */ + +#define BCM281XX_AON_CCU_HUB_TIMER 0 +#define BCM281XX_AON_CCU_PMU_BSC 1 +#define BCM281XX_AON_CCU_PMU_BSC_VAR 2 +#define BCM281XX_AON_CCU_CLOCK_COUNT 3 + +/* hub CCU clock ids */ + +#define BCM281XX_HUB_CCU_TMON_1M 0 +#define BCM281XX_HUB_CCU_CLOCK_COUNT 1 + +/* master CCU clock ids */ + +#define BCM281XX_MASTER_CCU_SDIO1 0 +#define BCM281XX_MASTER_CCU_SDIO2 1 +#define BCM281XX_MASTER_CCU_SDIO3 2 +#define BCM281XX_MASTER_CCU_SDIO4 3 +#define BCM281XX_MASTER_CCU_USB_IC 4 +#define BCM281XX_MASTER_CCU_HSIC2_48M 5 +#define BCM281XX_MASTER_CCU_HSIC2_12M 6 +#define BCM281XX_MASTER_CCU_CLOCK_COUNT 7 + +/* slave CCU clock ids */ + +#define BCM281XX_SLAVE_CCU_UARTB 0 +#define BCM281XX_SLAVE_CCU_UARTB2 1 +#define BCM281XX_SLAVE_CCU_UARTB3 2 +#define BCM281XX_SLAVE_CCU_UARTB4 3 +#define BCM281XX_SLAVE_CCU_SSP0 4 +#define BCM281XX_SLAVE_CCU_SSP2 5 +#define BCM281XX_SLAVE_CCU_BSC1 6 +#define BCM281XX_SLAVE_CCU_BSC2 7 +#define BCM281XX_SLAVE_CCU_BSC3 8 +#define BCM281XX_SLAVE_CCU_PWM 9 +#define BCM281XX_SLAVE_CCU_CLOCK_COUNT 10 + +#endif /* _CLOCK_BCM281XX_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/berlin2.h b/sys/gnu/dts/include/dt-bindings/clock/berlin2.h new file mode 100644 index 0000000..0c30800 --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/berlin2.h @@ -0,0 +1,45 @@ +/* + * Berlin2 BG2/BG2CD clock tree IDs + */ + +#define CLKID_SYS 0 +#define CLKID_CPU 1 +#define CLKID_DRMFIGO 2 +#define CLKID_CFG 3 +#define CLKID_GFX 4 +#define CLKID_ZSP 5 +#define CLKID_PERIF 6 +#define CLKID_PCUBE 7 +#define CLKID_VSCOPE 8 +#define CLKID_NFC_ECC 9 +#define CLKID_VPP 10 +#define CLKID_APP 11 +#define CLKID_AUDIO0 12 +#define CLKID_AUDIO2 13 +#define CLKID_AUDIO3 14 +#define CLKID_AUDIO1 15 +#define CLKID_GFX3D_CORE 16 +#define CLKID_GFX3D_SYS 17 +#define CLKID_ARC 18 +#define CLKID_VIP 19 +#define CLKID_SDIO0XIN 20 +#define CLKID_SDIO1XIN 21 +#define CLKID_GFX3D_EXTRA 22 +#define CLKID_GC360 23 +#define CLKID_SDIO_DLLMST 24 +#define CLKID_GETH0 25 +#define CLKID_GETH1 26 +#define CLKID_SATA 27 +#define CLKID_AHBAPB 28 +#define CLKID_USB0 29 +#define CLKID_USB1 30 +#define CLKID_PBRIDGE 31 +#define CLKID_SDIO0 32 +#define CLKID_SDIO1 33 +#define CLKID_NFC 34 +#define CLKID_SMEMC 35 +#define CLKID_AUDIOHD 36 +#define CLKID_VIDEO0 37 +#define CLKID_VIDEO1 38 +#define CLKID_VIDEO2 39 +#define CLKID_TWD 40 diff --git a/sys/gnu/dts/include/dt-bindings/clock/berlin2q.h b/sys/gnu/dts/include/dt-bindings/clock/berlin2q.h new file mode 100644 index 0000000..287fc3b --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/berlin2q.h @@ -0,0 +1,31 @@ +/* + * Berlin2 BG2Q clock tree IDs + */ + +#define CLKID_SYS 0 +#define CLKID_DRMFIGO 1 +#define CLKID_CFG 2 +#define CLKID_GFX2D 3 +#define CLKID_ZSP 4 +#define CLKID_PERIF 5 +#define CLKID_PCUBE 6 +#define CLKID_VSCOPE 7 +#define CLKID_NFC_ECC 8 +#define CLKID_VPP 9 +#define CLKID_APP 10 +#define CLKID_SDIO0XIN 11 +#define CLKID_SDIO1XIN 12 +#define CLKID_GFX2DAXI 13 +#define CLKID_GETH0 14 +#define CLKID_SATA 15 +#define CLKID_AHBAPB 16 +#define CLKID_USB0 17 +#define CLKID_USB1 18 +#define CLKID_USB2 19 +#define CLKID_USB3 20 +#define CLKID_PBRIDGE 21 +#define CLKID_SDIO 22 +#define CLKID_NFC 23 +#define CLKID_SMEMC 24 +#define CLKID_PCIE 25 +#define CLKID_TWD 26 diff --git a/sys/gnu/dts/include/dt-bindings/clock/clps711x-clock.h b/sys/gnu/dts/include/dt-bindings/clock/clps711x-clock.h new file mode 100644 index 0000000..0c4c80b --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/clps711x-clock.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DT_BINDINGS_CLOCK_CLPS711X_H +#define __DT_BINDINGS_CLOCK_CLPS711X_H + +#define CLPS711X_CLK_DUMMY 0 +#define CLPS711X_CLK_CPU 1 +#define CLPS711X_CLK_BUS 2 +#define CLPS711X_CLK_PLL 3 +#define CLPS711X_CLK_TIMERREF 4 +#define CLPS711X_CLK_TIMER1 5 +#define CLPS711X_CLK_TIMER2 6 +#define CLPS711X_CLK_PWM 7 +#define CLPS711X_CLK_SPIREF 8 +#define CLPS711X_CLK_SPI 9 +#define CLPS711X_CLK_UART 10 +#define CLPS711X_CLK_TICK 11 +#define CLPS711X_CLK_MAX 12 + +#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/exynos-audss-clk.h b/sys/gnu/dts/include/dt-bindings/clock/exynos-audss-clk.h new file mode 100644 index 0000000..0ae6f5a --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/exynos-audss-clk.h @@ -0,0 +1,26 @@ +/* + * This header provides constants for Samsung audio subsystem + * clock controller. + * + * The constants defined in this header are being used in dts + * and exynos audss driver. + */ + +#ifndef _DT_BINDINGS_CLK_EXYNOS_AUDSS_H +#define _DT_BINDINGS_CLK_EXYNOS_AUDSS_H + +#define EXYNOS_MOUT_AUDSS 0 +#define EXYNOS_MOUT_I2S 1 +#define EXYNOS_DOUT_SRP 2 +#define EXYNOS_DOUT_AUD_BUS 3 +#define EXYNOS_DOUT_I2S 4 +#define EXYNOS_SRP_CLK 5 +#define EXYNOS_I2S_BUS 6 +#define EXYNOS_SCLK_I2S 7 +#define EXYNOS_PCM_BUS 8 +#define EXYNOS_SCLK_PCM 9 +#define EXYNOS_ADMA 10 + +#define EXYNOS_AUDSS_MAX_CLKS 11 + +#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/exynos3250.h b/sys/gnu/dts/include/dt-bindings/clock/exynos3250.h new file mode 100644 index 0000000..b535e9d --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/exynos3250.h @@ -0,0 +1,258 @@ +/* + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * Author: Tomasz Figa <t.figa@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Device Tree binding constants for Samsung Exynos3250 clock controllers. + */ + +#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H +#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H + +/* + * Let each exported clock get a unique index, which is used on DT-enabled + * platforms to lookup the clock from a clock specifier. These indices are + * therefore considered an ABI and so must not be changed. This implies + * that new clocks should be added either in free spaces between clock groups + * or at the end. + */ + + +/* + * Main CMU + */ + +#define CLK_OSCSEL 1 +#define CLK_FIN_PLL 2 +#define CLK_FOUT_APLL 3 +#define CLK_FOUT_VPLL 4 +#define CLK_FOUT_UPLL 5 +#define CLK_FOUT_MPLL 6 + +/* Muxes */ +#define CLK_MOUT_MPLL_USER_L 16 +#define CLK_MOUT_GDL 17 +#define CLK_MOUT_MPLL_USER_R 18 +#define CLK_MOUT_GDR 19 +#define CLK_MOUT_EBI 20 +#define CLK_MOUT_ACLK_200 21 +#define CLK_MOUT_ACLK_160 22 +#define CLK_MOUT_ACLK_100 23 +#define CLK_MOUT_ACLK_266_1 24 +#define CLK_MOUT_ACLK_266_0 25 +#define CLK_MOUT_ACLK_266 26 +#define CLK_MOUT_VPLL 27 +#define CLK_MOUT_EPLL_USER 28 +#define CLK_MOUT_EBI_1 29 +#define CLK_MOUT_UPLL 30 +#define CLK_MOUT_ACLK_400_MCUISP_SUB 31 +#define CLK_MOUT_MPLL 32 +#define CLK_MOUT_ACLK_400_MCUISP 33 +#define CLK_MOUT_VPLLSRC 34 +#define CLK_MOUT_CAM1 35 +#define CLK_MOUT_CAM_BLK 36 +#define CLK_MOUT_MFC 37 +#define CLK_MOUT_MFC_1 38 +#define CLK_MOUT_MFC_0 39 +#define CLK_MOUT_G3D 40 +#define CLK_MOUT_G3D_1 41 +#define CLK_MOUT_G3D_0 42 +#define CLK_MOUT_MIPI0 43 +#define CLK_MOUT_FIMD0 44 +#define CLK_MOUT_UART_ISP 45 +#define CLK_MOUT_SPI1_ISP 46 +#define CLK_MOUT_SPI0_ISP 47 +#define CLK_MOUT_TSADC 48 +#define CLK_MOUT_MMC1 49 +#define CLK_MOUT_MMC0 50 +#define CLK_MOUT_UART1 51 +#define CLK_MOUT_UART0 52 +#define CLK_MOUT_SPI1 53 +#define CLK_MOUT_SPI0 54 +#define CLK_MOUT_AUDIO 55 +#define CLK_MOUT_MPLL_USER_C 56 +#define CLK_MOUT_HPM 57 +#define CLK_MOUT_CORE 58 +#define CLK_MOUT_APLL 59 +#define CLK_MOUT_ACLK_266_SUB 60 + +/* Dividers */ +#define CLK_DIV_GPL 64 +#define CLK_DIV_GDL 65 +#define CLK_DIV_GPR 66 +#define CLK_DIV_GDR 67 +#define CLK_DIV_MPLL_PRE 68 +#define CLK_DIV_ACLK_400_MCUISP 69 +#define CLK_DIV_EBI 70 +#define CLK_DIV_ACLK_200 71 +#define CLK_DIV_ACLK_160 72 +#define CLK_DIV_ACLK_100 73 +#define CLK_DIV_ACLK_266 74 +#define CLK_DIV_CAM1 75 +#define CLK_DIV_CAM_BLK 76 +#define CLK_DIV_MFC 77 +#define CLK_DIV_G3D 78 +#define CLK_DIV_MIPI0_PRE 79 +#define CLK_DIV_MIPI0 80 +#define CLK_DIV_FIMD0 81 +#define CLK_DIV_UART_ISP 82 +#define CLK_DIV_SPI1_ISP_PRE 83 +#define CLK_DIV_SPI1_ISP 84 +#define CLK_DIV_SPI0_ISP_PRE 85 +#define CLK_DIV_SPI0_ISP 86 +#define CLK_DIV_TSADC_PRE 87 +#define CLK_DIV_TSADC 88 +#define CLK_DIV_MMC1_PRE 89 +#define CLK_DIV_MMC1 90 +#define CLK_DIV_MMC0_PRE 91 +#define CLK_DIV_MMC0 92 +#define CLK_DIV_UART1 93 +#define CLK_DIV_UART0 94 +#define CLK_DIV_SPI1_PRE 95 +#define CLK_DIV_SPI1 96 +#define CLK_DIV_SPI0_PRE 97 +#define CLK_DIV_SPI0 98 +#define CLK_DIV_PCM 99 +#define CLK_DIV_AUDIO 100 +#define CLK_DIV_I2S 101 +#define CLK_DIV_CORE2 102 +#define CLK_DIV_APLL 103 +#define CLK_DIV_PCLK_DBG 104 +#define CLK_DIV_ATB 105 +#define CLK_DIV_COREM 106 +#define CLK_DIV_CORE 107 +#define CLK_DIV_HPM 108 +#define CLK_DIV_COPY 109 + +/* Gates */ +#define CLK_ASYNC_G3D 128 +#define CLK_ASYNC_MFCL 129 +#define CLK_PPMULEFT 130 +#define CLK_GPIO_LEFT 131 +#define CLK_ASYNC_ISPMX 132 +#define CLK_ASYNC_FSYSD 133 +#define CLK_ASYNC_LCD0X 134 +#define CLK_ASYNC_CAMX 135 +#define CLK_PPMURIGHT 136 +#define CLK_GPIO_RIGHT 137 +#define CLK_MONOCNT 138 +#define CLK_TZPC6 139 +#define CLK_PROVISIONKEY1 140 +#define CLK_PROVISIONKEY0 141 +#define CLK_CMU_ISPPART 142 +#define CLK_TMU_APBIF 143 +#define CLK_KEYIF 144 +#define CLK_RTC 145 +#define CLK_WDT 146 +#define CLK_MCT 147 +#define CLK_SECKEY 148 +#define CLK_TZPC5 149 +#define CLK_TZPC4 150 +#define CLK_TZPC3 151 +#define CLK_TZPC2 152 +#define CLK_TZPC1 153 +#define CLK_TZPC0 154 +#define CLK_CMU_COREPART 155 +#define CLK_CMU_TOPPART 156 +#define CLK_PMU_APBIF 157 +#define CLK_SYSREG 158 +#define CLK_CHIP_ID 159 +#define CLK_QEJPEG 160 +#define CLK_PIXELASYNCM1 161 +#define CLK_PIXELASYNCM0 162 +#define CLK_PPMUCAMIF 163 +#define CLK_QEM2MSCALER 164 +#define CLK_QEGSCALER1 165 +#define CLK_QEGSCALER0 166 +#define CLK_SMMUJPEG 167 +#define CLK_SMMUM2M2SCALER 168 +#define CLK_SMMUGSCALER1 169 +#define CLK_SMMUGSCALER0 170 +#define CLK_JPEG 171 +#define CLK_M2MSCALER 172 +#define CLK_GSCALER1 173 +#define CLK_GSCALER0 174 +#define CLK_QEMFC 175 +#define CLK_PPMUMFC_L 176 +#define CLK_SMMUMFC_L 177 +#define CLK_MFC 178 +#define CLK_SMMUG3D 179 +#define CLK_QEG3D 180 +#define CLK_PPMUG3D 181 +#define CLK_G3D 182 +#define CLK_QE_CH1_LCD 183 +#define CLK_QE_CH0_LCD 184 +#define CLK_PPMULCD0 185 +#define CLK_SMMUFIMD0 186 +#define CLK_DSIM0 187 +#define CLK_FIMD0 188 +#define CLK_CAM1 189 +#define CLK_UART_ISP_TOP 190 +#define CLK_SPI1_ISP_TOP 191 +#define CLK_SPI0_ISP_TOP 192 +#define CLK_TSADC 193 +#define CLK_PPMUFILE 194 +#define CLK_USBOTG 195 +#define CLK_USBHOST 196 +#define CLK_SROMC 197 +#define CLK_SDMMC1 198 +#define CLK_SDMMC0 199 +#define CLK_PDMA1 200 +#define CLK_PDMA0 201 +#define CLK_PWM 202 +#define CLK_PCM 203 +#define CLK_I2S 204 +#define CLK_SPI1 205 +#define CLK_SPI0 206 +#define CLK_I2C7 207 +#define CLK_I2C6 208 +#define CLK_I2C5 209 +#define CLK_I2C4 210 +#define CLK_I2C3 211 +#define CLK_I2C2 212 +#define CLK_I2C1 213 +#define CLK_I2C0 214 +#define CLK_UART1 215 +#define CLK_UART0 216 +#define CLK_BLOCK_LCD 217 +#define CLK_BLOCK_G3D 218 +#define CLK_BLOCK_MFC 219 +#define CLK_BLOCK_CAM 220 +#define CLK_SMIES 221 + +/* Special clocks */ +#define CLK_SCLK_JPEG 224 +#define CLK_SCLK_M2MSCALER 225 +#define CLK_SCLK_GSCALER1 226 +#define CLK_SCLK_GSCALER0 227 +#define CLK_SCLK_MFC 228 +#define CLK_SCLK_G3D 229 +#define CLK_SCLK_MIPIDPHY2L 230 +#define CLK_SCLK_MIPI0 231 +#define CLK_SCLK_FIMD0 232 +#define CLK_SCLK_CAM1 233 +#define CLK_SCLK_UART_ISP 234 +#define CLK_SCLK_SPI1_ISP 235 +#define CLK_SCLK_SPI0_ISP 236 +#define CLK_SCLK_UPLL 237 +#define CLK_SCLK_TSADC 238 +#define CLK_SCLK_EBI 239 +#define CLK_SCLK_MMC1 240 +#define CLK_SCLK_MMC0 241 +#define CLK_SCLK_I2S 242 +#define CLK_SCLK_PCM 243 +#define CLK_SCLK_SPI1 244 +#define CLK_SCLK_SPI0 245 +#define CLK_SCLK_UART1 246 +#define CLK_SCLK_UART0 247 + +/* + * Total number of clocks of main CMU. + * NOTE: Must be equal to last clock ID increased by one. + */ +#define CLK_NR_CLKS 248 + +#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/exynos4.h b/sys/gnu/dts/include/dt-bindings/clock/exynos4.h index 75aff33..459bd2b 100644 --- a/sys/gnu/dts/include/dt-bindings/clock/exynos4.h +++ b/sys/gnu/dts/include/dt-bindings/clock/exynos4.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * Author: Andrzej Haja <a.hajda@samsung.com> + * Author: Andrzej Hajda <a.hajda@samsung.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -33,6 +33,12 @@ #define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */ #define CLK_MOUT_CORE 19 #define CLK_MOUT_APLL 20 +#define CLK_SCLK_HDMIPHY 22 +#define CLK_OUT_DMC 23 +#define CLK_OUT_TOP 24 +#define CLK_OUT_LEFTBUS 25 +#define CLK_OUT_RIGHTBUS 26 +#define CLK_OUT_CPU 27 /* gate for special clocks (sclk) */ #define CLK_SCLK_FIMC0 128 @@ -181,7 +187,6 @@ #define CLK_KEYIF 347 #define CLK_AUDSS 348 #define CLK_MIPI_HSI 349 /* Exynos4210 only */ -#define CLK_MDMA2 350 /* Exynos4210 only */ #define CLK_PIXELASYNCM0 351 #define CLK_PIXELASYNCM1 352 #define CLK_FIMC_LITE0 353 /* Exynos4x12 only */ @@ -230,6 +235,24 @@ #define CLK_MOUT_G3D 394 #define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */ +/* gate clocks - ppmu */ +#define CLK_PPMULEFT 400 +#define CLK_PPMURIGHT 401 +#define CLK_PPMUCAMIF 402 +#define CLK_PPMUTV 403 +#define CLK_PPMUMFC_L 404 +#define CLK_PPMUMFC_R 405 +#define CLK_PPMUG3D 406 +#define CLK_PPMUIMAGE 407 +#define CLK_PPMULCD0 408 +#define CLK_PPMULCD1 409 /* Exynos4210 only */ +#define CLK_PPMUFILE 410 +#define CLK_PPMUGPS 411 +#define CLK_PPMUDMC0 412 +#define CLK_PPMUDMC1 413 +#define CLK_PPMUCPU 414 +#define CLK_PPMUACP 415 + /* div clocks */ #define CLK_DIV_ISP0 450 /* Exynos4x12 only */ #define CLK_DIV_ISP1 451 /* Exynos4x12 only */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/exynos5250.h b/sys/gnu/dts/include/dt-bindings/clock/exynos5250.h index 922f2dc..4273891 100644 --- a/sys/gnu/dts/include/dt-bindings/clock/exynos5250.h +++ b/sys/gnu/dts/include/dt-bindings/clock/exynos5250.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * Author: Andrzej Haja <a.hajda@samsung.com> + * Author: Andrzej Hajda <a.hajda@samsung.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -150,11 +150,30 @@ #define CLK_G2D 345 #define CLK_MDMA0 346 #define CLK_SMMU_MDMA0 347 +#define CLK_SSS 348 +#define CLK_G3D 349 +#define CLK_SMMU_TV 350 +#define CLK_SMMU_FIMD1 351 +#define CLK_SMMU_2D 352 +#define CLK_SMMU_FIMC_ISP 353 +#define CLK_SMMU_FIMC_DRC 354 +#define CLK_SMMU_FIMC_SCC 355 +#define CLK_SMMU_FIMC_SCP 356 +#define CLK_SMMU_FIMC_FD 357 +#define CLK_SMMU_FIMC_MCU 358 +#define CLK_SMMU_FIMC_ODC 359 +#define CLK_SMMU_FIMC_DIS0 360 +#define CLK_SMMU_FIMC_DIS1 361 +#define CLK_SMMU_FIMC_3DNR 362 +#define CLK_SMMU_FIMC_LITE0 363 +#define CLK_SMMU_FIMC_LITE1 364 +#define CLK_CAMIF_TOP 365 /* mux clocks */ #define CLK_MOUT_HDMI 1024 +#define CLK_MOUT_GPLL 1025 /* must be greater than maximal clock id */ -#define CLK_NR_CLKS 1025 +#define CLK_NR_CLKS 1026 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/exynos5260-clk.h b/sys/gnu/dts/include/dt-bindings/clock/exynos5260-clk.h new file mode 100644 index 0000000..a4bac9a --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/exynos5260-clk.h @@ -0,0 +1,469 @@ +/* + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * Author: Rahul Sharma <rahul.sharma@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Provides Constants for Exynos5260 clocks. +*/ + +#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H +#define _DT_BINDINGS_CLK_EXYNOS5260_H + +/* Clock names: <cmu><type><IP> */ + +/* List Of Clocks For CMU_TOP */ + +#define TOP_FOUT_DISP_PLL 1 +#define TOP_FOUT_AUD_PLL 2 +#define TOP_MOUT_AUDTOP_PLL_USER 3 +#define TOP_MOUT_AUD_PLL 4 +#define TOP_MOUT_DISP_PLL 5 +#define TOP_MOUT_BUSTOP_PLL_USER 6 +#define TOP_MOUT_MEMTOP_PLL_USER 7 +#define TOP_MOUT_MEDIATOP_PLL_USER 8 +#define TOP_MOUT_DISP_DISP_333 9 +#define TOP_MOUT_ACLK_DISP_333 10 +#define TOP_MOUT_DISP_DISP_222 11 +#define TOP_MOUT_ACLK_DISP_222 12 +#define TOP_MOUT_DISP_MEDIA_PIXEL 13 +#define TOP_MOUT_FIMD1 14 +#define TOP_MOUT_SCLK_PERI_SPI0_CLK 15 +#define TOP_MOUT_SCLK_PERI_SPI1_CLK 16 +#define TOP_MOUT_SCLK_PERI_SPI2_CLK 17 +#define TOP_MOUT_SCLK_PERI_UART0_UCLK 18 +#define TOP_MOUT_SCLK_PERI_UART2_UCLK 19 +#define TOP_MOUT_SCLK_PERI_UART1_UCLK 20 +#define TOP_MOUT_BUS4_BUSTOP_100 21 +#define TOP_MOUT_BUS4_BUSTOP_400 22 +#define TOP_MOUT_BUS3_BUSTOP_100 23 +#define TOP_MOUT_BUS3_BUSTOP_400 24 +#define TOP_MOUT_BUS2_BUSTOP_400 25 +#define TOP_MOUT_BUS2_BUSTOP_100 26 +#define TOP_MOUT_BUS1_BUSTOP_100 27 +#define TOP_MOUT_BUS1_BUSTOP_400 28 +#define TOP_MOUT_SCLK_FSYS_USB 29 +#define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A 30 +#define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A 31 +#define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A 32 +#define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B 33 +#define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B 34 +#define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B 35 +#define TOP_MOUT_ACLK_ISP1_266 36 +#define TOP_MOUT_ISP1_MEDIA_266 37 +#define TOP_MOUT_ACLK_ISP1_400 38 +#define TOP_MOUT_ISP1_MEDIA_400 39 +#define TOP_MOUT_SCLK_ISP1_SPI0 40 +#define TOP_MOUT_SCLK_ISP1_SPI1 41 +#define TOP_MOUT_SCLK_ISP1_UART 42 +#define TOP_MOUT_SCLK_ISP1_SENSOR2 43 +#define TOP_MOUT_SCLK_ISP1_SENSOR1 44 +#define TOP_MOUT_SCLK_ISP1_SENSOR0 45 +#define TOP_MOUT_ACLK_MFC_333 46 +#define TOP_MOUT_MFC_BUSTOP_333 47 +#define TOP_MOUT_ACLK_G2D_333 48 +#define TOP_MOUT_G2D_BUSTOP_333 49 +#define TOP_MOUT_ACLK_GSCL_FIMC 50 +#define TOP_MOUT_GSCL_BUSTOP_FIMC 51 +#define TOP_MOUT_ACLK_GSCL_333 52 +#define TOP_MOUT_GSCL_BUSTOP_333 53 +#define TOP_MOUT_ACLK_GSCL_400 54 +#define TOP_MOUT_M2M_MEDIATOP_400 55 +#define TOP_DOUT_ACLK_MFC_333 56 +#define TOP_DOUT_ACLK_G2D_333 57 +#define TOP_DOUT_SCLK_ISP1_SENSOR2_A 58 +#define TOP_DOUT_SCLK_ISP1_SENSOR1_A 59 +#define TOP_DOUT_SCLK_ISP1_SENSOR0_A 60 +#define TOP_DOUT_ACLK_GSCL_FIMC 61 +#define TOP_DOUT_ACLK_GSCL_400 62 +#define TOP_DOUT_ACLK_GSCL_333 63 +#define TOP_DOUT_SCLK_ISP1_SPI0_B 64 +#define TOP_DOUT_SCLK_ISP1_SPI0_A 65 +#define TOP_DOUT_ACLK_ISP1_400 66 +#define TOP_DOUT_ACLK_ISP1_266 67 +#define TOP_DOUT_SCLK_ISP1_UART 68 +#define TOP_DOUT_SCLK_ISP1_SPI1_B 69 +#define TOP_DOUT_SCLK_ISP1_SPI1_A 70 +#define TOP_DOUT_SCLK_ISP1_SENSOR2_B 71 +#define TOP_DOUT_SCLK_ISP1_SENSOR1_B 72 +#define TOP_DOUT_SCLK_ISP1_SENSOR0_B 73 +#define TOP_DOUTTOP__SCLK_HPM_TARGETCLK 74 +#define TOP_DOUT_SCLK_DISP_PIXEL 75 +#define TOP_DOUT_ACLK_DISP_222 76 +#define TOP_DOUT_ACLK_DISP_333 77 +#define TOP_DOUT_ACLK_BUS4_100 78 +#define TOP_DOUT_ACLK_BUS4_400 79 +#define TOP_DOUT_ACLK_BUS3_100 80 +#define TOP_DOUT_ACLK_BUS3_400 81 +#define TOP_DOUT_ACLK_BUS2_100 82 +#define TOP_DOUT_ACLK_BUS2_400 83 +#define TOP_DOUT_ACLK_BUS1_100 84 +#define TOP_DOUT_ACLK_BUS1_400 85 +#define TOP_DOUT_SCLK_PERI_SPI1_B 86 +#define TOP_DOUT_SCLK_PERI_SPI1_A 87 +#define TOP_DOUT_SCLK_PERI_SPI0_B 88 +#define TOP_DOUT_SCLK_PERI_SPI0_A 89 +#define TOP_DOUT_SCLK_PERI_UART0 90 +#define TOP_DOUT_SCLK_PERI_UART2 91 +#define TOP_DOUT_SCLK_PERI_UART1 92 +#define TOP_DOUT_SCLK_PERI_SPI2_B 93 +#define TOP_DOUT_SCLK_PERI_SPI2_A 94 +#define TOP_DOUT_ACLK_PERI_AUD 95 +#define TOP_DOUT_ACLK_PERI_66 96 +#define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B 97 +#define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A 98 +#define TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK 99 +#define TOP_DOUT_ACLK_FSYS_200 100 +#define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B 101 +#define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A 102 +#define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B 103 +#define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A 104 +#define TOP_SCLK_FIMD1 105 +#define TOP_SCLK_MMC2 106 +#define TOP_SCLK_MMC1 107 +#define TOP_SCLK_MMC0 108 +#define PHYCLK_DPTX_PHY_CH3_TXD_CLK 109 +#define PHYCLK_DPTX_PHY_CH2_TXD_CLK 110 +#define PHYCLK_DPTX_PHY_CH1_TXD_CLK 111 +#define PHYCLK_DPTX_PHY_CH0_TXD_CLK 112 +#define phyclk_hdmi_phy_tmds_clko 113 +#define PHYCLK_HDMI_PHY_PIXEL_CLKO 114 +#define PHYCLK_HDMI_LINK_O_TMDS_CLKHI 115 +#define PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS 116 +#define PHYCLK_DPTX_PHY_O_REF_CLK_24M 117 +#define PHYCLK_DPTX_PHY_CLK_DIV2 118 +#define PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0 119 +#define PHYCLK_USBHOST20_PHY_PHYCLOCK 120 +#define PHYCLK_USBHOST20_PHY_FREECLK 121 +#define PHYCLK_USBHOST20_PHY_CLK48MOHCI 122 +#define PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 123 +#define PHYCLK_USBDRD30_UDRD30_PHYCLOCK 124 +#define TOP_NR_CLK 125 + + +/* List Of Clocks For CMU_EGL */ + +#define EGL_FOUT_EGL_PLL 1 +#define EGL_FOUT_EGL_DPLL 2 +#define EGL_MOUT_EGL_B 3 +#define EGL_MOUT_EGL_PLL 4 +#define EGL_DOUT_EGL_PLL 5 +#define EGL_DOUT_EGL_PCLK_DBG 6 +#define EGL_DOUT_EGL_ATCLK 7 +#define EGL_DOUT_PCLK_EGL 8 +#define EGL_DOUT_ACLK_EGL 9 +#define EGL_DOUT_EGL2 10 +#define EGL_DOUT_EGL1 11 +#define EGL_NR_CLK 12 + + +/* List Of Clocks For CMU_KFC */ + +#define KFC_FOUT_KFC_PLL 1 +#define KFC_MOUT_KFC_PLL 2 +#define KFC_MOUT_KFC 3 +#define KFC_DOUT_KFC_PLL 4 +#define KFC_DOUT_PCLK_KFC 5 +#define KFC_DOUT_ACLK_KFC 6 +#define KFC_DOUT_KFC_PCLK_DBG 7 +#define KFC_DOUT_KFC_ATCLK 8 +#define KFC_DOUT_KFC2 9 +#define KFC_DOUT_KFC1 10 +#define KFC_NR_CLK 11 + + +/* List Of Clocks For CMU_MIF */ + +#define MIF_FOUT_MEM_PLL 1 +#define MIF_FOUT_MEDIA_PLL 2 +#define MIF_FOUT_BUS_PLL 3 +#define MIF_MOUT_CLK2X_PHY 4 +#define MIF_MOUT_MIF_DREX2X 5 +#define MIF_MOUT_CLKM_PHY 6 +#define MIF_MOUT_MIF_DREX 7 +#define MIF_MOUT_MEDIA_PLL 8 +#define MIF_MOUT_BUS_PLL 9 +#define MIF_MOUT_MEM_PLL 10 +#define MIF_DOUT_ACLK_BUS_100 11 +#define MIF_DOUT_ACLK_BUS_200 12 +#define MIF_DOUT_ACLK_MIF_466 13 +#define MIF_DOUT_CLK2X_PHY 14 +#define MIF_DOUT_CLKM_PHY 15 +#define MIF_DOUT_BUS_PLL 16 +#define MIF_DOUT_MEM_PLL 17 +#define MIF_DOUT_MEDIA_PLL 18 +#define MIF_CLK_LPDDR3PHY_WRAP1 19 +#define MIF_CLK_LPDDR3PHY_WRAP0 20 +#define MIF_CLK_MONOCNT 21 +#define MIF_CLK_MIF_RTC 22 +#define MIF_CLK_DREX1 23 +#define MIF_CLK_DREX0 24 +#define MIF_CLK_INTMEM 25 +#define MIF_SCLK_LPDDR3PHY_WRAP_U1 26 +#define MIF_SCLK_LPDDR3PHY_WRAP_U0 27 +#define MIF_NR_CLK 28 + + +/* List Of Clocks For CMU_G3D */ + +#define G3D_FOUT_G3D_PLL 1 +#define G3D_MOUT_G3D_PLL 2 +#define G3D_DOUT_PCLK_G3D 3 +#define G3D_DOUT_ACLK_G3D 4 +#define G3D_CLK_G3D_HPM 5 +#define G3D_CLK_G3D 6 +#define G3D_NR_CLK 7 + + +/* List Of Clocks For CMU_AUD */ + +#define AUD_MOUT_SCLK_AUD_PCM 1 +#define AUD_MOUT_SCLK_AUD_I2S 2 +#define AUD_MOUT_AUD_PLL_USER 3 +#define AUD_DOUT_ACLK_AUD_131 4 +#define AUD_DOUT_SCLK_AUD_UART 5 +#define AUD_DOUT_SCLK_AUD_PCM 6 +#define AUD_DOUT_SCLK_AUD_I2S 7 +#define AUD_CLK_AUD_UART 8 +#define AUD_CLK_PCM 9 +#define AUD_CLK_I2S 10 +#define AUD_CLK_DMAC 11 +#define AUD_CLK_SRAMC 12 +#define AUD_SCLK_AUD_UART 13 +#define AUD_SCLK_PCM 14 +#define AUD_SCLK_I2S 15 +#define AUD_NR_CLK 16 + + +/* List Of Clocks For CMU_MFC */ + +#define MFC_MOUT_ACLK_MFC_333_USER 1 +#define MFC_DOUT_PCLK_MFC_83 2 +#define MFC_CLK_MFC 3 +#define MFC_CLK_SMMU2_MFCM1 4 +#define MFC_CLK_SMMU2_MFCM0 5 +#define MFC_NR_CLK 6 + + +/* List Of Clocks For CMU_GSCL */ + +#define GSCL_MOUT_ACLK_CSIS 1 +#define GSCL_MOUT_ACLK_GSCL_FIMC_USER 2 +#define GSCL_MOUT_ACLK_M2M_400_USER 3 +#define GSCL_MOUT_ACLK_GSCL_333_USER 4 +#define GSCL_DOUT_ACLK_CSIS_200 5 +#define GSCL_DOUT_PCLK_M2M_100 6 +#define GSCL_CLK_PIXEL_GSCL1 7 +#define GSCL_CLK_PIXEL_GSCL0 8 +#define GSCL_CLK_MSCL1 9 +#define GSCL_CLK_MSCL0 10 +#define GSCL_CLK_GSCL1 11 +#define GSCL_CLK_GSCL0 12 +#define GSCL_CLK_FIMC_LITE_D 13 +#define GSCL_CLK_FIMC_LITE_B 14 +#define GSCL_CLK_FIMC_LITE_A 15 +#define GSCL_CLK_CSIS1 16 +#define GSCL_CLK_CSIS0 17 +#define GSCL_CLK_SMMU3_LITE_D 18 +#define GSCL_CLK_SMMU3_LITE_B 19 +#define GSCL_CLK_SMMU3_LITE_A 20 +#define GSCL_CLK_SMMU3_GSCL0 21 +#define GSCL_CLK_SMMU3_GSCL1 22 +#define GSCL_CLK_SMMU3_MSCL0 23 +#define GSCL_CLK_SMMU3_MSCL1 24 +#define GSCL_SCLK_CSIS1_WRAP 25 +#define GSCL_SCLK_CSIS0_WRAP 26 +#define GSCL_NR_CLK 27 + + +/* List Of Clocks For CMU_FSYS */ + +#define FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER 1 +#define FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER 2 +#define FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER 3 +#define FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER 4 +#define FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER 5 +#define FSYS_CLK_TSI 6 +#define FSYS_CLK_USBLINK 7 +#define FSYS_CLK_USBHOST20 8 +#define FSYS_CLK_USBDRD30 9 +#define FSYS_CLK_SROMC 10 +#define FSYS_CLK_PDMA 11 +#define FSYS_CLK_MMC2 12 +#define FSYS_CLK_MMC1 13 +#define FSYS_CLK_MMC0 14 +#define FSYS_CLK_RTIC 15 +#define FSYS_CLK_SMMU_RTIC 16 +#define FSYS_PHYCLK_USBDRD30 17 +#define FSYS_PHYCLK_USBHOST20 18 +#define FSYS_NR_CLK 19 + + +/* List Of Clocks For CMU_PERI */ + +#define PERI_MOUT_SCLK_SPDIF 1 +#define PERI_MOUT_SCLK_I2SCOD 2 +#define PERI_MOUT_SCLK_PCM 3 +#define PERI_DOUT_I2S 4 +#define PERI_DOUT_PCM 5 +#define PERI_CLK_WDT_KFC 6 +#define PERI_CLK_WDT_EGL 7 +#define PERI_CLK_HSIC3 8 +#define PERI_CLK_HSIC2 9 +#define PERI_CLK_HSIC1 10 +#define PERI_CLK_HSIC0 11 +#define PERI_CLK_PCM 12 +#define PERI_CLK_MCT 13 +#define PERI_CLK_I2S 14 +#define PERI_CLK_I2CHDMI 15 +#define PERI_CLK_I2C7 16 +#define PERI_CLK_I2C6 17 +#define PERI_CLK_I2C5 18 +#define PERI_CLK_I2C4 19 +#define PERI_CLK_I2C9 20 +#define PERI_CLK_I2C8 21 +#define PERI_CLK_I2C11 22 +#define PERI_CLK_I2C10 23 +#define PERI_CLK_HDMICEC 24 +#define PERI_CLK_EFUSE_WRITER 25 +#define PERI_CLK_ABB 26 +#define PERI_CLK_UART2 27 +#define PERI_CLK_UART1 28 +#define PERI_CLK_UART0 29 +#define PERI_CLK_ADC 30 +#define PERI_CLK_TMU4 31 +#define PERI_CLK_TMU3 32 +#define PERI_CLK_TMU2 33 +#define PERI_CLK_TMU1 34 +#define PERI_CLK_TMU0 35 +#define PERI_CLK_SPI2 36 +#define PERI_CLK_SPI1 37 +#define PERI_CLK_SPI0 38 +#define PERI_CLK_SPDIF 39 +#define PERI_CLK_PWM 40 +#define PERI_CLK_UART4 41 +#define PERI_CLK_CHIPID 42 +#define PERI_CLK_PROVKEY0 43 +#define PERI_CLK_PROVKEY1 44 +#define PERI_CLK_SECKEY 45 +#define PERI_CLK_TOP_RTC 46 +#define PERI_CLK_TZPC10 47 +#define PERI_CLK_TZPC9 48 +#define PERI_CLK_TZPC8 49 +#define PERI_CLK_TZPC7 50 +#define PERI_CLK_TZPC6 51 +#define PERI_CLK_TZPC5 52 +#define PERI_CLK_TZPC4 53 +#define PERI_CLK_TZPC3 54 +#define PERI_CLK_TZPC2 55 +#define PERI_CLK_TZPC1 56 +#define PERI_CLK_TZPC0 57 +#define PERI_SCLK_UART2 58 +#define PERI_SCLK_UART1 59 +#define PERI_SCLK_UART0 60 +#define PERI_SCLK_SPI2 61 +#define PERI_SCLK_SPI1 62 +#define PERI_SCLK_SPI0 63 +#define PERI_SCLK_SPDIF 64 +#define PERI_SCLK_I2S 65 +#define PERI_SCLK_PCM1 66 +#define PERI_NR_CLK 67 + + +/* List Of Clocks For CMU_DISP */ + +#define DISP_MOUT_SCLK_HDMI_SPDIF 1 +#define DISP_MOUT_SCLK_HDMI_PIXEL 2 +#define DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER 3 +#define DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER 4 +#define DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER 5 +#define DISP_MOUT_HDMI_PHY_PIXEL 6 +#define DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER 7 +#define DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS 8 +#define DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER 9 +#define DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER 10 +#define DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER 11 +#define DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER 12 +#define DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER 13 +#define DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER 14 +#define DISP_MOUT_ACLK_DISP_222_USER 15 +#define DISP_MOUT_SCLK_DISP_PIXEL_USER 16 +#define DISP_MOUT_ACLK_DISP_333_USER 17 +#define DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI 18 +#define DISP_DOUT_SCLK_FIMD1_EXTCLKPLL 19 +#define DISP_DOUT_PCLK_DISP_111 20 +#define DISP_CLK_SMMU_TV 21 +#define DISP_CLK_SMMU_FIMD1M1 22 +#define DISP_CLK_SMMU_FIMD1M0 23 +#define DISP_CLK_PIXEL_MIXER 24 +#define DISP_CLK_PIXEL_DISP 25 +#define DISP_CLK_MIXER 26 +#define DISP_CLK_MIPIPHY 27 +#define DISP_CLK_HDMIPHY 28 +#define DISP_CLK_HDMI 29 +#define DISP_CLK_FIMD1 30 +#define DISP_CLK_DSIM1 31 +#define DISP_CLK_DPPHY 32 +#define DISP_CLK_DP 33 +#define DISP_SCLK_PIXEL 34 +#define DISP_MOUT_HDMI_PHY_PIXEL_USER 35 +#define DISP_NR_CLK 36 + + +/* List Of Clocks For CMU_G2D */ + +#define G2D_MOUT_ACLK_G2D_333_USER 1 +#define G2D_DOUT_PCLK_G2D_83 2 +#define G2D_CLK_SMMU3_JPEG 3 +#define G2D_CLK_MDMA 4 +#define G2D_CLK_JPEG 5 +#define G2D_CLK_G2D 6 +#define G2D_CLK_SSS 7 +#define G2D_CLK_SLIM_SSS 8 +#define G2D_CLK_SMMU_SLIM_SSS 9 +#define G2D_CLK_SMMU_SSS 10 +#define G2D_CLK_SMMU_MDMA 11 +#define G2D_CLK_SMMU3_G2D 12 +#define G2D_NR_CLK 13 + + +/* List Of Clocks For CMU_ISP */ + +#define ISP_MOUT_ISP_400_USER 1 +#define ISP_MOUT_ISP_266_USER 2 +#define ISP_DOUT_SCLK_MPWM 3 +#define ISP_DOUT_CA5_PCLKDBG 4 +#define ISP_DOUT_CA5_ATCLKIN 5 +#define ISP_DOUT_PCLK_ISP_133 6 +#define ISP_DOUT_PCLK_ISP_66 7 +#define ISP_CLK_GIC 8 +#define ISP_CLK_WDT 9 +#define ISP_CLK_UART 10 +#define ISP_CLK_SPI1 11 +#define ISP_CLK_SPI0 12 +#define ISP_CLK_SMMU_SCALERP 13 +#define ISP_CLK_SMMU_SCALERC 14 +#define ISP_CLK_SMMU_ISPCX 15 +#define ISP_CLK_SMMU_ISP 16 +#define ISP_CLK_SMMU_FD 17 +#define ISP_CLK_SMMU_DRC 18 +#define ISP_CLK_PWM 19 +#define ISP_CLK_MTCADC 20 +#define ISP_CLK_MPWM 21 +#define ISP_CLK_MCUCTL 22 +#define ISP_CLK_I2C1 23 +#define ISP_CLK_I2C0 24 +#define ISP_CLK_FIMC_SCALERP 25 +#define ISP_CLK_FIMC_SCALERC 26 +#define ISP_CLK_FIMC 27 +#define ISP_CLK_FIMC_FD 28 +#define ISP_CLK_FIMC_DRC 29 +#define ISP_CLK_CA5 30 +#define ISP_SCLK_SPI0_EXT 31 +#define ISP_SCLK_SPI1_EXT 32 +#define ISP_SCLK_UART_EXT 33 +#define ISP_NR_CLK 34 + +#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/exynos5410.h b/sys/gnu/dts/include/dt-bindings/clock/exynos5410.h new file mode 100644 index 0000000..9b180f0 --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/exynos5410.h @@ -0,0 +1,33 @@ +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H +#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H + +/* core clocks */ +#define CLK_FIN_PLL 1 +#define CLK_FOUT_APLL 2 +#define CLK_FOUT_CPLL 3 +#define CLK_FOUT_MPLL 4 +#define CLK_FOUT_BPLL 5 +#define CLK_FOUT_KPLL 6 + +/* gate for special clocks (sclk) */ +#define CLK_SCLK_UART0 128 +#define CLK_SCLK_UART1 129 +#define CLK_SCLK_UART2 130 +#define CLK_SCLK_UART3 131 +#define CLK_SCLK_MMC0 132 +#define CLK_SCLK_MMC1 133 +#define CLK_SCLK_MMC2 134 + +/* gate clocks */ +#define CLK_UART0 257 +#define CLK_UART1 258 +#define CLK_UART2 259 +#define CLK_UART3 260 +#define CLK_MCT 315 +#define CLK_MMC0 351 +#define CLK_MMC1 352 +#define CLK_MMC2 353 + +#define CLK_NR_CLKS 512 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/exynos5420.h b/sys/gnu/dts/include/dt-bindings/clock/exynos5420.h index 5eefd88..8dc0913 100644 --- a/sys/gnu/dts/include/dt-bindings/clock/exynos5420.h +++ b/sys/gnu/dts/include/dt-bindings/clock/exynos5420.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * Author: Andrzej Haja <a.hajda@samsung.com> + * Author: Andrzej Hajda <a.hajda@samsung.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -58,9 +58,11 @@ #define CLK_SCLK_GSCL_WA 156 #define CLK_SCLK_GSCL_WB 157 #define CLK_SCLK_HDMIPHY 158 +#define CLK_MAU_EPLL 159 +#define CLK_SCLK_HSIC_12M 160 +#define CLK_SCLK_MPHY_IXTAL24 161 /* gate clocks */ -#define CLK_ACLK66_PERIC 256 #define CLK_UART0 257 #define CLK_UART1 258 #define CLK_UART2 259 @@ -69,10 +71,10 @@ #define CLK_I2C1 262 #define CLK_I2C2 263 #define CLK_I2C3 264 -#define CLK_I2C4 265 -#define CLK_I2C5 266 -#define CLK_I2C6 267 -#define CLK_I2C7 268 +#define CLK_USI0 265 +#define CLK_USI1 266 +#define CLK_USI2 267 +#define CLK_USI3 268 #define CLK_I2C_HDMI 269 #define CLK_TSADC 270 #define CLK_SPI0 271 @@ -85,9 +87,9 @@ #define CLK_PCM2 278 #define CLK_PWM 279 #define CLK_SPDIF 280 -#define CLK_I2C8 281 -#define CLK_I2C9 282 -#define CLK_I2C10 283 +#define CLK_USI4 281 +#define CLK_USI5 282 +#define CLK_USI6 283 #define CLK_ACLK66_PSGEN 300 #define CLK_CHIPID 301 #define CLK_SYSREG 302 @@ -140,7 +142,8 @@ #define CLK_HDMI 413 #define CLK_ACLK300_DISP1 420 #define CLK_FIMD1 421 -#define CLK_SMMU_FIMD1 422 +#define CLK_SMMU_FIMD1M0 422 +#define CLK_SMMU_FIMD1M1 423 #define CLK_ACLK166 430 #define CLK_MIXER 431 #define CLK_ACLK266 440 @@ -152,6 +155,7 @@ #define CLK_JPEG 451 #define CLK_JPEG2 452 #define CLK_SMMU_JPEG 453 +#define CLK_SMMU_JPEG2 454 #define CLK_ACLK300_GSCL 460 #define CLK_SMMU_GSCL0 461 #define CLK_SMMU_GSCL1 462 @@ -159,7 +163,7 @@ #define CLK_GSCL_WB 464 #define CLK_GSCL0 465 #define CLK_GSCL1 466 -#define CLK_CLK_3AA 467 +#define CLK_FIMC_3AA 467 #define CLK_ACLK266_G2D 470 #define CLK_SSS 471 #define CLK_SLIM_SSS 472 @@ -172,12 +176,34 @@ #define CLK_SMMU_FIMCL1 493 #define CLK_SMMU_FIMCL3 494 #define CLK_FIMC_LITE3 495 +#define CLK_FIMC_LITE0 496 +#define CLK_FIMC_LITE1 497 #define CLK_ACLK_G3D 500 #define CLK_G3D 501 #define CLK_SMMU_MIXER 502 +#define CLK_SMMU_G2D 503 +#define CLK_SMMU_MDMA0 504 +#define CLK_MC 505 +#define CLK_TOP_RTC 506 +#define CLK_SCLK_UART_ISP 510 +#define CLK_SCLK_SPI0_ISP 511 +#define CLK_SCLK_SPI1_ISP 512 +#define CLK_SCLK_PWM_ISP 513 +#define CLK_SCLK_ISP_SENSOR0 514 +#define CLK_SCLK_ISP_SENSOR1 515 +#define CLK_SCLK_ISP_SENSOR2 516 +#define CLK_ACLK432_SCALER 517 +#define CLK_ACLK432_CAM 518 +#define CLK_ACLK_FL1550_CAM 519 +#define CLK_ACLK550_CAM 520 /* mux clocks */ #define CLK_MOUT_HDMI 640 +#define CLK_MOUT_G3D 641 +#define CLK_MOUT_VPLL 642 +#define CLK_MOUT_MAUDIO0 643 +#define CLK_MOUT_USER_ACLK333 644 +#define CLK_MOUT_SW_ACLK333 645 /* divider clocks */ #define CLK_DOUT_PIXEL 768 diff --git a/sys/gnu/dts/include/dt-bindings/clock/exynos5440.h b/sys/gnu/dts/include/dt-bindings/clock/exynos5440.h index 70cd850..c66fc40 100644 --- a/sys/gnu/dts/include/dt-bindings/clock/exynos5440.h +++ b/sys/gnu/dts/include/dt-bindings/clock/exynos5440.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * Author: Andrzej Haja <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> + * Author: Andrzej Hajda <a.hajda@samsung.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/sys/gnu/dts/include/dt-bindings/clock/hi3620-clock.h b/sys/gnu/dts/include/dt-bindings/clock/hi3620-clock.h index 6eaa6a4..21b9d0e 100644 --- a/sys/gnu/dts/include/dt-bindings/clock/hi3620-clock.h +++ b/sys/gnu/dts/include/dt-bindings/clock/hi3620-clock.h @@ -147,6 +147,11 @@ #define HI3620_MMC_CLK3 217 #define HI3620_MCU_CLK 218 +#define HI3620_SD_CIUCLK 0 +#define HI3620_MMC_CIUCLK1 1 +#define HI3620_MMC_CIUCLK2 2 +#define HI3620_MMC_CIUCLK3 3 + #define HI3620_NR_CLKS 219 #endif /* __DTS_HI3620_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/hip04-clock.h b/sys/gnu/dts/include/dt-bindings/clock/hip04-clock.h new file mode 100644 index 0000000..695e61c --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/hip04-clock.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2013-2014 Hisilicon Limited. + * Copyright (c) 2013-2014 Linaro Limited. + * + * Author: Haojian Zhuang <haojian.zhuang@linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + */ + +#ifndef __DTS_HIP04_CLOCK_H +#define __DTS_HIP04_CLOCK_H + +#define HIP04_NONE_CLOCK 0 + +/* fixed rate & fixed factor clocks */ +#define HIP04_OSC50M 1 +#define HIP04_CLK_50M 2 +#define HIP04_CLK_168M 3 + +#define HIP04_NR_CLKS 64 + +#endif /* __DTS_HIP04_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/hix5hd2-clock.h b/sys/gnu/dts/include/dt-bindings/clock/hix5hd2-clock.h new file mode 100644 index 0000000..aad579a --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/hix5hd2-clock.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2014 Linaro Ltd. + * Copyright (c) 2014 Hisilicon Limited. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + */ + +#ifndef __DTS_HIX5HD2_CLOCK_H +#define __DTS_HIX5HD2_CLOCK_H + +/* fixed rate */ +#define HIX5HD2_FIXED_1200M 1 +#define HIX5HD2_FIXED_400M 2 +#define HIX5HD2_FIXED_48M 3 +#define HIX5HD2_FIXED_24M 4 +#define HIX5HD2_FIXED_600M 5 +#define HIX5HD2_FIXED_300M 6 +#define HIX5HD2_FIXED_75M 7 +#define HIX5HD2_FIXED_200M 8 +#define HIX5HD2_FIXED_100M 9 +#define HIX5HD2_FIXED_40M 10 +#define HIX5HD2_FIXED_150M 11 +#define HIX5HD2_FIXED_1728M 12 +#define HIX5HD2_FIXED_28P8M 13 +#define HIX5HD2_FIXED_432M 14 +#define HIX5HD2_FIXED_345P6M 15 +#define HIX5HD2_FIXED_288M 16 +#define HIX5HD2_FIXED_60M 17 +#define HIX5HD2_FIXED_750M 18 +#define HIX5HD2_FIXED_500M 19 +#define HIX5HD2_FIXED_54M 20 +#define HIX5HD2_FIXED_27M 21 +#define HIX5HD2_FIXED_1500M 22 +#define HIX5HD2_FIXED_375M 23 +#define HIX5HD2_FIXED_187M 24 +#define HIX5HD2_FIXED_250M 25 +#define HIX5HD2_FIXED_125M 26 +#define HIX5HD2_FIXED_2P02M 27 +#define HIX5HD2_FIXED_50M 28 +#define HIX5HD2_FIXED_25M 29 +#define HIX5HD2_FIXED_83M 30 + +/* mux clocks */ +#define HIX5HD2_SFC_MUX 64 +#define HIX5HD2_MMC_MUX 65 +#define HIX5HD2_FEPHY_MUX 66 + +/* gate clocks */ +#define HIX5HD2_SFC_RST 128 +#define HIX5HD2_SFC_CLK 129 +#define HIX5HD2_MMC_CIU_CLK 130 +#define HIX5HD2_MMC_BIU_CLK 131 +#define HIX5HD2_MMC_CIU_RST 132 + +#define HIX5HD2_NR_CLKS 256 +#endif /* __DTS_HIX5HD2_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx1-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx1-clock.h new file mode 100644 index 0000000..607bf01 --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/imx1-clock.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX1_H +#define __DT_BINDINGS_CLOCK_IMX1_H + +#define IMX1_CLK_DUMMY 0 +#define IMX1_CLK_CLK32 1 +#define IMX1_CLK_CLK16M_EXT 2 +#define IMX1_CLK_CLK16M 3 +#define IMX1_CLK_CLK32_PREMULT 4 +#define IMX1_CLK_PREM 5 +#define IMX1_CLK_MPLL 6 +#define IMX1_CLK_MPLL_GATE 7 +#define IMX1_CLK_SPLL 8 +#define IMX1_CLK_SPLL_GATE 9 +#define IMX1_CLK_MCU 10 +#define IMX1_CLK_FCLK 11 +#define IMX1_CLK_HCLK 12 +#define IMX1_CLK_CLK48M 13 +#define IMX1_CLK_PER1 14 +#define IMX1_CLK_PER2 15 +#define IMX1_CLK_PER3 16 +#define IMX1_CLK_CLKO 17 +#define IMX1_CLK_UART3_GATE 18 +#define IMX1_CLK_SSI2_GATE 19 +#define IMX1_CLK_BROM_GATE 20 +#define IMX1_CLK_DMA_GATE 21 +#define IMX1_CLK_CSI_GATE 22 +#define IMX1_CLK_MMA_GATE 23 +#define IMX1_CLK_USBD_GATE 24 +#define IMX1_CLK_MAX 25 + +#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx21-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx21-clock.h new file mode 100644 index 0000000..b13596c --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/imx21-clock.h @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX21_H +#define __DT_BINDINGS_CLOCK_IMX21_H + +#define IMX21_CLK_DUMMY 0 +#define IMX21_CLK_CKIL 1 +#define IMX21_CLK_CKIH 2 +#define IMX21_CLK_FPM 3 +#define IMX21_CLK_CKIH_DIV1P5 4 +#define IMX21_CLK_MPLL_GATE 5 +#define IMX21_CLK_SPLL_GATE 6 +#define IMX21_CLK_FPM_GATE 7 +#define IMX21_CLK_CKIH_GATE 8 +#define IMX21_CLK_MPLL_OSC_SEL 9 +#define IMX21_CLK_IPG 10 +#define IMX21_CLK_HCLK 11 +#define IMX21_CLK_MPLL_SEL 12 +#define IMX21_CLK_SPLL_SEL 13 +#define IMX21_CLK_SSI1_SEL 14 +#define IMX21_CLK_SSI2_SEL 15 +#define IMX21_CLK_USB_DIV 16 +#define IMX21_CLK_FCLK 17 +#define IMX21_CLK_MPLL 18 +#define IMX21_CLK_SPLL 19 +#define IMX21_CLK_NFC_DIV 20 +#define IMX21_CLK_SSI1_DIV 21 +#define IMX21_CLK_SSI2_DIV 22 +#define IMX21_CLK_PER1 23 +#define IMX21_CLK_PER2 24 +#define IMX21_CLK_PER3 25 +#define IMX21_CLK_PER4 26 +#define IMX21_CLK_UART1_IPG_GATE 27 +#define IMX21_CLK_UART2_IPG_GATE 28 +#define IMX21_CLK_UART3_IPG_GATE 29 +#define IMX21_CLK_UART4_IPG_GATE 30 +#define IMX21_CLK_CSPI1_IPG_GATE 31 +#define IMX21_CLK_CSPI2_IPG_GATE 32 +#define IMX21_CLK_SSI1_GATE 33 +#define IMX21_CLK_SSI2_GATE 34 +#define IMX21_CLK_SDHC1_IPG_GATE 35 +#define IMX21_CLK_SDHC2_IPG_GATE 36 +#define IMX21_CLK_GPIO_GATE 37 +#define IMX21_CLK_I2C_GATE 38 +#define IMX21_CLK_DMA_GATE 39 +#define IMX21_CLK_USB_GATE 40 +#define IMX21_CLK_EMMA_GATE 41 +#define IMX21_CLK_SSI2_BAUD_GATE 42 +#define IMX21_CLK_SSI1_BAUD_GATE 43 +#define IMX21_CLK_LCDC_IPG_GATE 44 +#define IMX21_CLK_NFC_GATE 45 +#define IMX21_CLK_LCDC_HCLK_GATE 46 +#define IMX21_CLK_PER4_GATE 47 +#define IMX21_CLK_BMI_GATE 48 +#define IMX21_CLK_USB_HCLK_GATE 49 +#define IMX21_CLK_SLCDC_GATE 50 +#define IMX21_CLK_SLCDC_HCLK_GATE 51 +#define IMX21_CLK_EMMA_HCLK_GATE 52 +#define IMX21_CLK_BROM_GATE 53 +#define IMX21_CLK_DMA_HCLK_GATE 54 +#define IMX21_CLK_CSI_HCLK_GATE 55 +#define IMX21_CLK_CSPI3_IPG_GATE 56 +#define IMX21_CLK_WDOG_GATE 57 +#define IMX21_CLK_GPT1_IPG_GATE 58 +#define IMX21_CLK_GPT2_IPG_GATE 59 +#define IMX21_CLK_GPT3_IPG_GATE 60 +#define IMX21_CLK_PWM_IPG_GATE 61 +#define IMX21_CLK_RTC_GATE 62 +#define IMX21_CLK_KPP_GATE 63 +#define IMX21_CLK_OWIRE_GATE 64 +#define IMX21_CLK_MAX 65 + +#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx27-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx27-clock.h new file mode 100644 index 0000000..148b053 --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/imx27-clock.h @@ -0,0 +1,108 @@ +/* + * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX27_H +#define __DT_BINDINGS_CLOCK_IMX27_H + +#define IMX27_CLK_DUMMY 0 +#define IMX27_CLK_CKIH 1 +#define IMX27_CLK_CKIL 2 +#define IMX27_CLK_MPLL 3 +#define IMX27_CLK_SPLL 4 +#define IMX27_CLK_MPLL_MAIN2 5 +#define IMX27_CLK_AHB 6 +#define IMX27_CLK_IPG 7 +#define IMX27_CLK_NFC_DIV 8 +#define IMX27_CLK_PER1_DIV 9 +#define IMX27_CLK_PER2_DIV 10 +#define IMX27_CLK_PER3_DIV 11 +#define IMX27_CLK_PER4_DIV 12 +#define IMX27_CLK_VPU_SEL 13 +#define IMX27_CLK_VPU_DIV 14 +#define IMX27_CLK_USB_DIV 15 +#define IMX27_CLK_CPU_SEL 16 +#define IMX27_CLK_CLKO_SEL 17 +#define IMX27_CLK_CPU_DIV 18 +#define IMX27_CLK_CLKO_DIV 19 +#define IMX27_CLK_SSI1_SEL 20 +#define IMX27_CLK_SSI2_SEL 21 +#define IMX27_CLK_SSI1_DIV 22 +#define IMX27_CLK_SSI2_DIV 23 +#define IMX27_CLK_CLKO_EN 24 +#define IMX27_CLK_SSI2_IPG_GATE 25 +#define IMX27_CLK_SSI1_IPG_GATE 26 +#define IMX27_CLK_SLCDC_IPG_GATE 27 +#define IMX27_CLK_SDHC3_IPG_GATE 28 +#define IMX27_CLK_SDHC2_IPG_GATE 29 +#define IMX27_CLK_SDHC1_IPG_GATE 30 +#define IMX27_CLK_SCC_IPG_GATE 31 +#define IMX27_CLK_SAHARA_IPG_GATE 32 +#define IMX27_CLK_RTC_IPG_GATE 33 +#define IMX27_CLK_PWM_IPG_GATE 34 +#define IMX27_CLK_OWIRE_IPG_GATE 35 +#define IMX27_CLK_LCDC_IPG_GATE 36 +#define IMX27_CLK_KPP_IPG_GATE 37 +#define IMX27_CLK_IIM_IPG_GATE 38 +#define IMX27_CLK_I2C2_IPG_GATE 39 +#define IMX27_CLK_I2C1_IPG_GATE 40 +#define IMX27_CLK_GPT6_IPG_GATE 41 +#define IMX27_CLK_GPT5_IPG_GATE 42 +#define IMX27_CLK_GPT4_IPG_GATE 43 +#define IMX27_CLK_GPT3_IPG_GATE 44 +#define IMX27_CLK_GPT2_IPG_GATE 45 +#define IMX27_CLK_GPT1_IPG_GATE 46 +#define IMX27_CLK_GPIO_IPG_GATE 47 +#define IMX27_CLK_FEC_IPG_GATE 48 +#define IMX27_CLK_EMMA_IPG_GATE 49 +#define IMX27_CLK_DMA_IPG_GATE 50 +#define IMX27_CLK_CSPI3_IPG_GATE 51 +#define IMX27_CLK_CSPI2_IPG_GATE 52 +#define IMX27_CLK_CSPI1_IPG_GATE 53 +#define IMX27_CLK_NFC_BAUD_GATE 54 +#define IMX27_CLK_SSI2_BAUD_GATE 55 +#define IMX27_CLK_SSI1_BAUD_GATE 56 +#define IMX27_CLK_VPU_BAUD_GATE 57 +#define IMX27_CLK_PER4_GATE 58 +#define IMX27_CLK_PER3_GATE 59 +#define IMX27_CLK_PER2_GATE 60 +#define IMX27_CLK_PER1_GATE 61 +#define IMX27_CLK_USB_AHB_GATE 62 +#define IMX27_CLK_SLCDC_AHB_GATE 63 +#define IMX27_CLK_SAHARA_AHB_GATE 64 +#define IMX27_CLK_LCDC_AHB_GATE 65 +#define IMX27_CLK_VPU_AHB_GATE 66 +#define IMX27_CLK_FEC_AHB_GATE 67 +#define IMX27_CLK_EMMA_AHB_GATE 68 +#define IMX27_CLK_EMI_AHB_GATE 69 +#define IMX27_CLK_DMA_AHB_GATE 70 +#define IMX27_CLK_CSI_AHB_GATE 71 +#define IMX27_CLK_BROM_AHB_GATE 72 +#define IMX27_CLK_ATA_AHB_GATE 73 +#define IMX27_CLK_WDOG_IPG_GATE 74 +#define IMX27_CLK_USB_IPG_GATE 75 +#define IMX27_CLK_UART6_IPG_GATE 76 +#define IMX27_CLK_UART5_IPG_GATE 77 +#define IMX27_CLK_UART4_IPG_GATE 78 +#define IMX27_CLK_UART3_IPG_GATE 79 +#define IMX27_CLK_UART2_IPG_GATE 80 +#define IMX27_CLK_UART1_IPG_GATE 81 +#define IMX27_CLK_CKIH_DIV1P5 82 +#define IMX27_CLK_FPM 83 +#define IMX27_CLK_MPLL_OSC_SEL 84 +#define IMX27_CLK_MPLL_SEL 85 +#define IMX27_CLK_SPLL_GATE 86 +#define IMX27_CLK_MSHC_DIV 87 +#define IMX27_CLK_RTIC_IPG_GATE 88 +#define IMX27_CLK_MSHC_IPG_GATE 89 +#define IMX27_CLK_RTIC_AHB_GATE 90 +#define IMX27_CLK_MSHC_BAUD_GATE 91 +#define IMX27_CLK_CKIH_GATE 92 +#define IMX27_CLK_MAX 93 + +#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx6qdl-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx6qdl-clock.h new file mode 100644 index 0000000..654151e --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/imx6qdl-clock.h @@ -0,0 +1,224 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H +#define __DT_BINDINGS_CLOCK_IMX6QDL_H + +#define IMX6QDL_CLK_DUMMY 0 +#define IMX6QDL_CLK_CKIL 1 +#define IMX6QDL_CLK_CKIH 2 +#define IMX6QDL_CLK_OSC 3 +#define IMX6QDL_CLK_PLL2_PFD0_352M 4 +#define IMX6QDL_CLK_PLL2_PFD1_594M 5 +#define IMX6QDL_CLK_PLL2_PFD2_396M 6 +#define IMX6QDL_CLK_PLL3_PFD0_720M 7 +#define IMX6QDL_CLK_PLL3_PFD1_540M 8 +#define IMX6QDL_CLK_PLL3_PFD2_508M 9 +#define IMX6QDL_CLK_PLL3_PFD3_454M 10 +#define IMX6QDL_CLK_PLL2_198M 11 +#define IMX6QDL_CLK_PLL3_120M 12 +#define IMX6QDL_CLK_PLL3_80M 13 +#define IMX6QDL_CLK_PLL3_60M 14 +#define IMX6QDL_CLK_TWD 15 +#define IMX6QDL_CLK_STEP 16 +#define IMX6QDL_CLK_PLL1_SW 17 +#define IMX6QDL_CLK_PERIPH_PRE 18 +#define IMX6QDL_CLK_PERIPH2_PRE 19 +#define IMX6QDL_CLK_PERIPH_CLK2_SEL 20 +#define IMX6QDL_CLK_PERIPH2_CLK2_SEL 21 +#define IMX6QDL_CLK_AXI_SEL 22 +#define IMX6QDL_CLK_ESAI_SEL 23 +#define IMX6QDL_CLK_ASRC_SEL 24 +#define IMX6QDL_CLK_SPDIF_SEL 25 +#define IMX6QDL_CLK_GPU2D_AXI 26 +#define IMX6QDL_CLK_GPU3D_AXI 27 +#define IMX6QDL_CLK_GPU2D_CORE_SEL 28 +#define IMX6QDL_CLK_GPU3D_CORE_SEL 29 +#define IMX6QDL_CLK_GPU3D_SHADER_SEL 30 +#define IMX6QDL_CLK_IPU1_SEL 31 +#define IMX6QDL_CLK_IPU2_SEL 32 +#define IMX6QDL_CLK_LDB_DI0_SEL 33 +#define IMX6QDL_CLK_LDB_DI1_SEL 34 +#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL 35 +#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL 36 +#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37 +#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL 38 +#define IMX6QDL_CLK_IPU1_DI0_SEL 39 +#define IMX6QDL_CLK_IPU1_DI1_SEL 40 +#define IMX6QDL_CLK_IPU2_DI0_SEL 41 +#define IMX6QDL_CLK_IPU2_DI1_SEL 42 +#define IMX6QDL_CLK_HSI_TX_SEL 43 +#define IMX6QDL_CLK_PCIE_AXI_SEL 44 +#define IMX6QDL_CLK_SSI1_SEL 45 +#define IMX6QDL_CLK_SSI2_SEL 46 +#define IMX6QDL_CLK_SSI3_SEL 47 +#define IMX6QDL_CLK_USDHC1_SEL 48 +#define IMX6QDL_CLK_USDHC2_SEL 49 +#define IMX6QDL_CLK_USDHC3_SEL 50 +#define IMX6QDL_CLK_USDHC4_SEL 51 +#define IMX6QDL_CLK_ENFC_SEL 52 +#define IMX6QDL_CLK_EMI_SEL 53 +#define IMX6QDL_CLK_EMI_SLOW_SEL 54 +#define IMX6QDL_CLK_VDO_AXI_SEL 55 +#define IMX6QDL_CLK_VPU_AXI_SEL 56 +#define IMX6QDL_CLK_CKO1_SEL 57 +#define IMX6QDL_CLK_PERIPH 58 +#define IMX6QDL_CLK_PERIPH2 59 +#define IMX6QDL_CLK_PERIPH_CLK2 60 +#define IMX6QDL_CLK_PERIPH2_CLK2 61 +#define IMX6QDL_CLK_IPG 62 +#define IMX6QDL_CLK_IPG_PER 63 +#define IMX6QDL_CLK_ESAI_PRED 64 +#define IMX6QDL_CLK_ESAI_PODF 65 +#define IMX6QDL_CLK_ASRC_PRED 66 +#define IMX6QDL_CLK_ASRC_PODF 67 +#define IMX6QDL_CLK_SPDIF_PRED 68 +#define IMX6QDL_CLK_SPDIF_PODF 69 +#define IMX6QDL_CLK_CAN_ROOT 70 +#define IMX6QDL_CLK_ECSPI_ROOT 71 +#define IMX6QDL_CLK_GPU2D_CORE_PODF 72 +#define IMX6QDL_CLK_GPU3D_CORE_PODF 73 +#define IMX6QDL_CLK_GPU3D_SHADER 74 +#define IMX6QDL_CLK_IPU1_PODF 75 +#define IMX6QDL_CLK_IPU2_PODF 76 +#define IMX6QDL_CLK_LDB_DI0_PODF 77 +#define IMX6QDL_CLK_LDB_DI1_PODF 78 +#define IMX6QDL_CLK_IPU1_DI0_PRE 79 +#define IMX6QDL_CLK_IPU1_DI1_PRE 80 +#define IMX6QDL_CLK_IPU2_DI0_PRE 81 +#define IMX6QDL_CLK_IPU2_DI1_PRE 82 +#define IMX6QDL_CLK_HSI_TX_PODF 83 +#define IMX6QDL_CLK_SSI1_PRED 84 +#define IMX6QDL_CLK_SSI1_PODF 85 +#define IMX6QDL_CLK_SSI2_PRED 86 +#define IMX6QDL_CLK_SSI2_PODF 87 +#define IMX6QDL_CLK_SSI3_PRED 88 +#define IMX6QDL_CLK_SSI3_PODF 89 +#define IMX6QDL_CLK_UART_SERIAL_PODF 90 +#define IMX6QDL_CLK_USDHC1_PODF 91 +#define IMX6QDL_CLK_USDHC2_PODF 92 +#define IMX6QDL_CLK_USDHC3_PODF 93 +#define IMX6QDL_CLK_USDHC4_PODF 94 +#define IMX6QDL_CLK_ENFC_PRED 95 +#define IMX6QDL_CLK_ENFC_PODF 96 +#define IMX6QDL_CLK_EMI_PODF 97 +#define IMX6QDL_CLK_EMI_SLOW_PODF 98 +#define IMX6QDL_CLK_VPU_AXI_PODF 99 +#define IMX6QDL_CLK_CKO1_PODF 100 +#define IMX6QDL_CLK_AXI 101 +#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF 102 +#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF 103 +#define IMX6QDL_CLK_ARM 104 +#define IMX6QDL_CLK_AHB 105 +#define IMX6QDL_CLK_APBH_DMA 106 +#define IMX6QDL_CLK_ASRC 107 +#define IMX6QDL_CLK_CAN1_IPG 108 +#define IMX6QDL_CLK_CAN1_SERIAL 109 +#define IMX6QDL_CLK_CAN2_IPG 110 +#define IMX6QDL_CLK_CAN2_SERIAL 111 +#define IMX6QDL_CLK_ECSPI1 112 +#define IMX6QDL_CLK_ECSPI2 113 +#define IMX6QDL_CLK_ECSPI3 114 +#define IMX6QDL_CLK_ECSPI4 115 +#define IMX6Q_CLK_ECSPI5 116 +#define IMX6DL_CLK_I2C4 116 +#define IMX6QDL_CLK_ENET 117 +#define IMX6QDL_CLK_ESAI 118 +#define IMX6QDL_CLK_GPT_IPG 119 +#define IMX6QDL_CLK_GPT_IPG_PER 120 +#define IMX6QDL_CLK_GPU2D_CORE 121 +#define IMX6QDL_CLK_GPU3D_CORE 122 +#define IMX6QDL_CLK_HDMI_IAHB 123 +#define IMX6QDL_CLK_HDMI_ISFR 124 +#define IMX6QDL_CLK_I2C1 125 +#define IMX6QDL_CLK_I2C2 126 +#define IMX6QDL_CLK_I2C3 127 +#define IMX6QDL_CLK_IIM 128 +#define IMX6QDL_CLK_ENFC 129 +#define IMX6QDL_CLK_IPU1 130 +#define IMX6QDL_CLK_IPU1_DI0 131 +#define IMX6QDL_CLK_IPU1_DI1 132 +#define IMX6QDL_CLK_IPU2 133 +#define IMX6QDL_CLK_IPU2_DI0 134 +#define IMX6QDL_CLK_LDB_DI0 135 +#define IMX6QDL_CLK_LDB_DI1 136 +#define IMX6QDL_CLK_IPU2_DI1 137 +#define IMX6QDL_CLK_HSI_TX 138 +#define IMX6QDL_CLK_MLB 139 +#define IMX6QDL_CLK_MMDC_CH0_AXI 140 +#define IMX6QDL_CLK_MMDC_CH1_AXI 141 +#define IMX6QDL_CLK_OCRAM 142 +#define IMX6QDL_CLK_OPENVG_AXI 143 +#define IMX6QDL_CLK_PCIE_AXI 144 +#define IMX6QDL_CLK_PWM1 145 +#define IMX6QDL_CLK_PWM2 146 +#define IMX6QDL_CLK_PWM3 147 +#define IMX6QDL_CLK_PWM4 148 +#define IMX6QDL_CLK_PER1_BCH 149 +#define IMX6QDL_CLK_GPMI_BCH_APB 150 +#define IMX6QDL_CLK_GPMI_BCH 151 +#define IMX6QDL_CLK_GPMI_IO 152 +#define IMX6QDL_CLK_GPMI_APB 153 +#define IMX6QDL_CLK_SATA 154 +#define IMX6QDL_CLK_SDMA 155 +#define IMX6QDL_CLK_SPBA 156 +#define IMX6QDL_CLK_SSI1 157 +#define IMX6QDL_CLK_SSI2 158 +#define IMX6QDL_CLK_SSI3 159 +#define IMX6QDL_CLK_UART_IPG 160 +#define IMX6QDL_CLK_UART_SERIAL 161 +#define IMX6QDL_CLK_USBOH3 162 +#define IMX6QDL_CLK_USDHC1 163 +#define IMX6QDL_CLK_USDHC2 164 +#define IMX6QDL_CLK_USDHC3 165 +#define IMX6QDL_CLK_USDHC4 166 +#define IMX6QDL_CLK_VDO_AXI 167 +#define IMX6QDL_CLK_VPU_AXI 168 +#define IMX6QDL_CLK_CKO1 169 +#define IMX6QDL_CLK_PLL1_SYS 170 +#define IMX6QDL_CLK_PLL2_BUS 171 +#define IMX6QDL_CLK_PLL3_USB_OTG 172 +#define IMX6QDL_CLK_PLL4_AUDIO 173 +#define IMX6QDL_CLK_PLL5_VIDEO 174 +#define IMX6QDL_CLK_PLL8_MLB 175 +#define IMX6QDL_CLK_PLL7_USB_HOST 176 +#define IMX6QDL_CLK_PLL6_ENET 177 +#define IMX6QDL_CLK_SSI1_IPG 178 +#define IMX6QDL_CLK_SSI2_IPG 179 +#define IMX6QDL_CLK_SSI3_IPG 180 +#define IMX6QDL_CLK_ROM 181 +#define IMX6QDL_CLK_USBPHY1 182 +#define IMX6QDL_CLK_USBPHY2 183 +#define IMX6QDL_CLK_LDB_DI0_DIV_3_5 184 +#define IMX6QDL_CLK_LDB_DI1_DIV_3_5 185 +#define IMX6QDL_CLK_SATA_REF 186 +#define IMX6QDL_CLK_SATA_REF_100M 187 +#define IMX6QDL_CLK_PCIE_REF 188 +#define IMX6QDL_CLK_PCIE_REF_125M 189 +#define IMX6QDL_CLK_ENET_REF 190 +#define IMX6QDL_CLK_USBPHY1_GATE 191 +#define IMX6QDL_CLK_USBPHY2_GATE 192 +#define IMX6QDL_CLK_PLL4_POST_DIV 193 +#define IMX6QDL_CLK_PLL5_POST_DIV 194 +#define IMX6QDL_CLK_PLL5_VIDEO_DIV 195 +#define IMX6QDL_CLK_EIM_SLOW 196 +#define IMX6QDL_CLK_SPDIF 197 +#define IMX6QDL_CLK_CKO2_SEL 198 +#define IMX6QDL_CLK_CKO2_PODF 199 +#define IMX6QDL_CLK_CKO2 200 +#define IMX6QDL_CLK_CKO 201 +#define IMX6QDL_CLK_VDOA 202 +#define IMX6QDL_CLK_PLL4_AUDIO_DIV 203 +#define IMX6QDL_CLK_LVDS1_SEL 204 +#define IMX6QDL_CLK_LVDS2_SEL 205 +#define IMX6QDL_CLK_LVDS1_GATE 206 +#define IMX6QDL_CLK_LVDS2_GATE 207 +#define IMX6QDL_CLK_ESAI_AHB 208 +#define IMX6QDL_CLK_END 209 + +#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx6sl-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx6sl-clock.h index 7cf5c99..b91dd46 100644 --- a/sys/gnu/dts/include/dt-bindings/clock/imx6sl-clock.h +++ b/sys/gnu/dts/include/dt-bindings/clock/imx6sl-clock.h @@ -145,6 +145,7 @@ #define IMX6SL_CLK_USDHC4 132 #define IMX6SL_CLK_PLL4_AUDIO_DIV 133 #define IMX6SL_CLK_SPBA 134 -#define IMX6SL_CLK_END 135 +#define IMX6SL_CLK_ENET 135 +#define IMX6SL_CLK_END 136 #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx6sx-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx6sx-clock.h new file mode 100644 index 0000000..421d8bb --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/imx6sx-clock.h @@ -0,0 +1,256 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX6SX_H +#define __DT_BINDINGS_CLOCK_IMX6SX_H + +#define IMX6SX_CLK_DUMMY 0 +#define IMX6SX_CLK_CKIL 1 +#define IMX6SX_CLK_CKIH 2 +#define IMX6SX_CLK_OSC 3 +#define IMX6SX_CLK_PLL1_SYS 4 +#define IMX6SX_CLK_PLL2_BUS 5 +#define IMX6SX_CLK_PLL3_USB_OTG 6 +#define IMX6SX_CLK_PLL4_AUDIO 7 +#define IMX6SX_CLK_PLL5_VIDEO 8 +#define IMX6SX_CLK_PLL6_ENET 9 +#define IMX6SX_CLK_PLL7_USB_HOST 10 +#define IMX6SX_CLK_USBPHY1 11 +#define IMX6SX_CLK_USBPHY2 12 +#define IMX6SX_CLK_USBPHY1_GATE 13 +#define IMX6SX_CLK_USBPHY2_GATE 14 +#define IMX6SX_CLK_PCIE_REF 15 +#define IMX6SX_CLK_PCIE_REF_125M 16 +#define IMX6SX_CLK_ENET_REF 17 +#define IMX6SX_CLK_PLL2_PFD0 18 +#define IMX6SX_CLK_PLL2_PFD1 19 +#define IMX6SX_CLK_PLL2_PFD2 20 +#define IMX6SX_CLK_PLL2_PFD3 21 +#define IMX6SX_CLK_PLL3_PFD0 22 +#define IMX6SX_CLK_PLL3_PFD1 23 +#define IMX6SX_CLK_PLL3_PFD2 24 +#define IMX6SX_CLK_PLL3_PFD3 25 +#define IMX6SX_CLK_PLL2_198M 26 +#define IMX6SX_CLK_PLL3_120M 27 +#define IMX6SX_CLK_PLL3_80M 28 +#define IMX6SX_CLK_PLL3_60M 29 +#define IMX6SX_CLK_TWD 30 +#define IMX6SX_CLK_PLL4_POST_DIV 31 +#define IMX6SX_CLK_PLL4_AUDIO_DIV 32 +#define IMX6SX_CLK_PLL5_POST_DIV 33 +#define IMX6SX_CLK_PLL5_VIDEO_DIV 34 +#define IMX6SX_CLK_STEP 35 +#define IMX6SX_CLK_PLL1_SW 36 +#define IMX6SX_CLK_OCRAM_SEL 37 +#define IMX6SX_CLK_PERIPH_PRE 38 +#define IMX6SX_CLK_PERIPH2_PRE 39 +#define IMX6SX_CLK_PERIPH_CLK2_SEL 40 +#define IMX6SX_CLK_PERIPH2_CLK2_SEL 41 +#define IMX6SX_CLK_PCIE_AXI_SEL 42 +#define IMX6SX_CLK_GPU_AXI_SEL 43 +#define IMX6SX_CLK_GPU_CORE_SEL 44 +#define IMX6SX_CLK_EIM_SLOW_SEL 45 +#define IMX6SX_CLK_USDHC1_SEL 46 +#define IMX6SX_CLK_USDHC2_SEL 47 +#define IMX6SX_CLK_USDHC3_SEL 48 +#define IMX6SX_CLK_USDHC4_SEL 49 +#define IMX6SX_CLK_SSI1_SEL 50 +#define IMX6SX_CLK_SSI2_SEL 51 +#define IMX6SX_CLK_SSI3_SEL 52 +#define IMX6SX_CLK_QSPI1_SEL 53 +#define IMX6SX_CLK_PERCLK_SEL 54 +#define IMX6SX_CLK_VID_SEL 55 +#define IMX6SX_CLK_ESAI_SEL 56 +#define IMX6SX_CLK_LDB_DI0_DIV_SEL 57 +#define IMX6SX_CLK_LDB_DI1_DIV_SEL 58 +#define IMX6SX_CLK_CAN_SEL 59 +#define IMX6SX_CLK_UART_SEL 60 +#define IMX6SX_CLK_QSPI2_SEL 61 +#define IMX6SX_CLK_LDB_DI1_SEL 62 +#define IMX6SX_CLK_LDB_DI0_SEL 63 +#define IMX6SX_CLK_SPDIF_SEL 64 +#define IMX6SX_CLK_AUDIO_SEL 65 +#define IMX6SX_CLK_ENET_PRE_SEL 66 +#define IMX6SX_CLK_ENET_SEL 67 +#define IMX6SX_CLK_M4_PRE_SEL 68 +#define IMX6SX_CLK_M4_SEL 69 +#define IMX6SX_CLK_ECSPI_SEL 70 +#define IMX6SX_CLK_LCDIF1_PRE_SEL 71 +#define IMX6SX_CLK_LCDIF2_PRE_SEL 72 +#define IMX6SX_CLK_LCDIF1_SEL 73 +#define IMX6SX_CLK_LCDIF2_SEL 74 +#define IMX6SX_CLK_DISPLAY_SEL 75 +#define IMX6SX_CLK_CSI_SEL 76 +#define IMX6SX_CLK_CKO1_SEL 77 +#define IMX6SX_CLK_CKO2_SEL 78 +#define IMX6SX_CLK_CKO 79 +#define IMX6SX_CLK_PERIPH_CLK2 80 +#define IMX6SX_CLK_PERIPH2_CLK2 81 +#define IMX6SX_CLK_IPG 82 +#define IMX6SX_CLK_GPU_CORE_PODF 83 +#define IMX6SX_CLK_GPU_AXI_PODF 84 +#define IMX6SX_CLK_LCDIF1_PODF 85 +#define IMX6SX_CLK_QSPI1_PODF 86 +#define IMX6SX_CLK_EIM_SLOW_PODF 87 +#define IMX6SX_CLK_LCDIF2_PODF 88 +#define IMX6SX_CLK_PERCLK 89 +#define IMX6SX_CLK_VID_PODF 90 +#define IMX6SX_CLK_CAN_PODF 91 +#define IMX6SX_CLK_USDHC1_PODF 92 +#define IMX6SX_CLK_USDHC2_PODF 93 +#define IMX6SX_CLK_USDHC3_PODF 94 +#define IMX6SX_CLK_USDHC4_PODF 95 +#define IMX6SX_CLK_UART_PODF 96 +#define IMX6SX_CLK_ESAI_PRED 97 +#define IMX6SX_CLK_ESAI_PODF 98 +#define IMX6SX_CLK_SSI3_PRED 99 +#define IMX6SX_CLK_SSI3_PODF 100 +#define IMX6SX_CLK_SSI1_PRED 101 +#define IMX6SX_CLK_SSI1_PODF 102 +#define IMX6SX_CLK_QSPI2_PRED 103 +#define IMX6SX_CLK_QSPI2_PODF 104 +#define IMX6SX_CLK_SSI2_PRED 105 +#define IMX6SX_CLK_SSI2_PODF 106 +#define IMX6SX_CLK_SPDIF_PRED 107 +#define IMX6SX_CLK_SPDIF_PODF 108 +#define IMX6SX_CLK_AUDIO_PRED 109 +#define IMX6SX_CLK_AUDIO_PODF 110 +#define IMX6SX_CLK_ENET_PODF 111 +#define IMX6SX_CLK_M4_PODF 112 +#define IMX6SX_CLK_ECSPI_PODF 113 +#define IMX6SX_CLK_LCDIF1_PRED 114 +#define IMX6SX_CLK_LCDIF2_PRED 115 +#define IMX6SX_CLK_DISPLAY_PODF 116 +#define IMX6SX_CLK_CSI_PODF 117 +#define IMX6SX_CLK_LDB_DI0_DIV_3_5 118 +#define IMX6SX_CLK_LDB_DI0_DIV_7 119 +#define IMX6SX_CLK_LDB_DI1_DIV_3_5 120 +#define IMX6SX_CLK_LDB_DI1_DIV_7 121 +#define IMX6SX_CLK_CKO1_PODF 122 +#define IMX6SX_CLK_CKO2_PODF 123 +#define IMX6SX_CLK_PERIPH 124 +#define IMX6SX_CLK_PERIPH2 125 +#define IMX6SX_CLK_OCRAM 126 +#define IMX6SX_CLK_AHB 127 +#define IMX6SX_CLK_MMDC_PODF 128 +#define IMX6SX_CLK_ARM 129 +#define IMX6SX_CLK_AIPS_TZ1 130 +#define IMX6SX_CLK_AIPS_TZ2 131 +#define IMX6SX_CLK_APBH_DMA 132 +#define IMX6SX_CLK_ASRC_GATE 133 +#define IMX6SX_CLK_CAAM_MEM 134 +#define IMX6SX_CLK_CAAM_ACLK 135 +#define IMX6SX_CLK_CAAM_IPG 136 +#define IMX6SX_CLK_CAN1_IPG 137 +#define IMX6SX_CLK_CAN1_SERIAL 138 +#define IMX6SX_CLK_CAN2_IPG 139 +#define IMX6SX_CLK_CAN2_SERIAL 140 +#define IMX6SX_CLK_CPU_DEBUG 141 +#define IMX6SX_CLK_DCIC1 142 +#define IMX6SX_CLK_DCIC2 143 +#define IMX6SX_CLK_AIPS_TZ3 144 +#define IMX6SX_CLK_ECSPI1 145 +#define IMX6SX_CLK_ECSPI2 146 +#define IMX6SX_CLK_ECSPI3 147 +#define IMX6SX_CLK_ECSPI4 148 +#define IMX6SX_CLK_ECSPI5 149 +#define IMX6SX_CLK_EPIT1 150 +#define IMX6SX_CLK_EPIT2 151 +#define IMX6SX_CLK_ESAI_EXTAL 152 +#define IMX6SX_CLK_WAKEUP 153 +#define IMX6SX_CLK_GPT_BUS 154 +#define IMX6SX_CLK_GPT_SERIAL 155 +#define IMX6SX_CLK_GPU 156 +#define IMX6SX_CLK_OCRAM_S 157 +#define IMX6SX_CLK_CANFD 158 +#define IMX6SX_CLK_CSI 159 +#define IMX6SX_CLK_I2C1 160 +#define IMX6SX_CLK_I2C2 161 +#define IMX6SX_CLK_I2C3 162 +#define IMX6SX_CLK_OCOTP 163 +#define IMX6SX_CLK_IOMUXC 164 +#define IMX6SX_CLK_IPMUX1 165 +#define IMX6SX_CLK_IPMUX2 166 +#define IMX6SX_CLK_IPMUX3 167 +#define IMX6SX_CLK_TZASC1 168 +#define IMX6SX_CLK_LCDIF_APB 169 +#define IMX6SX_CLK_PXP_AXI 170 +#define IMX6SX_CLK_M4 171 +#define IMX6SX_CLK_ENET 172 +#define IMX6SX_CLK_DISPLAY_AXI 173 +#define IMX6SX_CLK_LCDIF2_PIX 174 +#define IMX6SX_CLK_LCDIF1_PIX 175 +#define IMX6SX_CLK_LDB_DI0 176 +#define IMX6SX_CLK_QSPI1 177 +#define IMX6SX_CLK_MLB 178 +#define IMX6SX_CLK_MMDC_P0_FAST 179 +#define IMX6SX_CLK_MMDC_P0_IPG 180 +#define IMX6SX_CLK_AXI 181 +#define IMX6SX_CLK_PCIE_AXI 182 +#define IMX6SX_CLK_QSPI2 183 +#define IMX6SX_CLK_PER1_BCH 184 +#define IMX6SX_CLK_PER2_MAIN 185 +#define IMX6SX_CLK_PWM1 186 +#define IMX6SX_CLK_PWM2 187 +#define IMX6SX_CLK_PWM3 188 +#define IMX6SX_CLK_PWM4 189 +#define IMX6SX_CLK_GPMI_BCH_APB 190 +#define IMX6SX_CLK_GPMI_BCH 191 +#define IMX6SX_CLK_GPMI_IO 192 +#define IMX6SX_CLK_GPMI_APB 193 +#define IMX6SX_CLK_ROM 194 +#define IMX6SX_CLK_SDMA 195 +#define IMX6SX_CLK_SPBA 196 +#define IMX6SX_CLK_SPDIF 197 +#define IMX6SX_CLK_SSI1_IPG 198 +#define IMX6SX_CLK_SSI2_IPG 199 +#define IMX6SX_CLK_SSI3_IPG 200 +#define IMX6SX_CLK_SSI1 201 +#define IMX6SX_CLK_SSI2 202 +#define IMX6SX_CLK_SSI3 203 +#define IMX6SX_CLK_UART_IPG 204 +#define IMX6SX_CLK_UART_SERIAL 205 +#define IMX6SX_CLK_SAI1 206 +#define IMX6SX_CLK_SAI2 207 +#define IMX6SX_CLK_USBOH3 208 +#define IMX6SX_CLK_USDHC1 209 +#define IMX6SX_CLK_USDHC2 210 +#define IMX6SX_CLK_USDHC3 211 +#define IMX6SX_CLK_USDHC4 212 +#define IMX6SX_CLK_EIM_SLOW 213 +#define IMX6SX_CLK_PWM8 214 +#define IMX6SX_CLK_VADC 215 +#define IMX6SX_CLK_GIS 216 +#define IMX6SX_CLK_I2C4 217 +#define IMX6SX_CLK_PWM5 218 +#define IMX6SX_CLK_PWM6 219 +#define IMX6SX_CLK_PWM7 220 +#define IMX6SX_CLK_CKO1 221 +#define IMX6SX_CLK_CKO2 222 +#define IMX6SX_CLK_IPP_DI0 223 +#define IMX6SX_CLK_IPP_DI1 224 +#define IMX6SX_CLK_ENET_AHB 225 +#define IMX6SX_CLK_OCRAM_PODF 226 +#define IMX6SX_CLK_GPT_3M 227 +#define IMX6SX_CLK_ENET_PTP 228 +#define IMX6SX_CLK_ENET_PTP_REF 229 +#define IMX6SX_CLK_ENET2_REF 230 +#define IMX6SX_CLK_ENET2_REF_125M 231 +#define IMX6SX_CLK_AUDIO 232 +#define IMX6SX_CLK_LVDS1_SEL 233 +#define IMX6SX_CLK_LVDS1_OUT 234 +#define IMX6SX_CLK_ASRC_IPG 235 +#define IMX6SX_CLK_ASRC_MEM 236 +#define IMX6SX_CLK_SAI1_IPG 237 +#define IMX6SX_CLK_SAI2_IPG 238 +#define IMX6SX_CLK_ESAI_IPG 239 +#define IMX6SX_CLK_ESAI_MEM 240 +#define IMX6SX_CLK_CLK_END 241 + +#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/lsi,axm5516-clks.h b/sys/gnu/dts/include/dt-bindings/clock/lsi,axm5516-clks.h new file mode 100644 index 0000000..beb41ac --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/lsi,axm5516-clks.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2014 LSI Corporation + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + */ + +#ifndef _DT_BINDINGS_CLK_AXM5516_H +#define _DT_BINDINGS_CLK_AXM5516_H + +#define AXXIA_CLK_FAB_PLL 0 +#define AXXIA_CLK_CPU_PLL 1 +#define AXXIA_CLK_SYS_PLL 2 +#define AXXIA_CLK_SM0_PLL 3 +#define AXXIA_CLK_SM1_PLL 4 +#define AXXIA_CLK_FAB_DIV 5 +#define AXXIA_CLK_SYS_DIV 6 +#define AXXIA_CLK_NRCP_DIV 7 +#define AXXIA_CLK_CPU0_DIV 8 +#define AXXIA_CLK_CPU1_DIV 9 +#define AXXIA_CLK_CPU2_DIV 10 +#define AXXIA_CLK_CPU3_DIV 11 +#define AXXIA_CLK_PER_DIV 12 +#define AXXIA_CLK_MMC_DIV 13 +#define AXXIA_CLK_FAB 14 +#define AXXIA_CLK_SYS 15 +#define AXXIA_CLK_NRCP 16 +#define AXXIA_CLK_CPU0 17 +#define AXXIA_CLK_CPU1 18 +#define AXXIA_CLK_CPU2 19 +#define AXXIA_CLK_CPU3 20 +#define AXXIA_CLK_PER 21 +#define AXXIA_CLK_MMC 22 + +#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-apq8084.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-apq8084.h new file mode 100644 index 0000000..2c0da56 --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-apq8084.h @@ -0,0 +1,351 @@ +/* + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_APQ_GCC_8084_H +#define _DT_BINDINGS_CLK_APQ_GCC_8084_H + +#define GPLL0 0 +#define GPLL0_VOTE 1 +#define GPLL1 2 +#define GPLL1_VOTE 3 +#define GPLL2 4 +#define GPLL2_VOTE 5 +#define GPLL3 6 +#define GPLL3_VOTE 7 +#define GPLL4 8 +#define GPLL4_VOTE 9 +#define CONFIG_NOC_CLK_SRC 10 +#define PERIPH_NOC_CLK_SRC 11 +#define SYSTEM_NOC_CLK_SRC 12 +#define BLSP_UART_SIM_CLK_SRC 13 +#define QDSS_TSCTR_CLK_SRC 14 +#define UFS_AXI_CLK_SRC 15 +#define RPM_CLK_SRC 16 +#define KPSS_AHB_CLK_SRC 17 +#define QDSS_AT_CLK_SRC 18 +#define BIMC_DDR_CLK_SRC 19 +#define USB30_MASTER_CLK_SRC 20 +#define USB30_SEC_MASTER_CLK_SRC 21 +#define USB_HSIC_AHB_CLK_SRC 22 +#define MMSS_BIMC_GFX_CLK_SRC 23 +#define QDSS_STM_CLK_SRC 24 +#define ACC_CLK_SRC 25 +#define SEC_CTRL_CLK_SRC 26 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 27 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 28 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 29 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 30 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 31 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 32 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC 33 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC 34 +#define BLSP1_QUP5_I2C_APPS_CLK_SRC 35 +#define BLSP1_QUP5_SPI_APPS_CLK_SRC 36 +#define BLSP1_QUP6_I2C_APPS_CLK_SRC 37 +#define BLSP1_QUP6_SPI_APPS_CLK_SRC 38 +#define BLSP1_UART1_APPS_CLK_SRC 39 +#define BLSP1_UART2_APPS_CLK_SRC 40 +#define BLSP1_UART3_APPS_CLK_SRC 41 +#define BLSP1_UART4_APPS_CLK_SRC 42 +#define BLSP1_UART5_APPS_CLK_SRC 43 +#define BLSP1_UART6_APPS_CLK_SRC 44 +#define BLSP2_QUP1_I2C_APPS_CLK_SRC 45 +#define BLSP2_QUP1_SPI_APPS_CLK_SRC 46 +#define BLSP2_QUP2_I2C_APPS_CLK_SRC 47 +#define BLSP2_QUP2_SPI_APPS_CLK_SRC 48 +#define BLSP2_QUP3_I2C_APPS_CLK_SRC 49 +#define BLSP2_QUP3_SPI_APPS_CLK_SRC 50 +#define BLSP2_QUP4_I2C_APPS_CLK_SRC 51 +#define BLSP2_QUP4_SPI_APPS_CLK_SRC 52 +#define BLSP2_QUP5_I2C_APPS_CLK_SRC 53 +#define BLSP2_QUP5_SPI_APPS_CLK_SRC 54 +#define BLSP2_QUP6_I2C_APPS_CLK_SRC 55 +#define BLSP2_QUP6_SPI_APPS_CLK_SRC 56 +#define BLSP2_UART1_APPS_CLK_SRC 57 +#define BLSP2_UART2_APPS_CLK_SRC 58 +#define BLSP2_UART3_APPS_CLK_SRC 59 +#define BLSP2_UART4_APPS_CLK_SRC 60 +#define BLSP2_UART5_APPS_CLK_SRC 61 +#define BLSP2_UART6_APPS_CLK_SRC 62 +#define CE1_CLK_SRC 63 +#define CE2_CLK_SRC 64 +#define CE3_CLK_SRC 65 +#define GP1_CLK_SRC 66 +#define GP2_CLK_SRC 67 +#define GP3_CLK_SRC 68 +#define PDM2_CLK_SRC 69 +#define QDSS_TRACECLKIN_CLK_SRC 70 +#define RBCPR_CLK_SRC 71 +#define SATA_ASIC0_CLK_SRC 72 +#define SATA_PMALIVE_CLK_SRC 73 +#define SATA_RX_CLK_SRC 74 +#define SATA_RX_OOB_CLK_SRC 75 +#define SDCC1_APPS_CLK_SRC 76 +#define SDCC2_APPS_CLK_SRC 77 +#define SDCC3_APPS_CLK_SRC 78 +#define SDCC4_APPS_CLK_SRC 79 +#define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK 80 +#define SPMI_AHB_CLK_SRC 81 +#define SPMI_SER_CLK_SRC 82 +#define TSIF_REF_CLK_SRC 83 +#define USB30_MOCK_UTMI_CLK_SRC 84 +#define USB30_SEC_MOCK_UTMI_CLK_SRC 85 +#define USB_HS_SYSTEM_CLK_SRC 86 +#define USB_HSIC_CLK_SRC 87 +#define USB_HSIC_IO_CAL_CLK_SRC 88 +#define USB_HSIC_MOCK_UTMI_CLK_SRC 89 +#define USB_HSIC_SYSTEM_CLK_SRC 90 +#define GCC_BAM_DMA_AHB_CLK 91 +#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK 92 +#define DDR_CLK_SRC 93 +#define GCC_BIMC_CFG_AHB_CLK 94 +#define GCC_BIMC_CLK 95 +#define GCC_BIMC_KPSS_AXI_CLK 96 +#define GCC_BIMC_SLEEP_CLK 97 +#define GCC_BIMC_SYSNOC_AXI_CLK 98 +#define GCC_BIMC_XO_CLK 99 +#define GCC_BLSP1_AHB_CLK 100 +#define GCC_BLSP1_SLEEP_CLK 101 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 102 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 103 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 104 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 105 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 106 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 107 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 108 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 109 +#define GCC_BLSP1_QUP5_I2C_APPS_CLK 110 +#define GCC_BLSP1_QUP5_SPI_APPS_CLK 111 +#define GCC_BLSP1_QUP6_I2C_APPS_CLK 112 +#define GCC_BLSP1_QUP6_SPI_APPS_CLK 113 +#define GCC_BLSP1_UART1_APPS_CLK 114 +#define GCC_BLSP1_UART1_SIM_CLK 115 +#define GCC_BLSP1_UART2_APPS_CLK 116 +#define GCC_BLSP1_UART2_SIM_CLK 117 +#define GCC_BLSP1_UART3_APPS_CLK 118 +#define GCC_BLSP1_UART3_SIM_CLK 119 +#define GCC_BLSP1_UART4_APPS_CLK 120 +#define GCC_BLSP1_UART4_SIM_CLK 121 +#define GCC_BLSP1_UART5_APPS_CLK 122 +#define GCC_BLSP1_UART5_SIM_CLK 123 +#define GCC_BLSP1_UART6_APPS_CLK 124 +#define GCC_BLSP1_UART6_SIM_CLK 125 +#define GCC_BLSP2_AHB_CLK 126 +#define GCC_BLSP2_SLEEP_CLK 127 +#define GCC_BLSP2_QUP1_I2C_APPS_CLK 128 +#define GCC_BLSP2_QUP1_SPI_APPS_CLK 129 +#define GCC_BLSP2_QUP2_I2C_APPS_CLK 130 +#define GCC_BLSP2_QUP2_SPI_APPS_CLK 131 +#define GCC_BLSP2_QUP3_I2C_APPS_CLK 132 +#define GCC_BLSP2_QUP3_SPI_APPS_CLK 133 +#define GCC_BLSP2_QUP4_I2C_APPS_CLK 134 +#define GCC_BLSP2_QUP4_SPI_APPS_CLK 135 +#define GCC_BLSP2_QUP5_I2C_APPS_CLK 136 +#define GCC_BLSP2_QUP5_SPI_APPS_CLK 137 +#define GCC_BLSP2_QUP6_I2C_APPS_CLK 138 +#define GCC_BLSP2_QUP6_SPI_APPS_CLK 139 +#define GCC_BLSP2_UART1_APPS_CLK 140 +#define GCC_BLSP2_UART1_SIM_CLK 141 +#define GCC_BLSP2_UART2_APPS_CLK 142 +#define GCC_BLSP2_UART2_SIM_CLK 143 +#define GCC_BLSP2_UART3_APPS_CLK 144 +#define GCC_BLSP2_UART3_SIM_CLK 145 +#define GCC_BLSP2_UART4_APPS_CLK 146 +#define GCC_BLSP2_UART4_SIM_CLK 147 +#define GCC_BLSP2_UART5_APPS_CLK 148 +#define GCC_BLSP2_UART5_SIM_CLK 149 +#define GCC_BLSP2_UART6_APPS_CLK 150 +#define GCC_BLSP2_UART6_SIM_CLK 151 +#define GCC_BOOT_ROM_AHB_CLK 152 +#define GCC_CE1_AHB_CLK 153 +#define GCC_CE1_AXI_CLK 154 +#define GCC_CE1_CLK 155 +#define GCC_CE2_AHB_CLK 156 +#define GCC_CE2_AXI_CLK 157 +#define GCC_CE2_CLK 158 +#define GCC_CE3_AHB_CLK 159 +#define GCC_CE3_AXI_CLK 160 +#define GCC_CE3_CLK 161 +#define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK 162 +#define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK 163 +#define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK 164 +#define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK 165 +#define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK 166 +#define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK 167 +#define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK 168 +#define GCC_CNOC_BUS_TIMEOUT7_AHB_CLK 169 +#define GCC_CFG_NOC_AHB_CLK 170 +#define GCC_CFG_NOC_DDR_CFG_CLK 171 +#define GCC_CFG_NOC_RPM_AHB_CLK 172 +#define GCC_COPSS_SMMU_AHB_CLK 173 +#define GCC_COPSS_SMMU_AXI_CLK 174 +#define GCC_DCD_XO_CLK 175 +#define GCC_BIMC_DDR_CH0_CLK 176 +#define GCC_BIMC_DDR_CH1_CLK 177 +#define GCC_BIMC_DDR_CPLL0_CLK 178 +#define GCC_BIMC_DDR_CPLL1_CLK 179 +#define GCC_BIMC_GFX_CLK 180 +#define GCC_DDR_DIM_CFG_CLK 181 +#define GCC_DDR_DIM_SLEEP_CLK 182 +#define GCC_DEHR_CLK 183 +#define GCC_AHB_CLK 184 +#define GCC_IM_SLEEP_CLK 185 +#define GCC_XO_CLK 186 +#define GCC_XO_DIV4_CLK 187 +#define GCC_GP1_CLK 188 +#define GCC_GP2_CLK 189 +#define GCC_GP3_CLK 190 +#define GCC_IMEM_AXI_CLK 191 +#define GCC_IMEM_CFG_AHB_CLK 192 +#define GCC_KPSS_AHB_CLK 193 +#define GCC_KPSS_AXI_CLK 194 +#define GCC_LPASS_MPORT_AXI_CLK 195 +#define GCC_LPASS_Q6_AXI_CLK 196 +#define GCC_LPASS_SWAY_CLK 197 +#define GCC_MMSS_BIMC_GFX_CLK 198 +#define GCC_MMSS_NOC_AT_CLK 199 +#define GCC_MMSS_NOC_CFG_AHB_CLK 200 +#define GCC_MMSS_VPU_MAPLE_SYS_NOC_AXI_CLK 201 +#define GCC_OCMEM_NOC_CFG_AHB_CLK 202 +#define GCC_OCMEM_SYS_NOC_AXI_CLK 203 +#define GCC_MPM_AHB_CLK 204 +#define GCC_MSG_RAM_AHB_CLK 205 +#define GCC_NOC_CONF_XPU_AHB_CLK 206 +#define GCC_PDM2_CLK 207 +#define GCC_PDM_AHB_CLK 208 +#define GCC_PDM_XO4_CLK 209 +#define GCC_PERIPH_NOC_AHB_CLK 210 +#define GCC_PERIPH_NOC_AT_CLK 211 +#define GCC_PERIPH_NOC_CFG_AHB_CLK 212 +#define GCC_PERIPH_NOC_USB_HSIC_AHB_CLK 213 +#define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK 214 +#define GCC_PERIPH_XPU_AHB_CLK 215 +#define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK 216 +#define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK 217 +#define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK 218 +#define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK 219 +#define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK 220 +#define GCC_PRNG_AHB_CLK 221 +#define GCC_QDSS_AT_CLK 222 +#define GCC_QDSS_CFG_AHB_CLK 223 +#define GCC_QDSS_DAP_AHB_CLK 224 +#define GCC_QDSS_DAP_CLK 225 +#define GCC_QDSS_ETR_USB_CLK 226 +#define GCC_QDSS_STM_CLK 227 +#define GCC_QDSS_TRACECLKIN_CLK 228 +#define GCC_QDSS_TSCTR_DIV16_CLK 229 +#define GCC_QDSS_TSCTR_DIV2_CLK 230 +#define GCC_QDSS_TSCTR_DIV3_CLK 231 +#define GCC_QDSS_TSCTR_DIV4_CLK 232 +#define GCC_QDSS_TSCTR_DIV8_CLK 233 +#define GCC_QDSS_RBCPR_XPU_AHB_CLK 234 +#define GCC_RBCPR_AHB_CLK 235 +#define GCC_RBCPR_CLK 236 +#define GCC_RPM_BUS_AHB_CLK 237 +#define GCC_RPM_PROC_HCLK 238 +#define GCC_RPM_SLEEP_CLK 239 +#define GCC_RPM_TIMER_CLK 240 +#define GCC_SATA_ASIC0_CLK 241 +#define GCC_SATA_AXI_CLK 242 +#define GCC_SATA_CFG_AHB_CLK 243 +#define GCC_SATA_PMALIVE_CLK 244 +#define GCC_SATA_RX_CLK 245 +#define GCC_SATA_RX_OOB_CLK 246 +#define GCC_SDCC1_AHB_CLK 247 +#define GCC_SDCC1_APPS_CLK 248 +#define GCC_SDCC1_CDCCAL_FF_CLK 249 +#define GCC_SDCC1_CDCCAL_SLEEP_CLK 250 +#define GCC_SDCC2_AHB_CLK 251 +#define GCC_SDCC2_APPS_CLK 252 +#define GCC_SDCC2_INACTIVITY_TIMERS_CLK 253 +#define GCC_SDCC3_AHB_CLK 254 +#define GCC_SDCC3_APPS_CLK 255 +#define GCC_SDCC3_INACTIVITY_TIMERS_CLK 256 +#define GCC_SDCC4_AHB_CLK 257 +#define GCC_SDCC4_APPS_CLK 258 +#define GCC_SDCC4_INACTIVITY_TIMERS_CLK 259 +#define GCC_SEC_CTRL_ACC_CLK 260 +#define GCC_SEC_CTRL_AHB_CLK 261 +#define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK 262 +#define GCC_SEC_CTRL_CLK 263 +#define GCC_SEC_CTRL_SENSE_CLK 264 +#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 265 +#define GCC_SNOC_BUS_TIMEOUT3_AHB_CLK 266 +#define GCC_SPDM_BIMC_CY_CLK 267 +#define GCC_SPDM_CFG_AHB_CLK 268 +#define GCC_SPDM_DEBUG_CY_CLK 269 +#define GCC_SPDM_FF_CLK 270 +#define GCC_SPDM_MSTR_AHB_CLK 271 +#define GCC_SPDM_PNOC_CY_CLK 272 +#define GCC_SPDM_RPM_CY_CLK 273 +#define GCC_SPDM_SNOC_CY_CLK 274 +#define GCC_SPMI_AHB_CLK 275 +#define GCC_SPMI_CNOC_AHB_CLK 276 +#define GCC_SPMI_SER_CLK 277 +#define GCC_SPSS_AHB_CLK 278 +#define GCC_SNOC_CNOC_AHB_CLK 279 +#define GCC_SNOC_PNOC_AHB_CLK 280 +#define GCC_SYS_NOC_AT_CLK 281 +#define GCC_SYS_NOC_AXI_CLK 282 +#define GCC_SYS_NOC_KPSS_AHB_CLK 283 +#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 284 +#define GCC_SYS_NOC_UFS_AXI_CLK 285 +#define GCC_SYS_NOC_USB3_AXI_CLK 286 +#define GCC_SYS_NOC_USB3_SEC_AXI_CLK 287 +#define GCC_TCSR_AHB_CLK 288 +#define GCC_TLMM_AHB_CLK 289 +#define GCC_TLMM_CLK 290 +#define GCC_TSIF_AHB_CLK 291 +#define GCC_TSIF_INACTIVITY_TIMERS_CLK 292 +#define GCC_TSIF_REF_CLK 293 +#define GCC_UFS_AHB_CLK 294 +#define GCC_UFS_AXI_CLK 295 +#define GCC_UFS_RX_CFG_CLK 296 +#define GCC_UFS_RX_SYMBOL_0_CLK 297 +#define GCC_UFS_RX_SYMBOL_1_CLK 298 +#define GCC_UFS_TX_CFG_CLK 299 +#define GCC_UFS_TX_SYMBOL_0_CLK 300 +#define GCC_UFS_TX_SYMBOL_1_CLK 301 +#define GCC_USB2A_PHY_SLEEP_CLK 302 +#define GCC_USB2B_PHY_SLEEP_CLK 303 +#define GCC_USB30_MASTER_CLK 304 +#define GCC_USB30_MOCK_UTMI_CLK 305 +#define GCC_USB30_SLEEP_CLK 306 +#define GCC_USB30_SEC_MASTER_CLK 307 +#define GCC_USB30_SEC_MOCK_UTMI_CLK 308 +#define GCC_USB30_SEC_SLEEP_CLK 309 +#define GCC_USB_HS_AHB_CLK 310 +#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 311 +#define GCC_USB_HS_SYSTEM_CLK 312 +#define GCC_USB_HSIC_AHB_CLK 313 +#define GCC_USB_HSIC_CLK 314 +#define GCC_USB_HSIC_IO_CAL_CLK 315 +#define GCC_USB_HSIC_IO_CAL_SLEEP_CLK 316 +#define GCC_USB_HSIC_MOCK_UTMI_CLK 317 +#define GCC_USB_HSIC_SYSTEM_CLK 318 +#define PCIE_0_AUX_CLK_SRC 319 +#define PCIE_0_PIPE_CLK_SRC 320 +#define PCIE_1_AUX_CLK_SRC 321 +#define PCIE_1_PIPE_CLK_SRC 322 +#define GCC_PCIE_0_AUX_CLK 323 +#define GCC_PCIE_0_CFG_AHB_CLK 324 +#define GCC_PCIE_0_MSTR_AXI_CLK 325 +#define GCC_PCIE_0_PIPE_CLK 326 +#define GCC_PCIE_0_SLV_AXI_CLK 327 +#define GCC_PCIE_1_AUX_CLK 328 +#define GCC_PCIE_1_CFG_AHB_CLK 329 +#define GCC_PCIE_1_MSTR_AXI_CLK 330 +#define GCC_PCIE_1_PIPE_CLK 331 +#define GCC_PCIE_1_SLV_AXI_CLK 332 + +#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-ipq806x.h new file mode 100644 index 0000000..b857cad --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-ipq806x.h @@ -0,0 +1,293 @@ +/* + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_GCC_IPQ806X_H +#define _DT_BINDINGS_CLK_GCC_IPQ806X_H + +#define AFAB_CLK_SRC 0 +#define QDSS_STM_CLK 1 +#define SCSS_A_CLK 2 +#define SCSS_H_CLK 3 +#define AFAB_CORE_CLK 4 +#define SCSS_XO_SRC_CLK 5 +#define AFAB_EBI1_CH0_A_CLK 6 +#define AFAB_EBI1_CH1_A_CLK 7 +#define AFAB_AXI_S0_FCLK 8 +#define AFAB_AXI_S1_FCLK 9 +#define AFAB_AXI_S2_FCLK 10 +#define AFAB_AXI_S3_FCLK 11 +#define AFAB_AXI_S4_FCLK 12 +#define SFAB_CORE_CLK 13 +#define SFAB_AXI_S0_FCLK 14 +#define SFAB_AXI_S1_FCLK 15 +#define SFAB_AXI_S2_FCLK 16 +#define SFAB_AXI_S3_FCLK 17 +#define SFAB_AXI_S4_FCLK 18 +#define SFAB_AXI_S5_FCLK 19 +#define SFAB_AHB_S0_FCLK 20 +#define SFAB_AHB_S1_FCLK 21 +#define SFAB_AHB_S2_FCLK 22 +#define SFAB_AHB_S3_FCLK 23 +#define SFAB_AHB_S4_FCLK 24 +#define SFAB_AHB_S5_FCLK 25 +#define SFAB_AHB_S6_FCLK 26 +#define SFAB_AHB_S7_FCLK 27 +#define QDSS_AT_CLK_SRC 28 +#define QDSS_AT_CLK 29 +#define QDSS_TRACECLKIN_CLK_SRC 30 +#define QDSS_TRACECLKIN_CLK 31 +#define QDSS_TSCTR_CLK_SRC 32 +#define QDSS_TSCTR_CLK 33 +#define SFAB_ADM0_M0_A_CLK 34 +#define SFAB_ADM0_M1_A_CLK 35 +#define SFAB_ADM0_M2_H_CLK 36 +#define ADM0_CLK 37 +#define ADM0_PBUS_CLK 38 +#define IMEM0_A_CLK 39 +#define QDSS_H_CLK 40 +#define PCIE_A_CLK 41 +#define PCIE_AUX_CLK 42 +#define PCIE_H_CLK 43 +#define PCIE_PHY_CLK 44 +#define SFAB_CLK_SRC 45 +#define SFAB_LPASS_Q6_A_CLK 46 +#define SFAB_AFAB_M_A_CLK 47 +#define AFAB_SFAB_M0_A_CLK 48 +#define AFAB_SFAB_M1_A_CLK 49 +#define SFAB_SATA_S_H_CLK 50 +#define DFAB_CLK_SRC 51 +#define DFAB_CLK 52 +#define SFAB_DFAB_M_A_CLK 53 +#define DFAB_SFAB_M_A_CLK 54 +#define DFAB_SWAY0_H_CLK 55 +#define DFAB_SWAY1_H_CLK 56 +#define DFAB_ARB0_H_CLK 57 +#define DFAB_ARB1_H_CLK 58 +#define PPSS_H_CLK 59 +#define PPSS_PROC_CLK 60 +#define PPSS_TIMER0_CLK 61 +#define PPSS_TIMER1_CLK 62 +#define PMEM_A_CLK 63 +#define DMA_BAM_H_CLK 64 +#define SIC_H_CLK 65 +#define SPS_TIC_H_CLK 66 +#define CFPB_2X_CLK_SRC 67 +#define CFPB_CLK 68 +#define CFPB0_H_CLK 69 +#define CFPB1_H_CLK 70 +#define CFPB2_H_CLK 71 +#define SFAB_CFPB_M_H_CLK 72 +#define CFPB_MASTER_H_CLK 73 +#define SFAB_CFPB_S_H_CLK 74 +#define CFPB_SPLITTER_H_CLK 75 +#define TSIF_H_CLK 76 +#define TSIF_INACTIVITY_TIMERS_CLK 77 +#define TSIF_REF_SRC 78 +#define TSIF_REF_CLK 79 +#define CE1_H_CLK 80 +#define CE1_CORE_CLK 81 +#define CE1_SLEEP_CLK 82 +#define CE2_H_CLK 83 +#define CE2_CORE_CLK 84 +#define SFPB_H_CLK_SRC 85 +#define SFPB_H_CLK 86 +#define SFAB_SFPB_M_H_CLK 87 +#define SFAB_SFPB_S_H_CLK 88 +#define RPM_PROC_CLK 89 +#define RPM_BUS_H_CLK 90 +#define RPM_SLEEP_CLK 91 +#define RPM_TIMER_CLK 92 +#define RPM_MSG_RAM_H_CLK 93 +#define PMIC_ARB0_H_CLK 94 +#define PMIC_ARB1_H_CLK 95 +#define PMIC_SSBI2_SRC 96 +#define PMIC_SSBI2_CLK 97 +#define SDC1_H_CLK 98 +#define SDC2_H_CLK 99 +#define SDC3_H_CLK 100 +#define SDC4_H_CLK 101 +#define SDC1_SRC 102 +#define SDC1_CLK 103 +#define SDC2_SRC 104 +#define SDC2_CLK 105 +#define SDC3_SRC 106 +#define SDC3_CLK 107 +#define SDC4_SRC 108 +#define SDC4_CLK 109 +#define USB_HS1_H_CLK 110 +#define USB_HS1_XCVR_SRC 111 +#define USB_HS1_XCVR_CLK 112 +#define USB_HSIC_H_CLK 113 +#define USB_HSIC_XCVR_SRC 114 +#define USB_HSIC_XCVR_CLK 115 +#define USB_HSIC_SYSTEM_CLK_SRC 116 +#define USB_HSIC_SYSTEM_CLK 117 +#define CFPB0_C0_H_CLK 118 +#define CFPB0_D0_H_CLK 119 +#define CFPB0_C1_H_CLK 120 +#define CFPB0_D1_H_CLK 121 +#define USB_FS1_H_CLK 122 +#define USB_FS1_XCVR_SRC 123 +#define USB_FS1_XCVR_CLK 124 +#define USB_FS1_SYSTEM_CLK 125 +#define GSBI_COMMON_SIM_SRC 126 +#define GSBI1_H_CLK 127 +#define GSBI2_H_CLK 128 +#define GSBI3_H_CLK 129 +#define GSBI4_H_CLK 130 +#define GSBI5_H_CLK 131 +#define GSBI6_H_CLK 132 +#define GSBI7_H_CLK 133 +#define GSBI1_QUP_SRC 134 +#define GSBI1_QUP_CLK 135 +#define GSBI2_QUP_SRC 136 +#define GSBI2_QUP_CLK 137 +#define GSBI3_QUP_SRC 138 +#define GSBI3_QUP_CLK 139 +#define GSBI4_QUP_SRC 140 +#define GSBI4_QUP_CLK 141 +#define GSBI5_QUP_SRC 142 +#define GSBI5_QUP_CLK 143 +#define GSBI6_QUP_SRC 144 +#define GSBI6_QUP_CLK 145 +#define GSBI7_QUP_SRC 146 +#define GSBI7_QUP_CLK 147 +#define GSBI1_UART_SRC 148 +#define GSBI1_UART_CLK 149 +#define GSBI2_UART_SRC 150 +#define GSBI2_UART_CLK 151 +#define GSBI3_UART_SRC 152 +#define GSBI3_UART_CLK 153 +#define GSBI4_UART_SRC 154 +#define GSBI4_UART_CLK 155 +#define GSBI5_UART_SRC 156 +#define GSBI5_UART_CLK 157 +#define GSBI6_UART_SRC 158 +#define GSBI6_UART_CLK 159 +#define GSBI7_UART_SRC 160 +#define GSBI7_UART_CLK 161 +#define GSBI1_SIM_CLK 162 +#define GSBI2_SIM_CLK 163 +#define GSBI3_SIM_CLK 164 +#define GSBI4_SIM_CLK 165 +#define GSBI5_SIM_CLK 166 +#define GSBI6_SIM_CLK 167 +#define GSBI7_SIM_CLK 168 +#define USB_HSIC_HSIC_CLK_SRC 169 +#define USB_HSIC_HSIC_CLK 170 +#define USB_HSIC_HSIO_CAL_CLK 171 +#define SPDM_CFG_H_CLK 172 +#define SPDM_MSTR_H_CLK 173 +#define SPDM_FF_CLK_SRC 174 +#define SPDM_FF_CLK 175 +#define SEC_CTRL_CLK 176 +#define SEC_CTRL_ACC_CLK_SRC 177 +#define SEC_CTRL_ACC_CLK 178 +#define TLMM_H_CLK 179 +#define TLMM_CLK 180 +#define SATA_H_CLK 181 +#define SATA_CLK_SRC 182 +#define SATA_RXOOB_CLK 183 +#define SATA_PMALIVE_CLK 184 +#define SATA_PHY_REF_CLK 185 +#define SATA_A_CLK 186 +#define SATA_PHY_CFG_CLK 187 +#define TSSC_CLK_SRC 188 +#define TSSC_CLK 189 +#define PDM_SRC 190 +#define PDM_CLK 191 +#define GP0_SRC 192 +#define GP0_CLK 193 +#define GP1_SRC 194 +#define GP1_CLK 195 +#define GP2_SRC 196 +#define GP2_CLK 197 +#define MPM_CLK 198 +#define EBI1_CLK_SRC 199 +#define EBI1_CH0_CLK 200 +#define EBI1_CH1_CLK 201 +#define EBI1_2X_CLK 202 +#define EBI1_CH0_DQ_CLK 203 +#define EBI1_CH1_DQ_CLK 204 +#define EBI1_CH0_CA_CLK 205 +#define EBI1_CH1_CA_CLK 206 +#define EBI1_XO_CLK 207 +#define SFAB_SMPSS_S_H_CLK 208 +#define PRNG_SRC 209 +#define PRNG_CLK 210 +#define PXO_SRC 211 +#define SPDM_CY_PORT0_CLK 212 +#define SPDM_CY_PORT1_CLK 213 +#define SPDM_CY_PORT2_CLK 214 +#define SPDM_CY_PORT3_CLK 215 +#define SPDM_CY_PORT4_CLK 216 +#define SPDM_CY_PORT5_CLK 217 +#define SPDM_CY_PORT6_CLK 218 +#define SPDM_CY_PORT7_CLK 219 +#define PLL0 220 +#define PLL0_VOTE 221 +#define PLL3 222 +#define PLL3_VOTE 223 +#define PLL4 224 +#define PLL4_VOTE 225 +#define PLL8 226 +#define PLL8_VOTE 227 +#define PLL9 228 +#define PLL10 229 +#define PLL11 230 +#define PLL12 231 +#define PLL14 232 +#define PLL14_VOTE 233 +#define PLL18 234 +#define CE5_SRC 235 +#define CE5_H_CLK 236 +#define CE5_CORE_CLK 237 +#define CE3_SLEEP_CLK 238 +#define SFAB_AHB_S8_FCLK 239 +#define SPDM_CY_PORT8_CLK 246 +#define PCIE_ALT_REF_SRC 247 +#define PCIE_ALT_REF_CLK 248 +#define PCIE_1_A_CLK 249 +#define PCIE_1_AUX_CLK 250 +#define PCIE_1_H_CLK 251 +#define PCIE_1_PHY_CLK 252 +#define PCIE_1_ALT_REF_SRC 253 +#define PCIE_1_ALT_REF_CLK 254 +#define PCIE_2_A_CLK 255 +#define PCIE_2_AUX_CLK 256 +#define PCIE_2_H_CLK 257 +#define PCIE_2_PHY_CLK 258 +#define PCIE_2_ALT_REF_SRC 259 +#define PCIE_2_ALT_REF_CLK 260 +#define EBI2_CLK 261 +#define USB30_SLEEP_CLK 262 +#define USB30_UTMI_SRC 263 +#define USB30_0_UTMI_CLK 264 +#define USB30_1_UTMI_CLK 265 +#define USB30_MASTER_SRC 266 +#define USB30_0_MASTER_CLK 267 +#define USB30_1_MASTER_CLK 268 +#define GMAC_CORE1_CLK_SRC 269 +#define GMAC_CORE2_CLK_SRC 270 +#define GMAC_CORE3_CLK_SRC 271 +#define GMAC_CORE4_CLK_SRC 272 +#define GMAC_CORE1_CLK 273 +#define GMAC_CORE2_CLK 274 +#define GMAC_CORE3_CLK 275 +#define GMAC_CORE4_CLK 276 +#define UBI32_CORE1_CLK_SRC 277 +#define UBI32_CORE2_CLK_SRC 278 +#define UBI32_CORE1_CLK 279 +#define UBI32_CORE2_CLK 280 + +#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8960.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8960.h index 03bbf49..7d20eed 100644 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8960.h +++ b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8960.h @@ -51,7 +51,7 @@ #define QDSS_TSCTR_CLK 34 #define SFAB_ADM0_M0_A_CLK 35 #define SFAB_ADM0_M1_A_CLK 36 -#define SFAB_ADM0_M2_A_CLK 37 +#define SFAB_ADM0_M2_H_CLK 37 #define ADM0_CLK 38 #define ADM0_PBUS_CLK 39 #define MSS_XPU_CLK 40 @@ -99,7 +99,7 @@ #define CFPB2_H_CLK 82 #define SFAB_CFPB_M_H_CLK 83 #define CFPB_MASTER_H_CLK 84 -#define SFAB_CFPB_S_HCLK 85 +#define SFAB_CFPB_S_H_CLK 85 #define CFPB_SPLITTER_H_CLK 86 #define TSIF_H_CLK 87 #define TSIF_INACTIVITY_TIMERS_CLK 88 @@ -110,7 +110,6 @@ #define CE1_SLEEP_CLK 93 #define CE2_H_CLK 94 #define CE2_CORE_CLK 95 -#define CE2_SLEEP_CLK 96 #define SFPB_H_CLK_SRC 97 #define SFPB_H_CLK 98 #define SFAB_SFPB_M_H_CLK 99 @@ -252,7 +251,7 @@ #define MSS_S_H_CLK 235 #define MSS_CXO_SRC_CLK 236 #define SATA_H_CLK 237 -#define SATA_SRC_CLK 238 +#define SATA_CLK_SRC 238 #define SATA_RXOOB_CLK 239 #define SATA_PMALIVE_CLK 240 #define SATA_PHY_REF_CLK 241 @@ -309,5 +308,16 @@ #define PLL13 292 #define PLL14 293 #define PLL14_VOTE 294 +#define USB_HS3_H_CLK 295 +#define USB_HS3_XCVR_SRC 296 +#define USB_HS3_XCVR_CLK 297 +#define USB_HS4_H_CLK 298 +#define USB_HS4_XCVR_SRC 299 +#define USB_HS4_XCVR_CLK 300 +#define SATA_PHY_CFG_CLK 301 +#define SATA_A_CLK 302 +#define CE3_SRC 303 +#define CE3_CORE_CLK 304 +#define CE3_H_CLK 305 #endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8974.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8974.h index 223ca17..51e51c8 100644 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8974.h +++ b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8974.h @@ -316,5 +316,9 @@ #define GCC_CE2_CLK_SLEEP_ENA 299 #define GCC_CE2_AXI_CLK_SLEEP_ENA 300 #define GCC_CE2_AHB_CLK_SLEEP_ENA 301 +#define GPLL4 302 +#define GPLL4_VOTE 303 +#define GCC_SDCC1_CDCCAL_SLEEP_CLK 304 +#define GCC_SDCC1_CDCCAL_FF_CLK 305 #endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-apq8084.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-apq8084.h new file mode 100644 index 0000000..a929f86 --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-apq8084.h @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_APQ_MMCC_8084_H +#define _DT_BINDINGS_CLK_APQ_MMCC_8084_H + +#define MMSS_AHB_CLK_SRC 0 +#define MMSS_AXI_CLK_SRC 1 +#define MMPLL0 2 +#define MMPLL0_VOTE 3 +#define MMPLL1 4 +#define MMPLL1_VOTE 5 +#define MMPLL2 6 +#define MMPLL3 7 +#define MMPLL4 8 +#define CSI0_CLK_SRC 9 +#define CSI1_CLK_SRC 10 +#define CSI2_CLK_SRC 11 +#define CSI3_CLK_SRC 12 +#define VCODEC0_CLK_SRC 13 +#define VFE0_CLK_SRC 14 +#define VFE1_CLK_SRC 15 +#define MDP_CLK_SRC 16 +#define PCLK0_CLK_SRC 17 +#define PCLK1_CLK_SRC 18 +#define OCMEMNOC_CLK_SRC 19 +#define GFX3D_CLK_SRC 20 +#define JPEG0_CLK_SRC 21 +#define JPEG1_CLK_SRC 22 +#define JPEG2_CLK_SRC 23 +#define EDPPIXEL_CLK_SRC 24 +#define EXTPCLK_CLK_SRC 25 +#define VP_CLK_SRC 26 +#define CCI_CLK_SRC 27 +#define CAMSS_GP0_CLK_SRC 28 +#define CAMSS_GP1_CLK_SRC 29 +#define MCLK0_CLK_SRC 30 +#define MCLK1_CLK_SRC 31 +#define MCLK2_CLK_SRC 32 +#define MCLK3_CLK_SRC 33 +#define CSI0PHYTIMER_CLK_SRC 34 +#define CSI1PHYTIMER_CLK_SRC 35 +#define CSI2PHYTIMER_CLK_SRC 36 +#define CPP_CLK_SRC 37 +#define BYTE0_CLK_SRC 38 +#define BYTE1_CLK_SRC 39 +#define EDPAUX_CLK_SRC 40 +#define EDPLINK_CLK_SRC 41 +#define ESC0_CLK_SRC 42 +#define ESC1_CLK_SRC 43 +#define HDMI_CLK_SRC 44 +#define VSYNC_CLK_SRC 45 +#define RBCPR_CLK_SRC 46 +#define RBBMTIMER_CLK_SRC 47 +#define MAPLE_CLK_SRC 48 +#define VDP_CLK_SRC 49 +#define VPU_BUS_CLK_SRC 50 +#define MMSS_CXO_CLK 51 +#define MMSS_SLEEPCLK_CLK 52 +#define AVSYNC_AHB_CLK 53 +#define AVSYNC_EDPPIXEL_CLK 54 +#define AVSYNC_EXTPCLK_CLK 55 +#define AVSYNC_PCLK0_CLK 56 +#define AVSYNC_PCLK1_CLK 57 +#define AVSYNC_VP_CLK 58 +#define CAMSS_AHB_CLK 59 +#define CAMSS_CCI_CCI_AHB_CLK 60 +#define CAMSS_CCI_CCI_CLK 61 +#define CAMSS_CSI0_AHB_CLK 62 +#define CAMSS_CSI0_CLK 63 +#define CAMSS_CSI0PHY_CLK 64 +#define CAMSS_CSI0PIX_CLK 65 +#define CAMSS_CSI0RDI_CLK 66 +#define CAMSS_CSI1_AHB_CLK 67 +#define CAMSS_CSI1_CLK 68 +#define CAMSS_CSI1PHY_CLK 69 +#define CAMSS_CSI1PIX_CLK 70 +#define CAMSS_CSI1RDI_CLK 71 +#define CAMSS_CSI2_AHB_CLK 72 +#define CAMSS_CSI2_CLK 73 +#define CAMSS_CSI2PHY_CLK 74 +#define CAMSS_CSI2PIX_CLK 75 +#define CAMSS_CSI2RDI_CLK 76 +#define CAMSS_CSI3_AHB_CLK 77 +#define CAMSS_CSI3_CLK 78 +#define CAMSS_CSI3PHY_CLK 79 +#define CAMSS_CSI3PIX_CLK 80 +#define CAMSS_CSI3RDI_CLK 81 +#define CAMSS_CSI_VFE0_CLK 82 +#define CAMSS_CSI_VFE1_CLK 83 +#define CAMSS_GP0_CLK 84 +#define CAMSS_GP1_CLK 85 +#define CAMSS_ISPIF_AHB_CLK 86 +#define CAMSS_JPEG_JPEG0_CLK 87 +#define CAMSS_JPEG_JPEG1_CLK 88 +#define CAMSS_JPEG_JPEG2_CLK 89 +#define CAMSS_JPEG_JPEG_AHB_CLK 90 +#define CAMSS_JPEG_JPEG_AXI_CLK 91 +#define CAMSS_MCLK0_CLK 92 +#define CAMSS_MCLK1_CLK 93 +#define CAMSS_MCLK2_CLK 94 +#define CAMSS_MCLK3_CLK 95 +#define CAMSS_MICRO_AHB_CLK 96 +#define CAMSS_PHY0_CSI0PHYTIMER_CLK 97 +#define CAMSS_PHY1_CSI1PHYTIMER_CLK 98 +#define CAMSS_PHY2_CSI2PHYTIMER_CLK 99 +#define CAMSS_TOP_AHB_CLK 100 +#define CAMSS_VFE_CPP_AHB_CLK 101 +#define CAMSS_VFE_CPP_CLK 102 +#define CAMSS_VFE_VFE0_CLK 103 +#define CAMSS_VFE_VFE1_CLK 104 +#define CAMSS_VFE_VFE_AHB_CLK 105 +#define CAMSS_VFE_VFE_AXI_CLK 106 +#define MDSS_AHB_CLK 107 +#define MDSS_AXI_CLK 108 +#define MDSS_BYTE0_CLK 109 +#define MDSS_BYTE1_CLK 110 +#define MDSS_EDPAUX_CLK 111 +#define MDSS_EDPLINK_CLK 112 +#define MDSS_EDPPIXEL_CLK 113 +#define MDSS_ESC0_CLK 114 +#define MDSS_ESC1_CLK 115 +#define MDSS_EXTPCLK_CLK 116 +#define MDSS_HDMI_AHB_CLK 117 +#define MDSS_HDMI_CLK 118 +#define MDSS_MDP_CLK 119 +#define MDSS_MDP_LUT_CLK 120 +#define MDSS_PCLK0_CLK 121 +#define MDSS_PCLK1_CLK 122 +#define MDSS_VSYNC_CLK 123 +#define MMSS_RBCPR_AHB_CLK 124 +#define MMSS_RBCPR_CLK 125 +#define MMSS_SPDM_AHB_CLK 126 +#define MMSS_SPDM_AXI_CLK 127 +#define MMSS_SPDM_CSI0_CLK 128 +#define MMSS_SPDM_GFX3D_CLK 129 +#define MMSS_SPDM_JPEG0_CLK 130 +#define MMSS_SPDM_JPEG1_CLK 131 +#define MMSS_SPDM_JPEG2_CLK 132 +#define MMSS_SPDM_MDP_CLK 133 +#define MMSS_SPDM_PCLK0_CLK 134 +#define MMSS_SPDM_PCLK1_CLK 135 +#define MMSS_SPDM_VCODEC0_CLK 136 +#define MMSS_SPDM_VFE0_CLK 137 +#define MMSS_SPDM_VFE1_CLK 138 +#define MMSS_SPDM_RM_AXI_CLK 139 +#define MMSS_SPDM_RM_OCMEMNOC_CLK 140 +#define MMSS_MISC_AHB_CLK 141 +#define MMSS_MMSSNOC_AHB_CLK 142 +#define MMSS_MMSSNOC_BTO_AHB_CLK 143 +#define MMSS_MMSSNOC_AXI_CLK 144 +#define MMSS_S0_AXI_CLK 145 +#define OCMEMCX_AHB_CLK 146 +#define OCMEMCX_OCMEMNOC_CLK 147 +#define OXILI_OCMEMGX_CLK 148 +#define OXILI_GFX3D_CLK 149 +#define OXILI_RBBMTIMER_CLK 150 +#define OXILICX_AHB_CLK 151 +#define VENUS0_AHB_CLK 152 +#define VENUS0_AXI_CLK 153 +#define VENUS0_CORE0_VCODEC_CLK 154 +#define VENUS0_CORE1_VCODEC_CLK 155 +#define VENUS0_OCMEMNOC_CLK 156 +#define VENUS0_VCODEC0_CLK 157 +#define VPU_AHB_CLK 158 +#define VPU_AXI_CLK 159 +#define VPU_BUS_CLK 160 +#define VPU_CXO_CLK 161 +#define VPU_MAPLE_CLK 162 +#define VPU_SLEEP_CLK 163 +#define VPU_VDP_CLK 164 + +#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8960.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8960.h index 5868ef1..85041b2 100644 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8960.h +++ b/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8960.h @@ -133,5 +133,13 @@ #define CSIPHY0_TIMER_CLK 116 #define PLL1 117 #define PLL2 118 +#define RGB_TV_CLK 119 +#define NPL_TV_CLK 120 +#define VCAP_AHB_CLK 121 +#define VCAP_AXI_CLK 122 +#define VCAP_SRC 123 +#define VCAP_CLK 124 +#define VCAP_NPL_CLK 125 +#define PLL15 126 #endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/r7s72100-clock.h b/sys/gnu/dts/include/dt-bindings/clock/r7s72100-clock.h new file mode 100644 index 0000000..5128f4d --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/r7s72100-clock.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2014 Renesas Solutions Corp. + * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ + +#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__ +#define __DT_BINDINGS_CLOCK_R7S72100_H__ + +#define R7S72100_CLK_PLL 0 + +/* MSTP3 */ +#define R7S72100_CLK_MTU2 3 + +/* MSTP4 */ +#define R7S72100_CLK_SCIF0 7 +#define R7S72100_CLK_SCIF1 6 +#define R7S72100_CLK_SCIF2 5 +#define R7S72100_CLK_SCIF3 4 +#define R7S72100_CLK_SCIF4 3 +#define R7S72100_CLK_SCIF5 2 +#define R7S72100_CLK_SCIF6 1 +#define R7S72100_CLK_SCIF7 0 + +/* MSTP9 */ +#define R7S72100_CLK_I2C0 7 +#define R7S72100_CLK_I2C1 6 +#define R7S72100_CLK_I2C2 5 +#define R7S72100_CLK_I2C3 4 + +/* MSTP10 */ +#define R7S72100_CLK_SPI0 7 +#define R7S72100_CLK_SPI1 6 +#define R7S72100_CLK_SPI2 5 +#define R7S72100_CLK_SPI3 4 +#define R7S72100_CLK_SPI4 3 + +#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a7779-clock.h b/sys/gnu/dts/include/dt-bindings/clock/r8a7779-clock.h new file mode 100644 index 0000000..381a611 --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/r8a7779-clock.h @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2013 Horms Solutions Ltd. + * + * Contact: Simon Horman <horms@verge.net.au> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __DT_BINDINGS_CLOCK_R8A7779_H__ +#define __DT_BINDINGS_CLOCK_R8A7779_H__ + +/* CPG */ +#define R8A7779_CLK_PLLA 0 +#define R8A7779_CLK_Z 1 +#define R8A7779_CLK_ZS 2 +#define R8A7779_CLK_S 3 +#define R8A7779_CLK_S1 4 +#define R8A7779_CLK_P 5 +#define R8A7779_CLK_B 6 +#define R8A7779_CLK_OUT 7 + +/* MSTP 0 */ +#define R8A7779_CLK_HSPI 7 +#define R8A7779_CLK_TMU2 14 +#define R8A7779_CLK_TMU1 15 +#define R8A7779_CLK_TMU0 16 +#define R8A7779_CLK_HSCIF1 18 +#define R8A7779_CLK_HSCIF0 19 +#define R8A7779_CLK_SCIF5 21 +#define R8A7779_CLK_SCIF4 22 +#define R8A7779_CLK_SCIF3 23 +#define R8A7779_CLK_SCIF2 24 +#define R8A7779_CLK_SCIF1 25 +#define R8A7779_CLK_SCIF0 26 +#define R8A7779_CLK_I2C3 27 +#define R8A7779_CLK_I2C2 28 +#define R8A7779_CLK_I2C1 29 +#define R8A7779_CLK_I2C0 30 + +/* MSTP 1 */ +#define R8A7779_CLK_USB01 0 +#define R8A7779_CLK_USB2 1 +#define R8A7779_CLK_DU 3 +#define R8A7779_CLK_VIN2 8 +#define R8A7779_CLK_VIN1 9 +#define R8A7779_CLK_VIN0 10 +#define R8A7779_CLK_ETHER 14 +#define R8A7779_CLK_SATA 15 +#define R8A7779_CLK_PCIE 16 +#define R8A7779_CLK_VIN3 20 + +/* MSTP 3 */ +#define R8A7779_CLK_SDHI3 20 +#define R8A7779_CLK_SDHI2 21 +#define R8A7779_CLK_SDHI1 22 +#define R8A7779_CLK_SDHI0 23 +#define R8A7779_CLK_MMC1 30 +#define R8A7779_CLK_MMC0 31 + + +#endif /* __DT_BINDINGS_CLOCK_R8A7779_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a7790-clock.h b/sys/gnu/dts/include/dt-bindings/clock/r8a7790-clock.h index 859e9be..f929a79 100644 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a7790-clock.h +++ b/sys/gnu/dts/include/dt-bindings/clock/r8a7790-clock.h @@ -33,8 +33,8 @@ #define R8A7790_CLK_TMU0 25 #define R8A7790_CLK_VSP1_DU1 27 #define R8A7790_CLK_VSP1_DU0 28 -#define R8A7790_CLK_VSP1_RT 30 -#define R8A7790_CLK_VSP1_SY 31 +#define R8A7790_CLK_VSP1_R 30 +#define R8A7790_CLK_VSP1_S 31 /* MSTP2 */ #define R8A7790_CLK_SCIFA2 2 @@ -46,10 +46,11 @@ #define R8A7790_CLK_MSIOF1 8 #define R8A7790_CLK_MSIOF3 15 #define R8A7790_CLK_SCIFB2 16 -#define R8A7790_CLK_SYS_DMAC0 18 -#define R8A7790_CLK_SYS_DMAC1 19 +#define R8A7790_CLK_SYS_DMAC1 18 +#define R8A7790_CLK_SYS_DMAC0 19 /* MSTP3 */ +#define R8A7790_CLK_IIC2 0 #define R8A7790_CLK_TPU0 4 #define R8A7790_CLK_MMCIF1 5 #define R8A7790_CLK_SDHI3 11 @@ -57,6 +58,9 @@ #define R8A7790_CLK_SDHI1 13 #define R8A7790_CLK_SDHI0 14 #define R8A7790_CLK_MMCIF0 15 +#define R8A7790_CLK_IIC0 18 +#define R8A7790_CLK_PCIEC 19 +#define R8A7790_CLK_IIC1 23 #define R8A7790_CLK_SSUSB 28 #define R8A7790_CLK_CMT1 29 #define R8A7790_CLK_USBDMAC0 30 @@ -104,4 +108,30 @@ #define R8A7790_CLK_I2C1 30 #define R8A7790_CLK_I2C0 31 +/* MSTP10 */ +#define R8A7790_CLK_SSI_ALL 5 +#define R8A7790_CLK_SSI9 6 +#define R8A7790_CLK_SSI8 7 +#define R8A7790_CLK_SSI7 8 +#define R8A7790_CLK_SSI6 9 +#define R8A7790_CLK_SSI5 10 +#define R8A7790_CLK_SSI4 11 +#define R8A7790_CLK_SSI3 12 +#define R8A7790_CLK_SSI2 13 +#define R8A7790_CLK_SSI1 14 +#define R8A7790_CLK_SSI0 15 +#define R8A7790_CLK_SCU_ALL 17 +#define R8A7790_CLK_SCU_DVC1 18 +#define R8A7790_CLK_SCU_DVC0 19 +#define R8A7790_CLK_SCU_SRC9 22 +#define R8A7790_CLK_SCU_SRC8 23 +#define R8A7790_CLK_SCU_SRC7 24 +#define R8A7790_CLK_SCU_SRC6 25 +#define R8A7790_CLK_SCU_SRC5 26 +#define R8A7790_CLK_SCU_SRC4 27 +#define R8A7790_CLK_SCU_SRC3 28 +#define R8A7790_CLK_SCU_SRC2 29 +#define R8A7790_CLK_SCU_SRC1 30 +#define R8A7790_CLK_SCU_SRC0 31 + #endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a7791-clock.h b/sys/gnu/dts/include/dt-bindings/clock/r8a7791-clock.h index 30f82f2..f0d4d10 100644 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a7791-clock.h +++ b/sys/gnu/dts/include/dt-bindings/clock/r8a7791-clock.h @@ -32,7 +32,7 @@ #define R8A7791_CLK_TMU0 25 #define R8A7791_CLK_VSP1_DU1 27 #define R8A7791_CLK_VSP1_DU0 28 -#define R8A7791_CLK_VSP1_SY 31 +#define R8A7791_CLK_VSP1_S 31 /* MSTP2 */ #define R8A7791_CLK_SCIFA2 2 @@ -43,7 +43,8 @@ #define R8A7791_CLK_SCIFB1 7 #define R8A7791_CLK_MSIOF1 8 #define R8A7791_CLK_SCIFB2 16 -#define R8A7791_CLK_DMAC 18 +#define R8A7791_CLK_SYS_DMAC1 18 +#define R8A7791_CLK_SYS_DMAC0 19 /* MSTP3 */ #define R8A7791_CLK_TPU0 4 @@ -51,6 +52,9 @@ #define R8A7791_CLK_SDHI1 12 #define R8A7791_CLK_SDHI0 14 #define R8A7791_CLK_MMCIF0 15 +#define R8A7791_CLK_IIC0 18 +#define R8A7791_CLK_PCIEC 19 +#define R8A7791_CLK_IIC1 23 #define R8A7791_CLK_SSUSB 28 #define R8A7791_CLK_CMT1 29 #define R8A7791_CLK_USBDMAC0 30 @@ -61,6 +65,7 @@ #define R8A7791_CLK_PWM 23 /* MSTP7 */ +#define R8A7791_CLK_EHCI 3 #define R8A7791_CLK_HSUSB 4 #define R8A7791_CLK_HSCIF2 13 #define R8A7791_CLK_SCIF5 14 @@ -103,6 +108,32 @@ #define R8A7791_CLK_I2C1 30 #define R8A7791_CLK_I2C0 31 +/* MSTP10 */ +#define R8A7791_CLK_SSI_ALL 5 +#define R8A7791_CLK_SSI9 6 +#define R8A7791_CLK_SSI8 7 +#define R8A7791_CLK_SSI7 8 +#define R8A7791_CLK_SSI6 9 +#define R8A7791_CLK_SSI5 10 +#define R8A7791_CLK_SSI4 11 +#define R8A7791_CLK_SSI3 12 +#define R8A7791_CLK_SSI2 13 +#define R8A7791_CLK_SSI1 14 +#define R8A7791_CLK_SSI0 15 +#define R8A7791_CLK_SCU_ALL 17 +#define R8A7791_CLK_SCU_DVC1 18 +#define R8A7791_CLK_SCU_DVC0 19 +#define R8A7791_CLK_SCU_SRC9 22 +#define R8A7791_CLK_SCU_SRC8 23 +#define R8A7791_CLK_SCU_SRC7 24 +#define R8A7791_CLK_SCU_SRC6 25 +#define R8A7791_CLK_SCU_SRC5 26 +#define R8A7791_CLK_SCU_SRC4 27 +#define R8A7791_CLK_SCU_SRC3 28 +#define R8A7791_CLK_SCU_SRC2 29 +#define R8A7791_CLK_SCU_SRC1 30 +#define R8A7791_CLK_SCU_SRC0 31 + /* MSTP11 */ #define R8A7791_CLK_SCIFA3 6 #define R8A7791_CLK_SCIFA4 7 diff --git a/sys/gnu/dts/include/dt-bindings/clock/rk3066a-cru.h b/sys/gnu/dts/include/dt-bindings/clock/rk3066a-cru.h new file mode 100644 index 0000000..bc1ed1d --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/rk3066a-cru.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/clock/rk3188-cru-common.h> + +/* soft-reset indices */ +#define SRST_SRST1 0 +#define SRST_SRST2 1 + +#define SRST_L2MEM 18 +#define SRST_I2S0 23 +#define SRST_I2S1 24 +#define SRST_I2S2 25 +#define SRST_TIMER2 29 + +#define SRST_GPIO4 36 +#define SRST_GPIO6 38 + +#define SRST_TSADC 92 + +#define SRST_HDMI 96 +#define SRST_HDMI_APB 97 +#define SRST_CIF1 111 diff --git a/sys/gnu/dts/include/dt-bindings/clock/rk3188-cru-common.h b/sys/gnu/dts/include/dt-bindings/clock/rk3188-cru-common.h new file mode 100644 index 0000000..750ee60 --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/rk3188-cru-common.h @@ -0,0 +1,249 @@ +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* core clocks from */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define CORE_PERI 5 +#define CORE_L2C 6 + +/* sclk gates (special clocks) */ +#define SCLK_UART0 64 +#define SCLK_UART1 65 +#define SCLK_UART2 66 +#define SCLK_UART3 67 +#define SCLK_MAC 68 +#define SCLK_SPI0 69 +#define SCLK_SPI1 70 +#define SCLK_SARADC 71 +#define SCLK_SDMMC 72 +#define SCLK_SDIO 73 +#define SCLK_EMMC 74 +#define SCLK_I2S0 75 +#define SCLK_I2S1 76 +#define SCLK_I2S2 77 +#define SCLK_SPDIF 78 +#define SCLK_CIF0 79 +#define SCLK_CIF1 80 +#define SCLK_OTGPHY0 81 +#define SCLK_OTGPHY1 82 +#define SCLK_HSADC 83 +#define SCLK_TIMER0 84 +#define SCLK_TIMER1 85 +#define SCLK_TIMER2 86 +#define SCLK_TIMER3 87 +#define SCLK_TIMER4 88 +#define SCLK_TIMER5 89 +#define SCLK_TIMER6 90 +#define SCLK_JTAG 91 +#define SCLK_SMC 92 + +#define DCLK_LCDC0 190 +#define DCLK_LCDC1 191 + +/* aclk gates */ +#define ACLK_DMA1 192 +#define ACLK_DMA2 193 +#define ACLK_GPS 194 +#define ACLK_LCDC0 195 +#define ACLK_LCDC1 196 +#define ACLK_GPU 197 +#define ACLK_SMC 198 +#define ACLK_CIF 199 +#define ACLK_IPP 200 +#define ACLK_RGA 201 +#define ACLK_CIF0 202 + +/* pclk gates */ +#define PCLK_GRF 320 +#define PCLK_PMU 321 +#define PCLK_TIMER0 322 +#define PCLK_TIMER1 323 +#define PCLK_TIMER2 324 +#define PCLK_TIMER3 325 +#define PCLK_PWM01 326 +#define PCLK_PWM23 327 +#define PCLK_SPI0 328 +#define PCLK_SPI1 329 +#define PCLK_SARADC 330 +#define PCLK_WDT 331 +#define PCLK_UART0 332 +#define PCLK_UART1 333 +#define PCLK_UART2 334 +#define PCLK_UART3 335 +#define PCLK_I2C0 336 +#define PCLK_I2C1 337 +#define PCLK_I2C2 338 +#define PCLK_I2C3 339 +#define PCLK_I2C4 340 +#define PCLK_GPIO0 341 +#define PCLK_GPIO1 342 +#define PCLK_GPIO2 343 +#define PCLK_GPIO3 344 +#define PCLK_GPIO4 345 +#define PCLK_GPIO6 346 +#define PCLK_EFUSE 347 +#define PCLK_TZPC 348 +#define PCLK_TSADC 349 + +/* hclk gates */ +#define HCLK_SDMMC 448 +#define HCLK_SDIO 449 +#define HCLK_EMMC 450 +#define HCLK_OTG0 451 +#define HCLK_EMAC 452 +#define HCLK_SPDIF 453 +#define HCLK_I2S0 454 +#define HCLK_I2S1 455 +#define HCLK_I2S2 456 +#define HCLK_OTG1 457 +#define HCLK_HSIC 458 +#define HCLK_HSADC 459 +#define HCLK_PIDF 460 +#define HCLK_LCDC0 461 +#define HCLK_LCDC1 462 +#define HCLK_ROM 463 +#define HCLK_CIF0 464 +#define HCLK_IPP 465 +#define HCLK_RGA 466 +#define HCLK_NANDC0 467 + +#define CLK_NR_CLKS (HCLK_NANDC0 + 1) + +/* soft-reset indices */ +#define SRST_MCORE 2 +#define SRST_CORE0 3 +#define SRST_CORE1 4 +#define SRST_MCORE_DBG 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE0_WDT 12 +#define SRST_CORE1_WDT 13 +#define SRST_STRC_SYS 14 +#define SRST_L2C 15 + +#define SRST_CPU_AHB 17 +#define SRST_AHB2APB 19 +#define SRST_DMA1 20 +#define SRST_INTMEM 21 +#define SRST_ROM 22 +#define SRST_SPDIF 26 +#define SRST_TIMER0 27 +#define SRST_TIMER1 28 +#define SRST_EFUSE 30 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_GPIO3 35 + +#define SRST_UART0 39 +#define SRST_UART1 40 +#define SRST_UART2 41 +#define SRST_UART3 42 +#define SRST_I2C0 43 +#define SRST_I2C1 44 +#define SRST_I2C2 45 +#define SRST_I2C3 46 +#define SRST_I2C4 47 + +#define SRST_PWM0 48 +#define SRST_PWM1 49 +#define SRST_DAP_PO 50 +#define SRST_DAP 51 +#define SRST_DAP_SYS 52 +#define SRST_TPIU_ATB 53 +#define SRST_PMU_APB 54 +#define SRST_GRF 55 +#define SRST_PMU 56 +#define SRST_PERI_AXI 57 +#define SRST_PERI_AHB 58 +#define SRST_PERI_APB 59 +#define SRST_PERI_NIU 60 +#define SRST_CPU_PERI 61 +#define SRST_EMEM_PERI 62 +#define SRST_USB_PERI 63 + +#define SRST_DMA2 64 +#define SRST_SMC 65 +#define SRST_MAC 66 +#define SRST_NANC0 68 +#define SRST_USBOTG0 69 +#define SRST_USBPHY0 70 +#define SRST_OTGC0 71 +#define SRST_USBOTG1 72 +#define SRST_USBPHY1 73 +#define SRST_OTGC1 74 +#define SRST_HSADC 76 +#define SRST_PIDFILTER 77 +#define SRST_DDR_MSCH 79 + +#define SRST_TZPC 80 +#define SRST_SDMMC 81 +#define SRST_SDIO 82 +#define SRST_EMMC 83 +#define SRST_SPI0 84 +#define SRST_SPI1 85 +#define SRST_WDT 86 +#define SRST_SARADC 87 +#define SRST_DDRPHY 88 +#define SRST_DDRPHY_APB 89 +#define SRST_DDRCTL 90 +#define SRST_DDRCTL_APB 91 +#define SRST_DDRPUB 93 + +#define SRST_VIO0_AXI 98 +#define SRST_VIO0_AHB 99 +#define SRST_LCDC0_AXI 100 +#define SRST_LCDC0_AHB 101 +#define SRST_LCDC0_DCLK 102 +#define SRST_LCDC1_AXI 103 +#define SRST_LCDC1_AHB 104 +#define SRST_LCDC1_DCLK 105 +#define SRST_IPP_AXI 106 +#define SRST_IPP_AHB 107 +#define SRST_RGA_AXI 108 +#define SRST_RGA_AHB 109 +#define SRST_CIF0 110 + +#define SRST_VCODEC_AXI 112 +#define SRST_VCODEC_AHB 113 +#define SRST_VIO1_AXI 114 +#define SRST_VCODEC_CPU 115 +#define SRST_VCODEC_NIU 116 +#define SRST_GPU 120 +#define SRST_GPU_NIU 122 +#define SRST_TFUN_ATB 125 +#define SRST_TFUN_APB 126 +#define SRST_CTI4_APB 127 + +#define SRST_TPIU_APB 128 +#define SRST_TRACE 129 +#define SRST_CORE_DBG 130 +#define SRST_DBG_APB 131 +#define SRST_CTI0 132 +#define SRST_CTI0_APB 133 +#define SRST_CTI1 134 +#define SRST_CTI1_APB 135 +#define SRST_PTM_CORE0 136 +#define SRST_PTM_CORE1 137 +#define SRST_PTM0 138 +#define SRST_PTM0_ATB 139 +#define SRST_PTM1 140 +#define SRST_PTM1_ATB 141 +#define SRST_CTM 142 +#define SRST_TS 143 diff --git a/sys/gnu/dts/include/dt-bindings/clock/rk3188-cru.h b/sys/gnu/dts/include/dt-bindings/clock/rk3188-cru.h new file mode 100644 index 0000000..9fac8ed --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/rk3188-cru.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/clock/rk3188-cru-common.h> + +/* soft-reset indices */ +#define SRST_PTM_CORE2 0 +#define SRST_PTM_CORE3 1 +#define SRST_CORE2 5 +#define SRST_CORE3 6 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 + +#define SRST_TIMER2 16 +#define SRST_TIMER4 23 +#define SRST_I2S0 24 +#define SRST_TIMER5 25 +#define SRST_TIMER3 29 +#define SRST_TIMER6 31 + +#define SRST_PTM3 36 +#define SRST_PTM3_ATB 37 + +#define SRST_GPS 67 +#define SRST_HSICPHY 75 +#define SRST_TIMER 78 + +#define SRST_PTM2 92 +#define SRST_CORE2_WDT 94 +#define SRST_CORE3_WDT 95 + +#define SRST_PTM2_ATB 111 + +#define SRST_HSIC 117 +#define SRST_CTI2 118 +#define SRST_CTI2_APB 119 +#define SRST_GPU_BRIDGE 121 +#define SRST_CTI3 123 +#define SRST_CTI3_APB 124 diff --git a/sys/gnu/dts/include/dt-bindings/clock/rk3288-cru.h b/sys/gnu/dts/include/dt-bindings/clock/rk3288-cru.h new file mode 100644 index 0000000..ebcb460 --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/rk3288-cru.h @@ -0,0 +1,278 @@ +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define PLL_NPLL 5 + +/* sclk gates (special clocks) */ +#define SCLK_GPU 64 +#define SCLK_SPI0 65 +#define SCLK_SPI1 66 +#define SCLK_SPI2 67 +#define SCLK_SDMMC 68 +#define SCLK_SDIO0 69 +#define SCLK_SDIO1 70 +#define SCLK_EMMC 71 +#define SCLK_TSADC 72 +#define SCLK_SARADC 73 +#define SCLK_PS2C 74 +#define SCLK_NANDC0 75 +#define SCLK_NANDC1 76 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_UART3 80 +#define SCLK_UART4 81 +#define SCLK_I2S0 82 +#define SCLK_SPDIF 83 +#define SCLK_SPDIF8CH 84 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_TIMER4 89 +#define SCLK_TIMER5 90 +#define SCLK_TIMER6 91 +#define SCLK_HSADC 92 +#define SCLK_OTGPHY0 93 +#define SCLK_OTGPHY1 94 +#define SCLK_OTGPHY2 95 +#define SCLK_OTG_ADP 96 +#define SCLK_HSICPHY480M 97 +#define SCLK_HSICPHY12M 98 +#define SCLK_MACREF 99 +#define SCLK_LCDC_PWM0 100 +#define SCLK_LCDC_PWM1 101 +#define SCLK_MAC_RX 102 +#define SCLK_MAC_TX 103 + +#define DCLK_VOP0 190 +#define DCLK_VOP1 191 + +/* aclk gates */ +#define ACLK_GPU 192 +#define ACLK_DMAC1 193 +#define ACLK_DMAC2 194 +#define ACLK_MMU 195 +#define ACLK_GMAC 196 +#define ACLK_VOP0 197 +#define ACLK_VOP1 198 +#define ACLK_CRYPTO 199 +#define ACLK_RGA 200 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GPIO3 323 +#define PCLK_GPIO4 324 +#define PCLK_GPIO5 325 +#define PCLK_GPIO6 326 +#define PCLK_GPIO7 327 +#define PCLK_GPIO8 328 +#define PCLK_GRF 329 +#define PCLK_SGRF 330 +#define PCLK_PMU 331 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_I2C3 335 +#define PCLK_I2C4 336 +#define PCLK_I2C5 337 +#define PCLK_SPI0 338 +#define PCLK_SPI1 339 +#define PCLK_SPI2 340 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_UART3 344 +#define PCLK_UART4 345 +#define PCLK_TSADC 346 +#define PCLK_SARADC 347 +#define PCLK_SIM 348 +#define PCLK_GMAC 349 +#define PCLK_PWM 350 +#define PCLK_RKPWM 351 +#define PCLK_PS2C 352 +#define PCLK_TIMER 353 +#define PCLK_TZPC 354 + +/* hclk gates */ +#define HCLK_GPS 448 +#define HCLK_OTG0 449 +#define HCLK_USBHOST0 450 +#define HCLK_USBHOST1 451 +#define HCLK_HSIC 452 +#define HCLK_NANDC0 453 +#define HCLK_NANDC1 454 +#define HCLK_TSP 455 +#define HCLK_SDMMC 456 +#define HCLK_SDIO0 457 +#define HCLK_SDIO1 458 +#define HCLK_EMMC 459 +#define HCLK_HSADC 460 +#define HCLK_CRYPTO 461 +#define HCLK_I2S0 462 +#define HCLK_SPDIF 463 +#define HCLK_SPDIF8CH 464 +#define HCLK_VOP0 465 +#define HCLK_VOP1 466 +#define HCLK_ROM 467 +#define HCLK_IEP 468 +#define HCLK_ISP 469 +#define HCLK_RGA 470 + +#define CLK_NR_CLKS (HCLK_RGA + 1) + +/* soft-reset indices */ +#define SRST_CORE0 0 +#define SRST_CORE1 1 +#define SRST_CORE2 2 +#define SRST_CORE3 3 +#define SRST_CORE0_PO 4 +#define SRST_CORE1_PO 5 +#define SRST_CORE2_PO 6 +#define SRST_CORE3_PO 7 +#define SRST_PDCORE_STRSYS 8 +#define SRST_PDBUS_STRSYS 9 +#define SRST_L2C 10 +#define SRST_TOPDBG 11 +#define SRST_CORE0_DBG 12 +#define SRST_CORE1_DBG 13 +#define SRST_CORE2_DBG 14 +#define SRST_CORE3_DBG 15 + +#define SRST_PDBUG_AHB_ARBITOR 16 +#define SRST_EFUSE256 17 +#define SRST_DMAC1 18 +#define SRST_INTMEM 19 +#define SRST_ROM 20 +#define SRST_SPDIF8CH 21 +#define SRST_TIMER 22 +#define SRST_I2S0 23 +#define SRST_SPDIF 24 +#define SRST_TIMER0 25 +#define SRST_TIMER1 26 +#define SRST_TIMER2 27 +#define SRST_TIMER3 28 +#define SRST_TIMER4 29 +#define SRST_TIMER5 30 +#define SRST_EFUSE 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_GPIO3 35 +#define SRST_GPIO4 36 +#define SRST_GPIO5 37 +#define SRST_GPIO6 38 +#define SRST_GPIO7 39 +#define SRST_GPIO8 40 +#define SRST_I2C0 42 +#define SRST_I2C1 43 +#define SRST_I2C2 44 +#define SRST_I2C3 45 +#define SRST_I2C4 46 +#define SRST_I2C5 47 + +#define SRST_DWPWM 48 +#define SRST_MMC_PERI 49 +#define SRST_PERIPH_MMU 50 +#define SRST_DAP 51 +#define SRST_DAP_SYS 52 +#define SRST_TPIU 53 +#define SRST_PMU_APB 54 +#define SRST_GRF 55 +#define SRST_PMU 56 +#define SRST_PERIPH_AXI 57 +#define SRST_PERIPH_AHB 58 +#define SRST_PERIPH_APB 59 +#define SRST_PERIPH_NIU 60 +#define SRST_PDPERI_AHB_ARBI 61 +#define SRST_EMEM 62 +#define SRST_USB_PERI 63 + +#define SRST_DMAC2 64 +#define SRST_MAC 66 +#define SRST_GPS 67 +#define SRST_RKPWM 69 +#define SRST_CCP 71 +#define SRST_USBHOST0 72 +#define SRST_HSIC 73 +#define SRST_HSIC_AUX 74 +#define SRST_HSIC_PHY 75 +#define SRST_HSADC 76 +#define SRST_NANDC0 77 +#define SRST_NANDC1 78 + +#define SRST_TZPC 80 +#define SRST_SPI0 83 +#define SRST_SPI1 84 +#define SRST_SPI2 85 +#define SRST_SARADC 87 +#define SRST_PDALIVE_NIU 88 +#define SRST_PDPMU_INTMEM 89 +#define SRST_PDPMU_NIU 90 +#define SRST_SGRF 91 + +#define SRST_VIO_ARBI 96 +#define SRST_RGA_NIU 97 +#define SRST_VIO0_NIU_AXI 98 +#define SRST_VIO_NIU_AHB 99 +#define SRST_LCDC0_AXI 100 +#define SRST_LCDC0_AHB 101 +#define SRST_LCDC0_DCLK 102 +#define SRST_VIO1_NIU_AXI 103 +#define SRST_VIP 104 +#define SRST_RGA_CORE 105 +#define SRST_IEP_AXI 106 +#define SRST_IEP_AHB 107 +#define SRST_RGA_AXI 108 +#define SRST_RGA_AHB 109 +#define SRST_ISP 110 +#define SRST_EDP 111 + +#define SRST_VCODEC_AXI 112 +#define SRST_VCODEC_AHB 113 +#define SRST_VIO_H2P 114 +#define SRST_MIPIDSI0 115 +#define SRST_MIPIDSI1 116 +#define SRST_MIPICSI 117 +#define SRST_LVDS_PHY 118 +#define SRST_LVDS_CON 119 +#define SRST_GPU 120 +#define SRST_HDMI 121 +#define SRST_CORE_PVTM 124 +#define SRST_GPU_PVTM 125 + +#define SRST_MMC0 128 +#define SRST_SDIO0 129 +#define SRST_SDIO1 130 +#define SRST_EMMC 131 +#define SRST_USBOTG_AHB 132 +#define SRST_USBOTG_PHY 133 +#define SRST_USBOTG_CON 134 +#define SRST_USBHOST0_AHB 135 +#define SRST_USBHOST0_PHY 136 +#define SRST_USBHOST0_CON 137 +#define SRST_USBHOST1_AHB 138 +#define SRST_USBHOST1_PHY 139 +#define SRST_USBHOST1_CON 140 +#define SRST_USB_ADP 141 +#define SRST_ACC_EFUSE 142 diff --git a/sys/gnu/dts/include/dt-bindings/clock/s3c2410.h b/sys/gnu/dts/include/dt-bindings/clock/s3c2410.h new file mode 100644 index 0000000..352a767 --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/s3c2410.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Device Tree binding constants clock controllers of Samsung S3C2410 and later. + */ + +#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H +#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H + +/* + * Let each exported clock get a unique index, which is used on DT-enabled + * platforms to lookup the clock from a clock specifier. These indices are + * therefore considered an ABI and so must not be changed. This implies + * that new clocks should be added either in free spaces between clock groups + * or at the end. + */ + +/* Core clocks. */ + +/* id 1 is reserved */ +#define MPLL 2 +#define UPLL 3 +#define FCLK 4 +#define HCLK 5 +#define PCLK 6 +#define UCLK 7 +#define ARMCLK 8 + +/* pclk-gates */ +#define PCLK_UART0 16 +#define PCLK_UART1 17 +#define PCLK_UART2 18 +#define PCLK_I2C 19 +#define PCLK_SDI 20 +#define PCLK_SPI 21 +#define PCLK_ADC 22 +#define PCLK_AC97 23 +#define PCLK_I2S 24 +#define PCLK_PWM 25 +#define PCLK_RTC 26 +#define PCLK_GPIO 27 + + +/* hclk-gates */ +#define HCLK_LCD 32 +#define HCLK_USBH 33 +#define HCLK_USBD 34 +#define HCLK_NAND 35 +#define HCLK_CAM 36 + + +#define CAMIF 40 + + +/* Total number of clocks. */ +#define NR_CLKS (CAMIF + 1) + +#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/s3c2412.h b/sys/gnu/dts/include/dt-bindings/clock/s3c2412.h new file mode 100644 index 0000000..aac1dcf --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/s3c2412.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Device Tree binding constants clock controllers of Samsung S3C2412. + */ + +#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H +#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H + +/* + * Let each exported clock get a unique index, which is used on DT-enabled + * platforms to lookup the clock from a clock specifier. These indices are + * therefore considered an ABI and so must not be changed. This implies + * that new clocks should be added either in free spaces between clock groups + * or at the end. + */ + +/* Core clocks. */ + +/* id 1 is reserved */ +#define MPLL 2 +#define UPLL 3 +#define MDIVCLK 4 +#define MSYSCLK 5 +#define USYSCLK 6 +#define HCLK 7 +#define PCLK 8 +#define ARMDIV 9 +#define ARMCLK 10 + + +/* Special clocks */ +#define SCLK_CAM 16 +#define SCLK_UART 17 +#define SCLK_I2S 18 +#define SCLK_USBD 19 +#define SCLK_USBH 20 + +/* pclk-gates */ +#define PCLK_WDT 32 +#define PCLK_SPI 33 +#define PCLK_I2S 34 +#define PCLK_I2C 35 +#define PCLK_ADC 36 +#define PCLK_RTC 37 +#define PCLK_GPIO 38 +#define PCLK_UART2 39 +#define PCLK_UART1 40 +#define PCLK_UART0 41 +#define PCLK_SDI 42 +#define PCLK_PWM 43 +#define PCLK_USBD 44 + +/* hclk-gates */ +#define HCLK_HALF 48 +#define HCLK_X2 49 +#define HCLK_SDRAM 50 +#define HCLK_USBH 51 +#define HCLK_LCD 52 +#define HCLK_NAND 53 +#define HCLK_DMA3 54 +#define HCLK_DMA2 55 +#define HCLK_DMA1 56 +#define HCLK_DMA0 57 + +/* Total number of clocks. */ +#define NR_CLKS (HCLK_DMA0 + 1) + +#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/s3c2443.h b/sys/gnu/dts/include/dt-bindings/clock/s3c2443.h new file mode 100644 index 0000000..37e66b0 --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/s3c2443.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Device Tree binding constants clock controllers of Samsung S3C2443 and later. + */ + +#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H +#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H + +/* + * Let each exported clock get a unique index, which is used on DT-enabled + * platforms to lookup the clock from a clock specifier. These indices are + * therefore considered an ABI and so must not be changed. This implies + * that new clocks should be added either in free spaces between clock groups + * or at the end. + */ + +/* Core clocks. */ +#define MSYSCLK 1 +#define ESYSCLK 2 +#define ARMDIV 3 +#define ARMCLK 4 +#define HCLK 5 +#define PCLK 6 + +/* Special clocks */ +#define SCLK_HSSPI0 16 +#define SCLK_FIMD 17 +#define SCLK_I2S0 18 +#define SCLK_I2S1 19 +#define SCLK_HSMMC1 20 +#define SCLK_HSMMC_EXT 21 +#define SCLK_CAM 22 +#define SCLK_UART 23 +#define SCLK_USBH 24 + +/* Muxes */ +#define MUX_HSSPI0 32 +#define MUX_HSSPI1 33 +#define MUX_HSMMC0 34 +#define MUX_HSMMC1 35 + +/* hclk-gates */ +#define HCLK_DMA0 48 +#define HCLK_DMA1 49 +#define HCLK_DMA2 50 +#define HCLK_DMA3 51 +#define HCLK_DMA4 52 +#define HCLK_DMA5 53 +#define HCLK_DMA6 54 +#define HCLK_DMA7 55 +#define HCLK_CAM 56 +#define HCLK_LCD 57 +#define HCLK_USBH 58 +#define HCLK_USBD 59 +#define HCLK_IROM 60 +#define HCLK_HSMMC0 61 +#define HCLK_HSMMC1 62 +#define HCLK_CFC 63 +#define HCLK_SSMC 64 +#define HCLK_DRAM 65 +#define HCLK_2D 66 + +/* pclk-gates */ +#define PCLK_UART0 72 +#define PCLK_UART1 73 +#define PCLK_UART2 74 +#define PCLK_UART3 75 +#define PCLK_I2C0 76 +#define PCLK_SDI 77 +#define PCLK_SPI0 78 +#define PCLK_ADC 79 +#define PCLK_AC97 80 +#define PCLK_I2S0 81 +#define PCLK_PWM 82 +#define PCLK_WDT 83 +#define PCLK_RTC 84 +#define PCLK_GPIO 85 +#define PCLK_SPI1 86 +#define PCLK_CHIPID 87 +#define PCLK_I2C1 88 +#define PCLK_I2S1 89 +#define PCLK_PCM 90 + +/* Total number of clocks. */ +#define NR_CLKS (PCLK_PCM + 1) + +#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/s5pv210-audss.h b/sys/gnu/dts/include/dt-bindings/clock/s5pv210-audss.h new file mode 100644 index 0000000..fe57406 --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/s5pv210-audss.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2014 Tomasz Figa <tomasz.figa@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This header provides constants for Samsung audio subsystem + * clock controller. + * + * The constants defined in this header are being used in dts + * and s5pv210 audss driver. + */ + +#ifndef _DT_BINDINGS_CLOCK_S5PV210_AUDSS_H +#define _DT_BINDINGS_CLOCK_S5PV210_AUDSS_H + +#define CLK_MOUT_AUDSS 0 +#define CLK_MOUT_I2S_A 1 + +#define CLK_DOUT_AUD_BUS 2 +#define CLK_DOUT_I2S_A 3 + +#define CLK_I2S 4 +#define CLK_HCLK_I2S 5 +#define CLK_HCLK_UART 6 +#define CLK_HCLK_HWA 7 +#define CLK_HCLK_DMA 8 +#define CLK_HCLK_BUF 9 +#define CLK_HCLK_RP 10 + +#define AUDSS_MAX_CLKS 11 + +#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/s5pv210.h b/sys/gnu/dts/include/dt-bindings/clock/s5pv210.h new file mode 100644 index 0000000..e88986b --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/s5pv210.h @@ -0,0 +1,239 @@ +/* + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * Author: Mateusz Krawczuk <m.krawczuk@partner.samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Device Tree binding constants for Samsung S5PV210 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_S5PV210_H +#define _DT_BINDINGS_CLOCK_S5PV210_H + +/* Core clocks. */ +#define FIN_PLL 1 +#define FOUT_APLL 2 +#define FOUT_MPLL 3 +#define FOUT_EPLL 4 +#define FOUT_VPLL 5 + +/* Muxes. */ +#define MOUT_FLASH 6 +#define MOUT_PSYS 7 +#define MOUT_DSYS 8 +#define MOUT_MSYS 9 +#define MOUT_VPLL 10 +#define MOUT_EPLL 11 +#define MOUT_MPLL 12 +#define MOUT_APLL 13 +#define MOUT_VPLLSRC 14 +#define MOUT_CSIS 15 +#define MOUT_FIMD 16 +#define MOUT_CAM1 17 +#define MOUT_CAM0 18 +#define MOUT_DAC 19 +#define MOUT_MIXER 20 +#define MOUT_HDMI 21 +#define MOUT_G2D 22 +#define MOUT_MFC 23 +#define MOUT_G3D 24 +#define MOUT_FIMC2 25 +#define MOUT_FIMC1 26 +#define MOUT_FIMC0 27 +#define MOUT_UART3 28 +#define MOUT_UART2 29 +#define MOUT_UART1 30 +#define MOUT_UART0 31 +#define MOUT_MMC3 32 +#define MOUT_MMC2 33 +#define MOUT_MMC1 34 +#define MOUT_MMC0 35 +#define MOUT_PWM 36 +#define MOUT_SPI0 37 +#define MOUT_SPI1 38 +#define MOUT_DMC0 39 +#define MOUT_PWI 40 +#define MOUT_HPM 41 +#define MOUT_SPDIF 42 +#define MOUT_AUDIO2 43 +#define MOUT_AUDIO1 44 +#define MOUT_AUDIO0 45 + +/* Dividers. */ +#define DOUT_PCLKP 46 +#define DOUT_HCLKP 47 +#define DOUT_PCLKD 48 +#define DOUT_HCLKD 49 +#define DOUT_PCLKM 50 +#define DOUT_HCLKM 51 +#define DOUT_A2M 52 +#define DOUT_APLL 53 +#define DOUT_CSIS 54 +#define DOUT_FIMD 55 +#define DOUT_CAM1 56 +#define DOUT_CAM0 57 +#define DOUT_TBLK 58 +#define DOUT_G2D 59 +#define DOUT_MFC 60 +#define DOUT_G3D 61 +#define DOUT_FIMC2 62 +#define DOUT_FIMC1 63 +#define DOUT_FIMC0 64 +#define DOUT_UART3 65 +#define DOUT_UART2 66 +#define DOUT_UART1 67 +#define DOUT_UART0 68 +#define DOUT_MMC3 69 +#define DOUT_MMC2 70 +#define DOUT_MMC1 71 +#define DOUT_MMC0 72 +#define DOUT_PWM 73 +#define DOUT_SPI1 74 +#define DOUT_SPI0 75 +#define DOUT_DMC0 76 +#define DOUT_PWI 77 +#define DOUT_HPM 78 +#define DOUT_COPY 79 +#define DOUT_FLASH 80 +#define DOUT_AUDIO2 81 +#define DOUT_AUDIO1 82 +#define DOUT_AUDIO0 83 +#define DOUT_DPM 84 +#define DOUT_DVSEM 85 + +/* Gates */ +#define SCLK_FIMC 86 +#define CLK_CSIS 87 +#define CLK_ROTATOR 88 +#define CLK_FIMC2 89 +#define CLK_FIMC1 90 +#define CLK_FIMC0 91 +#define CLK_MFC 92 +#define CLK_G2D 93 +#define CLK_G3D 94 +#define CLK_IMEM 95 +#define CLK_PDMA1 96 +#define CLK_PDMA0 97 +#define CLK_MDMA 98 +#define CLK_DMC1 99 +#define CLK_DMC0 100 +#define CLK_NFCON 101 +#define CLK_SROMC 102 +#define CLK_CFCON 103 +#define CLK_NANDXL 104 +#define CLK_USB_HOST 105 +#define CLK_USB_OTG 106 +#define CLK_HDMI 107 +#define CLK_TVENC 108 +#define CLK_MIXER 109 +#define CLK_VP 110 +#define CLK_DSIM 111 +#define CLK_FIMD 112 +#define CLK_TZIC3 113 +#define CLK_TZIC2 114 +#define CLK_TZIC1 115 +#define CLK_TZIC0 116 +#define CLK_VIC3 117 +#define CLK_VIC2 118 +#define CLK_VIC1 119 +#define CLK_VIC0 120 +#define CLK_TSI 121 +#define CLK_HSMMC3 122 +#define CLK_HSMMC2 123 +#define CLK_HSMMC1 124 +#define CLK_HSMMC0 125 +#define CLK_JTAG 126 +#define CLK_MODEMIF 127 +#define CLK_CORESIGHT 128 +#define CLK_SDM 129 +#define CLK_SECSS 130 +#define CLK_PCM2 131 +#define CLK_PCM1 132 +#define CLK_PCM0 133 +#define CLK_SYSCON 134 +#define CLK_GPIO 135 +#define CLK_TSADC 136 +#define CLK_PWM 137 +#define CLK_WDT 138 +#define CLK_KEYIF 139 +#define CLK_UART3 140 +#define CLK_UART2 141 +#define CLK_UART1 142 +#define CLK_UART0 143 +#define CLK_SYSTIMER 144 +#define CLK_RTC 145 +#define CLK_SPI1 146 +#define CLK_SPI0 147 +#define CLK_I2C_HDMI_PHY 148 +#define CLK_I2C1 149 +#define CLK_I2C2 150 +#define CLK_I2C0 151 +#define CLK_I2S1 152 +#define CLK_I2S2 153 +#define CLK_I2S0 154 +#define CLK_AC97 155 +#define CLK_SPDIF 156 +#define CLK_TZPC3 157 +#define CLK_TZPC2 158 +#define CLK_TZPC1 159 +#define CLK_TZPC0 160 +#define CLK_SECKEY 161 +#define CLK_IEM_APC 162 +#define CLK_IEM_IEC 163 +#define CLK_CHIPID 164 +#define CLK_JPEG 163 + +/* Special clocks*/ +#define SCLK_PWI 164 +#define SCLK_SPDIF 165 +#define SCLK_AUDIO2 166 +#define SCLK_AUDIO1 167 +#define SCLK_AUDIO0 168 +#define SCLK_PWM 169 +#define SCLK_SPI1 170 +#define SCLK_SPI0 171 +#define SCLK_UART3 172 +#define SCLK_UART2 173 +#define SCLK_UART1 174 +#define SCLK_UART0 175 +#define SCLK_MMC3 176 +#define SCLK_MMC2 177 +#define SCLK_MMC1 178 +#define SCLK_MMC0 179 +#define SCLK_FINVPLL 180 +#define SCLK_CSIS 181 +#define SCLK_FIMD 182 +#define SCLK_CAM1 183 +#define SCLK_CAM0 184 +#define SCLK_DAC 185 +#define SCLK_MIXER 186 +#define SCLK_HDMI 187 +#define SCLK_FIMC2 188 +#define SCLK_FIMC1 189 +#define SCLK_FIMC0 190 +#define SCLK_HDMI27M 191 +#define SCLK_HDMIPHY 192 +#define SCLK_USBPHY0 193 +#define SCLK_USBPHY1 194 + +/* S5P6442-specific clocks */ +#define MOUT_D0SYNC 195 +#define MOUT_D1SYNC 196 +#define DOUT_MIXER 197 +#define CLK_ETB 198 +#define CLK_ETM 199 + +/* CLKOUT */ +#define FOUT_APLL_CLKOUT 200 +#define FOUT_MPLL_CLKOUT 201 +#define DOUT_APLL_CLKOUT 202 +#define MOUT_CLKSEL 203 +#define DOUT_CLKOUT 204 +#define MOUT_CLKOUT 205 + +/* Total number of clocks. */ +#define NR_CLKS 206 + +#endif /* _DT_BINDINGS_CLOCK_S5PV210_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/stih415-clks.h b/sys/gnu/dts/include/dt-bindings/clock/stih415-clks.h new file mode 100644 index 0000000..d80caa6 --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/stih415-clks.h @@ -0,0 +1,16 @@ +/* + * This header provides constants clk index STMicroelectronics + * STiH415 SoC. + */ +#ifndef _CLK_STIH415 +#define _CLK_STIH415 + +/* CLOCKGEN A0 */ +#define CLK_ICN_REG 0 +#define CLK_ETH1_PHY 4 + +/* CLOCKGEN A1 */ +#define CLK_ICN_IF_2 0 +#define CLK_GMAC0_PHY 3 + +#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/stih416-clks.h b/sys/gnu/dts/include/dt-bindings/clock/stih416-clks.h new file mode 100644 index 0000000..f9bdbd1 --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/clock/stih416-clks.h @@ -0,0 +1,16 @@ +/* + * This header provides constants clk index STMicroelectronics + * STiH416 SoC. + */ +#ifndef _CLK_STIH416 +#define _CLK_STIH416 + +/* CLOCKGEN A0 */ +#define CLK_ICN_REG 0 +#define CLK_ETH1_PHY 4 + +/* CLOCKGEN A1 */ +#define CLK_ICN_IF_2 0 +#define CLK_GMAC0_PHY 3 + +#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/tegra114-car.h b/sys/gnu/dts/include/dt-bindings/clock/tegra114-car.h index 6d0d8d8..fc12621 100644 --- a/sys/gnu/dts/include/dt-bindings/clock/tegra114-car.h +++ b/sys/gnu/dts/include/dt-bindings/clock/tegra114-car.h @@ -337,6 +337,7 @@ #define TEGRA114_CLK_CLK_OUT_3_MUX 308 #define TEGRA114_CLK_DSIA_MUX 309 #define TEGRA114_CLK_DSIB_MUX 310 -#define TEGRA114_CLK_CLK_MAX 311 +#define TEGRA114_CLK_XUSB_SS_DIV2 311 +#define TEGRA114_CLK_CLK_MAX 312 #endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/tegra124-car.h b/sys/gnu/dts/include/dt-bindings/clock/tegra124-car.h index a1116a3..8a4c589 100644 --- a/sys/gnu/dts/include/dt-bindings/clock/tegra124-car.h +++ b/sys/gnu/dts/include/dt-bindings/clock/tegra124-car.h @@ -29,17 +29,17 @@ /* 10 (register bit affects spdif_in and spdif_out) */ #define TEGRA124_CLK_I2S1 11 #define TEGRA124_CLK_I2C1 12 -#define TEGRA124_CLK_NDFLASH 13 +/* 13 */ #define TEGRA124_CLK_SDMMC1 14 #define TEGRA124_CLK_SDMMC4 15 /* 16 */ #define TEGRA124_CLK_PWM 17 #define TEGRA124_CLK_I2S2 18 /* 20 (register bit affects vi and vi_sensor) */ -#define TEGRA124_CLK_GR_2D 21 +/* 21 */ #define TEGRA124_CLK_USBD 22 #define TEGRA124_CLK_ISP 23 -#define TEGRA124_CLK_GR_3D 24 +/* 26 */ /* 25 */ #define TEGRA124_CLK_DISP2 26 #define TEGRA124_CLK_DISP1 27 @@ -83,7 +83,7 @@ /* 64 */ #define TEGRA124_CLK_UARTD 65 -#define TEGRA124_CLK_UARTE 66 +/* 66 */ #define TEGRA124_CLK_I2C3 67 #define TEGRA124_CLK_SBC4 68 #define TEGRA124_CLK_SDMMC3 69 @@ -97,7 +97,7 @@ #define TEGRA124_CLK_TRACE 77 #define TEGRA124_CLK_SOC_THERM 78 #define TEGRA124_CLK_DTV 79 -#define TEGRA124_CLK_NDSPEED 80 +/* 80 */ #define TEGRA124_CLK_I2CSLOW 81 #define TEGRA124_CLK_DSIB 82 #define TEGRA124_CLK_TSEC 83 @@ -336,6 +336,7 @@ #define TEGRA124_CLK_DSIA_MUX 309 #define TEGRA124_CLK_DSIB_MUX 310 #define TEGRA124_CLK_SOR0_LVDS 311 -#define TEGRA124_CLK_CLK_MAX 312 +#define TEGRA124_CLK_XUSB_SS_DIV2 312 +#define TEGRA124_CLK_CLK_MAX 313 #endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/vf610-clock.h b/sys/gnu/dts/include/dt-bindings/clock/vf610-clock.h index a916029..00953d9 100644 --- a/sys/gnu/dts/include/dt-bindings/clock/vf610-clock.h +++ b/sys/gnu/dts/include/dt-bindings/clock/vf610-clock.h @@ -164,6 +164,8 @@ #define VF610_CLK_DMAMUX1 151 #define VF610_CLK_DMAMUX2 152 #define VF610_CLK_DMAMUX3 153 -#define VF610_CLK_END 154 +#define VF610_CLK_FLEXCAN0_EN 154 +#define VF610_CLK_FLEXCAN1_EN 155 +#define VF610_CLK_END 156 #endif /* __DT_BINDINGS_CLOCK_VF610_H */ diff --git a/sys/gnu/dts/include/dt-bindings/dma/nbpfaxi.h b/sys/gnu/dts/include/dt-bindings/dma/nbpfaxi.h new file mode 100644 index 0000000..c1a5b9e --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/dma/nbpfaxi.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2013-2014 Renesas Electronics Europe Ltd. + * Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + */ + +#ifndef DT_BINDINGS_NBPFAXI_H +#define DT_BINDINGS_NBPFAXI_H + +/** + * Use "#dma-cells = <2>;" with the second integer defining slave DMA flags: + */ +#define NBPF_SLAVE_RQ_HIGH 1 +#define NBPF_SLAVE_RQ_LOW 2 +#define NBPF_SLAVE_RQ_LEVEL 4 + +#endif diff --git a/sys/gnu/dts/include/dt-bindings/mfd/as3722.h b/sys/gnu/dts/include/dt-bindings/mfd/as3722.h index 0e69256..e66c089 100644 --- a/sys/gnu/dts/include/dt-bindings/mfd/as3722.h +++ b/sys/gnu/dts/include/dt-bindings/mfd/as3722.h @@ -13,7 +13,7 @@ /* External control pins */ #define AS3722_EXT_CONTROL_PIN_ENABLE1 1 #define AS3722_EXT_CONTROL_PIN_ENABLE2 2 -#define AS3722_EXT_CONTROL_PIN_ENABLE2 3 +#define AS3722_EXT_CONTROL_PIN_ENABLE3 3 /* Interrupt numbers for AS3722 */ #define AS3722_IRQ_LID 0 diff --git a/sys/gnu/dts/include/dt-bindings/mfd/palmas.h b/sys/gnu/dts/include/dt-bindings/mfd/palmas.h new file mode 100644 index 0000000..2c8ac48 --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/mfd/palmas.h @@ -0,0 +1,18 @@ +/* + * This header provides macros for Palmas device bindings. + * + * Copyright (c) 2013, NVIDIA Corporation. + * + * Author: Laxman Dewangan <ldewangan@nvidia.com> + * + */ + +#ifndef __DT_BINDINGS_PALMAS_H__ +#define __DT_BINDINGS_PALMAS_H + +/* External control pins */ +#define PALMAS_EXT_CONTROL_PIN_ENABLE1 1 +#define PALMAS_EXT_CONTROL_PIN_ENABLE2 2 +#define PALMAS_EXT_CONTROL_PIN_NSLEEP 3 + +#endif /* __DT_BINDINGS_PALMAS_H */ diff --git a/sys/gnu/dts/include/dt-bindings/phy/phy-miphy365x.h b/sys/gnu/dts/include/dt-bindings/phy/phy-miphy365x.h new file mode 100644 index 0000000..8ef8aba --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/phy/phy-miphy365x.h @@ -0,0 +1,14 @@ +/* + * This header provides constants for the phy framework + * based on the STMicroelectronics MiPHY365x. + * + * Author: Lee Jones <lee.jones@linaro.org> + */ +#ifndef _DT_BINDINGS_PHY_MIPHY +#define _DT_BINDINGS_PHY_MIPHY + +#define MIPHY_TYPE_SATA 1 +#define MIPHY_TYPE_PCIE 2 +#define MIPHY_TYPE_USB 3 + +#endif /* _DT_BINDINGS_PHY_MIPHY */ diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/am43xx.h b/sys/gnu/dts/include/dt-bindings/pinctrl/am43xx.h index eb6c366..9c2e4f8 100644 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/am43xx.h +++ b/sys/gnu/dts/include/dt-bindings/pinctrl/am43xx.h @@ -13,6 +13,7 @@ #define MUX_MODE5 5 #define MUX_MODE6 6 #define MUX_MODE7 7 +#define MUX_MODE8 8 #define PULL_DISABLE (1 << 16) #define PULL_UP (1 << 17) diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/dra.h b/sys/gnu/dts/include/dt-bindings/pinctrl/dra.h index 002a285..3d33794 100644 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/dra.h +++ b/sys/gnu/dts/include/dt-bindings/pinctrl/dra.h @@ -30,7 +30,8 @@ #define MUX_MODE14 0xe #define MUX_MODE15 0xf -#define PULL_ENA (1 << 16) +#define PULL_ENA (0 << 16) +#define PULL_DIS (1 << 16) #define PULL_UP (1 << 17) #define INPUT_EN (1 << 18) #define SLEWCONTROL (1 << 19) @@ -38,10 +39,10 @@ #define WAKEUP_EVENT (1 << 25) /* Active pin states */ -#define PIN_OUTPUT 0 +#define PIN_OUTPUT (0 | PULL_DIS) #define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP) #define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA) -#define PIN_INPUT INPUT_EN +#define PIN_INPUT (INPUT_EN | PULL_DIS) #define PIN_INPUT_SLEW (INPUT_EN | SLEWCONTROL) #define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) #define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/omap.h b/sys/gnu/dts/include/dt-bindings/pinctrl/omap.h index b04528c..1c75b8c 100644 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/omap.h +++ b/sys/gnu/dts/include/dt-bindings/pinctrl/omap.h @@ -62,12 +62,29 @@ #define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val) #define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val) #define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) -#define OMAP4_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0040) (val) -#define OMAP4_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0xe040) (val) #define AM4372_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) -#define OMAP5_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2840) (val) -#define OMAP5_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0xc840) (val) #define DRA7XX_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x3400) (val) +/* + * Macros to allow using the offset from the padconf physical address + * instead of the offset from padconf base. + */ +#define OMAP_PADCONF_OFFSET(offset, base_offset) ((offset) - (base_offset)) + +#define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val) +#define OMAP5_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val) + +/* + * Define some commonly used pins configured by the boards. + * Note that some boards use alternative pins, so check + * the schematics before using these. + */ +#define OMAP3_UART1_RX 0x152 +#define OMAP3_UART2_RX 0x14a +#define OMAP3_UART3_RX 0x16e +#define OMAP4_UART2_RX 0xdc +#define OMAP4_UART3_RX 0x104 +#define OMAP4_UART4_RX 0x11c + #endif diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h b/sys/gnu/dts/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h new file mode 100644 index 0000000..914d56d --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h @@ -0,0 +1,7 @@ +#ifndef _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H +#define _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H 1 + +#define TEGRA_XUSB_PADCTL_PCIE 0 +#define TEGRA_XUSB_PADCTL_SATA 1 + +#endif /* _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H */ diff --git a/sys/gnu/dts/include/dt-bindings/reset-controller/stih415-resets.h b/sys/gnu/dts/include/dt-bindings/reset-controller/stih415-resets.h new file mode 100644 index 0000000..c2329fe --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/reset-controller/stih415-resets.h @@ -0,0 +1,27 @@ +/* + * This header provides constants for the reset controller + * based peripheral powerdown requests on the STMicroelectronics + * STiH415 SoC. + */ +#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH415 +#define _DT_BINDINGS_RESET_CONTROLLER_STIH415 + +#define STIH415_EMISS_POWERDOWN 0 +#define STIH415_NAND_POWERDOWN 1 +#define STIH415_KEYSCAN_POWERDOWN 2 +#define STIH415_USB0_POWERDOWN 3 +#define STIH415_USB1_POWERDOWN 4 +#define STIH415_USB2_POWERDOWN 5 +#define STIH415_SATA0_POWERDOWN 6 +#define STIH415_SATA1_POWERDOWN 7 +#define STIH415_PCIE_POWERDOWN 8 + +#define STIH415_ETH0_SOFTRESET 0 +#define STIH415_ETH1_SOFTRESET 1 +#define STIH415_IRB_SOFTRESET 2 +#define STIH415_USB0_SOFTRESET 3 +#define STIH415_USB1_SOFTRESET 4 +#define STIH415_USB2_SOFTRESET 5 +#define STIH415_KEYSCAN_SOFTRESET 6 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH415 */ diff --git a/sys/gnu/dts/include/dt-bindings/reset-controller/stih416-resets.h b/sys/gnu/dts/include/dt-bindings/reset-controller/stih416-resets.h new file mode 100644 index 0000000..fcf9af1 --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/reset-controller/stih416-resets.h @@ -0,0 +1,51 @@ +/* + * This header provides constants for the reset controller + * based peripheral powerdown requests on the STMicroelectronics + * STiH416 SoC. + */ +#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH416 +#define _DT_BINDINGS_RESET_CONTROLLER_STIH416 + +#define STIH416_EMISS_POWERDOWN 0 +#define STIH416_NAND_POWERDOWN 1 +#define STIH416_KEYSCAN_POWERDOWN 2 +#define STIH416_USB0_POWERDOWN 3 +#define STIH416_USB1_POWERDOWN 4 +#define STIH416_USB2_POWERDOWN 5 +#define STIH416_USB3_POWERDOWN 6 +#define STIH416_SATA0_POWERDOWN 7 +#define STIH416_SATA1_POWERDOWN 8 +#define STIH416_PCIE0_POWERDOWN 9 +#define STIH416_PCIE1_POWERDOWN 10 + +#define STIH416_ETH0_SOFTRESET 0 +#define STIH416_ETH1_SOFTRESET 1 +#define STIH416_IRB_SOFTRESET 2 +#define STIH416_USB0_SOFTRESET 3 +#define STIH416_USB1_SOFTRESET 4 +#define STIH416_USB2_SOFTRESET 5 +#define STIH416_USB3_SOFTRESET 6 +#define STIH416_SATA0_SOFTRESET 7 +#define STIH416_SATA1_SOFTRESET 8 +#define STIH416_PCIE0_SOFTRESET 9 +#define STIH416_PCIE1_SOFTRESET 10 +#define STIH416_AUD_DAC_SOFTRESET 11 +#define STIH416_HDTVOUT_SOFTRESET 12 +#define STIH416_VTAC_M_RX_SOFTRESET 13 +#define STIH416_VTAC_A_RX_SOFTRESET 14 +#define STIH416_SYNC_HD_SOFTRESET 15 +#define STIH416_SYNC_SD_SOFTRESET 16 +#define STIH416_BLITTER_SOFTRESET 17 +#define STIH416_GPU_SOFTRESET 18 +#define STIH416_VTAC_M_TX_SOFTRESET 19 +#define STIH416_VTAC_A_TX_SOFTRESET 20 +#define STIH416_VTG_AUX_SOFTRESET 21 +#define STIH416_JPEG_DEC_SOFTRESET 22 +#define STIH416_HVA_SOFTRESET 23 +#define STIH416_COMPO_M_SOFTRESET 24 +#define STIH416_COMPO_A_SOFTRESET 25 +#define STIH416_VP8_DEC_SOFTRESET 26 +#define STIH416_VTG_MAIN_SOFTRESET 27 +#define STIH416_KEYSCAN_SOFTRESET 28 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH416 */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/altr,rst-mgr.h b/sys/gnu/dts/include/dt-bindings/reset/altr,rst-mgr.h new file mode 100644 index 0000000..3f04908 --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/reset/altr,rst-mgr.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H + +/* MPUMODRST */ +#define CPU0_RESET 0 +#define CPU1_RESET 1 +#define WDS_RESET 2 +#define SCUPER_RESET 3 +#define L2_RESET 4 + +/* PERMODRST */ +#define EMAC0_RESET 32 +#define EMAC1_RESET 33 +#define USB0_RESET 34 +#define USB1_RESET 35 +#define NAND_RESET 36 +#define QSPI_RESET 37 +#define L4WD0_RESET 38 +#define L4WD1_RESET 39 +#define OSC1TIMER0_RESET 40 +#define OSC1TIMER1_RESET 41 +#define SPTIMER0_RESET 42 +#define SPTIMER1_RESET 43 +#define I2C0_RESET 44 +#define I2C1_RESET 45 +#define I2C2_RESET 46 +#define I2C3_RESET 47 +#define UART0_RESET 48 +#define UART1_RESET 49 +#define SPIM0_RESET 50 +#define SPIM1_RESET 51 +#define SPIS0_RESET 52 +#define SPIS1_RESET 53 +#define SDMMC_RESET 54 +#define CAN0_RESET 55 +#define CAN1_RESET 56 +#define GPIO0_RESET 57 +#define GPIO1_RESET 58 +#define GPIO2_RESET 59 +#define DMA_RESET 60 +#define SDR_RESET 61 + +/* PER2MODRST */ +#define DMAIF0_RESET 64 +#define DMAIF1_RESET 65 +#define DMAIF2_RESET 66 +#define DMAIF3_RESET 67 +#define DMAIF4_RESET 68 +#define DMAIF5_RESET 69 +#define DMAIF6_RESET 70 +#define DMAIF7_RESET 71 + +/* BRGMODRST */ +#define HPS2FPGA_RESET 96 +#define LWHPS2FPGA_RESET 97 +#define FPGA2HPS_RESET 98 + +/* MISCMODRST*/ +#define ROM_RESET 128 +#define OCRAM_RESET 129 +#define SYSMGR_RESET 130 +#define SYSMGRCOLD_RESET 131 +#define FPGAMGR_RESET 132 +#define ACPIDMAP_RESET 133 +#define S2F_RESET 134 +#define S2FCOLD_RESET 135 +#define NRSTPIN_RESET 136 +#define TIMESTAMPCOLD_RESET 137 +#define CLKMGRCOLD_RESET 138 +#define SCANMGR_RESET 139 +#define FRZCTRLCOLD_RESET 140 +#define SYSDBG_RESET 141 +#define DBG_RESET 142 +#define TAPCOLD_RESET 143 +#define SDRCOLD_RESET 144 + +#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-apq8084.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-apq8084.h new file mode 100644 index 0000000..527caaf --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-apq8084.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_RESET_APQ_GCC_8084_H +#define _DT_BINDINGS_RESET_APQ_GCC_8084_H + +#define GCC_SYSTEM_NOC_BCR 0 +#define GCC_CONFIG_NOC_BCR 1 +#define GCC_PERIPH_NOC_BCR 2 +#define GCC_IMEM_BCR 3 +#define GCC_MMSS_BCR 4 +#define GCC_QDSS_BCR 5 +#define GCC_USB_30_BCR 6 +#define GCC_USB3_PHY_BCR 7 +#define GCC_USB_HS_HSIC_BCR 8 +#define GCC_USB_HS_BCR 9 +#define GCC_USB2A_PHY_BCR 10 +#define GCC_USB2B_PHY_BCR 11 +#define GCC_SDCC1_BCR 12 +#define GCC_SDCC2_BCR 13 +#define GCC_SDCC3_BCR 14 +#define GCC_SDCC4_BCR 15 +#define GCC_BLSP1_BCR 16 +#define GCC_BLSP1_QUP1_BCR 17 +#define GCC_BLSP1_UART1_BCR 18 +#define GCC_BLSP1_QUP2_BCR 19 +#define GCC_BLSP1_UART2_BCR 20 +#define GCC_BLSP1_QUP3_BCR 21 +#define GCC_BLSP1_UART3_BCR 22 +#define GCC_BLSP1_QUP4_BCR 23 +#define GCC_BLSP1_UART4_BCR 24 +#define GCC_BLSP1_QUP5_BCR 25 +#define GCC_BLSP1_UART5_BCR 26 +#define GCC_BLSP1_QUP6_BCR 27 +#define GCC_BLSP1_UART6_BCR 28 +#define GCC_BLSP2_BCR 29 +#define GCC_BLSP2_QUP1_BCR 30 +#define GCC_BLSP2_UART1_BCR 31 +#define GCC_BLSP2_QUP2_BCR 32 +#define GCC_BLSP2_UART2_BCR 33 +#define GCC_BLSP2_QUP3_BCR 34 +#define GCC_BLSP2_UART3_BCR 35 +#define GCC_BLSP2_QUP4_BCR 36 +#define GCC_BLSP2_UART4_BCR 37 +#define GCC_BLSP2_QUP5_BCR 38 +#define GCC_BLSP2_UART5_BCR 39 +#define GCC_BLSP2_QUP6_BCR 40 +#define GCC_BLSP2_UART6_BCR 41 +#define GCC_PDM_BCR 42 +#define GCC_PRNG_BCR 43 +#define GCC_BAM_DMA_BCR 44 +#define GCC_TSIF_BCR 45 +#define GCC_TCSR_BCR 46 +#define GCC_BOOT_ROM_BCR 47 +#define GCC_MSG_RAM_BCR 48 +#define GCC_TLMM_BCR 49 +#define GCC_MPM_BCR 50 +#define GCC_MPM_AHB_RESET 51 +#define GCC_MPM_NON_AHB_RESET 52 +#define GCC_SEC_CTRL_BCR 53 +#define GCC_SPMI_BCR 54 +#define GCC_SPDM_BCR 55 +#define GCC_CE1_BCR 56 +#define GCC_CE2_BCR 57 +#define GCC_BIMC_BCR 58 +#define GCC_SNOC_BUS_TIMEOUT0_BCR 59 +#define GCC_SNOC_BUS_TIMEOUT2_BCR 60 +#define GCC_PNOC_BUS_TIMEOUT0_BCR 61 +#define GCC_PNOC_BUS_TIMEOUT1_BCR 62 +#define GCC_PNOC_BUS_TIMEOUT2_BCR 63 +#define GCC_PNOC_BUS_TIMEOUT3_BCR 64 +#define GCC_PNOC_BUS_TIMEOUT4_BCR 65 +#define GCC_CNOC_BUS_TIMEOUT0_BCR 66 +#define GCC_CNOC_BUS_TIMEOUT1_BCR 67 +#define GCC_CNOC_BUS_TIMEOUT2_BCR 68 +#define GCC_CNOC_BUS_TIMEOUT3_BCR 69 +#define GCC_CNOC_BUS_TIMEOUT4_BCR 70 +#define GCC_CNOC_BUS_TIMEOUT5_BCR 71 +#define GCC_CNOC_BUS_TIMEOUT6_BCR 72 +#define GCC_DEHR_BCR 73 +#define GCC_RBCPR_BCR 74 +#define GCC_MSS_RESTART 75 +#define GCC_LPASS_RESTART 76 +#define GCC_WCSS_RESTART 77 +#define GCC_VENUS_RESTART 78 +#define GCC_COPSS_SMMU_BCR 79 +#define GCC_SPSS_BCR 80 +#define GCC_PCIE_0_BCR 81 +#define GCC_PCIE_0_PHY_BCR 82 +#define GCC_PCIE_1_BCR 83 +#define GCC_PCIE_1_PHY_BCR 84 +#define GCC_USB_30_SEC_BCR 85 +#define GCC_USB3_SEC_PHY_BCR 86 +#define GCC_SATA_BCR 87 +#define GCC_CE3_BCR 88 +#define GCC_UFS_BCR 89 +#define GCC_USB30_PHY_COM_BCR 90 + +#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-ipq806x.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-ipq806x.h new file mode 100644 index 0000000..0ad5ef9 --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-ipq806x.h @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_RESET_IPQ_806X_H +#define _DT_BINDINGS_RESET_IPQ_806X_H + +#define QDSS_STM_RESET 0 +#define AFAB_SMPSS_S_RESET 1 +#define AFAB_SMPSS_M1_RESET 2 +#define AFAB_SMPSS_M0_RESET 3 +#define AFAB_EBI1_CH0_RESET 4 +#define AFAB_EBI1_CH1_RESET 5 +#define SFAB_ADM0_M0_RESET 6 +#define SFAB_ADM0_M1_RESET 7 +#define SFAB_ADM0_M2_RESET 8 +#define ADM0_C2_RESET 9 +#define ADM0_C1_RESET 10 +#define ADM0_C0_RESET 11 +#define ADM0_PBUS_RESET 12 +#define ADM0_RESET 13 +#define QDSS_CLKS_SW_RESET 14 +#define QDSS_POR_RESET 15 +#define QDSS_TSCTR_RESET 16 +#define QDSS_HRESET_RESET 17 +#define QDSS_AXI_RESET 18 +#define QDSS_DBG_RESET 19 +#define SFAB_PCIE_M_RESET 20 +#define SFAB_PCIE_S_RESET 21 +#define PCIE_EXT_RESET 22 +#define PCIE_PHY_RESET 23 +#define PCIE_PCI_RESET 24 +#define PCIE_POR_RESET 25 +#define PCIE_HCLK_RESET 26 +#define PCIE_ACLK_RESET 27 +#define SFAB_LPASS_RESET 28 +#define SFAB_AFAB_M_RESET 29 +#define AFAB_SFAB_M0_RESET 30 +#define AFAB_SFAB_M1_RESET 31 +#define SFAB_SATA_S_RESET 32 +#define SFAB_DFAB_M_RESET 33 +#define DFAB_SFAB_M_RESET 34 +#define DFAB_SWAY0_RESET 35 +#define DFAB_SWAY1_RESET 36 +#define DFAB_ARB0_RESET 37 +#define DFAB_ARB1_RESET 38 +#define PPSS_PROC_RESET 39 +#define PPSS_RESET 40 +#define DMA_BAM_RESET 41 +#define SPS_TIC_H_RESET 42 +#define SFAB_CFPB_M_RESET 43 +#define SFAB_CFPB_S_RESET 44 +#define TSIF_H_RESET 45 +#define CE1_H_RESET 46 +#define CE1_CORE_RESET 47 +#define CE1_SLEEP_RESET 48 +#define CE2_H_RESET 49 +#define CE2_CORE_RESET 50 +#define SFAB_SFPB_M_RESET 51 +#define SFAB_SFPB_S_RESET 52 +#define RPM_PROC_RESET 53 +#define PMIC_SSBI2_RESET 54 +#define SDC1_RESET 55 +#define SDC2_RESET 56 +#define SDC3_RESET 57 +#define SDC4_RESET 58 +#define USB_HS1_RESET 59 +#define USB_HSIC_RESET 60 +#define USB_FS1_XCVR_RESET 61 +#define USB_FS1_RESET 62 +#define GSBI1_RESET 63 +#define GSBI2_RESET 64 +#define GSBI3_RESET 65 +#define GSBI4_RESET 66 +#define GSBI5_RESET 67 +#define GSBI6_RESET 68 +#define GSBI7_RESET 69 +#define SPDM_RESET 70 +#define SEC_CTRL_RESET 71 +#define TLMM_H_RESET 72 +#define SFAB_SATA_M_RESET 73 +#define SATA_RESET 74 +#define TSSC_RESET 75 +#define PDM_RESET 76 +#define MPM_H_RESET 77 +#define MPM_RESET 78 +#define SFAB_SMPSS_S_RESET 79 +#define PRNG_RESET 80 +#define SFAB_CE3_M_RESET 81 +#define SFAB_CE3_S_RESET 82 +#define CE3_SLEEP_RESET 83 +#define PCIE_1_M_RESET 84 +#define PCIE_1_S_RESET 85 +#define PCIE_1_EXT_RESET 86 +#define PCIE_1_PHY_RESET 87 +#define PCIE_1_PCI_RESET 88 +#define PCIE_1_POR_RESET 89 +#define PCIE_1_HCLK_RESET 90 +#define PCIE_1_ACLK_RESET 91 +#define PCIE_2_M_RESET 92 +#define PCIE_2_S_RESET 93 +#define PCIE_2_EXT_RESET 94 +#define PCIE_2_PHY_RESET 95 +#define PCIE_2_PCI_RESET 96 +#define PCIE_2_POR_RESET 97 +#define PCIE_2_HCLK_RESET 98 +#define PCIE_2_ACLK_RESET 99 +#define SFAB_USB30_S_RESET 100 +#define SFAB_USB30_M_RESET 101 +#define USB30_0_PORT2_HS_PHY_RESET 102 +#define USB30_0_MASTER_RESET 103 +#define USB30_0_SLEEP_RESET 104 +#define USB30_0_UTMI_PHY_RESET 105 +#define USB30_0_POWERON_RESET 106 +#define USB30_0_PHY_RESET 107 +#define USB30_1_MASTER_RESET 108 +#define USB30_1_SLEEP_RESET 109 +#define USB30_1_UTMI_PHY_RESET 110 +#define USB30_1_POWERON_RESET 111 +#define USB30_1_PHY_RESET 112 +#define NSSFB0_RESET 113 +#define NSSFB1_RESET 114 +#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8960.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8960.h index a840e68..47c8686 100644 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8960.h +++ b/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8960.h @@ -58,7 +58,7 @@ #define PPSS_PROC_RESET 41 #define PPSS_RESET 42 #define DMA_BAM_RESET 43 -#define SIC_TIC_RESET 44 +#define SPS_TIC_H_RESET 44 #define SLIMBUS_H_RESET 45 #define SFAB_CFPB_M_RESET 46 #define SFAB_CFPB_S_RESET 47 @@ -114,5 +114,21 @@ #define SFAB_SMPSS_S_RESET 97 #define PRNG_RESET 98 #define RIVA_RESET 99 +#define USB_HS3_RESET 100 +#define USB_HS4_RESET 101 +#define CE3_RESET 102 +#define PCIE_EXT_PCI_RESET 103 +#define PCIE_PHY_RESET 104 +#define PCIE_PCI_RESET 105 +#define PCIE_POR_RESET 106 +#define PCIE_HCLK_RESET 107 +#define PCIE_ACLK_RESET 108 +#define CE3_H_RESET 109 +#define SFAB_CE3_M_RESET 110 +#define SFAB_CE3_S_RESET 111 +#define SATA_RESET 112 +#define CE3_SLEEP_RESET 113 +#define GSS_SLP_RESET 114 +#define GSS_RESET 115 #endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-apq8084.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-apq8084.h new file mode 100644 index 0000000..c167139 --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-apq8084.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_RESET_APQ_MMCC_8084_H +#define _DT_BINDINGS_RESET_APQ_MMCC_8084_H + +#define MMSS_SPDM_RESET 0 +#define MMSS_SPDM_RM_RESET 1 +#define VENUS0_RESET 2 +#define VPU_RESET 3 +#define MDSS_RESET 4 +#define AVSYNC_RESET 5 +#define CAMSS_PHY0_RESET 6 +#define CAMSS_PHY1_RESET 7 +#define CAMSS_PHY2_RESET 8 +#define CAMSS_CSI0_RESET 9 +#define CAMSS_CSI0PHY_RESET 10 +#define CAMSS_CSI0RDI_RESET 11 +#define CAMSS_CSI0PIX_RESET 12 +#define CAMSS_CSI1_RESET 13 +#define CAMSS_CSI1PHY_RESET 14 +#define CAMSS_CSI1RDI_RESET 15 +#define CAMSS_CSI1PIX_RESET 16 +#define CAMSS_CSI2_RESET 17 +#define CAMSS_CSI2PHY_RESET 18 +#define CAMSS_CSI2RDI_RESET 19 +#define CAMSS_CSI2PIX_RESET 20 +#define CAMSS_CSI3_RESET 21 +#define CAMSS_CSI3PHY_RESET 22 +#define CAMSS_CSI3RDI_RESET 23 +#define CAMSS_CSI3PIX_RESET 24 +#define CAMSS_ISPIF_RESET 25 +#define CAMSS_CCI_RESET 26 +#define CAMSS_MCLK0_RESET 27 +#define CAMSS_MCLK1_RESET 28 +#define CAMSS_MCLK2_RESET 29 +#define CAMSS_MCLK3_RESET 30 +#define CAMSS_GP0_RESET 31 +#define CAMSS_GP1_RESET 32 +#define CAMSS_TOP_RESET 33 +#define CAMSS_AHB_RESET 34 +#define CAMSS_MICRO_RESET 35 +#define CAMSS_JPEG_RESET 36 +#define CAMSS_VFE_RESET 37 +#define CAMSS_CSI_VFE0_RESET 38 +#define CAMSS_CSI_VFE1_RESET 39 +#define OXILI_RESET 40 +#define OXILICX_RESET 41 +#define OCMEMCX_RESET 42 +#define MMSS_RBCRP_RESET 43 +#define MMSSNOCAHB_RESET 44 +#define MMSSNOCAXI_RESET 45 + +#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-msm8960.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-msm8960.h index ba36ec6..1174111 100644 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-msm8960.h +++ b/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-msm8960.h @@ -89,5 +89,13 @@ #define CSI2_RESET 72 #define CSI_RDI1_RESET 73 #define CSI_RDI2_RESET 74 +#define GFX3D_AXI_RESET 75 +#define VCAP_AXI_RESET 76 +#define SMMU_VCAP_AHB_RESET 77 +#define VCAP_AHB_RESET 78 +#define CSI_RDI_RESET 79 +#define CSI_PIX_RESET 80 +#define VCAP_NPL_RESET 81 +#define VCAP_RESET 82 #endif diff --git a/sys/gnu/dts/include/dt-bindings/soc/qcom,gsbi.h b/sys/gnu/dts/include/dt-bindings/soc/qcom,gsbi.h new file mode 100644 index 0000000..7ac4292 --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/soc/qcom,gsbi.h @@ -0,0 +1,26 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __DT_BINDINGS_QCOM_GSBI_H +#define __DT_BINDINGS_QCOM_GSBI_H + +#define GSBI_PROT_IDLE 0 +#define GSBI_PROT_I2C_UIM 1 +#define GSBI_PROT_I2C 2 +#define GSBI_PROT_SPI 3 +#define GSBI_PROT_UART_W_FC 4 +#define GSBI_PROT_UIM 5 +#define GSBI_PROT_I2C_UART 6 + +#define GSBI_CRCI_QUP 0 +#define GSBI_CRCI_UART 1 + +#endif diff --git a/sys/gnu/dts/include/dt-bindings/sound/tlv320aic31xx-micbias.h b/sys/gnu/dts/include/dt-bindings/sound/tlv320aic31xx-micbias.h new file mode 100644 index 0000000..f5cb772 --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/sound/tlv320aic31xx-micbias.h @@ -0,0 +1,8 @@ +#ifndef __DT_TLV320AIC31XX_MICBIAS_H +#define __DT_TLV320AIC31XX_MICBIAS_H + +#define MICBIAS_2_0V 1 +#define MICBIAS_2_5V 2 +#define MICBIAS_AVDDV 3 + +#endif /* __DT_TLV320AIC31XX_MICBIAS_H */ diff --git a/sys/gnu/dts/include/dt-bindings/spmi/spmi.h b/sys/gnu/dts/include/dt-bindings/spmi/spmi.h new file mode 100644 index 0000000..d11e1e5 --- /dev/null +++ b/sys/gnu/dts/include/dt-bindings/spmi/spmi.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __DT_BINDINGS_SPMI_H +#define __DT_BINDINGS_SPMI_H + +#define SPMI_USID 0 +#define SPMI_GSID 1 + +#endif |
