IFC to head to catch up the bhyve branch

Approved by:	grehan@

426 files changed, 65542 insertions, 13797 deletions

diff --git a/sys/dev/aac/aac_pci.c b/sys/dev/aac/aac_pci.c
index 6f59e68..485d5ff 100644
--- a/sys/dev/aac/aac_pci.c
+++ b/sys/dev/aac/aac_pci.c
@@ -68,9 +68,7 @@ static device_method_t aac_methods[] = {
 	DEVMETHOD(device_suspend,	aac_suspend),
 	DEVMETHOD(device_resume,	aac_resume),
 
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t aac_pci_driver = {
diff --git a/sys/dev/acpi_support/acpi_wmi.c b/sys/dev/acpi_support/acpi_wmi.c
index 2acc262..16c2dd8 100644
--- a/sys/dev/acpi_support/acpi_wmi.c
+++ b/sys/dev/acpi_support/acpi_wmi.c
@@ -175,7 +175,6 @@ static device_method_t acpi_wmi_methods[] = {
 
 	/* bus interface */
 	DEVMETHOD(bus_add_child,	bus_generic_add_child),
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
 
 	/* acpi_wmi interface */
 	DEVMETHOD(acpi_wmi_provides_guid_string,
@@ -189,7 +188,7 @@ static device_method_t acpi_wmi_methods[] = {
 	DEVMETHOD(acpi_wmi_get_block, acpi_wmi_get_block_method),
 	DEVMETHOD(acpi_wmi_set_block, acpi_wmi_set_block_method),
 
-	{0, 0}
+	DEVMETHOD_END
 };
 
 static driver_t acpi_wmi_driver = {
@@ -265,7 +264,7 @@ acpi_wmi_attach(device_t dev)
 		    acpi_wmi_ec_handler);
 	} else {
 		sc->wmistat_dev_t = make_dev(&wmistat_cdevsw, 0, UID_ROOT,
-		    GID_WHEEL, 0644, "wmistat");
+		    GID_WHEEL, 0644, "wmistat%d", device_get_unit(dev));
 		sc->wmistat_dev_t->si_drv1 = sc;
 		sc->wmistat_open_pid = 0;
 		sc->wmistat_bufptr = -1;
diff --git a/sys/dev/acpica/acpi_battery.c b/sys/dev/acpica/acpi_battery.c
index ba57853..3d7d94a 100644
--- a/sys/dev/acpica/acpi_battery.c
+++ b/sys/dev/acpica/acpi_battery.c
@@ -205,6 +205,14 @@ acpi_battery_get_battinfo(device_t dev, struct acpi_battinfo *battinfo)
 	    bif->lfcap = (bif->lfcap * bif->dvol) / 1000;
 	}
 
+	/*
+	 * The calculation above may set bif->lfcap to zero. This was
+	 * seen on a laptop with a broken battery. The result of the
+	 * division was rounded to zero.
+	 */
+	if (!acpi_battery_bif_valid(bif))
+	    continue;
+
 	/* Calculate percent capacity remaining. */
 	bi[i].cap = (100 * bst[i].cap) / bif->lfcap;
 
diff --git a/sys/dev/acpica/acpi_cpu.c b/sys/dev/acpica/acpi_cpu.c
index d26903d..29034e1 100644
--- a/sys/dev/acpica/acpi_cpu.c
+++ b/sys/dev/acpica/acpi_cpu.c
@@ -187,13 +187,12 @@ static device_method_t acpi_cpu_methods[] = {
     DEVMETHOD(bus_set_resource,	bus_generic_rl_set_resource),
     DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource),
     DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
-    DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
     DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
     DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
     DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
     DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
 
-    {0, 0}
+    DEVMETHOD_END
 };
 
 static driver_t acpi_cpu_driver = {
diff --git a/sys/dev/acpica/acpi_isab.c b/sys/dev/acpica/acpi_isab.c
index 0da0182..3febea7 100644
--- a/sys/dev/acpica/acpi_isab.c
+++ b/sys/dev/acpica/acpi_isab.c
@@ -68,7 +68,6 @@ static device_method_t acpi_isab_methods[] = {
 	DEVMETHOD(device_resume,	bus_generic_resume),
 
 	/* Bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
 	DEVMETHOD(bus_read_ivar,	acpi_isab_read_ivar),
 	DEVMETHOD(bus_alloc_resource,	bus_generic_alloc_resource),
 	DEVMETHOD(bus_release_resource,	bus_generic_release_resource),
@@ -77,7 +76,7 @@ static device_method_t acpi_isab_methods[] = {
 	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
 	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
 
-	{0, 0}
+	DEVMETHOD_END
 };
 
 static driver_t acpi_isab_driver = {
diff --git a/sys/dev/acpica/acpi_pcib_acpi.c b/sys/dev/acpica/acpi_pcib_acpi.c
index 3284fc5..9770f51 100644
--- a/sys/dev/acpica/acpi_pcib_acpi.c
+++ b/sys/dev/acpica/acpi_pcib_acpi.c
@@ -106,7 +106,6 @@ static device_method_t acpi_pcib_acpi_methods[] = {
     DEVMETHOD(device_resume,		bus_generic_resume),
 
     /* Bus interface */
-    DEVMETHOD(bus_print_child,		bus_generic_print_child),
     DEVMETHOD(bus_read_ivar,		acpi_pcib_read_ivar),
     DEVMETHOD(bus_write_ivar,		acpi_pcib_write_ivar),
     DEVMETHOD(bus_alloc_resource,	acpi_pcib_acpi_alloc_resource),
@@ -133,7 +132,7 @@ static device_method_t acpi_pcib_acpi_methods[] = {
     DEVMETHOD(pcib_map_msi,		acpi_pcib_map_msi),
     DEVMETHOD(pcib_power_for_sleep,	acpi_pcib_power_for_sleep),
 
-    {0, 0}
+    DEVMETHOD_END
 };
 
 static devclass_t pcib_devclass;
@@ -512,8 +511,17 @@ acpi_pcib_acpi_alloc_resource(device_t dev, device_t child, int type, int *rid,
     sc = device_get_softc(dev);
     res = pcib_host_res_alloc(&sc->ap_host_res, child, type, rid, start, end,
 	count, flags);
+
+    /*
+     * XXX: If this is a request for a specific range, assume it is
+     * correct and pass it up to the parent.  What we probably want to
+     * do long-term is explicitly trust any firmware-configured
+     * resources during the initial bus scan on boot and then disable
+     * this after that.
+     */
     if (res == NULL && start + count - 1 == end)
-	res = acpi_alloc_sysres(child, type, rid, start, end, count, flags);
+	res = bus_generic_alloc_resource(dev, child, type, rid, start, end,
+	    count, flags);
     return (res);
 #else
     return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
diff --git a/sys/dev/ahci/ahci.c b/sys/dev/ahci/ahci.c
index 6aa131c..df4f66a 100644
--- a/sys/dev/ahci/ahci.c
+++ b/sys/dev/ahci/ahci.c
@@ -291,6 +291,9 @@ static struct {
 #define RECOVERY_REQUEST_SENSE	2
 #define recovery_slot		spriv_field1
 
+static int force_ahci = 1;
+TUNABLE_INT("hw.ahci.force", &force_ahci);
+
 static int
 ahci_probe(device_t dev)
 {
@@ -308,7 +311,8 @@ ahci_probe(device_t dev)
 	for (i = 0; ahci_ids[i].id != 0; i++) {
 		if (ahci_ids[i].id == devid &&
 		    ahci_ids[i].rev <= revid &&
-		    (valid || !(ahci_ids[i].quirks & AHCI_Q_NOFORCE))) {
+		    (valid || (force_ahci == 1 &&
+		     !(ahci_ids[i].quirks & AHCI_Q_NOFORCE)))) {
 			/* Do not attach JMicrons with single PCI function. */
 			if (pci_get_vendor(dev) == 0x197b &&
 			    (pci_read_config(dev, 0xdf, 1) & 0x40) == 0)
@@ -518,7 +522,7 @@ ahci_detach(device_t dev)
 	int i;
 
 	/* Detach & delete all children */
-	device_delete_all_children(dev);
+	device_delete_children(dev);
 
 	/* Free interrupts. */
 	for (i = 0; i < ctlr->numirqs; i++) {
diff --git a/sys/dev/aic7xxx/aicasm/aicasm_macro_scan.l b/sys/dev/aic7xxx/aicasm/aicasm_macro_scan.l
index ac14c12..03fb6b4 100644
--- a/sys/dev/aic7xxx/aicasm/aicasm_macro_scan.l
+++ b/sys/dev/aic7xxx/aicasm/aicasm_macro_scan.l
@@ -66,6 +66,8 @@ static char msgbuf[255];
 extern int mmlex(void);
 %}
 
+%option noinput
+
 WORD		[A-Za-z_][-A-Za-z_0-9]*
 SPACE		[ \t]+
 MCARG		[^(), \t]+
diff --git a/sys/dev/aic7xxx/aicasm/aicasm_scan.l b/sys/dev/aic7xxx/aicasm/aicasm_scan.l
index acc74a4..45da98f 100644
--- a/sys/dev/aic7xxx/aicasm/aicasm_scan.l
+++ b/sys/dev/aic7xxx/aicasm/aicasm_scan.l
@@ -72,6 +72,8 @@ extern void mm_switch_to_buffer(YY_BUFFER_STATE);
 extern void mm_delete_buffer(YY_BUFFER_STATE);
 %}
 
+%option noinput
+
 PATH		([/]*[-A-Za-z0-9_.])+
 WORD		[A-Za-z_][-A-Za-z_0-9]*
 SPACE		[ \t]+
diff --git a/sys/dev/amd/amd.c b/sys/dev/amd/amd.c
deleted file mode 100644
index f4b3d80..0000000
--- a/sys/dev/amd/amd.c
+++ /dev/null
@@ -1,2539 +0,0 @@
-/*-
- *********************************************************************
- *	FILE NAME  : amd.c
- *	     BY    : C.L. Huang 	(ching@tekram.com.tw)
- *		     Erich Chen     (erich@tekram.com.tw)
- *	Description: Device Driver for the amd53c974 PCI Bus Master
- *		     SCSI Host adapter found on cards such as
- *		     the Tekram DC-390(T).
- * (C)Copyright 1995-1999 Tekram Technology Co., Ltd.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *********************************************************************
- * $FreeBSD$
- */
-
-/*
- *********************************************************************
- *	HISTORY:
- *
- *	REV#	DATE	NAME    	DESCRIPTION
- *	1.00  07/02/96	CLH	        First release for RELEASE-2.1.0
- *	1.01  08/20/96	CLH	        Update for RELEASE-2.1.5
- *	1.02  11/06/96	CLH	        Fixed more than 1 LUN scanning
- *	1.03  12/20/96	CLH	        Modify to support 2.2-ALPHA
- *	1.04  12/26/97	CLH	        Modify to support RELEASE-2.2.5
- *	1.05  01/01/99  ERICH CHEN	Modify to support RELEASE-3.0.x (CAM)
- *********************************************************************
- */
-
-/* #define AMD_DEBUG0		*/
-/* #define AMD_DEBUG_SCSI_PHASE */
-
-#include <sys/param.h>
-
-#include <sys/systm.h>
-#include <sys/queue.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/lock.h>
-#include <sys/mutex.h>
-#include <sys/malloc.h>
-
-#include <vm/vm.h>
-#include <vm/pmap.h>
-
-#include <machine/bus.h>
-#include <machine/resource.h>
-#include <sys/bus.h>
-#include <sys/rman.h>
-
-#include <cam/cam.h>
-#include <cam/cam_ccb.h>
-#include <cam/cam_sim.h>
-#include <cam/cam_xpt_sim.h>
-#include <cam/cam_debug.h>
-
-#include <cam/scsi/scsi_all.h>
-#include <cam/scsi/scsi_message.h>
-
-#include <dev/pci/pcivar.h>
-#include <dev/pci/pcireg.h>
-#include <dev/amd/amd.h>
-
-#define PCI_DEVICE_ID_AMD53C974 	0x20201022ul
-#define PCI_BASE_ADDR0	    		0x10
-
-typedef u_int (phase_handler_t)(struct amd_softc *, struct amd_srb *, u_int);
-typedef phase_handler_t *phase_handler_func_t;
-
-static void amd_intr(void *vamd);
-static int amdstart(struct amd_softc *amd, struct amd_srb * pSRB);
-static phase_handler_t amd_NopPhase;
-
-static phase_handler_t amd_DataOutPhase0;
-static phase_handler_t amd_DataInPhase0;
-#define amd_CommandPhase0 amd_NopPhase
-static phase_handler_t amd_StatusPhase0;
-static phase_handler_t amd_MsgOutPhase0;
-static phase_handler_t amd_MsgInPhase0;
-static phase_handler_t amd_DataOutPhase1;
-static phase_handler_t amd_DataInPhase1;
-static phase_handler_t amd_CommandPhase1;
-static phase_handler_t amd_StatusPhase1;
-static phase_handler_t amd_MsgOutPhase1;
-static phase_handler_t amd_MsgInPhase1;
-
-static void	amdsetupcommand(struct amd_softc *amd, struct amd_srb *srb);
-static int	amdparsemsg(struct amd_softc *amd);
-static int	amdhandlemsgreject(struct amd_softc *amd);
-static void	amdconstructsdtr(struct amd_softc *amd,
-				 u_int period, u_int offset);
-static u_int	amdfindclockrate(struct amd_softc *amd, u_int *period);
-static int	amdsentmsg(struct amd_softc *amd, u_int msgtype, int full);
-
-static void DataIO_Comm(struct amd_softc *amd, struct amd_srb *pSRB, u_int dir);
-static void amd_Disconnect(struct amd_softc *amd);
-static void amd_Reselect(struct amd_softc *amd);
-static void SRBdone(struct amd_softc *amd, struct amd_srb *pSRB);
-static void amd_ScsiRstDetect(struct amd_softc *amd);
-static void amd_ResetSCSIBus(struct amd_softc *amd);
-static void RequestSense(struct amd_softc *amd, struct amd_srb *pSRB);
-static void amd_InvalidCmd(struct amd_softc *amd);
-
-static void amd_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs,
-			  int error);
-
-#if 0
-static void amd_timeout(void *arg1);
-static void amd_reset(struct amd_softc *amd);
-#endif
-static u_int8_t * phystovirt(struct amd_srb *pSRB, u_int32_t xferCnt);
-
-void    amd_linkSRB(struct amd_softc *amd);
-static int amd_init(device_t);
-static void amd_load_defaults(struct amd_softc *amd);
-static void amd_load_eeprom_or_defaults(struct amd_softc *amd);
-static int amd_EEpromInDO(struct amd_softc *amd);
-static u_int16_t EEpromGetData1(struct amd_softc *amd);
-static void amd_EnDisableCE(struct amd_softc *amd, int mode, int *regval);
-static void amd_EEpromOutDI(struct amd_softc *amd, int *regval, int Carry);
-static void amd_Prepare(struct amd_softc *amd, int *regval, u_int8_t EEpromCmd);
-static void amd_ReadEEprom(struct amd_softc *amd);
-
-static int amd_probe(device_t);
-static int amd_attach(device_t);
-static void amdcompletematch(struct amd_softc *amd, target_id_t target,
-			     lun_id_t lun, u_int tag, struct srb_queue *queue,
-			     cam_status status);
-static void amdsetsync(struct amd_softc *amd, u_int target, u_int clockrate,
-		       u_int period, u_int offset, u_int type);
-static void amdsettags(struct amd_softc *amd, u_int target, int tagenb);
-
-static __inline void amd_clear_msg_state(struct amd_softc *amd);
-
-static __inline void
-amd_clear_msg_state(struct amd_softc *amd)
-{
-	amd->msgout_len = 0;
-	amd->msgout_index = 0;
-	amd->msgin_index = 0;
-}
-
-static __inline uint32_t
-amd_get_sense_bufaddr(struct amd_softc *amd, struct amd_srb *pSRB)
-{
-	int offset;
-
-	offset = pSRB->TagNumber;
-	return (amd->sense_busaddr + (offset * sizeof(struct scsi_sense_data)));
-}
-
-static __inline struct scsi_sense_data *
-amd_get_sense_buf(struct amd_softc *amd, struct amd_srb *pSRB)
-{
-	int offset;
-
-	offset = pSRB->TagNumber;
-	return (&amd->sense_buffers[offset]);
-}
-
-static __inline uint32_t
-amd_get_sense_bufsize(struct amd_softc *amd, struct amd_srb *pSRB)
-{
-	return (sizeof(struct scsi_sense_data));
-}
-
-/* CAM SIM entry points */
-#define ccb_srb_ptr spriv_ptr0
-#define ccb_amd_ptr spriv_ptr1
-static void	amd_action(struct cam_sim *sim, union ccb *ccb);
-static void	amd_poll(struct cam_sim *sim);
-
-/*
- * State engine function tables indexed by SCSI phase number
- */
-phase_handler_func_t amd_SCSI_phase0[] = {
-	amd_DataOutPhase0,
-	amd_DataInPhase0,
-	amd_CommandPhase0,
-	amd_StatusPhase0,
-	amd_NopPhase,
-	amd_NopPhase,
-	amd_MsgOutPhase0,
-	amd_MsgInPhase0
-};
-
-phase_handler_func_t amd_SCSI_phase1[] = {
-	amd_DataOutPhase1,
-	amd_DataInPhase1,
-	amd_CommandPhase1,
-	amd_StatusPhase1,
-	amd_NopPhase,
-	amd_NopPhase,
-	amd_MsgOutPhase1,
-	amd_MsgInPhase1
-};
-
-/*
- * EEProm/BIOS negotiation periods
- */
-u_int8_t   eeprom_period[] = {
-	 25,	/* 10.0MHz */
-	 32,	/*  8.0MHz */
-	 38,	/*  6.6MHz */
-	 44,	/*  5.7MHz */
-	 50,	/*  5.0MHz */
-	 63,	/*  4.0MHz */
-	 83,	/*  3.0MHz */
-	125	/*  2.0MHz */
-};
-
-/*
- * chip clock setting to SCSI specified sync parameter table.
- */
-u_int8_t tinfo_sync_period[] = {
-	25,	/* 10.0 */
-	32,	/* 8.0 */
-	38,	/* 6.6 */
-	44,	/* 5.7 */
-	50,	/* 5.0 */
-	57,	/* 4.4 */
-	63,	/* 4.0 */
-	70,	/* 3.6 */
-	76,	/* 3.3 */
-	83	/* 3.0 */
-};
-
-static __inline struct amd_srb *
-amdgetsrb(struct amd_softc * amd)
-{
-	int     intflag;
-	struct amd_srb *    pSRB;
-
-	intflag = splcam();
-	pSRB = TAILQ_FIRST(&amd->free_srbs);
-	if (pSRB)
-		TAILQ_REMOVE(&amd->free_srbs, pSRB, links);
-	splx(intflag);
-	return (pSRB);
-}
-
-static void
-amdsetupcommand(struct amd_softc *amd, struct amd_srb *srb)
-{
-	struct scsi_request_sense sense_cmd;
-	u_int8_t *cdb;
-	u_int cdb_len;
-
-	if (srb->SRBFlag & AUTO_REQSENSE) {
-		sense_cmd.opcode = REQUEST_SENSE;
-		sense_cmd.byte2 = srb->pccb->ccb_h.target_lun << 5;
-		sense_cmd.unused[0] = 0;
-		sense_cmd.unused[1] = 0;
-		sense_cmd.length = sizeof(struct scsi_sense_data);
-		sense_cmd.control = 0;
-		cdb = &sense_cmd.opcode;
-		cdb_len = sizeof(sense_cmd);
-	} else {
-		cdb = &srb->CmdBlock[0];
-		cdb_len = srb->ScsiCmdLen;
-	}
-	amd_write8_multi(amd, SCSIFIFOREG, cdb, cdb_len);
-}
-
-/*
- * Attempt to start a waiting transaction.  Interrupts must be disabled
- * upon entry to this function.
- */
-static void
-amdrunwaiting(struct amd_softc *amd) {
-	struct amd_srb *srb;
-
-	if (amd->last_phase != SCSI_BUS_FREE)
-		return;
-
-	srb = TAILQ_FIRST(&amd->waiting_srbs);
-	if (srb == NULL)
-		return;
-	
-	if (amdstart(amd, srb) == 0) {
-		TAILQ_REMOVE(&amd->waiting_srbs, srb, links);
-		TAILQ_INSERT_HEAD(&amd->running_srbs, srb, links);
-	}
-}
-
-static void
-amdexecutesrb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
-{
-	struct	 amd_srb *srb;
-	union	 ccb *ccb;
-	struct	 amd_softc *amd;
-	int	 s;
-
-	srb = (struct amd_srb *)arg;
-	ccb = srb->pccb;
-	amd = (struct amd_softc *)ccb->ccb_h.ccb_amd_ptr;
-
-	if (error != 0) {
-		if (error != EFBIG)
-			printf("amd%d: Unexepected error 0x%x returned from "
-			       "bus_dmamap_load\n", amd->unit, error);
-		if (ccb->ccb_h.status == CAM_REQ_INPROG) {
-			xpt_freeze_devq(ccb->ccb_h.path, /*count*/1);
-			ccb->ccb_h.status = CAM_REQ_TOO_BIG|CAM_DEV_QFRZN;
-		}
-		TAILQ_INSERT_HEAD(&amd->free_srbs, srb, links);
-		xpt_done(ccb);
-		return;
-	}
-
-	if (nseg != 0) {
-		struct amd_sg *sg;
-		bus_dma_segment_t *end_seg;
-		bus_dmasync_op_t op;
-
-		end_seg = dm_segs + nseg;
-
-		/* Copy the segments into our SG list */
-		srb->pSGlist = &srb->SGsegment[0];
-		sg = srb->pSGlist;
-		while (dm_segs < end_seg) {
-			sg->SGXLen = dm_segs->ds_len;
-			sg->SGXPtr = dm_segs->ds_addr;
-			sg++;
-			dm_segs++;
-		}
-
-		if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
-			op = BUS_DMASYNC_PREREAD;
-		else
-			op = BUS_DMASYNC_PREWRITE;
-
-		bus_dmamap_sync(amd->buffer_dmat, srb->dmamap, op);
-
-	}
-	srb->SGcount = nseg;
-	srb->SGIndex = 0;
-	srb->AdaptStatus = 0;
-	srb->TargetStatus = 0;
-	srb->MsgCnt = 0;
-	srb->SRBStatus = 0;
-	srb->SRBFlag = 0;
-	srb->SRBState = 0;
-	srb->TotalXferredLen = 0;
-	srb->SGPhysAddr = 0;
-	srb->SGToBeXferLen = 0;
-	srb->EndMessage = 0;
-
-	s = splcam();
-
-	/*
-	 * Last time we need to check if this CCB needs to
-	 * be aborted.
-	 */
-	if (ccb->ccb_h.status != CAM_REQ_INPROG) {
-		if (nseg != 0)
-			bus_dmamap_unload(amd->buffer_dmat, srb->dmamap);
-		TAILQ_INSERT_HEAD(&amd->free_srbs, srb, links);
-		xpt_done(ccb);
-		splx(s);
-		return;
-	}
-	ccb->ccb_h.status |= CAM_SIM_QUEUED;
-#if 0
-	/* XXX Need a timeout handler */
-	ccb->ccb_h.timeout_ch =
-	    timeout(amdtimeout, (caddr_t)srb,
-		    (ccb->ccb_h.timeout * hz) / 1000);
-#endif
-	TAILQ_INSERT_TAIL(&amd->waiting_srbs, srb, links);
-	amdrunwaiting(amd);
-	splx(s);
-}
-
-static void
-amd_action(struct cam_sim * psim, union ccb * pccb)
-{
-	struct amd_softc *    amd;
-	u_int   target_id;
-
-	CAM_DEBUG(pccb->ccb_h.path, CAM_DEBUG_TRACE, ("amd_action\n"));
-
-	amd = (struct amd_softc *) cam_sim_softc(psim);
-	target_id = pccb->ccb_h.target_id;
-
-	switch (pccb->ccb_h.func_code) {
-	case XPT_SCSI_IO:
-	{
-		struct amd_srb *    pSRB;
-		struct ccb_scsiio *pcsio;
-
-		pcsio = &pccb->csio;
-
-		/*
-		 * Assign an SRB and connect it with this ccb.
-		 */
-		pSRB = amdgetsrb(amd);
-
-		if (!pSRB) {
-			/* Freeze SIMQ */
-			pccb->ccb_h.status = CAM_RESRC_UNAVAIL;
-			xpt_done(pccb);
-			return;
-		}
-		pSRB->pccb = pccb;
-		pccb->ccb_h.ccb_srb_ptr = pSRB;
-		pccb->ccb_h.ccb_amd_ptr = amd;
-		pSRB->ScsiCmdLen = pcsio->cdb_len;
-		bcopy(pcsio->cdb_io.cdb_bytes, pSRB->CmdBlock, pcsio->cdb_len);
-		if ((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
-			if ((pccb->ccb_h.flags & CAM_SCATTER_VALID) == 0) {
-				/*
-				 * We've been given a pointer
-				 * to a single buffer.
-				 */
-				if ((pccb->ccb_h.flags & CAM_DATA_PHYS) == 0) {
-					int s;
-					int error;
-
-					s = splsoftvm();
-					error =
-					    bus_dmamap_load(amd->buffer_dmat,
-							    pSRB->dmamap,
-							    pcsio->data_ptr,
-							    pcsio->dxfer_len,
-							    amdexecutesrb,
-							    pSRB, /*flags*/0);
-					if (error == EINPROGRESS) {
-						/*
-						 * So as to maintain
-						 * ordering, freeze the
-						 * controller queue
-						 * until our mapping is
-						 * returned.
-						 */
-						xpt_freeze_simq(amd->psim, 1);
-						pccb->ccb_h.status |=
-						    CAM_RELEASE_SIMQ;
-					}
-					splx(s);
-				} else {
-					struct bus_dma_segment seg;
-
-					/* Pointer to physical buffer */
-					seg.ds_addr =
-					    (bus_addr_t)pcsio->data_ptr;
-					seg.ds_len = pcsio->dxfer_len;
-					amdexecutesrb(pSRB, &seg, 1, 0);
-				}
-			} else {
-				struct bus_dma_segment *segs;
-
-				if ((pccb->ccb_h.flags & CAM_SG_LIST_PHYS) == 0
-				 || (pccb->ccb_h.flags & CAM_DATA_PHYS) != 0) {
-					TAILQ_INSERT_HEAD(&amd->free_srbs,
-							  pSRB, links);
-					pccb->ccb_h.status = CAM_PROVIDE_FAIL;
-					xpt_done(pccb);
-					return;
-				}
-
-				/* Just use the segments provided */
-				segs =
-				    (struct bus_dma_segment *)pcsio->data_ptr;
-				amdexecutesrb(pSRB, segs, pcsio->sglist_cnt, 0);
-			}
-		} else
-			amdexecutesrb(pSRB, NULL, 0, 0);
-		break;
-	}
-	case XPT_PATH_INQ:
-	{
-		struct ccb_pathinq *cpi = &pccb->cpi;
-
-		cpi->version_num = 1;
-		cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE;
-		cpi->target_sprt = 0;
-		cpi->hba_misc = 0;
-		cpi->hba_eng_cnt = 0;
-		cpi->max_target = 7;
-		cpi->max_lun = amd->max_lun;	/* 7 or 0 */
-		cpi->initiator_id = amd->AdaptSCSIID;
-		cpi->bus_id = cam_sim_bus(psim);
-		strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
-		strncpy(cpi->hba_vid, "TRM-AMD", HBA_IDLEN);
-		strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN);
-		cpi->unit_number = cam_sim_unit(psim);
-                cpi->transport = XPORT_SPI;
-                cpi->transport_version = 2;
-                cpi->protocol = PROTO_SCSI;
-                cpi->protocol_version = SCSI_REV_2;
-		cpi->ccb_h.status = CAM_REQ_CMP;
-		xpt_done(pccb);
-		break;
-	}
-	case XPT_ABORT:
-		pccb->ccb_h.status = CAM_REQ_INVALID;
-		xpt_done(pccb);
-		break;
-	case XPT_RESET_BUS:
-	{
-
-		int     i;
-
-		amd_ResetSCSIBus(amd);
-		amd->ACBFlag = 0;
-
-		for (i = 0; i < 500; i++) {
-			DELAY(1000);	/* Wait until our interrupt
-					 * handler sees it */
-		}
-
-		pccb->ccb_h.status = CAM_REQ_CMP;
-		xpt_done(pccb);
-		break;
-	}
-	case XPT_RESET_DEV:
-		pccb->ccb_h.status = CAM_REQ_INVALID;
-		xpt_done(pccb);
-		break;
-	case XPT_TERM_IO:
-		pccb->ccb_h.status = CAM_REQ_INVALID;
-		xpt_done(pccb);
-		break;
-	case XPT_GET_TRAN_SETTINGS:
-	{
-		struct ccb_trans_settings *cts = &pccb->cts;
-		struct amd_target_info *targ_info = &amd->tinfo[target_id];
-		struct amd_transinfo *tinfo;
-		int     intflag;
-		struct ccb_trans_settings_scsi *scsi =
-		    &cts->proto_specific.scsi;
-		struct ccb_trans_settings_spi *spi =
-		    &cts->xport_specific.spi;
-
-		cts->protocol = PROTO_SCSI;
-		cts->protocol_version = SCSI_REV_2;
-		cts->transport = XPORT_SPI;
-		cts->transport_version = 2;
-
-		intflag = splcam();
-		if (cts->type == CTS_TYPE_CURRENT_SETTINGS) {
-			/* current transfer settings */
-			if (targ_info->disc_tag & AMD_CUR_DISCENB) {
-				spi->flags = CTS_SPI_FLAGS_DISC_ENB;
-			} else {
-				spi->flags = 0;
-			}
-			if (targ_info->disc_tag & AMD_CUR_TAGENB) {
-				scsi->flags = CTS_SCSI_FLAGS_TAG_ENB;
-			} else {
-				scsi->flags = 0;
-			}
-			tinfo = &targ_info->current;
-		} else {
-			/* default(user) transfer settings */
-			if (targ_info->disc_tag & AMD_USR_DISCENB) {
-				spi->flags = CTS_SPI_FLAGS_DISC_ENB;
-			} else {
-				spi->flags = 0;
-			}
-			if (targ_info->disc_tag & AMD_USR_TAGENB) {
-				scsi->flags = CTS_SCSI_FLAGS_TAG_ENB;
-			} else {
-				scsi->flags = 0;
-			}
-			tinfo = &targ_info->user;
-		}
-		spi->sync_period = tinfo->period;
-		spi->sync_offset = tinfo->offset;
-		splx(intflag);
-
-		spi->bus_width = MSG_EXT_WDTR_BUS_8_BIT;
-		spi->valid = CTS_SPI_VALID_SYNC_RATE
-			   | CTS_SPI_VALID_SYNC_OFFSET
-			   | CTS_SPI_VALID_BUS_WIDTH
-			   | CTS_SPI_VALID_DISC;
-		scsi->valid = CTS_SCSI_VALID_TQ;
-		pccb->ccb_h.status = CAM_REQ_CMP;
-		xpt_done(pccb);
-		break;
-	}
-#define	IS_CURRENT_SETTINGS(c)	(c->type == CTS_TYPE_CURRENT_SETTINGS)
-#define	IS_USER_SETTINGS(c)	(c->type == CTS_TYPE_USER_SETTINGS)
-	case XPT_SET_TRAN_SETTINGS:
-	{
-		struct ccb_trans_settings *cts = &pccb->cts;
-		struct amd_target_info *targ_info;
-		u_int  update_type = 0;
-		int    intflag;
-		int    last_entry;
-		struct ccb_trans_settings_scsi *scsi =
-		    &cts->proto_specific.scsi;
-		struct ccb_trans_settings_spi *spi =
-		    &cts->xport_specific.spi;
-		if (IS_CURRENT_SETTINGS(cts)) {
-			update_type |= AMD_TRANS_GOAL;
-		} else if (IS_USER_SETTINGS(cts)) {
-			update_type |= AMD_TRANS_USER;
-		}
-		if (update_type == 0
-		 || update_type == (AMD_TRANS_USER|AMD_TRANS_GOAL)) {
-			cts->ccb_h.status = CAM_REQ_INVALID;
-			xpt_done(pccb);
-		}
-
-		intflag = splcam();
-		targ_info = &amd->tinfo[target_id];
-
-		if ((spi->valid & CTS_SPI_VALID_DISC) != 0) {
-			if (update_type & AMD_TRANS_GOAL) {
-				if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB)
-				   != 0) {
-					targ_info->disc_tag |= AMD_CUR_DISCENB;
-				} else {
-					targ_info->disc_tag &= ~AMD_CUR_DISCENB;
-				}
-			}
-			if (update_type & AMD_TRANS_USER) {
-				if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB)
-				   != 0) {
-					targ_info->disc_tag |= AMD_USR_DISCENB;
-				} else {
-					targ_info->disc_tag &= ~AMD_USR_DISCENB;
-				}
-			}
-		}
-		if ((scsi->valid & CTS_SCSI_VALID_TQ) != 0) {
-			if (update_type & AMD_TRANS_GOAL) {
-				if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB)
-				   != 0) {
-					targ_info->disc_tag |= AMD_CUR_TAGENB;
-				} else {
-					targ_info->disc_tag &= ~AMD_CUR_TAGENB;
-				}
-			}
-			if (update_type & AMD_TRANS_USER) {
-				if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB)
-				    != 0) {
-					targ_info->disc_tag |= AMD_USR_TAGENB;
-				} else {
-					targ_info->disc_tag &= ~AMD_USR_TAGENB;
-				}
-			}
-		}
-
-		if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) == 0) {
-			if (update_type & AMD_TRANS_GOAL)
-				spi->sync_offset = targ_info->goal.offset;
-			else
-				spi->sync_offset = targ_info->user.offset;
-		}
-
-		if (spi->sync_offset > AMD_MAX_SYNC_OFFSET)
-			spi->sync_offset = AMD_MAX_SYNC_OFFSET;
-
-		if ((spi->valid & CTS_SPI_VALID_SYNC_RATE) == 0) {
-			if (update_type & AMD_TRANS_GOAL)
-				spi->sync_period = targ_info->goal.period;
-			else
-				spi->sync_period = targ_info->user.period;
-		}
-
-		last_entry = sizeof(tinfo_sync_period) - 1;
-		if ((spi->sync_period != 0)
-		 && (spi->sync_period < tinfo_sync_period[0]))
-			spi->sync_period = tinfo_sync_period[0];
-		if (spi->sync_period > tinfo_sync_period[last_entry])
-		 	spi->sync_period = 0;
-		if (spi->sync_offset == 0)
-			spi->sync_period = 0;
-
-		if ((update_type & AMD_TRANS_USER) != 0) {
-			targ_info->user.period = spi->sync_period;
-			targ_info->user.offset = spi->sync_offset;
-		}
-		if ((update_type & AMD_TRANS_GOAL) != 0) {
-			targ_info->goal.period = spi->sync_period;
-			targ_info->goal.offset = spi->sync_offset;
-		}
-		splx(intflag);
-		pccb->ccb_h.status = CAM_REQ_CMP;
-		xpt_done(pccb);
-		break;
-	}
-	case XPT_CALC_GEOMETRY:
-	{
-		int     extended;
-
-		extended = (amd->eepromBuf[EE_MODE2] & GREATER_1G) != 0;
-		cam_calc_geometry(&pccb->ccg, extended);
-		xpt_done(pccb);
-		break;
-	}
-	default:
-		pccb->ccb_h.status = CAM_REQ_INVALID;
-		xpt_done(pccb);
-		break;
-	}
-}
-
-static void
-amd_poll(struct cam_sim * psim)
-{
-	amd_intr(cam_sim_softc(psim));
-}
-
-static u_int8_t * 
-phystovirt(struct amd_srb * pSRB, u_int32_t xferCnt)
-{
-	intptr_t   dataPtr;
-	struct ccb_scsiio *pcsio;
-	u_int8_t   i;
-	struct amd_sg *    pseg;
-
-	dataPtr = 0;
-	pcsio = &pSRB->pccb->csio;
-
-	dataPtr = (intptr_t) pcsio->data_ptr;
-	pseg = pSRB->SGsegment;
-	for (i = 0; i < pSRB->SGIndex; i++) {
-		dataPtr += (int) pseg->SGXLen;
-		pseg++;
-	}
-	dataPtr += (int) xferCnt;
-	return ((u_int8_t *) dataPtr);
-}
-
-static void
-amd_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
-{
-	bus_addr_t *baddr;
-
-	baddr = (bus_addr_t *)arg;
-	*baddr = segs->ds_addr;
-}
-
-static void
-ResetDevParam(struct amd_softc * amd)
-{
-	u_int target;
-
-	for (target = 0; target <= amd->max_id; target++) {
-		if (amd->AdaptSCSIID != target) {
-			amdsetsync(amd, target, /*clockrate*/0,
-				   /*period*/0, /*offset*/0, AMD_TRANS_CUR);
-		}
-	}
-}
-
-static void
-amdcompletematch(struct amd_softc *amd, target_id_t target, lun_id_t lun,
-		 u_int tag, struct srb_queue *queue, cam_status status)
-{
-	struct amd_srb *srb;
-	struct amd_srb *next_srb;
-
-	for (srb = TAILQ_FIRST(queue); srb != NULL; srb = next_srb) {
-		union ccb *ccb;
-
-		next_srb = TAILQ_NEXT(srb, links);
-		if (srb->pccb->ccb_h.target_id != target
-		 && target != CAM_TARGET_WILDCARD)
-			continue;
-
-		if (srb->pccb->ccb_h.target_lun != lun
-		 && lun != CAM_LUN_WILDCARD)
-			continue;
-
-		if (srb->TagNumber != tag
-		 && tag != AMD_TAG_WILDCARD)
-			continue;
-		
-		ccb = srb->pccb;
-		TAILQ_REMOVE(queue, srb, links);
-		TAILQ_INSERT_HEAD(&amd->free_srbs, srb, links);
-		if ((ccb->ccb_h.status & CAM_DEV_QFRZN) == 0
-		 && (status & CAM_DEV_QFRZN) != 0)
-			xpt_freeze_devq(ccb->ccb_h.path, /*count*/1);
-		ccb->ccb_h.status = status;
-		xpt_done(ccb);
-	}
-
-}
-
-static void
-amdsetsync(struct amd_softc *amd, u_int target, u_int clockrate,
-	   u_int period, u_int offset, u_int type)
-{
-	struct amd_target_info *tinfo;
-	u_int old_period;
-	u_int old_offset;
-
-	tinfo = &amd->tinfo[target];
-	old_period = tinfo->current.period;
-	old_offset = tinfo->current.offset;
-	if ((type & AMD_TRANS_CUR) != 0
-	 && (old_period != period || old_offset != offset)) {
-		struct cam_path *path;
-
-		tinfo->current.period = period;
-		tinfo->current.offset = offset;
-		tinfo->sync_period_reg = clockrate;
-		tinfo->sync_offset_reg = offset;
-		tinfo->CtrlR3 &= ~FAST_SCSI;
-		tinfo->CtrlR4 &= ~EATER_25NS;
-		if (clockrate > 7)
-			tinfo->CtrlR4 |= EATER_25NS;
-		else
-			tinfo->CtrlR3 |= FAST_SCSI;
-
-		if ((type & AMD_TRANS_ACTIVE) == AMD_TRANS_ACTIVE) {
-			amd_write8(amd, SYNCPERIOREG, tinfo->sync_period_reg);
-			amd_write8(amd, SYNCOFFREG, tinfo->sync_offset_reg);
-			amd_write8(amd, CNTLREG3, tinfo->CtrlR3);
-			amd_write8(amd, CNTLREG4, tinfo->CtrlR4);
-		}
-		/* If possible, update the XPT's notion of our transfer rate */
-		if (xpt_create_path(&path, /*periph*/NULL,
-				    cam_sim_path(amd->psim), target,
-				    CAM_LUN_WILDCARD) == CAM_REQ_CMP) {
-			struct ccb_trans_settings neg;
-			struct ccb_trans_settings_spi *spi =
-			    &neg.xport_specific.spi;
-			xpt_setup_ccb(&neg.ccb_h, path, /*priority*/1);
-			memset(&neg, 0, sizeof (neg));
-			spi->sync_period = period;
-			spi->sync_offset = offset;
-			spi->valid = CTS_SPI_VALID_SYNC_RATE
-				  | CTS_SPI_VALID_SYNC_OFFSET;
-			xpt_async(AC_TRANSFER_NEG, path, &neg);
-			xpt_free_path(path);	
-		}
-	}
-	if ((type & AMD_TRANS_GOAL) != 0) {
-		tinfo->goal.period = period;
-		tinfo->goal.offset = offset;
-	}
-
-	if ((type & AMD_TRANS_USER) != 0) {
-		tinfo->user.period = period;
-		tinfo->user.offset = offset;
-	}
-}
-
-static void
-amdsettags(struct amd_softc *amd, u_int target, int tagenb)
-{
-	panic("Implement me!\n");
-}
-
-
-#if 0
-/*
- **********************************************************************
- * Function : amd_reset (struct amd_softc * amd)
- * Purpose  : perform a hard reset on the SCSI bus( and AMD chip).
- * Inputs   : cmd - command which caused the SCSI RESET
- **********************************************************************
- */
-static void
-amd_reset(struct amd_softc * amd)
-{
-	int	   intflag;
-	u_int8_t   bval;
-	u_int16_t  i;
-
-
-#ifdef AMD_DEBUG0
-	printf("DC390: RESET");
-#endif
-
-	intflag = splcam();
-	bval = amd_read8(amd, CNTLREG1);
-	bval |= DIS_INT_ON_SCSI_RST;
-	amd_write8(amd, CNTLREG1, bval);	/* disable interrupt */
-	amd_ResetSCSIBus(amd);
-
-	for (i = 0; i < 500; i++) {
-		DELAY(1000);
-	}
-
-	bval = amd_read8(amd, CNTLREG1);
-	bval &= ~DIS_INT_ON_SCSI_RST;
-	amd_write8(amd, CNTLREG1, bval);	/* re-enable interrupt */
-
-	amd_write8(amd, DMA_Cmd, DMA_IDLE_CMD);
-	amd_write8(amd, SCSICMDREG, CLEAR_FIFO_CMD);
-
-	ResetDevParam(amd);
-	amdcompletematch(amd, CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD,
-			 AMD_TAG_WILDCARD, &amd->running_srbs,
-			 CAM_DEV_QFRZN|CAM_SCSI_BUS_RESET);
-	amdcompletematch(amd, CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD,
-			 AMD_TAG_WILDCARD, &amd->waiting_srbs,
-			 CAM_DEV_QFRZN|CAM_SCSI_BUS_RESET);
-	amd->active_srb = NULL;
-	amd->ACBFlag = 0;
-	splx(intflag);
-	return;
-}
-
-void
-amd_timeout(void *arg1)
-{
-	struct amd_srb *    pSRB;
-
-	pSRB = (struct amd_srb *) arg1;
-}
-#endif
-
-static int
-amdstart(struct amd_softc *amd, struct amd_srb *pSRB)
-{
-	union ccb *pccb;
-	struct ccb_scsiio *pcsio;
-	struct amd_target_info *targ_info;
-	u_int identify_msg;
-	u_int command;
-	u_int target;
-	u_int lun;
-
-	pccb = pSRB->pccb;
-	pcsio = &pccb->csio;
-	target = pccb->ccb_h.target_id;
-	lun = pccb->ccb_h.target_lun;
-	targ_info = &amd->tinfo[target];
-
-	amd_clear_msg_state(amd);
-	amd_write8(amd, SCSIDESTIDREG, target);
-	amd_write8(amd, SYNCPERIOREG, targ_info->sync_period_reg);
-	amd_write8(amd, SYNCOFFREG, targ_info->sync_offset_reg);
-	amd_write8(amd, CNTLREG1, targ_info->CtrlR1);
-	amd_write8(amd, CNTLREG3, targ_info->CtrlR3);
-	amd_write8(amd, CNTLREG4, targ_info->CtrlR4);
-	amd_write8(amd, SCSICMDREG, CLEAR_FIFO_CMD);
-
-	identify_msg = MSG_IDENTIFYFLAG | lun;
-	if ((targ_info->disc_tag & AMD_CUR_DISCENB) != 0
-	  && (pccb->ccb_h.flags & CAM_DIS_DISCONNECT) == 0
-	  && (pSRB->CmdBlock[0] != REQUEST_SENSE)
-	  && (pSRB->SRBFlag & AUTO_REQSENSE) == 0)
-		identify_msg |= MSG_IDENTIFY_DISCFLAG;
-
-	amd_write8(amd, SCSIFIFOREG, identify_msg);
-	if ((targ_info->disc_tag & AMD_CUR_TAGENB) == 0
-	  || (identify_msg & MSG_IDENTIFY_DISCFLAG) == 0)
-		pccb->ccb_h.flags &= ~CAM_TAG_ACTION_VALID;
-	if (targ_info->current.period != targ_info->goal.period
-	 || targ_info->current.offset != targ_info->goal.offset) {
-		command = SEL_W_ATN_STOP;
-		amdconstructsdtr(amd, targ_info->goal.period,
-				 targ_info->goal.offset);
-	} else if ((pccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0) {
-		command = SEL_W_ATN2;
-		pSRB->SRBState = SRB_START;
-		amd_write8(amd, SCSIFIFOREG, pcsio->tag_action);
-		amd_write8(amd, SCSIFIFOREG, pSRB->TagNumber);
-	} else {
-		command = SEL_W_ATN;
-		pSRB->SRBState = SRB_START;
-	}
-	if (command != SEL_W_ATN_STOP)
-		amdsetupcommand(amd, pSRB);
-
-	if (amd_read8(amd, SCSISTATREG) & INTERRUPT) {
-		pSRB->SRBState = SRB_READY;
-		return (1);
-	} else {
-		amd->last_phase = SCSI_ARBITRATING;
-		amd_write8(amd, SCSICMDREG, command);
-		amd->active_srb = pSRB;
-		amd->cur_target = target;
-		amd->cur_lun = lun;
-		return (0);
-	}
-}
-
-/*
- *  Catch an interrupt from the adapter.
- *  Process pending device interrupts.
- */
-static void 
-amd_intr(void   *arg)
-{
-	struct amd_softc *amd;
-	struct amd_srb *pSRB;
-	u_int  internstat = 0;
-	u_int  scsistat;
-	u_int  intstat;
-
-	amd = (struct amd_softc *)arg;
-
-	if (amd == NULL) {
-#ifdef AMD_DEBUG0
-		printf("amd_intr: amd NULL return......");
-#endif
-		return;
-	}
-
-	scsistat = amd_read8(amd, SCSISTATREG);
-	if (!(scsistat & INTERRUPT)) {
-#ifdef AMD_DEBUG0
-		printf("amd_intr: scsistat = NULL ,return......");
-#endif
-		return;
-	}
-#ifdef AMD_DEBUG_SCSI_PHASE
-	printf("scsistat=%2x,", scsistat);
-#endif
-
-	internstat = amd_read8(amd, INTERNSTATREG);
-	intstat = amd_read8(amd, INTSTATREG);
-
-#ifdef AMD_DEBUG_SCSI_PHASE
-	printf("intstat=%2x,", intstat);
-#endif
-
-	if (intstat & DISCONNECTED) {
-		amd_Disconnect(amd);
-		return;
-	}
-	if (intstat & RESELECTED) {
-		amd_Reselect(amd);
-		return;
-	}
-	if (intstat & INVALID_CMD) {
-		amd_InvalidCmd(amd);
-		return;
-	}
-	if (intstat & SCSI_RESET_) {
-		amd_ScsiRstDetect(amd);
-		return;
-	}
-	if (intstat & (SUCCESSFUL_OP + SERVICE_REQUEST)) {
-		pSRB = amd->active_srb;
-		/*
-		 * Run our state engine.  First perform
-		 * post processing for the last phase we
-		 * were in, followed by any processing
-		 * required to handle the current phase.
-		 */
-		scsistat =
-		    amd_SCSI_phase0[amd->last_phase](amd, pSRB, scsistat);
-		amd->last_phase = scsistat & SCSI_PHASE_MASK;
-		(void)amd_SCSI_phase1[amd->last_phase](amd, pSRB, scsistat);
-	}
-}
-
-static u_int
-amd_DataOutPhase0(struct amd_softc *amd, struct amd_srb *pSRB, u_int scsistat)
-{
-	struct amd_sg *psgl;
-	u_int32_t   ResidCnt, xferCnt;
-
-	if (!(pSRB->SRBState & SRB_XFERPAD)) {
-		if (scsistat & PARITY_ERR) {
-			pSRB->SRBStatus |= PARITY_ERROR;
-		}
-		if (scsistat & COUNT_2_ZERO) {
-			while ((amd_read8(amd, DMA_Status)&DMA_XFER_DONE) == 0)
-				;
-			pSRB->TotalXferredLen += pSRB->SGToBeXferLen;
-			pSRB->SGIndex++;
-			if (pSRB->SGIndex < pSRB->SGcount) {
-				pSRB->pSGlist++;
-				psgl = pSRB->pSGlist;
-				pSRB->SGPhysAddr = psgl->SGXPtr;
-				pSRB->SGToBeXferLen = psgl->SGXLen;
-			} else {
-				pSRB->SGToBeXferLen = 0;
-			}
-		} else {
-			ResidCnt = amd_read8(amd, CURRENTFIFOREG) & 0x1f;
-			ResidCnt += amd_read8(amd, CTCREG_LOW)
-				  | (amd_read8(amd, CTCREG_MID) << 8)
-				  | (amd_read8(amd, CURTXTCNTREG) << 16);
-
-			xferCnt = pSRB->SGToBeXferLen - ResidCnt;
-			pSRB->SGPhysAddr += xferCnt;
-			pSRB->TotalXferredLen += xferCnt;
-			pSRB->SGToBeXferLen = ResidCnt;
-		}
-	}
-	amd_write8(amd, DMA_Cmd, WRITE_DIRECTION | DMA_IDLE_CMD);
-	return (scsistat);
-}
-
-static u_int
-amd_DataInPhase0(struct amd_softc *amd, struct amd_srb *pSRB, u_int scsistat)
-{
-	u_int8_t bval;
-	u_int16_t  i, residual;
-	struct amd_sg *psgl;
-	u_int32_t   ResidCnt, xferCnt;
-	u_int8_t *  ptr;
-
-	if (!(pSRB->SRBState & SRB_XFERPAD)) {
-		if (scsistat & PARITY_ERR) {
-			pSRB->SRBStatus |= PARITY_ERROR;
-		}
-		if (scsistat & COUNT_2_ZERO) {
-			while (1) {
-				bval = amd_read8(amd, DMA_Status);
-				if ((bval & DMA_XFER_DONE) != 0)
-					break;
-			}
-			amd_write8(amd, DMA_Cmd, READ_DIRECTION|DMA_IDLE_CMD);
-
-			pSRB->TotalXferredLen += pSRB->SGToBeXferLen;
-			pSRB->SGIndex++;
-			if (pSRB->SGIndex < pSRB->SGcount) {
-				pSRB->pSGlist++;
-				psgl = pSRB->pSGlist;
-				pSRB->SGPhysAddr = psgl->SGXPtr;
-				pSRB->SGToBeXferLen = psgl->SGXLen;
-			} else {
-				pSRB->SGToBeXferLen = 0;
-			}
-		} else {	/* phase changed */
-			residual = 0;
-			bval = amd_read8(amd, CURRENTFIFOREG);
-			while (bval & 0x1f) {
-				if ((bval & 0x1f) == 1) {
-					for (i = 0; i < 0x100; i++) {
-						bval = amd_read8(amd, CURRENTFIFOREG);
-						if (!(bval & 0x1f)) {
-							goto din_1;
-						} else if (i == 0x0ff) {
-							residual = 1;
-							goto din_1;
-						}
-					}
-				} else {
-					bval = amd_read8(amd, CURRENTFIFOREG);
-				}
-			}
-	din_1:
-			amd_write8(amd, DMA_Cmd, READ_DIRECTION|DMA_BLAST_CMD);
-			for (i = 0; i < 0x8000; i++) {
-				if ((amd_read8(amd, DMA_Status)&BLAST_COMPLETE))
-					break;
-			}
-			amd_write8(amd, DMA_Cmd, READ_DIRECTION|DMA_IDLE_CMD);
-
-			ResidCnt = amd_read8(amd, CTCREG_LOW)
-				 | (amd_read8(amd, CTCREG_MID) << 8)
-				 | (amd_read8(amd, CURTXTCNTREG) << 16);
-			xferCnt = pSRB->SGToBeXferLen - ResidCnt;
-			pSRB->SGPhysAddr += xferCnt;
-			pSRB->TotalXferredLen += xferCnt;
-			pSRB->SGToBeXferLen = ResidCnt;
-			if (residual) {
-				/* get residual byte */	
-				bval = amd_read8(amd, SCSIFIFOREG);
-				ptr = phystovirt(pSRB, xferCnt);
-				*ptr = bval;
-				pSRB->SGPhysAddr++;
-				pSRB->TotalXferredLen++;
-				pSRB->SGToBeXferLen--;
-			}
-		}
-	}
-	return (scsistat);
-}
-
-static u_int
-amd_StatusPhase0(struct amd_softc *amd, struct amd_srb *pSRB, u_int scsistat)
-{
-	pSRB->TargetStatus = amd_read8(amd, SCSIFIFOREG);
-	/* get message */
-	pSRB->EndMessage = amd_read8(amd, SCSIFIFOREG);
-	pSRB->SRBState = SRB_COMPLETED;
-	amd_write8(amd, SCSICMDREG, MSG_ACCEPTED_CMD);
-	return (SCSI_NOP0);
-}
-
-static u_int
-amd_MsgOutPhase0(struct amd_softc *amd, struct amd_srb *pSRB, u_int scsistat)
-{
-	if (pSRB->SRBState & (SRB_UNEXPECT_RESEL + SRB_ABORT_SENT)) {
-		scsistat = SCSI_NOP0;
-	}
-	return (scsistat);
-}
-
-static u_int
-amd_MsgInPhase0(struct amd_softc *amd, struct amd_srb *pSRB, u_int scsistat)
-{
-	int done;
-	
-	amd->msgin_buf[amd->msgin_index]  = amd_read8(amd, SCSIFIFOREG);
-
-	done = amdparsemsg(amd);
-	if (done)
-		amd->msgin_index = 0;
-	else 
-		amd->msgin_index++;
-	return (SCSI_NOP0);
-}
-
-static int
-amdparsemsg(struct amd_softc *amd)
-{
-	int	reject;
-	int	done;
-	int	response;
-
-	done = FALSE;
-	response = FALSE;
-	reject = FALSE;
-
-	/*
-	 * Parse as much of the message as is availible,
-	 * rejecting it if we don't support it.  When
-	 * the entire message is availible and has been
-	 * handled, return TRUE indicating that we have
-	 * parsed an entire message.
-	 */
-	switch (amd->msgin_buf[0]) {
-	case MSG_DISCONNECT:
-		amd->active_srb->SRBState = SRB_DISCONNECT;
-		amd->disc_count[amd->cur_target][amd->cur_lun]++;
-		done = TRUE;
-		break;
-	case MSG_SIMPLE_Q_TAG:
-	{
-		struct amd_srb *disc_srb;
-
-		if (amd->msgin_index < 1)
-			break;		
-		disc_srb = &amd->SRB_array[amd->msgin_buf[1]];
-		if (amd->active_srb != NULL
-		 || disc_srb->SRBState != SRB_DISCONNECT
-		 || disc_srb->pccb->ccb_h.target_id != amd->cur_target
-		 || disc_srb->pccb->ccb_h.target_lun != amd->cur_lun) {
-			printf("amd%d: Unexpected tagged reselection "
-			       "for target %d, Issuing Abort\n", amd->unit,
-			       amd->cur_target);
-			amd->msgout_buf[0] = MSG_ABORT;
-			amd->msgout_len = 1;
-			response = TRUE;
-			break;
-		}
-		amd->active_srb = disc_srb;
-		amd->disc_count[amd->cur_target][amd->cur_lun]--;
-		done = TRUE;
-		break;
-	}
-	case MSG_MESSAGE_REJECT:
-		response = amdhandlemsgreject(amd);
-		if (response == FALSE)
-			amd_write8(amd, SCSICMDREG, RESET_ATN_CMD);
-		/* FALLTHROUGH */
-	case MSG_NOOP:
-		done = TRUE;
-		break;
-	case MSG_EXTENDED:
-	{
-		u_int clockrate;
-		u_int period;
-		u_int offset;
-		u_int saved_offset;
-
-		/* Wait for enough of the message to begin validation */
-		if (amd->msgin_index < 1)
-			break;
-		if (amd->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
-			reject = TRUE;
-			break;
-		}
-
-		/* Wait for opcode */
-		if (amd->msgin_index < 2)
-			break;
-
-		if (amd->msgin_buf[2] != MSG_EXT_SDTR) {
-			reject = TRUE;
-			break;
-		}
-
-		/*
-		 * Wait until we have both args before validating
-		 * and acting on this message.
-		 *
-		 * Add one to MSG_EXT_SDTR_LEN to account for
-		 * the extended message preamble.
-		 */
-		if (amd->msgin_index < (MSG_EXT_SDTR_LEN + 1))
-			break;
-
-		period = amd->msgin_buf[3];
-		saved_offset = offset = amd->msgin_buf[4];
-		clockrate = amdfindclockrate(amd, &period);
-		if (offset > AMD_MAX_SYNC_OFFSET)
-			offset = AMD_MAX_SYNC_OFFSET;
-		if (period == 0 || offset == 0) {
-			offset = 0;
-			period = 0;
-			clockrate = 0;
-		}
-		amdsetsync(amd, amd->cur_target, clockrate, period, offset,
-			   AMD_TRANS_ACTIVE|AMD_TRANS_GOAL);
-
-		/*
-		 * See if we initiated Sync Negotiation
-		 * and didn't have to fall down to async
-		 * transfers.
-		 */
-		if (amdsentmsg(amd, MSG_EXT_SDTR, /*full*/TRUE)) {
-			/* We started it */
-			if (saved_offset != offset) {
-				/* Went too low - force async */
-				reject = TRUE;
-			}
-		} else {
-			/*
-			 * Send our own SDTR in reply
-			 */
-			if (bootverbose)
-				printf("Sending SDTR!\n");
-			amd->msgout_index = 0;
-			amd->msgout_len = 0;
-			amdconstructsdtr(amd, period, offset);
-			amd->msgout_index = 0;
-			response = TRUE;
-		}
-		done = TRUE;
-		break;
-	}
-	case MSG_SAVEDATAPOINTER:
-	case MSG_RESTOREPOINTERS:
-		/* XXX Implement!!! */
-		done = TRUE;
-		break;
-	default:
-		reject = TRUE;
-		break;
-	}
-
-	if (reject) {
-		amd->msgout_index = 0;
-		amd->msgout_len = 1;
-		amd->msgout_buf[0] = MSG_MESSAGE_REJECT;
-		done = TRUE;
-		response = TRUE;
-	}
-
-	if (response)
-		amd_write8(amd, SCSICMDREG, SET_ATN_CMD);
-
-	if (done && !response)
-		/* Clear the outgoing message buffer */
-		amd->msgout_len = 0;
-
-	/* Drop Ack */
-	amd_write8(amd, SCSICMDREG, MSG_ACCEPTED_CMD);
-
-	return (done);
-}
-
-static u_int
-amdfindclockrate(struct amd_softc *amd, u_int *period)
-{
-	u_int i;
-	u_int clockrate;
-
-	for (i = 0; i < sizeof(tinfo_sync_period); i++) {
-		u_int8_t *table_entry;
-
-		table_entry = &tinfo_sync_period[i];
-		if (*period <= *table_entry) {
-			/*
-			 * When responding to a target that requests
-			 * sync, the requested rate may fall between
-			 * two rates that we can output, but still be
-			 * a rate that we can receive.  Because of this,
-			 * we want to respond to the target with
-			 * the same rate that it sent to us even
-			 * if the period we use to send data to it
-			 * is lower.  Only lower the response period
-			 * if we must.
-			 */ 
-			if (i == 0) {
-				*period = *table_entry;
-			}
-			break;
-		}
-	}
-
-	if (i == sizeof(tinfo_sync_period)) {
-		/* Too slow for us.  Use asnyc transfers. */
-		*period = 0;
-		clockrate = 0;
-	} else
-		clockrate = i + 4;
-
-	return (clockrate);
-}
-
-/*
- * See if we sent a particular extended message to the target.
- * If "full" is true, the target saw the full message.
- * If "full" is false, the target saw at least the first
- * byte of the message.
- */
-static int
-amdsentmsg(struct amd_softc *amd, u_int msgtype, int full)
-{
-	int found;
-	int index;
-
-	found = FALSE;
-	index = 0;
-
-	while (index < amd->msgout_len) {
-		if ((amd->msgout_buf[index] & MSG_IDENTIFYFLAG) != 0
-		 || amd->msgout_buf[index] == MSG_MESSAGE_REJECT)
-			index++;
-		else if (amd->msgout_buf[index] >= MSG_SIMPLE_Q_TAG
-		      && amd->msgout_buf[index] < MSG_IGN_WIDE_RESIDUE) {
-			/* Skip tag type and tag id */
-			index += 2;
-		} else if (amd->msgout_buf[index] == MSG_EXTENDED) {
-			/* Found a candidate */
-			if (amd->msgout_buf[index+2] == msgtype) {
-				u_int end_index;
-
-				end_index = index + 1
-					  + amd->msgout_buf[index + 1];
-				if (full) {
-					if (amd->msgout_index > end_index)
-						found = TRUE;
-				} else if (amd->msgout_index > index)
-					found = TRUE;
-			}
-			break;
-		} else {
-			panic("amdsentmsg: Inconsistent msg buffer");
-		}
-	}
-	return (found);
-}
-
-static void
-amdconstructsdtr(struct amd_softc *amd, u_int period, u_int offset)
-{
-	amd->msgout_buf[amd->msgout_index++] = MSG_EXTENDED;
-	amd->msgout_buf[amd->msgout_index++] = MSG_EXT_SDTR_LEN;
-	amd->msgout_buf[amd->msgout_index++] = MSG_EXT_SDTR;
-	amd->msgout_buf[amd->msgout_index++] = period;
-	amd->msgout_buf[amd->msgout_index++] = offset;
-	amd->msgout_len += 5;
-}
-
-static int
-amdhandlemsgreject(struct amd_softc *amd)
-{
-	/*
-	 * If we had an outstanding SDTR for this
-	 * target, this is a signal that the target
-	 * is refusing negotiation.  Also watch out
-	 * for rejected tag messages.
-	 */
-	struct	amd_srb *srb;
-	struct	amd_target_info *targ_info;
-	int	response = FALSE;
-
-	srb = amd->active_srb;
-	targ_info = &amd->tinfo[amd->cur_target];
-	if (amdsentmsg(amd, MSG_EXT_SDTR, /*full*/FALSE)) {
-		/* note asynch xfers and clear flag */
-		amdsetsync(amd, amd->cur_target, /*clockrate*/0,
-			   /*period*/0, /*offset*/0,
-			   AMD_TRANS_ACTIVE|AMD_TRANS_GOAL);
-		printf("amd%d:%d: refuses synchronous negotiation. "
-		       "Using asynchronous transfers\n",
-		       amd->unit, amd->cur_target);
-	} else if ((srb != NULL)
-		&& (srb->pccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0) {
-		struct  ccb_trans_settings neg;
-		struct ccb_trans_settings_scsi *scsi = &neg.proto_specific.scsi;
-
-		printf("amd%d:%d: refuses tagged commands.  Performing "
-		       "non-tagged I/O\n", amd->unit, amd->cur_target);
-
-		amdsettags(amd, amd->cur_target, FALSE);
-		memset(&neg, 0, sizeof (neg));
-		scsi->valid = CTS_SCSI_VALID_TQ;
-		xpt_setup_ccb(&neg.ccb_h, srb->pccb->ccb_h.path, /*priority*/1);
-		xpt_async(AC_TRANSFER_NEG, srb->pccb->ccb_h.path, &neg);
-
-		/*
-		 * Resend the identify for this CCB as the target
-		 * may believe that the selection is invalid otherwise.
-		 */
-		if (amd->msgout_len != 0)
-			bcopy(&amd->msgout_buf[0], &amd->msgout_buf[1],
-			      amd->msgout_len);
-		amd->msgout_buf[0] = MSG_IDENTIFYFLAG
-				    | srb->pccb->ccb_h.target_lun;
-		amd->msgout_len++;
-		if ((targ_info->disc_tag & AMD_CUR_DISCENB) != 0
-		  && (srb->pccb->ccb_h.flags & CAM_DIS_DISCONNECT) == 0)
-			amd->msgout_buf[0] |= MSG_IDENTIFY_DISCFLAG;
-
-		srb->pccb->ccb_h.flags &= ~CAM_TAG_ACTION_VALID;
-
-		/*
-		 * Requeue all tagged commands for this target
-		 * currently in our posession so they can be
-		 * converted to untagged commands.
-		 */
-		amdcompletematch(amd, amd->cur_target, amd->cur_lun,
-				 AMD_TAG_WILDCARD, &amd->waiting_srbs,
-				 CAM_DEV_QFRZN|CAM_REQUEUE_REQ);
-	} else {
-		/*
-		 * Otherwise, we ignore it.
-		 */
-		printf("amd%d:%d: Message reject received -- ignored\n",
-		       amd->unit, amd->cur_target);
-	}
-	return (response);
-}
-
-#if 0
-	if (!(pSRB->SRBState & SRB_MSGIN_MULTI)) {
-		if (bval == MSG_DISCONNECT) {
-			pSRB->SRBState = SRB_DISCONNECT;
-		} else if (bval == MSG_SAVEDATAPOINTER) {
-			goto min6;
-		} else if ((bval == MSG_EXTENDED)
-			|| ((bval >= MSG_SIMPLE_Q_TAG)
-			 && (bval <= MSG_ORDERED_Q_TAG))) {
-			pSRB->SRBState |= SRB_MSGIN_MULTI;
-			pSRB->MsgInBuf[0] = bval;
-			pSRB->MsgCnt = 1;
-			pSRB->pMsgPtr = &pSRB->MsgInBuf[1];
-		} else if (bval == MSG_MESSAGE_REJECT) {
-			amd_write8(amd, SCSICMDREG, RESET_ATN_CMD);
-
-			if (pSRB->SRBState & DO_SYNC_NEGO) {
-				goto set_async;
-			}
-		} else if (bval == MSG_RESTOREPOINTERS) {
-			goto min6;
-		} else {
-			goto min6;
-		}
-	} else {		/* minx: */
-		*pSRB->pMsgPtr = bval;
-		pSRB->MsgCnt++;
-		pSRB->pMsgPtr++;
-		if ((pSRB->MsgInBuf[0] >= MSG_SIMPLE_Q_TAG)
-		 && (pSRB->MsgInBuf[0] <= MSG_ORDERED_Q_TAG)) {
-			if (pSRB->MsgCnt == 2) {
-				pSRB->SRBState = 0;
-				pSRB = &amd->SRB_array[pSRB->MsgInBuf[1]];
-				if (pSRB->SRBState & SRB_DISCONNECT) == 0) {
-					pSRB = amd->pTmpSRB;
-					pSRB->SRBState = SRB_UNEXPECT_RESEL;
-					pDCB->pActiveSRB = pSRB;
-					pSRB->MsgOutBuf[0] = MSG_ABORT_TAG;
-					EnableMsgOut2(amd, pSRB);
-				} else {
-					if (pDCB->DCBFlag & ABORT_DEV_) {
-						pSRB->SRBState = SRB_ABORT_SENT;
-						EnableMsgOut1(amd, pSRB);
-					}
-					pDCB->pActiveSRB = pSRB;
-					pSRB->SRBState = SRB_DATA_XFER;
-				}
-			}
-		} else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED)
-			&& (pSRB->MsgCnt == 5)) {
-			pSRB->SRBState &= ~(SRB_MSGIN_MULTI + DO_SYNC_NEGO);
-			if ((pSRB->MsgInBuf[1] != 3)
-			 || (pSRB->MsgInBuf[2] != 1)) {	/* reject_msg: */
-				pSRB->MsgCnt = 1;
-				pSRB->MsgInBuf[0] = MSG_MESSAGE_REJECT;
-				amd_write8(amd, SCSICMDREG, SET_ATN_CMD);
-			} else if (!(pSRB->MsgInBuf[3])
-				|| !(pSRB->MsgInBuf[4])) {
-		set_async:	/* set async */
-
-				pDCB = pSRB->pSRBDCB;
-				/* disable sync & sync nego */
-				pDCB->SyncMode &= ~(SYNC_ENABLE|SYNC_NEGO_DONE);
-				pDCB->SyncPeriod = 0;
-				pDCB->SyncOffset = 0;
-
-				pDCB->tinfo.goal.period = 0;
-				pDCB->tinfo.goal.offset = 0;
-
-				pDCB->tinfo.current.period = 0;
-				pDCB->tinfo.current.offset = 0;
-				pDCB->tinfo.current.width =
-				    MSG_EXT_WDTR_BUS_8_BIT;
-
-				pDCB->CtrlR3 = FAST_CLK; /* non_fast */
-				pDCB->CtrlR4 &= 0x3f;
-				pDCB->CtrlR4 |= EATER_25NS; 
-				goto re_prog;
-			} else {/* set sync */
-
-				pDCB = pSRB->pSRBDCB;
-				/* enable sync & sync nego */
-				pDCB->SyncMode |= SYNC_ENABLE|SYNC_NEGO_DONE;
-
-				/* set sync offset */
-				pDCB->SyncOffset &= 0x0f0;
-				pDCB->SyncOffset |= pSRB->MsgInBuf[4];
-
-				/* set sync period */
-				pDCB->MaxNegoPeriod = pSRB->MsgInBuf[3];
-
-				wval = (u_int16_t) pSRB->MsgInBuf[3];
-				wval = wval << 2;
-				wval--;
-				wval1 = wval / 25;
-				if ((wval1 * 25) != wval) {
-					wval1++;
-				}
-				bval = FAST_CLK|FAST_SCSI;
-				pDCB->CtrlR4 &= 0x3f;
-				if (wval1 >= 8) {
-					/* Fast SCSI */
-					wval1--;
-					bval = FAST_CLK;
-					pDCB->CtrlR4 |= EATER_25NS;
-				}
-				pDCB->CtrlR3 = bval;
-				pDCB->SyncPeriod = (u_int8_t) wval1;
-
-				pDCB->tinfo.goal.period =
-				    tinfo_sync_period[pDCB->SyncPeriod - 4];
-				pDCB->tinfo.goal.offset = pDCB->SyncOffset;
-				pDCB->tinfo.current.period =
-				    tinfo_sync_period[pDCB->SyncPeriod - 4];
-				pDCB->tinfo.current.offset = pDCB->SyncOffset;
-
-				/*
-				 * program SCSI control register
-				 */
-		re_prog:
-				amd_write8(amd, SYNCPERIOREG, pDCB->SyncPeriod);
-				amd_write8(amd, SYNCOFFREG, pDCB->SyncOffset);
-				amd_write8(amd, CNTLREG3, pDCB->CtrlR3);
-				amd_write8(amd, CNTLREG4, pDCB->CtrlR4);
-			}
-		}
-	}
-min6:
-	amd_write8(amd, SCSICMDREG, MSG_ACCEPTED_CMD);
-	return (SCSI_NOP0);
-}
-#endif
-
-static u_int
-amd_DataOutPhase1(struct amd_softc *amd, struct amd_srb *pSRB, u_int scsistat)
-{
-	DataIO_Comm(amd, pSRB, WRITE_DIRECTION);
-	return (scsistat);
-}
-
-static u_int 
-amd_DataInPhase1(struct amd_softc *amd, struct amd_srb *pSRB, u_int scsistat)
-{
-	DataIO_Comm(amd, pSRB, READ_DIRECTION);
-	return (scsistat);
-}
-
-static void
-DataIO_Comm(struct amd_softc *amd, struct amd_srb *pSRB, u_int ioDir)
-{
-	struct amd_sg *    psgl;
-	u_int32_t   lval;
-
-	if (pSRB->SGIndex < pSRB->SGcount) {
-		amd_write8(amd, DMA_Cmd, DMA_IDLE_CMD|ioDir);/* |EN_DMA_INT */
-
-		if (!pSRB->SGToBeXferLen) {
-			psgl = pSRB->pSGlist;
-			pSRB->SGPhysAddr = psgl->SGXPtr;
-			pSRB->SGToBeXferLen = psgl->SGXLen;
-		}
-		lval = pSRB->SGToBeXferLen;
-		amd_write8(amd, CTCREG_LOW, lval);
-		amd_write8(amd, CTCREG_MID, lval >> 8);
-		amd_write8(amd, CURTXTCNTREG, lval >> 16);
-
-		amd_write32(amd, DMA_XferCnt, pSRB->SGToBeXferLen);
-
-		amd_write32(amd, DMA_XferAddr, pSRB->SGPhysAddr);
-
-		pSRB->SRBState = SRB_DATA_XFER;
-
-		amd_write8(amd, SCSICMDREG, DMA_COMMAND|INFO_XFER_CMD);
-
-		amd_write8(amd, DMA_Cmd, DMA_IDLE_CMD|ioDir); /* |EN_DMA_INT */
-
-		amd_write8(amd, DMA_Cmd, DMA_START_CMD|ioDir);/* |EN_DMA_INT */
-	} else {		/* xfer pad */
-		if (pSRB->SGcount) {
-			pSRB->AdaptStatus = H_OVER_UNDER_RUN;
-			pSRB->SRBStatus |= OVER_RUN;
-		}
-		amd_write8(amd, CTCREG_LOW, 0);
-		amd_write8(amd, CTCREG_MID, 0);
-		amd_write8(amd, CURTXTCNTREG, 0);
-
-		pSRB->SRBState |= SRB_XFERPAD;
-		amd_write8(amd, SCSICMDREG, DMA_COMMAND|XFER_PAD_BYTE);
-	}
-}
-
-static u_int
-amd_CommandPhase1(struct amd_softc *amd, struct amd_srb *srb, u_int scsistat)
-{
-	amd_write8(amd, SCSICMDREG, RESET_ATN_CMD);
-	amd_write8(amd, SCSICMDREG, CLEAR_FIFO_CMD);
-
-	amdsetupcommand(amd, srb);
-
-	srb->SRBState = SRB_COMMAND;
-	amd_write8(amd, SCSICMDREG, INFO_XFER_CMD);
-	return (scsistat);
-}
-
-static u_int
-amd_StatusPhase1(struct amd_softc *amd, struct amd_srb *pSRB, u_int scsistat)
-{
-	amd_write8(amd, SCSICMDREG, CLEAR_FIFO_CMD);
-	pSRB->SRBState = SRB_STATUS;
-	amd_write8(amd, SCSICMDREG, INITIATOR_CMD_CMPLTE);
-	return (scsistat);
-}
-
-static u_int
-amd_MsgOutPhase1(struct amd_softc *amd, struct amd_srb *pSRB, u_int scsistat)
-{
-	amd_write8(amd, SCSICMDREG, CLEAR_FIFO_CMD);
-
-	if (amd->msgout_len == 0) {
-		amd->msgout_buf[0] = MSG_NOOP;
-		amd->msgout_len = 1;
-	}
-	amd_write8_multi(amd, SCSIFIFOREG, amd->msgout_buf, amd->msgout_len);
-	amd_write8(amd, SCSICMDREG, INFO_XFER_CMD);
-	return (scsistat);
-}
-
-static u_int
-amd_MsgInPhase1(struct amd_softc *amd, struct amd_srb *pSRB, u_int scsistat)
-{
-	amd_write8(amd, SCSICMDREG, CLEAR_FIFO_CMD);
-	amd_write8(amd, SCSICMDREG, INFO_XFER_CMD);
-	return (scsistat);
-}
-
-static u_int
-amd_NopPhase(struct amd_softc *amd, struct amd_srb *pSRB, u_int scsistat)
-{
-	return (scsistat);
-}
-
-static void
-amd_Disconnect(struct amd_softc * amd)
-{
-	struct	amd_srb *srb;
-	int	target;
-	int	lun;
-
-	srb = amd->active_srb;
-	amd->active_srb = NULL;
-	amd->last_phase = SCSI_BUS_FREE;
-	amd_write8(amd, SCSICMDREG, EN_SEL_RESEL);
-	target = amd->cur_target;
-	lun = amd->cur_lun;
-
-	if (srb == NULL) {
-		/* Invalid reselection */
-		amdrunwaiting(amd);
-	} else if (srb->SRBState & SRB_ABORT_SENT) {
-		/* Clean up and done this srb */
-#if 0
-		while (( = TAILQ_FIRST(&amd->running_srbs)) != NULL) {
-			/* XXX What about "done'ing" these srbs??? */
-			if (pSRB->pSRBDCB == pDCB) {
-				TAILQ_REMOVE(&amd->running_srbs, pSRB, links);
-				TAILQ_INSERT_HEAD(&amd->free_srbs, pSRB, links);
-			}
-		}
-		amdrunwaiting(amd);
-#endif
-	} else {
-		if ((srb->SRBState & (SRB_START | SRB_MSGOUT))
-		 || !(srb->SRBState & (SRB_DISCONNECT | SRB_COMPLETED))) {
-			srb->TargetStatus = AMD_SCSI_STAT_SEL_TIMEOUT;
-			goto disc1;
-		} else if (srb->SRBState & SRB_DISCONNECT) {
-			if (!(srb->pccb->ccb_h.flags & CAM_TAG_ACTION_VALID))
-				amd->untagged_srbs[target][lun] = srb;
-			amdrunwaiting(amd);
-		} else if (srb->SRBState & SRB_COMPLETED) {
-	disc1:
-			srb->SRBState = SRB_FREE;
-			SRBdone(amd, srb);
-		}
-	}
-	return;
-}
-
-static void
-amd_Reselect(struct amd_softc *amd)
-{
-	struct amd_target_info *tinfo;
-	u_int16_t disc_count;
-
-	amd_clear_msg_state(amd);
-	if (amd->active_srb != NULL) {
-		/* Requeue the SRB for our attempted Selection */
-		TAILQ_REMOVE(&amd->running_srbs, amd->active_srb, links);
-		TAILQ_INSERT_HEAD(&amd->waiting_srbs, amd->active_srb, links);
-		amd->active_srb = NULL;
-	}
-	/* get ID */
-	amd->cur_target = amd_read8(amd, SCSIFIFOREG);
-	amd->cur_target ^= amd->HostID_Bit;
-	amd->cur_target = ffs(amd->cur_target) - 1;
-	amd->cur_lun = amd_read8(amd, SCSIFIFOREG) & 7;
-	tinfo = &amd->tinfo[amd->cur_target];
-	amd->active_srb = amd->untagged_srbs[amd->cur_target][amd->cur_lun];
-	disc_count = amd->disc_count[amd->cur_target][amd->cur_lun];
-	if (disc_count == 0) {
-		printf("amd%d: Unexpected reselection for target %d, "
-		       "Issuing Abort\n", amd->unit, amd->cur_target);
-		amd->msgout_buf[0] = MSG_ABORT;
-		amd->msgout_len = 1;
-		amd_write8(amd, SCSICMDREG, SET_ATN_CMD);
-	}
-	if (amd->active_srb != NULL) {
-		amd->disc_count[amd->cur_target][amd->cur_lun]--;
-		amd->untagged_srbs[amd->cur_target][amd->cur_lun] = NULL;
-	}
-	
-	amd_write8(amd, SCSIDESTIDREG, amd->cur_target);
-	amd_write8(amd, SYNCPERIOREG, tinfo->sync_period_reg);
-	amd_write8(amd, SYNCOFFREG, tinfo->sync_offset_reg);
-	amd_write8(amd, CNTLREG1, tinfo->CtrlR1);
-	amd_write8(amd, CNTLREG3, tinfo->CtrlR3);
-	amd_write8(amd, CNTLREG4, tinfo->CtrlR4);
-	amd_write8(amd, SCSICMDREG, MSG_ACCEPTED_CMD);/* drop /ACK */
-	amd->last_phase = SCSI_NOP0;
-}
-
-static void
-SRBdone(struct amd_softc *amd, struct amd_srb *pSRB)
-{
-	u_int8_t   bval, i, status;
-	union ccb *pccb;
-	struct ccb_scsiio *pcsio;
-	int	   intflag;
-	struct amd_sg *ptr2;
-	u_int32_t   swlval;
-
-	pccb = pSRB->pccb;
-	pcsio = &pccb->csio;
-
-	CAM_DEBUG(pccb->ccb_h.path, CAM_DEBUG_TRACE,
-		  ("SRBdone - TagNumber %d\n", pSRB->TagNumber));
-
-	if ((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
-		bus_dmasync_op_t op;
-
-		if ((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
-			op = BUS_DMASYNC_POSTREAD;
-		else
-			op = BUS_DMASYNC_POSTWRITE;
-		bus_dmamap_sync(amd->buffer_dmat, pSRB->dmamap, op);
-		bus_dmamap_unload(amd->buffer_dmat, pSRB->dmamap);
-	}
-
-	status = pSRB->TargetStatus;
-	pccb->ccb_h.status = CAM_REQ_CMP;
-	if (pSRB->SRBFlag & AUTO_REQSENSE) {
-		pSRB->SRBFlag &= ~AUTO_REQSENSE;
-		pSRB->AdaptStatus = 0;
-		pSRB->TargetStatus = SCSI_STATUS_CHECK_COND;
-
-		if (status == SCSI_STATUS_CHECK_COND) {
-			pccb->ccb_h.status = CAM_AUTOSENSE_FAIL;
-			goto ckc_e;
-		}
-		*((u_int32_t *)&(pSRB->CmdBlock[0])) = pSRB->Segment0[0];
-
-		pcsio->sense_resid = pcsio->sense_len
-				   - pSRB->TotalXferredLen;
-		pSRB->TotalXferredLen = pSRB->Segment1[1];
-		if (pSRB->TotalXferredLen) {
-			/* ???? */
-			pcsio->resid = pcsio->dxfer_len
-				     - pSRB->TotalXferredLen;
-			/* The resid field contains valid data	 */
-			/* Flush resid bytes on complete        */
-		} else {
-			pcsio->scsi_status = SCSI_STATUS_CHECK_COND;
-		}
-		bzero(&pcsio->sense_data, pcsio->sense_len);
-		bcopy(amd_get_sense_buf(amd, pSRB), &pcsio->sense_data,
-		      pcsio->sense_len);
-		pccb->ccb_h.status = CAM_AUTOSNS_VALID;
-		goto ckc_e;
-	}
-	if (status) {
-		if (status == SCSI_STATUS_CHECK_COND) {
-
-			if ((pSRB->SGIndex < pSRB->SGcount)
-			 && (pSRB->SGcount) && (pSRB->SGToBeXferLen)) {
-				bval = pSRB->SGcount;
-				swlval = pSRB->SGToBeXferLen;
-				ptr2 = pSRB->pSGlist;
-				ptr2++;
-				for (i = pSRB->SGIndex + 1; i < bval; i++) {
-					swlval += ptr2->SGXLen;
-					ptr2++;
-				}
-				/* ??????? */
-				pcsio->resid = (u_int32_t) swlval;
-
-#ifdef	AMD_DEBUG0
-				printf("XferredLen=%8x,NotYetXferLen=%8x,",
-					pSRB->TotalXferredLen, swlval);
-#endif
-			}
-			if ((pcsio->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) {
-#ifdef	AMD_DEBUG0
-				printf("RequestSense..................\n");
-#endif
-				RequestSense(amd, pSRB);
-				return;
-			}
-			pcsio->scsi_status = SCSI_STATUS_CHECK_COND;
-			pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
-			goto ckc_e;
-		} else if (status == SCSI_STATUS_QUEUE_FULL) {
-			pSRB->AdaptStatus = 0;
-			pSRB->TargetStatus = 0;
-			pcsio->scsi_status = SCSI_STATUS_QUEUE_FULL;
-			pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
-			goto ckc_e;
-		} else if (status == AMD_SCSI_STAT_SEL_TIMEOUT) {
-			pSRB->AdaptStatus = H_SEL_TIMEOUT;
-			pSRB->TargetStatus = 0;
-
-			pcsio->scsi_status = AMD_SCSI_STAT_SEL_TIMEOUT;
-			pccb->ccb_h.status = CAM_SEL_TIMEOUT;
-		} else if (status == SCSI_STATUS_BUSY) {
-#ifdef AMD_DEBUG0
-			printf("DC390: target busy at %s %d\n",
-			       __FILE__, __LINE__);
-#endif
-			pcsio->scsi_status = SCSI_STATUS_BUSY;
-			pccb->ccb_h.status = CAM_SCSI_BUSY;
-		} else if (status == SCSI_STATUS_RESERV_CONFLICT) {
-#ifdef AMD_DEBUG0
-			printf("DC390: target reserved at %s %d\n",
-			       __FILE__, __LINE__);
-#endif
-			pcsio->scsi_status = SCSI_STATUS_RESERV_CONFLICT;
-			pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; /* XXX */
-		} else {
-			pSRB->AdaptStatus = 0;
-#ifdef AMD_DEBUG0
-			printf("DC390: driver stuffup at %s %d\n",
-			       __FILE__, __LINE__);
-#endif
-			pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
-		}
-	} else {
-		status = pSRB->AdaptStatus;
-		if (status & H_OVER_UNDER_RUN) {
-			pSRB->TargetStatus = 0;
-
-			pccb->ccb_h.status = CAM_DATA_RUN_ERR;	
-		} else if (pSRB->SRBStatus & PARITY_ERROR) {
-#ifdef AMD_DEBUG0
-			printf("DC390: driver stuffup %s %d\n",
-			       __FILE__, __LINE__);
-#endif
-			/* Driver failed to perform operation	  */
-			pccb->ccb_h.status = CAM_UNCOR_PARITY;
-		} else {	/* No error */
-			pSRB->AdaptStatus = 0;
-			pSRB->TargetStatus = 0;
-			pcsio->resid = 0;
-			/* there is no error, (sense is invalid)  */
-		}
-	}
-ckc_e:
-	intflag = splcam();
-	if ((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) {
-		/* CAM request not yet complete =>device_Q frozen */
-		xpt_freeze_devq(pccb->ccb_h.path, 1);
-		pccb->ccb_h.status |= CAM_DEV_QFRZN;
-	}
-	TAILQ_REMOVE(&amd->running_srbs, pSRB, links);
-	TAILQ_INSERT_HEAD(&amd->free_srbs, pSRB, links);
-	amdrunwaiting(amd);
-	splx(intflag);
-	xpt_done(pccb);
-
-}
-
-static void
-amd_ResetSCSIBus(struct amd_softc * amd)
-{
-	int     intflag;
-
-	intflag = splcam();
-	amd->ACBFlag |= RESET_DEV;
-	amd_write8(amd, DMA_Cmd, DMA_IDLE_CMD);
-	amd_write8(amd, SCSICMDREG, RST_SCSI_BUS_CMD);
-	splx(intflag);
-	return;
-}
-
-static void
-amd_ScsiRstDetect(struct amd_softc * amd)
-{
-	int     intflag;
-	u_int32_t   wlval;
-
-#ifdef AMD_DEBUG0
-	printf("amd_ScsiRstDetect \n");
-#endif
-
-	wlval = 1000;
-	while (--wlval) {	/* delay 1 sec */
-		DELAY(1000);
-	}
-	intflag = splcam();
-
-	amd_write8(amd, DMA_Cmd, DMA_IDLE_CMD);
-	amd_write8(amd, SCSICMDREG, CLEAR_FIFO_CMD);
-
-	if (amd->ACBFlag & RESET_DEV) {
-		amd->ACBFlag |= RESET_DONE;
-	} else {
-		amd->ACBFlag |= RESET_DETECT;
-		ResetDevParam(amd);
-		amdcompletematch(amd, CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD,
-				 AMD_TAG_WILDCARD, &amd->running_srbs,
-				 CAM_DEV_QFRZN|CAM_SCSI_BUS_RESET);
-		amdcompletematch(amd, CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD,
-				 AMD_TAG_WILDCARD, &amd->waiting_srbs,
-				 CAM_DEV_QFRZN|CAM_SCSI_BUS_RESET);
-		amd->active_srb = NULL;
-		amd->ACBFlag = 0;
-		amdrunwaiting(amd);
-	}
-	splx(intflag);
-	return;
-}
-
-static void
-RequestSense(struct amd_softc *amd, struct amd_srb *pSRB)
-{
-	union ccb *pccb;
-	struct ccb_scsiio *pcsio;
-
-	pccb = pSRB->pccb;
-	pcsio = &pccb->csio;
-
-	pSRB->SRBFlag |= AUTO_REQSENSE;
-	pSRB->Segment0[0] = *((u_int32_t *) & (pSRB->CmdBlock[0]));
-	pSRB->Segment0[1] = *((u_int32_t *) & (pSRB->CmdBlock[4]));
-	pSRB->Segment1[0] = (pSRB->ScsiCmdLen << 8) + pSRB->SGcount;
-	pSRB->Segment1[1] = pSRB->TotalXferredLen;
-
-	pSRB->AdaptStatus = 0;
-	pSRB->TargetStatus = 0;
-
-	pSRB->Segmentx.SGXPtr = amd_get_sense_bufaddr(amd, pSRB);
-	pSRB->Segmentx.SGXLen = amd_get_sense_bufsize(amd, pSRB);
-
-	pSRB->pSGlist = &pSRB->Segmentx;
-	pSRB->SGcount = 1;
-	pSRB->SGIndex = 0;
-
-	pSRB->CmdBlock[0] = REQUEST_SENSE;
-	pSRB->CmdBlock[1] = pSRB->pccb->ccb_h.target_lun << 5;
-	pSRB->CmdBlock[2] = 0;
-	pSRB->CmdBlock[3] = 0;
-	pSRB->CmdBlock[4] = pcsio->sense_len;
-	pSRB->CmdBlock[5] = 0;
-	pSRB->ScsiCmdLen = 6;
-
-	pSRB->TotalXferredLen = 0;
-	pSRB->SGToBeXferLen = 0;
-	if (amdstart(amd, pSRB) != 0) {
-		TAILQ_REMOVE(&amd->running_srbs, pSRB, links);
-		TAILQ_INSERT_HEAD(&amd->waiting_srbs, pSRB, links);
-	}
-}
-
-static void
-amd_InvalidCmd(struct amd_softc * amd)
-{
-	struct amd_srb *srb;
-
-	srb = amd->active_srb;
-	if (srb->SRBState & (SRB_START|SRB_MSGOUT))
-		amd_write8(amd, SCSICMDREG, CLEAR_FIFO_CMD);
-}
-
-void 
-amd_linkSRB(struct amd_softc *amd)
-{
-	u_int16_t  count, i;
-	struct amd_srb *psrb;
-	int error;
-
-	count = amd->SRBCount;
-
-	for (i = 0; i < count; i++) {
-		psrb = (struct amd_srb *)&amd->SRB_array[i];
-		psrb->TagNumber = i;
-
-		/*
-		 * Create the dmamap.  This is no longer optional!
-		 *
-		 * XXX Since there is no detach method in this driver,
-		 * this does not get freed!
-		 */
-		if ((error = bus_dmamap_create(amd->buffer_dmat, 0,
-					       &psrb->dmamap)) != 0) {
-			device_printf(amd->dev, "Error %d creating buffer "
-				      "dmamap!\n", error);
-			return;
-		}
-		TAILQ_INSERT_TAIL(&amd->free_srbs, psrb, links);
-	}
-}
-
-static void
-amd_EnDisableCE(struct amd_softc *amd, int mode, int *regval)
-{
-	if (mode == ENABLE_CE) {
-		*regval = 0xc0;
-	} else {
-		*regval = 0x80;
-	}
-	pci_write_config(amd->dev, *regval, 0, /*bytes*/1);
-	if (mode == DISABLE_CE) {
-		pci_write_config(amd->dev, *regval, 0, /*bytes*/1);
-	}
-	DELAY(160);
-}
-
-static void
-amd_EEpromOutDI(struct amd_softc *amd, int *regval, int Carry)
-{
-	u_int bval;
-
-	bval = 0;
-	if (Carry) {
-		bval = 0x40;
-		*regval = 0x80;
-		pci_write_config(amd->dev, *regval, bval, /*bytes*/1);
-	}
-	DELAY(160);
-	bval |= 0x80;
-	pci_write_config(amd->dev, *regval, bval, /*bytes*/1);
-	DELAY(160);
-	pci_write_config(amd->dev, *regval, 0, /*bytes*/1);
-	DELAY(160);
-}
-
-static int
-amd_EEpromInDO(struct amd_softc *amd)
-{
-	pci_write_config(amd->dev, 0x80, 0x80, /*bytes*/1);
-	DELAY(160);
-	pci_write_config(amd->dev, 0x80, 0x40, /*bytes*/1);
-	DELAY(160);
-	if (pci_read_config(amd->dev, 0, /*bytes*/1) == 0x22)
-		return (1);
-	return (0);
-}
-
-static u_int16_t
-EEpromGetData1(struct amd_softc *amd)
-{
-	u_int	  i;
-	u_int	  carryFlag;
-	u_int16_t wval;
-
-	wval = 0;
-	for (i = 0; i < 16; i++) {
-		wval <<= 1;
-		carryFlag = amd_EEpromInDO(amd);
-		wval |= carryFlag;
-	}
-	return (wval);
-}
-
-static void
-amd_Prepare(struct amd_softc *amd, int *regval, u_int8_t EEpromCmd)
-{
-	u_int i, j;
-	int carryFlag;
-
-	carryFlag = 1;
-	j = 0x80;
-	for (i = 0; i < 9; i++) {
-		amd_EEpromOutDI(amd, regval, carryFlag);
-		carryFlag = (EEpromCmd & j) ? 1 : 0;
-		j >>= 1;
-	}
-}
-
-static void
-amd_ReadEEprom(struct amd_softc *amd)
-{
-	int	   regval;
-	u_int	   i;
-	u_int16_t *ptr;
-	u_int8_t   cmd;
-
-	ptr = (u_int16_t *)&amd->eepromBuf[0];
-	cmd = EEPROM_READ;
-	for (i = 0; i < 0x40; i++) {
-		amd_EnDisableCE(amd, ENABLE_CE, &regval);
-		amd_Prepare(amd, &regval, cmd);
-		*ptr = EEpromGetData1(amd);
-		ptr++;
-		cmd++;
-		amd_EnDisableCE(amd, DISABLE_CE, &regval);
-	}
-}
-
-static void
-amd_load_defaults(struct amd_softc *amd)
-{
-	int target;
-
-	bzero(&amd->eepromBuf, sizeof amd->eepromBuf);
-	for (target = 0; target < MAX_SCSI_ID; target++)
-		amd->eepromBuf[target << 2] =
-		    (TAG_QUEUING|EN_DISCONNECT|SYNC_NEGO|PARITY_CHK);
-	amd->eepromBuf[EE_ADAPT_SCSI_ID] = 7;
-	amd->eepromBuf[EE_MODE2] = ACTIVE_NEGATION|LUN_CHECK|GREATER_1G;
-	amd->eepromBuf[EE_TAG_CMD_NUM] = 4;
-}
-
-static void
-amd_load_eeprom_or_defaults(struct amd_softc *amd)
-{
-	u_int16_t  wval, *ptr;
-	u_int8_t   i;
-
-	amd_ReadEEprom(amd);
-	wval = 0;
-	ptr = (u_int16_t *) & amd->eepromBuf[0];
-	for (i = 0; i < EE_DATA_SIZE; i += 2, ptr++)
-		wval += *ptr;
-
-	if (wval != EE_CHECKSUM) {
-		if (bootverbose)
-			printf("amd%d: SEEPROM data unavailable.  "
-			       "Using default device parameters.\n",
-			       amd->unit);
-		amd_load_defaults(amd);
-	}
-}
-
-/*
- **********************************************************************
- * Function      : static int amd_init (struct Scsi_Host *host)
- * Purpose       : initialize the internal structures for a given SCSI host
- * Inputs        : host - pointer to this host adapter's structure/
- **********************************************************************
- */
-static int
-amd_init(device_t dev)
-{
-	struct amd_softc *amd = device_get_softc(dev);
-	struct resource	*iores;
-	int	i, rid;
-	u_int	bval;
-
-	rid = PCI_BASE_ADDR0;
-	iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, RF_ACTIVE);
-	if (iores == NULL) {
-		if (bootverbose)
-			printf("amd_init: bus_alloc_resource failure!\n");
-		return ENXIO;
-	}
-	amd->tag = rman_get_bustag(iores);
-	amd->bsh = rman_get_bushandle(iores);
-
-	/* DMA tag for mapping buffers into device visible space. */
-	if (bus_dma_tag_create(/*parent_dmat*/NULL, /*alignment*/1,
-			       /*boundary*/0,
-			       /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
-			       /*highaddr*/BUS_SPACE_MAXADDR,
-			       /*filter*/NULL, /*filterarg*/NULL,
-			       /*maxsize*/MAXBSIZE, /*nsegments*/AMD_NSEG,
-			       /*maxsegsz*/AMD_MAXTRANSFER_SIZE,
-			       /*flags*/BUS_DMA_ALLOCNOW,
-			       /*lockfunc*/busdma_lock_mutex,
-			       /*lockarg*/&Giant,
-			       &amd->buffer_dmat) != 0) {
-		if (bootverbose)
-			printf("amd_init: bus_dma_tag_create failure!\n");
-		return ENXIO;
-        }
-
-	/* Create, allocate, and map DMA buffers for autosense data */
-	if (bus_dma_tag_create(/*parent_dmat*/NULL, /*alignment*/1,
-			       /*boundary*/0,
-			       /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
-			       /*highaddr*/BUS_SPACE_MAXADDR,
-			       /*filter*/NULL, /*filterarg*/NULL,
-			       sizeof(struct scsi_sense_data) * MAX_SRB_CNT,
-			       /*nsegments*/1,
-			       /*maxsegsz*/AMD_MAXTRANSFER_SIZE,
-			       /*flags*/0,
-			       /*lockfunc*/busdma_lock_mutex,
-			       /*lockarg*/&Giant, &amd->sense_dmat) != 0) {
-		if (bootverbose)
-			device_printf(dev, "cannot create sense buffer dmat\n");
-		return (ENXIO);
-	}
-
-	if (bus_dmamem_alloc(amd->sense_dmat, (void **)&amd->sense_buffers,
-			     BUS_DMA_NOWAIT, &amd->sense_dmamap) != 0)
-		return (ENOMEM);
-
-	bus_dmamap_load(amd->sense_dmat, amd->sense_dmamap,
-		       amd->sense_buffers,
-		       sizeof(struct scsi_sense_data) * MAX_SRB_CNT,
-		       amd_dmamap_cb, &amd->sense_busaddr, /*flags*/0);
-
-	TAILQ_INIT(&amd->free_srbs);
-	TAILQ_INIT(&amd->running_srbs);
-	TAILQ_INIT(&amd->waiting_srbs);
-	amd->last_phase = SCSI_BUS_FREE;
-	amd->dev = dev;
-	amd->unit = device_get_unit(dev);
-	amd->SRBCount = MAX_SRB_CNT;
-	amd->status = 0;
-	amd_load_eeprom_or_defaults(amd);
-	amd->max_id = 7;
-	if (amd->eepromBuf[EE_MODE2] & LUN_CHECK) {
-		amd->max_lun = 7;
-	} else {
-		amd->max_lun = 0;
-	}
-	amd->AdaptSCSIID = amd->eepromBuf[EE_ADAPT_SCSI_ID];
-	amd->HostID_Bit = (1 << amd->AdaptSCSIID);
-	amd->AdaptSCSILUN = 0;
-	/* (eepromBuf[EE_TAG_CMD_NUM]) << 2; */
-	amd->ACBFlag = 0;
-	amd->Gmode2 = amd->eepromBuf[EE_MODE2];
-	amd_linkSRB(amd);
-	for (i = 0; i <= amd->max_id; i++) {
-
-		if (amd->AdaptSCSIID != i) {
-			struct amd_target_info *tinfo;
-			PEEprom prom;
-
-			tinfo = &amd->tinfo[i];
-			prom = (PEEprom)&amd->eepromBuf[i << 2];
-			if ((prom->EE_MODE1 & EN_DISCONNECT) != 0) {
-				tinfo->disc_tag |= AMD_USR_DISCENB;
-				if ((prom->EE_MODE1 & TAG_QUEUING) != 0)
-					tinfo->disc_tag |= AMD_USR_TAGENB;
-			}
-			if ((prom->EE_MODE1 & SYNC_NEGO) != 0) {
-				tinfo->user.period =
-				    eeprom_period[prom->EE_SPEED];
-				tinfo->user.offset = AMD_MAX_SYNC_OFFSET;
-			}
-			tinfo->CtrlR1 = amd->AdaptSCSIID;
-			if ((prom->EE_MODE1 & PARITY_CHK) != 0)
-				tinfo->CtrlR1 |= PARITY_ERR_REPO;
-			tinfo->CtrlR3 = FAST_CLK;
-			tinfo->CtrlR4 = EATER_25NS;
-			if ((amd->eepromBuf[EE_MODE2] & ACTIVE_NEGATION) != 0)
-				tinfo->CtrlR4 |= NEGATE_REQACKDATA;
-		}
-	}
-	amd_write8(amd, SCSITIMEOUTREG, 153); /* 250ms selection timeout */
-	/* Conversion factor = 0 , 40MHz clock */
-	amd_write8(amd, CLKFACTREG, CLK_FREQ_40MHZ);
-	/* NOP cmd - clear command register */
-	amd_write8(amd, SCSICMDREG, NOP_CMD);	
-	amd_write8(amd, CNTLREG2, EN_FEATURE|EN_SCSI2_CMD);
-	amd_write8(amd, CNTLREG3, FAST_CLK);
-	bval = EATER_25NS;
-	if (amd->eepromBuf[EE_MODE2] & ACTIVE_NEGATION) {
-		bval |= NEGATE_REQACKDATA;
-	}
-	amd_write8(amd, CNTLREG4, bval);
-
-	/* Disable SCSI bus reset interrupt */
-	amd_write8(amd, CNTLREG1, DIS_INT_ON_SCSI_RST);
-
-	return 0;
-}
-
-/*
- * attach and init a host adapter
- */
-static int
-amd_attach(device_t dev)
-{
-	struct cam_devq	*devq;	/* Device Queue to use for this SIM */
-	u_int8_t	intstat;
-	struct amd_softc *amd = device_get_softc(dev);
-	int		unit = device_get_unit(dev);
-	int		rid;
-	void		*ih;
-	struct resource	*irqres;
-
-	if (amd_init(dev)) {
-		if (bootverbose)
-			printf("amd_attach: amd_init failure!\n");
-		return ENXIO;
-	}
-
-	/* Reset Pending INT */
-	intstat = amd_read8(amd, INTSTATREG);
-
-	/* After setting up the adapter, map our interrupt */
-	rid = 0;
-	irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
-					RF_SHAREABLE | RF_ACTIVE);
-	if (irqres == NULL ||
-	    bus_setup_intr(dev, irqres, INTR_TYPE_CAM | INTR_ENTROPY,
-	    NULL, amd_intr, amd, &ih)) {
-		if (bootverbose)
-			printf("amd%d: unable to register interrupt handler!\n",
-			       unit);
-		return ENXIO;
-	}
-
-	/*
-	 * Now let the CAM generic SCSI layer find the SCSI devices on
-	 * the bus *  start queue to reset to the idle loop. *
-	 * Create device queue of SIM(s) *  (MAX_START_JOB - 1) :
-	 * max_sim_transactions
-	 */
-	devq = cam_simq_alloc(MAX_START_JOB);
-	if (devq == NULL) {
-		if (bootverbose)
-			printf("amd_attach: cam_simq_alloc failure!\n");
-		return ENXIO;
-	}
-
-	amd->psim = cam_sim_alloc(amd_action, amd_poll, "amd",
-				  amd, amd->unit, &Giant,
-				  1, MAX_TAGS_CMD_QUEUE, devq);
-	if (amd->psim == NULL) {
-		cam_simq_free(devq);
-		if (bootverbose)
-			printf("amd_attach: cam_sim_alloc failure!\n");
-		return ENXIO;
-	}
-
-	if (xpt_bus_register(amd->psim, dev, 0) != CAM_SUCCESS) {
-		cam_sim_free(amd->psim, /*free_devq*/TRUE);
-		if (bootverbose)
-			printf("amd_attach: xpt_bus_register failure!\n");
-		return ENXIO;
-	}
-
-	if (xpt_create_path(&amd->ppath, /* periph */ NULL,
-			    cam_sim_path(amd->psim), CAM_TARGET_WILDCARD,
-			    CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
-		xpt_bus_deregister(cam_sim_path(amd->psim));
-		cam_sim_free(amd->psim, /* free_simq */ TRUE);
-		if (bootverbose)
-			printf("amd_attach: xpt_create_path failure!\n");
-		return ENXIO;
-	}
-
-	return 0;
-}
-
-static int
-amd_probe(device_t dev)
-{
-	if (pci_get_devid(dev) == PCI_DEVICE_ID_AMD53C974) {
-		device_set_desc(dev,
-			"Tekram DC390(T)/AMD53c974 SCSI Host Adapter");
-		return BUS_PROBE_DEFAULT;
-	}
-	return ENXIO;
-}
-
-static device_method_t amd_methods[] = {
-	/* Device interface */
-	DEVMETHOD(device_probe,		amd_probe),
-	DEVMETHOD(device_attach,	amd_attach),
-	{ 0, 0 }
-};
-
-static driver_t amd_driver = {
-	"amd", amd_methods, sizeof(struct amd_softc)
-};
-
-static devclass_t amd_devclass;
-DRIVER_MODULE(amd, pci, amd_driver, amd_devclass, 0, 0);
-MODULE_DEPEND(amd, pci, 1, 1, 1);
-MODULE_DEPEND(amd, cam, 1, 1, 1);
diff --git a/sys/dev/amd/amd.h b/sys/dev/amd/amd.h
deleted file mode 100644
index c671f22..0000000
--- a/sys/dev/amd/amd.h
+++ /dev/null
@@ -1,585 +0,0 @@
-/*-
- *********************************************************************
- *	FILE NAME  : amd.h
- *	     BY    : C.L. Huang 	(ching@tekram.com.tw)
- *		     Erich Chen     (erich@tekram.com.tw)
- *	Description: Device Driver for the amd53c974 PCI Bus Master
- *		     SCSI Host adapter found on cards such as
- *		     the Tekram DC-390(T).
- * (C)Copyright 1995-1999 Tekram Technology Co., Ltd.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *********************************************************************
- * $FreeBSD$
- */
-
-#ifndef AMD_H
-#define AMD_H
-
-#define AMD_TRANS_CUR		0x01	/* Modify current neogtiation status */
-#define AMD_TRANS_ACTIVE	0x03	/* Assume this is the active target */
-#define AMD_TRANS_GOAL		0x04	/* Modify negotiation goal */
-#define AMD_TRANS_USER		0x08	/* Modify user negotiation settings */
-
-/*
- * Per target transfer parameters.
- */
-struct amd_transinfo {
-	u_int8_t period;
-	u_int8_t offset;
-};
-
-struct amd_target_info {
-	/*
-	 * Records the currently active and user/default settings for
-	 * tagged queueing and disconnection for each target.
-	 */
-	u_int8_t disc_tag;
-#define		AMD_CUR_DISCENB	0x01
-#define		AMD_CUR_TAGENB	0x02
-#define		AMD_USR_DISCENB	0x04
-#define		AMD_USR_TAGENB	0x08
-	u_int8_t   CtrlR1;
-	u_int8_t   CtrlR3;
-	u_int8_t   CtrlR4;
-	u_int8_t   sync_period_reg;
-	u_int8_t   sync_offset_reg;
-
-	/*
-	 * Currently active transfer settings.
-	 */
-	struct amd_transinfo current;
-	/*
-	 * Transfer settings we wish to achieve
-	 * through negotiation.
-	 */
-	struct amd_transinfo goal;
-	/*
-	 * User defined or default transfer settings.
-	 */
-	struct amd_transinfo user;
-};
-
-/*
- * Scatter/Gather Segment entry.
- */
-struct amd_sg {
-	u_int32_t   SGXLen;
-	u_int32_t   SGXPtr;
-};
-
-/*
- * Chipset feature limits
- */
-#define MAX_SCSI_ID		8
-#define AMD_MAX_SYNC_OFFSET	15
-#define AMD_TARGET_MAX	7
-#define AMD_LUN_MAX		7
-#define AMD_MAXPHYS		(128 * 1024) /* legacy MAXPHYS */
-#define AMD_NSEG		(btoc(AMD_MAXPHYS) + 1)
-#define AMD_MAXTRANSFER_SIZE	0xFFFFFF /* restricted by 24 bit counter */
-#define MAX_DEVICES		10
-#define MAX_TAGS_CMD_QUEUE	256
-#define MAX_CMD_PER_LUN		6
-#define MAX_SRB_CNT		256
-#define MAX_START_JOB		256
-
-/*
- * BIT position to integer mapping.
- */
-#define BIT(N) (0x01 << N)
-
-/*
- * EEPROM storage offsets and data structures.
- */
-typedef struct _EEprom {
-	u_int8_t   EE_MODE1;
-	u_int8_t   EE_SPEED;
-	u_int8_t   xx1;
-	u_int8_t   xx2;
-}       EEprom, *PEEprom;
-
-#define EE_ADAPT_SCSI_ID	64
-#define EE_MODE2		65
-#define EE_DELAY		66
-#define EE_TAG_CMD_NUM		67
-#define EE_DATA_SIZE		128
-#define EE_CHECKSUM		0x1234
-
-/*
- * EE_MODE1 bits definition
- */
-#define PARITY_CHK   	  	BIT(0)
-#define SYNC_NEGO      		BIT(1)
-#define EN_DISCONNECT  		BIT(2)
-#define SEND_START     		BIT(3)
-#define TAG_QUEUING    		BIT(4)
-
-/*
- * EE_MODE2 bits definition
- */
-#define MORE2_DRV		BIT(0)
-#define GREATER_1G		BIT(1)
-#define RST_SCSI_BUS		BIT(2)
-#define ACTIVE_NEGATION		BIT(3)
-#define NO_SEEK			BIT(4)
-#define LUN_CHECK		BIT(5)
-
-#define ENABLE_CE		1
-#define DISABLE_CE		0
-#define EEPROM_READ		0x80
-
-#define AMD_TAG_WILDCARD ((u_int)(~0))
-
-/*
- * SCSI Request Block
- */
-struct amd_srb {
-	TAILQ_ENTRY(amd_srb) links;
-	u_int8_t	 CmdBlock[12];
-	union		 ccb *pccb;
-	bus_dmamap_t	 dmamap;
-	struct		 amd_sg *pSGlist;
-
-	u_int32_t	 TotalXferredLen;
-	u_int32_t	 SGPhysAddr;	/* a segment starting address */
-	u_int32_t	 SGToBeXferLen;	/* to be xfer length */
-	u_int32_t	 Segment0[2];
-	u_int32_t	 Segment1[2];
-
-	struct		 amd_sg SGsegment[AMD_NSEG];
-	struct		 amd_sg Segmentx;/* a one entry of S/G list table */
-	u_int8_t	*pMsgPtr;
-	u_int16_t	 SRBState;
-
-	u_int8_t	 AdaptStatus;
-	u_int8_t	 TargetStatus;
-	u_int8_t	 MsgCnt;
-	u_int8_t	 EndMessage;
-	u_int8_t	 TagNumber;
-	u_int8_t	 SGcount;
-	u_int8_t	 SGIndex;
-	u_int8_t	 IORBFlag;	/* ;81h-Reset, 2-retry */
-
-	u_int8_t	 SRBStatus;
-	u_int8_t	 SRBFlag;
-	/* ; b0-AutoReqSense,b6-Read,b7-write */
-	/* ; b4-settimeout,b5-Residual valid */
-	u_int8_t	 ScsiCmdLen;
-};
-
-TAILQ_HEAD(srb_queue, amd_srb);
-
-/*
- * Per-adapter, software configuration.
- */
-struct amd_softc {
-	device_t		dev;
-	bus_space_tag_t		tag;
-	bus_space_handle_t	bsh;
-	bus_dma_tag_t		buffer_dmat;   /* dmat for buffer I/O */  
-	bus_dma_tag_t		sense_dmat;   /* dmat for sense buffer */  
-	bus_dmamap_t		sense_dmamap;
-	struct scsi_sense_data	*sense_buffers;
-	bus_addr_t		sense_busaddr;
-	int			unit;
-
-	int	   last_phase;
-	int	   cur_target;
-	int	   cur_lun;
-	struct	   amd_srb *active_srb;
-	struct	   amd_srb *untagged_srbs[AMD_TARGET_MAX+1][AMD_LUN_MAX+1];
-	struct	   amd_target_info tinfo[AMD_TARGET_MAX+1];
-	u_int16_t  disc_count[AMD_TARGET_MAX+1][AMD_LUN_MAX+1];
-
-	struct	   srb_queue free_srbs;
-	struct	   srb_queue waiting_srbs;
-	struct	   srb_queue running_srbs;
-
-	struct	   amd_srb *pTmpSRB;
-
-	u_int16_t  SRBCount;
-
-	u_int16_t  max_id;
-	u_int16_t  max_lun;
-
-	/* Hooks into the CAM XPT */
-	struct	   cam_sim *psim;
-	struct	   cam_path *ppath;
-
-	u_int8_t   msgin_buf[6];
-	u_int8_t   msgout_buf[6];
-	u_int	   msgin_index;
-	u_int	   msgout_index;
-	u_int	   msgout_len;
-
-	u_int8_t   status;
-	u_int8_t   AdaptSCSIID;		/* ; Adapter SCSI Target ID */
-	u_int8_t   AdaptSCSILUN;	/* ; Adapter SCSI LUN */
-
-	u_int8_t   ACBFlag;
-
-	u_int8_t   Gmode2;
-
-	u_int8_t   HostID_Bit;
-
-	u_int8_t   InitDCB_flag[8][8];	/* flag of initDCB for device */
-	struct	   amd_srb SRB_array[MAX_SRB_CNT]; /* +45Ch, Len=	 */
-	struct	   amd_srb TmpSRB;
-	/* Setup data stored in an 93c46 serial eeprom */
-	u_int8_t   eepromBuf[EE_DATA_SIZE];
-};
-
-/*
- *   ----SRB State machine definition
- */
-#define SRB_FREE        	0
-#define SRB_READY       	BIT(1)
-#define SRB_MSGOUT      	BIT(2)	/* ;arbitration+msg_out 1st byte */
-#define SRB_MSGIN       	BIT(3)
-#define SRB_MSGIN_MULTI		BIT(4)
-#define SRB_COMMAND     	BIT(5)
-#define SRB_START	     	BIT(6)	/* ;arbitration+msg_out+command_out */
-#define SRB_DISCONNECT   	BIT(7)
-#define SRB_DATA_XFER    	BIT(8)
-#define SRB_XFERPAD     	BIT(9)
-#define SRB_STATUS      	BIT(10)
-#define SRB_COMPLETED    	BIT(11)
-#define SRB_ABORT_SENT   	BIT(12)
-#define DO_SYNC_NEGO    	BIT(13)
-#define SRB_UNEXPECT_RESEL	BIT(14)
-
-/*
- *   ---ACB Flag
- */
-#define RESET_DEV       	BIT(0)
-#define RESET_DETECT    	BIT(1)
-#define RESET_DONE      	BIT(2)
-
-/*
- *   ---DCB Flag
- */
-#define ABORT_DEV_      	BIT(0)
-
-/*
- *   ---SRB status
- */
-#define SRB_OK	        	BIT(0)
-#define ABORTION        	BIT(1)
-#define OVER_RUN        	BIT(2)
-#define UNDER_RUN       	BIT(3)
-#define PARITY_ERROR    	BIT(4)
-#define SRB_ERROR       	BIT(5)
-
-/*
- *   ---SRB Flags
- */
-#define DATAOUT         	BIT(7)
-#define DATAIN	        	BIT(6)
-#define RESIDUAL_VALID   	BIT(5)
-#define ENABLE_TIMER    	BIT(4)
-#define RESET_DEV0      	BIT(2)
-#define ABORT_DEV       	BIT(1)
-#define AUTO_REQSENSE    	BIT(0)
-
-/*
- *   ---Adapter status
- */
-#define H_STATUS_GOOD		0
-#define H_SEL_TIMEOUT		0x11
-#define H_OVER_UNDER_RUN	0x12
-#define H_UNEXP_BUS_FREE	0x13
-#define H_TARGET_PHASE_F	0x14
-#define H_INVALID_CCB_OP	0x16
-#define H_LINK_CCB_BAD		0x17
-#define H_BAD_TARGET_DIR	0x18
-#define H_DUPLICATE_CCB		0x19
-#define H_BAD_CCB_OR_SG		0x1A
-#define H_ABORT			0x0FF
-
-/*
- * AMD specific "status" codes returned in the SCSI status byte.
- */
-#define AMD_SCSI_STAT_UNEXP_BUS_F    	0xFD	/* ;  Unexpect Bus Free */
-#define AMD_SCSI_STAT_BUS_RST_DETECT	0xFE	/* ;  Scsi Bus Reset detected */
-#define AMD_SCSI_STAT_SEL_TIMEOUT   	0xFF	/* ;  Selection Time out */
-
-/*
- *   ---Sync_Mode
- */
-#define SYNC_DISABLE	    0
-#define SYNC_ENABLE 	    BIT(0)
-#define SYNC_NEGO_DONE	    BIT(1)
-#define WIDE_ENABLE 	    BIT(2)
-#define WIDE_NEGO_DONE	    BIT(3)
-#define EN_TAG_QUEUING	    BIT(4)
-#define EN_ATN_STOP         BIT(5)
-
-#define SYNC_NEGO_OFFSET    15
-
-/*
- *    ---SCSI bus phase
- */
-#define SCSI_DATA_OUT		0
-#define SCSI_DATA_IN		1
-#define SCSI_COMMAND		2
-#define SCSI_STATUS		3
-#define SCSI_NOP0		4
-#define SCSI_ARBITRATING	5
-#define SCSI_MSG_OUT		6
-#define SCSI_MSG_IN		7
-#define SCSI_BUS_FREE		8
-
-/*
- *==========================================================
- *      	AMD 53C974 Registers bit Definition
- *==========================================================
- */
-
-/*
- *      ------SCSI Register-------
- *      Command Reg.(+0CH)
- */
-#define DMA_COMMAND   	    	BIT(7)
-#define NOP_CMD 	       	0
-#define CLEAR_FIFO_CMD	    	1
-#define RST_DEVICE_CMD	    	2
-#define RST_SCSI_BUS_CMD    	3
-#define INFO_XFER_CMD	    	0x10
-#define INITIATOR_CMD_CMPLTE	0x11
-#define MSG_ACCEPTED_CMD    	0x12
-#define XFER_PAD_BYTE	     	0x18
-#define SET_ATN_CMD	       	0x1A
-#define RESET_ATN_CMD    	0x1B
-#define SEL_W_ATN		0x42
-#define SEL_W_ATN_STOP	    	0x43
-#define EN_SEL_RESEL	    	0x44
-#define SEL_W_ATN2	       	0x46
-#define DATA_XFER_CMD	    	INFO_XFER_CMD
-
-
-/*
- *     ------SCSI Register-------
- *     SCSI Status Reg.(+10H)
- */
-#define INTERRUPT	    	BIT(7)
-#define ILLEGAL_OP_ERR		BIT(6)
-#define PARITY_ERR	    	BIT(5)
-#define COUNT_2_ZERO		BIT(4)
-#define GROUP_CODE_VALID	BIT(3)
-#define SCSI_PHASE_MASK 	(BIT(2)+BIT(1)+BIT(0))
-
-/*
- *     ------SCSI Register-------
- *     Interrupt Status Reg.(+14H)
- */
-#define SCSI_RESET_	    	BIT(7)
-#define INVALID_CMD	    	BIT(6)
-#define DISCONNECTED		BIT(5)
-#define SERVICE_REQUEST 	BIT(4)
-#define SUCCESSFUL_OP		BIT(3)
-#define RESELECTED	    	BIT(2)
-#define SEL_ATTENTION		BIT(1)
-#define SELECTED	    	BIT(0)
-
-/*
- *     ------SCSI Register-------
- *    Internal State Reg.(+18H)
- */
-#define SYNC_OFFSET_FLAG	BIT(3)
-#define INTRN_STATE_MASK	(BIT(2)+BIT(1)+BIT(0))
-
-/*
- *     ------SCSI Register-------
- *     Clock Factor Reg.(+24H)
- */
-#define CLK_FREQ_40MHZ		0
-#define CLK_FREQ_35MHZ		(BIT(2)+BIT(1)+BIT(0))
-#define CLK_FREQ_30MHZ		(BIT(2)+BIT(1))
-#define CLK_FREQ_25MHZ		(BIT(2)+BIT(0))
-#define CLK_FREQ_20MHZ		BIT(2)
-#define CLK_FREQ_15MHZ		(BIT(1)+BIT(0))
-#define CLK_FREQ_10MHZ		BIT(1)
-
-/*
- *     ------SCSI Register-------
- *     Control Reg. 1(+20H)
- */
-#define EXTENDED_TIMING 	BIT(7)
-#define DIS_INT_ON_SCSI_RST	BIT(6)
-#define PARITY_ERR_REPO 	BIT(4)
-#define SCSI_ID_ON_BUS		(BIT(2)+BIT(1)+BIT(0))
-
-/*
- *     ------SCSI Register-------
- *     Control Reg. 2(+2CH)
- */
-#define EN_FEATURE	    	BIT(6)
-#define EN_SCSI2_CMD		BIT(3)
-
-/*
- *     ------SCSI Register-------
- *     Control Reg. 3(+30H)
- */
-#define ID_MSG_CHECK		BIT(7)
-#define EN_QTAG_MSG	    	BIT(6)
-#define EN_GRP2_CMD	    	BIT(5)
-#define FAST_SCSI	    	BIT(4)	/* ;10MB/SEC */
-#define FAST_CLK	    	BIT(3)	/* ;25 - 40 MHZ */
-
-/*
- *     ------SCSI Register-------
- *     Control Reg. 4(+34H)
- */
-#define EATER_12NS	    	0
-#define EATER_25NS	    	BIT(7)
-#define EATER_35NS	    	BIT(6)
-#define EATER_0NS	    	(BIT(7)+BIT(6))
-#define NEGATE_REQACKDATA	BIT(2)
-#define NEGATE_REQACK		BIT(3)
-
-/*
- *========================================
- *             DMA Register
- *========================================
- */
-
-/*
- *        -------DMA Register--------
- *        DMA Command Reg.(+40H)
- */
-#define READ_DIRECTION		BIT(7)
-#define WRITE_DIRECTION 	0
-#define EN_DMA_INT	    	BIT(6)
-#define MAP_TO_MDL	    	BIT(5)
-#define DMA_DIAGNOSTIC		BIT(4)
-#define DMA_IDLE_CMD		0
-#define DMA_BLAST_CMD		BIT(0)
-#define DMA_ABORT_CMD		BIT(1)
-#define DMA_START_CMD		(BIT(1)|BIT(0))
-
-/*
- *        -------DMA Register--------
- *         DMA Status Reg.(+54H)
- */
-#define PCI_MS_ABORT		BIT(6)
-#define BLAST_COMPLETE		BIT(5)
-#define SCSI_INTERRUPT		BIT(4)
-#define DMA_XFER_DONE		BIT(3)
-#define DMA_XFER_ABORT		BIT(2)
-#define DMA_XFER_ERROR		BIT(1)
-#define POWER_DOWN	    	BIT(0)
-
-/*
- *        -------DMA Register--------
- *        DMA SCSI Bus and Ctrl.(+70H)
- *        EN_INT_ON_PCI_ABORT
- */
-
-/*
- *==========================================================
- *           SCSI Chip register address offset
- *==========================================================
- */
-#define CTCREG_LOW   	0x00	/* (R)   current transfer count register low */
-#define STCREG_LOW   	0x00	/* (W)   start transfer count register low */
-
-#define CTCREG_MID   	0x04	/* (R)   current transfer count register
-				 * middle */
-#define STCREG_MID   	0x04	/* (W)   start transfer count register middle */
-
-#define SCSIFIFOREG    	0x08	/* (R/W) SCSI FIFO register */
-
-#define SCSICMDREG     	0x0C	/* (R/W) SCSI command register */
-
-#define SCSISTATREG  	0x10	/* (R)   SCSI status register */
-#define SCSIDESTIDREG  	0x10	/* (W)   SCSI destination ID register */
-
-#define INTSTATREG   	0x14	/* (R)   interrupt status register */
-#define SCSITIMEOUTREG 	0x14	/* (W)   SCSI timeout register */
-
-
-#define INTERNSTATREG  	0x18	/* (R)   internal state register */
-#define SYNCPERIOREG  	0x18	/* (W)   synchronous transfer period register */
-
-#define CURRENTFIFOREG  0x1C	/* (R)   current FIFO/internal state register */
-#define SYNCOFFREG 	    0x1C/* (W)   synchronous transfer period register */
-
-#define CNTLREG1    	0x20	/* (R/W) control register 1 */
-#define CLKFACTREG  	0x24	/* (W)   clock factor register */
-#define CNTLREG2    	0x2C	/* (R/W) control register 2 */
-#define CNTLREG3    	0x30	/* (R/W) control register 3 */
-#define CNTLREG4    	0x34	/* (R/W) control register 4 */
-
-#define CURTXTCNTREG  	0x38	/* (R)   current transfer count register
-				 * high/part-unique ID code */
-#define STCREG_HIGH  	0x38	/* (W)   Start current transfer count register
-				 * high */
-
-/*
- *********************************************************
- *
- *                 SCSI DMA register
- *
- *********************************************************
- */
-#define DMA_Cmd     	0x40	/* (R/W) command register */
-#define DMA_XferCnt  	0x44	/* (R/W) starting transfer count */
-#define DMA_XferAddr	0x48	/* (R/W) starting Physical address */
-#define DMA_Wk_ByteCntr 0x4C	/* ( R ) working byte counter */
-#define DMA_Wk_AddrCntr 0x50	/* ( R ) working address counter */
-#define DMA_Status   	0x54	/* ( R ) status register */
-#define DMA_MDL_Addr	0x58	/* (R/W) starting memory descriptor list (MDL)
-				 * address */
-#define DMA_Wk_MDL_Cntr 0x5C	/* ( R ) working MDL counter */
-#define DMA_ScsiBusCtrl 0x70	/* (bits R/W) SCSI BUS and control */
-
-/* ******************************************************* */
-#define am_target    	SCSISTATREG
-#define am_timeout   	INTSTATREG
-#define am_seq_step 	SYNCPERIOREG
-#define am_fifo_count	SYNCOFFREG
-
-
-#define amd_read8(amd, port)				\
-	bus_space_read_1((amd)->tag, (amd)->bsh, port)
-
-#define amd_read16(amd, port)				\
-	bus_space_read_2((amd)->tag, (amd)->bsh, port)
-
-#define amd_read32(amd, port)				\
-	bus_space_read_4((amd)->tag, (amd)->bsh, port)
-
-#define amd_write8(amd, port, value)			\
-	bus_space_write_1((amd)->tag, (amd)->bsh, port, value)
-
-#define amd_write8_multi(amd, port, ptr, len)		\
-	bus_space_write_multi_1((amd)->tag, (amd)->bsh, port, ptr, len)
-
-#define amd_write16(amd, port, value)			\
-	bus_space_write_2((amd)->tag, (amd)->bsh, port, value)
-
-#define amd_write32(amd, port, value)			\
-	bus_space_write_4((amd)->tag, (amd)->bsh, port, value)
-
-#endif /* AMD_H */
diff --git a/sys/dev/amr/amr_pci.c b/sys/dev/amr/amr_pci.c
index d72a129..b10c65f 100644
--- a/sys/dev/amr/amr_pci.c
+++ b/sys/dev/amr/amr_pci.c
@@ -106,9 +106,7 @@ static device_method_t amr_methods[] = {
     DEVMETHOD(device_suspend,	amr_pci_suspend),
     DEVMETHOD(device_resume,	amr_pci_resume),
 
-    DEVMETHOD(bus_print_child,	bus_generic_print_child),
-    DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-    { 0, 0 }
+    DEVMETHOD_END
 };
 
 static driver_t amr_pci_driver = {
diff --git a/sys/dev/an/if_an.c b/sys/dev/an/if_an.c
index f52f292..aa7c918 100644
--- a/sys/dev/an/if_an.c
+++ b/sys/dev/an/if_an.c
@@ -797,7 +797,7 @@ an_attach(struct an_softc *sc, int flags)
 	ADD(IFM_AUTO, IFM_IEEE80211_ADHOC);
 	for (i = 0; i < nrate; i++) {
 		r = sc->an_caps.an_rates[i];
-		mword = ieee80211_rate2media(NULL, r, IEEE80211_T_DS);
+		mword = ieee80211_rate2media(NULL, r, IEEE80211_MODE_AUTO);
 		if (mword == 0)
 			continue;
 		printf("%s%d%sMbps", (i != 0 ? " " : ""),
@@ -3299,7 +3299,7 @@ an_media_status(struct ifnet *ifp, struct ifmediareq *imr)
 	if (sc->an_config.an_opmode == AN_OPMODE_IBSS_ADHOC)
 		imr->ifm_active |= IFM_IEEE80211_ADHOC;
 	imr->ifm_active |= ieee80211_rate2media(NULL,
-		status.an_current_tx_rate, IEEE80211_T_DS);
+		status.an_current_tx_rate, IEEE80211_MODE_AUTO);
 	imr->ifm_status = IFM_AVALID;
 	if (status.an_opmode & AN_STATUS_OPMODE_ASSOCIATED)
 		imr->ifm_status |= IFM_ACTIVE;
diff --git a/sys/dev/arcmsr/arcmsr.c b/sys/dev/arcmsr/arcmsr.c
index 10bb504..9fde306 100644
--- a/sys/dev/arcmsr/arcmsr.c
+++ b/sys/dev/arcmsr/arcmsr.c
@@ -70,8 +70,11 @@
 **     1.20.00.21	03/03/2011		Ching Huang			 if a command timeout, then wait its ccb back before free it
 **     1.20.00.22	07/04/2011		Ching Huang			 Fixed multiple MTX panic
 ******************************************************************************************
-* $FreeBSD$
 */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #if 0
 #define ARCMSR_DEBUG1			1
 #endif
@@ -223,9 +226,8 @@ static device_method_t arcmsr_methods[]={
 	DEVMETHOD(device_shutdown,	arcmsr_shutdown),
 	DEVMETHOD(device_suspend,	arcmsr_suspend),
 	DEVMETHOD(device_resume,	arcmsr_resume),
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added, bus_generic_driver_added),
-	{ 0, 0 }
+
+	DEVMETHOD_END
 };
 	
 static driver_t arcmsr_driver={
@@ -2712,16 +2714,20 @@ static void arcmsr_action(struct cam_sim * psim, union ccb * pccb)
 			xpt_done(pccb);
 			break;
 		}
-	case XPT_CALC_GEOMETRY: {
-			struct ccb_calc_geometry *ccg;
-			u_int32_t size_mb;
-			u_int32_t secs_per_cylinder;
-	
+	case XPT_CALC_GEOMETRY:
 			if(pccb->ccb_h.target_id == 16) {
 				pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
 				xpt_done(pccb);
 				break;
 			}
+#if __FreeBSD_version >= 500000
+			cam_calc_geometry(&pccb->ccg, 1);
+#else
+			{
+			struct ccb_calc_geometry *ccg;
+			u_int32_t size_mb;
+			u_int32_t secs_per_cylinder;
+
 			ccg= &pccb->ccg;
 			if (ccg->block_size == 0) {
 				pccb->ccb_h.status = CAM_REQ_INVALID;
@@ -2744,9 +2750,10 @@ static void arcmsr_action(struct cam_sim * psim, union ccb * pccb)
 			secs_per_cylinder=ccg->heads * ccg->secs_per_track;
 			ccg->cylinders=ccg->volume_size / secs_per_cylinder;
 			pccb->ccb_h.status |= CAM_REQ_CMP;
+			}
+#endif
 			xpt_done(pccb);
 			break;
-		}
 	default:
 		pccb->ccb_h.status |= CAM_REQ_INVALID;
 		xpt_done(pccb);
diff --git a/sys/dev/ata/ata-disk.c b/sys/dev/ata/ata-disk.c
index c872f62..5388349 100644
--- a/sys/dev/ata/ata-disk.c
+++ b/sys/dev/ata/ata-disk.c
@@ -181,7 +181,7 @@ ad_detach(device_t dev)
     callout_drain(&atadev->spindown_timer);
 
     /* detach & delete all children */
-    device_delete_all_children(dev);
+    device_delete_children(dev);
 
     /* destroy disk from the system so we don't get any further requests */
     disk_destroy(adp->disk);
@@ -532,8 +532,8 @@ ad_describe(device_t dev)
     u_int8_t *marker, vendor[64], product[64];
 
     /* try to separate the ATA model string into vendor and model parts */
-    if ((marker = index(atadev->param.model, ' ')) ||
-	(marker = index(atadev->param.model, '-'))) {
+    if ((marker = strchr(atadev->param.model, ' ')) ||
+	(marker = strchr(atadev->param.model, '-'))) {
 	int len = (marker - atadev->param.model);
 
 	strncpy(vendor, atadev->param.model, len);
diff --git a/sys/dev/ata/ata-pci.c b/sys/dev/ata/ata-pci.c
index 9fcd003..f838d79 100644
--- a/sys/dev/ata/ata-pci.c
+++ b/sys/dev/ata/ata-pci.c
@@ -138,7 +138,7 @@ ata_pci_detach(device_t dev)
     struct ata_pci_controller *ctlr = device_get_softc(dev);
 
     /* detach & delete all children */
-    device_delete_all_children(dev);
+    device_delete_children(dev);
 
     if (ctlr->r_irq) {
 	bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle);
diff --git a/sys/dev/ata/ata-pci.h b/sys/dev/ata/ata-pci.h
index 2aa2065..f18812f 100644
--- a/sys/dev/ata/ata-pci.h
+++ b/sys/dev/ata/ata-pci.h
@@ -193,6 +193,10 @@ struct ata_pci_controller {
 #define ATA_I82801IB_AH4        0x29238086
 #define ATA_I82801IB_R1         0x29258086
 #define ATA_I82801IB_S2         0x29268086
+#define ATA_I82801IBM_S1        0x29288086
+#define ATA_I82801IBM_AH        0x29298086
+#define ATA_I82801IBM_R1        0x292a8086
+#define ATA_I82801IBM_S2        0x292d8086
 #define ATA_I82801JIB_S1        0x3a208086
 #define ATA_I82801JIB_AH        0x3a228086
 #define ATA_I82801JIB_R1        0x3a258086
diff --git a/sys/dev/ata/chipsets/ata-ati.c b/sys/dev/ata/chipsets/ata-ati.c
index 1dfd84b..ada70d7 100644
--- a/sys/dev/ata/chipsets/ata-ati.c
+++ b/sys/dev/ata/chipsets/ata-ati.c
@@ -53,6 +53,7 @@ __FBSDID("$FreeBSD$");
 
 /* local prototypes */
 static int ata_ati_chipinit(device_t dev);
+static int ata_ati_dumb_ch_attach(device_t dev);
 static int ata_ati_ixp700_ch_attach(device_t dev);
 static int ata_ati_setmode(device_t dev, int target, int mode);
 
@@ -63,6 +64,8 @@ static int ata_ati_setmode(device_t dev, int target, int mode);
 #define SII_MEMIO       1
 #define SII_BUG         0x04
 
+static int force_ahci = 1;
+TUNABLE_INT("hw.ahci.force", &force_ahci);
 
 /*
  * ATI chipset support functions
@@ -111,7 +114,10 @@ ata_ati_probe(device_t dev)
 	ctlr->chipinit = ata_sii_chipinit;
 	break;
     case ATI_AHCI:
-	ctlr->chipinit = ata_ahci_chipinit;
+	if (force_ahci == 1 || pci_get_subclass(dev) != PCIS_STORAGE_IDE)
+		ctlr->chipinit = ata_ahci_chipinit;
+	else
+		ctlr->chipinit = ata_ati_chipinit;
 	break;
     }
     return (BUS_PROBE_DEFAULT);
@@ -127,6 +133,11 @@ ata_ati_chipinit(device_t dev)
     if (ata_setup_interrupt(dev, ata_generic_intr))
 	return ENXIO;
 
+    if (ctlr->chip->cfg1 == ATI_AHCI) {
+	ctlr->ch_attach = ata_ati_dumb_ch_attach;
+	ctlr->setmode = ata_sata_setmode;
+	return (0);
+    }
     switch (ctlr->chip->chipid) {
     case ATA_ATI_IXP600:
 	/* IXP600 only has 1 PATA channel */
@@ -165,6 +176,17 @@ ata_ati_chipinit(device_t dev)
 }
 
 static int
+ata_ati_dumb_ch_attach(device_t dev)
+{
+	struct ata_channel *ch = device_get_softc(dev);
+
+	if (ata_pci_ch_attach(dev))
+		return ENXIO;
+	ch->flags |= ATA_SATA;
+	return (0);
+}
+
+static int
 ata_ati_ixp700_ch_attach(device_t dev)
 {
 	struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
diff --git a/sys/dev/ata/chipsets/ata-intel.c b/sys/dev/ata/chipsets/ata-intel.c
index c5c22cb..ebcfd79 100644
--- a/sys/dev/ata/chipsets/ata-intel.c
+++ b/sys/dev/ata/chipsets/ata-intel.c
@@ -157,6 +157,10 @@ ata_intel_probe(device_t dev)
      { ATA_I82801IB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
      { ATA_I82801IB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
      { ATA_I82801IB_R1,  0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
+     { ATA_I82801IBM_S1, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" },
+     { ATA_I82801IBM_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" },
+     { ATA_I82801IBM_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" },
+     { ATA_I82801IBM_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" },
      { ATA_I82801JIB_S1, 0, INTEL_6CH,  0, ATA_SA300, "ICH10" },
      { ATA_I82801JIB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
      { ATA_I82801JIB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
diff --git a/sys/dev/ata/chipsets/ata-nvidia.c b/sys/dev/ata/chipsets/ata-nvidia.c
index 2edc0f1..580dfca 100644
--- a/sys/dev/ata/chipsets/ata-nvidia.c
+++ b/sys/dev/ata/chipsets/ata-nvidia.c
@@ -65,6 +65,8 @@ static int ata_nvidia_setmode(device_t dev, int target, int mode);
 #define NVAHCI          0x04
 #define NVNOFORCE       0x08
 
+static int force_ahci = 1;
+TUNABLE_INT("hw.ahci.force", &force_ahci);
 
 /*
  * nVidia chipset support functions
@@ -181,7 +183,7 @@ ata_nvidia_probe(device_t dev)
 
     ata_set_desc(dev);
     if ((ctlr->chip->cfg1 & NVAHCI) &&
-	((ctlr->chip->cfg1 & NVNOFORCE) == 0 ||
+	((force_ahci == 1 && (ctlr->chip->cfg1 & NVNOFORCE) == 0) ||
 	 pci_get_subclass(dev) != PCIS_STORAGE_IDE))
 	ctlr->chipinit = ata_ahci_chipinit;
     else
diff --git a/sys/dev/ath/ath_hal/ar5210/ar5210reg.h b/sys/dev/ath/ath_hal/ar5210/ar5210reg.h
index 894d9bb..7382107 100644
--- a/sys/dev/ath/ath_hal/ar5210/ar5210reg.h
+++ b/sys/dev/ath/ath_hal/ar5210/ar5210reg.h
@@ -245,9 +245,20 @@
 #define	AR_SCR_SLDUR		0x0000ffff	/* sleep duration */
 #define	AR_SCR_SLE		0x00030000	/* sleep enable */
 #define	AR_SCR_SLE_S		16
-#define	AR_SCR_SLE_WAKE		0x00000000	/* force wake */
-#define	AR_SCR_SLE_SLP		0x00010000	/* force sleep */
-#define	AR_SCR_SLE_ALLOW	0x00020000	/* allow to control sleep */
+/*
+ * The previous values for the following three defines were:
+ *
+ *	AR_SCR_SLE_WAKE		0x00000000
+ *	AR_SCR_SLE_SLP		0x00010000
+ *	AR_SCR_SLE_ALLOW	0x00020000
+ *
+ * However, these have been pre-shifted with AR_SCR_SLE_S.  The
+ * OS_REG_READ() macro would attempt to shift them again, effectively
+ * shifting out any of the set bits completely.
+ */
+#define	AR_SCR_SLE_WAKE		0		/* force wake */
+#define	AR_SCR_SLE_SLP		1		/* force sleep */
+#define	AR_SCR_SLE_ALLOW	2		/* allow to control sleep */
 #define	AR_SCR_BITS	"\20\20SLE_SLP\21SLE_ALLOW"
 
 #define	AR_INTPEND_IP		0x00000001	/* interrupt pending */
diff --git a/sys/dev/ath/ath_hal/ar5211/ar5211reg.h b/sys/dev/ath/ath_hal/ar5211/ar5211reg.h
index 647f20d..93d4fc5 100644
--- a/sys/dev/ath/ath_hal/ar5211/ar5211reg.h
+++ b/sys/dev/ath/ath_hal/ar5211/ar5211reg.h
@@ -618,9 +618,20 @@
 #define	AR_SCR_SLDUR_S	0
 #define	AR_SCR_SLE	0x00030000	/* sleep enable mask */
 #define	AR_SCR_SLE_S	16		/* sleep enable bits shift */
-#define	AR_SCR_SLE_WAKE	0x00000000	/* force wake */
-#define	AR_SCR_SLE_SLP	0x00010000	/* force sleep */
-#define	AR_SCR_SLE_NORM	0x00020000	/* sleep logic normal operation */
+/*
+ * The previous values for the following three defines were:
+ *
+ *	AR_SCR_SLE_WAKE	0x00000000
+ *	AR_SCR_SLE_SLP	0x00010000
+ *	AR_SCR_SLE_NORM	0x00020000
+ *
+ * However, these have been pre-shifted with AR_SCR_SLE_S.  The
+ * OS_REG_READ() macro would attempt to shift them again, effectively
+ * shifting out any of the set bits completely.
+ */
+#define	AR_SCR_SLE_WAKE	0		/* force wake */
+#define	AR_SCR_SLE_SLP	1		/* force sleep */
+#define	AR_SCR_SLE_NORM	2		/* sleep logic normal operation */
 #define	AR_SCR_SLE_UNITS	0x00000008	/* SCR units/TU */
 #define	AR_SCR_BITS	"\20\20SLE_SLP\21SLE"
 
diff --git a/sys/dev/ath/ath_hal/ar5212/ar5212_misc.c b/sys/dev/ath/ath_hal/ar5212/ar5212_misc.c
index 0ea42d0..7eceec3 100644
--- a/sys/dev/ath/ath_hal/ar5212/ar5212_misc.c
+++ b/sys/dev/ath/ath_hal/ar5212/ar5212_misc.c
@@ -574,7 +574,7 @@ ar5212SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en)
 	struct ath_hal_5212 *ahp = AH5212(ah);
 
         if (keyidx >= HAL_DECOMP_MASK_SIZE)
-                return HAL_EINVAL; 
+                return AH_FALSE;
         OS_REG_WRITE(ah, AR_DCM_A, keyidx);
         OS_REG_WRITE(ah, AR_DCM_D, en ? AR_DCM_D_EN : 0);
         ahp->ah_decompMask[keyidx] = en;
diff --git a/sys/dev/ath/ath_hal/ar5416/ar2133.c b/sys/dev/ath/ath_hal/ar5416/ar2133.c
index f25c108..779f0de 100644
--- a/sys/dev/ath/ath_hal/ar5416/ar2133.c
+++ b/sys/dev/ath/ath_hal/ar5416/ar2133.c
@@ -549,3 +549,11 @@ ar2133RfAttach(struct ath_hal *ah, HAL_STATUS *status)
 
 	return AH_TRUE;
 }
+
+static HAL_BOOL
+ar2133Probe(struct ath_hal *ah)
+{
+	return (AR_SREV_OWL(ah) || AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah));
+}
+
+AH_RF(RF2133, ar2133Probe, ar2133RfAttach);
diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c b/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c
index 37412fa..940b516 100644
--- a/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c
+++ b/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c
@@ -339,7 +339,7 @@ ar5416Attach(uint16_t devid, HAL_SOFTC sc,
 	OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
 
 	/* Read Radio Chip Rev Extract */
-	AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah);
+	AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
 	switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
         case AR_RAD5122_SREV_MAJOR:	/* Fowl: 5G/2x2 */
         case AR_RAD2122_SREV_MAJOR:	/* Fowl: 2+5G/2x2 */
@@ -865,7 +865,7 @@ ar5416FillCapabilityInfo(struct ath_hal *ah)
 			;
 
 	pCap->halFastCCSupport = AH_TRUE;
-	pCap->halNumGpioPins = 6;
+	pCap->halNumGpioPins = 14;
 	pCap->halWowSupport = AH_FALSE;
 	pCap->halWowMatchPatternExact = AH_FALSE;
 	pCap->halBtCoexSupport = AH_FALSE;	/* XXX need support */
diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c b/sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c
index dc56d15..89334f5 100644
--- a/sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c
+++ b/sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c
@@ -35,7 +35,10 @@ static void
 cfgOutputMux(struct ath_hal *ah, uint32_t gpio, uint32_t type)
 {
 	int addr;
-	uint32_t gpio_shift, reg;
+	uint32_t gpio_shift, tmp;
+
+	HALDEBUG(ah, HAL_DEBUG_GPIO, "%s: gpio=%d, type=%d\n",
+	    __func__, gpio, type);
 
 	/* each MUX controls 6 GPIO pins */
 	if (gpio > 11)
@@ -61,12 +64,17 @@ cfgOutputMux(struct ath_hal *ah, uint32_t gpio, uint32_t type)
 	 * will never be used.  So it should be fine that bit 4 won't be
 	 * able to recover.
 	 */
-	reg = OS_REG_READ(ah, addr);
-	if (addr == AR_GPIO_OUTPUT_MUX1 && !AR_SREV_MERLIN_20_OR_LATER(ah))
-		reg = ((reg & 0x1F0) << 1) | (reg & ~0x1F0);
-	reg &= ~(0x1f << gpio_shift);
-	reg |= type << gpio_shift;
-	OS_REG_WRITE(ah, addr, reg);
+	if (AR_SREV_MERLIN_20_OR_LATER(ah) ||
+	    (addr != AR_GPIO_OUTPUT_MUX1)) {
+		OS_REG_RMW(ah, addr, (type << gpio_shift),
+		    (0x1f << gpio_shift));
+	} else {
+		tmp = OS_REG_READ(ah, addr);
+		tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
+		tmp &= ~(0x1f << gpio_shift);
+		tmp |= type << gpio_shift;
+		OS_REG_WRITE(ah, addr, tmp);
+	}
 }
 
 /*
@@ -79,12 +87,17 @@ ar5416GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)
 
 	HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
 
+	HALDEBUG(ah, HAL_DEBUG_GPIO,
+	    "%s: gpio=%d, type=%d\n", __func__, gpio, type);
+
 	/* NB: type maps directly to hardware */
+	/* XXX this may not actually be the case, for anything but output */
 	cfgOutputMux(ah, gpio, type);
 	gpio_shift = gpio << 1;			/* 2 bits per output mode */
 
 	reg = OS_REG_READ(ah, AR_GPIO_OE_OUT);
 	reg &= ~(AR_GPIO_OE_OUT_DRV << gpio_shift);
+	/* Always drive, rather than tristate/drive low/drive high */
 	reg |= AR_GPIO_OE_OUT_DRV_ALL << gpio_shift;
 	OS_REG_WRITE(ah, AR_GPIO_OE_OUT, reg);
 
@@ -101,6 +114,8 @@ ar5416GpioCfgInput(struct ath_hal *ah, uint32_t gpio)
 
 	HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
 
+	HALDEBUG(ah, HAL_DEBUG_GPIO, "%s: gpio=%d\n", __func__, gpio);
+
 	/* TODO: configure input mux for AR5416 */
 	/* If configured as input, set output to tristate */
 	gpio_shift = gpio << 1;
@@ -122,6 +137,8 @@ ar5416GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)
 	uint32_t reg;
 
 	HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
+	HALDEBUG(ah, HAL_DEBUG_GPIO,
+	   "%s: gpio=%d, val=%d\n", __func__, gpio, val);
 
 	reg = OS_REG_READ(ah, AR_GPIO_IN_OUT);
 	if (val & 1)
@@ -146,6 +163,8 @@ ar5416GpioGet(struct ath_hal *ah, uint32_t gpio)
 	 * Read output value for all gpio's, shift it,
 	 * and verify whether the specific bit is set.
 	 */
+	if (AR_SREV_KIWI_10_OR_LATER(ah))
+		bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR9287_GPIO_IN_VAL);
 	if (AR_SREV_KITE_10_OR_LATER(ah))
 		bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR9285_GPIO_IN_VAL);
 	else if (AR_SREV_MERLIN_10_OR_LATER(ah))
@@ -165,6 +184,8 @@ ar5416GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)
 	uint32_t val, mask;
 
 	HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
+	HALDEBUG(ah, HAL_DEBUG_GPIO,
+	    "%s: gpio=%d, ilevel=%d\n", __func__, gpio, ilevel);
 
 	if (ilevel == HAL_GPIO_INTR_DISABLE) {
 		val = MS(OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE),
diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_misc.c b/sys/dev/ath/ath_hal/ar5416/ar5416_misc.c
index b1c1b98..4df10cd 100644
--- a/sys/dev/ath/ath_hal/ar5416/ar5416_misc.c
+++ b/sys/dev/ath/ath_hal/ar5416/ar5416_misc.c
@@ -73,21 +73,29 @@ ar5416SetLedState(struct ath_hal *ah, HAL_LED_STATE state)
 		AR_MAC_LED_ASSOC_NONE,
 		AR_MAC_LED_ASSOC_NONE,
 	};
-	uint32_t bits;
 
 	if (AR_SREV_HOWL(ah))
 		return;
 
-	bits = OS_REG_READ(ah, AR_MAC_LED);
-	bits = (bits &~ AR_MAC_LED_MODE)
-	     | SM(AR_MAC_LED_MODE_POWON, AR_MAC_LED_MODE)
-#if 1
-	     | SM(AR_MAC_LED_MODE_NETON, AR_MAC_LED_MODE)
-#endif
-	     ;
-	bits = (bits &~ AR_MAC_LED_ASSOC)
-	     | SM(ledbits[state & 0x7], AR_MAC_LED_ASSOC);
-	OS_REG_WRITE(ah, AR_MAC_LED, bits);
+	/*
+	 * Set the blink operating mode.
+	 */
+	OS_REG_RMW_FIELD(ah, AR_MAC_LED,
+	    AR_MAC_LED_ASSOC, ledbits[state & 0x7]);
+
+	/* XXX Blink slow mode? */
+	/* XXX Blink threshold? */
+	/* XXX Blink sleep hystersis? */
+
+	/*
+	 * Set the LED blink configuration to be proportional
+	 * to the current TX and RX filter bytes.  (Ie, RX'ed
+	 * frames that don't match the filter are ignored.)
+	 * This means that higher TX/RX throughput will result
+	 * in the blink rate increasing.
+	 */
+	OS_REG_RMW_FIELD(ah, AR_MAC_LED, AR_MAC_LED_MODE,
+	    AR_MAC_LED_MODE_PROP);
 }
 
 /*
@@ -161,7 +169,7 @@ ar5416SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
 HAL_BOOL
 ar5416SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en)
 {
-	return HAL_OK;
+	return AH_TRUE;
 }
 
 /* Setup coverage class */
diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416reg.h b/sys/dev/ath/ath_hal/ar5416/ar5416reg.h
index 6f92eb7..6b00664 100644
--- a/sys/dev/ath/ath_hal/ar5416/ar5416reg.h
+++ b/sys/dev/ath/ath_hal/ar5416/ar5416reg.h
@@ -203,9 +203,9 @@
 #define	AR_MAC_LED_MODE_POWON	5	/* Power LED on (s/w control) */
 #define	AR_MAC_LED_MODE_NETON	6	/* Network LED on (s/w control) */
 #define	AR_MAC_LED_ASSOC	0x00000c00
-#define	AR_MAC_LED_ASSOC_NONE	0x00000000 /* STA is not associated or trying */
-#define	AR_MAC_LED_ASSOC_ACTIVE	0x00000400 /* STA is associated */
-#define	AR_MAC_LED_ASSOC_PEND	0x00000800 /* STA is trying to associate */
+#define	AR_MAC_LED_ASSOC_NONE	0x0	/* STA is not associated or trying */
+#define	AR_MAC_LED_ASSOC_ACTIVE	0x1	/* STA is associated */
+#define	AR_MAC_LED_ASSOC_PEND	0x2	/* STA is trying to associate */
 #define	AR_MAC_LED_ASSOC_S	10
 
 #define	AR_WA_UNTIE_RESET_EN	0x00008000	/* ena PCI reset to POR */
@@ -504,6 +504,8 @@
 #define	AR928X_GPIO_IN_VAL_S	10
 #define	AR9285_GPIO_IN_VAL	0x00FFF000
 #define	AR9285_GPIO_IN_VAL_S	12
+#define	AR9287_GPIO_IN_VAL	0x003FF800
+#define	AR9287_GPIO_IN_VAL_S	11
 
 #define	AR_GPIO_OE_OUT_DRV	0x3	/* 2 bit mask shifted by 2*bitpos */
 #define	AR_GPIO_OE_OUT_DRV_NO	0x0	/* tristate */
diff --git a/sys/dev/ath/ath_hal/ar9002/ar9280.c b/sys/dev/ath/ath_hal/ar9002/ar9280.c
index 99fd1d7..cc622f8 100644
--- a/sys/dev/ath/ath_hal/ar9002/ar9280.c
+++ b/sys/dev/ath/ath_hal/ar9002/ar9280.c
@@ -384,3 +384,11 @@ ar9280RfAttach(struct ath_hal *ah, HAL_STATUS *status)
 
 	return AH_TRUE;
 }
+
+static HAL_BOOL
+ar9280RfProbe(struct ath_hal *ah)
+{
+	return (AR_SREV_MERLIN(ah));
+}
+
+AH_RF(RF9280, ar9280RfProbe, ar9280RfAttach);
diff --git a/sys/dev/ath/ath_hal/ar9002/ar9285.c b/sys/dev/ath/ath_hal/ar9002/ar9285.c
index f1851cc..9e9f95c 100644
--- a/sys/dev/ath/ath_hal/ar9002/ar9285.c
+++ b/sys/dev/ath/ath_hal/ar9002/ar9285.c
@@ -77,3 +77,11 @@ ar9285RfAttach(struct ath_hal *ah, HAL_STATUS *status)
 
 	return AH_TRUE;
 }
+
+static HAL_BOOL
+ar9285RfProbe(struct ath_hal *ah)
+{
+	return (AR_SREV_KITE(ah));
+}
+
+AH_RF(RF9285, ar9285RfProbe, ar9285RfAttach);
diff --git a/sys/dev/ath/ath_hal/ar9002/ar9287.c b/sys/dev/ath/ath_hal/ar9002/ar9287.c
index 9b874b3..724fb7c 100644
--- a/sys/dev/ath/ath_hal/ar9002/ar9287.c
+++ b/sys/dev/ath/ath_hal/ar9002/ar9287.c
@@ -390,3 +390,11 @@ ar9287RfAttach(struct ath_hal *ah, HAL_STATUS *status)
 
 	return AH_TRUE;
 }
+
+static HAL_BOOL
+ar9287RfProbe(struct ath_hal *ah)
+{
+	return (AR_SREV_KIWI(ah));
+}
+
+AH_RF(RF9287, ar9287RfProbe, ar9287RfAttach);
diff --git a/sys/dev/ath/ath_hal/ar9002/ar9287.h b/sys/dev/ath/ath_hal/ar9002/ar9287.h
index 90d25ed..3122ea4 100644
--- a/sys/dev/ath/ath_hal/ar9002/ar9287.h
+++ b/sys/dev/ath/ath_hal/ar9002/ar9287.h
@@ -45,9 +45,7 @@ struct ath_hal_9287 {
 #define	AH9287(_ah)	((struct ath_hal_9287 *)(_ah))
 
 #define	AR9287_DEFAULT_RXCHAINMASK	3
-#define	AR9285_DEFAULT_RXCHAINMASK	1
 #define	AR9287_DEFAULT_TXCHAINMASK	3
-#define	AR9285_DEFAULT_TXCHAINMASK	1
 
 #define	AR_PHY_CCA_NOM_VAL_9287_2GHZ		-112
 #define	AR_PHY_CCA_NOM_VAL_9287_5GHZ		-112
diff --git a/sys/dev/ath/if_ath.c b/sys/dev/ath/if_ath.c
index 462bc3f..ae785b2 100644
--- a/sys/dev/ath/if_ath.c
+++ b/sys/dev/ath/if_ath.c
@@ -101,6 +101,7 @@ __FBSDID("$FreeBSD$");
 #include <dev/ath/if_ath_misc.h>
 #include <dev/ath/if_ath_tx.h>
 #include <dev/ath/if_ath_sysctl.h>
+#include <dev/ath/if_ath_led.h>
 #include <dev/ath/if_ath_keycache.h>
 #include <dev/ath/if_athdfs.h>
 
@@ -128,9 +129,9 @@ __FBSDID("$FreeBSD$");
 CTASSERT(ATH_BCBUF <= 8);
 
 static struct ieee80211vap *ath_vap_create(struct ieee80211com *,
-		    const char name[IFNAMSIZ], int unit, int opmode,
-		    int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
-		    const uint8_t mac[IEEE80211_ADDR_LEN]);
+		    const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
+		    const uint8_t [IEEE80211_ADDR_LEN],
+		    const uint8_t [IEEE80211_ADDR_LEN]);
 static void	ath_vap_delete(struct ieee80211vap *);
 static void	ath_init(void *);
 static void	ath_stop_locked(struct ifnet *);
@@ -204,7 +205,6 @@ static int	ath_setregdomain(struct ieee80211com *,
 static void	ath_getradiocaps(struct ieee80211com *, int, int *,
 		    struct ieee80211_channel []);
 static int	ath_getchannels(struct ath_softc *);
-static void	ath_led_event(struct ath_softc *, int);
 
 static int	ath_rate_setup(struct ath_softc *, u_int mode);
 static void	ath_setcurmode(struct ath_softc *, enum ieee80211_phymode);
@@ -299,7 +299,8 @@ ath_attach(u_int16_t devid, struct ath_softc *sc)
 	if_initname(ifp, device_get_name(sc->sc_dev),
 		device_get_unit(sc->sc_dev));
 
-	ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, sc->sc_eepromdata, &status);
+	ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh,
+	    sc->sc_eepromdata, &status);
 	if (ah == NULL) {
 		if_printf(ifp, "unable to attach hardware; HAL status %u\n",
 			status);
@@ -469,7 +470,8 @@ ath_attach(u_int16_t devid, struct ath_softc *sc)
 
 	/* Attach DFS module */
 	if (! ath_dfs_attach(sc)) {
-		device_printf(sc->sc_dev, "%s: unable to attach DFS\n", __func__);
+		device_printf(sc->sc_dev,
+		    "%s: unable to attach DFS\n", __func__);
 		error = EIO;
 		goto bad2;
 	}
@@ -477,22 +479,35 @@ ath_attach(u_int16_t devid, struct ath_softc *sc)
 	/* Start DFS processing tasklet */
 	TASK_INIT(&sc->sc_dfstask, 0, ath_dfs_tasklet, sc);
 
+	/* Configure LED state */
 	sc->sc_blinking = 0;
 	sc->sc_ledstate = 1;
 	sc->sc_ledon = 0;			/* low true */
 	sc->sc_ledidle = (2700*hz)/1000;	/* 2.7sec */
 	callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE);
+
+	/*
+	 * Don't setup hardware-based blinking.
+	 *
+	 * Although some NICs may have this configured in the
+	 * default reset register values, the user may wish
+	 * to alter which pins have which function.
+	 *
+	 * The reference driver attaches the MAC network LED to GPIO1 and
+	 * the MAC power LED to GPIO2.  However, the DWA-552 cardbus
+	 * NIC has these reversed.
+	 */
+	sc->sc_hardled = (1 == 0);
+	sc->sc_led_net_pin = -1;
+	sc->sc_led_pwr_pin = -1;
 	/*
 	 * Auto-enable soft led processing for IBM cards and for
 	 * 5211 minipci cards.  Users can also manually enable/disable
 	 * support with a sysctl.
 	 */
 	sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID);
-	if (sc->sc_softled) {
-		ath_hal_gpioCfgOutput(ah, sc->sc_ledpin,
-		    HAL_GPIO_MUX_MAC_NETWORK_LED);
-		ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon);
-	}
+	ath_led_config(sc);
+	ath_hal_setledstate(ah, HAL_LED_INIT);
 
 	ifp->if_softc = sc;
 	ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
@@ -521,7 +536,7 @@ ath_attach(u_int16_t devid, struct ath_softc *sc)
 		| IEEE80211_C_BGSCAN		/* capable of bg scanning */
 		| IEEE80211_C_TXFRAG		/* handle tx frags */
 #ifdef	ATH_ENABLE_DFS
-		| IEEE80211_C_DFS		/* Enable DFS radar detection */
+		| IEEE80211_C_DFS		/* Enable radar detection */
 #endif
 		;
 	/*
@@ -633,11 +648,12 @@ ath_attach(u_int16_t devid, struct ath_softc *sc)
 		int rxs, txs;
 
 		device_printf(sc->sc_dev, "[HT] enabling HT modes\n");
-		ic->ic_htcaps = IEEE80211_HTC_HT		/* HT operation */
-			    | IEEE80211_HTC_AMPDU		/* A-MPDU tx/rx */
-			    | IEEE80211_HTC_AMSDU		/* A-MSDU tx/rx */
-			    | IEEE80211_HTCAP_MAXAMSDU_3839	/* max A-MSDU length */
-			    | IEEE80211_HTCAP_SMPS_OFF;		/* SM power save off */
+		ic->ic_htcaps = IEEE80211_HTC_HT	/* HT operation */
+			    | IEEE80211_HTC_AMPDU	/* A-MPDU tx/rx */
+			    | IEEE80211_HTC_AMSDU	/* A-MSDU tx/rx */
+			    | IEEE80211_HTCAP_MAXAMSDU_3839
+			    				/* max A-MSDU length */
+			    | IEEE80211_HTCAP_SMPS_OFF;	/* SM power save off */
 			;
 
 		/*
@@ -658,8 +674,8 @@ ath_attach(u_int16_t devid, struct ath_softc *sc)
 			    |  IEEE80211_HTCAP_SHORTGI40;
 
 		/*
-		 * rx/tx stream is not currently used anywhere; it needs to be taken
-		 * into account when negotiating which MCS rates it'll receive and
+		 * TX/RX streams need to be taken into account when
+		 * negotiating which MCS rates it'll receive and
 		 * what MCS rates are available for TX.
 		 */
 		(void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 0, &rxs);
@@ -671,7 +687,8 @@ ath_attach(u_int16_t devid, struct ath_softc *sc)
 		ic->ic_txstream = txs;
 		ic->ic_rxstream = rxs;
 
-		device_printf(sc->sc_dev, "[HT] %d RX streams; %d TX streams\n", rxs, txs);
+		device_printf(sc->sc_dev,
+		    "[HT] %d RX streams; %d TX streams\n", rxs, txs);
 	}
 #endif
 
@@ -683,7 +700,8 @@ ath_attach(u_int16_t devid, struct ath_softc *sc)
 	    ath_hal_getcapability(ah, HAL_CAP_SERIALISE_WAR,
 	     0, NULL) == HAL_OK) {
 		sc->sc_ah->ah_config.ah_serialise_reg_war = 1;
-		device_printf(sc->sc_dev, "Enabling register serialisation\n");
+		device_printf(sc->sc_dev,
+		    "Enabling register serialisation\n");
 	}
 
 	/*
@@ -885,16 +903,17 @@ assign_bslot(struct ath_softc *sc)
 }
 
 static struct ieee80211vap *
-ath_vap_create(struct ieee80211com *ic,
-	const char name[IFNAMSIZ], int unit, int opmode, int flags,
-	const uint8_t bssid[IEEE80211_ADDR_LEN],
-	const uint8_t mac0[IEEE80211_ADDR_LEN])
+ath_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
+    enum ieee80211_opmode opmode, int flags,
+    const uint8_t bssid[IEEE80211_ADDR_LEN],
+    const uint8_t mac0[IEEE80211_ADDR_LEN])
 {
 	struct ath_softc *sc = ic->ic_ifp->if_softc;
 	struct ath_vap *avp;
 	struct ieee80211vap *vap;
 	uint8_t mac[IEEE80211_ADDR_LEN];
-	int ic_opmode, needbeacon, error;
+	int needbeacon, error;
+	enum ieee80211_opmode ic_opmode;
 
 	avp = (struct ath_vap *) malloc(sizeof(struct ath_vap),
 	    M_80211_VAP, M_WAITOK | M_ZERO);
@@ -1310,9 +1329,14 @@ ath_resume(struct ath_softc *sc)
 	/* Let DFS at it in case it's a DFS channel */
 	ath_dfs_radar_enable(sc, ic->ic_curchan);
 
+	/* Restore the LED configuration */
+	ath_led_config(sc);
+	ath_hal_setledstate(ah, HAL_LED_INIT);
+
 	if (sc->sc_resume_up) {
 		if (ic->ic_opmode == IEEE80211_M_STA) {
 			ath_init(sc);
+			ath_hal_setledstate(ah, HAL_LED_RUN);
 			/*
 			 * Program the beacon registers using the last rx'd
 			 * beacon frame and enable sync on the next beacon
@@ -1326,11 +1350,6 @@ ath_resume(struct ath_softc *sc)
 		} else
 			ieee80211_resume_all(ic);
 	}
-	if (sc->sc_softled) {
-		ath_hal_gpioCfgOutput(ah, sc->sc_ledpin,
-		    HAL_GPIO_MUX_MAC_NETWORK_LED);
-		ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon);
-	}
 
 	/* XXX beacons ? */
 }
@@ -1878,7 +1897,7 @@ ath_txrx_stop(struct ath_softc *sc)
 	    sc->sc_txstart_cnt || sc->sc_intr_cnt) {
 		if (i <= 0)
 			break;
-		msleep(sc, &sc->sc_mtx, 0, "ath_txrx_stop", 1);
+		msleep(sc, &sc->sc_pcu_mtx, 0, "ath_txrx_stop", 1);
 		i--;
 	}
 	ATH_PCU_UNLOCK(sc);
@@ -1897,6 +1916,70 @@ ath_txrx_start(struct ath_softc *sc)
 	taskqueue_unblock(sc->sc_tq);
 }
 
+/*
+ * Grab the reset lock, and wait around until noone else
+ * is trying to do anything with it.
+ *
+ * This is totally horrible but we can't hold this lock for
+ * long enough to do TX/RX or we end up with net80211/ip stack
+ * LORs and eventual deadlock.
+ *
+ * "dowait" signals whether to spin, waiting for the reset
+ * lock count to reach 0. This should (for now) only be used
+ * during the reset path, as the rest of the code may not
+ * be locking-reentrant enough to behave correctly.
+ *
+ * Another, cleaner way should be found to serialise all of
+ * these operations.
+ */
+#define	MAX_RESET_ITERATIONS	10
+static int
+ath_reset_grablock(struct ath_softc *sc, int dowait)
+{
+	int w = 0;
+	int i = MAX_RESET_ITERATIONS;
+
+	ATH_PCU_LOCK_ASSERT(sc);
+	do {
+		if (sc->sc_inreset_cnt == 0) {
+			w = 1;
+			break;
+		}
+		if (dowait == 0) {
+			w = 0;
+			break;
+		}
+		ATH_PCU_UNLOCK(sc);
+		pause("ath_reset_grablock", 1);
+		i--;
+		ATH_PCU_LOCK(sc);
+	} while (i > 0);
+
+	/*
+	 * We always increment the refcounter, regardless
+	 * of whether we succeeded to get it in an exclusive
+	 * way.
+	 */
+	sc->sc_inreset_cnt++;
+
+	if (i <= 0)
+		device_printf(sc->sc_dev,
+		    "%s: didn't finish after %d iterations\n",
+		    __func__, MAX_RESET_ITERATIONS);
+
+	if (w == 0)
+		device_printf(sc->sc_dev,
+		    "%s: warning, recursive reset path!\n",
+		    __func__);
+
+	return w;
+}
+#undef MAX_RESET_ITERATIONS
+
+/*
+ * XXX TODO: write ath_reset_releaselock
+ */
+
 static void
 ath_stop(struct ifnet *ifp)
 {
@@ -1925,18 +2008,15 @@ ath_reset(struct ifnet *ifp, ATH_RESET_TYPE reset_type)
 
 	DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__);
 
-	/* XXX ensure ATH_LOCK isn't held; ath_rx_proc can't be locked */
+	/* Ensure ATH_LOCK isn't held; ath_rx_proc can't be locked */
 	ATH_PCU_UNLOCK_ASSERT(sc);
 	ATH_UNLOCK_ASSERT(sc);
 
 	ATH_PCU_LOCK(sc);
-	/* XXX if we're already inside a reset, print out a big warning */
-	if (sc->sc_inreset_cnt > 0) {
-		device_printf(sc->sc_dev,
-		    "%s: concurrent ath_reset()! Danger!\n",
+	if (ath_reset_grablock(sc, 1) == 0) {
+		device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n",
 		    __func__);
 	}
-	sc->sc_inreset_cnt++;
 	ath_hal_intrset(ah, 0);		/* disable interrupts */
 	ATH_PCU_UNLOCK(sc);
 
@@ -3961,6 +4041,7 @@ ath_rx_proc(struct ath_softc *sc, int resched)
 		npkts++;
 
 		/* These aren't specifically errors */
+#ifdef	AH_SUPPORT_AR5416
 		if (rs->rs_flags & HAL_RX_GI)
 			sc->sc_stats.ast_rx_halfgi++;
 		if (rs->rs_flags & HAL_RX_2040)
@@ -3973,6 +4054,7 @@ ath_rx_proc(struct ath_softc *sc, int resched)
 			sc->sc_stats.ast_rx_decrypt_busy_err++;
 		if (rs->rs_flags & HAL_RX_HI_RX_CHAIN)
 			sc->sc_stats.ast_rx_hi_rx_chain++;
+#endif /* AH_SUPPORT_AR5416 */
 
 		if (rs->rs_status != 0) {
 			if (rs->rs_status & HAL_RXERR_CRC)
@@ -4110,6 +4192,35 @@ rx_accept:
 			m->m_pkthdr.len = len;
 		}
 
+		/*
+		 * Validate rs->rs_antenna.
+		 *
+		 * Some users w/ AR9285 NICs have reported crashes
+		 * here because rs_antenna field is bogusly large.
+		 * Let's enforce the maximum antenna limit of 8
+		 * (and it shouldn't be hard coded, but that's a
+		 * separate problem) and if there's an issue, print
+		 * out an error and adjust rs_antenna to something
+		 * sensible.
+		 *
+		 * This code should be removed once the actual
+		 * root cause of the issue has been identified.
+		 * For example, it may be that the rs_antenna
+		 * field is only valid for the lsat frame of
+		 * an aggregate and it just happens that it is
+		 * "mostly" right. (This is a general statement -
+		 * the majority of the statistics are only valid
+		 * for the last frame in an aggregate.
+		 */
+		if (rs->rs_antenna > 7) {
+			device_printf(sc->sc_dev, "%s: rs_antenna > 7 (%d)\n",
+			    __func__, rs->rs_antenna);
+#ifdef	ATH_DEBUG
+			ath_printrxbuf(sc, bf, 0, status == HAL_OK);
+#endif /* ATH_DEBUG */
+			rs->rs_antenna = 0;	/* XXX better than nothing */
+		}
+
 		ifp->if_ipackets++;
 		sc->sc_stats.ast_ant_rx[rs->rs_antenna]++;
 
@@ -4161,8 +4272,10 @@ rx_accept:
 				IEEE80211_KEYIX_NONE : rs->rs_keyix);
 		sc->sc_lastrs = rs;
 
+#ifdef	AH_SUPPORT_AR5416
 		if (rs->rs_isaggr)
 			sc->sc_stats.ast_rx_agg++;
+#endif /* AH_SUPPORT_AR5416 */
 
 		if (ni != NULL) {
 			/*
@@ -5216,10 +5329,10 @@ ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
 
 	/* Treat this as an interface reset */
 	ATH_PCU_LOCK(sc);
-	if (sc->sc_inreset_cnt > 0)
-		device_printf(sc->sc_dev, "%s: danger! concurrent reset!\n",
+	if (ath_reset_grablock(sc, 1) == 0) {
+		device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n",
 		    __func__);
-	sc->sc_inreset_cnt++;
+	}
 	if (chan != sc->sc_curchan) {
 		dointr = 1;
 		/* XXX only do this if inreset_cnt is 1? */
@@ -5370,6 +5483,7 @@ ath_calibrate(void *arg)
 			sc->sc_doresetcal = AH_TRUE;
 			ATH_UNLOCK(sc);
 			ath_reset(ifp, ATH_RESET_NOLOSS);
+			ATH_LOCK(sc);
 			return;
 		}
 		/*
@@ -5855,49 +5969,6 @@ ath_getchannels(struct ath_softc *sc)
 	return 0;
 }
 
-static void
-ath_led_done(void *arg)
-{
-	struct ath_softc *sc = arg;
-
-	sc->sc_blinking = 0;
-}
-
-/*
- * Turn the LED off: flip the pin and then set a timer so no
- * update will happen for the specified duration.
- */
-static void
-ath_led_off(void *arg)
-{
-	struct ath_softc *sc = arg;
-
-	ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon);
-	callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc);
-}
-
-/*
- * Blink the LED according to the specified on/off times.
- */
-static void
-ath_led_blink(struct ath_softc *sc, int on, int off)
-{
-	DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off);
-	ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon);
-	sc->sc_blinking = 1;
-	sc->sc_ledoff = off;
-	callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc);
-}
-
-static void
-ath_led_event(struct ath_softc *sc, int rix)
-{
-	sc->sc_ledevent = ticks;	/* time of last event */
-	if (sc->sc_blinking)		/* don't interrupt active blink */
-		return;
-	ath_led_blink(sc, sc->sc_hwmap[rix].ledon, sc->sc_hwmap[rix].ledoff);
-}
-
 static int
 ath_rate_setup(struct ath_softc *sc, u_int mode)
 {
@@ -6217,6 +6288,8 @@ ath_announce(struct ath_softc *sc)
 	if_printf(ifp, "AR%s mac %d.%d RF%s phy %d.%d\n",
 		ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev,
 		ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf);
+	if_printf(ifp, "2GHz radio: 0x%.4x; 5GHz radio: 0x%.4x\n",
+		ah->ah_analog2GhzRev, ah->ah_analog5GhzRev);
 	if (bootverbose) {
 		int i;
 		for (i = 0; i <= WME_AC_VO; i++) {
diff --git a/sys/dev/ath/if_ath_led.c b/sys/dev/ath/if_ath_led.c
new file mode 100644
index 0000000..47ae3e1
--- /dev/null
+++ b/sys/dev/ath/if_ath_led.c
@@ -0,0 +1,190 @@
+/*-
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer,
+ *    without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
+ *    redistribution must be conditioned upon including a substantially
+ *    similar Disclaimer requirement for further binary redistribution.
+ *
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * Driver for the Atheros Wireless LAN controller.
+ *
+ * This software is derived from work of Atsushi Onoe; his contribution
+ * is greatly appreciated.
+ */
+
+#include "opt_inet.h"
+#include "opt_ath.h"
+/*
+ * This is needed for register operations which are performed
+ * by the driver - eg, calls to ath_hal_gettsf32().
+ */
+#include "opt_ah.h"
+#include "opt_wlan.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/sysctl.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/sockio.h>
+#include <sys/errno.h>
+#include <sys/callout.h>
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/kthread.h>
+#include <sys/taskqueue.h>
+#include <sys/priv.h>
+#include <sys/module.h>
+#include <sys/ktr.h>
+#include <sys/smp.h>	/* for mp_ncpus */
+
+#include <machine/bus.h>
+
+#include <net/if.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+#include <net/if_arp.h>
+#include <net/ethernet.h>
+#include <net/if_llc.h>
+
+#include <net80211/ieee80211_var.h>
+#include <net80211/ieee80211_regdomain.h>
+#ifdef IEEE80211_SUPPORT_SUPERG
+#include <net80211/ieee80211_superg.h>
+#endif
+#ifdef IEEE80211_SUPPORT_TDMA
+#include <net80211/ieee80211_tdma.h>
+#endif
+
+#include <net/bpf.h>
+
+#ifdef INET
+#include <netinet/in.h>
+#include <netinet/if_ether.h>
+#endif
+
+#include <dev/ath/if_athvar.h>
+#include <dev/ath/ath_hal/ah_devid.h>		/* XXX for softled */
+#include <dev/ath/ath_hal/ah_diagcodes.h>
+
+#include <dev/ath/if_ath_debug.h>
+#include <dev/ath/if_ath_misc.h>
+
+#include <dev/ath/if_ath_led.h>
+
+/*
+ * Software LED driver routines.
+ */
+
+/*
+ * XXX TODO: move the LED sysctls here.
+ */
+
+
+/*
+ * Configure the hardware for software and LED blinking.
+ * The user may choose to configure part of each, depending upon the
+ * NIC being used.
+ *
+ * This requires the configuration to be set before this function
+ * is called.
+ */
+void
+ath_led_config(struct ath_softc *sc)
+{
+	/* Software LED blinking - GPIO controlled LED */
+	if (sc->sc_softled) {
+		ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin,
+		    HAL_GPIO_MUX_OUTPUT);
+		ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon);
+	}
+
+	/* Hardware LED blinking - MAC controlled LED */
+	if (sc->sc_hardled) {
+		/*
+		 * Only enable each LED if required.
+		 *
+		 * Some NICs only have one LED connected; others may
+		 * have GPIO1/GPIO2 connected to other hardware.
+		 */
+		if (sc->sc_led_pwr_pin > 0)
+			ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_led_pwr_pin,
+			    HAL_GPIO_MUX_MAC_POWER_LED);
+		if (sc->sc_led_net_pin > 0)
+			ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_led_net_pin,
+			    HAL_GPIO_MUX_MAC_NETWORK_LED);
+	}
+}
+
+static void
+ath_led_done(void *arg)
+{
+	struct ath_softc *sc = arg;
+
+	sc->sc_blinking = 0;
+}
+
+/*
+ * Turn the LED off: flip the pin and then set a timer so no
+ * update will happen for the specified duration.
+ */
+static void
+ath_led_off(void *arg)
+{
+	struct ath_softc *sc = arg;
+
+	ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon);
+	callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc);
+}
+
+/*
+ * Blink the LED according to the specified on/off times.
+ */
+static void
+ath_led_blink(struct ath_softc *sc, int on, int off)
+{
+	DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off);
+	ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon);
+	sc->sc_blinking = 1;
+	sc->sc_ledoff = off;
+	callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc);
+}
+
+void
+ath_led_event(struct ath_softc *sc, int rix)
+{
+	sc->sc_ledevent = ticks;	/* time of last event */
+	if (sc->sc_blinking)		/* don't interrupt active blink */
+		return;
+	ath_led_blink(sc, sc->sc_hwmap[rix].ledon, sc->sc_hwmap[rix].ledoff);
+}
diff --git a/sys/dev/ath/if_ath_led.h b/sys/dev/ath/if_ath_led.h
new file mode 100644
index 0000000..54de4c4
--- /dev/null
+++ b/sys/dev/ath/if_ath_led.h
@@ -0,0 +1,37 @@
+/*-
+ * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer,
+ *    without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
+ *    redistribution must be conditioned upon including a substantially
+ *    similar Disclaimer requirement for further binary redistribution.
+ *
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.
+ *
+ * $FreeBSD$
+ */
+#ifndef	__IF_ATH_LED_H__
+#define	__IF_ATH_LED_H__
+
+extern	void ath_led_event(struct ath_softc *sc, int rix);
+extern	void ath_led_config(struct ath_softc *sc);
+
+#endif
diff --git a/sys/dev/ath/if_ath_sysctl.c b/sys/dev/ath/if_ath_sysctl.c
index 5323504..57781f5 100644
--- a/sys/dev/ath/if_ath_sysctl.c
+++ b/sys/dev/ath/if_ath_sysctl.c
@@ -90,6 +90,7 @@ __FBSDID("$FreeBSD$");
 #include <dev/ath/ath_hal/ah_diagcodes.h>
 
 #include <dev/ath/if_ath_debug.h>
+#include <dev/ath/if_ath_led.h>
 #include <dev/ath/if_ath_misc.h>
 #include <dev/ath/if_ath_tx.h>
 #include <dev/ath/if_ath_sysctl.h>
@@ -151,10 +152,7 @@ ath_sysctl_softled(SYSCTL_HANDLER_ARGS)
 	if (softled != sc->sc_softled) {
 		if (softled) {
 			/* NB: handle any sc_ledpin change */
-			ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin,
-			    HAL_GPIO_MUX_MAC_NETWORK_LED);
-			ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin,
-				!sc->sc_ledon);
+			ath_led_config(sc);
 		}
 		sc->sc_softled = softled;
 	}
@@ -174,16 +172,34 @@ ath_sysctl_ledpin(SYSCTL_HANDLER_ARGS)
 	if (ledpin != sc->sc_ledpin) {
 		sc->sc_ledpin = ledpin;
 		if (sc->sc_softled) {
-			ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin,
-			    HAL_GPIO_MUX_MAC_NETWORK_LED);
-			ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin,
-				!sc->sc_ledon);
+			ath_led_config(sc);
 		}
 	}
 	return 0;
 }
 
 static int
+ath_sysctl_hardled(SYSCTL_HANDLER_ARGS)
+{
+	struct ath_softc *sc = arg1;
+	int hardled = sc->sc_hardled;
+	int error;
+
+	error = sysctl_handle_int(oidp, &hardled, 0, req);
+	if (error || !req->newptr)
+		return error;
+	hardled = (hardled != 0);
+	if (hardled != sc->sc_hardled) {
+		if (hardled) {
+			/* NB: handle any sc_ledpin change */
+			ath_led_config(sc);
+		}
+		sc->sc_hardled = hardled;
+	}
+	return 0;
+}
+
+static int
 ath_sysctl_txantenna(SYSCTL_HANDLER_ARGS)
 {
 	struct ath_softc *sc = arg1;
@@ -496,6 +512,7 @@ ath_sysctlattach(struct ath_softc *sc)
 	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 		"ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
 		ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)");
+
 	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 		"softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
 		ath_sysctl_softled, "I", "enable/disable software LED support");
@@ -508,6 +525,18 @@ ath_sysctlattach(struct ath_softc *sc)
 	SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 		"ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0,
 		"idle time for inactivity LED (ticks)");
+
+	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
+		"hardled", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
+		ath_sysctl_hardled, "I", "enable/disable hardware LED support");
+	/* XXX Laziness - configure pins, then flip hardled off/on */
+	SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
+		"led_net_pin", CTLFLAG_RW, &sc->sc_led_net_pin, 0,
+		"MAC Network LED pin, or -1 to disable");
+	SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
+		"led_pwr_pin", CTLFLAG_RW, &sc->sc_led_pwr_pin, 0,
+		"MAC Power LED pin, or -1 to disable");
+
 	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 		"txantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
 		ath_sysctl_txantenna, "I", "antenna switch");
@@ -842,9 +871,15 @@ ath_sysctl_stats_attach(struct ath_softc *sc)
 	    &sc->sc_stats.ast_tx_data_underrun, 0, "");
 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_delim_underrun", CTLFLAG_RD,
 	    &sc->sc_stats.ast_tx_delim_underrun, 0, "");
-	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_aggrfail", CTLFLAG_RD,
-	    &sc->sc_stats.ast_tx_aggrfail, 0,
+	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_aggr_failall", CTLFLAG_RD,
+	    &sc->sc_stats.ast_tx_aggr_failall, 0,
 	    "Number of aggregate TX failures (whole frame)");
+	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_aggr_ok", CTLFLAG_RD,
+	    &sc->sc_stats.ast_tx_aggr_ok, 0,
+	    "Number of aggregate TX OK completions (subframe)");
+	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_aggr_fail", CTLFLAG_RD,
+	    &sc->sc_stats.ast_tx_aggr_fail, 0,
+	    "Number of aggregate TX failures (subframe)");
 
 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_intr", CTLFLAG_RD,
 	    &sc->sc_stats.ast_rx_intr, 0, "RX interrupts");
diff --git a/sys/dev/ath/if_ath_tx.c b/sys/dev/ath/if_ath_tx.c
index 5625bf2..3d2204a 100644
--- a/sys/dev/ath/if_ath_tx.c
+++ b/sys/dev/ath/if_ath_tx.c
@@ -2405,6 +2405,12 @@ ath_tx_tid_drain(struct ath_softc *sc, struct ath_node *an, struct ath_tid *tid,
 			     tid->hwq_depth, tid->incomp, tid->baw_head,
 			     tid->baw_tail, tap == NULL ? -1 : tap->txa_start,
 			     ni->ni_txseqs[tid->tid]);
+
+			/* XXX Dump the frame, see what it is? */
+			ieee80211_dump_pkt(ni->ni_ic,
+			    mtod(bf->bf_m, const uint8_t *),
+			    bf->bf_m->m_len, 0, -1);
+
 			t = 1;
 		}
 
@@ -2940,7 +2946,6 @@ ath_tx_comp_aggr_error(struct ath_softc *sc, struct ath_buf *bf_first,
 
 	TAILQ_INIT(&bf_q);
 	TAILQ_INIT(&bf_cq);
-	sc->sc_stats.ast_tx_aggrfail++;
 
 	/*
 	 * Update rate control - all frames have failed.
@@ -2955,12 +2960,14 @@ ath_tx_comp_aggr_error(struct ath_softc *sc, struct ath_buf *bf_first,
 
 	ATH_TXQ_LOCK(sc->sc_ac2q[tid->ac]);
 	tap = ath_tx_get_tx_tid(an, tid->tid);
+	sc->sc_stats.ast_tx_aggr_failall++;
 
 	/* Retry all subframes */
 	bf = bf_first;
 	while (bf) {
 		bf_next = bf->bf_next;
 		bf->bf_next = NULL;	/* Remove it from the aggr list */
+		sc->sc_stats.ast_tx_aggr_fail++;
 		if (ath_tx_retry_subframe(sc, bf, &bf_q)) {
 			drops++;
 			bf->bf_next = NULL;
@@ -3196,6 +3203,7 @@ ath_tx_aggr_comp_aggr(struct ath_softc *sc, struct ath_buf *bf_first, int fail)
 		    ATH_BA_ISSET(ba, ba_index));
 
 		if (tx_ok && ATH_BA_ISSET(ba, ba_index)) {
+			sc->sc_stats.ast_tx_aggr_ok++;
 			ath_tx_update_baw(sc, an, atid, bf);
 			bf->bf_state.bfs_dobaw = 0;
 			if (! bf->bf_state.bfs_addedbaw)
@@ -3205,6 +3213,7 @@ ath_tx_aggr_comp_aggr(struct ath_softc *sc, struct ath_buf *bf_first, int fail)
 			bf->bf_next = NULL;
 			TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list);
 		} else {
+			sc->sc_stats.ast_tx_aggr_fail++;
 			if (ath_tx_retry_subframe(sc, bf, &bf_q)) {
 				drops++;
 				bf->bf_next = NULL;
diff --git a/sys/dev/ath/if_athioctl.h b/sys/dev/ath/if_athioctl.h
index 680694f..9c1cc12 100644
--- a/sys/dev/ath/if_athioctl.h
+++ b/sys/dev/ath/if_athioctl.h
@@ -148,12 +148,14 @@ struct ath_stats {
 	u_int32_t	ast_tx_swretrymax;	/* software TX retry max limit reach */
 	u_int32_t	ast_tx_data_underrun;
 	u_int32_t	ast_tx_delim_underrun;
-	u_int32_t	ast_tx_aggrfail;		/* aggregate TX failed in its entirety */
+	u_int32_t	ast_tx_aggr_failall;	/* aggregate TX failed in its entirety */
 	u_int32_t	ast_tx_getnobuf;
 	u_int32_t	ast_tx_getbusybuf;
 	u_int32_t	ast_tx_intr;
 	u_int32_t	ast_rx_intr;
-	u_int32_t	ast_pad[4];
+	u_int32_t	ast_tx_aggr_ok;		/* aggregate TX ok */
+	u_int32_t	ast_tx_aggr_fail;	/* aggregate TX failed */
+	u_int32_t	ast_pad[2];
 };
 
 #define	SIOCGATHSTATS	_IOWR('i', 137, struct ifreq)
diff --git a/sys/dev/ath/if_athvar.h b/sys/dev/ath/if_athvar.h
index 331bea4..8491fe1 100644
--- a/sys/dev/ath/if_athvar.h
+++ b/sys/dev/ath/if_athvar.h
@@ -371,6 +371,7 @@ struct ath_softc {
 	unsigned int		sc_invalid  : 1,/* disable hardware accesses */
 				sc_mrretry  : 1,/* multi-rate retry support */
 				sc_softled  : 1,/* enable LED gpio status */
+				sc_hardled  : 1,/* enable MAC LED status */
 				sc_splitmic : 1,/* split TKIP MIC keys */
 				sc_needmib  : 1,/* enable MIB stats intr */
 				sc_diversity: 1,/* enable rx diversity */
@@ -445,6 +446,9 @@ struct ath_softc {
 	u_int			sc_keymax;	/* size of key cache */
 	u_int8_t		sc_keymap[ATH_KEYBYTES];/* key use bit map */
 
+	/*
+	 * Software based LED blinking
+	 */
 	u_int			sc_ledpin;	/* GPIO pin for driving LED */
 	u_int			sc_ledon;	/* pin setting for LED on */
 	u_int			sc_ledidle;	/* idle polling interval */
@@ -453,6 +457,12 @@ struct ath_softc {
 	u_int16_t		sc_ledoff;	/* off time for current blink */
 	struct callout		sc_ledtimer;	/* led off timer */
 
+	/*
+	 * Hardware based LED blinking
+	 */
+	int			sc_led_pwr_pin;	/* MAC power LED GPIO pin */
+	int			sc_led_net_pin;	/* MAC network LED GPIO pin */
+
 	u_int			sc_rfsilentpin;	/* GPIO pin for rfkill int */
 	u_int			sc_rfsilentpol;	/* pin setting for rfkill on */
 
diff --git a/sys/dev/bce/if_bce.c b/sys/dev/bce/if_bce.c
index 39a93aa..72ba76a 100644
--- a/sys/dev/bce/if_bce.c
+++ b/sys/dev/bce/if_bce.c
@@ -455,10 +455,6 @@ static device_method_t bce_methods[] = {
 /*	DEVMETHOD(device_resume,	bce_resume),        */
 /*	DEVMETHOD(device_quiesce,	bce_quiesce),       */
 
-	/* Bus interface (bus_if.h) */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* MII interface (miibus_if.h) */
 	DEVMETHOD(miibus_readreg,	bce_miibus_read_reg),
 	DEVMETHOD(miibus_writereg,	bce_miibus_write_reg),
@@ -467,7 +463,7 @@ static device_method_t bce_methods[] = {
 /*	DEVMETHOD(miibus_linkchg,	bce_miibus_linkchg),   */
 /*	DEVMETHOD(miibus_mediainit,	bce_miibus_mediainit), */
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t bce_driver = {
@@ -1986,6 +1982,7 @@ static void
 bce_miibus_statchg(device_t dev)
 {
 	struct bce_softc *sc;
+	struct ifnet *ifp;
 	struct mii_data *mii;
 	int val;
 
@@ -1993,42 +1990,57 @@ bce_miibus_statchg(device_t dev)
 
 	DBENTER(BCE_VERBOSE_PHY);
 
+	ifp = sc->bce_ifp;
 	mii = device_get_softc(sc->bce_miibus);
+	if (mii == NULL || ifp == NULL ||
+	    (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
+		return;
 
+	sc->bce_link_up = FALSE;
 	val = REG_RD(sc, BCE_EMAC_MODE);
 	val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX |
 	    BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK |
 	    BCE_EMAC_MODE_25G);
 
 	/* Set MII or GMII interface based on the PHY speed. */
-	switch (IFM_SUBTYPE(mii->mii_media_active)) {
-	case IFM_10_T:
-		if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
-			DBPRINT(sc, BCE_INFO_PHY,
-			    "Enabling 10Mb interface.\n");
-			val |= BCE_EMAC_MODE_PORT_MII_10;
+	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
+	    (IFM_ACTIVE | IFM_AVALID)) {
+		switch (IFM_SUBTYPE(mii->mii_media_active)) {
+		case IFM_10_T:
+			if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
+				DBPRINT(sc, BCE_INFO_PHY,
+				    "Enabling 10Mb interface.\n");
+				val |= BCE_EMAC_MODE_PORT_MII_10;
+				sc->bce_link_up = TRUE;
+				break;
+			}
+			/* FALLTHROUGH */
+		case IFM_100_TX:
+			DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n");
+			val |= BCE_EMAC_MODE_PORT_MII;
+			sc->bce_link_up = TRUE;
+			break;
+		case IFM_2500_SX:
+			DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n");
+			val |= BCE_EMAC_MODE_25G;
+			/* FALLTHROUGH */
+		case IFM_1000_T:
+		case IFM_1000_SX:
+			DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n");
+			val |= BCE_EMAC_MODE_PORT_GMII;
+			sc->bce_link_up = TRUE;
+			if (bce_verbose || bootverbose)
+				BCE_PRINTF("Gigabit link up!\n");
+			break;
+		default:
+			DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed.\n");
 			break;
 		}
-		/* fall-through */
-	case IFM_100_TX:
-		DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n");
-		val |= BCE_EMAC_MODE_PORT_MII;
-		break;
-	case IFM_2500_SX:
-		DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n");
-		val |= BCE_EMAC_MODE_25G;
-		/* fall-through */
-	case IFM_1000_T:
-	case IFM_1000_SX:
-		DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n");
-		val |= BCE_EMAC_MODE_PORT_GMII;
-		break;
-	default:
-		DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling "
-		    "default GMII interface.\n");
-		val |= BCE_EMAC_MODE_PORT_GMII;
 	}
 
+	if (sc->bce_link_up == FALSE)
+		return;
+
 	/* Set half or full duplex based on PHY settings. */
 	if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) {
 		DBPRINT(sc, BCE_INFO_PHY,
@@ -2040,7 +2052,7 @@ bce_miibus_statchg(device_t dev)
 
 	REG_WR(sc, BCE_EMAC_MODE, val);
 
- 	if ((mii->mii_media_active & IFM_ETH_RXPAUSE) != 0) {
+	if ((mii->mii_media_active & IFM_ETH_RXPAUSE) != 0) {
 		DBPRINT(sc, BCE_INFO_PHY,
 		    "%s(): Enabling RX flow control.\n", __FUNCTION__);
 		BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
@@ -2050,7 +2062,7 @@ bce_miibus_statchg(device_t dev)
 		BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
 	}
 
- 	if ((mii->mii_media_active & IFM_ETH_TXPAUSE) != 0) {
+	if ((mii->mii_media_active & IFM_ETH_TXPAUSE) != 0) {
 		DBPRINT(sc, BCE_INFO_PHY,
 		    "%s(): Enabling TX flow control.\n", __FUNCTION__);
 		BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
@@ -6210,15 +6222,11 @@ bce_phy_intr(struct bce_softc *sc)
 			DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n",
 			    __FUNCTION__);
 		}
-
 		/*
-		 * Assume link is down and allow
-		 * tick routine to update the state
-		 * based on the actual media state.
+		 * Link state changed, allow tick routine to update
+		 * the state baased on actual media state.
 		 */
-		sc->bce_link_up = FALSE;
-		callout_stop(&sc->bce_tick_callout);
-		bce_tick(sc);
+		sc->bce_link_tick = TRUE;
 	}
 
 	/* Acknowledge the link change interrupt. */
@@ -6902,12 +6910,13 @@ bce_init_locked(struct bce_softc *sc)
 	/* Enable host interrupts. */
 	bce_enable_intr(sc, 1);
 
-	bce_ifmedia_upd_locked(ifp);
-
 	/* Let the OS know the driver is up and running. */
 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 
+	sc->bce_link_tick = TRUE;
+	bce_ifmedia_upd_locked(ifp);
+
 	callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
 
 bce_init_locked_exit:
@@ -8203,31 +8212,19 @@ bce_tick(void *xsc)
 	bce_watchdog(sc);
 
 	/* If link is up already up then we're done. */
-	if (sc->bce_link_up == TRUE)
+	if (sc->bce_link_tick == FALSE && sc->bce_link_up == TRUE)
 		goto bce_tick_exit;
 
 	/* Link is down.  Check what the PHY's doing. */
 	mii = device_get_softc(sc->bce_miibus);
 	mii_tick(mii);
 
-	/* Check if the link has come up. */
-	if ((mii->mii_media_status & IFM_ACTIVE) &&
-	    (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) {
+	sc->bce_link_tick = FALSE;
+	/* Now that link is up, handle any outstanding TX traffic. */
+	if (sc->bce_link_up == TRUE && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
 		DBPRINT(sc, BCE_VERBOSE_MISC,
-		    "%s(): Link up!\n", __FUNCTION__);
-		sc->bce_link_up = TRUE;
-		if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
-		    IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX ||
-		    IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) &&
-		    (bce_verbose || bootverbose))
-			BCE_PRINTF("Gigabit link up!\n");
-
-		/* Now that link is up, handle any outstanding TX traffic. */
-		if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
-			DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found "
-			    "pending TX traffic.\n", __FUNCTION__);
-			bce_start_locked(ifp);
-		}
+		    "%s(): Found pending TX traffic.\n", __FUNCTION__);
+		bce_start_locked(ifp);
 	}
 
 bce_tick_exit:
diff --git a/sys/dev/bce/if_bcereg.h b/sys/dev/bce/if_bcereg.h
index f74c4d2..65a3424 100644
--- a/sys/dev/bce/if_bcereg.h
+++ b/sys/dev/bce/if_bcereg.h
@@ -6560,6 +6560,7 @@ struct bce_softc
 	u16			pg_prod;
 	u16			pg_cons;
 
+	int			bce_link_tick;
 	int			bce_link_up;
 	struct		callout bce_tick_callout;
 	struct		callout bce_pulse_callout;
diff --git a/sys/dev/bfe/if_bfe.c b/sys/dev/bfe/if_bfe.c
index 7f970f4..6dd33cd 100644
--- a/sys/dev/bfe/if_bfe.c
+++ b/sys/dev/bfe/if_bfe.c
@@ -137,16 +137,12 @@ static device_method_t bfe_methods[] = {
 	DEVMETHOD(device_suspend,	bfe_suspend),
 	DEVMETHOD(device_resume,	bfe_resume),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	bfe_miibus_readreg),
 	DEVMETHOD(miibus_writereg,	bfe_miibus_writereg),
 	DEVMETHOD(miibus_statchg,	bfe_miibus_statchg),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t bfe_driver = {
diff --git a/sys/dev/bge/if_bge.c b/sys/dev/bge/if_bge.c
index f7d1730..ea477fd 100644
--- a/sys/dev/bge/if_bge.c
+++ b/sys/dev/bge/if_bge.c
@@ -493,16 +493,12 @@ static device_method_t bge_methods[] = {
 	DEVMETHOD(device_suspend,	bge_suspend),
 	DEVMETHOD(device_resume,	bge_resume),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	bge_miibus_readreg),
 	DEVMETHOD(miibus_writereg,	bge_miibus_writereg),
 	DEVMETHOD(miibus_statchg,	bge_miibus_statchg),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t bge_driver = {
@@ -2084,9 +2080,15 @@ bge_blockinit(struct bge_softc *sc)
 			val |= BGE_RDMAMODE_TSO6_ENABLE;
 	}
 
-	if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
+	if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
 		val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
 			BGE_RDMAMODE_H2BNC_VLAN_DET;
+		/*
+		 * Allow multiple outstanding read requests from
+		 * non-LSO read DMA engine.
+		 */
+		val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
+	}
 
 	if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
 	    sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
@@ -2116,12 +2118,20 @@ bge_blockinit(struct bge_softc *sc)
 		    BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
 	}
 
-	if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
-	    sc->bge_asicrev == BGE_ASICREV_BCM5720) {
+	if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
 		CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
 		    CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
+	} else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
+		/*
+		 * Allow 4KB burst length reads for non-LSO frames.
+		 * Enable 512B burst length reads for buffer descriptors.
+		 */
+		CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
+		    CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
+		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
+		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
 	}
 
 	CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
@@ -2348,6 +2358,8 @@ bge_dma_free(struct bge_softc *sc)
 
 	if (sc->bge_cdata.bge_rx_mtag)
 		bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
+	if (sc->bge_cdata.bge_mtag_jumbo)
+		bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo);
 	if (sc->bge_cdata.bge_tx_mtag)
 		bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
 
diff --git a/sys/dev/bge/if_bgereg.h b/sys/dev/bge/if_bgereg.h
index 3ba4176..ccb2c6d 100644
--- a/sys/dev/bge/if_bgereg.h
+++ b/sys/dev/bge/if_bgereg.h
@@ -1573,6 +1573,7 @@
 #define	BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK	0x000FF000
 #define	BGE_RDMA_RSRVCTRL_TXMRGN_MASK	0xFFE00000
 
+#define	BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512	0x00020000
 #define	BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K	0x00030000
 #define	BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K	0x000C0000
 
diff --git a/sys/dev/bm/if_bm.c b/sys/dev/bm/if_bm.c
index c478e7b..872da6d 100644
--- a/sys/dev/bm/if_bm.c
+++ b/sys/dev/bm/if_bm.c
@@ -135,15 +135,12 @@ static device_method_t bm_methods[] = {
 	DEVMETHOD(device_detach,	bm_detach),
 	DEVMETHOD(device_shutdown,	bm_shutdown),
 
-	/* bus interface, for miibus */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	bm_miibus_readreg),
 	DEVMETHOD(miibus_writereg,	bm_miibus_writereg),
 	DEVMETHOD(miibus_statchg,	bm_miibus_statchg),
-	{ 0, 0 }
+
+	DEVMETHOD_END
 };
 
 static driver_t bm_macio_driver = {
diff --git a/sys/dev/bwi/if_bwi.c b/sys/dev/bwi/if_bwi.c
index b155507..8db43b3 100644
--- a/sys/dev/bwi/if_bwi.c
+++ b/sys/dev/bwi/if_bwi.c
@@ -96,9 +96,9 @@ struct bwi_myaddr_bssid {
 } __packed;
 
 static struct ieee80211vap *bwi_vap_create(struct ieee80211com *,
-		   const char [IFNAMSIZ], int, int, int,
-		   const uint8_t [IEEE80211_ADDR_LEN],
-		   const uint8_t [IEEE80211_ADDR_LEN]);
+		    const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
+		    const uint8_t [IEEE80211_ADDR_LEN],
+		    const uint8_t [IEEE80211_ADDR_LEN]);
 static void	bwi_vap_delete(struct ieee80211vap *);
 static void	bwi_init(void *);
 static int	bwi_ioctl(struct ifnet *, u_long, caddr_t);
@@ -118,7 +118,7 @@ static void	bwi_calibrate(void *);
 
 static int	bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *);
 static int	bwi_calc_noise(struct bwi_softc *);
-static __inline uint8_t bwi_plcp2rate(uint32_t, enum ieee80211_phymode);
+static __inline uint8_t bwi_plcp2rate(uint32_t, enum ieee80211_phytype);
 static void	bwi_rx_radiotap(struct bwi_softc *, struct mbuf *,
 			struct bwi_rxbuf_hdr *, const void *, int, int, int);
 
@@ -591,10 +591,10 @@ bwi_detach(struct bwi_softc *sc)
 }
 
 static struct ieee80211vap *
-bwi_vap_create(struct ieee80211com *ic,
-	const char name[IFNAMSIZ], int unit, int opmode, int flags,
-	const uint8_t bssid[IEEE80211_ADDR_LEN],
-	const uint8_t mac[IEEE80211_ADDR_LEN])
+bwi_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
+    enum ieee80211_opmode opmode, int flags,
+    const uint8_t bssid[IEEE80211_ADDR_LEN],
+    const uint8_t mac[IEEE80211_ADDR_LEN])
 {
 	struct bwi_vap *bvp;
 	struct ieee80211vap *vap;
@@ -2667,9 +2667,9 @@ bwi_rxeof(struct bwi_softc *sc, int end_idx)
 		m_adj(m, sizeof(*hdr) + wh_ofs);
 
 		if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM)
-			rate = bwi_plcp2rate(plcp, IEEE80211_MODE_11G);
+			rate = bwi_plcp2rate(plcp, IEEE80211_T_OFDM);
 		else
-			rate = bwi_plcp2rate(plcp, IEEE80211_MODE_11B);
+			rate = bwi_plcp2rate(plcp, IEEE80211_T_CCK);
 
 		/* RX radio tap */
 		if (ieee80211_radiotap_active(ic))
@@ -3801,10 +3801,10 @@ bwi_calc_noise(struct bwi_softc *sc)
 }
 
 static __inline uint8_t
-bwi_plcp2rate(const uint32_t plcp0, enum ieee80211_phymode phymode)
+bwi_plcp2rate(const uint32_t plcp0, enum ieee80211_phytype type)
 {
-       uint32_t plcp = le32toh(plcp0) & IEEE80211_OFDM_PLCP_RATE_MASK;
-	return (ieee80211_plcp2rate(plcp, phymode));
+	uint32_t plcp = le32toh(plcp0) & IEEE80211_OFDM_PLCP_RATE_MASK;
+	return (ieee80211_plcp2rate(plcp, type));
 }
 
 static void
diff --git a/sys/dev/bwn/if_bwn.c b/sys/dev/bwn/if_bwn.c
index af10ace..b2cd527 100644
--- a/sys/dev/bwn/if_bwn.c
+++ b/sys/dev/bwn/if_bwn.c
@@ -193,8 +193,8 @@ static void	bwn_scan_start(struct ieee80211com *);
 static void	bwn_scan_end(struct ieee80211com *);
 static void	bwn_set_channel(struct ieee80211com *);
 static struct ieee80211vap *bwn_vap_create(struct ieee80211com *,
-		    const char [IFNAMSIZ], int, int,
-		    int, const uint8_t [IEEE80211_ADDR_LEN],
+		    const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
+		    const uint8_t [IEEE80211_ADDR_LEN],
 		    const uint8_t [IEEE80211_ADDR_LEN]);
 static void	bwn_vap_delete(struct ieee80211vap *);
 static void	bwn_stop(struct bwn_softc *, int);
@@ -2927,10 +2927,10 @@ fail:
 }
 
 static struct ieee80211vap *
-bwn_vap_create(struct ieee80211com *ic,
-	const char name[IFNAMSIZ], int unit, int opmode, int flags,
-	const uint8_t bssid[IEEE80211_ADDR_LEN],
-	const uint8_t mac0[IEEE80211_ADDR_LEN])
+bwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
+    enum ieee80211_opmode opmode, int flags,
+    const uint8_t bssid[IEEE80211_ADDR_LEN],
+    const uint8_t mac0[IEEE80211_ADDR_LEN])
 {
 	struct ifnet *ifp = ic->ic_ifp;
 	struct bwn_softc *sc = ifp->if_softc;
@@ -14226,7 +14226,7 @@ static device_method_t bwn_methods[] = {
 	DEVMETHOD(device_detach,	bwn_detach),
 	DEVMETHOD(device_suspend,	bwn_suspend),
 	DEVMETHOD(device_resume,	bwn_resume),
-	KOBJMETHOD_END
+	DEVMETHOD_END
 };
 static driver_t bwn_driver = {
 	"bwn",
diff --git a/sys/dev/bwn/if_bwnvar.h b/sys/dev/bwn/if_bwnvar.h
index 461587d..f6647b0 100644
--- a/sys/dev/bwn/if_bwnvar.h
+++ b/sys/dev/bwn/if_bwnvar.h
@@ -714,7 +714,7 @@ struct bwn_txhdr {
 			uint16_t	tx_status;
 			struct bwn_plcp6	rts_plcp;
 			uint8_t		rts_frame[16];
-			uint8_t		pad1[2];;
+			uint8_t		pad1[2];
 			struct bwn_plcp6	plcp;
 		} __packed old;
 		/* format > r410 */
diff --git a/sys/dev/bxe/bxe_reg.h b/sys/dev/bxe/bxe_reg.h
index e561ce6..df2e707 100644
--- a/sys/dev/bxe/bxe_reg.h
+++ b/sys/dev/bxe/bxe_reg.h
@@ -1594,7 +1594,7 @@
 /*
  * [RW 1] Setting this bit enables a timer in the GRC block to timeout an
  * access that does not finish within
- * ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
+ * ~misc_registers_grc_timeout_val.grc_timeout_val cycles. When this bit is
  * cleared; this timeout is disabled. If this timeout occurs; the GRC shall
  * assert it attention output.
  */
diff --git a/sys/dev/bxe/if_bxe.c b/sys/dev/bxe/if_bxe.c
index 9957359..6ccd045 100644
--- a/sys/dev/bxe/if_bxe.c
+++ b/sys/dev/bxe/if_bxe.c
@@ -400,11 +400,7 @@ static device_method_t bxe_methods[] = {
 	DEVMETHOD(device_detach,	bxe_detach),
 	DEVMETHOD(device_shutdown,	bxe_shutdown),
 
-	/* Bus interface (bus_if.h) */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
-	KOBJMETHOD_END
+	DEVMETHOD_END
 };
 
 
diff --git a/sys/dev/cas/if_cas.c b/sys/dev/cas/if_cas.c
index 858c8bc..894f466 100644
--- a/sys/dev/cas/if_cas.c
+++ b/sys/dev/cas/if_cas.c
@@ -2600,16 +2600,12 @@ static device_method_t cas_pci_methods[] = {
 	/* Use the suspend handler here, it is all that is required. */
 	DEVMETHOD(device_shutdown,	cas_pci_suspend),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	cas_mii_readreg),
 	DEVMETHOD(miibus_writereg,	cas_mii_writereg),
 	DEVMETHOD(miibus_statchg,	cas_mii_statchg),
 
-	KOBJMETHOD_END
+	DEVMETHOD_END
 };
 
 static driver_t cas_pci_driver = {
diff --git a/sys/dev/ce/if_ce.c b/sys/dev/ce/if_ce.c
index d151b42..7fb208a 100644
--- a/sys/dev/ce/if_ce.c
+++ b/sys/dev/ce/if_ce.c
@@ -1313,9 +1313,11 @@ static int ce_ioctl (struct cdev *dev, u_long cmd, caddr_t data, int flag, struc
 			IFP2SP(d->ifp)->pp_flags &= ~(PP_FR);
 			IFP2SP(d->ifp)->pp_flags |= PP_KEEPALIVE;
 			d->ifp->if_flags |= PP_CISCO;
-		} else if (! strcmp ("fr", (char*)data) && PP_FR) {
+#if PP_FR != 0
+		} else if (! strcmp ("fr", (char*)data)) {
 			d->ifp->if_flags &= ~(PP_CISCO);
 			IFP2SP(d->ifp)->pp_flags |= PP_FR | PP_KEEPALIVE;
+#endif
 		} else if (! strcmp ("ppp", (char*)data)) {
 			IFP2SP(d->ifp)->pp_flags &= ~PP_FR;
 			IFP2SP(d->ifp)->pp_flags &= ~PP_KEEPALIVE;
diff --git a/sys/dev/cesa/cesa.c b/sys/dev/cesa/cesa.c
index 54bb8e3..5d67fc6 100644
--- a/sys/dev/cesa/cesa.c
+++ b/sys/dev/cesa/cesa.c
@@ -93,16 +93,12 @@ static device_method_t cesa_methods[] = {
 	DEVMETHOD(device_attach,	cesa_attach),
 	DEVMETHOD(device_detach,	cesa_detach),
 
-	/* Bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* Crypto device methods */
 	DEVMETHOD(cryptodev_newsession,	cesa_newsession),
 	DEVMETHOD(cryptodev_freesession,cesa_freesession),
 	DEVMETHOD(cryptodev_process,	cesa_process),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t cesa_driver = {
diff --git a/sys/dev/cfe/cfe_console.c b/sys/dev/cfe/cfe_console.c
index 5a6b0a2..485fd08 100644
--- a/sys/dev/cfe/cfe_console.c
+++ b/sys/dev/cfe/cfe_console.c
@@ -76,6 +76,8 @@ static cn_init_t	cfe_cninit;
 static cn_term_t	cfe_cnterm;
 static cn_getc_t	cfe_cngetc;
 static cn_putc_t	cfe_cnputc;
+static cn_grab_t	cfe_cngrab;
+static cn_ungrab_t	cfe_cnungrab;
 
 CONSOLE_DRIVER(cfe);
 
@@ -183,6 +185,18 @@ cfe_cnterm(struct consdev *cp)
 
 }
 
+static void
+cfe_cngrab(struct consdev *cp)
+{
+
+}
+
+static void
+cfe_cnungrab(struct consdev *cp)
+{
+
+}
+
 static int
 cfe_cngetc(struct consdev *cp)
 {
diff --git a/sys/dev/cm/smc90cx6.c b/sys/dev/cm/smc90cx6.c
index 719e468..eb89675 100644
--- a/sys/dev/cm/smc90cx6.c
+++ b/sys/dev/cm/smc90cx6.c
@@ -596,7 +596,7 @@ cleanup:
 	}
 }
 
-__inline static void
+static inline void
 cm_tint_locked(sc, isr)
 	struct cm_softc *sc;
 	int isr;
diff --git a/sys/dev/cp/if_cp.c b/sys/dev/cp/if_cp.c
index e640230..49e329e 100644
--- a/sys/dev/cp/if_cp.c
+++ b/sys/dev/cp/if_cp.c
@@ -1052,9 +1052,11 @@ static int cp_ioctl (struct cdev *dev, u_long cmd, caddr_t data, int flag, struc
 			IFP2SP(d->ifp)->pp_flags &= ~(PP_FR);
 			IFP2SP(d->ifp)->pp_flags |= PP_KEEPALIVE;
 			d->ifp->if_flags |= PP_CISCO;
-		} else if (! strcmp ("fr", (char*)data) && PP_FR) {
+#if PP_FR != 0
+		} else if (! strcmp ("fr", (char*)data)) {
 			d->ifp->if_flags &= ~(PP_CISCO);
 			IFP2SP(d->ifp)->pp_flags |= PP_FR | PP_KEEPALIVE;
+#endif
 		} else if (! strcmp ("ppp", (char*)data)) {
 			IFP2SP(d->ifp)->pp_flags &= ~PP_FR;
 			IFP2SP(d->ifp)->pp_flags &= ~PP_KEEPALIVE;
diff --git a/sys/dev/cpuctl/cpuctl.c b/sys/dev/cpuctl/cpuctl.c
index c3a2434..1553457 100644
--- a/sys/dev/cpuctl/cpuctl.c
+++ b/sys/dev/cpuctl/cpuctl.c
@@ -74,6 +74,8 @@ static int cpuctl_do_update(int cpu, cpuctl_update_args_t *data,
 static int update_intel(int cpu, cpuctl_update_args_t *args,
     struct thread *td);
 static int update_amd(int cpu, cpuctl_update_args_t *args, struct thread *td);
+static int update_via(int cpu, cpuctl_update_args_t *args,
+    struct thread *td);
 
 static struct cdev **cpuctl_devs;
 static MALLOC_DEFINE(M_CPUCTL, "cpuctl", "CPUCTL buffer");
@@ -281,8 +283,10 @@ cpuctl_do_update(int cpu, cpuctl_update_args_t *data, struct thread *td)
 	vendor[12] = '\0';
 	if (strncmp(vendor, INTEL_VENDOR_ID, sizeof(INTEL_VENDOR_ID)) == 0)
 		ret = update_intel(cpu, data, td);
-	else if(strncmp(vendor, INTEL_VENDOR_ID, sizeof(AMD_VENDOR_ID)) == 0)
+	else if(strncmp(vendor, AMD_VENDOR_ID, sizeof(AMD_VENDOR_ID)) == 0)
 		ret = update_amd(cpu, data, td);
+	else if(strncmp(vendor, CENTAUR_VENDOR_ID, sizeof(CENTAUR_VENDOR_ID)) == 0)
+		ret = update_via(cpu, data, td);
 	else
 		ret = ENXIO;
 	return (ret);
@@ -402,6 +406,81 @@ fail:
 	return (ret);
 }
 
+static int
+update_via(int cpu, cpuctl_update_args_t *args, struct thread *td)
+{
+	void *ptr = NULL;
+	uint64_t rev0, rev1, res;
+	uint32_t tmp[4];
+	int is_bound = 0;
+	int oldcpu;
+	int ret;
+
+	if (args->size == 0 || args->data == NULL) {
+		DPRINTF("[cpuctl,%d]: zero-sized firmware image", __LINE__);
+		return (EINVAL);
+	}
+	if (args->size > UCODE_SIZE_MAX) {
+		DPRINTF("[cpuctl,%d]: firmware image too large", __LINE__);
+		return (EINVAL);
+	}
+
+	/*
+	 * 4 byte alignment required.
+	 */
+	ptr = malloc(args->size + 16, M_CPUCTL, M_WAITOK);
+	ptr = (void *)(16 + ((intptr_t)ptr & ~0xf));
+	if (copyin(args->data, ptr, args->size) != 0) {
+		DPRINTF("[cpuctl,%d]: copyin %p->%p of %zd bytes failed",
+		    __LINE__, args->data, ptr, args->size);
+		ret = EFAULT;
+		goto fail;
+	}
+	oldcpu = td->td_oncpu;
+	is_bound = cpu_sched_is_bound(td);
+	set_cpu(cpu, td);
+	critical_enter();
+	rdmsr_safe(MSR_BIOS_SIGN, &rev0); /* Get current micorcode revision. */
+
+	/*
+	 * Perform update.
+	 */
+	wrmsr_safe(MSR_BIOS_UPDT_TRIG, (uintptr_t)(ptr));
+	do_cpuid(1, tmp);
+
+	/*
+	 * Result are in low byte of MSR FCR5:
+	 * 0x00: No update has been attempted since RESET.
+	 * 0x01: The last attempted update was successful.
+	 * 0x02: The last attempted update was unsuccessful due to a bad
+	 *       environment. No update was loaded and any preexisting
+	 *       patches are still active.
+	 * 0x03: The last attempted update was not applicable to this processor.
+	 *       No update was loaded and any preexisting patches are still
+	 *       active.
+	 * 0x04: The last attempted update was not successful due to an invalid
+	 *       update data block. No update was loaded and any preexisting
+	 *       patches are still active
+	 */
+	rdmsr_safe(0x1205, &res);
+	res &= 0xff;
+	critical_exit();
+	rdmsr_safe(MSR_BIOS_SIGN, &rev1); /* Get new microcode revision. */
+	restore_cpu(oldcpu, is_bound, td);
+
+	DPRINTF("[cpu,%d]: rev0=%x rev1=%x res=%x\n", __LINE__,
+	    (unsigned)(rev0 >> 32), (unsigned)(rev1 >> 32), (unsigned)res);
+
+	if (res != 0x01)
+		ret = EINVAL;
+	else
+		ret = 0;
+fail:
+	if (ptr != NULL)
+		contigfree(ptr, args->size, M_CPUCTL);
+	return (ret);
+}
+
 int
 cpuctl_open(struct cdev *dev, int flags, int fmt __unused, struct thread *td)
 {
diff --git a/sys/dev/cxgb/common/cxgb_aq100x.c b/sys/dev/cxgb/common/cxgb_aq100x.c
index 46f07ca..d36d07a 100644
--- a/sys/dev/cxgb/common/cxgb_aq100x.c
+++ b/sys/dev/cxgb/common/cxgb_aq100x.c
@@ -232,7 +232,7 @@ aq100x_power_down(struct cphy *phy, int off)
 	err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR, BMCR_PDOWN,
 	    off ? BMCR_PDOWN : 0);
 	if (err || off)
-		return (v);
+		return (err);
 
 	msleep(300);
 	do {
diff --git a/sys/dev/cxgb/cxgb_main.c b/sys/dev/cxgb/cxgb_main.c
index ae32221..c5d46a0 100644
--- a/sys/dev/cxgb/cxgb_main.c
+++ b/sys/dev/cxgb/cxgb_main.c
@@ -129,11 +129,7 @@ static device_method_t cxgb_controller_methods[] = {
 	DEVMETHOD(device_attach,	cxgb_controller_attach),
 	DEVMETHOD(device_detach,	cxgb_controller_detach),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t cxgb_controller_driver = {
diff --git a/sys/dev/cxgbe/adapter.h b/sys/dev/cxgbe/adapter.h
index 8624fc1..7e56932 100644
--- a/sys/dev/cxgbe/adapter.h
+++ b/sys/dev/cxgbe/adapter.h
@@ -31,6 +31,7 @@
 #ifndef __T4_ADAPTER_H__
 #define __T4_ADAPTER_H__
 
+#include <sys/kernel.h>
 #include <sys/bus.h>
 #include <sys/rman.h>
 #include <sys/types.h>
@@ -46,8 +47,9 @@
 #include <netinet/tcp_lro.h>
 
 #include "offload.h"
-#include "common/t4fw_interface.h"
+#include "firmware/t4fw_interface.h"
 
+#define T4_CFGNAME "t4fw_cfg"
 #define T4_FWNAME "t4fw"
 
 MALLOC_DECLARE(M_CXGBE);
@@ -110,25 +112,21 @@ enum {
 	FW_IQ_QSIZE = 256,
 	FW_IQ_ESIZE = 64,	/* At least 64 mandated by the firmware spec */
 
-	INTR_IQ_QSIZE = 64,
-	INTR_IQ_ESIZE = 64,	/* Handles some CPLs too, do not reduce */
-
-	CTRL_EQ_QSIZE = 128,
-	CTRL_EQ_ESIZE = 64,
-
 	RX_IQ_QSIZE = 1024,
 	RX_IQ_ESIZE = 64,	/* At least 64 so CPL_RX_PKT will fit */
 
-	RX_FL_ESIZE = 64,	/* 8 64bit addresses */
+	EQ_ESIZE = 64,		/* All egress queues use this entry size */
 
+	RX_FL_ESIZE = EQ_ESIZE,	/* 8 64bit addresses */
 #if MJUMPAGESIZE != MCLBYTES
 	FL_BUF_SIZES = 4,	/* cluster, jumbop, jumbo9k, jumbo16k */
 #else
 	FL_BUF_SIZES = 3,	/* cluster, jumbo9k, jumbo16k */
 #endif
 
+	CTRL_EQ_QSIZE = 128,
+
 	TX_EQ_QSIZE = 1024,
-	TX_EQ_ESIZE = 64,
 	TX_SGL_SEGS = 36,
 	TX_WR_FLITS = SGE_MAX_WR_LEN / 8
 };
@@ -144,13 +142,16 @@ enum {
 	/* adapter flags */
 	FULL_INIT_DONE	= (1 << 0),
 	FW_OK		= (1 << 1),
-	INTR_SHARED	= (1 << 2),	/* one set of intrq's for all ports */
+	INTR_DIRECT	= (1 << 2),	/* direct interrupts for everything */
+	MASTER_PF	= (1 << 3),
+	ADAP_SYSCTL_CTX	= (1 << 4),
 
 	CXGBE_BUSY	= (1 << 9),
 
 	/* port flags */
 	DOOMED		= (1 << 0),
-	VI_ENABLED	= (1 << 1),
+	PORT_INIT_DONE	= (1 << 1),
+	PORT_SYSCTL_CTX	= (1 << 2),
 };
 
 #define IS_DOOMED(pi)	(pi->flags & DOOMED)
@@ -186,6 +187,12 @@ struct port_info {
 	int first_txq;	/* index of first tx queue */
 	int nrxq;	/* # of rx queues */
 	int first_rxq;	/* index of first rx queue */
+#ifndef TCP_OFFLOAD_DISABLE
+	int nofldtxq;		/* # of offload tx queues */
+	int first_ofld_txq;	/* index of first offload tx queue */
+	int nofldrxq;		/* # of offload rx queues */
+	int first_ofld_rxq;	/* index of first offload rx queue */
+#endif
 	int tmr_idx;
 	int pktc_idx;
 	int qsize_rxq;
@@ -194,11 +201,8 @@ struct port_info {
 	struct link_config link_cfg;
 	struct port_stats stats;
 
-	struct taskqueue *tq;
 	struct callout tick;
-	struct sysctl_ctx_list ctx;	/* lives from ifconfig up to down */
-	struct sysctl_oid *oid_rxq;
-	struct sysctl_oid *oid_txq;
+	struct sysctl_ctx_list ctx;	/* from ifconfig up to driver detach */
 
 	uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
 };
@@ -222,17 +226,26 @@ struct tx_map {
 	bus_dmamap_t map;
 };
 
+/* DMA maps used for tx */
+struct tx_maps {
+	struct tx_map *maps;
+	uint32_t map_total;	/* # of DMA maps */
+	uint32_t map_pidx;	/* next map to be used */
+	uint32_t map_cidx;	/* reclaimed up to this index */
+	uint32_t map_avail;	/* # of available maps */
+};
+
 struct tx_sdesc {
 	uint8_t desc_used;	/* # of hardware descriptors used by the WR */
 	uint8_t credits;	/* NIC txq: # of frames sent out in the WR */
 };
 
-typedef void (iq_intr_handler_t)(void *);
-
 enum {
 	/* iq flags */
-	IQ_ALLOCATED	= (1 << 1),	/* firmware resources allocated */
-	IQ_STARTED	= (1 << 2),	/* started */
+	IQ_ALLOCATED	= (1 << 0),	/* firmware resources allocated */
+	IQ_HAS_FL	= (1 << 1),	/* iq associated with a freelist */
+	IQ_INTR		= (1 << 2),	/* iq takes direct interrupt */
+	IQ_LRO_ENABLED	= (1 << 3),	/* iq is an eth rxq with LRO enabled */
 
 	/* iq state */
 	IQS_DISABLED	= 0,
@@ -252,26 +265,35 @@ struct sge_iq {
 	uint16_t abs_id;	/* absolute SGE id for the iq */
 	int8_t   intr_pktc_idx;	/* packet count threshold index */
 	int8_t   pad0;
-	iq_intr_handler_t *handler;
 	__be64  *desc;		/* KVA of descriptor ring */
 
-	volatile uint32_t state;
+	volatile int state;
 	struct adapter *adapter;
 	const __be64 *cdesc;	/* current descriptor */
 	uint8_t  gen;		/* generation bit */
 	uint8_t  intr_params;	/* interrupt holdoff parameters */
-	uint8_t  intr_next;	/* holdoff for next interrupt */
+	uint8_t  intr_next;	/* XXX: holdoff for next interrupt */
 	uint8_t  esize;		/* size (bytes) of each entry in the queue */
 	uint16_t qsize;		/* size (# of entries) of the queue */
 	uint16_t cidx;		/* consumer index */
-	uint16_t cntxt_id;	/* SGE context id  for the iq */
+	uint16_t cntxt_id;	/* SGE context id for the iq */
+
+	STAILQ_ENTRY(sge_iq) link;
 };
 
 enum {
+	EQ_CTRL		= 1,
+	EQ_ETH		= 2,
+#ifndef TCP_OFFLOAD_DISABLE
+	EQ_OFLD		= 3,
+#endif
+
 	/* eq flags */
-	EQ_ALLOCATED	= (1 << 1),	/* firmware resources allocated */
-	EQ_STARTED	= (1 << 2),	/* started */
-	EQ_CRFLUSHED	= (1 << 3),	/* expecting an update from SGE */
+	EQ_TYPEMASK	= 7,		/* 3 lsbits hold the type */
+	EQ_ALLOCATED	= (1 << 3),	/* firmware resources allocated */
+	EQ_DOOMED	= (1 << 4),	/* about to be destroyed */
+	EQ_CRFLUSHED	= (1 << 5),	/* expecting an update from SGE */
+	EQ_STALLED	= (1 << 6),	/* out of hw descriptors or dmamaps */
 };
 
 /*
@@ -281,10 +303,11 @@ enum {
  * consumes them) but it's special enough to have its own struct (see sge_fl).
  */
 struct sge_eq {
+	unsigned int flags;	/* MUST be first */
+	unsigned int cntxt_id;	/* SGE context id for the eq */
 	bus_dma_tag_t desc_tag;
 	bus_dmamap_t desc_map;
 	char lockname[16];
-	unsigned int flags;
 	struct mtx eq_lock;
 
 	struct tx_desc *desc;	/* KVA of descriptor ring */
@@ -297,9 +320,24 @@ struct sge_eq {
 	uint16_t pidx;		/* producer idx (desc idx) */
 	uint16_t pending;	/* # of descriptors used since last doorbell */
 	uint16_t iqid;		/* iq that gets egr_update for the eq */
-	unsigned int  cntxt_id;	/* SGE context id for the eq */
+	uint8_t tx_chan;	/* tx channel used by the eq */
+	struct task tx_task;
+	struct callout tx_callout;
+
+	/* stats */
+
+	uint32_t egr_update;	/* # of SGE_EGR_UPDATE notifications for eq */
+	uint32_t unstalled;	/* recovered from stall */
+};
+
+enum {
+	FL_STARVING	= (1 << 0), /* on the adapter's list of starving fl's */
+	FL_DOOMED	= (1 << 1), /* about to be destroyed */
 };
 
+#define FL_RUNNING_LOW(fl)	(fl->cap - fl->needed <= fl->lowat)
+#define FL_NOT_RUNNING_LOW(fl)	(fl->cap - fl->needed >= 2 * fl->lowat)
+
 struct sge_fl {
 	bus_dma_tag_t desc_tag;
 	bus_dmamap_t desc_map;
@@ -307,6 +345,7 @@ struct sge_fl {
 	uint8_t tag_idx;
 	struct mtx fl_lock;
 	char lockname[16];
+	int flags;
 
 	__be64 *desc;		/* KVA of descriptor ring, ptr to addresses */
 	bus_addr_t ba;		/* bus address of descriptor ring */
@@ -317,8 +356,10 @@ struct sge_fl {
 	uint32_t cidx;		/* consumer idx (buffer idx, NOT hw desc idx) */
 	uint32_t pidx;		/* producer idx (buffer idx, NOT hw desc idx) */
 	uint32_t needed;	/* # of buffers needed to fill up fl. */
+	uint32_t lowat;		/* # of buffers <= this means fl needs help */
 	uint32_t pending;	/* # of bufs allocated since last doorbell */
 	unsigned int dmamap_failed;
+	TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
 };
 
 /* txq: SGE egress queue + what's needed for Ethernet NIC */
@@ -330,14 +371,8 @@ struct sge_txq {
 	struct buf_ring *br;	/* tx buffer ring */
 	struct tx_sdesc *sdesc;	/* KVA of software descriptor ring */
 	struct mbuf *m;		/* held up due to temporary resource shortage */
-	struct task resume_tx;
 
-	/* DMA maps used for tx */
-	struct tx_map *maps;
-	uint32_t map_total;	/* # of DMA maps */
-	uint32_t map_pidx;	/* next map to be used */
-	uint32_t map_cidx;	/* reclaimed up to this index */
-	uint32_t map_avail;	/* # of available maps */
+	struct tx_maps txmaps;
 
 	/* stats for common events first */
 
@@ -354,20 +389,14 @@ struct sge_txq {
 
 	uint32_t no_dmamap;	/* no DMA map to load the mbuf */
 	uint32_t no_desc;	/* out of hardware descriptors */
-	uint32_t egr_update;	/* # of SGE_EGR_UPDATE notifications for txq */
 } __aligned(CACHE_LINE_SIZE);
 
-enum {
-	RXQ_LRO_ENABLED	= (1 << 0)
-};
-
 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
 struct sge_rxq {
 	struct sge_iq iq;	/* MUST be first */
-	struct sge_fl fl;
+	struct sge_fl fl;	/* MUST follow iq */
 
 	struct ifnet *ifp;	/* the interface this rxq belongs to */
-	unsigned int flags;
 #ifdef INET
 	struct lro_ctrl lro;	/* LRO state */
 #endif
@@ -381,12 +410,28 @@ struct sge_rxq {
 
 } __aligned(CACHE_LINE_SIZE);
 
-/* ctrlq: SGE egress queue + stats for control queue */
-struct sge_ctrlq {
+#ifndef TCP_OFFLOAD_DISABLE
+/* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
+struct sge_ofld_rxq {
+	struct sge_iq iq;	/* MUST be first */
+	struct sge_fl fl;	/* MUST follow iq */
+} __aligned(CACHE_LINE_SIZE);
+#endif
+
+/*
+ * wrq: SGE egress queue that is given prebuilt work requests.  Both the control
+ * and offload tx queues are of this type.
+ */
+struct sge_wrq {
 	struct sge_eq eq;	/* MUST be first */
 
+	struct adapter *adapter;
+	struct mbuf *head;	/* held up due to lack of descriptors */
+	struct mbuf *tail;	/* valid only if head is valid */
+
 	/* stats for common events first */
 
+	uint64_t tx_wrs;	/* # of tx work requests */
 
 	/* stats for not-that-common events */
 
@@ -394,20 +439,28 @@ struct sge_ctrlq {
 } __aligned(CACHE_LINE_SIZE);
 
 struct sge {
-	uint16_t timer_val[SGE_NTIMERS];
-	uint8_t  counter_val[SGE_NCOUNTERS];
+	int timer_val[SGE_NTIMERS];
+	int counter_val[SGE_NCOUNTERS];
 	int fl_starve_threshold;
 
-	int nrxq;	/* total rx queues (all ports and the rest) */
-	int ntxq;	/* total tx queues (all ports and the rest) */
-	int niq;	/* total ingress queues */
-	int neq;	/* total egress queues */
+	int nrxq;	/* total # of Ethernet rx queues */
+	int ntxq;	/* total # of Ethernet tx tx queues */
+#ifndef TCP_OFFLOAD_DISABLE
+	int nofldrxq;	/* total # of TOE rx queues */
+	int nofldtxq;	/* total # of TOE tx queues */
+#endif
+	int niq;	/* total # of ingress queues */
+	int neq;	/* total # of egress queues */
 
 	struct sge_iq fwq;	/* Firmware event queue */
-	struct sge_ctrlq *ctrlq;/* Control queues */
-	struct sge_iq *intrq;	/* Interrupt queues */
+	struct sge_wrq mgmtq;	/* Management queue (control queue) */
+	struct sge_wrq *ctrlq;	/* Control queues */
 	struct sge_txq *txq;	/* NIC tx queues */
 	struct sge_rxq *rxq;	/* NIC rx queues */
+#ifndef TCP_OFFLOAD_DISABLE
+	struct sge_wrq *ofld_txq;	/* TOE tx queues */
+	struct sge_ofld_rxq *ofld_rxq;	/* TOE rx queues */
+#endif
 
 	uint16_t iq_start;
 	int eq_start;
@@ -415,7 +468,12 @@ struct sge {
 	struct sge_eq **eqmap;	/* eq->cntxt_id to eq mapping */
 };
 
+struct rss_header;
+typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
+    struct mbuf *);
+
 struct adapter {
+	SLIST_ENTRY(adapter) link;
 	device_t dev;
 	struct cdev *cdev;
 
@@ -444,27 +502,47 @@ struct adapter {
 
 	struct sge sge;
 
+	struct taskqueue *tq[NCHAN];	/* taskqueues that flush data out */
 	struct port_info *port[MAX_NPORTS];
 	uint8_t chan_map[NCHAN];
+	uint32_t filter_mode;
 
+#ifndef TCP_OFFLOAD_DISABLE
+	struct uld_softc tom;
+	struct tom_tunables tt;
+#endif
 	struct l2t_data *l2t;	/* L2 table */
 	struct tid_info tids;
 
-	int registered_device_map;
 	int open_device_map;
+#ifndef TCP_OFFLOAD_DISABLE
+	int offload_map;
+#endif
 	int flags;
 
 	char fw_version[32];
+	unsigned int cfcsum;
 	struct adapter_params params;
 	struct t4_virt_res vres;
 
-	struct sysctl_ctx_list ctx; /* from first_port_up to last_port_down */
-	struct sysctl_oid *oid_fwq;
-	struct sysctl_oid *oid_ctrlq;
-	struct sysctl_oid *oid_intrq;
+	uint16_t linkcaps;
+	uint16_t niccaps;
+	uint16_t toecaps;
+	uint16_t rdmacaps;
+	uint16_t iscsicaps;
+	uint16_t fcoecaps;
+
+	struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */
 
 	struct mtx sc_lock;
 	char lockname[16];
+
+	/* Starving free lists */
+	struct mtx sfl_lock;	/* same cache-line as sc_lock? but that's ok */
+	TAILQ_HEAD(, sge_fl) sfl;
+	struct callout sfl_callout;
+
+	cpl_handler_t cpl_handler[256] __aligned(CACHE_LINE_SIZE);
 };
 
 #define ADAPTER_LOCK(sc)		mtx_lock(&(sc)->sc_lock)
@@ -506,11 +584,15 @@ struct adapter {
 #define for_each_rxq(pi, iter, rxq) \
 	rxq = &pi->adapter->sge.rxq[pi->first_rxq]; \
 	for (iter = 0; iter < pi->nrxq; ++iter, ++rxq)
+#define for_each_ofld_txq(pi, iter, ofld_txq) \
+	ofld_txq = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq]; \
+	for (iter = 0; iter < pi->nofldtxq; ++iter, ++ofld_txq)
+#define for_each_ofld_rxq(pi, iter, ofld_rxq) \
+	ofld_rxq = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq]; \
+	for (iter = 0; iter < pi->nofldrxq; ++iter, ++ofld_rxq)
 
 /* One for errors, one for firmware events */
 #define T4_EXTRA_INTR 2
-#define NINTRQ(sc) ((sc)->intr_count > T4_EXTRA_INTR ? \
-    (sc)->intr_count - T4_EXTRA_INTR : 1)
 
 static inline uint32_t
 t4_read_reg(struct adapter *sc, uint32_t reg)
@@ -589,29 +671,52 @@ static inline bool is_10G_port(const struct port_info *pi)
 	return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
 }
 
+static inline int tx_resume_threshold(struct sge_eq *eq)
+{
+	return (eq->qsize / 4);
+}
+
 /* t4_main.c */
-void cxgbe_txq_start(void *, int);
+void t4_tx_task(void *, int);
+void t4_tx_callout(void *);
 int t4_os_find_pci_capability(struct adapter *, int);
 int t4_os_pci_save_state(struct adapter *);
 int t4_os_pci_restore_state(struct adapter *);
 void t4_os_portmod_changed(const struct adapter *, int);
 void t4_os_link_changed(struct adapter *, int, int);
+void t4_iterate(void (*)(struct adapter *, void *), void *);
+int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t);
 
 /* t4_sge.c */
 void t4_sge_modload(void);
-void t4_sge_init(struct adapter *);
+int t4_sge_init(struct adapter *);
 int t4_create_dma_tag(struct adapter *);
 int t4_destroy_dma_tag(struct adapter *);
 int t4_setup_adapter_queues(struct adapter *);
 int t4_teardown_adapter_queues(struct adapter *);
-int t4_setup_eth_queues(struct port_info *);
-int t4_teardown_eth_queues(struct port_info *);
+int t4_setup_port_queues(struct port_info *);
+int t4_teardown_port_queues(struct port_info *);
+int t4_alloc_tx_maps(struct tx_maps *, bus_dma_tag_t, int, int);
+void t4_free_tx_maps(struct tx_maps *, bus_dma_tag_t);
 void t4_intr_all(void *);
 void t4_intr(void *);
 void t4_intr_err(void *);
 void t4_intr_evt(void *);
 int t4_mgmt_tx(struct adapter *, struct mbuf *);
+int t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct mbuf *);
 int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *);
 void t4_update_fl_bufsize(struct ifnet *);
+int can_resume_tx(struct sge_eq *);
+
+static inline int t4_wrq_tx(struct adapter *sc, struct sge_wrq *wrq, struct mbuf *m)
+{
+	int rc;
+
+	TXQ_LOCK(wrq);
+	rc = t4_wrq_tx_locked(sc, wrq, m);
+	TXQ_UNLOCK(wrq);
+	return (rc);
+}
+
 
 #endif
diff --git a/sys/dev/cxgbe/common/common.h b/sys/dev/cxgbe/common/common.h
index 913be9b..81866df 100644
--- a/sys/dev/cxgbe/common/common.h
+++ b/sys/dev/cxgbe/common/common.h
@@ -42,6 +42,15 @@ enum {
 
 enum { MEM_EDC0, MEM_EDC1, MEM_MC };
 
+enum {
+	MEMWIN0_APERTURE = 2048,
+	MEMWIN0_BASE     = 0x1b800,
+	MEMWIN1_APERTURE = 32768,
+	MEMWIN1_BASE     = 0x28000,
+	MEMWIN2_APERTURE = 65536,
+	MEMWIN2_BASE     = 0x30000,
+};
+
 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST };
 
 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR };
@@ -53,8 +62,8 @@ enum {
 };
 
 #define FW_VERSION_MAJOR 1
-#define FW_VERSION_MINOR 3
-#define FW_VERSION_MICRO 10
+#define FW_VERSION_MINOR 4
+#define FW_VERSION_MICRO 16
 
 struct port_stats {
 	u64 tx_octets;            /* total # of octets in good frames */
@@ -190,7 +199,6 @@ struct tp_proxy_stats {
 struct tp_cpl_stats {
 	u32 req[4];
 	u32 rsp[4];
-	u32 tx_err[4];
 };
 
 struct tp_rdma_stats {
@@ -214,9 +222,9 @@ struct vpd_params {
 };
 
 struct pci_params {
-	unsigned int  vpd_cap_addr;
-	unsigned char speed;
-	unsigned char width;
+	unsigned int vpd_cap_addr;
+	unsigned short speed;
+	unsigned short width;
 };
 
 /*
@@ -239,20 +247,20 @@ struct adapter_params {
 
 	unsigned int fw_vers;
 	unsigned int tp_vers;
-	u8 api_vers[7];
 
 	unsigned short mtus[NMTUS];
 	unsigned short a_wnd[NCCTRL_WIN];
 	unsigned short b_wnd[NCCTRL_WIN];
 
-	unsigned int mc_size;             /* MC memory size */
-	unsigned int nfilters;            /* size of filter region */
+	unsigned int mc_size;		/* MC memory size */
+	unsigned int nfilters;		/* size of filter region */
 
 	unsigned int cim_la_size;
 
-	unsigned int nports;             /* # of ethernet ports */
+	/* Used as int in sysctls, do not reduce size */
+	unsigned int nports;		/* # of ethernet ports */
 	unsigned int portvec;
-	unsigned int rev;                /* chip revision */
+	unsigned int rev;		/* chip revision */
 	unsigned int offload;
 
 	unsigned int ofldq_wr_cred;
@@ -366,6 +374,9 @@ int t4_seeprom_wp(struct adapter *adapter, int enable);
 int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords,
 		  u32 *data, int byte_oriented);
 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
+int t4_load_boot(struct adapter *adap, const u8 *boot_data,
+                 unsigned int boot_addr, unsigned int size);
+unsigned int t4_flash_cfg_addr(struct adapter *adapter);
 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
 int t4_get_fw_version(struct adapter *adapter, u32 *vers);
 int t4_get_tp_version(struct adapter *adapter, u32 *vers);
@@ -460,8 +471,8 @@ int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
 		enum dev_master master, enum dev_state *state);
 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
-int t4_early_init(struct adapter *adap, unsigned int mbox);
 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
+int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
 		    unsigned int vf, unsigned int nparams, const u32 *params,
 		    u32 *val);
diff --git a/sys/dev/cxgbe/common/t4_hw.c b/sys/dev/cxgbe/common/t4_hw.c
index dd8d0fc..48462aa 100644
--- a/sys/dev/cxgbe/common/t4_hw.c
+++ b/sys/dev/cxgbe/common/t4_hw.c
@@ -30,10 +30,10 @@ __FBSDID("$FreeBSD$");
 #include "common.h"
 #include "t4_regs.h"
 #include "t4_regs_values.h"
-#include "t4fw_interface.h"
+#include "firmware/t4fw_interface.h"
 
 #undef msleep
-#define msleep(x) DELAY((x) * 1000)
+#define msleep(x) pause("t4hw", (x) * hz / 1000)
 
 /**
  *	t4_wait_op_done_val - wait until an operation is completed
@@ -187,7 +187,7 @@ int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
 	 * off to larger delays to a maximum retry delay.
 	 */
 	static const int delay[] = {
-		1, 1, 3, 5, 10, 10, 20, 50, 100, 200
+		1, 1, 3, 5, 10, 10, 20, 50, 100
 	};
 
 	u32 v;
@@ -625,17 +625,6 @@ enum {
 	SF_RD_DATA_FAST = 0xb,        /* read flash */
 	SF_RD_ID        = 0x9f,       /* read ID */
 	SF_ERASE_SECTOR = 0xd8,       /* erase sector */
-
-	FW_START_SEC = 8,             /* first flash sector for FW */
-	FW_END_SEC = 15,              /* last flash sector for FW */
-	FW_IMG_START = FW_START_SEC * SF_SEC_SIZE,
-	FW_MAX_SIZE = (FW_END_SEC - FW_START_SEC + 1) * SF_SEC_SIZE,
-        
-	FLASH_CFG_MAX_SIZE    = 0x10000 , /* max size of the flash config file */
-	FLASH_CFG_OFFSET      = 0x1f0000,
-	FLASH_CFG_START_SEC   = FLASH_CFG_OFFSET / SF_SEC_SIZE,
-	FPGA_FLASH_CFG_OFFSET = 0xf0000 , /* if FPGA mode, then cfg file is at 1MB - 64KB */
-	FPGA_FLASH_CFG_START_SEC  = FPGA_FLASH_CFG_OFFSET / SF_SEC_SIZE,
 };
 
 /**
@@ -763,12 +752,15 @@ int t4_read_flash(struct adapter *adapter, unsigned int addr,
  *	@addr: the start address to write
  *	@n: length of data to write in bytes
  *	@data: the data to write
+ *	@byte_oriented: whether to store data as bytes or as words
  *
  *	Writes up to a page of data (256 bytes) to the serial flash starting
  *	at the given address.  All the data must be written to the same page.
+ *	If @byte_oriented is set the write data is stored as byte stream 
+ *	(i.e. matches what on disk), otherwise in big-endian.
  */
 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
-			  unsigned int n, const u8 *data)
+			  unsigned int n, const u8 *data, int byte_oriented)
 {
 	int ret;
 	u32 buf[SF_PAGE_SIZE / 4];
@@ -788,6 +780,9 @@ static int t4_write_flash(struct adapter *adapter, unsigned int addr,
 		for (val = 0, i = 0; i < c; ++i)
 			val = (val << 8) + *data++;
 
+		if (!byte_oriented)
+			val = htonl(val);
+
 		ret = sf1_write(adapter, c, c != left, 1, val);
 		if (ret)
 			goto unlock;
@@ -799,7 +794,8 @@ static int t4_write_flash(struct adapter *adapter, unsigned int addr,
 	t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
 
 	/* Read the page to verify the write succeeded */
-	ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
+	ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf,
+			    byte_oriented);
 	if (ret)
 		return ret;
 
@@ -825,7 +821,7 @@ unlock:
 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
 {
 	return t4_read_flash(adapter,
-			     FW_IMG_START + offsetof(struct fw_hdr, fw_ver), 1,
+			     FLASH_FW_START + offsetof(struct fw_hdr, fw_ver), 1,
 			     vers, 0);
 }
 
@@ -838,7 +834,7 @@ int t4_get_fw_version(struct adapter *adapter, u32 *vers)
  */
 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
 {
-	return t4_read_flash(adapter, FW_IMG_START + offsetof(struct fw_hdr,
+	return t4_read_flash(adapter, FLASH_FW_START + offsetof(struct fw_hdr,
 							      tp_microcode_ver),
 			     1, vers, 0);
 }
@@ -854,24 +850,17 @@ int t4_get_tp_version(struct adapter *adapter, u32 *vers)
  */
 int t4_check_fw_version(struct adapter *adapter)
 {
-	u32 api_vers[2];
 	int ret, major, minor, micro;
 
 	ret = t4_get_fw_version(adapter, &adapter->params.fw_vers);
 	if (!ret)
 		ret = t4_get_tp_version(adapter, &adapter->params.tp_vers);
-	if (!ret)
-		ret = t4_read_flash(adapter,
-			FW_IMG_START + offsetof(struct fw_hdr, intfver_nic),
-			2, api_vers, 1);
 	if (ret)
 		return ret;
 
 	major = G_FW_HDR_FW_VER_MAJOR(adapter->params.fw_vers);
 	minor = G_FW_HDR_FW_VER_MINOR(adapter->params.fw_vers);
 	micro = G_FW_HDR_FW_VER_MICRO(adapter->params.fw_vers);
-	memcpy(adapter->params.api_vers, api_vers,
-	       sizeof(adapter->params.api_vers));
 
 	if (major != FW_VERSION_MAJOR) {            /* major mismatch - fail */
 		CH_ERR(adapter, "card FW has major version %u, driver wants "
@@ -914,6 +903,21 @@ static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
 }
 
 /**
+ *	t4_flash_cfg_addr - return the address of the flash configuration file
+ *	@adapter: the adapter
+ *
+ *	Return the address within the flash where the Firmware Configuration
+ *	File is stored.
+ */
+unsigned int t4_flash_cfg_addr(struct adapter *adapter)
+{
+	if (adapter->params.sf_size == 0x100000)
+		return FLASH_FPGA_CFG_START;
+	else
+		return FLASH_CFG_START;
+}
+
+/**
  *	t4_load_cfg - download config file
  *	@adap: the adapter
  *	@cfg_data: the cfg text file to write
@@ -928,17 +932,8 @@ int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
 	unsigned int flash_cfg_start_sec;
 	unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
 
-	if (adap->params.sf_size == 0x100000) {
-		addr = FPGA_FLASH_CFG_OFFSET;
-		flash_cfg_start_sec = FPGA_FLASH_CFG_START_SEC;
-	} else {
-		addr = FLASH_CFG_OFFSET;
-		flash_cfg_start_sec = FLASH_CFG_START_SEC;
-	}
-	if (!size) {
-		CH_ERR(adap, "cfg file has no data\n");
-		return -EINVAL;
-	}
+	addr = t4_flash_cfg_addr(adap);
+	flash_cfg_start_sec = addr / SF_SEC_SIZE;
 
 	if (size > FLASH_CFG_MAX_SIZE) {
 		CH_ERR(adap, "cfg file too large, max is %u bytes\n",
@@ -950,7 +945,11 @@ int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
 			 sf_sec_size);
 	ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
 				     flash_cfg_start_sec + i - 1);
-	if (ret)
+	/*
+	 * If size == 0 then we're simply erasing the FLASH sectors associated
+	 * with the on-adapter Firmware Configuration File.
+	 */
+	if (ret || size == 0)
 		goto out;
 
         /* this will write to the flash up to SF_PAGE_SIZE at a time */
@@ -959,7 +958,7 @@ int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
 			n = size - i;
 		else 
 			n = SF_PAGE_SIZE;
-		ret = t4_write_flash(adap, addr, n, cfg_data);
+		ret = t4_write_flash(adap, addr, n, cfg_data, 1);
 		if (ret)
 			goto out;
 		
@@ -969,7 +968,8 @@ int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
                 
 out:
 	if (ret)
-		CH_ERR(adap, "config file download failed %d\n", ret);
+		CH_ERR(adap, "config file %s failed %d\n",
+		       (size == 0 ? "clear" : "download"), ret);
 	return ret;
 }
 
@@ -1004,9 +1004,9 @@ int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
 		CH_ERR(adap, "FW image size differs from size in FW header\n");
 		return -EINVAL;
 	}
-	if (size > FW_MAX_SIZE) {
+	if (size > FLASH_FW_MAX_SIZE) {
 		CH_ERR(adap, "FW image too large, max is %u bytes\n",
-		       FW_MAX_SIZE);
+		       FLASH_FW_MAX_SIZE);
 		return -EFBIG;
 	}
 
@@ -1020,7 +1020,8 @@ int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
 	}
 
 	i = DIV_ROUND_UP(size, sf_sec_size);        /* # of sectors spanned */
-	ret = t4_flash_erase_sectors(adap, FW_START_SEC, FW_START_SEC + i - 1);
+	ret = t4_flash_erase_sectors(adap, FLASH_FW_START_SEC,
+	    FLASH_FW_START_SEC + i - 1);
 	if (ret)
 		goto out;
 
@@ -1031,28 +1032,110 @@ int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
 	 */
 	memcpy(first_page, fw_data, SF_PAGE_SIZE);
 	((struct fw_hdr *)first_page)->fw_ver = htonl(0xffffffff);
-	ret = t4_write_flash(adap, FW_IMG_START, SF_PAGE_SIZE, first_page);
+	ret = t4_write_flash(adap, FLASH_FW_START, SF_PAGE_SIZE, first_page, 1);
 	if (ret)
 		goto out;
 
-	addr = FW_IMG_START;
+	addr = FLASH_FW_START;
 	for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
 		addr += SF_PAGE_SIZE;
 		fw_data += SF_PAGE_SIZE;
-		ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
+		ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1);
 		if (ret)
 			goto out;
 	}
 
 	ret = t4_write_flash(adap,
-			     FW_IMG_START + offsetof(struct fw_hdr, fw_ver),
-			     sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
+			     FLASH_FW_START + offsetof(struct fw_hdr, fw_ver),
+			     sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1);
 out:
 	if (ret)
 		CH_ERR(adap, "firmware download failed, error %d\n", ret);
 	return ret;
 }
 
+/* BIOS boot header */
+typedef struct boot_header_s {
+	u8	signature[2];	/* signature */
+	u8	length;		/* image length (include header) */
+	u8	offset[4];	/* initialization vector */
+	u8	reserved[19];	/* reserved */
+	u8	exheader[2];	/* offset to expansion header */
+} boot_header_t;
+
+enum {
+	BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */
+	BOOT_SIGNATURE = 0xaa55,   /* signature of BIOS boot ROM */
+	BOOT_SIZE_INC = 512,       /* image size measured in 512B chunks */
+	BOOT_MIN_SIZE = sizeof(boot_header_t), /* at least basic header */
+	BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC /* 1 byte * length increment  */
+};
+
+/*
+ *	t4_load_boot - download boot flash
+ *	@adapter: the adapter
+ *	@boot_data: the boot image to write
+ *	@size: image size
+ *
+ *	Write the supplied boot image to the card's serial flash.
+ *	The boot image has the following sections: a 28-byte header and the
+ *	boot image.
+ */
+int t4_load_boot(struct adapter *adap, const u8 *boot_data, 
+		 unsigned int boot_addr, unsigned int size)
+{
+	int ret, addr;
+	unsigned int i;
+	unsigned int boot_sector = boot_addr * 1024;
+	unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
+
+	/*
+	 * Perform some primitive sanity testing to avoid accidentally
+	 * writing garbage over the boot sectors.  We ought to check for
+	 * more but it's not worth it for now ...
+	 */
+	if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) {
+		CH_ERR(adap, "boot image too small/large\n");
+		return -EFBIG;
+	}
+
+	/*
+	 * Make sure the boot image does not encroach on the firmware region
+	 */
+	if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) {
+		CH_ERR(adap, "boot image encroaching on firmware region\n");
+		return -EFBIG;
+	}
+
+	i = DIV_ROUND_UP(size, sf_sec_size);        /* # of sectors spanned */
+	ret = t4_flash_erase_sectors(adap, boot_sector >> 16, 
+				     (boot_sector >> 16) + i - 1);
+	if (ret)
+		goto out;
+
+	/*
+	 * Skip over the first SF_PAGE_SIZE worth of data and write it after
+	 * we finish copying the rest of the boot image. This will ensure
+	 * that the BIOS boot header will only be written if the boot image
+	 * was written in full.
+	 */
+	addr = boot_sector;
+	for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
+		addr += SF_PAGE_SIZE; 
+		boot_data += SF_PAGE_SIZE;
+		ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0);
+		if (ret)
+			goto out;
+	}
+
+	ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE, boot_data, 0);
+
+out:
+	if (ret)
+		CH_ERR(adap, "boot image download failed, error %d\n", ret);
+	return ret;
+}
+
 /**
  *	t4_read_cimq_cfg - read CIM queue configuration
  *	@adap: the adapter
@@ -1668,7 +1751,10 @@ static void sge_intr_handler(struct adapter *adapter)
 	err = t4_read_reg(adapter, A_SGE_ERROR_STATS);
 	if (err & F_ERROR_QID_VALID) {
 		CH_ERR(adapter, "SGE error for queue %u\n", G_ERROR_QID(err));
-		t4_write_reg(adapter, A_SGE_ERROR_STATS, F_ERROR_QID_VALID);
+		if (err & F_UNCAPTURED_ERROR)
+			CH_ERR(adapter, "SGE UNCAPTURED_ERROR set (clearing)\n");
+		t4_write_reg(adapter, A_SGE_ERROR_STATS, F_ERROR_QID_VALID |
+			     F_UNCAPTURED_ERROR);
 	}
 
 	if (v != 0)
@@ -2261,6 +2347,7 @@ int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
 	 */
 	while (n > 0) {
 		int nq = min(n, 32);
+		int nq_packed = 0;
 		__be32 *qp = &cmd.iq0_to_iq2;
 
 		/*
@@ -2282,25 +2369,28 @@ int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
 		 * Ingress Queue ID array and insert them into the command.
 		 */
 		while (nq > 0) {
-			unsigned int v;
 			/*
 			 * Grab up to the next 3 Ingress Queue IDs (wrapping
 			 * around the Ingress Queue ID array if necessary) and
 			 * insert them into the firmware RSS command at the
 			 * current 3-tuple position within the commad.
 			 */
-			v = V_FW_RSS_IND_TBL_CMD_IQ0(*rsp);
-			if (++rsp >= rsp_end)
-				rsp = rspq;
-			v |= V_FW_RSS_IND_TBL_CMD_IQ1(*rsp);
-			if (++rsp >= rsp_end)
-				rsp = rspq;
-			v |= V_FW_RSS_IND_TBL_CMD_IQ2(*rsp);
-			if (++rsp >= rsp_end)
-				rsp = rspq;
-
-			*qp++ = htonl(v);
-			nq -= 3;
+			u16 qbuf[3];
+			u16 *qbp = qbuf;
+			int nqbuf = min(3, nq);
+
+			nq -= nqbuf;
+			qbuf[0] = qbuf[1] = qbuf[2] = 0;
+			while (nqbuf && nq_packed < 32) {
+				nqbuf--;
+				nq_packed++;
+				*qbp++ = *rsp++;
+				if (rsp >= rsp_end)
+					rsp = rspq;
+			}
+			*qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
+					    V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
+					    V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
 		}
 
 		/*
@@ -2694,8 +2784,6 @@ void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st)
 {
 	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->req,
 			 8, A_TP_MIB_CPL_IN_REQ_0);
-	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->tx_err,
-			 4, A_TP_MIB_CPL_OUT_ERR_0);
 }
 
 /**
@@ -3298,6 +3386,7 @@ void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
 	t4_read_reg64(adap, PORT_REG(idx, A_MPS_PORT_STAT_##name##_L))
 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
 
+	p->tx_pause            = GET_STAT(TX_PORT_PAUSE);
 	p->tx_octets           = GET_STAT(TX_PORT_BYTES);
 	p->tx_frames           = GET_STAT(TX_PORT_FRAMES);
 	p->tx_bcast_frames     = GET_STAT(TX_PORT_BCAST);
@@ -3312,7 +3401,6 @@ void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
 	p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
 	p->tx_frames_1519_max  = GET_STAT(TX_PORT_1519B_MAX);
 	p->tx_drop             = GET_STAT(TX_PORT_DROP);
-	p->tx_pause            = GET_STAT(TX_PORT_PAUSE);
 	p->tx_ppp0             = GET_STAT(TX_PORT_PPP0);
 	p->tx_ppp1             = GET_STAT(TX_PORT_PPP1);
 	p->tx_ppp2             = GET_STAT(TX_PORT_PPP2);
@@ -3322,6 +3410,7 @@ void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
 	p->tx_ppp6             = GET_STAT(TX_PORT_PPP6);
 	p->tx_ppp7             = GET_STAT(TX_PORT_PPP7);
 
+	p->rx_pause            = GET_STAT(RX_PORT_PAUSE);
 	p->rx_octets           = GET_STAT(RX_PORT_BYTES);
 	p->rx_frames           = GET_STAT(RX_PORT_FRAMES);
 	p->rx_bcast_frames     = GET_STAT(RX_PORT_BCAST);
@@ -3340,7 +3429,6 @@ void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
 	p->rx_frames_512_1023  = GET_STAT(RX_PORT_512B_1023B);
 	p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
 	p->rx_frames_1519_max  = GET_STAT(RX_PORT_1519B_MAX);
-	p->rx_pause            = GET_STAT(RX_PORT_PAUSE);
 	p->rx_ppp0             = GET_STAT(RX_PORT_PPP0);
 	p->rx_ppp1             = GET_STAT(RX_PORT_PPP1);
 	p->rx_ppp2             = GET_STAT(RX_PORT_PPP2);
@@ -3683,28 +3771,114 @@ int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
 {
 	int ret;
 	struct fw_hello_cmd c;
+	u32 v;
+	unsigned int master_mbox;
+	int retries = FW_CMD_HELLO_RETRIES;
 
+retry:
 	memset(&c, 0, sizeof(c));
 	INIT_CMD(c, HELLO, WRITE);
-	c.err_to_mbasyncnot = htonl(
+	c.err_to_clearinit = htonl(
 		V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
 		V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
 		V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
 			M_FW_HELLO_CMD_MBMASTER) |
-		V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox));
+		V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
+		V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
+		F_FW_HELLO_CMD_CLEARINIT);
 
+	/*
+	 * Issue the HELLO command to the firmware.  If it's not successful
+	 * but indicates that we got a "busy" or "timeout" condition, retry
+	 * the HELLO until we exhaust our retry limit.
+	 */
 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
-	if (ret == 0 && state) {
-		u32 v = ntohl(c.err_to_mbasyncnot);
-		if (v & F_FW_HELLO_CMD_INIT)
-			*state = DEV_STATE_INIT;
-		else if (v & F_FW_HELLO_CMD_ERR)
+	if (ret != FW_SUCCESS) {
+		if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
+			goto retry;
+		return ret;
+	}
+
+	v = ntohl(c.err_to_clearinit);
+	master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
+	if (state) {
+		if (v & F_FW_HELLO_CMD_ERR)
 			*state = DEV_STATE_ERR;
+		else if (v & F_FW_HELLO_CMD_INIT)
+			*state = DEV_STATE_INIT;
 		else
 			*state = DEV_STATE_UNINIT;
-		return G_FW_HELLO_CMD_MBMASTER(v);
 	}
-	return ret;
+
+	/*
+	 * If we're not the Master PF then we need to wait around for the
+	 * Master PF Driver to finish setting up the adapter.
+	 *
+	 * Note that we also do this wait if we're a non-Master-capable PF and
+	 * there is no current Master PF; a Master PF may show up momentarily
+	 * and we wouldn't want to fail pointlessly.  (This can happen when an
+	 * OS loads lots of different drivers rapidly at the same time).  In
+	 * this case, the Master PF returned by the firmware will be
+	 * M_PCIE_FW_MASTER so the test below will work ...
+	 */
+	if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 &&
+	    master_mbox != mbox) {
+		int waiting = FW_CMD_HELLO_TIMEOUT;
+
+		/*
+		 * Wait for the firmware to either indicate an error or
+		 * initialized state.  If we see either of these we bail out
+		 * and report the issue to the caller.  If we exhaust the
+		 * "hello timeout" and we haven't exhausted our retries, try
+		 * again.  Otherwise bail with a timeout error.
+		 */
+		for (;;) {
+			u32 pcie_fw;
+
+			msleep(50);
+			waiting -= 50;
+
+			/*
+			 * If neither Error nor Initialialized are indicated
+			 * by the firmware keep waiting till we exhaust our
+			 * timeout ... and then retry if we haven't exhausted
+			 * our retries ...
+			 */
+			pcie_fw = t4_read_reg(adap, A_PCIE_FW);
+			if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) {
+				if (waiting <= 0) {
+					if (retries-- > 0)
+						goto retry;
+
+					return -ETIMEDOUT;
+				}
+				continue;
+			}
+
+			/*
+			 * We either have an Error or Initialized condition
+			 * report errors preferentially.
+			 */
+			if (state) {
+				if (pcie_fw & F_PCIE_FW_ERR)
+					*state = DEV_STATE_ERR;
+				else if (pcie_fw & F_PCIE_FW_INIT)
+					*state = DEV_STATE_INIT;
+			}
+
+			/*
+			 * If we arrived before a Master PF was selected and
+			 * there's not a valid Master PF, grab its identity
+			 * for our caller.
+			 */
+			if (master_mbox == M_PCIE_FW_MASTER &&
+			    (pcie_fw & F_PCIE_FW_MASTER_VLD))
+				master_mbox = G_PCIE_FW_MASTER(pcie_fw);
+			break;
+		}
+	}
+
+	return master_mbox;
 }
 
 /**
@@ -3724,37 +3898,37 @@ int t4_fw_bye(struct adapter *adap, unsigned int mbox)
 }
 
 /**
- *	t4_init_cmd - ask FW to initialize the device
+ *	t4_fw_reset - issue a reset to FW
  *	@adap: the adapter
  *	@mbox: mailbox to use for the FW command
+ *	@reset: specifies the type of reset to perform
  *
- *	Issues a command to FW to partially initialize the device.  This
- *	performs initialization that generally doesn't depend on user input.
+ *	Issues a reset command of the specified type to FW.
  */
-int t4_early_init(struct adapter *adap, unsigned int mbox)
+int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
 {
-	struct fw_initialize_cmd c;
+	struct fw_reset_cmd c;
 
 	memset(&c, 0, sizeof(c));
-	INIT_CMD(c, INITIALIZE, WRITE);
+	INIT_CMD(c, RESET, WRITE);
+	c.val = htonl(reset);
 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
 }
 
 /**
- *	t4_fw_reset - issue a reset to FW
+ *	t4_fw_initialize - ask FW to initialize the device
  *	@adap: the adapter
  *	@mbox: mailbox to use for the FW command
- *	@reset: specifies the type of reset to perform
  *
- *	Issues a reset command of the specified type to FW.
+ *	Issues a command to FW to partially initialize the device.  This
+ *	performs initialization that generally doesn't depend on user input.
  */
-int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
+int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
 {
-	struct fw_reset_cmd c;
+	struct fw_initialize_cmd c;
 
 	memset(&c, 0, sizeof(c));
-	INIT_CMD(c, RESET, WRITE);
-	c.val = htonl(reset);
+	INIT_CMD(c, INITIALIZE, WRITE);
 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
 }
 
@@ -4495,6 +4669,21 @@ static int __devinit get_flash_params(struct adapter *adapter)
 	return 0;
 }
 
+static void __devinit set_pcie_completion_timeout(struct adapter *adapter,
+						  u8 range)
+{
+	u16 val;
+	u32 pcie_cap;
+
+	pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
+	if (pcie_cap) {
+		t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
+		val &= 0xfff0;
+		val |= range ;
+		t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
+	}
+}
+
 /**
  *	t4_prep_adapter - prepare SW and HW for operation
  *	@adapter: the adapter
@@ -4541,6 +4730,8 @@ int __devinit t4_prep_adapter(struct adapter *adapter)
 	adapter->params.portvec = 1;
 	adapter->params.vpd.cclk = 50000;
 
+	/* Set pci completion timeout value to 4 seconds. */
+	set_pcie_completion_timeout(adapter, 0xd);
 	return 0;
 }
 
diff --git a/sys/dev/cxgbe/common/t4_hw.h b/sys/dev/cxgbe/common/t4_hw.h
index fd48aab..b93734e 100644
--- a/sys/dev/cxgbe/common/t4_hw.h
+++ b/sys/dev/cxgbe/common/t4_hw.h
@@ -182,4 +182,82 @@ struct pagepod {
 #define M_PPOD_OFST    0xFFFFFFFF
 #define V_PPOD_OFST(x) ((x) << S_PPOD_OFST)
 
+/*
+ * Flash layout.
+ */
+#define FLASH_START(start)	((start) * SF_SEC_SIZE)
+#define FLASH_MAX_SIZE(nsecs)	((nsecs) * SF_SEC_SIZE)
+
+enum {
+	/*
+	 * Various Expansion-ROM boot images, etc.
+	 */
+	FLASH_EXP_ROM_START_SEC = 0,
+	FLASH_EXP_ROM_NSECS = 6,
+	FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC),
+	FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS),
+
+	/*
+	 * iSCSI Boot Firmware Table (iBFT) and other driver-related
+	 * parameters ...
+	 */
+	FLASH_IBFT_START_SEC = 6,
+	FLASH_IBFT_NSECS = 1,
+	FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC),
+	FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS),
+
+	/*
+	 * Boot configuration data.
+	 */
+	FLASH_BOOTCFG_START_SEC = 7,
+	FLASH_BOOTCFG_NSECS = 1,
+	FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC),
+	FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS),
+
+	/*
+	 * Location of firmware image in FLASH.
+	 */
+	FLASH_FW_START_SEC = 8,
+	FLASH_FW_NSECS = 8,
+	FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
+	FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
+        
+	/*
+	 * iSCSI persistent/crash information.
+	 */
+	FLASH_ISCSI_CRASH_START_SEC = 29,
+	FLASH_ISCSI_CRASH_NSECS = 1,
+	FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC),
+	FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS),
+
+	/*
+	 * FCoE persistent/crash information.
+	 */
+	FLASH_FCOE_CRASH_START_SEC = 30,
+	FLASH_FCOE_CRASH_NSECS = 1,
+	FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC),
+	FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS),
+
+	/*
+	 * Location of Firmware Configuration File in FLASH.  Since the FPGA
+	 * "FLASH" is smaller we need to store the Configuration File in a
+	 * different location -- which will overlap the end of the firmware
+	 * image if firmware ever gets that large ...
+	 */
+	FLASH_CFG_START_SEC = 31,
+	FLASH_CFG_NSECS = 1,
+	FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
+	FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
+
+	FLASH_FPGA_CFG_START_SEC = 15,
+	FLASH_FPGA_CFG_START = FLASH_START(FLASH_FPGA_CFG_START_SEC),
+
+	/*
+	 * Sectors 32-63 are reserved for FLASH failover.
+	 */
+};
+
+#undef FLASH_START
+#undef FLASH_MAX_SIZE
+
 #endif /* __T4_HW_H */
diff --git a/sys/dev/cxgbe/firmware/t4fw_cfg.txt b/sys/dev/cxgbe/firmware/t4fw_cfg.txt
new file mode 100644
index 0000000..65d6f0b
--- /dev/null
+++ b/sys/dev/cxgbe/firmware/t4fw_cfg.txt
@@ -0,0 +1,132 @@
+# Firmware configuration file.
+#
+# Global limits (some are hardware limits, others are due to the firmware).
+# Also note that the firmware reserves some of these resources for its own use
+# so it's not always possible for the drivers to grab everything listed here.
+# nvi = 128		virtual interfaces
+# niqflint = 1023	ingress queues with freelists and/or interrupts
+# nethctrl = 64K	Ethernet or ctrl egress queues
+# neq = 64K		egress queues of all kinds, including freelists
+# nexactf = 336		MPS TCAM entries, can oversubscribe.
+#
+
+[global]
+	rss_glb_config_mode = basicvirtual
+	rss_glb_config_options = tnlmapen, hashtoeplitz, tnlalllkp
+
+	sge_timer_value = 1, 5, 10, 50, 100, 200	# usecs
+
+	# TP_SHIFT_CNT
+	reg[0x7dc0] = 0x64f8849
+
+	filterMode = fragmentation, mpshittype, protocol, vlan, port, fcoe
+
+	# TP rx and tx payload memory (% of the total EDRAM + DDR3).
+	tp_pmrx = 40
+	tp_pmtx = 60
+	tp_pmrx_pagesize = 64K
+	tp_pmtx_pagesize = 64K
+
+# PFs 0-3.  These get 8 MSI/8 MSI-X vectors each.  VFs are supported by
+# these 4 PFs only.  Not used here at all.
+[function "0"]
+	nvf = 16
+	nvi = 1
+[function "0/*"]
+	nvi = 1
+
+[function "1"]
+	nvf = 16
+	nvi = 1
+[function "1/*"]
+	nvi = 1
+
+[function "2"]
+	nvf = 16
+	nvi = 1
+[function "2/*"]
+	nvi = 1
+
+[function "3"]
+	nvf = 16
+	nvi = 1
+[function "3/*"]
+	nvi = 1
+
+# PF4 is the resource-rich PF that the bus/nexus driver attaches to.
+# It gets 32 MSI/128 MSI-X vectors.
+[function "4"]
+	wx_caps = all
+	r_caps = all
+	nvi = 48
+	niqflint = 256
+	nethctrl = 128
+	neq = 256
+	nexactf = 300
+	cmask = all
+	pmask = all
+
+	# driver will mask off features it won't use
+	protocol = ofld
+
+	tp_l2t = 100
+
+	# TCAM has 8K cells; each region must start at a multiple of 128 cell.
+	# Each entry in these categories takes 4 cells each.  nhash will use the
+	# TCAM iff there is room left (that is, the rest don't add up to 2048).
+	nroute = 32
+	nclip = 0	# needed only for IPv6 offload
+	nfilter = 1504
+	nserver = 512
+	nhash = 16384
+
+# PF5 is the SCSI Controller PF. It gets 32 MSI/40 MSI-X vectors.
+# Not used right now.
+[function "5"]
+	nvi = 1
+
+# PF6 is the FCoE Controller PF. It gets 32 MSI/40 MSI-X vectors.
+# Not used right now.
+[function "6"]
+	nvi = 1
+
+# MPS has 192K buffer space for ingress packets from the wire as well as
+# loopback path of the L2 switch.
+[port "0"]
+	dcb = none
+	bg_mem = 25
+	lpbk_mem = 25
+	hwm = 30
+	lwm = 15
+	dwm = 30
+
+[port "1"]
+	dcb = none
+	bg_mem = 25
+	lpbk_mem = 25
+	hwm = 30
+	lwm = 15
+	dwm = 30
+
+[port "2"]
+	dcb = none
+	bg_mem = 25
+	lpbk_mem = 25
+	hwm = 30
+	lwm = 15
+	dwm = 30
+
+[port "3"]
+	dcb = none
+	bg_mem = 25
+	lpbk_mem = 25
+	hwm = 30
+	lwm = 15
+	dwm = 30
+
+[fini]
+	version = 0x1
+	checksum = 0xb31cdfac
+#
+# $FreeBSD$
+#
diff --git a/sys/dev/cxgbe/firmware/t4fw_cfg_uwire.txt b/sys/dev/cxgbe/firmware/t4fw_cfg_uwire.txt
new file mode 100644
index 0000000..134d60c
--- /dev/null
+++ b/sys/dev/cxgbe/firmware/t4fw_cfg_uwire.txt
@@ -0,0 +1,503 @@
+# Chelsio T4 Factory Default configuration file.
+#
+# Copyright (C) 2010 Chelsio Communications.  All rights reserved.
+#
+
+# This file provides the default, power-on configuration for 4-port T4-based
+# adapters shipped from the factory.  These defaults are designed to address
+# the needs of the vast majority of T4 customers.  The basic idea is to have
+# a default configuration which allows a customer to plug a T4 adapter in and
+# have it work regardless of OS, driver or application except in the most
+# unusual and/or demanding customer applications.
+#
+# Many of the T4 resources which are described by this configuration are
+# finite.  This requires balancing the configuration/operation needs of
+# device drivers across OSes and a large number of customer application.
+#
+# Some of the more important resources to allocate and their constaints are:
+#  1. Virtual Interfaces: 128.
+#  2. Ingress Queues with Free Lists: 1024.  PCI-E SR-IOV Virtual Functions
+#     must use a power of 2 Ingress Queues.
+#  3. Egress Queues: 128K.  PCI-E SR-IOV Virtual Functions must use a
+#     power of 2 Egress Queues.
+#  4. MSI-X Vectors: 1088.  A complication here is that the PCI-E SR-IOV
+#     Virtual Functions based off of a Physical Function all get the
+#     same umber of MSI-X Vectors as the base Physical Function.
+#     Additionally, regardless of whether Virtual Functions are enabled or
+#     not, their MSI-X "needs" are counted by the PCI-E implementation.
+#     And finally, all Physical Funcations capable of supporting Virtual
+#     Functions (PF0-3) must have the same number of configured TotalVFs in
+#     their SR-IOV Capabilities.
+#  5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
+#     address matching on Ingress Packets.
+#
+# Some of the important OS/Driver resource needs are:
+#  6. Some OS Drivers will manage all resources through a single Physical
+#     Function (currently PF0 but it could be any Physical Function).  Thus,
+#     this "Unified PF"  will need to have enough resources allocated to it
+#     to allow for this.  And because of the MSI-X resource allocation
+#     constraints mentioned above, this probably means we'll either have to
+#     severely limit the TotalVFs if we continue to use PF0 as the Unified PF
+#     or we'll need to move the Unified PF into the PF4-7 range since those
+#     Physical Functions don't have any Virtual Functions associated with
+#     them.
+#  7. Some OS Drivers will manage different ports and functions (NIC,
+#     storage, etc.) on different Physical Functions.  For example, NIC
+#     functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc.
+#
+# Some of the customer application needs which need to be accommodated:
+#  8. Some customers will want to support large CPU count systems with
+#     good scaling.  Thus, we'll need to accommodate a number of
+#     Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
+#     to be involved per port and per application function.  For example,
+#     in the case where all ports and application functions will be
+#     managed via a single Unified PF and we want to accommodate scaling up
+#     to 8 CPUs, we would want:
+#
+#         4 ports *
+#         3 application functions (NIC, FCoE, iSCSI) per port *
+#         8 Ingress Queue/MSI-X Vectors per application function
+#
+#     for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
+#     (Plus a few for Firmware Event Queues, etc.)
+#
+#  9. Some customers will want to use T4's PCI-E SR-IOV Capability to allow
+#     Virtual Machines to directly access T4 functionality via SR-IOV
+#     Virtual Functions and "PCI Device Passthrough" -- this is especially
+#     true for the NIC application functionality.  (Note that there is
+#     currently no ability to use the TOE, FCoE, iSCSI, etc. via Virtual
+#     Functions so this is in fact solely limited to NIC.)
+#
+
+
+# Global configuration settings.
+#
+[global]
+	rss_glb_config_mode = basicvirtual
+	rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp
+
+	# The following Scatter Gather Engine (SGE) settings assume a 4KB Host
+	# Page Size and a 64B L1 Cache Line Size. It programs the
+	# EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2.
+	# If a Master PF Driver finds itself on a machine with different
+	# parameters, then the Master PF Driver is responsible for initializing
+	# these parameters to appropriate values.
+	#
+	# Notes:
+	#  1. The Free List Buffer Sizes below are raw and the firmware will
+	#     round them up to the Ingress Padding Boundary.
+	#  2. The SGE Timer Values below are expressed below in microseconds.
+	#     The firmware will convert these values to Core Clock Ticks when
+	#     it processes the configuration parameters.
+	#
+	reg[0x1008] = 0x40810/0x21c70	# SGE_CONTROL
+	reg[0x100c] = 0x22222222	# SGE_HOST_PAGE_SIZE
+	reg[0x10a0] = 0x01040810	# SGE_INGRESS_RX_THRESHOLD
+	reg[0x1044] = 4096		# SGE_FL_BUFFER_SIZE0
+	reg[0x1048] = 65536		# SGE_FL_BUFFER_SIZE1
+	reg[0x104c] = 1536		# SGE_FL_BUFFER_SIZE2
+	reg[0x1050] = 9024		# SGE_FL_BUFFER_SIZE3
+	reg[0x1054] = 9216		# SGE_FL_BUFFER_SIZE4
+	reg[0x1058] = 2048		# SGE_FL_BUFFER_SIZE5
+	reg[0x105c] = 128		# SGE_FL_BUFFER_SIZE6
+	reg[0x1060] = 8192		# SGE_FL_BUFFER_SIZE7
+	reg[0x1064] = 16384		# SGE_FL_BUFFER_SIZE8
+	reg[0x10a4] = 0xa000a000/0xf000f000 # SGE_DBFIFO_STATUS
+	reg[0x10a8] = 0x2000/0x2000	# SGE_DOORBELL_CONTROL
+	sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs
+
+	reg[0x7dc0] = 0x64f8849		# TP_SHIFT_CNT
+
+	# Selection of tuples for LE filter lookup, fields (and widths which
+	# must sum to <= 36): { IP Fragment (1), MPS Match Type (3),
+	# IP Protocol (8), [Inner] VLAN (17), Port (3), FCoE (1) }
+	#
+	filterMode = fragmentation, mpshittype, protocol, vnic_id, port, fcoe
+
+	# Percentage of dynamic memory (in either the EDRAM or external MEM)
+	# to use for TP RX payload
+	tp_pmrx = 30
+
+	# TP RX payload page size
+	tp_pmrx_pagesize = 64K
+
+	# Percentage of dynamic memory (in either the EDRAM or external MEM)
+	# to use for TP TX payload
+	tp_pmtx = 50
+
+	# TP TX payload page size
+	tp_pmtx_pagesize = 64K
+
+# Some "definitions" to make the rest of this a bit more readable.  We support
+# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets"
+# per function per port ...
+#
+# NMSIX = 1088			# available MSI-X Vectors
+# NVI = 128			# available Virtual Interfaces
+# NMPSTCAM = 336		# MPS TCAM entries
+#
+# NPORTS = 4			# ports
+# NCPUS = 8			# CPUs we want to support scalably
+# NFUNCS = 3			# functions per port (NIC, FCoE, iSCSI)
+
+# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified
+# PF" which many OS Drivers will use to manage most or all functions.
+#
+# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
+# use Forwarded Interrupt Ingress Queues.  For these latter, an Ingress Queue
+# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue
+# will be specified as the "Ingress Queue Asynchronous Destination Index."
+# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
+# than or equal to the number of Ingress Queues ...
+#
+# NVI_NIC = 4			# NIC access to NPORTS
+# NFLIQ_NIC = 32		# NIC Ingress Queues with Free Lists
+# NETHCTRL_NIC = 32		# NIC Ethernet Control/TX Queues
+# NEQ_NIC = 64			# NIC Egress Queues (FL, ETHCTRL/TX)
+# NMPSTCAM_NIC = 16		# NIC MPS TCAM Entries (NPORTS*4)
+# NMSIX_NIC = 32		# NIC MSI-X Interrupt Vectors (FLIQ)
+# 
+# NVI_OFLD = 0			# Offload uses NIC function to access ports
+# NFLIQ_OFLD = 16		# Offload Ingress Queues with Free Lists
+# NETHCTRL_OFLD = 0		# Offload Ethernet Control/TX Queues
+# NEQ_OFLD = 16			# Offload Egress Queues (FL)
+# NMPSTCAM_OFLD = 0		# Offload MPS TCAM Entries (uses NIC's)
+# NMSIX_OFLD = 16		# Offload MSI-X Interrupt Vectors (FLIQ)
+#
+# NVI_RDMA = 0			# RDMA uses NIC function to access ports
+# NFLIQ_RDMA = 4		# RDMA Ingress Queues with Free Lists
+# NETHCTRL_RDMA = 0		# RDMA Ethernet Control/TX Queues
+# NEQ_RDMA = 4			# RDMA Egress Queues (FL)
+# NMPSTCAM_RDMA = 0		# RDMA MPS TCAM Entries (uses NIC's)
+# NMSIX_RDMA = 4		# RDMA MSI-X Interrupt Vectors (FLIQ)
+#
+# NEQ_WD = 128			# Wire Direct TX Queues and FLs
+# NETHCTRL_WD = 64		# Wire Direct TX Queues
+# NFLIQ_WD = 64	`		# Wire Direct Ingress Queues with Free Lists
+#
+# NVI_ISCSI = 4			# ISCSI access to NPORTS
+# NFLIQ_ISCSI = 4		# ISCSI Ingress Queues with Free Lists
+# NETHCTRL_ISCSI = 0		# ISCSI Ethernet Control/TX Queues
+# NEQ_ISCSI = 4			# ISCSI Egress Queues (FL)
+# NMPSTCAM_ISCSI = 4		# ISCSI MPS TCAM Entries (NPORTS)
+# NMSIX_ISCSI = 4		# ISCSI MSI-X Interrupt Vectors (FLIQ)
+#
+# NVI_FCOE = 4			# FCOE access to NPORTS
+# NFLIQ_FCOE = 34		# FCOE Ingress Queues with Free Lists
+# NETHCTRL_FCOE = 32		# FCOE Ethernet Control/TX Queues
+# NEQ_FCOE = 66			# FCOE Egress Queues (FL)
+# NMPSTCAM_FCOE = 32 		# FCOE MPS TCAM Entries (NPORTS)
+# NMSIX_FCOE = 34		# FCOE MSI-X Interrupt Vectors (FLIQ)
+
+# Two extra Ingress Queues per function for Firmware Events and Forwarded
+# Interrupts, and two extra interrupts per function for Firmware Events (or a
+# Forwarded Interrupt Queue) and General Interrupts per function.
+#
+# NFLIQ_EXTRA = 6		# "extra" Ingress Queues 2*NFUNCS (Firmware and
+# 				#   Forwarded Interrupts
+# NMSIX_EXTRA = 6		# extra interrupts 2*NFUNCS (Firmware and
+# 				#   General Interrupts
+
+# Microsoft HyperV resources.  The HyperV Virtual Ingress Queues will have
+# their interrupts forwarded to another set of Forwarded Interrupt Queues.
+#
+# NVI_HYPERV = 16		# VMs we want to support
+# NVIIQ_HYPERV = 2		# Virtual Ingress Queues with Free Lists per VM
+# NFLIQ_HYPERV = 40		# VIQs + NCPUS Forwarded Interrupt Queues
+# NEQ_HYPERV = 32		# VIQs Free Lists
+# NMPSTCAM_HYPERV = 16		# MPS TCAM Entries (NVI_HYPERV)
+# NMSIX_HYPERV = 8		# NCPUS Forwarded Interrupt Queues
+
+# Adding all of the above Unified PF resource needs together: (NIC + OFLD +
+# RDMA + ISCSI + FCOE + EXTRA + HYPERV)
+#
+# NVI_UNIFIED = 28
+# NFLIQ_UNIFIED = 106
+# NETHCTRL_UNIFIED = 32
+# NEQ_UNIFIED = 124
+# NMPSTCAM_UNIFIED = 40
+#
+# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round
+# that up to 128 to make sure the Unified PF doesn't run out of resources.
+#
+# NMSIX_UNIFIED = 128
+#
+# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors
+# which is 34 but they're probably safe with 32.
+#
+# NMSIX_STORAGE = 32
+
+# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions
+# associated with it.  Thus, the MSI-X Vector allocations we give to the
+# UnifiedPF aren't inherited by any Virtual Functions.  As a result we can
+# provision many more Virtual Functions than we can if the UnifiedPF were
+# one of PF0-3.
+#
+
+# All of the below PCI-E parameters are actually stored in various *_init.txt
+# files.  We include them below essentially as comments.
+#
+# For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated
+# ports 0-3.
+#
+# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above.
+#
+# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI
+# storage applications across all four possible ports.
+#
+# Additionally, since the UnifiedPF isn't one of the per-port Physical
+# Functions, we give the UnifiedPF and the PF0-3 Physical Functions
+# different PCI Device IDs which will allow Unified and Per-Port Drivers
+# to directly select the type of Physical Function to which they wish to be
+# attached.
+#
+# Note that the actual values used for the PCI-E Intelectual Property will be
+# 1 less than those below since that's the way it "counts" things.  For
+# readability, we use the number we actually mean ...
+#
+# PF0_INT = 8			# NCPUS
+# PF1_INT = 8			# NCPUS
+# PF2_INT = 8			# NCPUS
+# PF3_INT = 8			# NCPUS
+# PF0_3_INT = 32		# PF0_INT + PF1_INT + PF2_INT + PF3_INT
+# 
+# PF4_INT = 128			# NMSIX_UNIFIED
+# PF5_INT = 32			# NMSIX_STORAGE
+# PF6_INT = 32			# NMSIX_STORAGE
+# PF7_INT = 0			# Nothing Assigned
+# PF4_7_INT = 192		# PF4_INT + PF5_INT + PF6_INT + PF7_INT
+# 
+# PF0_7_INT = 224		# PF0_3_INT + PF4_7_INT
+# 
+# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries)
+# but we'll lower that to 16 to make our total 64 and a nice power of 2 ...
+#
+# NVF = 16
+
+# For those OSes which manage different ports on different PFs, we need
+# only enough resources to support a single port's NIC application functions
+# on PF0-3.  The below assumes that we're only doing NIC with NCPUS "Queue
+# Sets" for ports 0-3.  The FCoE and iSCSI functions for such OSes will be
+# managed on the "storage PFs" (see below).
+#
+[function "0"]
+	nvf = 16		# NVF on this function
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 1			# 1 port
+	niqflint = 8		# NCPUS "Queue Sets"
+	nethctrl = 8		# NCPUS "Queue Sets"
+	neq = 16		# niqflint + nethctrl Egress Queues
+	nexactf = 8		# number of exact MPSTCAM MAC filters
+	cmask = all		# access to all channels
+	pmask = 0x1		# access to only one port
+
+[function "1"]
+	nvf = 16		# NVF on this function
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 1			# 1 port
+	niqflint = 8		# NCPUS "Queue Sets"
+	nethctrl = 8		# NCPUS "Queue Sets"
+	neq = 16		# niqflint + nethctrl Egress Queues
+	nexactf = 8		# number of exact MPSTCAM MAC filters
+	cmask = all		# access to all channels
+	pmask = 0x2		# access to only one port
+
+[function "2"]
+	nvf = 16		# NVF on this function
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 1			# 1 port
+	niqflint = 8		# NCPUS "Queue Sets"
+	nethctrl = 8		# NCPUS "Queue Sets"
+	neq = 16		# niqflint + nethctrl Egress Queues
+	nexactf = 8		# number of exact MPSTCAM MAC filters
+	cmask = all		# access to all channels
+	pmask = 0x4		# access to only one port
+
+[function "3"]
+	nvf = 16		# NVF on this function
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 1			# 1 port
+	niqflint = 8		# NCPUS "Queue Sets"
+	nethctrl = 8		# NCPUS "Queue Sets"
+	neq = 16		# niqflint + nethctrl Egress Queues
+	nexactf = 8		# number of exact MPSTCAM MAC filters
+	cmask = all		# access to all channels
+	pmask = 0x8		# access to only one port
+
+# Some OS Drivers manage all application functions for all ports via PF4.
+# Thus we need to provide a large number of resources here.  For Egress
+# Queues we need to account for both TX Queues as well as Free List Queues
+# (because the host is responsible for producing Free List Buffers for the
+# hardware to consume).
+#
+[function "4"]
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 28		# NVI_UNIFIED
+	niqflint = 170		# NFLIQ_UNIFIED + NLFIQ_WD
+	nethctrl = 96 		# NETHCTRL_UNIFIED + NETHCTRL_WD
+	neq = 252		# NEQ_UNIFIED + NEQ_WD
+	nexactf = 40		# NMPSTCAM_UNIFIED
+	cmask = all		# access to all channels
+	pmask = all		# access to all four ports ...
+	nroute = 32		# number of routing region entries
+	nclip = 32		# number of clip region entries
+	nfilter = 768		# number of filter region entries
+	nserver = 256		# number of server region entries
+	nhash = 0		# number of hash region entries
+	protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu
+	tp_l2t = 100
+	tp_ddp = 2
+	tp_ddp_iscsi = 2
+	tp_stag = 2
+	tp_pbl = 5
+	tp_rq = 7
+
+# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may
+# need to have Virtual Interfaces on each of the four ports with up to NCPUS
+# "Queue Sets" each.
+#
+[function "5"]
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 4			# NPORTS
+	niqflint = 34		# NPORTS*NCPUS + NMSIX_EXTRA
+	nethctrl = 32		# NPORTS*NCPUS
+	neq = 64		# NPORTS*NCPUS * 2 (FL, ETHCTRL/TX)
+	nexactf = 4		# NPORTS
+	cmask = all		# access to all channels
+	pmask = all		# access to all four ports ...
+
+[function "6"]
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 4			# NPORTS
+	niqflint = 34		# NPORTS*NCPUS + NMSIX_EXTRA
+	nethctrl = 32		# NPORTS*NCPUS
+	neq = 66		# NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA)
+	nexactf = 32		# NPORTS + adding 28 exact entries for FCoE
+				# which is OK since < MIN(SUM PF0..3, PF4)
+				# and we never load PF0..3 and PF4 concurrently
+	cmask = all		# access to all channels
+	pmask = all		# access to all four ports ...
+	nhash = 0 
+	protocol = fcoe_initiator
+	tp_ddp = 2
+	fcoe_nfcf = 16
+	fcoe_nvnp = 32
+	fcoe_nssn = 1024
+
+# For Virtual functions, we only allow NIC functionality and we only allow
+# access to one port (1 << PF).  Note that because of limitations in the
+# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL
+# and GTS registers, the number of Ingress and Egress Queues must be a power
+# of 2.
+#
+[function "0/*"]		# NVF
+	wx_caps = 0x82		# DMAQ | VF
+	r_caps = 0x86		# DMAQ | VF | PORT
+	nvi = 1			# 1 port
+	niqflint = 4		# 2 "Queue Sets" + NXIQ
+	nethctrl = 2		# 2 "Queue Sets"
+	neq = 4			# 2 "Queue Sets" * 2
+	nexactf = 4
+	cmask = all		# access to all channels
+	pmask = 0x1		# access to only one port ...
+
+[function "1/*"]		# NVF
+	wx_caps = 0x82		# DMAQ | VF
+	r_caps = 0x86		# DMAQ | VF | PORT
+	nvi = 1			# 1 port
+	niqflint = 4		# 2 "Queue Sets" + NXIQ
+	nethctrl = 2		# 2 "Queue Sets"
+	neq = 4			# 2 "Queue Sets" * 2
+	nexactf = 4
+	cmask = all		# access to all channels
+	pmask = 0x2		# access to only one port ...
+
+[function "2/*"]		# NVF
+	wx_caps = 0x82		# DMAQ | VF
+	r_caps = 0x86		# DMAQ | VF | PORT
+	nvi = 1			# 1 port
+	niqflint = 4		# 2 "Queue Sets" + NXIQ
+	nethctrl = 2		# 2 "Queue Sets"
+	neq = 4			# 2 "Queue Sets" * 2
+	nexactf = 4
+	cmask = all		# access to all channels
+	pmask = 0x4		# access to only one port ...
+
+[function "3/*"]		# NVF
+	wx_caps = 0x82		# DMAQ | VF
+	r_caps = 0x86		# DMAQ | VF | PORT
+	nvi = 1			# 1 port
+	niqflint = 4		# 2 "Queue Sets" + NXIQ
+	nethctrl = 2		# 2 "Queue Sets"
+	neq = 4			# 2 "Queue Sets" * 2
+	nexactf = 4
+	cmask = all		# access to all channels
+	pmask = 0x8		# access to only one port ...
+
+# MPS features a 196608 bytes ingress buffer that is used for ingress buffering
+# for packets from the wire as well as the loopback path of the L2 switch. The
+# folling params control how the buffer memory is distributed and the L2 flow
+# control settings:
+#
+# bg_mem:	%-age of mem to use for port/buffer group
+# lpbk_mem:	%-age of port/bg mem to use for loopback
+# hwm:		high watermark; bytes available when starting to send pause
+#		frames (in units of 0.1 MTU)
+# lwm:		low watermark; bytes remaining when sending 'unpause' frame
+#		(in inuits of 0.1 MTU)
+# dwm:		minimum delta between high and low watermark (in units of 100
+#		Bytes)
+#
+[port "0"]
+	dcb = ppp, dcbx		# configure for DCB PPP and enable DCBX offload
+	bg_mem = 25
+	lpbk_mem = 25
+	hwm = 30
+	lwm = 15
+	dwm = 30
+
+[port "1"]
+	dcb = ppp, dcbx
+	bg_mem = 25
+	lpbk_mem = 25
+	hwm = 30
+	lwm = 15
+	dwm = 30
+
+[port "2"]
+	dcb = ppp, dcbx
+	bg_mem = 25
+	lpbk_mem = 25
+	hwm = 30
+	lwm = 15
+	dwm = 30
+
+[port "3"]
+	dcb = ppp, dcbx
+	bg_mem = 25
+	lpbk_mem = 25
+	hwm = 30
+	lwm = 15
+	dwm = 30
+
+[fini]
+	version = 0x14250007
+	checksum = 0xfcbadefb
+
+# Total resources used by above allocations:
+#   Virtual Interfaces: 104
+#   Ingress Queues/w Free Lists and Interrupts: 526
+#   Egress Queues: 702
+#   MPS TCAM Entries: 336
+#   MSI-X Vectors: 736
+#   Virtual Functions: 64
+#
+# $FreeBSD$
+#
diff --git a/sys/dev/cxgbe/common/t4fw_interface.h b/sys/dev/cxgbe/firmware/t4fw_interface.h
index 3eb9615..6d259a5 100644
--- a/sys/dev/cxgbe/common/t4fw_interface.h
+++ b/sys/dev/cxgbe/firmware/t4fw_interface.h
@@ -37,16 +37,23 @@
 enum fw_retval {
 	FW_SUCCESS		= 0,	/* completed sucessfully */
 	FW_EPERM		= 1,	/* operation not permitted */
+	FW_ENOENT		= 2,	/* no such file or directory */
 	FW_EIO			= 5,	/* input/output error; hw bad */
-	FW_ENOEXEC		= 8,	/* Exec format error; inv microcode */
+	FW_ENOEXEC		= 8,	/* exec format error; inv microcode */
 	FW_EAGAIN		= 11,	/* try again */
 	FW_ENOMEM		= 12,	/* out of memory */
 	FW_EFAULT		= 14,	/* bad address; fw bad */
 	FW_EBUSY		= 16,	/* resource busy */
-	FW_EEXIST		= 17,	/* File exists */
+	FW_EEXIST		= 17,	/* file exists */
 	FW_EINVAL		= 22,	/* invalid argument */
+	FW_ENOSPC		= 28,	/* no space left on device */
 	FW_ENOSYS		= 38,	/* functionality not implemented */
 	FW_EPROTO		= 71,	/* protocol error */
+	FW_EADDRINUSE		= 98,	/* address already in use */
+	FW_EADDRNOTAVAIL	= 99,	/* cannot assigned requested address */
+	FW_ENETDOWN		= 100,	/* network is down */
+	FW_ENETUNREACH		= 101,	/* network is unreachable */
+	FW_ENOBUFS		= 105,	/* no buffer space available */
 	FW_ETIMEDOUT		= 110,	/* timeout */
 	FW_EINPROGRESS		= 115,	/* fw internal */
 	FW_SCSI_ABORT_REQUESTED	= 128,	/* */
@@ -62,6 +69,8 @@ enum fw_retval {
 	FW_ERR_RDEV_IMPL_LOGO	= 138,	/* */
 	FW_SCSI_UNDER_FLOW_ERR  = 139,	/* */
 	FW_SCSI_OVER_FLOW_ERR   = 140,	/* */
+	FW_SCSI_DDP_ERR		= 141,	/* DDP error*/
+	FW_SCSI_TASK_ERR	= 142,	/* No SCSI tasks available */
 };
 
 /******************************************************************************
@@ -89,7 +98,7 @@ enum fw_wr_opcodes {
 	FW_RI_INV_LSTAG_WR	= 0x1a,
 	FW_RI_WR		= 0x0d,
 	FW_ISCSI_NODE_WR	= 0x4a,
-	FW_LASTC2E_WR		= 0x4b
+	FW_LASTC2E_WR		= 0x50
 };
 
 /*
@@ -512,8 +521,14 @@ struct fw_eth_tx_pkt_wr {
 	__be64 r3;
 };
 
+#define S_FW_ETH_TX_PKT_WR_IMMDLEN	0
+#define M_FW_ETH_TX_PKT_WR_IMMDLEN	0x1ff
+#define V_FW_ETH_TX_PKT_WR_IMMDLEN(x)	((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
+#define G_FW_ETH_TX_PKT_WR_IMMDLEN(x)	\
+    (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
+
 struct fw_eth_tx_pkts_wr {
-	__be32 op_immdlen;
+	__be32 op_pkd;
 	__be32 equiq_to_len16;
 	__be32 r3;
 	__be16 plen;
@@ -537,7 +552,7 @@ enum fw_flowc_mnem {
 	FW_FLOWC_MNEM_RCVNXT,
 	FW_FLOWC_MNEM_SNDBUF,
 	FW_FLOWC_MNEM_MSS,
-	FW_FLOWC_MEM_TXDATAPLEN_MAX,
+	FW_FLOWC_MNEM_TXDATAPLEN_MAX,
 };
 
 struct fw_flowc_mnemval {
@@ -1469,22 +1484,129 @@ struct fw_ri_wr {
 #define G_FW_RI_WR_P2PTYPE(x)	\
     (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE)
 
-#ifdef FOISCSI
+/******************************************************************************
+ *   S C S I   W O R K   R E Q U E S T s
+ **********************************************/
+
+
+/******************************************************************************
+ *   F O i S C S I   W O R K   R E Q U E S T s
+ **********************************************/
+
+#define	ISCSI_NAME_MAX_LEN	224
+#define	ISCSI_ALIAS_MAX_LEN	224
+
+enum session_type {
+	ISCSI_SESSION_DISCOVERY = 0,
+	ISCSI_SESSION_NORMAL,
+};
+
+enum digest_val {
+	DIGEST_NONE = 0,
+	DIGEST_CRC32,
+	DIGEST_BOTH,
+};
+
+enum fw_iscsi_subops {
+	NODE_ONLINE = 1,
+	SESS_ONLINE,
+	CONN_ONLINE,
+	NODE_OFFLINE,
+	SESS_OFFLINE,
+	CONN_OFFLINE,
+	NODE_STATS,
+	SESS_STATS,
+	CONN_STATS,
+	UPDATE_IOHANDLE,
+};
+
+struct fw_iscsi_node_attr {
+	__u8		name_len;
+	__u8		node_name[ISCSI_NAME_MAX_LEN];
+	__u8		alias_len;
+	__u8		node_alias[ISCSI_ALIAS_MAX_LEN];
+};
+
+struct fw_iscsi_sess_attr {
+	__u8		sess_type;
+	__u8		seq_inorder;
+	__u8		pdu_inorder;
+	__u8		immd_data_en;
+	__u8		init_r2t_en;
+	__u8		erl;
+	__be16		max_conn;
+	__be16		max_r2t;
+	__be16		time2wait;
+	__be16		time2retain;
+	__be32		max_burst;
+	__be32		first_burst;
+};
+
+struct fw_iscsi_conn_attr {
+	__u8		hdr_digest;
+	__u8		data_digest;
+	__be32		max_rcv_dsl;
+	__be16		dst_port;
+	__be32		dst_addr;
+	__be16		src_port;
+	__be32		src_addr;
+	__be32		ping_tmo;
+};
+
+struct fw_iscsi_node_stats {
+	__be16		sess_count;
+	__be16		chap_fail_count;
+	__be16		login_count;
+	__be16		r1;
+};
+
+struct fw_iscsi_sess_stats {
+	__be32		rxbytes;
+	__be32		txbytes;
+	__be32		scmd_count;
+	__be32		read_cmds;
+	__be32		write_cmds;
+	__be32		read_bytes;
+	__be32		write_bytes;
+	__be32		scsi_err_count;
+	__be32		scsi_rst_count;
+	__be32		iscsi_tmf_count;
+	__be32		conn_count;
+};
+
+struct fw_iscsi_conn_stats {
+	__be32		txbytes;
+	__be32		rxbytes;
+	__be32		dataout;
+	__be32		datain;
+};
+
 struct fw_iscsi_node_wr {
 	__u8   opcode;
 	__u8   subop;
-	__u8   node_attr_to_compl;
-	__u8   len16;
-	__u8   status;
-	__u8   r2;
 	__be16 immd_len;
+	__be32 flowid_len16;
 	__be64 cookie;
+	__u8   node_attr_to_compl;
+	__u8   status;
+	__be16 r1;
 	__be32 node_id;
 	__be32 ctrl_handle;
 	__be32 io_handle;
-	__be32 r3;
 };
 
+#define S_FW_ISCSI_NODE_WR_FLOWID	8
+#define M_FW_ISCSI_NODE_WR_FLOWID	0xfffff
+#define V_FW_ISCSI_NODE_WR_FLOWID(x)	((x) << S_FW_ISCSI_NODE_WR_FLOWID)
+#define G_FW_ISCSI_NODE_WR_FLOWID(x)	\
+    (((x) >> S_FW_ISCSI_NODE_WR_FLOWID) & M_FW_ISCSI_NODE_WR_FLOWID)
+
+#define S_FW_ISCSI_NODE_WR_LEN16	0
+#define M_FW_ISCSI_NODE_WR_LEN16	0xff
+#define V_FW_ISCSI_NODE_WR_LEN16(x)	((x) << S_FW_ISCSI_NODE_WR_LEN16)
+#define G_FW_ISCSI_NODE_WR_LEN16(x)	\
+    (((x) >> S_FW_ISCSI_NODE_WR_LEN16) & M_FW_ISCSI_NODE_WR_LEN16)
+
 #define S_FW_ISCSI_NODE_WR_NODE_ATTR	7
 #define M_FW_ISCSI_NODE_WR_NODE_ATTR	0x1
 #define V_FW_ISCSI_NODE_WR_NODE_ATTR(x)	((x) << S_FW_ISCSI_NODE_WR_NODE_ATTR)
@@ -1527,7 +1649,109 @@ struct fw_iscsi_node_wr {
     (((x) >> S_FW_ISCSI_NODE_WR_COMPL) & M_FW_ISCSI_NODE_WR_COMPL)
 #define F_FW_ISCSI_NODE_WR_COMPL	V_FW_ISCSI_NODE_WR_COMPL(1U)
 
-#endif
+#define FW_ISCSI_NODE_INVALID_ID	0xffffffff
+
+struct fw_scsi_iscsi_data {
+	__u8   r0;
+	__u8   fbit_to_tattr;
+	__be16 r2;
+	__be32 r3;
+	__u8   lun[8];
+	__be32 r4;
+	__be32 dlen;
+	__be32 r5;
+	__be32 r6;
+	__u8   cdb[16];
+};
+
+#define S_FW_SCSI_ISCSI_DATA_FBIT	7
+#define M_FW_SCSI_ISCSI_DATA_FBIT	0x1
+#define V_FW_SCSI_ISCSI_DATA_FBIT(x)	((x) << S_FW_SCSI_ISCSI_DATA_FBIT)
+#define G_FW_SCSI_ISCSI_DATA_FBIT(x)	\
+    (((x) >> S_FW_SCSI_ISCSI_DATA_FBIT) & M_FW_SCSI_ISCSI_DATA_FBIT)
+#define F_FW_SCSI_ISCSI_DATA_FBIT	V_FW_SCSI_ISCSI_DATA_FBIT(1U)
+
+#define S_FW_SCSI_ISCSI_DATA_RBIT	6
+#define M_FW_SCSI_ISCSI_DATA_RBIT	0x1
+#define V_FW_SCSI_ISCSI_DATA_RBIT(x)	((x) << S_FW_SCSI_ISCSI_DATA_RBIT)
+#define G_FW_SCSI_ISCSI_DATA_RBIT(x)	\
+    (((x) >> S_FW_SCSI_ISCSI_DATA_RBIT) & M_FW_SCSI_ISCSI_DATA_RBIT)
+#define F_FW_SCSI_ISCSI_DATA_RBIT	V_FW_SCSI_ISCSI_DATA_RBIT(1U)
+
+#define S_FW_SCSI_ISCSI_DATA_WBIT	5
+#define M_FW_SCSI_ISCSI_DATA_WBIT	0x1
+#define V_FW_SCSI_ISCSI_DATA_WBIT(x)	((x) << S_FW_SCSI_ISCSI_DATA_WBIT)
+#define G_FW_SCSI_ISCSI_DATA_WBIT(x)	\
+    (((x) >> S_FW_SCSI_ISCSI_DATA_WBIT) & M_FW_SCSI_ISCSI_DATA_WBIT)
+#define F_FW_SCSI_ISCSI_DATA_WBIT	V_FW_SCSI_ISCSI_DATA_WBIT(1U)
+
+#define S_FW_SCSI_ISCSI_DATA_TATTR	0
+#define M_FW_SCSI_ISCSI_DATA_TATTR	0x7
+#define V_FW_SCSI_ISCSI_DATA_TATTR(x)	((x) << S_FW_SCSI_ISCSI_DATA_TATTR)
+#define G_FW_SCSI_ISCSI_DATA_TATTR(x)	\
+    (((x) >> S_FW_SCSI_ISCSI_DATA_TATTR) & M_FW_SCSI_ISCSI_DATA_TATTR)
+
+#define FW_SCSI_ISCSI_DATA_TATTR_UNTAGGED	0
+#define FW_SCSI_ISCSI_DATA_TATTR_SIMPLE		1
+#define	FW_SCSI_ISCSI_DATA_TATTR_ORDERED	2
+#define FW_SCSI_ISCSI_DATA_TATTR_HEADOQ		3
+#define FW_SCSI_ISCSI_DATA_TATTR_ACA		4
+
+#define FW_SCSI_ISCSI_TMF_OP			0x02
+#define FW_SCSI_ISCSI_ABORT_FUNC		0x01
+#define FW_SCSI_ISCSI_LUN_RESET_FUNC		0x05
+#define FW_SCSI_ISCSI_RESERVED_TAG		0xffffffff
+
+struct fw_scsi_iscsi_rsp {
+	__u8   r0;
+	__u8   sbit_to_uflow;
+	__u8   response;
+	__u8   status;
+	__be32 r4;
+	__u8   r5[32];
+	__be32 bidir_res_cnt;
+	__be32 res_cnt;
+	__u8   sense_data[128];
+};
+
+#define S_FW_SCSI_ISCSI_RSP_SBIT	7
+#define M_FW_SCSI_ISCSI_RSP_SBIT	0x1
+#define V_FW_SCSI_ISCSI_RSP_SBIT(x)	((x) << S_FW_SCSI_ISCSI_RSP_SBIT)
+#define G_FW_SCSI_ISCSI_RSP_SBIT(x)	\
+    (((x) >> S_FW_SCSI_ISCSI_RSP_SBIT) & M_FW_SCSI_ISCSI_RSP_SBIT)
+#define F_FW_SCSI_ISCSI_RSP_SBIT	V_FW_SCSI_ISCSI_RSP_SBIT(1U)
+
+#define S_FW_SCSI_ISCSI_RSP_BIDIR_OFLOW		4
+#define M_FW_SCSI_ISCSI_RSP_BIDIR_OFLOW		0x1
+#define V_FW_SCSI_ISCSI_RSP_BIDIR_OFLOW(x)	\
+    ((x) << S_FW_SCSI_ISCSI_RSP_BIDIR_OFLOW)
+#define G_FW_SCSI_ISCSI_RSP_BIDIR_OFLOW(x)	\
+    (((x) >> S_FW_SCSI_ISCSI_RSP_BIDIR_OFLOW) & \
+     M_FW_SCSI_ISCSI_RSP_BIDIR_OFLOW)
+#define F_FW_SCSI_ISCSI_RSP_BIDIR_OFLOW	V_FW_SCSI_ISCSI_RSP_BIDIR_OFLOW(1U)
+
+#define S_FW_SCSI_ISCSI_RSP_BIDIR_UFLOW		3
+#define M_FW_SCSI_ISCSI_RSP_BIDIR_UFLOW		0x1
+#define V_FW_SCSI_ISCSI_RSP_BIDIR_UFLOW(x)	\
+    ((x) << S_FW_SCSI_ISCSI_RSP_BIDIR_UFLOW)
+#define G_FW_SCSI_ISCSI_RSP_BIDIR_UFLOW(x)	\
+    (((x) >> S_FW_SCSI_ISCSI_RSP_BIDIR_UFLOW) & \
+     M_FW_SCSI_ISCSI_RSP_BIDIR_UFLOW)
+#define F_FW_SCSI_ISCSI_RSP_BIDIR_UFLOW	V_FW_SCSI_ISCSI_RSP_BIDIR_UFLOW(1U)
+
+#define S_FW_SCSI_ISCSI_RSP_OFLOW	2
+#define M_FW_SCSI_ISCSI_RSP_OFLOW	0x1
+#define V_FW_SCSI_ISCSI_RSP_OFLOW(x)	((x) << S_FW_SCSI_ISCSI_RSP_OFLOW)
+#define G_FW_SCSI_ISCSI_RSP_OFLOW(x)	\
+    (((x) >> S_FW_SCSI_ISCSI_RSP_OFLOW) & M_FW_SCSI_ISCSI_RSP_OFLOW)
+#define F_FW_SCSI_ISCSI_RSP_OFLOW	V_FW_SCSI_ISCSI_RSP_OFLOW(1U)
+
+#define S_FW_SCSI_ISCSI_RSP_UFLOW	1
+#define M_FW_SCSI_ISCSI_RSP_UFLOW	0x1
+#define V_FW_SCSI_ISCSI_RSP_UFLOW(x)	((x) << S_FW_SCSI_ISCSI_RSP_UFLOW)
+#define G_FW_SCSI_ISCSI_RSP_UFLOW(x)	\
+    (((x) >> S_FW_SCSI_ISCSI_RSP_UFLOW) & M_FW_SCSI_ISCSI_RSP_UFLOW)
+#define F_FW_SCSI_ISCSI_RSP_UFLOW	V_FW_SCSI_ISCSI_RSP_UFLOW(1U)
 
 /******************************************************************************
  *  C O M M A N D s
@@ -1543,6 +1767,16 @@ struct fw_iscsi_node_wr {
  */
 #define FW_CMD_MAX_TIMEOUT	10000
 
+/*
+ * If a host driver does a HELLO and discovers that there's already a MASTER
+ * selected, we may have to wait for that MASTER to finish issuing RESET,
+ * configuration and INITIALIZE commands.  Also, there's a possibility that
+ * our own HELLO may get lost if it happens right as the MASTER is issuign a
+ * RESET command, so we need to be willing to make a few retries of our HELLO.
+ */
+#define FW_CMD_HELLO_TIMEOUT	(3 * FW_CMD_MAX_TIMEOUT)
+#define FW_CMD_HELLO_RETRIES	3
+
 enum fw_cmd_opcodes {
 	FW_LDST_CMD                    = 0x01,
 	FW_RESET_CMD                   = 0x03,
@@ -1575,10 +1809,11 @@ enum fw_cmd_opcodes {
 	FW_SCHED_CMD                   = 0x24,
 	FW_DEVLOG_CMD                  = 0x25,
 	FW_NETIF_CMD                   = 0x26,
+	FW_WATCHDOG_CMD                = 0x27,
+	FW_CLIP_CMD                    = 0x28,
 	FW_LASTC2E_CMD                 = 0x40,
 	FW_ERROR_CMD                   = 0x80,
 	FW_DEBUG_CMD                   = 0x81,
-
 };
 
 enum fw_cmd_cap {
@@ -1696,7 +1931,7 @@ struct fw_ldst_cmd {
 		} addrval;
 		struct fw_ldst_idctxt {
 			__be32 physid;
-			__be32 msg_pkd;
+			__be32 msg_ctxtflush;
 			__be32 ctxt_data7;
 			__be32 ctxt_data6;
 			__be32 ctxt_data5;
@@ -1769,6 +2004,13 @@ struct fw_ldst_cmd {
     (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG)
 #define F_FW_LDST_CMD_MSG	V_FW_LDST_CMD_MSG(1U)
 
+#define S_FW_LDST_CMD_CTXTFLUSH		30
+#define M_FW_LDST_CMD_CTXTFLUSH		0x1
+#define V_FW_LDST_CMD_CTXTFLUSH(x)	((x) << S_FW_LDST_CMD_CTXTFLUSH)
+#define G_FW_LDST_CMD_CTXTFLUSH(x)	\
+    (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH)
+#define F_FW_LDST_CMD_CTXTFLUSH	V_FW_LDST_CMD_CTXTFLUSH(1U)
+
 #define S_FW_LDST_CMD_PADDR	8
 #define M_FW_LDST_CMD_PADDR	0x1f
 #define V_FW_LDST_CMD_PADDR(x)	((x) << S_FW_LDST_CMD_PADDR)
@@ -1852,13 +2094,27 @@ struct fw_reset_cmd {
 	__be32 op_to_write;
 	__be32 retval_len16;
 	__be32 val;
-	__be32 r3;
+	__be32 halt_pkd;
+};
+
+#define S_FW_RESET_CMD_HALT	31
+#define M_FW_RESET_CMD_HALT	0x1
+#define V_FW_RESET_CMD_HALT(x)	((x) << S_FW_RESET_CMD_HALT)
+#define G_FW_RESET_CMD_HALT(x)	\
+    (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
+#define F_FW_RESET_CMD_HALT	V_FW_RESET_CMD_HALT(1U)
+
+enum {
+	FW_HELLO_CMD_STAGE_OS		= 0,
+	FW_HELLO_CMD_STAGE_PREOS0	= 1,
+	FW_HELLO_CMD_STAGE_PREOS1	= 2,
+	FW_HELLO_CMD_STAGE_POSTOS	= 3,
 };
 
 struct fw_hello_cmd {
 	__be32 op_to_write;
 	__be32 retval_len16;
-	__be32 err_to_mbasyncnot;
+	__be32 err_to_clearinit;
 	__be32 fwrev;
 };
 
@@ -1909,6 +2165,19 @@ struct fw_hello_cmd {
 #define G_FW_HELLO_CMD_MBASYNCNOT(x)	\
     (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
 
+#define S_FW_HELLO_CMD_STAGE	17
+#define M_FW_HELLO_CMD_STAGE	0x7
+#define V_FW_HELLO_CMD_STAGE(x)	((x) << S_FW_HELLO_CMD_STAGE)
+#define G_FW_HELLO_CMD_STAGE(x)	\
+    (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
+
+#define S_FW_HELLO_CMD_CLEARINIT	16
+#define M_FW_HELLO_CMD_CLEARINIT	0x1
+#define V_FW_HELLO_CMD_CLEARINIT(x)	((x) << S_FW_HELLO_CMD_CLEARINIT)
+#define G_FW_HELLO_CMD_CLEARINIT(x)	\
+    (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
+#define F_FW_HELLO_CMD_CLEARINIT	V_FW_HELLO_CMD_CLEARINIT(1U)
+
 struct fw_bye_cmd {
 	__be32 op_to_write;
 	__be32 retval_len16;
@@ -1989,6 +2258,8 @@ enum fw_caps_config_nic {
 	FW_CAPS_CONFIG_NIC		= 0x00000001,
 	FW_CAPS_CONFIG_NIC_VM		= 0x00000002,
 	FW_CAPS_CONFIG_NIC_IDS		= 0x00000004,
+	FW_CAPS_CONFIG_NIC_UM		= 0x00000008,
+	FW_CAPS_CONFIG_NIC_UM_ISGL	= 0x00000010,
 };
 
 enum fw_caps_config_toe {
@@ -2015,9 +2286,16 @@ enum fw_caps_config_fcoe {
 	FW_CAPS_CONFIG_FCOE_CTRL_OFLD   = 0x00000004,
 };
 
+enum fw_memtype_cf {
+	FW_MEMTYPE_CF_EDC0		= 0x0,
+	FW_MEMTYPE_CF_EDC1		= 0x1,
+	FW_MEMTYPE_CF_EXTMEM		= 0x2,
+	FW_MEMTYPE_CF_FLASH		= 0x4,
+};
+
 struct fw_caps_config_cmd {
 	__be32 op_to_write;
-	__be32 retval_len16;
+	__be32 cfvalid_to_len16;
 	__be32 r2;
 	__be32 hwmbitmap;
 	__be16 nbmcaps;
@@ -2030,9 +2308,33 @@ struct fw_caps_config_cmd {
 	__be16 r4;
 	__be16 iscsicaps;
 	__be16 fcoecaps;
-	__be32 r5;
-	__be64 r6;
-};
+	__be32 cfcsum;
+	__be32 finiver;
+	__be32 finicsum;
+};
+
+#define S_FW_CAPS_CONFIG_CMD_CFVALID	27
+#define M_FW_CAPS_CONFIG_CMD_CFVALID	0x1
+#define V_FW_CAPS_CONFIG_CMD_CFVALID(x)	((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)
+#define G_FW_CAPS_CONFIG_CMD_CFVALID(x)	\
+    (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
+#define F_FW_CAPS_CONFIG_CMD_CFVALID	V_FW_CAPS_CONFIG_CMD_CFVALID(1U)
+
+#define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF		24
+#define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF		0x7
+#define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x)	\
+    ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
+#define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x)	\
+    (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
+     M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
+
+#define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF	16
+#define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF	0xff
+#define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x)	\
+    ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
+#define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x)	\
+    (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
+     M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
 
 /*
  * params command mnemonics
@@ -2056,15 +2358,17 @@ enum fw_params_param_dev {
 						 * Lookup Engine
 						 */
 	FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
-	FW_PARAMS_PARAM_DEV_INTVER_NIC	= 0x04,
-	FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
-	FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
-	FW_PARAMS_PARAM_DEV_INTVER_RI	= 0x07,
-	FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
-	FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
-	FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A,
+	FW_PARAMS_PARAM_DEV_INTFVER_NIC	= 0x04,
+	FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05,
+	FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06,
+	FW_PARAMS_PARAM_DEV_INTFVER_RI	= 0x07,
+	FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08,
+	FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09,
+	FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A,
 	FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
 	FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
+	FW_PARAMS_PARAM_DEV_CF = 0x0D,
+	FW_PARAMS_PARAM_DEV_BYPASS = 0x0E,
 };
 
 /*
@@ -2119,6 +2423,23 @@ enum fw_params_param_dmaq {
 	FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
 };
 
+/*
+ * dev bypass parameters; actions and modes
+ */
+enum fw_params_param_dev_bypass {
+
+	/* actions
+	 */
+	FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00,
+	FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01,
+
+	/* modes
+	 */
+	FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00,
+	FW_PARAMS_PARAM_DEV_BYPASS_DROP	= 0x1,
+	FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2,
+};
+
 #define S_FW_PARAMS_MNEM	24
 #define M_FW_PARAMS_MNEM	0xff
 #define V_FW_PARAMS_MNEM(x)	((x) << S_FW_PARAMS_MNEM)
@@ -2271,6 +2592,7 @@ struct fw_pfvf_cmd {
 #define V_FW_PFVF_CMD_NETHCTRL(x)	((x) << S_FW_PFVF_CMD_NETHCTRL)
 #define G_FW_PFVF_CMD_NETHCTRL(x)	\
     (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
+
 /*
  *	ingress queue type; the first 1K ingress queues can have associated 0,
  *	1 or 2 free lists and an interrupt, all other ingress queues lack these
@@ -3518,6 +3840,7 @@ struct fw_eq_ofld_cmd {
 #define V_FW_EQ_OFLD_CMD_EQSIZE(x)	((x) << S_FW_EQ_OFLD_CMD_EQSIZE)
 #define G_FW_EQ_OFLD_CMD_EQSIZE(x)	\
     (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE)
+
 /* Macros for VIID parsing:
    VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */
 #define S_FW_VIID_PFN		8
@@ -4081,8 +4404,10 @@ enum fw_port_action {
 	FW_PORT_ACTION_L2_WOL_MODE_EN	= 0x0012,
 	FW_PORT_ACTION_LPBK_TO_NORMAL	= 0x0020,
 	FW_PORT_ACTION_L1_SS_LPBK_ASIC	= 0x0021,
+	FW_PORT_ACTION_MAC_LPBK		= 0x0022,
 	FW_PORT_ACTION_L1_WS_LPBK_ASIC	= 0x0023,
 	FW_PORT_ACTION_L1_EXT_LPBK      = 0x0026,
+	FW_PORT_ACTION_PCS_LPBK		= 0x0028,
 	FW_PORT_ACTION_PHY_RESET	= 0x0040,
 	FW_PORT_ACTION_PMA_RESET	= 0x0041,
 	FW_PORT_ACTION_PCS_RESET	= 0x0042,
@@ -4164,7 +4489,8 @@ struct fw_port_cmd {
 			struct fw_port_dcb_pgrate {
 				__u8   type;
 				__u8   apply_pkd;
-				__u8   r10_lo[6];
+				__u8   r10_lo[5];
+				__u8   num_tcs_supported;
 				__u8   pgrate[8];
 			} pgrate;
 			struct fw_port_dcb_priorate {
@@ -4181,11 +4507,12 @@ struct fw_port_cmd {
 			} pfc;
 			struct fw_port_app_priority {
 				__u8   type;
-				__u8   r10_lo[3];
-				__u8   prio;
-				__u8   sel;
+				__u8   r10[2];
+				__u8   idx;
+				__u8   user_prio_map;
+				__u8   sel_field;
 				__be16 protocolid;
-				__u8   r12[8];
+				__be64 r12;
 			} app_priority;
 		} dcb;
 	} u;
@@ -4337,20 +4664,6 @@ struct fw_port_cmd {
     (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY)
 #define F_FW_PORT_CMD_APPLY	V_FW_PORT_CMD_APPLY(1U)
 
-#define S_FW_PORT_CMD_APPLY	7
-#define M_FW_PORT_CMD_APPLY	0x1
-#define V_FW_PORT_CMD_APPLY(x)	((x) << S_FW_PORT_CMD_APPLY)
-#define G_FW_PORT_CMD_APPLY(x)	\
-    (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY)
-#define F_FW_PORT_CMD_APPLY	V_FW_PORT_CMD_APPLY(1U)
-
-#define S_FW_PORT_CMD_APPLY	7
-#define M_FW_PORT_CMD_APPLY	0x1
-#define V_FW_PORT_CMD_APPLY(x)	((x) << S_FW_PORT_CMD_APPLY)
-#define G_FW_PORT_CMD_APPLY(x)	\
-    (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY)
-#define F_FW_PORT_CMD_APPLY	V_FW_PORT_CMD_APPLY(1U)
-
 /*
  *	These are configured into the VPD and hence tools that generate
  *	VPD may use this enumeration.
@@ -4383,6 +4696,7 @@ enum fw_port_module_type {
 	FW_PORT_MOD_TYPE_TWINAX_PASSIVE	= 0x4,
 	FW_PORT_MOD_TYPE_TWINAX_ACTIVE	= 0x5,
 	FW_PORT_MOD_TYPE_LRM		= 0x6,
+	FW_PORT_MOD_TYPE_ERROR		= M_FW_PORT_CMD_MODTYPE - 3,
 	FW_PORT_MOD_TYPE_UNKNOWN	= M_FW_PORT_CMD_MODTYPE - 2,
 	FW_PORT_MOD_TYPE_NOTSUPPORTED	= M_FW_PORT_CMD_MODTYPE - 1,
 	FW_PORT_MOD_TYPE_NONE		= M_FW_PORT_CMD_MODTYPE
@@ -5189,15 +5503,12 @@ struct fw_rss_vi_config_cmd {
 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN	\
     V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)
 
-#define S_FW_RSS_VI_CONFIG_CMD_UDPEN		0
-#define M_FW_RSS_VI_CONFIG_CMD_UDPEN		0x1
-#define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x)		\
-    ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
-#define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x)		\
-    (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & \
-     M_FW_RSS_VI_CONFIG_CMD_UDPEN)
-#define F_FW_RSS_VI_CONFIG_CMD_UDPEN		\
-    V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
+#define S_FW_RSS_VI_CONFIG_CMD_UDPEN	0
+#define M_FW_RSS_VI_CONFIG_CMD_UDPEN	0x1
+#define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x)	((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
+#define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x)	\
+    (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
+#define F_FW_RSS_VI_CONFIG_CMD_UDPEN	V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
 
 enum fw_sched_sc {
 	FW_SCHED_SC_CONFIG		= 0,
@@ -5352,103 +5663,97 @@ struct fw_devlog_cmd {
      M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG)
 
 struct fw_netif_cmd {
-	__be32 op_portid;
-	__be32 retval_to_len16;
-	__be32 add_to_ipv4gw;
-	__be32 vlanid_mtuval;
+	__be32 op_to_ipv4gw;
+	__be32 retval_len16;
+	__be32 netifi_ifadridx;
+	__be32 portid_to_mtuval;
 	__be32 gwaddr;
 	__be32 addr;
 	__be32 nmask;
 	__be32 bcaddr;
 };
 
-#define S_FW_NETIF_CMD_PORTID		0
-#define M_FW_NETIF_CMD_PORTID		0xf
-#define V_FW_NETIF_CMD_PORTID(x)	((x) << S_FW_NETIF_CMD_PORTID)
-#define G_FW_NETIF_CMD_PORTID(x)	\
-    (((x) >> S_FW_NETIF_CMD_PORTID) & M_FW_NETIF_CMD_PORTID)
-
-#define S_FW_NETIF_CMD_RETVAL		24
-#define M_FW_NETIF_CMD_RETVAL		0xff
-#define V_FW_NETIF_CMD_RETVAL(x)	((x) << S_FW_NETIF_CMD_RETVAL)
-#define G_FW_NETIF_CMD_RETVAL(x)	\
-    (((x) >> S_FW_NETIF_CMD_RETVAL) & M_FW_NETIF_CMD_RETVAL)
-
-#define S_FW_NETIF_CMD_IFIDX	16
-#define M_FW_NETIF_CMD_IFIDX	0xff
-#define V_FW_NETIF_CMD_IFIDX(x)	((x) << S_FW_NETIF_CMD_IFIDX)
-#define G_FW_NETIF_CMD_IFIDX(x)	\
-    (((x) >> S_FW_NETIF_CMD_IFIDX) & M_FW_NETIF_CMD_IFIDX)
-
-#define S_FW_NETIF_CMD_LEN16	0
-#define M_FW_NETIF_CMD_LEN16	0xff
-#define V_FW_NETIF_CMD_LEN16(x)	((x) << S_FW_NETIF_CMD_LEN16)
-#define G_FW_NETIF_CMD_LEN16(x)	\
-    (((x) >> S_FW_NETIF_CMD_LEN16) & M_FW_NETIF_CMD_LEN16)
-
-#define S_FW_NETIF_CMD_ADD	31
+#define S_FW_NETIF_CMD_ADD	20
 #define M_FW_NETIF_CMD_ADD	0x1
 #define V_FW_NETIF_CMD_ADD(x)	((x) << S_FW_NETIF_CMD_ADD)
 #define G_FW_NETIF_CMD_ADD(x)	\
     (((x) >> S_FW_NETIF_CMD_ADD) & M_FW_NETIF_CMD_ADD)
 #define F_FW_NETIF_CMD_ADD	V_FW_NETIF_CMD_ADD(1U)
 
-#define S_FW_NETIF_CMD_LINK	30
+#define S_FW_NETIF_CMD_LINK	19
 #define M_FW_NETIF_CMD_LINK	0x1
 #define V_FW_NETIF_CMD_LINK(x)	((x) << S_FW_NETIF_CMD_LINK)
 #define G_FW_NETIF_CMD_LINK(x)	\
     (((x) >> S_FW_NETIF_CMD_LINK) & M_FW_NETIF_CMD_LINK)
 #define F_FW_NETIF_CMD_LINK	V_FW_NETIF_CMD_LINK(1U)
 
-#define S_FW_NETIF_CMD_VLAN	29
+#define S_FW_NETIF_CMD_VLAN	18
 #define M_FW_NETIF_CMD_VLAN	0x1
 #define V_FW_NETIF_CMD_VLAN(x)	((x) << S_FW_NETIF_CMD_VLAN)
 #define G_FW_NETIF_CMD_VLAN(x)	\
     (((x) >> S_FW_NETIF_CMD_VLAN) & M_FW_NETIF_CMD_VLAN)
 #define F_FW_NETIF_CMD_VLAN	V_FW_NETIF_CMD_VLAN(1U)
 
-#define S_FW_NETIF_CMD_MTU	28
+#define S_FW_NETIF_CMD_MTU	17
 #define M_FW_NETIF_CMD_MTU	0x1
 #define V_FW_NETIF_CMD_MTU(x)	((x) << S_FW_NETIF_CMD_MTU)
 #define G_FW_NETIF_CMD_MTU(x)	\
     (((x) >> S_FW_NETIF_CMD_MTU) & M_FW_NETIF_CMD_MTU)
 #define F_FW_NETIF_CMD_MTU	V_FW_NETIF_CMD_MTU(1U)
 
-#define S_FW_NETIF_CMD_DHCP	27
+#define S_FW_NETIF_CMD_DHCP	16
 #define M_FW_NETIF_CMD_DHCP	0x1
 #define V_FW_NETIF_CMD_DHCP(x)	((x) << S_FW_NETIF_CMD_DHCP)
 #define G_FW_NETIF_CMD_DHCP(x)	\
     (((x) >> S_FW_NETIF_CMD_DHCP) & M_FW_NETIF_CMD_DHCP)
 #define F_FW_NETIF_CMD_DHCP	V_FW_NETIF_CMD_DHCP(1U)
 
-#define S_FW_NETIF_CMD_IPV4BCADDR	3
+#define S_FW_NETIF_CMD_IPV4BCADDR	15
 #define M_FW_NETIF_CMD_IPV4BCADDR	0x1
 #define V_FW_NETIF_CMD_IPV4BCADDR(x)	((x) << S_FW_NETIF_CMD_IPV4BCADDR)
 #define G_FW_NETIF_CMD_IPV4BCADDR(x)	\
     (((x) >> S_FW_NETIF_CMD_IPV4BCADDR) & M_FW_NETIF_CMD_IPV4BCADDR)
 #define F_FW_NETIF_CMD_IPV4BCADDR	V_FW_NETIF_CMD_IPV4BCADDR(1U)
 
-#define S_FW_NETIF_CMD_IPV4NMASK	2
+#define S_FW_NETIF_CMD_IPV4NMASK	14
 #define M_FW_NETIF_CMD_IPV4NMASK	0x1
 #define V_FW_NETIF_CMD_IPV4NMASK(x)	((x) << S_FW_NETIF_CMD_IPV4NMASK)
 #define G_FW_NETIF_CMD_IPV4NMASK(x)	\
     (((x) >> S_FW_NETIF_CMD_IPV4NMASK) & M_FW_NETIF_CMD_IPV4NMASK)
 #define F_FW_NETIF_CMD_IPV4NMASK	V_FW_NETIF_CMD_IPV4NMASK(1U)
 
-#define S_FW_NETIF_CMD_IPV4ADDR		1
+#define S_FW_NETIF_CMD_IPV4ADDR		13
 #define M_FW_NETIF_CMD_IPV4ADDR		0x1
 #define V_FW_NETIF_CMD_IPV4ADDR(x)	((x) << S_FW_NETIF_CMD_IPV4ADDR)
 #define G_FW_NETIF_CMD_IPV4ADDR(x)	\
     (((x) >> S_FW_NETIF_CMD_IPV4ADDR) & M_FW_NETIF_CMD_IPV4ADDR)
 #define F_FW_NETIF_CMD_IPV4ADDR	V_FW_NETIF_CMD_IPV4ADDR(1U)
 
-#define S_FW_NETIF_CMD_IPV4GW		0
+#define S_FW_NETIF_CMD_IPV4GW		12
 #define M_FW_NETIF_CMD_IPV4GW		0x1
 #define V_FW_NETIF_CMD_IPV4GW(x)	((x) << S_FW_NETIF_CMD_IPV4GW)
 #define G_FW_NETIF_CMD_IPV4GW(x)	\
     (((x) >> S_FW_NETIF_CMD_IPV4GW) & M_FW_NETIF_CMD_IPV4GW)
 #define F_FW_NETIF_CMD_IPV4GW	V_FW_NETIF_CMD_IPV4GW(1U)
 
+#define S_FW_NETIF_CMD_NETIFI		8
+#define M_FW_NETIF_CMD_NETIFI		0xffffff
+#define V_FW_NETIF_CMD_NETIFI(x)	((x) << S_FW_NETIF_CMD_NETIFI)
+#define G_FW_NETIF_CMD_NETIFI(x)	\
+    (((x) >> S_FW_NETIF_CMD_NETIFI) & M_FW_NETIF_CMD_NETIFI)
+
+#define S_FW_NETIF_CMD_IFADRIDX		0
+#define M_FW_NETIF_CMD_IFADRIDX		0xff
+#define V_FW_NETIF_CMD_IFADRIDX(x)	((x) << S_FW_NETIF_CMD_IFADRIDX)
+#define G_FW_NETIF_CMD_IFADRIDX(x)	\
+    (((x) >> S_FW_NETIF_CMD_IFADRIDX) & M_FW_NETIF_CMD_IFADRIDX)
+
+#define S_FW_NETIF_CMD_PORTID		28
+#define M_FW_NETIF_CMD_PORTID		0xf
+#define V_FW_NETIF_CMD_PORTID(x)	((x) << S_FW_NETIF_CMD_PORTID)
+#define G_FW_NETIF_CMD_PORTID(x)	\
+    (((x) >> S_FW_NETIF_CMD_PORTID) & M_FW_NETIF_CMD_PORTID)
+
 #define S_FW_NETIF_CMD_VLANID		16
 #define M_FW_NETIF_CMD_VLANID		0xfff
 #define V_FW_NETIF_CMD_VLANID(x)	((x) << S_FW_NETIF_CMD_VLANID)
@@ -5461,6 +5766,42 @@ struct fw_netif_cmd {
 #define G_FW_NETIF_CMD_MTUVAL(x)	\
     (((x) >> S_FW_NETIF_CMD_MTUVAL) & M_FW_NETIF_CMD_MTUVAL)
 
+enum fw_watchdog_actions {
+	FW_WATCHDOG_ACTION_FLR = 0x1,
+	FW_WATCHDOG_ACTION_BYPASS = 0x2,
+};
+
+#define FW_WATCHDOG_MAX_TIMEOUT_SECS	60
+
+struct fw_watchdog_cmd {
+	__be32 op_to_write;
+	__be32 retval_len16;
+	__be32 timeout;
+	__be32 actions;
+};
+
+struct fw_clip_cmd {
+	__be32 op_to_write;
+	__be32 alloc_to_len16;
+	__be64 ip_hi;
+	__be64 ip_lo;
+	__be32 r4[2];
+};
+
+#define S_FW_CLIP_CMD_ALLOC	31
+#define M_FW_CLIP_CMD_ALLOC	0x1
+#define V_FW_CLIP_CMD_ALLOC(x)	((x) << S_FW_CLIP_CMD_ALLOC)
+#define G_FW_CLIP_CMD_ALLOC(x)	\
+    (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC)
+#define F_FW_CLIP_CMD_ALLOC	V_FW_CLIP_CMD_ALLOC(1U)
+
+#define S_FW_CLIP_CMD_FREE	30
+#define M_FW_CLIP_CMD_FREE	0x1
+#define V_FW_CLIP_CMD_FREE(x)	((x) << S_FW_CLIP_CMD_FREE)
+#define G_FW_CLIP_CMD_FREE(x)	\
+    (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE)
+#define F_FW_CLIP_CMD_FREE	V_FW_CLIP_CMD_FREE(1U)
+
 enum fw_error_type {
 	FW_ERROR_TYPE_EXCEPTION		= 0x0,
 	FW_ERROR_TYPE_HWMODULE		= 0x1,
@@ -5570,6 +5911,94 @@ struct fw_debug_cmd {
 #define G_FW_DEBUG_CMD_TYPE(x)	\
     (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
 
+
+/******************************************************************************
+ *   P C I E   F W   R E G I S T E R
+ **************************************/
+
+/**
+ *	Register definitions for the PCIE_FW register which the firmware uses
+ *	to retain status across RESETs.  This register should be considered
+ *	as a READ-ONLY register for Host Software and only to be used to
+ *	track firmware initialization/error state, etc.
+ */
+#define S_PCIE_FW_ERR		31
+#define M_PCIE_FW_ERR		0x1
+#define V_PCIE_FW_ERR(x)	((x) << S_PCIE_FW_ERR)
+#define G_PCIE_FW_ERR(x)	(((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)
+#define F_PCIE_FW_ERR		V_PCIE_FW_ERR(1U)
+
+#define S_PCIE_FW_INIT		30
+#define M_PCIE_FW_INIT		0x1
+#define V_PCIE_FW_INIT(x)	((x) << S_PCIE_FW_INIT)
+#define G_PCIE_FW_INIT(x)	(((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)
+#define F_PCIE_FW_INIT		V_PCIE_FW_INIT(1U)
+
+#define S_PCIE_FW_HALT          29
+#define M_PCIE_FW_HALT          0x1
+#define V_PCIE_FW_HALT(x)       ((x) << S_PCIE_FW_HALT)
+#define G_PCIE_FW_HALT(x)       (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
+#define F_PCIE_FW_HALT          V_PCIE_FW_HALT(1U)
+
+#define S_PCIE_FW_STAGE		21
+#define M_PCIE_FW_STAGE		0x7
+#define V_PCIE_FW_STAGE(x)	((x) << S_PCIE_FW_STAGE)
+#define G_PCIE_FW_STAGE(x)	(((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE)
+
+#define S_PCIE_FW_ASYNCNOT_VLD	20
+#define M_PCIE_FW_ASYNCNOT_VLD	0x1
+#define V_PCIE_FW_ASYNCNOT_VLD(x) \
+    ((x) << S_PCIE_FW_ASYNCNOT_VLD)
+#define G_PCIE_FW_ASYNCNOT_VLD(x) \
+    (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD)
+#define F_PCIE_FW_ASYNCNOT_VLD	V_PCIE_FW_ASYNCNOT_VLD(1U)
+
+#define S_PCIE_FW_ASYNCNOTINT	19
+#define M_PCIE_FW_ASYNCNOTINT	0x1
+#define V_PCIE_FW_ASYNCNOTINT(x) \
+    ((x) << S_PCIE_FW_ASYNCNOTINT)
+#define G_PCIE_FW_ASYNCNOTINT(x) \
+    (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT)
+#define F_PCIE_FW_ASYNCNOTINT	V_PCIE_FW_ASYNCNOTINT(1U)
+
+#define S_PCIE_FW_ASYNCNOT	16
+#define M_PCIE_FW_ASYNCNOT	0x7
+#define V_PCIE_FW_ASYNCNOT(x)	((x) << S_PCIE_FW_ASYNCNOT)
+#define G_PCIE_FW_ASYNCNOT(x)	\
+    (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT)
+
+#define S_PCIE_FW_MASTER_VLD	15
+#define M_PCIE_FW_MASTER_VLD	0x1
+#define V_PCIE_FW_MASTER_VLD(x)	((x) << S_PCIE_FW_MASTER_VLD)
+#define G_PCIE_FW_MASTER_VLD(x)	\
+    (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
+#define F_PCIE_FW_MASTER_VLD	V_PCIE_FW_MASTER_VLD(1U)
+
+#define S_PCIE_FW_MASTER	12
+#define M_PCIE_FW_MASTER	0x7
+#define V_PCIE_FW_MASTER(x)	((x) << S_PCIE_FW_MASTER)
+#define G_PCIE_FW_MASTER(x)	(((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)
+
+#define S_PCIE_FW_RESET_VLD		11
+#define M_PCIE_FW_RESET_VLD		0x1
+#define V_PCIE_FW_RESET_VLD(x)	((x) << S_PCIE_FW_RESET_VLD)
+#define G_PCIE_FW_RESET_VLD(x)	\
+    (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD)
+#define F_PCIE_FW_RESET_VLD	V_PCIE_FW_RESET_VLD(1U)
+
+#define S_PCIE_FW_RESET		8
+#define M_PCIE_FW_RESET		0x7
+#define V_PCIE_FW_RESET(x)	((x) << S_PCIE_FW_RESET)
+#define G_PCIE_FW_RESET(x)	\
+    (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET)
+
+#define S_PCIE_FW_REGISTERED	0
+#define M_PCIE_FW_REGISTERED	0xff
+#define V_PCIE_FW_REGISTERED(x)	((x) << S_PCIE_FW_REGISTERED)
+#define G_PCIE_FW_REGISTERED(x)	\
+    (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED)
+
+
 /******************************************************************************
  *   B I N A R Y   H E A D E R   F O R M A T
  **********************************************/
@@ -5579,7 +6008,7 @@ struct fw_debug_cmd {
  */
 struct fw_hdr {
 	__u8	ver;
-	__u8	reserved1;
+	__u8	chip;			/* terminator chip family */
 	__be16	len512;			/* bin length in units of 512-bytes */
 	__be32	fw_ver;			/* firmware version */
 	__be32	tp_microcode_ver;	/* tcp processor microcode version */
@@ -5591,7 +6020,16 @@ struct fw_hdr {
 	__u8	intfver_iscsi;
 	__u8	intfver_fcoe;
 	__u8	reserved2;
-	__be32	reserved3[27];
+	__u32	reserved3;
+	__u32	reserved4;
+	__u32	reserved5;
+	__be32	flags;
+	__be32	reserved6[23];
+};
+
+enum fw_hdr_chip {
+	FW_HDR_CHIP_T4,
+	FW_HDR_CHIP_T5
 };
 
 #define S_FW_HDR_FW_VER_MAJOR	24
@@ -5622,4 +6060,18 @@ struct fw_hdr {
 #define G_FW_HDR_FW_VER_BUILD(x) \
     (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
 
+enum fw_hdr_intfver {
+	FW_HDR_INTFVER_NIC	= 0x00,
+	FW_HDR_INTFVER_VNIC	= 0x00,
+	FW_HDR_INTFVER_OFLD	= 0x00,
+	FW_HDR_INTFVER_RI	= 0x00,
+	FW_HDR_INTFVER_ISCSIPDU	= 0x00,
+	FW_HDR_INTFVER_ISCSI	= 0x00,
+	FW_HDR_INTFVER_FCOE	= 0x00,
+};
+
+enum fw_hdr_flags {
+	FW_HDR_FLAGS_RESET_HALT	= 0x00000001,
+};
+
 #endif /* _T4FW_INTERFACE_H_ */
diff --git a/sys/dev/cxgbe/offload.h b/sys/dev/cxgbe/offload.h
index f31b840..f6ada9d 100644
--- a/sys/dev/cxgbe/offload.h
+++ b/sys/dev/cxgbe/offload.h
@@ -31,15 +31,18 @@
 #ifndef __T4_OFFLOAD_H__
 #define __T4_OFFLOAD_H__
 
-/* CPL message priority levels */
-enum {
-	CPL_PRIORITY_DATA     = 0,  /* data messages */
-	CPL_PRIORITY_SETUP    = 1,  /* connection setup messages */
-	CPL_PRIORITY_TEARDOWN = 0,  /* connection teardown messages */
-	CPL_PRIORITY_LISTEN   = 1,  /* listen start/stop messages */
-	CPL_PRIORITY_ACK      = 1,  /* RX ACK messages */
-	CPL_PRIORITY_CONTROL  = 1   /* control messages */
-};
+/* XXX: flagrant misuse of mbuf fields (during tx by TOM) */
+#define MBUF_EQ(m)		(*((void **)(&(m)->m_pkthdr.rcvif)))
+/* These have to work for !M_PKTHDR so we use a field from m_hdr. */
+#define MBUF_TX_CREDITS(m)	((m)->m_hdr.pad[0])
+#define MBUF_DMA_MAPPED(m)	((m)->m_hdr.pad[1])
+
+#define INIT_ULPTX_WR(w, wrlen, atomic, tid) do { \
+	(w)->wr.wr_hi = htonl(V_FW_WR_OP(FW_ULPTX_WR) | V_FW_WR_ATOMIC(atomic)); \
+	(w)->wr.wr_mid = htonl(V_FW_WR_LEN16(DIV_ROUND_UP(wrlen, 16)) | \
+			       V_FW_WR_FLOWID(tid)); \
+	(w)->wr.wr_lo = cpu_to_be64(0); \
+} while (0)
 
 #define INIT_TP_WR(w, tid) do { \
 	(w)->wr.wr_hi = htonl(V_FW_WR_OP(FW_TP_WR) | \
@@ -49,13 +52,19 @@ enum {
 	(w)->wr.wr_lo = cpu_to_be64(0); \
 } while (0)
 
+#define INIT_TP_WR_MIT_CPL(w, cpl, tid) do { \
+	INIT_TP_WR(w, tid); \
+	OPCODE_TID(w) = htonl(MK_OPCODE_TID(cpl, tid)); \
+} while (0)
+
 /*
  * Max # of ATIDs.  The absolute HW max is 16K but we keep it lower.
  */
 #define MAX_ATIDS 8192U
 
-struct serv_entry {
+union serv_entry {
 	void *data;
+	union serv_entry *next;
 };
 
 union aopen_entry {
@@ -71,8 +80,7 @@ struct tid_info {
 	void **tid_tab;
 	unsigned int ntids;
 
-	struct serv_entry *stid_tab;
-	unsigned long *stid_bmap;
+	union serv_entry *stid_tab;
 	unsigned int nstids;
 	unsigned int stid_base;
 
@@ -84,10 +92,15 @@ struct tid_info {
 	unsigned int ftid_base;
 	unsigned int ftids_in_use;
 
+	struct mtx atid_lock;
 	union aopen_entry *afree;
 	unsigned int atids_in_use;
 
+	struct mtx stid_lock;
+	union serv_entry *sfree;
 	unsigned int stids_in_use;
+
+	unsigned int tids_in_use;
 };
 
 struct t4_range {
@@ -101,6 +114,40 @@ struct t4_virt_res {                      /* virtualized HW resources */
 	struct t4_range stag;
 	struct t4_range rq;
 	struct t4_range pbl;
+	struct t4_range qp;
+	struct t4_range cq;
+	struct t4_range ocq;
 };
 
+#ifndef TCP_OFFLOAD_DISABLE
+enum {
+	ULD_TOM = 1,
+};
+
+struct adapter;
+struct port_info;
+struct uld_info {
+	SLIST_ENTRY(uld_info) link;
+	int refcount;
+	int uld_id;
+	int (*attach)(struct adapter *, void **);
+	int (*detach)(void *);
+};
+
+struct uld_softc {
+	struct uld_info *uld;
+	void *softc;
+};
+
+struct tom_tunables {
+	int sndbuf;
+	int ddp;
+	int indsz;
+	int ddp_thres;
+};
+
+int t4_register_uld(struct uld_info *);
+int t4_unregister_uld(struct uld_info *);
+#endif
+
 #endif
diff --git a/sys/dev/cxgbe/osdep.h b/sys/dev/cxgbe/osdep.h
index bde1eb4..40ed61b 100644
--- a/sys/dev/cxgbe/osdep.h
+++ b/sys/dev/cxgbe/osdep.h
@@ -70,9 +70,11 @@ typedef uint64_t __be64;
 #error "Must set BYTE_ORDER"
 #endif
 
+#ifndef __bool_true_false_are_defined
 typedef boolean_t bool;
 #define false FALSE
 #define true TRUE
+#endif
 
 #define mdelay(x) DELAY((x) * 1000)
 #define udelay(x) DELAY(x)
@@ -122,6 +124,7 @@ typedef boolean_t bool;
 #define PCI_EXP_LNKSTA		PCIR_EXPRESS_LINK_STA
 #define PCI_EXP_LNKSTA_CLS	PCIM_LINK_STA_SPEED
 #define PCI_EXP_LNKSTA_NLW	PCIM_LINK_STA_WIDTH
+#define PCI_EXP_DEVCTL2		0x28
 
 static inline int
 ilog2(long x)
diff --git a/sys/dev/cxgbe/t4_ioctl.h b/sys/dev/cxgbe/t4_ioctl.h
index ecc2c3d..2a3fa39 100644
--- a/sys/dev/cxgbe/t4_ioctl.h
+++ b/sys/dev/cxgbe/t4_ioctl.h
@@ -47,6 +47,8 @@ enum {
 	T4_SET_FILTER,			/* program a filter */
 	T4_DEL_FILTER,			/* delete a filter */
 	T4_GET_SGE_CONTEXT,		/* get SGE context for a queue */
+	T4_LOAD_FW,			/* flash firmware */
+	T4_GET_MEM,			/* read memory */
 };
 
 struct t4_reg {
@@ -62,6 +64,11 @@ struct t4_regdump {
 	uint32_t *data;
 };
 
+struct t4_data {
+	uint32_t len;
+	uint8_t *data;
+};
+
 /*
  * A hardware filter is some valid combination of these.
  */
@@ -73,8 +80,8 @@ struct t4_regdump {
 #define T4_FILTER_IP_DPORT	0x20	/* Destination IP port */
 #define T4_FILTER_FCoE		0x40	/* Fibre Channel over Ethernet packet */
 #define T4_FILTER_PORT		0x80	/* Physical ingress port */
-#define T4_FILTER_OVLAN		0x100	/* Outer VLAN ID */
-#define T4_FILTER_IVLAN		0x200	/* Inner VLAN ID */
+#define T4_FILTER_VNIC		0x100	/* VNIC id or outer VLAN */
+#define T4_FILTER_VLAN		0x200	/* VLAN ID */
 #define T4_FILTER_IP_TOS	0x400	/* IPv4 TOS/IPv6 Traffic Class */
 #define T4_FILTER_IP_PROTO	0x800	/* IP protocol */
 #define T4_FILTER_ETH_TYPE	0x1000	/* Ethernet Type */
@@ -131,8 +138,8 @@ struct t4_filter_tuple {
 	 * is used to select the global mode and all filters are limited to the
 	 * set of fields allowed by the global mode.
 	 */
-	uint16_t ovlan;		/* outer VLAN */
-	uint16_t ivlan;		/* inner VLAN */
+	uint16_t vnic;		/* VNIC id or outer VLAN tag */
+	uint16_t vlan;		/* VLAN tag */
 	uint16_t ethtype;	/* Ethernet type */
 	uint8_t  tos;		/* TOS/Traffic Type */
 	uint8_t  proto;		/* protocol type */
@@ -141,8 +148,8 @@ struct t4_filter_tuple {
 	uint32_t matchtype:3;	/* MPS match type */
 	uint32_t frag:1;	/* fragmentation extension header */
 	uint32_t macidx:9;	/* exact match MAC index */
-	uint32_t ivlan_vld:1;	/* inner VLAN valid */
-	uint32_t ovlan_vld:1;	/* outer VLAN valid */
+	uint32_t vlan_vld:1;	/* VLAN valid */
+	uint32_t vnic_vld:1;	/* VNIC id/outer VLAN tag valid */
 };
 
 struct t4_filter_specification {
@@ -199,6 +206,12 @@ struct t4_sge_context {
 	uint32_t data[T4_SGE_CONTEXT_SIZE / 4];
 };
 
+struct t4_mem_range {
+	uint32_t addr;
+	uint32_t len;
+	uint32_t *data;
+};
+
 #define CHELSIO_T4_GETREG	_IOWR('f', T4_GETREG, struct t4_reg)
 #define CHELSIO_T4_SETREG	_IOW('f', T4_SETREG, struct t4_reg)
 #define CHELSIO_T4_REGDUMP	_IOWR('f', T4_REGDUMP, struct t4_regdump)
@@ -209,4 +222,6 @@ struct t4_sge_context {
 #define CHELSIO_T4_DEL_FILTER	_IOW('f', T4_DEL_FILTER, struct t4_filter)
 #define CHELSIO_T4_GET_SGE_CONTEXT _IOWR('f', T4_GET_SGE_CONTEXT, \
     struct t4_sge_context)
+#define CHELSIO_T4_LOAD_FW	_IOW('f', T4_LOAD_FW, struct t4_data)
+#define CHELSIO_T4_GET_MEM	_IOW('f', T4_GET_MEM, struct t4_mem_range)
 #endif
diff --git a/sys/dev/cxgbe/t4_l2t.c b/sys/dev/cxgbe/t4_l2t.c
index 31197b8..be206c1 100644
--- a/sys/dev/cxgbe/t4_l2t.c
+++ b/sys/dev/cxgbe/t4_l2t.c
@@ -37,7 +37,9 @@ __FBSDID("$FreeBSD$");
 #include <sys/mutex.h>
 #include <sys/rwlock.h>
 #include <sys/socket.h>
+#include <sys/sbuf.h>
 #include <net/if.h>
+#include <net/if_types.h>
 #include <net/ethernet.h>
 #include <net/if_vlan_var.h>
 #include <net/if_dl.h>
@@ -50,9 +52,26 @@ __FBSDID("$FreeBSD$");
 #include "common/common.h"
 #include "common/jhash.h"
 #include "common/t4_msg.h"
-#include "offload.h"
 #include "t4_l2t.h"
 
+/*
+ * Module locking notes:  There is a RW lock protecting the L2 table as a
+ * whole plus a spinlock per L2T entry.  Entry lookups and allocations happen
+ * under the protection of the table lock, individual entry changes happen
+ * while holding that entry's spinlock.  The table lock nests outside the
+ * entry locks.  Allocations of new entries take the table lock as writers so
+ * no other lookups can happen while allocating new entries.  Entry updates
+ * take the table lock as readers so multiple entries can be updated in
+ * parallel.  An L2T entry can be dropped by decrementing its reference count
+ * and therefore can happen in parallel with entry allocation but no entry
+ * can change state or increment its ref count during allocation as both of
+ * these perform lookups.
+ *
+ * Note: We do not take refereces to ifnets in this module because both
+ * the TOE and the sockets already hold references to the interfaces and the
+ * lifetime of an L2T entry is fully contained in the lifetime of the TOE.
+ */
+
 /* identifies sync vs async L2T_WRITE_REQs */
 #define S_SYNC_WR    12
 #define V_SYNC_WR(x) ((x) << S_SYNC_WR)
@@ -76,34 +95,251 @@ struct l2t_data {
 	struct l2t_entry l2tab[L2T_SIZE];
 };
 
+static int do_l2t_write_rpl(struct sge_iq *, const struct rss_header *,
+    struct mbuf *);
+
+#define VLAN_NONE	0xfff
+#define SA(x)           ((struct sockaddr *)(x))
+#define SIN(x)          ((struct sockaddr_in *)(x))
+#define SINADDR(x)      (SIN(x)->sin_addr.s_addr)
+
 /*
- * Module locking notes:  There is a RW lock protecting the L2 table as a
- * whole plus a spinlock per L2T entry.  Entry lookups and allocations happen
- * under the protection of the table lock, individual entry changes happen
- * while holding that entry's spinlock.  The table lock nests outside the
- * entry locks.  Allocations of new entries take the table lock as writers so
- * no other lookups can happen while allocating new entries.  Entry updates
- * take the table lock as readers so multiple entries can be updated in
- * parallel.  An L2T entry can be dropped by decrementing its reference count
- * and therefore can happen in parallel with entry allocation but no entry
- * can change state or increment its ref count during allocation as both of
- * these perform lookups.
- *
- * Note: We do not take refereces to ifnets in this module because both
- * the TOE and the sockets already hold references to the interfaces and the
- * lifetime of an L2T entry is fully contained in the lifetime of the TOE.
+ * Allocate a free L2T entry.  Must be called with l2t_data.lock held.
  */
+static struct l2t_entry *
+alloc_l2e(struct l2t_data *d)
+{
+	struct l2t_entry *end, *e, **p;
+
+	rw_assert(&d->lock, RA_WLOCKED);
+
+	if (!atomic_load_acq_int(&d->nfree))
+		return (NULL);
+
+	/* there's definitely a free entry */
+	for (e = d->rover, end = &d->l2tab[L2T_SIZE]; e != end; ++e)
+		if (atomic_load_acq_int(&e->refcnt) == 0)
+			goto found;
+
+	for (e = d->l2tab; atomic_load_acq_int(&e->refcnt); ++e) ;
+found:
+	d->rover = e + 1;
+	atomic_subtract_int(&d->nfree, 1);
+
+	/*
+	 * The entry we found may be an inactive entry that is
+	 * presently in the hash table.  We need to remove it.
+	 */
+	if (e->state < L2T_STATE_SWITCHING) {
+		for (p = &d->l2tab[e->hash].first; *p; p = &(*p)->next) {
+			if (*p == e) {
+				*p = e->next;
+				e->next = NULL;
+				break;
+			}
+		}
+	}
+
+	e->state = L2T_STATE_UNUSED;
+	return (e);
+}
+
+/*
+ * Write an L2T entry.  Must be called with the entry locked.
+ * The write may be synchronous or asynchronous.
+ */
+static int
+write_l2e(struct adapter *sc, struct l2t_entry *e, int sync)
+{
+	struct mbuf *m;
+	struct cpl_l2t_write_req *req;
+
+	mtx_assert(&e->lock, MA_OWNED);
+
+	if ((m = m_gethdr(M_NOWAIT, MT_DATA)) == NULL)
+		return (ENOMEM);
+
+	req = mtod(m, struct cpl_l2t_write_req *);
+	m->m_pkthdr.len = m->m_len = sizeof(*req);
+
+	INIT_TP_WR(req, 0);
+	OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, e->idx |
+	    V_SYNC_WR(sync) | V_TID_QID(sc->sge.fwq.abs_id)));
+	req->params = htons(V_L2T_W_PORT(e->lport) | V_L2T_W_NOREPLY(!sync));
+	req->l2t_idx = htons(e->idx);
+	req->vlan = htons(e->vlan);
+	memcpy(req->dst_mac, e->dmac, sizeof(req->dst_mac));
+
+	t4_mgmt_tx(sc, m);
+
+	if (sync && e->state != L2T_STATE_SWITCHING)
+		e->state = L2T_STATE_SYNC_WRITE;
+
+	return (0);
+}
+
+/*
+ * Allocate an L2T entry for use by a switching rule.  Such need to be
+ * explicitly freed and while busy they are not on any hash chain, so normal
+ * address resolution updates do not see them.
+ */
+struct l2t_entry *
+t4_l2t_alloc_switching(struct l2t_data *d)
+{
+	struct l2t_entry *e;
+
+	rw_rlock(&d->lock);
+	e = alloc_l2e(d);
+	if (e) {
+		mtx_lock(&e->lock);          /* avoid race with t4_l2t_free */
+		e->state = L2T_STATE_SWITCHING;
+		atomic_store_rel_int(&e->refcnt, 1);
+		mtx_unlock(&e->lock);
+	}
+	rw_runlock(&d->lock);
+	return e;
+}
+
+/*
+ * Sets/updates the contents of a switching L2T entry that has been allocated
+ * with an earlier call to @t4_l2t_alloc_switching.
+ */
+int
+t4_l2t_set_switching(struct adapter *sc, struct l2t_entry *e, uint16_t vlan,
+    uint8_t port, uint8_t *eth_addr)
+{
+	int rc;
+
+	e->vlan = vlan;
+	e->lport = port;
+	memcpy(e->dmac, eth_addr, ETHER_ADDR_LEN);
+	mtx_lock(&e->lock);
+	rc = write_l2e(sc, e, 0);
+	mtx_unlock(&e->lock);
+	return (rc);
+}
+
+int
+t4_init_l2t(struct adapter *sc, int flags)
+{
+	int i;
+	struct l2t_data *d;
+
+	d = malloc(sizeof(*d), M_CXGBE, M_ZERO | flags);
+	if (!d)
+		return (ENOMEM);
+
+	d->rover = d->l2tab;
+	atomic_store_rel_int(&d->nfree, L2T_SIZE);
+	rw_init(&d->lock, "L2T");
+
+	for (i = 0; i < L2T_SIZE; i++) {
+		d->l2tab[i].idx = i;
+		d->l2tab[i].state = L2T_STATE_UNUSED;
+		mtx_init(&d->l2tab[i].lock, "L2T_E", NULL, MTX_DEF);
+		atomic_store_rel_int(&d->l2tab[i].refcnt, 0);
+	}
+
+	sc->l2t = d;
+	t4_register_cpl_handler(sc, CPL_L2T_WRITE_RPL, do_l2t_write_rpl);
+
+	return (0);
+}
+
+int
+t4_free_l2t(struct l2t_data *d)
+{
+	int i;
+
+	for (i = 0; i < L2T_SIZE; i++)
+		mtx_destroy(&d->l2tab[i].lock);
+	rw_destroy(&d->lock);
+	free(d, M_CXGBE);
+
+	return (0);
+}
+
 static inline unsigned int
 vlan_prio(const struct l2t_entry *e)
 {
 	return e->vlan >> 13;
 }
 
+static char
+l2e_state(const struct l2t_entry *e)
+{
+	switch (e->state) {
+	case L2T_STATE_VALID: return 'V';  /* valid, fast-path entry */
+	case L2T_STATE_STALE: return 'S';  /* needs revalidation, but usable */
+	case L2T_STATE_SYNC_WRITE: return 'W';
+	case L2T_STATE_RESOLVING: return e->arpq_head ? 'A' : 'R';
+	case L2T_STATE_SWITCHING: return 'X';
+	default: return 'U';
+	}
+}
+
+int
+sysctl_l2t(SYSCTL_HANDLER_ARGS)
+{
+	struct adapter *sc = arg1;
+	struct l2t_data *l2t = sc->l2t;
+	struct l2t_entry *e;
+	struct sbuf *sb;
+	int rc, i, header = 0;
+	char ip[60];
+
+	if (l2t == NULL)
+		return (ENXIO);
+
+	rc = sysctl_wire_old_buffer(req, 0);
+	if (rc != 0)
+		return (rc);
+
+	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
+	if (sb == NULL)
+		return (ENOMEM);
+
+	e = &l2t->l2tab[0];
+	for (i = 0; i < L2T_SIZE; i++, e++) {
+		mtx_lock(&e->lock);
+		if (e->state == L2T_STATE_UNUSED)
+			goto skip;
+
+		if (header == 0) {
+			sbuf_printf(sb, " Idx IP address      "
+			    "Ethernet address  VLAN/P LP State Users Port");
+			header = 1;
+		}
+		if (e->state == L2T_STATE_SWITCHING || e->v6)
+			ip[0] = 0;
+		else
+			snprintf(ip, sizeof(ip), "%s",
+			    inet_ntoa(*(struct in_addr *)&e->addr[0]));
+
+		/* XXX: accessing lle probably not safe? */
+		sbuf_printf(sb, "\n%4u %-15s %02x:%02x:%02x:%02x:%02x:%02x %4d"
+			   " %u %2u   %c   %5u %s",
+			   e->idx, ip, e->dmac[0], e->dmac[1], e->dmac[2],
+			   e->dmac[3], e->dmac[4], e->dmac[5],
+			   e->vlan & 0xfff, vlan_prio(e), e->lport,
+			   l2e_state(e), atomic_load_acq_int(&e->refcnt),
+			   e->lle ? e->lle->lle_tbl->llt_ifp->if_xname : "");
+skip:
+		mtx_unlock(&e->lock);
+	}
+
+	rc = sbuf_finish(sb);
+	sbuf_delete(sb);
+
+	return (rc);
+}
+
+#ifndef TCP_OFFLOAD_DISABLE
 static inline void
 l2t_hold(struct l2t_data *d, struct l2t_entry *e)
 {
 	if (atomic_fetchadd_int(&e->refcnt, 1) == 0)  /* 0 -> 1 transition */
-		atomic_add_int(&d->nfree, -1);
+		atomic_subtract_int(&d->nfree, 1);
 }
 
 /*
@@ -154,38 +390,6 @@ addreq(const struct l2t_entry *e, const uint32_t *addr)
 }
 
 /*
- * Write an L2T entry.  Must be called with the entry locked (XXX: really?).
- * The write may be synchronous or asynchronous.
- */
-static int
-write_l2e(struct adapter *sc, struct l2t_entry *e, int sync)
-{
-	struct mbuf *m;
-	struct cpl_l2t_write_req *req;
-
-	if ((m = m_gethdr(M_NOWAIT, MT_DATA)) == NULL)
-		return (ENOMEM);
-
-	req = mtod(m, struct cpl_l2t_write_req *);
-	m->m_pkthdr.len = m->m_len = sizeof(*req);
-
-	INIT_TP_WR(req, 0);
-	OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, e->idx |
-	    V_SYNC_WR(sync) | V_TID_QID(sc->sge.fwq.abs_id)));
-	req->params = htons(V_L2T_W_PORT(e->lport) | V_L2T_W_NOREPLY(!sync));
-	req->l2t_idx = htons(e->idx);
-	req->vlan = htons(e->vlan);
-	memcpy(req->dst_mac, e->dmac, sizeof(req->dst_mac));
-
-	t4_mgmt_tx(sc, m);
-
-	if (sync && e->state != L2T_STATE_SWITCHING)
-		e->state = L2T_STATE_SYNC_WRITE;
-
-	return (0);
-}
-
-/*
  * Add a packet to an L2T entry's queue of packets awaiting resolution.
  * Must be called with the entry's lock held.
  */
@@ -194,53 +398,133 @@ arpq_enqueue(struct l2t_entry *e, struct mbuf *m)
 {
 	mtx_assert(&e->lock, MA_OWNED);
 
-	m->m_next = NULL;
+	KASSERT(m->m_nextpkt == NULL, ("%s: m_nextpkt not NULL", __func__));
 	if (e->arpq_head)
-		e->arpq_tail->m_next = m;
+		e->arpq_tail->m_nextpkt = m;
 	else
 		e->arpq_head = m;
 	e->arpq_tail = m;
 }
 
-/*
- * Allocate a free L2T entry.  Must be called with l2t_data.lock held.
- */
-static struct l2t_entry *
-alloc_l2e(struct l2t_data *d)
+static inline void
+send_pending(struct adapter *sc, struct l2t_entry *e)
 {
-	struct l2t_entry *end, *e, **p;
+	struct mbuf *m, *next;
 
-	rw_assert(&d->lock, RA_WLOCKED);
+	mtx_assert(&e->lock, MA_OWNED);
 
-	if (!atomic_load_acq_int(&d->nfree))
-		return (NULL);
+	for (m = e->arpq_head; m; m = next) {
+		next = m->m_nextpkt;
+		m->m_nextpkt = NULL;
+		t4_wrq_tx(sc, MBUF_EQ(m), m);
+	}
+	e->arpq_head = e->arpq_tail = NULL;
+}
 
-	/* there's definitely a free entry */
-	for (e = d->rover, end = &d->l2tab[L2T_SIZE]; e != end; ++e)
-		if (atomic_load_acq_int(&e->refcnt) == 0)
-			goto found;
+#ifdef INET
+/*
+ * Looks up and fills up an l2t_entry's lle.  We grab all the locks that we need
+ * ourself, and update e->state at the end if e->lle was successfully filled.
+ *
+ * The lle passed in comes from arpresolve and is ignored as it does not appear
+ * to be of much use.
+ */
+static int
+l2t_fill_lle(struct adapter *sc, struct l2t_entry *e, struct llentry *unused)
+{
+        int rc = 0;
+        struct sockaddr_in sin;
+        struct ifnet *ifp = e->ifp;
+        struct llentry *lle;
 
-	for (e = d->l2tab; atomic_load_acq_int(&e->refcnt); ++e) ;
-found:
-	d->rover = e + 1;
-	atomic_add_int(&d->nfree, -1);
+        bzero(&sin, sizeof(struct sockaddr_in));
+	if (e->v6)
+		panic("%s: IPv6 L2 resolution not supported yet.", __func__);
+
+	sin.sin_family = AF_INET;
+	sin.sin_len = sizeof(struct sockaddr_in);
+	memcpy(&sin.sin_addr, e->addr, sizeof(struct sockaddr_in));
+
+        mtx_assert(&e->lock, MA_NOTOWNED);
+        KASSERT(e->addr && ifp, ("%s: bad prep before call", __func__));
+
+        IF_AFDATA_LOCK(ifp);
+        lle = lla_lookup(LLTABLE(ifp), LLE_EXCLUSIVE, SA(&sin));
+        IF_AFDATA_UNLOCK(ifp);
+        if (!LLE_IS_VALID(lle))
+                return (ENOMEM);
+        if (!(lle->la_flags & LLE_VALID)) {
+                rc = EINVAL;
+                goto done;
+        }
+
+        LLE_ADDREF(lle);
+
+        mtx_lock(&e->lock);
+        if (e->state == L2T_STATE_RESOLVING) {
+                KASSERT(e->lle == NULL, ("%s: lle already valid", __func__));
+                e->lle = lle;
+                memcpy(e->dmac, &lle->ll_addr, ETHER_ADDR_LEN);
+		write_l2e(sc, e, 1);
+        } else {
+                KASSERT(e->lle == lle, ("%s: lle changed", __func__));
+                LLE_REMREF(lle);
+        }
+        mtx_unlock(&e->lock);
+done:
+        LLE_WUNLOCK(lle);
+        return (rc);
+}
+#endif
 
-	/*
-	 * The entry we found may be an inactive entry that is
-	 * presently in the hash table.  We need to remove it.
-	 */
-	if (e->state < L2T_STATE_SWITCHING) {
-		for (p = &d->l2tab[e->hash].first; *p; p = &(*p)->next) {
-			if (*p == e) {
-				*p = e->next;
-				e->next = NULL;
-				break;
-			}
+int
+t4_l2t_send(struct adapter *sc, struct mbuf *m, struct l2t_entry *e)
+{
+#ifndef INET
+	return (EINVAL);
+#else
+	struct llentry *lle = NULL;
+	struct sockaddr_in sin;
+	struct ifnet *ifp = e->ifp;
+
+	if (e->v6)
+		panic("%s: IPv6 L2 resolution not supported yet.", __func__);
+
+        bzero(&sin, sizeof(struct sockaddr_in));
+	sin.sin_family = AF_INET;
+	sin.sin_len = sizeof(struct sockaddr_in);
+	memcpy(&sin.sin_addr, e->addr, sizeof(struct sockaddr_in));
+
+again:
+	switch (e->state) {
+	case L2T_STATE_STALE:     /* entry is stale, kick off revalidation */
+		if (arpresolve(ifp, NULL, NULL, SA(&sin), e->dmac, &lle) == 0)
+			l2t_fill_lle(sc, e, lle);
+
+		/* Fall through */
+
+	case L2T_STATE_VALID:     /* fast-path, send the packet on */
+		return t4_wrq_tx(sc, MBUF_EQ(m), m);
+
+	case L2T_STATE_RESOLVING:
+	case L2T_STATE_SYNC_WRITE:
+		mtx_lock(&e->lock);
+		if (e->state != L2T_STATE_SYNC_WRITE &&
+		    e->state != L2T_STATE_RESOLVING) {
+			/* state changed by the time we got here */
+			mtx_unlock(&e->lock);
+			goto again;
 		}
+		arpq_enqueue(e, m);
+		mtx_unlock(&e->lock);
+
+		if (e->state == L2T_STATE_RESOLVING &&
+		    arpresolve(ifp, NULL, NULL, SA(&sin), e->dmac, &lle) == 0)
+			l2t_fill_lle(sc, e, lle);
 	}
 
-	e->state = L2T_STATE_UNUSED;
-	return e;
+	return (0);
+#endif
 }
 
 /*
@@ -287,75 +571,214 @@ t4_l2t_release(struct l2t_entry *e)
 		t4_l2e_free(e);
 }
 
+static int
+do_l2t_write_rpl(struct sge_iq *iq, const struct rss_header *rss,
+    struct mbuf *m)
+{
+	struct adapter *sc = iq->adapter;
+	const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1);
+	unsigned int tid = GET_TID(rpl);
+	unsigned int idx = tid & (L2T_SIZE - 1);
+
+	if (__predict_false(rpl->status != CPL_ERR_NONE)) {
+		log(LOG_ERR,
+		    "Unexpected L2T_WRITE_RPL status %u for entry %u\n",
+		    rpl->status, idx);
+		return (EINVAL);
+	}
+
+	if (tid & F_SYNC_WR) {
+		struct l2t_entry *e = &sc->l2t->l2tab[idx];
+
+		mtx_lock(&e->lock);
+		if (e->state != L2T_STATE_SWITCHING) {
+			send_pending(sc, e);
+			e->state = L2T_STATE_VALID;
+		}
+		mtx_unlock(&e->lock);
+	}
+
+	return (0);
+}
+
 /*
- * Allocate an L2T entry for use by a switching rule.  Such need to be
- * explicitly freed and while busy they are not on any hash chain, so normal
- * address resolution updates do not see them.
+ * Reuse an L2T entry that was previously used for the same next hop.
+ */
+static void
+reuse_entry(struct l2t_entry *e)
+{
+	struct llentry *lle;
+
+	mtx_lock(&e->lock);                /* avoid race with t4_l2t_free */
+	lle = e->lle;
+	if (lle) {
+		KASSERT(lle->la_flags & LLE_VALID,
+			("%s: invalid lle stored in l2t_entry", __func__));
+
+		if (lle->la_expire >= time_uptime)
+			e->state = L2T_STATE_STALE;
+		else
+			e->state = L2T_STATE_VALID;
+	} else
+		e->state = L2T_STATE_RESOLVING;
+	mtx_unlock(&e->lock);
+}
+
+/*
+ * The TOE wants an L2 table entry that it can use to reach the next hop over
+ * the specified port.  Produce such an entry - create one if needed.
+ *
+ * Note that the ifnet could be a pseudo-device like if_vlan, if_lagg, etc. on
+ * top of the real cxgbe interface.
  */
 struct l2t_entry *
-t4_l2t_alloc_switching(struct l2t_data *d)
+t4_l2t_get(struct port_info *pi, struct ifnet *ifp, struct sockaddr *sa)
 {
 	struct l2t_entry *e;
+	struct l2t_data *d = pi->adapter->l2t;
+	int addr_len;
+	uint32_t *addr;
+	int hash;
+	struct sockaddr_in6 *sin6;
+	unsigned int smt_idx = pi->port_id;
+
+	if (sa->sa_family == AF_INET) {
+		addr = (uint32_t *)&SINADDR(sa);
+		addr_len = sizeof(SINADDR(sa));
+	} else if (sa->sa_family == AF_INET6) {
+		sin6 = (struct sockaddr_in6 *)sa;
+		addr = (uint32_t *)&sin6->sin6_addr.s6_addr;
+		addr_len = sizeof(sin6->sin6_addr.s6_addr);
+	} else
+		return (NULL);
 
-	rw_rlock(&d->lock);
+	hash = addr_hash(addr, addr_len, ifp->if_index);
+
+	rw_wlock(&d->lock);
+	for (e = d->l2tab[hash].first; e; e = e->next) {
+		if (!addreq(e, addr) && e->ifp == ifp && e->smt_idx == smt_idx){
+			l2t_hold(d, e);
+			if (atomic_load_acq_int(&e->refcnt) == 1)
+				reuse_entry(e);
+			goto done;
+		}
+	}
+
+	/* Need to allocate a new entry */
 	e = alloc_l2e(d);
 	if (e) {
 		mtx_lock(&e->lock);          /* avoid race with t4_l2t_free */
-		e->state = L2T_STATE_SWITCHING;
+		e->state = L2T_STATE_RESOLVING;
+		memcpy(e->addr, addr, addr_len);
+		e->ifindex = ifp->if_index;
+		e->smt_idx = smt_idx;
+		e->ifp = ifp;
+		e->hash = hash;
+		e->lport = pi->lport;
+		e->v6 = (addr_len == 16);
+		e->lle = NULL;
 		atomic_store_rel_int(&e->refcnt, 1);
+		if (ifp->if_type == IFT_L2VLAN)
+			VLAN_TAG(ifp, &e->vlan);
+		else
+			e->vlan = VLAN_NONE;
+		e->next = d->l2tab[hash].first;
+		d->l2tab[hash].first = e;
 		mtx_unlock(&e->lock);
 	}
-	rw_runlock(&d->lock);
+done:
+	rw_wunlock(&d->lock);
 	return e;
 }
 
 /*
- * Sets/updates the contents of a switching L2T entry that has been allocated
- * with an earlier call to @t4_l2t_alloc_switching.
+ * Called when the host's neighbor layer makes a change to some entry that is
+ * loaded into the HW L2 table.
  */
-int
-t4_l2t_set_switching(struct adapter *sc, struct l2t_entry *e, uint16_t vlan,
-    uint8_t port, uint8_t *eth_addr)
+void
+t4_l2t_update(struct adapter *sc, struct llentry *lle)
 {
-	e->vlan = vlan;
-	e->lport = port;
-	memcpy(e->dmac, eth_addr, ETHER_ADDR_LEN);
-	return write_l2e(sc, e, 0);
-}
+	struct l2t_entry *e;
+	struct l2t_data *d = sc->l2t;
+	struct sockaddr *sa = L3_ADDR(lle);
+	struct llentry *old_lle = NULL;
+	uint32_t *addr = (uint32_t *)&SINADDR(sa);
+	struct ifnet *ifp = lle->lle_tbl->llt_ifp;
+	int hash = addr_hash(addr, sizeof(*addr), ifp->if_index);
+
+	KASSERT(d != NULL, ("%s: no L2 table", __func__));
+	LLE_WLOCK_ASSERT(lle);
+	KASSERT(lle->la_flags & LLE_VALID || lle->la_flags & LLE_DELETED,
+	    ("%s: entry neither valid nor deleted.", __func__));
 
-struct l2t_data *
-t4_init_l2t(int flags)
-{
-	int i;
-	struct l2t_data *d;
+	rw_rlock(&d->lock);
+	for (e = d->l2tab[hash].first; e; e = e->next) {
+		if (!addreq(e, addr) && e->ifp == ifp) {
+			mtx_lock(&e->lock);
+			if (atomic_load_acq_int(&e->refcnt))
+				goto found;
+			e->state = L2T_STATE_STALE;
+			mtx_unlock(&e->lock);
+			break;
+		}
+	}
+	rw_runlock(&d->lock);
 
-	d = malloc(sizeof(*d), M_CXGBE, M_ZERO | flags);
-	if (!d)
-		return (NULL);
+	/* The TOE has no interest in this LLE */
+	return;
 
-	d->rover = d->l2tab;
-	atomic_store_rel_int(&d->nfree, L2T_SIZE);
-	rw_init(&d->lock, "L2T");
+ found:
+	rw_runlock(&d->lock);
 
-	for (i = 0; i < L2T_SIZE; i++) {
-		d->l2tab[i].idx = i;
-		d->l2tab[i].state = L2T_STATE_UNUSED;
-		mtx_init(&d->l2tab[i].lock, "L2T_E", NULL, MTX_DEF);
-		atomic_store_rel_int(&d->l2tab[i].refcnt, 0);
-	}
+        if (atomic_load_acq_int(&e->refcnt)) {
 
-	return (d);
-}
+                /* Entry is referenced by at least 1 offloaded connection. */
 
-int
-t4_free_l2t(struct l2t_data *d)
-{
-	int i;
+                /* Handle deletes first */
+                if (lle->la_flags & LLE_DELETED) {
+                        if (lle == e->lle) {
+                                e->lle = NULL;
+                                e->state = L2T_STATE_RESOLVING;
+                                LLE_REMREF(lle);
+                        }
+                        goto done;
+                }
 
-	for (i = 0; i < L2T_SIZE; i++)
-		mtx_destroy(&d->l2tab[i].lock);
-	rw_destroy(&d->lock);
-	free(d, M_CXGBE);
+                if (lle != e->lle) {
+                        old_lle = e->lle;
+                        LLE_ADDREF(lle);
+                        e->lle = lle;
+                }
 
-	return (0);
+                if (e->state == L2T_STATE_RESOLVING ||
+                    memcmp(e->dmac, &lle->ll_addr, ETHER_ADDR_LEN)) {
+
+                        /* unresolved -> resolved; or dmac changed */
+
+                        memcpy(e->dmac, &lle->ll_addr, ETHER_ADDR_LEN);
+			write_l2e(sc, e, 1);
+                } else {
+
+                        /* +ve reinforcement of a valid or stale entry */
+
+                }
+
+                e->state = L2T_STATE_VALID;
+
+        } else {
+                /*
+                 * Entry was used previously but is unreferenced right now.
+                 * e->lle has been released and NULL'd out by t4_l2t_free, or
+                 * l2t_release is about to call t4_l2t_free and do that.
+                 *
+                 * Either way this is of no interest to us.
+                 */
+        }
+
+done:
+        mtx_unlock(&e->lock);
+        if (old_lle)
+                LLE_FREE(old_lle);
 }
+
+#endif
diff --git a/sys/dev/cxgbe/t4_l2t.h b/sys/dev/cxgbe/t4_l2t.h
index c5520c6..8004c9e 100644
--- a/sys/dev/cxgbe/t4_l2t.h
+++ b/sys/dev/cxgbe/t4_l2t.h
@@ -54,18 +54,26 @@ struct l2t_entry {
 	struct mbuf *arpq_head;		/* list of mbufs awaiting resolution */
 	struct mbuf *arpq_tail;
 	struct mtx lock;
-	volatile uint32_t refcnt;	/* entry reference count */
+	volatile int refcnt;		/* entry reference count */
 	uint16_t hash;			/* hash bucket the entry is on */
 	uint8_t v6;			/* whether entry is for IPv6 */
 	uint8_t lport;			/* associated offload logical port */
 	uint8_t dmac[ETHER_ADDR_LEN];	/* next hop's MAC address */
 };
 
-struct l2t_data *t4_init_l2t(int);
+int t4_init_l2t(struct adapter *, int);
 int t4_free_l2t(struct l2t_data *);
 struct l2t_entry *t4_l2t_alloc_switching(struct l2t_data *);
 int t4_l2t_set_switching(struct adapter *, struct l2t_entry *, uint16_t,
     uint8_t, uint8_t *);
 void t4_l2t_release(struct l2t_entry *);
+int sysctl_l2t(SYSCTL_HANDLER_ARGS);
+
+#ifndef TCP_OFFLOAD_DISABLE
+struct l2t_entry *t4_l2t_get(struct port_info *, struct ifnet *,
+    struct sockaddr *);
+int t4_l2t_send(struct adapter *, struct mbuf *, struct l2t_entry *);
+void t4_l2t_update(struct adapter *, struct llentry *);
+#endif
 
 #endif  /* __T4_L2T_H */
diff --git a/sys/dev/cxgbe/t4_main.c b/sys/dev/cxgbe/t4_main.c
index b7cb09a..37a4a7c 100644
--- a/sys/dev/cxgbe/t4_main.c
+++ b/sys/dev/cxgbe/t4_main.c
@@ -55,12 +55,10 @@ __FBSDID("$FreeBSD$");
 #include <net/if_dl.h>
 #include <net/if_vlan_var.h>
 
-#include "common/t4_hw.h"
 #include "common/common.h"
 #include "common/t4_msg.h"
 #include "common/t4_regs.h"
 #include "common/t4_regs_values.h"
-#include "common/t4fw_interface.h"
 #include "t4_ioctl.h"
 #include "t4_l2t.h"
 
@@ -73,11 +71,7 @@ static device_method_t t4_methods[] = {
 	DEVMETHOD(device_attach,	t4_attach),
 	DEVMETHOD(device_detach,	t4_detach),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 static driver_t t4_driver = {
 	"t4nex",
@@ -126,115 +120,130 @@ static void cxgbe_media_status(struct ifnet *, struct ifmediareq *);
 
 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4 Ethernet driver and services");
 
-/*
- * Tunables.
- */
-static SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD, 0,
-    "cxgbe driver parameters");
-
-static int force_firmware_install = 0;
-TUNABLE_INT("hw.cxgbe.force_firmware_install", &force_firmware_install);
-SYSCTL_UINT(_hw_cxgbe, OID_AUTO, force_firmware_install, CTLFLAG_RDTUN,
-    &force_firmware_install, 0, "install firmware on every attach.");
+static struct mtx t4_list_lock;
+static SLIST_HEAD(, adapter) t4_list;
+#ifndef TCP_OFFLOAD_DISABLE
+static struct mtx t4_uld_list_lock;
+static SLIST_HEAD(, uld_info) t4_uld_list;
+#endif
 
 /*
- * Holdoff timer and packet counter values.
+ * Tunables.  See tweak_tunables() too.
  */
-static unsigned int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200};
-static unsigned int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */
 
 /*
- * Max # of tx and rx queues to use for each 10G and 1G port.
+ * Number of queues for tx and rx, 10G and 1G, NIC and offload.
  */
-static unsigned int max_ntxq_10g = 8;
-TUNABLE_INT("hw.cxgbe.max_ntxq_10G_port", &max_ntxq_10g);
-SYSCTL_UINT(_hw_cxgbe, OID_AUTO, max_ntxq_10G_port, CTLFLAG_RDTUN,
-    &max_ntxq_10g, 0, "maximum number of tx queues per 10G port.");
-
-static unsigned int max_nrxq_10g = 8;
-TUNABLE_INT("hw.cxgbe.max_nrxq_10G_port", &max_nrxq_10g);
-SYSCTL_UINT(_hw_cxgbe, OID_AUTO, max_nrxq_10G_port, CTLFLAG_RDTUN,
-    &max_nrxq_10g, 0, "maximum number of rxq's (per 10G port).");
-
-static unsigned int max_ntxq_1g = 2;
-TUNABLE_INT("hw.cxgbe.max_ntxq_1G_port", &max_ntxq_1g);
-SYSCTL_UINT(_hw_cxgbe, OID_AUTO, max_ntxq_1G_port, CTLFLAG_RDTUN,
-    &max_ntxq_1g, 0, "maximum number of tx queues per 1G port.");
-
-static unsigned int max_nrxq_1g = 2;
-TUNABLE_INT("hw.cxgbe.max_nrxq_1G_port", &max_nrxq_1g);
-SYSCTL_UINT(_hw_cxgbe, OID_AUTO, max_nrxq_1G_port, CTLFLAG_RDTUN,
-    &max_nrxq_1g, 0, "maximum number of rxq's (per 1G port).");
+#define NTXQ_10G 16
+static int t4_ntxq10g = -1;
+TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq10g);
+
+#define NRXQ_10G 8
+static int t4_nrxq10g = -1;
+TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq10g);
+
+#define NTXQ_1G 4
+static int t4_ntxq1g = -1;
+TUNABLE_INT("hw.cxgbe.ntxq1g", &t4_ntxq1g);
+
+#define NRXQ_1G 2
+static int t4_nrxq1g = -1;
+TUNABLE_INT("hw.cxgbe.nrxq1g", &t4_nrxq1g);
+
+#ifndef TCP_OFFLOAD_DISABLE
+#define NOFLDTXQ_10G 8
+static int t4_nofldtxq10g = -1;
+TUNABLE_INT("hw.cxgbe.nofldtxq10g", &t4_nofldtxq10g);
+
+#define NOFLDRXQ_10G 2
+static int t4_nofldrxq10g = -1;
+TUNABLE_INT("hw.cxgbe.nofldrxq10g", &t4_nofldrxq10g);
+
+#define NOFLDTXQ_1G 2
+static int t4_nofldtxq1g = -1;
+TUNABLE_INT("hw.cxgbe.nofldtxq1g", &t4_nofldtxq1g);
+
+#define NOFLDRXQ_1G 1
+static int t4_nofldrxq1g = -1;
+TUNABLE_INT("hw.cxgbe.nofldrxq1g", &t4_nofldrxq1g);
+#endif
 
 /*
  * Holdoff parameters for 10G and 1G ports.
  */
-static unsigned int tmr_idx_10g = 1;
-TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &tmr_idx_10g);
-SYSCTL_UINT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_10G, CTLFLAG_RDTUN,
-    &tmr_idx_10g, 0,
-    "default timer index for interrupt holdoff (10G ports).");
-
-static int pktc_idx_10g = 2;
-TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &pktc_idx_10g);
-SYSCTL_UINT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_10G, CTLFLAG_RDTUN,
-    &pktc_idx_10g, 0,
-    "default pkt counter index for interrupt holdoff (10G ports).");
-
-static unsigned int tmr_idx_1g = 1;
-TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_1G", &tmr_idx_1g);
-SYSCTL_UINT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_1G, CTLFLAG_RDTUN,
-    &tmr_idx_1g, 0,
-    "default timer index for interrupt holdoff (1G ports).");
-
-static int pktc_idx_1g = 2;
-TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_1G", &pktc_idx_1g);
-SYSCTL_UINT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_1G, CTLFLAG_RDTUN,
-    &pktc_idx_1g, 0,
-    "default pkt counter index for interrupt holdoff (1G ports).");
+#define TMR_IDX_10G 1
+static int t4_tmr_idx_10g = TMR_IDX_10G;
+TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx_10g);
+
+#define PKTC_IDX_10G 2
+static int t4_pktc_idx_10g = PKTC_IDX_10G;
+TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx_10g);
+
+#define TMR_IDX_1G 1
+static int t4_tmr_idx_1g = TMR_IDX_1G;
+TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_1G", &t4_tmr_idx_1g);
+
+#define PKTC_IDX_1G 2
+static int t4_pktc_idx_1g = PKTC_IDX_1G;
+TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_1G", &t4_pktc_idx_1g);
 
 /*
  * Size (# of entries) of each tx and rx queue.
  */
-static unsigned int qsize_txq = TX_EQ_QSIZE;
-TUNABLE_INT("hw.cxgbe.qsize_txq", &qsize_txq);
-SYSCTL_UINT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN,
-    &qsize_txq, 0, "default queue size of NIC tx queues.");
+static unsigned int t4_qsize_txq = TX_EQ_QSIZE;
+TUNABLE_INT("hw.cxgbe.qsize_txq", &t4_qsize_txq);
 
-static unsigned int qsize_rxq = RX_IQ_QSIZE;
-TUNABLE_INT("hw.cxgbe.qsize_rxq", &qsize_rxq);
-SYSCTL_UINT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN,
-    &qsize_rxq, 0, "default queue size of NIC rx queues.");
+static unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
+TUNABLE_INT("hw.cxgbe.qsize_rxq", &t4_qsize_rxq);
 
 /*
- * Interrupt types allowed.
+ * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
  */
-static int intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
-TUNABLE_INT("hw.cxgbe.interrupt_types", &intr_types);
-SYSCTL_UINT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &intr_types, 0,
-    "interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively)");
+static int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
+TUNABLE_INT("hw.cxgbe.interrupt_types", &t4_intr_types);
 
 /*
- * Force the driver to use the same set of interrupts for all ports.
+ * Configuration file.
  */
-static int intr_shared = 0;
-TUNABLE_INT("hw.cxgbe.interrupts_shared", &intr_shared);
-SYSCTL_UINT(_hw_cxgbe, OID_AUTO, interrupts_shared, CTLFLAG_RDTUN,
-    &intr_shared, 0, "interrupts shared between all ports");
+static char t4_cfg_file[32] = "default";
+TUNABLE_STR("hw.cxgbe.config_file", t4_cfg_file, sizeof(t4_cfg_file));
+
+/*
+ * ASIC features that will be used.  Disable the ones you don't want so that the
+ * chip resources aren't wasted on features that will not be used.
+ */
+static int t4_linkcaps_allowed = 0;	/* No DCBX, PPP, etc. by default */
+TUNABLE_INT("hw.cxgbe.linkcaps_allowed", &t4_linkcaps_allowed);
+
+static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC;
+TUNABLE_INT("hw.cxgbe.niccaps_allowed", &t4_niccaps_allowed);
 
-static unsigned int filter_mode = HW_TPL_FR_MT_PR_IV_P_FC;
-TUNABLE_INT("hw.cxgbe.filter_mode", &filter_mode);
-SYSCTL_UINT(_hw_cxgbe, OID_AUTO, filter_mode, CTLFLAG_RDTUN,
-    &filter_mode, 0, "default global filter mode.");
+static int t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
+TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed);
+
+static int t4_rdmacaps_allowed = 0;
+TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed);
+
+static int t4_iscsicaps_allowed = 0;
+TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed);
+
+static int t4_fcoecaps_allowed = 0;
+TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed);
 
 struct intrs_and_queues {
 	int intr_type;		/* INTx, MSI, or MSI-X */
 	int nirq;		/* Number of vectors */
-	int intr_shared;	/* Interrupts shared between all ports */
+	int intr_flags;
 	int ntxq10g;		/* # of NIC txq's for each 10G port */
 	int nrxq10g;		/* # of NIC rxq's for each 10G port */
 	int ntxq1g;		/* # of NIC txq's for each 1G port */
 	int nrxq1g;		/* # of NIC rxq's for each 1G port */
+#ifndef TCP_OFFLOAD_DISABLE
+	int nofldtxq10g;	/* # of TOE txq's for each 10G port */
+	int nofldrxq10g;	/* # of TOE rxq's for each 10G port */
+	int nofldtxq1g;		/* # of TOE txq's for each 1G port */
+	int nofldrxq1g;		/* # of TOE rxq's for each 1G port */
+#endif
 };
 
 struct filter_entry {
@@ -248,15 +257,6 @@ struct filter_entry {
 };
 
 enum {
-	MEMWIN0_APERTURE = 2048,
-	MEMWIN0_BASE     = 0x1b800,
-	MEMWIN1_APERTURE = 32768,
-	MEMWIN1_BASE     = 0x28000,
-	MEMWIN2_APERTURE = 65536,
-	MEMWIN2_BASE     = 0x30000,
-};
-
-enum {
 	XGMAC_MTU	= (1 << 0),
 	XGMAC_PROMISC	= (1 << 1),
 	XGMAC_ALLMULTI	= (1 << 2),
@@ -272,9 +272,11 @@ static void setup_memwin(struct adapter *);
 static int cfg_itype_and_nqueues(struct adapter *, int, int,
     struct intrs_and_queues *);
 static int prep_firmware(struct adapter *);
-static int get_devlog_params(struct adapter *, struct devlog_params *);
-static int get_capabilities(struct adapter *, struct fw_caps_config_cmd *);
-static int get_params(struct adapter *, struct fw_caps_config_cmd *);
+static int upload_config_file(struct adapter *, const struct firmware *,
+    uint32_t *, uint32_t *);
+static int partition_resources(struct adapter *, const struct firmware *);
+static int get_params__pre_init(struct adapter *);
+static int get_params__post_init(struct adapter *);
 static void t4_set_desc(struct adapter *);
 static void build_medialist(struct port_info *);
 static int update_mac_settings(struct port_info *, int);
@@ -282,24 +284,46 @@ static int cxgbe_init_locked(struct port_info *);
 static int cxgbe_init_synchronized(struct port_info *);
 static int cxgbe_uninit_locked(struct port_info *);
 static int cxgbe_uninit_synchronized(struct port_info *);
-static int first_port_up(struct adapter *);
-static int last_port_down(struct adapter *);
+static int adapter_full_init(struct adapter *);
+static int adapter_full_uninit(struct adapter *);
+static int port_full_init(struct port_info *);
+static int port_full_uninit(struct port_info *);
+static void quiesce_eq(struct adapter *, struct sge_eq *);
+static void quiesce_iq(struct adapter *, struct sge_iq *);
+static void quiesce_fl(struct adapter *, struct sge_fl *);
 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
-    iq_intr_handler_t *, void *, char *);
+    driver_intr_t *, void *, char *);
 static int t4_free_irq(struct adapter *, struct irq *);
 static void reg_block_dump(struct adapter *, uint8_t *, unsigned int,
     unsigned int);
 static void t4_get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
 static void cxgbe_tick(void *);
+static int cpl_not_handled(struct sge_iq *, const struct rss_header *,
+    struct mbuf *);
 static int t4_sysctls(struct adapter *);
 static int cxgbe_sysctls(struct port_info *);
 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
+static int sysctl_bitfield(SYSCTL_HANDLER_ARGS);
 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
+static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
+static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
+static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
+static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
+static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
+static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
+static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
+static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
+static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
+static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
+static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
+static int sysctl_tids(SYSCTL_HANDLER_ARGS);
+static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
+static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
 static inline void txq_start(struct ifnet *, struct sge_txq *);
 static uint32_t fconf_to_mode(uint32_t);
 static uint32_t mode_to_fconf(uint32_t);
@@ -313,8 +337,15 @@ static int del_filter(struct adapter *, struct t4_filter *);
 static void clear_filter(struct filter_entry *);
 static int set_filter_wr(struct adapter *, int);
 static int del_filter_wr(struct adapter *, int);
-void filter_rpl(struct adapter *, const struct cpl_set_tcb_rpl *);
+static int filter_rpl(struct sge_iq *, const struct rss_header *,
+    struct mbuf *);
 static int get_sge_context(struct adapter *, struct t4_sge_context *);
+static int read_card_mem(struct adapter *, struct t4_mem_range *);
+#ifndef TCP_OFFLOAD_DISABLE
+static int toe_capability(struct port_info *, int);
+static int activate_uld(struct adapter *, int, struct uld_softc *);
+static int deactivate_uld(struct uld_softc *);
+#endif
 static int t4_mod_event(module_t, int, void *);
 
 struct t4_pciids {
@@ -336,6 +367,11 @@ struct t4_pciids {
 	{0x440a, 4, "Chelsio T404-BT"},
 };
 
+#ifndef TCP_OFFLOAD_DISABLE
+/* This is used in service_iq() to get to the fl associated with an iq. */
+CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
+#endif
+
 static int
 t4_probe(device_t dev)
 {
@@ -362,10 +398,11 @@ t4_attach(device_t dev)
 {
 	struct adapter *sc;
 	int rc = 0, i, n10g, n1g, rqidx, tqidx;
-	struct fw_caps_config_cmd caps;
-	uint32_t p, v;
 	struct intrs_and_queues iaq;
 	struct sge *s;
+#ifndef TCP_OFFLOAD_DISABLE
+	int ofld_rqidx, ofld_tqidx;
+#endif
 
 	sc = device_get_softc(dev);
 	sc->dev = dev;
@@ -374,6 +411,8 @@ t4_attach(device_t dev)
 
 	pci_enable_busmaster(dev);
 	if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
+		uint32_t v;
+
 		pci_set_max_read_req(dev, 4096);
 		v = pci_read_config(dev, i + PCIR_EXPRESS_DEVICE_CTL, 2);
 		v |= PCIM_EXP_CTL_RELAXED_ORD_ENABLE;
@@ -383,12 +422,22 @@ t4_attach(device_t dev)
 	snprintf(sc->lockname, sizeof(sc->lockname), "%s",
 	    device_get_nameunit(dev));
 	mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
+	mtx_lock(&t4_list_lock);
+	SLIST_INSERT_HEAD(&t4_list, sc, link);
+	mtx_unlock(&t4_list_lock);
+
+	mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
+	TAILQ_INIT(&sc->sfl);
+	callout_init(&sc->sfl_callout, CALLOUT_MPSAFE);
 
 	rc = map_bars(sc);
 	if (rc != 0)
 		goto done; /* error message displayed already */
 
 	memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
+	for (i = 0; i < ARRAY_SIZE(sc->cpl_handler); i++)
+		sc->cpl_handler[i] = cpl_not_handled;
+	t4_register_cpl_handler(sc, CPL_SET_TCB_RPL, filter_rpl);
 
 	/* Prepare the adapter for operation */
 	rc = -t4_prep_adapter(sc);
@@ -397,107 +446,75 @@ t4_attach(device_t dev)
 		goto done;
 	}
 
-	/* Do this really early */
+	/*
+	 * Do this really early, with the memory windows set up even before the
+	 * character device.  The userland tool's register i/o and mem read
+	 * will work even in "recovery mode".
+	 */
+	setup_memwin(sc);
 	sc->cdev = make_dev(&t4_cdevsw, device_get_unit(dev), UID_ROOT,
 	    GID_WHEEL, 0600, "%s", device_get_nameunit(dev));
 	sc->cdev->si_drv1 = sc;
 
+	/* Go no further if recovery mode has been requested. */
+	if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
+		device_printf(dev, "recovery mode.\n");
+		goto done;
+	}
+
 	/* Prepare the firmware for operation */
 	rc = prep_firmware(sc);
 	if (rc != 0)
 		goto done; /* error message displayed already */
 
-	/* Read firmware devlog parameters */
-	(void) get_devlog_params(sc, &sc->params.devlog);
-
-	/* Get device capabilities and select which ones we'll use */
-	rc = get_capabilities(sc, &caps);
-	if (rc != 0) {
-		device_printf(dev,
-		    "failed to initialize adapter capabilities: %d.\n", rc);
-		goto done;
-	}
+	rc = get_params__pre_init(sc);
+	if (rc != 0)
+		goto done; /* error message displayed already */
 
-	/* Choose the global RSS mode. */
-	rc = -t4_config_glbl_rss(sc, sc->mbox,
-	    FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
-	    F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN |
-	    F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ |
-	    F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP);
-	if (rc != 0) {
-		device_printf(dev,
-		    "failed to select global RSS mode: %d.\n", rc);
-		goto done;
-	}
+	rc = t4_sge_init(sc);
+	if (rc != 0)
+		goto done; /* error message displayed already */
 
-	/* These are total (sum of all ports) limits for a bus driver */
-	rc = -t4_cfg_pfvf(sc, sc->mbox, sc->pf, 0,
-	    128,	/* max # of egress queues */
-	    64,		/* max # of egress Ethernet or control queues */
-	    64,		/* max # of ingress queues with fl/interrupt */
-	    0,		/* max # of ingress queues without interrupt */
-	    0,		/* PCIe traffic class */
-	    4,		/* max # of virtual interfaces */
-	    M_FW_PFVF_CMD_CMASK, M_FW_PFVF_CMD_PMASK, 16,
-	    FW_CMD_CAP_PF, FW_CMD_CAP_PF);
-	if (rc != 0) {
-		device_printf(dev,
-		    "failed to configure pf/vf resources: %d.\n", rc);
-		goto done;
+	if (sc->flags & MASTER_PF) {
+		/* get basic stuff going */
+		rc = -t4_fw_initialize(sc, sc->mbox);
+		if (rc != 0) {
+			device_printf(dev, "early init failed: %d.\n", rc);
+			goto done;
+		}
 	}
 
-	/* Need this before sge_init */
-	for (i = 0; i < SGE_NTIMERS; i++)
-		sc->sge.timer_val[i] = min(intr_timer[i], 200U);
-	for (i = 0; i < SGE_NCOUNTERS; i++)
-		sc->sge.counter_val[i] = min(intr_pktcount[i], M_THRESHOLD_0);
-
-	/* Also need the cooked value of cclk before sge_init */
-	p = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
-	    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
-	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &p, &v);
-	if (rc != 0) {
-		device_printf(sc->dev,
-		    "failed to obtain core clock value: %d.\n", rc);
-		goto done;
-	}
-	sc->params.vpd.cclk = v;
+	rc = get_params__post_init(sc);
+	if (rc != 0)
+		goto done; /* error message displayed already */
 
-	t4_sge_init(sc);
+	if (sc->flags & MASTER_PF) {
 
-	t4_set_filter_mode(sc, filter_mode);
-	t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG,
-	    V_FIVETUPLELOOKUP(M_FIVETUPLELOOKUP),
-	    V_FIVETUPLELOOKUP(M_FIVETUPLELOOKUP));
-	t4_tp_wr_bits_indirect(sc, A_TP_INGRESS_CONFIG, F_CSUM_HAS_PSEUDO_HDR,
-	    F_LOOKUPEVERYPKT);
+		/* final tweaks to some settings */
 
-	/* get basic stuff going */
-	rc = -t4_early_init(sc, sc->mbox);
-	if (rc != 0) {
-		device_printf(dev, "early init failed: %d.\n", rc);
-		goto done;
+		t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd,
+		    sc->params.b_wnd);
+		t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12));
+		t4_set_reg_field(sc, A_TP_PARA_REG3, F_TUNNELCNGDROP0 |
+		    F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 | F_TUNNELCNGDROP3, 0);
+		t4_set_reg_field(sc, A_TP_PARA_REG5,
+		    V_INDICATESIZE(M_INDICATESIZE) |
+		    F_REARMDDPOFFSET | F_RESETDDPOFFSET,
+		    V_INDICATESIZE(M_INDICATESIZE) |
+		    F_REARMDDPOFFSET | F_RESETDDPOFFSET);
+	} else {
+		/*
+		 * XXX: Verify that we can live with whatever the master driver
+		 * has done so far, and hope that it doesn't change any global
+		 * setting from underneath us in the future.
+		 */
 	}
 
-	rc = get_params(sc, &caps);
-	if (rc != 0)
-		goto done; /* error message displayed already */
-
-	/* These are finalized by FW initialization, load their values now */
-	v = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
-	sc->params.tp.tre = G_TIMERRESOLUTION(v);
-	sc->params.tp.dack_re = G_DELAYEDACKRESOLUTION(v);
-	t4_read_mtu_tbl(sc, sc->params.mtus, NULL);
-
-	/* tweak some settings */
-	t4_write_reg(sc, A_TP_SHIFT_CNT, V_SYNSHIFTMAX(6) | V_RXTSHIFTMAXR1(4) |
-	    V_RXTSHIFTMAXR2(15) | V_PERSHIFTBACKOFFMAX(8) | V_PERSHIFTMAX(8) |
-	    V_KEEPALIVEMAXR1(4) | V_KEEPALIVEMAXR2(9));
-	t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12));
-	t4_set_reg_field(sc, A_TP_PARA_REG3, F_TUNNELCNGDROP0 |
-	    F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 | F_TUNNELCNGDROP3, 0);
+	t4_read_indirect(sc, A_TP_PIO_ADDR, A_TP_PIO_DATA, &sc->filter_mode, 1,
+	    A_TP_VLAN_PRI_MAP);
 
-	setup_memwin(sc);
+	for (i = 0; i < NCHAN; i++)
+		sc->params.tp.tx_modq[i] = i;
 
 	rc = t4_create_dma_tag(sc);
 	if (rc != 0)
@@ -536,31 +553,18 @@ t4_attach(device_t dev)
 
 		if (is_10G_port(pi)) {
 			n10g++;
-			pi->tmr_idx = tmr_idx_10g;
-			pi->pktc_idx = pktc_idx_10g;
+			pi->tmr_idx = t4_tmr_idx_10g;
+			pi->pktc_idx = t4_pktc_idx_10g;
 		} else {
 			n1g++;
-			pi->tmr_idx = tmr_idx_1g;
-			pi->pktc_idx = pktc_idx_1g;
+			pi->tmr_idx = t4_tmr_idx_1g;
+			pi->pktc_idx = t4_pktc_idx_1g;
 		}
 
 		pi->xact_addr_filt = -1;
 
-		pi->qsize_rxq = max(qsize_rxq, 128);
-		while (pi->qsize_rxq & 7)
-			pi->qsize_rxq++;
-		pi->qsize_txq = max(qsize_txq, 128);
-
-		if (pi->qsize_rxq != qsize_rxq) {
-			device_printf(dev,
-			    "using %d instead of %d as the rx queue size.\n",
-			    pi->qsize_rxq, qsize_rxq);
-		}
-		if (pi->qsize_txq != qsize_txq) {
-			device_printf(dev,
-			    "using %d instead of %d as the tx queue size.\n",
-			    pi->qsize_txq, qsize_txq);
-		}
+		pi->qsize_rxq = t4_qsize_rxq;
+		pi->qsize_txq = t4_qsize_txq;
 
 		pi->dev = device_add_child(dev, "cxgbe", -1);
 		if (pi->dev == NULL) {
@@ -570,14 +574,6 @@ t4_attach(device_t dev)
 			goto done;
 		}
 		device_set_softc(pi->dev, pi);
-
-		setbit(&sc->registered_device_map, i);
-	}
-
-	if (sc->registered_device_map == 0) {
-		device_printf(dev, "no usable ports\n");
-		rc = ENXIO;
-		goto done;
 	}
 
 	/*
@@ -589,20 +585,31 @@ t4_attach(device_t dev)
 
 	sc->intr_type = iaq.intr_type;
 	sc->intr_count = iaq.nirq;
+	sc->flags |= iaq.intr_flags;
 
 	s = &sc->sge;
 	s->nrxq = n10g * iaq.nrxq10g + n1g * iaq.nrxq1g;
 	s->ntxq = n10g * iaq.ntxq10g + n1g * iaq.ntxq1g;
 	s->neq = s->ntxq + s->nrxq;	/* the free list in an rxq is an eq */
-	s->neq += sc->params.nports;	/* control queues, 1 per port */
+	s->neq += sc->params.nports + 1;/* ctrl queues: 1 per port + 1 mgmt */
 	s->niq = s->nrxq + 1;		/* 1 extra for firmware event queue */
-	if (iaq.intr_shared)
-		sc->flags |= INTR_SHARED;
-	s->niq += NINTRQ(sc);		/* interrupt queues */
 
-	s->intrq = malloc(NINTRQ(sc) * sizeof(struct sge_iq), M_CXGBE,
-	    M_ZERO | M_WAITOK);
-	s->ctrlq = malloc(sc->params.nports * sizeof(struct sge_ctrlq), M_CXGBE,
+#ifndef TCP_OFFLOAD_DISABLE
+	if (is_offload(sc)) {
+
+		s->nofldrxq = n10g * iaq.nofldrxq10g + n1g * iaq.nofldrxq1g;
+		s->nofldtxq = n10g * iaq.nofldtxq10g + n1g * iaq.nofldtxq1g;
+		s->neq += s->nofldtxq + s->nofldrxq;
+		s->niq += s->nofldrxq;
+
+		s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
+		    M_CXGBE, M_ZERO | M_WAITOK);
+		s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq),
+		    M_CXGBE, M_ZERO | M_WAITOK);
+	}
+#endif
+
+	s->ctrlq = malloc(sc->params.nports * sizeof(struct sge_wrq), M_CXGBE,
 	    M_ZERO | M_WAITOK);
 	s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
 	    M_ZERO | M_WAITOK);
@@ -616,15 +623,16 @@ t4_attach(device_t dev)
 	sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
 	    M_ZERO | M_WAITOK);
 
-	sc->l2t = t4_init_l2t(M_WAITOK);
-
-	t4_sysctls(sc);
+	t4_init_l2t(sc, M_WAITOK);
 
 	/*
 	 * Second pass over the ports.  This time we know the number of rx and
 	 * tx queues that each port should get.
 	 */
 	rqidx = tqidx = 0;
+#ifndef TCP_OFFLOAD_DISABLE
+	ofld_rqidx = ofld_tqidx = 0;
+#endif
 	for_each_port(sc, i) {
 		struct port_info *pi = sc->port[i];
 
@@ -632,13 +640,33 @@ t4_attach(device_t dev)
 			continue;
 
 		pi->first_rxq = rqidx;
-		pi->nrxq = is_10G_port(pi) ? iaq.nrxq10g : iaq.nrxq1g;
-
 		pi->first_txq = tqidx;
-		pi->ntxq = is_10G_port(pi) ? iaq.ntxq10g : iaq.ntxq1g;
+		if (is_10G_port(pi)) {
+			pi->nrxq = iaq.nrxq10g;
+			pi->ntxq = iaq.ntxq10g;
+		} else {
+			pi->nrxq = iaq.nrxq1g;
+			pi->ntxq = iaq.ntxq1g;
+		}
 
 		rqidx += pi->nrxq;
 		tqidx += pi->ntxq;
+
+#ifndef TCP_OFFLOAD_DISABLE
+		if (is_offload(sc)) {
+			pi->first_ofld_rxq = ofld_rqidx;
+			pi->first_ofld_txq = ofld_tqidx;
+			if (is_10G_port(pi)) {
+				pi->nofldrxq = iaq.nofldrxq10g;
+				pi->nofldtxq = iaq.nofldtxq10g;
+			} else {
+				pi->nofldrxq = iaq.nofldrxq1g;
+				pi->nofldtxq = iaq.nofldtxq1g;
+			}
+			ofld_rqidx += pi->nofldrxq;
+			ofld_tqidx += pi->nofldtxq;
+		}
+#endif
 	}
 
 	rc = bus_generic_attach(dev);
@@ -648,17 +676,27 @@ t4_attach(device_t dev)
 		goto done;
 	}
 
-#ifdef INVARIANTS
 	device_printf(dev,
-	    "%p, %d ports (0x%x), %d intr_type, %d intr_count\n",
-	    sc, sc->params.nports, sc->params.portvec,
-	    sc->intr_type, sc->intr_count);
-#endif
+	    "PCIe x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
+	    sc->params.pci.width, sc->params.nports, sc->intr_count,
+	    sc->intr_type == INTR_MSIX ? "MSI-X" :
+	    (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
+	    sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
+
 	t4_set_desc(sc);
 
 done:
+	if (rc != 0 && sc->cdev) {
+		/* cdev was created and so cxgbetool works; recover that way. */
+		device_printf(dev,
+		    "error during attach, adapter is now in recovery mode.\n");
+		rc = 0;
+	}
+
 	if (rc != 0)
 		t4_detach(dev);
+	else
+		t4_sysctls(sc);
 
 	return (rc);
 }
@@ -671,14 +709,25 @@ t4_detach(device_t dev)
 {
 	struct adapter *sc;
 	struct port_info *pi;
-	int i;
+	int i, rc;
 
 	sc = device_get_softc(dev);
 
-	if (sc->cdev)
+	if (sc->flags & FULL_INIT_DONE)
+		t4_intr_disable(sc);
+
+	if (sc->cdev) {
 		destroy_dev(sc->cdev);
+		sc->cdev = NULL;
+	}
+
+	rc = bus_generic_detach(dev);
+	if (rc) {
+		device_printf(dev,
+		    "failed to detach child devices: %d\n", rc);
+		return (rc);
+	}
 
-	bus_generic_detach(dev);
 	for (i = 0; i < MAX_NPORTS; i++) {
 		pi = sc->port[i];
 		if (pi) {
@@ -691,6 +740,9 @@ t4_detach(device_t dev)
 		}
 	}
 
+	if (sc->flags & FULL_INIT_DONE)
+		adapter_full_uninit(sc);
+
 	if (sc->flags & FW_OK)
 		t4_fw_bye(sc, sc->mbox);
 
@@ -708,16 +760,27 @@ t4_detach(device_t dev)
 	if (sc->l2t)
 		t4_free_l2t(sc->l2t);
 
+#ifndef TCP_OFFLOAD_DISABLE
+	free(sc->sge.ofld_rxq, M_CXGBE);
+	free(sc->sge.ofld_txq, M_CXGBE);
+#endif
 	free(sc->irq, M_CXGBE);
 	free(sc->sge.rxq, M_CXGBE);
 	free(sc->sge.txq, M_CXGBE);
 	free(sc->sge.ctrlq, M_CXGBE);
-	free(sc->sge.intrq, M_CXGBE);
 	free(sc->sge.iqmap, M_CXGBE);
 	free(sc->sge.eqmap, M_CXGBE);
 	free(sc->tids.ftid_tab, M_CXGBE);
 	t4_destroy_dma_tag(sc);
-	mtx_destroy(&sc->sc_lock);
+	if (mtx_initialized(&sc->sc_lock)) {
+		mtx_lock(&t4_list_lock);
+		SLIST_REMOVE(&t4_list, sc, adapter, link);
+		mtx_unlock(&t4_list_lock);
+		mtx_destroy(&sc->sc_lock);
+	}
+
+	if (mtx_initialized(&sc->sfl_lock))
+		mtx_destroy(&sc->sfl_lock);
 
 	bzero(sc, sizeof(*sc));
 
@@ -731,7 +794,7 @@ cxgbe_probe(device_t dev)
 	char buf[128];
 	struct port_info *pi = device_get_softc(dev);
 
-	snprintf(buf, sizeof(buf), "Port %d", pi->port_id);
+	snprintf(buf, sizeof(buf), "port %d", pi->port_id);
 	device_set_desc_copy(dev, buf);
 
 	return (BUS_PROBE_DEFAULT);
@@ -758,15 +821,6 @@ cxgbe_attach(device_t dev)
 	ifp->if_softc = pi;
 
 	callout_init(&pi->tick, CALLOUT_MPSAFE);
-	pi->tq = taskqueue_create("cxgbe_taskq", M_NOWAIT,
-	    taskqueue_thread_enqueue, &pi->tq);
-	if (pi->tq == NULL) {
-		device_printf(dev, "failed to allocate port task queue\n");
-		if_free(pi->ifp);
-		return (ENOMEM);
-	}
-	taskqueue_start_threads(&pi->tq, 1, PI_NET, "%s taskq",
-	    device_get_nameunit(dev));
 
 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
@@ -782,6 +836,10 @@ cxgbe_attach(device_t dev)
 	IFQ_SET_READY(&ifp->if_snd);
 
 	ifp->if_capabilities = T4_CAP;
+#ifndef TCP_OFFLOAD_DISABLE
+	if (is_offload(pi->adapter))
+		ifp->if_capabilities |= IFCAP_TOE4;
+#endif
 	ifp->if_capenable = T4_CAP_ENABLE;
 	ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO;
 
@@ -792,9 +850,14 @@ cxgbe_attach(device_t dev)
 
 	ether_ifattach(ifp, pi->hw_addr);
 
-#ifdef INVARIANTS
-	device_printf(dev, "%p, %d txq, %d rxq\n", pi, pi->ntxq, pi->nrxq);
+#ifndef TCP_OFFLOAD_DISABLE
+	if (is_offload(pi->adapter)) {
+		device_printf(dev,
+		    "%d txq, %d rxq (NIC); %d txq, %d rxq (TOE)\n",
+		    pi->ntxq, pi->nrxq, pi->nofldtxq, pi->nofldrxq);
+	} else
 #endif
+		device_printf(dev, "%d txq, %d rxq\n", pi->ntxq, pi->nrxq);
 
 	cxgbe_sysctls(pi);
 
@@ -806,7 +869,7 @@ cxgbe_detach(device_t dev)
 {
 	struct port_info *pi = device_get_softc(dev);
 	struct adapter *sc = pi->adapter;
-	int rc;
+	struct ifnet *ifp = pi->ifp;
 
 	/* Tell if_ioctl and if_init that the port is going away */
 	ADAPTER_LOCK(sc);
@@ -817,11 +880,15 @@ cxgbe_detach(device_t dev)
 	SET_BUSY(sc);
 	ADAPTER_UNLOCK(sc);
 
-	rc = cxgbe_uninit_synchronized(pi);
-	if (rc != 0)
-		device_printf(dev, "port uninit failed: %d.\n", rc);
+	PORT_LOCK(pi);
+	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+	callout_stop(&pi->tick);
+	PORT_UNLOCK(pi);
+	callout_drain(&pi->tick);
 
-	taskqueue_free(pi->tq);
+	/* Let detach proceed even if these fail. */
+	cxgbe_uninit_synchronized(pi);
+	port_full_uninit(pi);
 
 	ifmedia_removeall(&pi->media);
 	ether_ifdetach(pi->ifp);
@@ -960,6 +1027,7 @@ fail:
 					if_printf(ifp,
 					    "enable txcsum first.\n");
 					rc = EAGAIN;
+					goto fail;
 				}
 			} else
 				ifp->if_hwassist &= ~CSUM_TSO;
@@ -972,15 +1040,21 @@ fail:
 			ifp->if_capenable ^= IFCAP_LRO;
 			for_each_rxq(pi, i, rxq) {
 				if (ifp->if_capenable & IFCAP_LRO)
-					rxq->flags |= RXQ_LRO_ENABLED;
+					rxq->iq.flags |= IQ_LRO_ENABLED;
 				else
-					rxq->flags &= ~RXQ_LRO_ENABLED;
+					rxq->iq.flags &= ~IQ_LRO_ENABLED;
 			}
 #endif
 		}
 #ifndef TCP_OFFLOAD_DISABLE
-		if (mask & IFCAP_TOE4) {
-			rc = EOPNOTSUPP;
+		if (mask & IFCAP_TOE) {
+			int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE;
+
+			rc = toe_capability(pi, enable);
+			if (rc != 0)
+				goto fail;
+
+			ifp->if_capenable ^= mask;
 		}
 #endif
 		if (mask & IFCAP_VLAN_HWTAGGING) {
@@ -1045,9 +1119,9 @@ cxgbe_transmit(struct ifnet *ifp, struct mbuf *m)
 
 	M_ASSERTPKTHDR(m);
 
-	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
+	if (__predict_false(pi->link_cfg.link_ok == 0)) {
 		m_freem(m);
-		return (0);
+		return (ENETDOWN);
 	}
 
 	if (m->m_flags & M_FLOWID)
@@ -1055,13 +1129,20 @@ cxgbe_transmit(struct ifnet *ifp, struct mbuf *m)
 	br = txq->br;
 
 	if (TXQ_TRYLOCK(txq) == 0) {
+		struct sge_eq *eq = &txq->eq;
+
 		/*
-		 * XXX: make sure that this packet really is sent out.  There is
-		 * a small race where t4_eth_tx may stop draining the drbr and
-		 * goes away, just before we enqueued this mbuf.
+		 * It is possible that t4_eth_tx finishes up and releases the
+		 * lock between the TRYLOCK above and the drbr_enqueue here.  We
+		 * need to make sure that this mbuf doesn't just sit there in
+		 * the drbr.
 		 */
 
-		return (drbr_enqueue(ifp, br, m));
+		rc = drbr_enqueue(ifp, br, m);
+		if (rc == 0 && callout_pending(&eq->tx_callout) == 0 &&
+		    !(eq->flags & EQ_DOOMED))
+			callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq);
+		return (rc);
 	}
 
 	/*
@@ -1102,11 +1183,12 @@ cxgbe_qflush(struct ifnet *ifp)
 	int i;
 	struct mbuf *m;
 
-	/* queues do not exist if !IFF_DRV_RUNNING. */
-	if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
+	/* queues do not exist if !PORT_INIT_DONE. */
+	if (pi->flags & PORT_INIT_DONE) {
 		for_each_txq(pi, i, txq) {
 			TXQ_LOCK(txq);
 			m_freem(txq->m);
+			txq->m = NULL;
 			while ((m = buf_ring_dequeue_sc(txq->br)) != NULL)
 				m_freem(m);
 			TXQ_UNLOCK(txq);
@@ -1220,14 +1302,25 @@ static int
 cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g,
     struct intrs_and_queues *iaq)
 {
-	int rc, itype, navail, nc, nrxq10g, nrxq1g;
+	int rc, itype, navail, nrxq10g, nrxq1g, n;
+	int nofldrxq10g = 0, nofldrxq1g = 0;
 
 	bzero(iaq, sizeof(*iaq));
-	nc = mp_ncpus;	/* our snapshot of the number of CPUs */
+
+	iaq->ntxq10g = t4_ntxq10g;
+	iaq->ntxq1g = t4_ntxq1g;
+	iaq->nrxq10g = nrxq10g = t4_nrxq10g;
+	iaq->nrxq1g = nrxq1g = t4_nrxq1g;
+#ifndef TCP_OFFLOAD_DISABLE
+	iaq->nofldtxq10g = t4_nofldtxq10g;
+	iaq->nofldtxq1g = t4_nofldtxq1g;
+	iaq->nofldrxq10g = nofldrxq10g = t4_nofldrxq10g;
+	iaq->nofldrxq1g = nofldrxq1g = t4_nofldrxq1g;
+#endif
 
 	for (itype = INTR_MSIX; itype; itype >>= 1) {
 
-		if ((itype & intr_types) == 0)
+		if ((itype & t4_intr_types) == 0)
 			continue;	/* not allowed */
 
 		if (itype == INTR_MSIX)
@@ -1236,60 +1329,93 @@ cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g,
 			navail = pci_msi_count(sc->dev);
 		else
 			navail = 1;
-
+restart:
 		if (navail == 0)
 			continue;
 
 		iaq->intr_type = itype;
+		iaq->intr_flags = 0;
 
-		iaq->ntxq10g = min(nc, max_ntxq_10g);
-		iaq->ntxq1g = min(nc, max_ntxq_1g);
-
-		nrxq10g = min(nc, max_nrxq_10g);
-		nrxq1g = min(nc, max_nrxq_1g);
-
-		iaq->nirq = n10g * nrxq10g + n1g * nrxq1g + T4_EXTRA_INTR;
-		if (iaq->nirq <= navail && intr_shared == 0) {
-
-			if (itype == INTR_MSI && !powerof2(iaq->nirq))
-				goto share;
-
-			/* One for err, one for fwq, and one for each rxq */
-
-			iaq->intr_shared = 0;
-			iaq->nrxq10g = nrxq10g;
-			iaq->nrxq1g = nrxq1g;
+		/*
+		 * Best option: an interrupt vector for errors, one for the
+		 * firmware event queue, and one each for each rxq (NIC as well
+		 * as offload).
+		 */
+		iaq->nirq = T4_EXTRA_INTR;
+		iaq->nirq += n10g * (nrxq10g + nofldrxq10g);
+		iaq->nirq += n1g * (nrxq1g + nofldrxq1g);
+		if (iaq->nirq <= navail &&
+		    (itype != INTR_MSI || powerof2(iaq->nirq))) {
+			iaq->intr_flags |= INTR_DIRECT;
+			goto allocate;
+		}
 
-		} else {
-share:
-			iaq->intr_shared = 1;
+		/*
+		 * Second best option: an interrupt vector for errors, one for
+		 * the firmware event queue, and one each for either NIC or
+		 * offload rxq's.
+		 */
+		iaq->nirq = T4_EXTRA_INTR;
+		iaq->nirq += n10g * max(nrxq10g, nofldrxq10g);
+		iaq->nirq += n1g * max(nrxq1g, nofldrxq1g);
+		if (iaq->nirq <= navail &&
+		    (itype != INTR_MSI || powerof2(iaq->nirq)))
+			goto allocate;
 
-			if (navail >= nc + T4_EXTRA_INTR) {
-				if (itype == INTR_MSIX)
-					navail = nc + T4_EXTRA_INTR;
+		/*
+		 * Next best option: an interrupt vector for errors, one for the
+		 * firmware event queue, and at least one per port.  At this
+		 * point we know we'll have to downsize nrxq or nofldrxq to fit
+		 * what's available to us.
+		 */
+		iaq->nirq = T4_EXTRA_INTR;
+		iaq->nirq += n10g + n1g;
+		if (iaq->nirq <= navail) {
+			int leftover = navail - iaq->nirq;
+
+			if (n10g > 0) {
+				int target = max(nrxq10g, nofldrxq10g);
+
+				n = 1;
+				while (n < target && leftover >= n10g) {
+					leftover -= n10g;
+					iaq->nirq += n10g;
+					n++;
+				}
+				iaq->nrxq10g = min(n, nrxq10g);
+#ifndef TCP_OFFLOAD_DISABLE
+				iaq->nofldrxq10g = min(n, nofldrxq10g);
+#endif
+			}
 
-				/* navail is and must remain a pow2 for MSI */
-				if (itype == INTR_MSI) {
-					KASSERT(powerof2(navail),
-					    ("%d not power of 2", navail));
+			if (n1g > 0) {
+				int target = max(nrxq1g, nofldrxq1g);
 
-					while (navail / 2 >= nc + T4_EXTRA_INTR)
-						navail /= 2;
+				n = 1;
+				while (n < target && leftover >= n1g) {
+					leftover -= n1g;
+					iaq->nirq += n1g;
+					n++;
 				}
+				iaq->nrxq1g = min(n, nrxq1g);
+#ifndef TCP_OFFLOAD_DISABLE
+				iaq->nofldrxq1g = min(n, nofldrxq1g);
+#endif
 			}
-			iaq->nirq = navail;	/* total # of interrupts */
 
-			/*
-			 * If we have multiple vectors available reserve one
-			 * exclusively for errors.  The rest will be shared by
-			 * the fwq and data.
-			 */
-			if (navail > 1)
-				navail--;
-			iaq->nrxq10g = min(nrxq10g, navail);
-			iaq->nrxq1g = min(nrxq1g, navail);
+			if (itype != INTR_MSI || powerof2(iaq->nirq))
+				goto allocate;
 		}
 
+		/*
+		 * Least desirable option: one interrupt vector for everything.
+		 */
+		iaq->nirq = iaq->nrxq10g = iaq->nrxq1g = 1;
+#ifndef TCP_OFFLOAD_DISABLE
+		iaq->nofldrxq10g = iaq->nofldrxq1g = 1;
+#endif
+
+allocate:
 		navail = iaq->nirq;
 		rc = 0;
 		if (itype == INTR_MSIX)
@@ -1305,8 +1431,11 @@ share:
 			 * Didn't get the number requested.  Use whatever number
 			 * the kernel is willing to allocate (it's in navail).
 			 */
+			device_printf(sc->dev, "fewer vectors than requested, "
+			    "type=%d, req=%d, rcvd=%d; will downshift req.\n",
+			    itype, iaq->nirq, navail);
 			pci_release_msi(sc->dev);
-			goto share;
+			goto restart;
 		}
 
 		device_printf(sc->dev,
@@ -1316,26 +1445,30 @@ share:
 
 	device_printf(sc->dev,
 	    "failed to find a usable interrupt type.  "
-	    "allowed=%d, msi-x=%d, msi=%d, intx=1", intr_types,
+	    "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
 	    pci_msix_count(sc->dev), pci_msi_count(sc->dev));
 
 	return (ENXIO);
 }
 
 /*
- * Install a compatible firmware (if required), establish contact with it,
- * become the master, and reset the device.
+ * Install a compatible firmware (if required), establish contact with it (by
+ * saying hello), and reset the device.  If we end up as the master driver,
+ * partition adapter resources by providing a configuration file to the
+ * firmware.
  */
 static int
 prep_firmware(struct adapter *sc)
 {
-	const struct firmware *fw;
+	const struct firmware *fw = NULL, *cfg = NULL, *default_cfg;
 	int rc;
 	enum dev_state state;
 
+	default_cfg = firmware_get(T4_CFGNAME);
+
 	/* Check firmware version and install a different one if necessary */
 	rc = t4_check_fw_version(sc);
-	if (rc != 0 || force_firmware_install) {
+	if (rc != 0) {
 		uint32_t v = 0;
 
 		fw = firmware_get(T4_FWNAME);
@@ -1347,7 +1480,7 @@ prep_firmware(struct adapter *sc)
 			/*
 			 * The firmware module will not be used if it isn't the
 			 * same major version as what the driver was compiled
-			 * with.  This check trumps force_firmware_install.
+			 * with.
 			 */
 			if (G_FW_HDR_FW_VER_MAJOR(v) != FW_VERSION_MAJOR) {
 				device_printf(sc->dev,
@@ -1360,17 +1493,16 @@ prep_firmware(struct adapter *sc)
 			}
 		}
 
-		if (fw == NULL && (rc < 0 || force_firmware_install)) {
+		if (fw == NULL && rc < 0) {
 			device_printf(sc->dev, "No usable firmware. "
-			    "card has %d.%d.%d, driver compiled with %d.%d.%d, "
-			    "force_firmware_install%s set",
+			    "card has %d.%d.%d, driver compiled with %d.%d.%d",
 			    G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
 			    G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
 			    G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
 			    FW_VERSION_MAJOR, FW_VERSION_MINOR,
-			    FW_VERSION_MICRO,
-			    force_firmware_install ? "" : " not");
-			return (EAGAIN);
+			    FW_VERSION_MICRO);
+			rc = EAGAIN;
+			goto done;
 		}
 
 		/*
@@ -1378,8 +1510,7 @@ prep_firmware(struct adapter *sc)
 		 * Downgrade only for a major version mismatch or if
 		 * force_firmware_install was specified.
 		 */
-		if (fw != NULL && (rc < 0 || force_firmware_install ||
-		    v > sc->params.fw_vers)) {
+		if (fw != NULL && (rc < 0 || v > sc->params.fw_vers)) {
 			device_printf(sc->dev,
 			    "installing firmware %d.%d.%d.%d on card.\n",
 			    G_FW_HDR_FW_VER_MAJOR(v), G_FW_HDR_FW_VER_MINOR(v),
@@ -1389,26 +1520,24 @@ prep_firmware(struct adapter *sc)
 			if (rc != 0) {
 				device_printf(sc->dev,
 				    "failed to install firmware: %d\n", rc);
-				firmware_put(fw, FIRMWARE_UNLOAD);
-				return (rc);
+				goto done;
 			} else {
 				/* refresh */
 				(void) t4_check_fw_version(sc);
 			}
 		}
-
-		if (fw != NULL)
-			firmware_put(fw, FIRMWARE_UNLOAD);
 	}
 
-	/* Contact firmware, request master */
-	rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MUST, &state);
+	/* Contact firmware.  */
+	rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
 	if (rc < 0) {
 		rc = -rc;
 		device_printf(sc->dev,
 		    "failed to connect to the firmware: %d.\n", rc);
-		return (rc);
+		goto done;
 	}
+	if (rc == sc->mbox)
+		sc->flags |= MASTER_PF;
 
 	/* Reset device */
 	rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST);
@@ -1416,7 +1545,26 @@ prep_firmware(struct adapter *sc)
 		device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
 		if (rc != ETIMEDOUT && rc != EIO)
 			t4_fw_bye(sc, sc->mbox);
-		return (rc);
+		goto done;
+	}
+
+	/* Partition adapter resources as specified in the config file. */
+	if (sc->flags & MASTER_PF) {
+		if (strncmp(t4_cfg_file, "default", sizeof(t4_cfg_file))) {
+			char s[32];
+
+			snprintf(s, sizeof(s), "t4fw_cfg_%s", t4_cfg_file);
+			cfg = firmware_get(s);
+			if (cfg == NULL) {
+				device_printf(sc->dev,
+				    "unable to locate %s module, "
+				    "will use default config file.\n", s);
+			}
+		}
+
+		rc = partition_resources(sc, cfg ? cfg : default_cfg);
+		if (rc != 0)
+			goto done;	/* error message displayed already */
 	}
 
 	snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
@@ -1426,84 +1574,207 @@ prep_firmware(struct adapter *sc)
 	    G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
 	sc->flags |= FW_OK;
 
-	return (0);
+done:
+	if (fw != NULL)
+		firmware_put(fw, FIRMWARE_UNLOAD);
+	if (cfg != NULL)
+		firmware_put(cfg, FIRMWARE_UNLOAD);
+	if (default_cfg != NULL)
+		firmware_put(default_cfg, FIRMWARE_UNLOAD);
+
+	return (rc);
 }
 
+#define FW_PARAM_DEV(param) \
+	(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
+	 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
+#define FW_PARAM_PFVF(param) \
+	(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
+	 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
+
+/*
+ * Upload configuration file to card's memory.
+ */
 static int
-get_devlog_params(struct adapter *sc, struct devlog_params *dlog)
+upload_config_file(struct adapter *sc, const struct firmware *fw, uint32_t *mt,
+    uint32_t *ma)
 {
-	struct fw_devlog_cmd devlog_cmd;
-	uint32_t meminfo;
-	int rc;
+	int rc, i;
+	uint32_t param, val, mtype, maddr, bar, off, win, remaining;
+	const uint32_t *b;
 
-	bzero(&devlog_cmd, sizeof(devlog_cmd));
-	devlog_cmd.op_to_write = htobe32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
-	    F_FW_CMD_REQUEST | F_FW_CMD_READ);
-	devlog_cmd.retval_len16 = htobe32(FW_LEN16(devlog_cmd));
-	rc = -t4_wr_mbox(sc, sc->mbox, &devlog_cmd, sizeof(devlog_cmd),
-	    &devlog_cmd);
+	/* Figure out where the firmware wants us to upload it. */
+	param = FW_PARAM_DEV(CF);
+	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
 	if (rc != 0) {
+		/* Firmwares without config file support will fail this way */
 		device_printf(sc->dev,
-		    "failed to get devlog parameters: %d.\n", rc);
-		bzero(dlog, sizeof (*dlog));
+		    "failed to query config file location: %d.\n", rc);
 		return (rc);
 	}
+	*mt = mtype = G_FW_PARAMS_PARAM_Y(val);
+	*ma = maddr = G_FW_PARAMS_PARAM_Z(val) << 16;
 
-	meminfo = be32toh(devlog_cmd.memtype_devlog_memaddr16_devlog);
-	dlog->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(meminfo);
-	dlog->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(meminfo) << 4;
-	dlog->size = be32toh(devlog_cmd.memsize_devlog);
+	if (maddr & 3) {
+		device_printf(sc->dev,
+		    "cannot upload config file (type %u, addr %x).\n",
+		    mtype, maddr);
+		return (EFAULT);
+	}
 
-	return (0);
+	/* Translate mtype/maddr to an address suitable for the PCIe window */
+	val = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
+	val &= F_EDRAM0_ENABLE | F_EDRAM1_ENABLE | F_EXT_MEM_ENABLE;
+	switch (mtype) {
+	case FW_MEMTYPE_CF_EDC0:
+		if (!(val & F_EDRAM0_ENABLE))
+			goto err;
+		bar = t4_read_reg(sc, A_MA_EDRAM0_BAR);
+		maddr += G_EDRAM0_BASE(bar) << 20;
+		break;
+
+	case FW_MEMTYPE_CF_EDC1:
+		if (!(val & F_EDRAM1_ENABLE))
+			goto err;
+		bar = t4_read_reg(sc, A_MA_EDRAM1_BAR);
+		maddr += G_EDRAM1_BASE(bar) << 20;
+		break;
+
+	case FW_MEMTYPE_CF_EXTMEM:
+		if (!(val & F_EXT_MEM_ENABLE))
+			goto err;
+		bar = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
+		maddr += G_EXT_MEM_BASE(bar) << 20;
+		break;
+
+	default:
+err:
+		device_printf(sc->dev,
+		    "cannot upload config file (type %u, enabled %u).\n",
+		    mtype, val);
+		return (EFAULT);
+	}
+
+	/*
+	 * Position the PCIe window (we use memwin2) to the 16B aligned area
+	 * just at/before the upload location.
+	 */
+	win = maddr & ~0xf;
+	off = maddr - win;  /* offset from the start of the window. */
+	t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2), win);
+	t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2));
+
+	remaining = fw->datasize;
+	if (remaining > FLASH_CFG_MAX_SIZE ||
+	    remaining > MEMWIN2_APERTURE - off) {
+		device_printf(sc->dev, "cannot upload config file all at once "
+		    "(size %u, max %u, room %u).\n",
+		    remaining, FLASH_CFG_MAX_SIZE, MEMWIN2_APERTURE - off);
+		return (EFBIG);
+	}
+
+	/*
+	 * XXX: sheer laziness.  We deliberately added 4 bytes of useless
+	 * stuffing/comments at the end of the config file so it's ok to simply
+	 * throw away the last remaining bytes when the config file is not an
+	 * exact multiple of 4.
+	 */
+	b = fw->data;
+	for (i = 0; remaining >= 4; i += 4, remaining -= 4)
+		t4_write_reg(sc, MEMWIN2_BASE + off + i, *b++);
+
+	return (rc);
 }
 
+/*
+ * Partition chip resources for use between various PFs, VFs, etc.  This is done
+ * by uploading the firmware configuration file to the adapter and instructing
+ * the firmware to process it.
+ */
 static int
-get_capabilities(struct adapter *sc, struct fw_caps_config_cmd *caps)
+partition_resources(struct adapter *sc, const struct firmware *cfg)
 {
 	int rc;
+	struct fw_caps_config_cmd caps;
+	uint32_t mtype, maddr, finicsum, cfcsum;
 
-	bzero(caps, sizeof(*caps));
-	caps->op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
-	    F_FW_CMD_REQUEST | F_FW_CMD_READ);
-	caps->retval_len16 = htobe32(FW_LEN16(*caps));
+	rc = cfg ? upload_config_file(sc, cfg, &mtype, &maddr) : ENOENT;
+	if (rc != 0) {
+		mtype = FW_MEMTYPE_CF_FLASH;
+		maddr = t4_flash_cfg_addr(sc);
+	}
 
-	rc = -t4_wr_mbox(sc, sc->mbox, caps, sizeof(*caps), caps);
-	if (rc != 0)
+	bzero(&caps, sizeof(caps));
+	caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
+	    F_FW_CMD_REQUEST | F_FW_CMD_READ);
+	caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
+	    V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
+	    V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) | FW_LEN16(caps));
+	rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
+	if (rc != 0) {
+		device_printf(sc->dev,
+		    "failed to pre-process config file: %d.\n", rc);
 		return (rc);
+	}
+
+	finicsum = be32toh(caps.finicsum);
+	cfcsum = be32toh(caps.cfcsum);
+	if (finicsum != cfcsum) {
+		device_printf(sc->dev,
+		    "WARNING: config file checksum mismatch: %08x %08x\n",
+		    finicsum, cfcsum);
+	}
+	sc->cfcsum = cfcsum;
 
-	if (caps->niccaps & htobe16(FW_CAPS_CONFIG_NIC_VM))
-		caps->niccaps ^= htobe16(FW_CAPS_CONFIG_NIC_VM);
+#define LIMIT_CAPS(x) do { \
+	caps.x &= htobe16(t4_##x##_allowed); \
+	sc->x = htobe16(caps.x); \
+} while (0)
 
-	caps->op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
+	/*
+	 * Let the firmware know what features will (not) be used so it can tune
+	 * things accordingly.
+	 */
+	LIMIT_CAPS(linkcaps);
+	LIMIT_CAPS(niccaps);
+	LIMIT_CAPS(toecaps);
+	LIMIT_CAPS(rdmacaps);
+	LIMIT_CAPS(iscsicaps);
+	LIMIT_CAPS(fcoecaps);
+#undef LIMIT_CAPS
+
+	caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 	    F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
-	rc = -t4_wr_mbox(sc, sc->mbox, caps, sizeof(*caps), NULL);
+	caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
+	rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
+	if (rc != 0) {
+		device_printf(sc->dev,
+		    "failed to process config file: %d.\n", rc);
+		return (rc);
+	}
 
-	return (rc);
+	return (0);
 }
 
+/*
+ * Retrieve parameters that are needed (or nice to have) prior to calling
+ * t4_sge_init and t4_fw_initialize.
+ */
 static int
-get_params(struct adapter *sc, struct fw_caps_config_cmd *caps)
+get_params__pre_init(struct adapter *sc)
 {
 	int rc;
-	uint32_t params[7], val[7];
-
-#define FW_PARAM_DEV(param) \
-	(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
-	 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
-#define FW_PARAM_PFVF(param) \
-	(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
-	 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
+	uint32_t param[2], val[2];
+	struct fw_devlog_cmd cmd;
+	struct devlog_params *dlog = &sc->params.devlog;
 
-	params[0] = FW_PARAM_DEV(PORTVEC);
-	params[1] = FW_PARAM_PFVF(IQFLINT_START);
-	params[2] = FW_PARAM_PFVF(EQ_START);
-	params[3] = FW_PARAM_PFVF(FILTER_START);
-	params[4] = FW_PARAM_PFVF(FILTER_END);
-	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 5, params, val);
+	param[0] = FW_PARAM_DEV(PORTVEC);
+	param[1] = FW_PARAM_DEV(CCLK);
+	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
 	if (rc != 0) {
 		device_printf(sc->dev,
-		    "failed to query parameters: %d.\n", rc);
-		goto done;
+		    "failed to query parameters (pre_init): %d.\n", rc);
+		return (rc);
 	}
 
 	sc->params.portvec = val[0];
@@ -1513,24 +1784,81 @@ get_params(struct adapter *sc, struct fw_caps_config_cmd *caps)
 		val[0] &= val[0] - 1;
 	}
 
-	sc->sge.iq_start = val[1];
-	sc->sge.eq_start = val[2];
-	sc->tids.ftid_base = val[3];
-	sc->tids.nftids = val[4] - val[3] + 1;
+	sc->params.vpd.cclk = val[1];
+
+	/* Read device log parameters. */
+	bzero(&cmd, sizeof(cmd));
+	cmd.op_to_write = htobe32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
+	    F_FW_CMD_REQUEST | F_FW_CMD_READ);
+	cmd.retval_len16 = htobe32(FW_LEN16(cmd));
+	rc = -t4_wr_mbox(sc, sc->mbox, &cmd, sizeof(cmd), &cmd);
+	if (rc != 0) {
+		device_printf(sc->dev,
+		    "failed to get devlog parameters: %d.\n", rc);
+		bzero(dlog, sizeof (*dlog));
+		rc = 0;	/* devlog isn't critical for device operation */
+	} else {
+		val[0] = be32toh(cmd.memtype_devlog_memaddr16_devlog);
+		dlog->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(val[0]);
+		dlog->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(val[0]) << 4;
+		dlog->size = be32toh(cmd.memsize_devlog);
+	}
+
+	return (rc);
+}
+
+/*
+ * Retrieve various parameters that are of interest to the driver.  The device
+ * has been initialized by the firmware at this point.
+ */
+static int
+get_params__post_init(struct adapter *sc)
+{
+	int rc;
+	uint32_t param[7], val[7];
+	struct fw_caps_config_cmd caps;
+
+	param[0] = FW_PARAM_PFVF(IQFLINT_START);
+	param[1] = FW_PARAM_PFVF(EQ_START);
+	param[2] = FW_PARAM_PFVF(FILTER_START);
+	param[3] = FW_PARAM_PFVF(FILTER_END);
+	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val);
+	if (rc != 0) {
+		device_printf(sc->dev,
+		    "failed to query parameters (post_init): %d.\n", rc);
+		return (rc);
+	}
+
+	sc->sge.iq_start = val[0];
+	sc->sge.eq_start = val[1];
+	sc->tids.ftid_base = val[2];
+	sc->tids.nftids = val[3] - val[2] + 1;
 
-	if (caps->toecaps) {
+	/* get capabilites */
+	bzero(&caps, sizeof(caps));
+	caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
+	    F_FW_CMD_REQUEST | F_FW_CMD_READ);
+	caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
+	rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
+	if (rc != 0) {
+		device_printf(sc->dev,
+		    "failed to get card capabilities: %d.\n", rc);
+		return (rc);
+	}
+
+	if (caps.toecaps) {
 		/* query offload-related parameters */
-		params[0] = FW_PARAM_DEV(NTID);
-		params[1] = FW_PARAM_PFVF(SERVER_START);
-		params[2] = FW_PARAM_PFVF(SERVER_END);
-		params[3] = FW_PARAM_PFVF(TDDP_START);
-		params[4] = FW_PARAM_PFVF(TDDP_END);
-		params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
-		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, params, val);
+		param[0] = FW_PARAM_DEV(NTID);
+		param[1] = FW_PARAM_PFVF(SERVER_START);
+		param[2] = FW_PARAM_PFVF(SERVER_END);
+		param[3] = FW_PARAM_PFVF(TDDP_START);
+		param[4] = FW_PARAM_PFVF(TDDP_END);
+		param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
+		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
 		if (rc != 0) {
 			device_printf(sc->dev,
 			    "failed to query TOE parameters: %d.\n", rc);
-			goto done;
+			return (rc);
 		}
 		sc->tids.ntids = val[0];
 		sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
@@ -1541,18 +1869,18 @@ get_params(struct adapter *sc, struct fw_caps_config_cmd *caps)
 		sc->params.ofldq_wr_cred = val[5];
 		sc->params.offload = 1;
 	}
-	if (caps->rdmacaps) {
-		params[0] = FW_PARAM_PFVF(STAG_START);
-		params[1] = FW_PARAM_PFVF(STAG_END);
-		params[2] = FW_PARAM_PFVF(RQ_START);
-		params[3] = FW_PARAM_PFVF(RQ_END);
-		params[4] = FW_PARAM_PFVF(PBL_START);
-		params[5] = FW_PARAM_PFVF(PBL_END);
-		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, params, val);
+	if (caps.rdmacaps) {
+		param[0] = FW_PARAM_PFVF(STAG_START);
+		param[1] = FW_PARAM_PFVF(STAG_END);
+		param[2] = FW_PARAM_PFVF(RQ_START);
+		param[3] = FW_PARAM_PFVF(RQ_END);
+		param[4] = FW_PARAM_PFVF(PBL_START);
+		param[5] = FW_PARAM_PFVF(PBL_END);
+		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
 		if (rc != 0) {
 			device_printf(sc->dev,
-			    "failed to query RDMA parameters: %d.\n", rc);
-			goto done;
+			    "failed to query RDMA parameters(1): %d.\n", rc);
+			return (rc);
 		}
 		sc->vres.stag.start = val[0];
 		sc->vres.stag.size = val[1] - val[0] + 1;
@@ -1560,37 +1888,59 @@ get_params(struct adapter *sc, struct fw_caps_config_cmd *caps)
 		sc->vres.rq.size = val[3] - val[2] + 1;
 		sc->vres.pbl.start = val[4];
 		sc->vres.pbl.size = val[5] - val[4] + 1;
+
+		param[0] = FW_PARAM_PFVF(SQRQ_START);
+		param[1] = FW_PARAM_PFVF(SQRQ_END);
+		param[2] = FW_PARAM_PFVF(CQ_START);
+		param[3] = FW_PARAM_PFVF(CQ_END);
+		param[4] = FW_PARAM_PFVF(OCQ_START);
+		param[5] = FW_PARAM_PFVF(OCQ_END);
+		rc = -t4_query_params(sc, 0, 0, 0, 6, param, val);
+		if (rc != 0) {
+			device_printf(sc->dev,
+			    "failed to query RDMA parameters(2): %d.\n", rc);
+			return (rc);
+		}
+		sc->vres.qp.start = val[0];
+		sc->vres.qp.size = val[1] - val[0] + 1;
+		sc->vres.cq.start = val[2];
+		sc->vres.cq.size = val[3] - val[2] + 1;
+		sc->vres.ocq.start = val[4];
+		sc->vres.ocq.size = val[5] - val[4] + 1;
 	}
-	if (caps->iscsicaps) {
-		params[0] = FW_PARAM_PFVF(ISCSI_START);
-		params[1] = FW_PARAM_PFVF(ISCSI_END);
-		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, params, val);
+	if (caps.iscsicaps) {
+		param[0] = FW_PARAM_PFVF(ISCSI_START);
+		param[1] = FW_PARAM_PFVF(ISCSI_END);
+		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
 		if (rc != 0) {
 			device_printf(sc->dev,
 			    "failed to query iSCSI parameters: %d.\n", rc);
-			goto done;
+			return (rc);
 		}
 		sc->vres.iscsi.start = val[0];
 		sc->vres.iscsi.size = val[1] - val[0] + 1;
 	}
-#undef FW_PARAM_PFVF
-#undef FW_PARAM_DEV
 
-done:
+	/* These are finalized by FW initialization, load their values now */
+	val[0] = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
+	sc->params.tp.tre = G_TIMERRESOLUTION(val[0]);
+	sc->params.tp.dack_re = G_DELAYEDACKRESOLUTION(val[0]);
+	t4_read_mtu_tbl(sc, sc->params.mtus, NULL);
+
 	return (rc);
 }
 
+#undef FW_PARAM_PFVF
+#undef FW_PARAM_DEV
+
 static void
 t4_set_desc(struct adapter *sc)
 {
 	char buf[128];
 	struct adapter_params *p = &sc->params;
 
-	snprintf(buf, sizeof(buf),
-	    "Chelsio %s (rev %d) %d port %sNIC PCIe-x%d %d %s, S/N:%s, E/C:%s",
-	    p->vpd.id, p->rev, p->nports, is_offload(sc) ? "R" : "",
-	    p->pci.width, sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" :
-	    (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), p->vpd.sn, p->vpd.ec);
+	snprintf(buf, sizeof(buf), "Chelsio %s %sNIC (rev %d), S/N:%s, E/C:%s",
+	    p->vpd.id, is_offload(sc) ? "R" : "", p->rev, p->vpd.sn, p->vpd.ec);
 
 	device_set_desc_copy(sc->dev, buf);
 }
@@ -1807,9 +2157,7 @@ cxgbe_init_synchronized(struct port_info *pi)
 {
 	struct adapter *sc = pi->adapter;
 	struct ifnet *ifp = pi->ifp;
-	int rc = 0, i;
-	uint16_t *rss;
-	struct sge_rxq *rxq;
+	int rc = 0;
 
 	ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
 
@@ -1819,30 +2167,13 @@ cxgbe_init_synchronized(struct port_info *pi)
 		return (0);	/* already running */
 	}
 
-	if (sc->open_device_map == 0 && ((rc = first_port_up(sc)) != 0))
+	if (!(sc->flags & FULL_INIT_DONE) &&
+	    ((rc = adapter_full_init(sc)) != 0))
 		return (rc);	/* error message displayed already */
 
-	/*
-	 * Allocate tx/rx/fl queues for this port.
-	 */
-	rc = t4_setup_eth_queues(pi);
-	if (rc != 0)
-		goto done;	/* error message displayed already */
-
-	/*
-	 * Setup RSS for this port.
-	 */
-	rss = malloc(pi->nrxq * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK);
-	for_each_rxq(pi, i, rxq) {
-		rss[i] = rxq->iq.abs_id;
-	}
-	rc = -t4_config_rss_range(sc, sc->mbox, pi->viid, 0, pi->rss_size, rss,
-	    pi->nrxq);
-	free(rss, M_CXGBE);
-	if (rc != 0) {
-		if_printf(ifp, "rss_config failed: %d\n", rc);
-		goto done;
-	}
+	if (!(pi->flags & PORT_INIT_DONE) &&
+	    ((rc = port_full_init(pi)) != 0))
+		return (rc); /* error message displayed already */
 
 	PORT_LOCK(pi);
 	rc = update_mac_settings(pi, XGMAC_ALL);
@@ -1861,12 +2192,10 @@ cxgbe_init_synchronized(struct port_info *pi)
 		if_printf(ifp, "enable_vi failed: %d\n", rc);
 		goto done;
 	}
-	pi->flags |= VI_ENABLED;
 
 	/* all ok */
 	setbit(&sc->open_device_map, pi->port_id);
 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
-	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 
 	callout_reset(&pi->tick, hz, cxgbe_tick, pi);
 done:
@@ -1919,51 +2248,28 @@ cxgbe_uninit_synchronized(struct port_info *pi)
 	struct ifnet *ifp = pi->ifp;
 	int rc;
 
-	/*
-	 * taskqueue_drain may cause a deadlock if the adapter lock is held.
-	 */
 	ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
 
 	/*
-	 * Clear this port's bit from the open device map, and then drain
-	 * tasks and callouts.
-	 */
-	clrbit(&sc->open_device_map, pi->port_id);
-
-	PORT_LOCK(pi);
-	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
-	callout_stop(&pi->tick);
-	PORT_UNLOCK(pi);
-	callout_drain(&pi->tick);
-
-	/*
-	 * Stop and then free the queues' resources, including the queues
-	 * themselves.
-	 *
-	 * XXX: we could just stop the queues here (on ifconfig down) and free
-	 * them later (on port detach), but having up/down go through the entire
-	 * allocate/activate/deactivate/free sequence is a good way to find
-	 * leaks and bugs.
+	 * Disable the VI so that all its data in either direction is discarded
+	 * by the MPS.  Leave everything else (the queues, interrupts, and 1Hz
+	 * tick) intact as the TP can deliver negative advice or data that it's
+	 * holding in its RAM (for an offloaded connection) even after the VI is
+	 * disabled.
 	 */
-	rc = t4_teardown_eth_queues(pi);
-	if (rc != 0)
-		if_printf(ifp, "teardown failed: %d\n", rc);
-
-	if (pi->flags & VI_ENABLED) {
-		rc = -t4_enable_vi(sc, sc->mbox, pi->viid, false, false);
-		if (rc)
-			if_printf(ifp, "disable_vi failed: %d\n", rc);
-		else
-			pi->flags &= ~VI_ENABLED;
+	rc = -t4_enable_vi(sc, sc->mbox, pi->viid, false, false);
+	if (rc) {
+		if_printf(ifp, "disable_vi failed: %d\n", rc);
+		return (rc);
 	}
 
+	clrbit(&sc->open_device_map, pi->port_id);
+	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+
 	pi->link_cfg.link_ok = 0;
 	pi->link_cfg.speed = 0;
 	t4_os_link_changed(sc, pi->port_id, 0);
 
-	if (sc->open_device_map == 0)
-		last_port_down(sc);
-
 	return (0);
 }
 
@@ -1972,15 +2278,22 @@ cxgbe_uninit_synchronized(struct port_info *pi)
 	if (rc != 0) \
 		goto done; \
 } while (0)
+
 static int
-first_port_up(struct adapter *sc)
+adapter_full_init(struct adapter *sc)
 {
 	int rc, i, rid, p, q;
 	char s[8];
 	struct irq *irq;
-	struct sge_iq *intrq;
+	struct port_info *pi;
+	struct sge_rxq *rxq;
+#ifndef TCP_OFFLOAD_DISABLE
+	struct sge_ofld_rxq *ofld_rxq;
+#endif
 
 	ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
+	KASSERT((sc->flags & FULL_INIT_DONE) == 0,
+	    ("%s: FULL_INIT_DONE already", __func__));
 
 	/*
 	 * queues that belong to the adapter (not any particular port).
@@ -1989,95 +2302,265 @@ first_port_up(struct adapter *sc)
 	if (rc != 0)
 		goto done;
 
+	for (i = 0; i < ARRAY_SIZE(sc->tq); i++) {
+		sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
+		    taskqueue_thread_enqueue, &sc->tq[i]);
+		if (sc->tq[i] == NULL) {
+			device_printf(sc->dev,
+			    "failed to allocate task queue %d\n", i);
+			rc = ENOMEM;
+			goto done;
+		}
+		taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
+		    device_get_nameunit(sc->dev), i);
+	}
+
 	/*
 	 * Setup interrupts.
 	 */
 	irq = &sc->irq[0];
 	rid = sc->intr_type == INTR_INTX ? 0 : 1;
 	if (sc->intr_count == 1) {
-		KASSERT(sc->flags & INTR_SHARED,
-		    ("%s: single interrupt but not shared?", __func__));
+		KASSERT(!(sc->flags & INTR_DIRECT),
+		    ("%s: single interrupt && INTR_DIRECT?", __func__));
 
 		T4_ALLOC_IRQ(sc, irq, rid, t4_intr_all, sc, "all");
 	} else {
-		/* Multiple interrupts.  The first one is always error intr */
+		/* Multiple interrupts. */
+		KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
+		    ("%s: too few intr.", __func__));
+
+		/* The first one is always error intr */
 		T4_ALLOC_IRQ(sc, irq, rid, t4_intr_err, sc, "err");
 		irq++;
 		rid++;
 
-		/* Firmware event queue normally has an interrupt of its own */
-		if (sc->intr_count > T4_EXTRA_INTR) {
-			T4_ALLOC_IRQ(sc, irq, rid, t4_intr_evt, &sc->sge.fwq,
-			    "evt");
-			irq++;
-			rid++;
-		}
-
-		intrq = &sc->sge.intrq[0];
-		if (sc->flags & INTR_SHARED) {
+		/* The second one is always the firmware event queue */
+		T4_ALLOC_IRQ(sc, irq, rid, t4_intr_evt, &sc->sge.fwq, "evt");
+		irq++;
+		rid++;
 
-			/* All ports share these interrupt queues */
+		/*
+		 * Note that if INTR_DIRECT is not set then either the NIC rx
+		 * queues or (exclusive or) the TOE rx queueus will be taking
+		 * direct interrupts.
+		 *
+		 * There is no need to check for is_offload(sc) as nofldrxq
+		 * will be 0 if offload is disabled.
+		 */
+		for_each_port(sc, p) {
+			pi = sc->port[p];
 
-			for (i = 0; i < NINTRQ(sc); i++) {
-				snprintf(s, sizeof(s), "*.%d", i);
-				T4_ALLOC_IRQ(sc, irq, rid, t4_intr, intrq, s);
+#ifndef TCP_OFFLOAD_DISABLE
+			/*
+			 * Skip over the NIC queues if they aren't taking direct
+			 * interrupts.
+			 */
+			if (!(sc->flags & INTR_DIRECT) &&
+			    pi->nofldrxq > pi->nrxq)
+				goto ofld_queues;
+#endif
+			rxq = &sc->sge.rxq[pi->first_rxq];
+			for (q = 0; q < pi->nrxq; q++, rxq++) {
+				snprintf(s, sizeof(s), "%d.%d", p, q);
+				T4_ALLOC_IRQ(sc, irq, rid, t4_intr, rxq, s);
 				irq++;
 				rid++;
-				intrq++;
 			}
-		} else {
-
-			/* Each port has its own set of interrupt queues */
 
-			for (p = 0; p < sc->params.nports; p++) {
-				for (q = 0; q < sc->port[p]->nrxq; q++) {
-					snprintf(s, sizeof(s), "%d.%d", p, q);
-					T4_ALLOC_IRQ(sc, irq, rid, t4_intr,
-					    intrq, s);
-					irq++;
-					rid++;
-					intrq++;
-				}
+#ifndef TCP_OFFLOAD_DISABLE
+			/*
+			 * Skip over the offload queues if they aren't taking
+			 * direct interrupts.
+			 */
+			if (!(sc->flags & INTR_DIRECT))
+				continue;
+ofld_queues:
+			ofld_rxq = &sc->sge.ofld_rxq[pi->first_ofld_rxq];
+			for (q = 0; q < pi->nofldrxq; q++, ofld_rxq++) {
+				snprintf(s, sizeof(s), "%d,%d", p, q);
+				T4_ALLOC_IRQ(sc, irq, rid, t4_intr, ofld_rxq, s);
+				irq++;
+				rid++;
 			}
+#endif
 		}
 	}
 
 	t4_intr_enable(sc);
 	sc->flags |= FULL_INIT_DONE;
-
 done:
 	if (rc != 0)
-		last_port_down(sc);
+		adapter_full_uninit(sc);
 
 	return (rc);
 }
 #undef T4_ALLOC_IRQ
 
-/*
- * Idempotent.
- */
 static int
-last_port_down(struct adapter *sc)
+adapter_full_uninit(struct adapter *sc)
 {
 	int i;
 
 	ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
 
-	t4_intr_disable(sc);
-
 	t4_teardown_adapter_queues(sc);
 
 	for (i = 0; i < sc->intr_count; i++)
 		t4_free_irq(sc, &sc->irq[i]);
 
+	for (i = 0; i < ARRAY_SIZE(sc->tq) && sc->tq[i]; i++) {
+		taskqueue_free(sc->tq[i]);
+		sc->tq[i] = NULL;
+	}
+
 	sc->flags &= ~FULL_INIT_DONE;
 
 	return (0);
 }
 
 static int
+port_full_init(struct port_info *pi)
+{
+	struct adapter *sc = pi->adapter;
+	struct ifnet *ifp = pi->ifp;
+	uint16_t *rss;
+	struct sge_rxq *rxq;
+	int rc, i;
+
+	ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
+	KASSERT((pi->flags & PORT_INIT_DONE) == 0,
+	    ("%s: PORT_INIT_DONE already", __func__));
+
+	sysctl_ctx_init(&pi->ctx);
+	pi->flags |= PORT_SYSCTL_CTX;
+
+	/*
+	 * Allocate tx/rx/fl queues for this port.
+	 */
+	rc = t4_setup_port_queues(pi);
+	if (rc != 0)
+		goto done;	/* error message displayed already */
+
+	/*
+	 * Setup RSS for this port.
+	 */
+	rss = malloc(pi->nrxq * sizeof (*rss), M_CXGBE,
+	    M_ZERO | M_WAITOK);
+	for_each_rxq(pi, i, rxq) {
+		rss[i] = rxq->iq.abs_id;
+	}
+	rc = -t4_config_rss_range(sc, sc->mbox, pi->viid, 0,
+	    pi->rss_size, rss, pi->nrxq);
+	free(rss, M_CXGBE);
+	if (rc != 0) {
+		if_printf(ifp, "rss_config failed: %d\n", rc);
+		goto done;
+	}
+
+	pi->flags |= PORT_INIT_DONE;
+done:
+	if (rc != 0)
+		port_full_uninit(pi);
+
+	return (rc);
+}
+
+/*
+ * Idempotent.
+ */
+static int
+port_full_uninit(struct port_info *pi)
+{
+	struct adapter *sc = pi->adapter;
+	int i;
+	struct sge_rxq *rxq;
+	struct sge_txq *txq;
+#ifndef TCP_OFFLOAD_DISABLE
+	struct sge_ofld_rxq *ofld_rxq;
+	struct sge_wrq *ofld_txq;
+#endif
+
+	if (pi->flags & PORT_INIT_DONE) {
+
+		/* Need to quiesce queues.  XXX: ctrl queues? */
+
+		for_each_txq(pi, i, txq) {
+			quiesce_eq(sc, &txq->eq);
+		}
+
+#ifndef TCP_OFFLOAD_DISABLE
+		for_each_ofld_txq(pi, i, ofld_txq) {
+			quiesce_eq(sc, &ofld_txq->eq);
+		}
+#endif
+
+		for_each_rxq(pi, i, rxq) {
+			quiesce_iq(sc, &rxq->iq);
+			quiesce_fl(sc, &rxq->fl);
+		}
+
+#ifndef TCP_OFFLOAD_DISABLE
+		for_each_ofld_rxq(pi, i, ofld_rxq) {
+			quiesce_iq(sc, &ofld_rxq->iq);
+			quiesce_fl(sc, &ofld_rxq->fl);
+		}
+#endif
+	}
+
+	t4_teardown_port_queues(pi);
+	pi->flags &= ~PORT_INIT_DONE;
+
+	return (0);
+}
+
+static void
+quiesce_eq(struct adapter *sc, struct sge_eq *eq)
+{
+	EQ_LOCK(eq);
+	eq->flags |= EQ_DOOMED;
+
+	/*
+	 * Wait for the response to a credit flush if one's
+	 * pending.
+	 */
+	while (eq->flags & EQ_CRFLUSHED)
+		mtx_sleep(eq, &eq->eq_lock, 0, "crflush", 0);
+	EQ_UNLOCK(eq);
+
+	callout_drain(&eq->tx_callout);	/* XXX: iffy */
+	pause("callout", 10);		/* Still iffy */
+
+	taskqueue_drain(sc->tq[eq->tx_chan], &eq->tx_task);
+}
+
+static void
+quiesce_iq(struct adapter *sc, struct sge_iq *iq)
+{
+	(void) sc;	/* unused */
+
+	/* Synchronize with the interrupt handler */
+	while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
+		pause("iqfree", 1);
+}
+
+static void
+quiesce_fl(struct adapter *sc, struct sge_fl *fl)
+{
+	mtx_lock(&sc->sfl_lock);
+	FL_LOCK(fl);
+	fl->flags |= FL_DOOMED;
+	FL_UNLOCK(fl);
+	mtx_unlock(&sc->sfl_lock);
+
+	callout_drain(&sc->sfl_callout);
+	KASSERT((fl->flags & FL_STARVING) == 0,
+	    ("%s: still starving", __func__));
+}
+
+static int
 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
-    iq_intr_handler_t *handler, void *arg, char *name)
+    driver_intr_t *handler, void *arg, char *name)
 {
 	int rc;
 
@@ -2369,12 +2852,12 @@ cxgbe_tick(void *arg)
 
 	t4_get_port_stats(pi->adapter, pi->tx_chan, s);
 
-	ifp->if_opackets = s->tx_frames;
-	ifp->if_ipackets = s->rx_frames;
-	ifp->if_obytes = s->tx_octets;
-	ifp->if_ibytes = s->rx_octets;
-	ifp->if_omcasts = s->tx_mcast_frames;
-	ifp->if_imcasts = s->rx_mcast_frames;
+	ifp->if_opackets = s->tx_frames - s->tx_pause;
+	ifp->if_ipackets = s->rx_frames - s->rx_pause;
+	ifp->if_obytes = s->tx_octets - s->tx_pause * 64;
+	ifp->if_ibytes = s->rx_octets - s->rx_pause * 64;
+	ifp->if_omcasts = s->tx_mcast_frames - s->tx_pause;
+	ifp->if_imcasts = s->rx_mcast_frames - s->rx_pause;
 	ifp->if_iqdrops = s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
 	    s->rx_ovflow3;
 
@@ -2392,15 +2875,58 @@ cxgbe_tick(void *arg)
 }
 
 static int
+cpl_not_handled(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
+{
+#ifdef INVARIANTS
+	panic("%s: opcode %02x on iq %p with payload %p",
+	    __func__, rss->opcode, iq, m);
+#else
+	log(LOG_ERR, "%s: opcode %02x on iq %p with payload %p",
+	    __func__, rss->opcode, iq, m);
+	m_freem(m);
+#endif
+	return (EDOOFUS);
+}
+
+int
+t4_register_cpl_handler(struct adapter *sc, int opcode, cpl_handler_t h)
+{
+	uintptr_t *loc, new;
+
+	if (opcode >= ARRAY_SIZE(sc->cpl_handler))
+		return (EINVAL);
+
+	new = h ? (uintptr_t)h : (uintptr_t)cpl_not_handled;
+	loc = (uintptr_t *) &sc->cpl_handler[opcode];
+	atomic_store_rel_ptr(loc, new);
+
+	return (0);
+}
+
+static int
 t4_sysctls(struct adapter *sc)
 {
 	struct sysctl_ctx_list *ctx;
 	struct sysctl_oid *oid;
-	struct sysctl_oid_list *children;
+	struct sysctl_oid_list *children, *c0;
+	static char *caps[] = {
+		"\20\1PPP\2QFC\3DCBX",			/* caps[0] linkcaps */
+		"\20\1NIC\2VM\3IDS\4UM\5UM_ISGL",	/* caps[1] niccaps */
+		"\20\1TOE",				/* caps[2] toecaps */
+		"\20\1RDDP\2RDMAC",			/* caps[3] rdmacaps */
+		"\20\1INITIATOR_PDU\2TARGET_PDU"	/* caps[4] iscsicaps */
+		    "\3INITIATOR_CNXOFLD\4TARGET_CNXOFLD"
+		    "\5INITIATOR_SSNOFLD\6TARGET_SSNOFLD",
+		"\20\1INITIATOR\2TARGET\3CTRL_OFLD"	/* caps[5] fcoecaps */
+	};
 
 	ctx = device_get_sysctl_ctx(sc->dev);
+
+	/*
+	 * dev.t4nex.X.
+	 */
 	oid = device_get_sysctl_tree(sc->dev);
-	children = SYSCTL_CHILDREN(oid);
+	c0 = children = SYSCTL_CHILDREN(oid);
 
 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD,
 	    &sc->params.nports, 0, "# of ports");
@@ -2411,23 +2937,146 @@ t4_sysctls(struct adapter *sc)
 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
 	    CTLFLAG_RD, &sc->fw_version, 0, "firmware version");
 
-	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "TOE", CTLFLAG_RD,
-	    &sc->params.offload, 0, "hardware is capable of TCP offload");
+	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
+	    CTLFLAG_RD, &t4_cfg_file, 0, "configuration file");
+
+	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD,
+	    &sc->cfcsum, 0, "config file checksum");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkcaps",
+	    CTLTYPE_STRING | CTLFLAG_RD, caps[0], sc->linkcaps,
+	    sysctl_bitfield, "A", "available link capabilities");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "niccaps",
+	    CTLTYPE_STRING | CTLFLAG_RD, caps[1], sc->niccaps,
+	    sysctl_bitfield, "A", "available NIC capabilities");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "toecaps",
+	    CTLTYPE_STRING | CTLFLAG_RD, caps[2], sc->toecaps,
+	    sysctl_bitfield, "A", "available TCP offload capabilities");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdmacaps",
+	    CTLTYPE_STRING | CTLFLAG_RD, caps[3], sc->rdmacaps,
+	    sysctl_bitfield, "A", "available RDMA capabilities");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "iscsicaps",
+	    CTLTYPE_STRING | CTLFLAG_RD, caps[4], sc->iscsicaps,
+	    sysctl_bitfield, "A", "available iSCSI capabilities");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoecaps",
+	    CTLTYPE_STRING | CTLFLAG_RD, caps[5], sc->fcoecaps,
+	    sysctl_bitfield, "A", "available FCoE capabilities");
 
 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD,
 	    &sc->params.vpd.cclk, 0, "core clock frequency (in KHz)");
 
 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
-	    CTLTYPE_STRING | CTLFLAG_RD, &intr_timer, sizeof(intr_timer),
-	    sysctl_int_array, "A", "interrupt holdoff timer values (us)");
+	    CTLTYPE_STRING | CTLFLAG_RD, sc->sge.timer_val,
+	    sizeof(sc->sge.timer_val), sysctl_int_array, "A",
+	    "interrupt holdoff timer values (us)");
 
 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
-	    CTLTYPE_STRING | CTLFLAG_RD, &intr_pktcount, sizeof(intr_pktcount),
-	    sysctl_int_array, "A", "interrupt holdoff packet counter values");
+	    CTLTYPE_STRING | CTLFLAG_RD, sc->sge.counter_val,
+	    sizeof(sc->sge.counter_val), sysctl_int_array, "A",
+	    "interrupt holdoff packet counter values");
+
+	/*
+	 * dev.t4nex.X.misc.  Marked CTLFLAG_SKIP to avoid information overload.
+	 */
+	oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
+	    CTLFLAG_RD | CTLFLAG_SKIP, NULL,
+	    "logs and miscellaneous information");
+	children = SYSCTL_CHILDREN(oid);
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
+	    CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
+	    sysctl_cctrl, "A", "congestion control");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
+	    CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
+	    sysctl_cpl_stats, "A", "CPL statistics");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
+	    CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
+	    sysctl_ddp_stats, "A", "DDP statistics");
 
 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
 	    CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
-	    sysctl_devlog, "A", "device log");
+	    sysctl_devlog, "A", "firmware's device log");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
+	    CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
+	    sysctl_fcoe_stats, "A", "FCoE statistics");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
+	    CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
+	    sysctl_hw_sched, "A", "hardware scheduler ");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
+	    CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
+	    sysctl_l2t, "A", "hardware L2 table");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
+	    CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
+	    sysctl_lb_stats, "A", "loopback statistics");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
+	    CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
+	    sysctl_meminfo, "A", "memory regions");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
+	    CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
+	    sysctl_path_mtus, "A", "path MTUs");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
+	    CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
+	    sysctl_pm_stats, "A", "PM statistics");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
+	    CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
+	    sysctl_rdma_stats, "A", "RDMA statistics");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
+	    CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
+	    sysctl_tcp_stats, "A", "TCP statistics");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
+	    CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
+	    sysctl_tids, "A", "TID information");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
+	    CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
+	    sysctl_tp_err_stats, "A", "TP error statistics");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
+	    CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
+	    sysctl_tx_rate, "A", "Tx rate");
+
+#ifndef TCP_OFFLOAD_DISABLE
+	if (is_offload(sc)) {
+		/*
+		 * dev.t4nex.X.toe.
+		 */
+		oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD,
+		    NULL, "TOE parameters");
+		children = SYSCTL_CHILDREN(oid);
+
+		sc->tt.sndbuf = 256 * 1024;
+		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
+		    &sc->tt.sndbuf, 0, "max hardware send buffer size");
+
+		sc->tt.ddp = 0;
+		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW,
+		    &sc->tt.ddp, 0, "DDP allowed");
+		sc->tt.indsz = M_INDICATESIZE;
+		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "indsz", CTLFLAG_RW,
+		    &sc->tt.indsz, 0, "DDP max indicate size allowed");
+		sc->tt.ddp_thres = 3*4096;
+		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp_thres", CTLFLAG_RW,
+		    &sc->tt.ddp_thres, 0, "DDP threshold");
+	}
+#endif
+
 
 	return (0);
 }
@@ -2456,6 +3105,23 @@ cxgbe_sysctls(struct port_info *pi)
 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
 	    &pi->first_txq, 0, "index of first tx queue");
 
+#ifndef TCP_OFFLOAD_DISABLE
+	if (is_offload(pi->adapter)) {
+		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
+		    &pi->nofldrxq, 0,
+		    "# of rx queues for offloaded TCP connections");
+		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
+		    &pi->nofldtxq, 0,
+		    "# of tx queues for offloaded TCP connections");
+		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
+		    CTLFLAG_RD, &pi->first_ofld_rxq, 0,
+		    "index of first TOE rx queue");
+		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
+		    CTLFLAG_RD, &pi->first_ofld_txq, 0,
+		    "index of first TOE tx queue");
+	}
+#endif
+
 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
 	    CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_holdoff_tmr_idx, "I",
 	    "holdoff timer index");
@@ -2646,11 +3312,31 @@ sysctl_int_array(SYSCTL_HANDLER_ARGS)
 }
 
 static int
+sysctl_bitfield(SYSCTL_HANDLER_ARGS)
+{
+	int rc;
+	struct sbuf *sb;
+
+	rc = sysctl_wire_old_buffer(req, 0);
+	if (rc != 0)
+		return(rc);
+
+	sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
+	if (sb == NULL)
+		return (ENOMEM);
+
+	sbuf_printf(sb, "%b", (int)arg2, (char *)arg1);
+	rc = sbuf_finish(sb);
+	sbuf_delete(sb);
+
+	return (rc);
+}
+
+static int
 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
 {
 	struct port_info *pi = arg1;
 	struct adapter *sc = pi->adapter;
-	struct sge_rxq *rxq;
 	int idx, rc, i;
 
 	idx = pi->tmr_idx;
@@ -2665,9 +3351,16 @@ sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
 	ADAPTER_LOCK(sc);
 	rc = IS_DOOMED(pi) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0);
 	if (rc == 0) {
+		struct sge_rxq *rxq;
+		uint8_t v;
+
+		v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(pi->pktc_idx != -1);
 		for_each_rxq(pi, i, rxq) {
-			rxq->iq.intr_params = V_QINTR_TIMER_IDX(idx) |
-			    V_QINTR_CNT_EN(pi->pktc_idx != -1);
+#ifdef atomic_store_rel_8
+			atomic_store_rel_8(&rxq->iq.intr_params, v);
+#else
+			rxq->iq.intr_params = v;
+#endif
 		}
 		pi->tmr_idx = idx;
 	}
@@ -2694,8 +3387,8 @@ sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
 
 	ADAPTER_LOCK(sc);
 	rc = IS_DOOMED(pi) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0);
-	if (rc == 0 && pi->ifp->if_drv_flags & IFF_DRV_RUNNING)
-		rc = EBUSY; /* can be changed only when port is down */
+	if (rc == 0 && pi->flags & PORT_INIT_DONE)
+		rc = EBUSY; /* cannot be changed once the queues are created */
 
 	if (rc == 0)
 		pi->pktc_idx = idx;
@@ -2722,8 +3415,8 @@ sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
 
 	ADAPTER_LOCK(sc);
 	rc = IS_DOOMED(pi) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0);
-	if (rc == 0 && pi->ifp->if_drv_flags & IFF_DRV_RUNNING)
-		rc = EBUSY; /* can be changed only when port is down */
+	if (rc == 0 && pi->flags & PORT_INIT_DONE)
+		rc = EBUSY; /* cannot be changed once the queues are created */
 
 	if (rc == 0)
 		pi->qsize_rxq = qsize;
@@ -2750,8 +3443,8 @@ sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
 
 	ADAPTER_LOCK(sc);
 	rc = IS_DOOMED(pi) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0);
-	if (rc == 0 && pi->ifp->if_drv_flags & IFF_DRV_RUNNING)
-		rc = EBUSY; /* can be changed only when port is down */
+	if (rc == 0 && pi->flags & PORT_INIT_DONE)
+		rc = EBUSY; /* cannot be changed once the queues are created */
 
 	if (rc == 0)
 		pi->qsize_txq = qsize;
@@ -2772,6 +3465,103 @@ sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
 	return (sysctl_handle_64(oidp, &val, 0, req));
 }
 
+static int
+sysctl_cctrl(SYSCTL_HANDLER_ARGS)
+{
+	struct adapter *sc = arg1;
+	struct sbuf *sb;
+	int rc, i;
+	uint16_t incr[NMTUS][NCCTRL_WIN];
+	static const char *dec_fac[] = {
+		"0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
+		"0.9375"
+	};
+
+	rc = sysctl_wire_old_buffer(req, 0);
+	if (rc != 0)
+		return (rc);
+
+	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
+	if (sb == NULL)
+		return (ENOMEM);
+
+	t4_read_cong_tbl(sc, incr);
+
+	for (i = 0; i < NCCTRL_WIN; ++i) {
+		sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
+		    incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
+		    incr[5][i], incr[6][i], incr[7][i]);
+		sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
+		    incr[8][i], incr[9][i], incr[10][i], incr[11][i],
+		    incr[12][i], incr[13][i], incr[14][i], incr[15][i],
+		    sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
+	}
+
+	rc = sbuf_finish(sb);
+	sbuf_delete(sb);
+
+	return (rc);
+}
+
+static int
+sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
+{
+	struct adapter *sc = arg1;
+	struct sbuf *sb;
+	int rc;
+	struct tp_cpl_stats stats;
+
+	rc = sysctl_wire_old_buffer(req, 0);
+	if (rc != 0)
+		return (rc);
+
+	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
+	if (sb == NULL)
+		return (ENOMEM);
+
+	t4_tp_get_cpl_stats(sc, &stats);
+
+	sbuf_printf(sb, "                 channel 0  channel 1  channel 2  "
+	    "channel 3\n");
+	sbuf_printf(sb, "CPL requests:   %10u %10u %10u %10u\n",
+		   stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
+	sbuf_printf(sb, "CPL responses:  %10u %10u %10u %10u",
+		   stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
+
+	rc = sbuf_finish(sb);
+	sbuf_delete(sb);
+
+	return (rc);
+}
+
+static int
+sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
+{
+	struct adapter *sc = arg1;
+	struct sbuf *sb;
+	int rc;
+	struct tp_usm_stats stats;
+
+	rc = sysctl_wire_old_buffer(req, 0);
+	if (rc != 0)
+		return(rc);
+
+	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
+	if (sb == NULL)
+		return (ENOMEM);
+
+	t4_get_usm_stats(sc, &stats);
+
+	sbuf_printf(sb, "Frames: %u\n", stats.frames);
+	sbuf_printf(sb, "Octets: %ju\n", stats.octets);
+	sbuf_printf(sb, "Drops:  %u", stats.drops);
+
+	rc = sbuf_finish(sb);
+	sbuf_delete(sb);
+
+	return (rc);
+}
+
 const char *devlog_level_strings[] = {
 	[FW_DEVLOG_LEVEL_EMERG]		= "EMERG",
 	[FW_DEVLOG_LEVEL_CRIT]		= "CRIT",
@@ -2856,7 +3646,11 @@ sysctl_devlog(SYSCTL_HANDLER_ARGS)
 		goto done;
 
 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
-	sbuf_printf(sb, "\n%10s  %15s  %8s  %8s  %s\n",
+	if (sb == NULL) {
+		rc = ENOMEM;
+		goto done;
+	}
+	sbuf_printf(sb, "%10s  %15s  %8s  %8s  %s\n",
 	    "Seq#", "Tstamp", "Level", "Facility", "Message");
 
 	i = first;
@@ -2886,6 +3680,624 @@ done:
 	return (rc);
 }
 
+static int
+sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
+{
+	struct adapter *sc = arg1;
+	struct sbuf *sb;
+	int rc;
+	struct tp_fcoe_stats stats[4];
+
+	rc = sysctl_wire_old_buffer(req, 0);
+	if (rc != 0)
+		return (rc);
+
+	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
+	if (sb == NULL)
+		return (ENOMEM);
+
+	t4_get_fcoe_stats(sc, 0, &stats[0]);
+	t4_get_fcoe_stats(sc, 1, &stats[1]);
+	t4_get_fcoe_stats(sc, 2, &stats[2]);
+	t4_get_fcoe_stats(sc, 3, &stats[3]);
+
+	sbuf_printf(sb, "                   channel 0        channel 1        "
+	    "channel 2        channel 3\n");
+	sbuf_printf(sb, "octetsDDP:  %16ju %16ju %16ju %16ju\n",
+	    stats[0].octetsDDP, stats[1].octetsDDP, stats[2].octetsDDP,
+	    stats[3].octetsDDP);
+	sbuf_printf(sb, "framesDDP:  %16u %16u %16u %16u\n", stats[0].framesDDP,
+	    stats[1].framesDDP, stats[2].framesDDP, stats[3].framesDDP);
+	sbuf_printf(sb, "framesDrop: %16u %16u %16u %16u",
+	    stats[0].framesDrop, stats[1].framesDrop, stats[2].framesDrop,
+	    stats[3].framesDrop);
+
+	rc = sbuf_finish(sb);
+	sbuf_delete(sb);
+
+	return (rc);
+}
+
+static int
+sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
+{
+	struct adapter *sc = arg1;
+	struct sbuf *sb;
+	int rc, i;
+	unsigned int map, kbps, ipg, mode;
+	unsigned int pace_tab[NTX_SCHED];
+
+	rc = sysctl_wire_old_buffer(req, 0);
+	if (rc != 0)
+		return (rc);
+
+	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
+	if (sb == NULL)
+		return (ENOMEM);
+
+	map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
+	mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
+	t4_read_pace_tbl(sc, pace_tab);
+
+	sbuf_printf(sb, "Scheduler  Mode   Channel  Rate (Kbps)   "
+	    "Class IPG (0.1 ns)   Flow IPG (us)");
+
+	for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
+		t4_get_tx_sched(sc, i, &kbps, &ipg);
+		sbuf_printf(sb, "\n    %u      %-5s     %u     ", i,
+		    (mode & (1 << i)) ? "flow" : "class", map & 3);
+		if (kbps)
+			sbuf_printf(sb, "%9u     ", kbps);
+		else
+			sbuf_printf(sb, " disabled     ");
+
+		if (ipg)
+			sbuf_printf(sb, "%13u        ", ipg);
+		else
+			sbuf_printf(sb, "     disabled        ");
+
+		if (pace_tab[i])
+			sbuf_printf(sb, "%10u", pace_tab[i]);
+		else
+			sbuf_printf(sb, "  disabled");
+	}
+
+	rc = sbuf_finish(sb);
+	sbuf_delete(sb);
+
+	return (rc);
+}
+
+static int
+sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
+{
+	struct adapter *sc = arg1;
+	struct sbuf *sb;
+	int rc, i, j;
+	uint64_t *p0, *p1;
+	struct lb_port_stats s[2];
+	static const char *stat_name[] = {
+		"OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
+		"UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
+		"Frames128To255:", "Frames256To511:", "Frames512To1023:",
+		"Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
+		"BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
+		"BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
+		"BG2FramesTrunc:", "BG3FramesTrunc:"
+	};
+
+	rc = sysctl_wire_old_buffer(req, 0);
+	if (rc != 0)
+		return (rc);
+
+	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
+	if (sb == NULL)
+		return (ENOMEM);
+
+	memset(s, 0, sizeof(s));
+
+	for (i = 0; i < 4; i += 2) {
+		t4_get_lb_stats(sc, i, &s[0]);
+		t4_get_lb_stats(sc, i + 1, &s[1]);
+
+		p0 = &s[0].octets;
+		p1 = &s[1].octets;
+		sbuf_printf(sb, "%s                       Loopback %u"
+		    "           Loopback %u", i == 0 ? "" : "\n", i, i + 1);
+
+		for (j = 0; j < ARRAY_SIZE(stat_name); j++)
+			sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
+				   *p0++, *p1++);
+	}
+
+	rc = sbuf_finish(sb);
+	sbuf_delete(sb);
+
+	return (rc);
+}
+
+struct mem_desc {
+	unsigned int base;
+	unsigned int limit;
+	unsigned int idx;
+};
+
+static int
+mem_desc_cmp(const void *a, const void *b)
+{
+	return ((const struct mem_desc *)a)->base -
+	       ((const struct mem_desc *)b)->base;
+}
+
+static void
+mem_region_show(struct sbuf *sb, const char *name, unsigned int from,
+    unsigned int to)
+{
+	unsigned int size;
+
+	size = to - from + 1;
+	if (size == 0)
+		return;
+
+	/* XXX: need humanize_number(3) in libkern for a more readable 'size' */
+	sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size);
+}
+
+static int
+sysctl_meminfo(SYSCTL_HANDLER_ARGS)
+{
+	struct adapter *sc = arg1;
+	struct sbuf *sb;
+	int rc, i, n;
+	uint32_t lo, hi;
+	static const char *memory[] = { "EDC0:", "EDC1:", "MC:" };
+	static const char *region[] = {
+		"DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
+		"Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
+		"Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
+		"TDDP region:", "TPT region:", "STAG region:", "RQ region:",
+		"RQUDP region:", "PBL region:", "TXPBL region:", "ULPRX state:",
+		"ULPTX state:", "On-chip queues:"
+	};
+	struct mem_desc avail[3];
+	struct mem_desc mem[ARRAY_SIZE(region) + 3];	/* up to 3 holes */
+	struct mem_desc *md = mem;
+
+	rc = sysctl_wire_old_buffer(req, 0);
+	if (rc != 0)
+		return (rc);
+
+	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
+	if (sb == NULL)
+		return (ENOMEM);
+
+	for (i = 0; i < ARRAY_SIZE(mem); i++) {
+		mem[i].limit = 0;
+		mem[i].idx = i;
+	}
+
+	/* Find and sort the populated memory ranges */
+	i = 0;
+	lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
+	if (lo & F_EDRAM0_ENABLE) {
+		hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
+		avail[i].base = G_EDRAM0_BASE(hi) << 20;
+		avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20);
+		avail[i].idx = 0;
+		i++;
+	}
+	if (lo & F_EDRAM1_ENABLE) {
+		hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
+		avail[i].base = G_EDRAM1_BASE(hi) << 20;
+		avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20);
+		avail[i].idx = 1;
+		i++;
+	}
+	if (lo & F_EXT_MEM_ENABLE) {
+		hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
+		avail[i].base = G_EXT_MEM_BASE(hi) << 20;
+		avail[i].limit = avail[i].base + (G_EXT_MEM_SIZE(hi) << 20);
+		avail[i].idx = 2;
+		i++;
+	}
+	if (!i)                                    /* no memory available */
+		return 0;
+	qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
+
+	(md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
+	(md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
+	(md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
+	(md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
+	(md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
+	(md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
+	(md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
+	(md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
+	(md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
+
+	/* the next few have explicit upper bounds */
+	md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
+	md->limit = md->base - 1 +
+		    t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
+		    G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
+	md++;
+
+	md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
+	md->limit = md->base - 1 +
+		    t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
+		    G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
+	md++;
+
+	if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
+		hi = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4;
+		md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
+		md->limit = (sc->tids.ntids - hi) * 16 + md->base - 1;
+	} else {
+		md->base = 0;
+		md->idx = ARRAY_SIZE(region);  /* hide it */
+	}
+	md++;
+
+#define ulp_region(reg) \
+	md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\
+	(md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT)
+
+	ulp_region(RX_ISCSI);
+	ulp_region(RX_TDDP);
+	ulp_region(TX_TPT);
+	ulp_region(RX_STAG);
+	ulp_region(RX_RQ);
+	ulp_region(RX_RQUDP);
+	ulp_region(RX_PBL);
+	ulp_region(TX_PBL);
+#undef ulp_region
+
+	md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
+	md->limit = md->base + sc->tids.ntids - 1;
+	md++;
+	md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
+	md->limit = md->base + sc->tids.ntids - 1;
+	md++;
+
+	md->base = sc->vres.ocq.start;
+	if (sc->vres.ocq.size)
+		md->limit = md->base + sc->vres.ocq.size - 1;
+	else
+		md->idx = ARRAY_SIZE(region);  /* hide it */
+	md++;
+
+	/* add any address-space holes, there can be up to 3 */
+	for (n = 0; n < i - 1; n++)
+		if (avail[n].limit < avail[n + 1].base)
+			(md++)->base = avail[n].limit;
+	if (avail[n].limit)
+		(md++)->base = avail[n].limit;
+
+	n = md - mem;
+	qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
+
+	for (lo = 0; lo < i; lo++)
+		mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
+				avail[lo].limit - 1);
+
+	sbuf_printf(sb, "\n");
+	for (i = 0; i < n; i++) {
+		if (mem[i].idx >= ARRAY_SIZE(region))
+			continue;                        /* skip holes */
+		if (!mem[i].limit)
+			mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
+		mem_region_show(sb, region[mem[i].idx], mem[i].base,
+				mem[i].limit);
+	}
+
+	sbuf_printf(sb, "\n");
+	lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
+	hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
+	mem_region_show(sb, "uP RAM:", lo, hi);
+
+	lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
+	hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
+	mem_region_show(sb, "uP Extmem2:", lo, hi);
+
+	lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
+	sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n",
+		   G_PMRXMAXPAGE(lo),
+		   t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10,
+		   (lo & F_PMRXNUMCHN) ? 2 : 1);
+
+	lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
+	hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
+	sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n",
+		   G_PMTXMAXPAGE(lo),
+		   hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
+		   hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo));
+	sbuf_printf(sb, "%u p-structs\n",
+		   t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT));
+
+	for (i = 0; i < 4; i++) {
+		lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
+		sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
+			   i, G_USED(lo), G_ALLOC(lo));
+	}
+	for (i = 0; i < 4; i++) {
+		lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
+		sbuf_printf(sb,
+			   "\nLoopback %d using %u pages out of %u allocated",
+			   i, G_USED(lo), G_ALLOC(lo));
+	}
+
+	rc = sbuf_finish(sb);
+	sbuf_delete(sb);
+
+	return (rc);
+}
+
+static int
+sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
+{
+	struct adapter *sc = arg1;
+	struct sbuf *sb;
+	int rc;
+	uint16_t mtus[NMTUS];
+
+	rc = sysctl_wire_old_buffer(req, 0);
+	if (rc != 0)
+		return (rc);
+
+	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
+	if (sb == NULL)
+		return (ENOMEM);
+
+	t4_read_mtu_tbl(sc, mtus, NULL);
+
+	sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
+	    mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
+	    mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
+	    mtus[14], mtus[15]);
+
+	rc = sbuf_finish(sb);
+	sbuf_delete(sb);
+
+	return (rc);
+}
+
+static int
+sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
+{
+	struct adapter *sc = arg1;
+	struct sbuf *sb;
+	int rc, i;
+	uint32_t tx_cnt[PM_NSTATS], rx_cnt[PM_NSTATS];
+	uint64_t tx_cyc[PM_NSTATS], rx_cyc[PM_NSTATS];
+	static const char *pm_stats[] = {
+		"Read:", "Write bypass:", "Write mem:", "Flush:", "FIFO wait:"
+	};
+
+	rc = sysctl_wire_old_buffer(req, 0);
+	if (rc != 0)
+		return (rc);
+
+	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
+	if (sb == NULL)
+		return (ENOMEM);
+
+	t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
+	t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
+
+	sbuf_printf(sb, "                Tx count            Tx cycles    "
+	    "Rx count            Rx cycles");
+	for (i = 0; i < PM_NSTATS; i++)
+		sbuf_printf(sb, "\n%-13s %10u %20ju  %10u %20ju",
+		    pm_stats[i], tx_cnt[i], tx_cyc[i], rx_cnt[i], rx_cyc[i]);
+
+	rc = sbuf_finish(sb);
+	sbuf_delete(sb);
+
+	return (rc);
+}
+
+static int
+sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
+{
+	struct adapter *sc = arg1;
+	struct sbuf *sb;
+	int rc;
+	struct tp_rdma_stats stats;
+
+	rc = sysctl_wire_old_buffer(req, 0);
+	if (rc != 0)
+		return (rc);
+
+	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
+	if (sb == NULL)
+		return (ENOMEM);
+
+	t4_tp_get_rdma_stats(sc, &stats);
+	sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
+	sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
+
+	rc = sbuf_finish(sb);
+	sbuf_delete(sb);
+
+	return (rc);
+}
+
+static int
+sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
+{
+	struct adapter *sc = arg1;
+	struct sbuf *sb;
+	int rc;
+	struct tp_tcp_stats v4, v6;
+
+	rc = sysctl_wire_old_buffer(req, 0);
+	if (rc != 0)
+		return (rc);
+
+	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
+	if (sb == NULL)
+		return (ENOMEM);
+
+	t4_tp_get_tcp_stats(sc, &v4, &v6);
+	sbuf_printf(sb,
+	    "                                IP                 IPv6\n");
+	sbuf_printf(sb, "OutRsts:      %20u %20u\n",
+	    v4.tcpOutRsts, v6.tcpOutRsts);
+	sbuf_printf(sb, "InSegs:       %20ju %20ju\n",
+	    v4.tcpInSegs, v6.tcpInSegs);
+	sbuf_printf(sb, "OutSegs:      %20ju %20ju\n",
+	    v4.tcpOutSegs, v6.tcpOutSegs);
+	sbuf_printf(sb, "RetransSegs:  %20ju %20ju",
+	    v4.tcpRetransSegs, v6.tcpRetransSegs);
+
+	rc = sbuf_finish(sb);
+	sbuf_delete(sb);
+
+	return (rc);
+}
+
+static int
+sysctl_tids(SYSCTL_HANDLER_ARGS)
+{
+	struct adapter *sc = arg1;
+	struct sbuf *sb;
+	int rc;
+	struct tid_info *t = &sc->tids;
+
+	rc = sysctl_wire_old_buffer(req, 0);
+	if (rc != 0)
+		return (rc);
+
+	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
+	if (sb == NULL)
+		return (ENOMEM);
+
+	if (t->natids) {
+		sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
+		    t->atids_in_use);
+	}
+
+	if (t->ntids) {
+		if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
+			uint32_t b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
+
+			if (b) {
+				sbuf_printf(sb, "TID range: 0-%u, %u-%u", b - 1,
+				    t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4,
+				    t->ntids - 1);
+			} else {
+				sbuf_printf(sb, "TID range: %u-%u",
+				    t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4,
+				    t->ntids - 1);
+			}
+		} else
+			sbuf_printf(sb, "TID range: 0-%u", t->ntids - 1);
+		sbuf_printf(sb, ", in use: %u\n",
+		    atomic_load_acq_int(&t->tids_in_use));
+	}
+
+	if (t->nstids) {
+		sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
+		    t->stid_base + t->nstids - 1, t->stids_in_use);
+	}
+
+	if (t->nftids) {
+		sbuf_printf(sb, "FTID range: %u-%u\n", t->ftid_base,
+		    t->ftid_base + t->nftids - 1);
+	}
+
+	sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users",
+	    t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4),
+	    t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6));
+
+	rc = sbuf_finish(sb);
+	sbuf_delete(sb);
+
+	return (rc);
+}
+
+static int
+sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
+{
+	struct adapter *sc = arg1;
+	struct sbuf *sb;
+	int rc;
+	struct tp_err_stats stats;
+
+	rc = sysctl_wire_old_buffer(req, 0);
+	if (rc != 0)
+		return (rc);
+
+	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
+	if (sb == NULL)
+		return (ENOMEM);
+
+	t4_tp_get_err_stats(sc, &stats);
+
+	sbuf_printf(sb, "                 channel 0  channel 1  channel 2  "
+		      "channel 3\n");
+	sbuf_printf(sb, "macInErrs:      %10u %10u %10u %10u\n",
+	    stats.macInErrs[0], stats.macInErrs[1], stats.macInErrs[2],
+	    stats.macInErrs[3]);
+	sbuf_printf(sb, "hdrInErrs:      %10u %10u %10u %10u\n",
+	    stats.hdrInErrs[0], stats.hdrInErrs[1], stats.hdrInErrs[2],
+	    stats.hdrInErrs[3]);
+	sbuf_printf(sb, "tcpInErrs:      %10u %10u %10u %10u\n",
+	    stats.tcpInErrs[0], stats.tcpInErrs[1], stats.tcpInErrs[2],
+	    stats.tcpInErrs[3]);
+	sbuf_printf(sb, "tcp6InErrs:     %10u %10u %10u %10u\n",
+	    stats.tcp6InErrs[0], stats.tcp6InErrs[1], stats.tcp6InErrs[2],
+	    stats.tcp6InErrs[3]);
+	sbuf_printf(sb, "tnlCongDrops:   %10u %10u %10u %10u\n",
+	    stats.tnlCongDrops[0], stats.tnlCongDrops[1], stats.tnlCongDrops[2],
+	    stats.tnlCongDrops[3]);
+	sbuf_printf(sb, "tnlTxDrops:     %10u %10u %10u %10u\n",
+	    stats.tnlTxDrops[0], stats.tnlTxDrops[1], stats.tnlTxDrops[2],
+	    stats.tnlTxDrops[3]);
+	sbuf_printf(sb, "ofldVlanDrops:  %10u %10u %10u %10u\n",
+	    stats.ofldVlanDrops[0], stats.ofldVlanDrops[1],
+	    stats.ofldVlanDrops[2], stats.ofldVlanDrops[3]);
+	sbuf_printf(sb, "ofldChanDrops:  %10u %10u %10u %10u\n\n",
+	    stats.ofldChanDrops[0], stats.ofldChanDrops[1],
+	    stats.ofldChanDrops[2], stats.ofldChanDrops[3]);
+	sbuf_printf(sb, "ofldNoNeigh:    %u\nofldCongDefer:  %u",
+	    stats.ofldNoNeigh, stats.ofldCongDefer);
+
+	rc = sbuf_finish(sb);
+	sbuf_delete(sb);
+
+	return (rc);
+}
+
+static int
+sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
+{
+	struct adapter *sc = arg1;
+	struct sbuf *sb;
+	int rc;
+	u64 nrate[NCHAN], orate[NCHAN];
+
+	rc = sysctl_wire_old_buffer(req, 0);
+	if (rc != 0)
+		return (rc);
+
+	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
+	if (sb == NULL)
+		return (ENOMEM);
+
+	t4_get_chan_txrate(sc, nrate, orate);
+	sbuf_printf(sb, "              channel 0   channel 1   channel 2   "
+		 "channel 3\n");
+	sbuf_printf(sb, "NIC B/s:     %10ju  %10ju  %10ju  %10ju\n",
+	    nrate[0], nrate[1], nrate[2], nrate[3]);
+	sbuf_printf(sb, "Offload B/s: %10ju  %10ju  %10ju  %10ju",
+	    orate[0], orate[1], orate[2], orate[3]);
+
+	rc = sbuf_finish(sb);
+	sbuf_delete(sb);
+
+	return (rc);
+}
+
 static inline void
 txq_start(struct ifnet *ifp, struct sge_txq *txq)
 {
@@ -2901,17 +4313,57 @@ txq_start(struct ifnet *ifp, struct sge_txq *txq)
 }
 
 void
-cxgbe_txq_start(void *arg, int count)
+t4_tx_callout(void *arg)
 {
-	struct sge_txq *txq = arg;
+	struct sge_eq *eq = arg;
+	struct adapter *sc;
+
+	if (EQ_TRYLOCK(eq) == 0)
+		goto reschedule;
+
+	if (eq->flags & EQ_STALLED && !can_resume_tx(eq)) {
+		EQ_UNLOCK(eq);
+reschedule:
+		if (__predict_true(!(eq->flags && EQ_DOOMED)))
+			callout_schedule(&eq->tx_callout, 1);
+		return;
+	}
+
+	EQ_LOCK_ASSERT_OWNED(eq);
+
+	if (__predict_true((eq->flags & EQ_DOOMED) == 0)) {
+
+		if ((eq->flags & EQ_TYPEMASK) == EQ_ETH) {
+			struct sge_txq *txq = arg;
+			struct port_info *pi = txq->ifp->if_softc;
+
+			sc = pi->adapter;
+		} else {
+			struct sge_wrq *wrq = arg;
+
+			sc = wrq->adapter;
+		}
+
+		taskqueue_enqueue(sc->tq[eq->tx_chan], &eq->tx_task);
+	}
 
-	TXQ_LOCK(txq);
-	if (txq->eq.flags & EQ_CRFLUSHED) {
-		txq->eq.flags &= ~EQ_CRFLUSHED;
+	EQ_UNLOCK(eq);
+}
+
+void
+t4_tx_task(void *arg, int count)
+{
+	struct sge_eq *eq = arg;
+
+	EQ_LOCK(eq);
+	if ((eq->flags & EQ_TYPEMASK) == EQ_ETH) {
+		struct sge_txq *txq = arg;
 		txq_start(txq->ifp, txq);
-	} else
-		wakeup_one(txq);	/* txq is going away, wakeup free_txq */
-	TXQ_UNLOCK(txq);
+	} else {
+		struct sge_wrq *wrq = arg;
+		t4_wrq_tx_locked(wrq->adapter, wrq, NULL);
+	}
+	EQ_UNLOCK(eq);
 }
 
 static uint32_t
@@ -2941,10 +4393,10 @@ fconf_to_mode(uint32_t fconf)
 		mode |= T4_FILTER_IP_TOS;
 
 	if (fconf & F_VLAN)
-		mode |= T4_FILTER_IVLAN;
+		mode |= T4_FILTER_VLAN;
 
 	if (fconf & F_VNIC_ID)
-		mode |= T4_FILTER_OVLAN;
+		mode |= T4_FILTER_VNIC;
 
 	if (fconf & F_PORT)
 		mode |= T4_FILTER_PORT;
@@ -2978,10 +4430,10 @@ mode_to_fconf(uint32_t mode)
 	if (mode & T4_FILTER_IP_TOS)
 		fconf |= F_TOS;
 
-	if (mode & T4_FILTER_IVLAN)
+	if (mode & T4_FILTER_VLAN)
 		fconf |= F_VLAN;
 
-	if (mode & T4_FILTER_OVLAN)
+	if (mode & T4_FILTER_VNIC)
 		fconf |= F_VNIC_ID;
 
 	if (mode & T4_FILTER_PORT)
@@ -3016,10 +4468,10 @@ fspec_to_fconf(struct t4_filter_specification *fs)
 	if (fs->val.tos || fs->mask.tos)
 		fconf |= F_TOS;
 
-	if (fs->val.ivlan_vld || fs->mask.ivlan_vld)
+	if (fs->val.vlan_vld || fs->mask.vlan_vld)
 		fconf |= F_VLAN;
 
-	if (fs->val.ovlan_vld || fs->mask.ovlan_vld)
+	if (fs->val.vnic_vld || fs->mask.vnic_vld)
 		fconf |= F_VNIC_ID;
 
 	if (fs->val.iport || fs->mask.iport)
@@ -3039,7 +4491,13 @@ get_filter_mode(struct adapter *sc, uint32_t *mode)
 	t4_read_indirect(sc, A_TP_PIO_ADDR, A_TP_PIO_DATA, &fconf, 1,
 	    A_TP_VLAN_PRI_MAP);
 
-	*mode = fconf_to_mode(fconf);
+	if (sc->filter_mode != fconf) {
+		log(LOG_WARNING, "%s: cached filter mode out of sync %x %x.\n",
+		    device_get_nameunit(sc->dev), sc->filter_mode, fconf);
+		sc->filter_mode = fconf;
+	}
+
+	*mode = fconf_to_mode(sc->filter_mode);
 
 	return (0);
 }
@@ -3063,7 +4521,21 @@ set_filter_mode(struct adapter *sc, uint32_t mode)
 		goto done;
 	}
 
+#ifndef TCP_OFFLOAD_DISABLE
+	if (sc->offload_map) {
+		rc = EBUSY;
+		goto done;
+	}
+#endif
+
+#ifdef notyet
 	rc = -t4_set_filter_mode(sc, fconf);
+	if (rc == 0)
+		sc->filter_mode = fconf;
+#else
+	rc = ENOTSUP;
+#endif
+
 done:
 	ADAPTER_UNLOCK(sc);
 	return (rc);
@@ -3123,7 +4595,6 @@ get_filter(struct adapter *sc, struct t4_filter *t)
 static int
 set_filter(struct adapter *sc, struct t4_filter *t)
 {
-	uint32_t fconf;
 	unsigned int nfilters, nports;
 	struct filter_entry *f;
 	int i;
@@ -3143,9 +4614,7 @@ set_filter(struct adapter *sc, struct t4_filter *t)
 		return (EINVAL);
 
 	/* Validate against the global filter mode */
-	t4_read_indirect(sc, A_TP_PIO_ADDR, A_TP_PIO_DATA, &fconf, 1,
-	    A_TP_VLAN_PRI_MAP);
-	if ((fconf | fspec_to_fconf(&t->fs)) != fconf)
+	if ((sc->filter_mode | fspec_to_fconf(&t->fs)) != sc->filter_mode)
 		return (E2BIG);
 
 	if (t->fs.action == FILTER_SWITCH && t->fs.eport >= nports)
@@ -3242,7 +4711,6 @@ clear_filter(struct filter_entry *f)
 static int
 set_filter_wr(struct adapter *sc, int fidx)
 {
-	int rc;
 	struct filter_entry *f = &sc->tids.ftid_tab[fidx];
 	struct mbuf *m;
 	struct fw_filter_wr *fwr;
@@ -3302,13 +4770,13 @@ set_filter_wr(struct adapter *sc, int fidx)
 	fwr->frag_to_ovlan_vldm =
 	    (V_FW_FILTER_WR_FRAG(f->fs.val.frag) |
 		V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) |
-		V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.ivlan_vld) |
-		V_FW_FILTER_WR_OVLAN_VLD(f->fs.val.ovlan_vld) |
-		V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.ivlan_vld) |
-		V_FW_FILTER_WR_OVLAN_VLDM(f->fs.mask.ovlan_vld));
+		V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.vlan_vld) |
+		V_FW_FILTER_WR_OVLAN_VLD(f->fs.val.vnic_vld) |
+		V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.vlan_vld) |
+		V_FW_FILTER_WR_OVLAN_VLDM(f->fs.mask.vnic_vld));
 	fwr->smac_sel = 0;
 	fwr->rx_chan_rx_rpl_iq = htobe16(V_FW_FILTER_WR_RX_CHAN(0) |
-	    V_FW_FILTER_WR_RX_RPL_IQ(sc->sge.intrq[0].abs_id));
+	    V_FW_FILTER_WR_RX_RPL_IQ(sc->sge.fwq.abs_id));
 	fwr->maci_to_matchtypem =
 	    htobe32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
 		V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
@@ -3322,10 +4790,10 @@ set_filter_wr(struct adapter *sc, int fidx)
 	fwr->ptclm = f->fs.mask.proto;
 	fwr->ttyp = f->fs.val.tos;
 	fwr->ttypm = f->fs.mask.tos;
-	fwr->ivlan = htobe16(f->fs.val.ivlan);
-	fwr->ivlanm = htobe16(f->fs.mask.ivlan);
-	fwr->ovlan = htobe16(f->fs.val.ovlan);
-	fwr->ovlanm = htobe16(f->fs.mask.ovlan);
+	fwr->ivlan = htobe16(f->fs.val.vlan);
+	fwr->ivlanm = htobe16(f->fs.mask.vlan);
+	fwr->ovlan = htobe16(f->fs.val.vnic);
+	fwr->ovlanm = htobe16(f->fs.mask.vnic);
 	bcopy(f->fs.val.dip, fwr->lip, sizeof (fwr->lip));
 	bcopy(f->fs.mask.dip, fwr->lipm, sizeof (fwr->lipm));
 	bcopy(f->fs.val.sip, fwr->fip, sizeof (fwr->fip));
@@ -3339,13 +4807,9 @@ set_filter_wr(struct adapter *sc, int fidx)
 
 	f->pending = 1;
 	sc->tids.ftids_in_use++;
-	rc = t4_mgmt_tx(sc, m);
-	if (rc != 0) {
-		sc->tids.ftids_in_use--;
-		m_freem(m);
-		clear_filter(f);
-	}
-	return (rc);
+
+	t4_mgmt_tx(sc, m);
+	return (0);
 }
 
 static int
@@ -3354,7 +4818,7 @@ del_filter_wr(struct adapter *sc, int fidx)
 	struct filter_entry *f = &sc->tids.ftid_tab[fidx];
 	struct mbuf *m;
 	struct fw_filter_wr *fwr;
-	unsigned int rc, ftid;
+	unsigned int ftid;
 
 	ADAPTER_LOCK_ASSERT_OWNED(sc);
 
@@ -3368,55 +4832,48 @@ del_filter_wr(struct adapter *sc, int fidx)
 	m->m_len = m->m_pkthdr.len = sizeof(*fwr);
 	bzero(fwr, sizeof (*fwr));
 
-	t4_mk_filtdelwr(ftid, fwr, sc->sge.intrq[0].abs_id);
+	t4_mk_filtdelwr(ftid, fwr, sc->sge.fwq.abs_id);
 
 	f->pending = 1;
-	rc = t4_mgmt_tx(sc, m);
-	if (rc != 0) {
-		f->pending = 0;
-		m_freem(m);
-	}
-	return (rc);
+	t4_mgmt_tx(sc, m);
+	return (0);
 }
 
-/* XXX move intr handlers to main.c and make this static */
-void
-filter_rpl(struct adapter *sc, const struct cpl_set_tcb_rpl *rpl)
+static int
+filter_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
 {
+	struct adapter *sc = iq->adapter;
+	const struct cpl_set_tcb_rpl *rpl = (const void *)(rss + 1);
 	unsigned int idx = GET_TID(rpl);
 
+	KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
+	    rss->opcode));
+
 	if (idx >= sc->tids.ftid_base &&
 	    (idx -= sc->tids.ftid_base) < sc->tids.nftids) {
 		unsigned int rc = G_COOKIE(rpl->cookie);
 		struct filter_entry *f = &sc->tids.ftid_tab[idx];
 
-		if (rc == FW_FILTER_WR_FLT_DELETED) {
-			/*
-			 * Clear the filter when we get confirmation from the
-			 * hardware that the filter has been deleted.
-			 */
-			clear_filter(f);
-			sc->tids.ftids_in_use--;
-		} else if (rc == FW_FILTER_WR_SMT_TBL_FULL) {
-			device_printf(sc->dev,
-			    "filter %u setup failed due to full SMT\n", idx);
-			clear_filter(f);
-			sc->tids.ftids_in_use--;
-		} else if (rc == FW_FILTER_WR_FLT_ADDED) {
+		if (rc == FW_FILTER_WR_FLT_ADDED) {
 			f->smtidx = (be64toh(rpl->oldval) >> 24) & 0xff;
 			f->pending = 0;  /* asynchronous setup completed */
 			f->valid = 1;
-		} else {
-			/*
-			 * Something went wrong.  Issue a warning about the
-			 * problem and clear everything out.
-			 */
+			return (0);
+		}
+
+		if (rc != FW_FILTER_WR_FLT_DELETED) {
+			/* Add or delete failed, need to display an error */
 			device_printf(sc->dev,
 			    "filter %u setup failed with error %u\n", idx, rc);
-			clear_filter(f);
-			sc->tids.ftids_in_use--;
 		}
+
+		clear_filter(f);
+		ADAPTER_LOCK(sc);
+		sc->tids.ftids_in_use--;
+		ADAPTER_UNLOCK(sc);
 	}
+
+	return (0);
 }
 
 static int
@@ -3448,6 +4905,84 @@ get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
 	return (rc);
 }
 
+static int
+read_card_mem(struct adapter *sc, struct t4_mem_range *mr)
+{
+	uint32_t base, size, lo, hi, win, off, remaining, i, n;
+	uint32_t *buf, *b;
+	int rc;
+
+	/* reads are in multiples of 32 bits */
+	if (mr->addr & 3 || mr->len & 3 || mr->len == 0)
+		return (EINVAL);
+
+	/*
+	 * We don't want to deal with potential holes so we mandate that the
+	 * requested region must lie entirely within one of the 3 memories.
+	 */
+	lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
+	if (lo & F_EDRAM0_ENABLE) {
+		hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
+		base = G_EDRAM0_BASE(hi) << 20;
+		size = G_EDRAM0_SIZE(hi) << 20;
+		if (size > 0 &&
+		    mr->addr >= base && mr->addr < base + size &&
+		    mr->addr + mr->len <= base + size)
+			goto proceed;
+	}
+	if (lo & F_EDRAM1_ENABLE) {
+		hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
+		base = G_EDRAM1_BASE(hi) << 20;
+		size = G_EDRAM1_SIZE(hi) << 20;
+		if (size > 0 &&
+		    mr->addr >= base && mr->addr < base + size &&
+		    mr->addr + mr->len <= base + size)
+			goto proceed;
+	}
+	if (lo & F_EXT_MEM_ENABLE) {
+		hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
+		base = G_EXT_MEM_BASE(hi) << 20;
+		size = G_EXT_MEM_SIZE(hi) << 20;
+		if (size > 0 &&
+		    mr->addr >= base && mr->addr < base + size &&
+		    mr->addr + mr->len <= base + size)
+			goto proceed;
+	}
+	return (ENXIO);
+
+proceed:
+	buf = b = malloc(mr->len, M_CXGBE, M_WAITOK);
+
+	/*
+	 * Position the PCIe window (we use memwin2) to the 16B aligned area
+	 * just at/before the requested region.
+	 */
+	win = mr->addr & ~0xf;
+	off = mr->addr - win;  /* offset of the requested region in the win */
+	remaining = mr->len;
+
+	while (remaining) {
+		t4_write_reg(sc,
+		    PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2), win);
+		t4_read_reg(sc,
+		    PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2));
+
+		/* number of bytes that we'll copy in the inner loop */
+		n = min(remaining, MEMWIN2_APERTURE - off);
+
+		for (i = 0; i < n; i += 4, remaining -= 4)
+			*b++ = t4_read_reg(sc, MEMWIN2_BASE + off + i);
+
+		win += MEMWIN2_APERTURE;
+		off = 0;
+	}
+
+	rc = copyout(buf, mr->data, mr->len);
+	free(buf, M_CXGBE);
+
+	return (rc);
+}
+
 int
 t4_os_find_pci_capability(struct adapter *sc, int cap)
 {
@@ -3518,6 +5053,22 @@ t4_os_link_changed(struct adapter *sc, int idx, int link_stat)
 		if_link_state_change(ifp, LINK_STATE_DOWN);
 }
 
+void
+t4_iterate(void (*func)(struct adapter *, void *), void *arg)
+{
+	struct adapter *sc;
+
+	mtx_lock(&t4_list_lock);
+	SLIST_FOREACH(sc, &t4_list, link) {
+		/*
+		 * func should not make any assumptions about what state sc is
+		 * in - the only guarantee is that sc->sc_lock is a valid lock.
+		 */
+		func(sc, arg);
+	}
+	mtx_unlock(&t4_list_lock);
+}
+
 static int
 t4_open(struct cdev *dev, int flags, int type, struct thread *td)
 {
@@ -3614,6 +5165,27 @@ t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
 	case CHELSIO_T4_GET_SGE_CONTEXT:
 		rc = get_sge_context(sc, (struct t4_sge_context *)data);
 		break;
+	case CHELSIO_T4_LOAD_FW: {
+		struct t4_data *fw = (struct t4_data *)data;
+		uint8_t *fw_data;
+
+		if (sc->flags & FULL_INIT_DONE)
+			return (EBUSY);
+
+		fw_data = malloc(fw->len, M_CXGBE, M_NOWAIT);
+		if (fw_data == NULL)
+			return (ENOMEM);
+
+		rc = copyin(fw->data, fw_data, fw->len);
+		if (rc == 0)
+			rc = -t4_load_fw(sc, fw_data, fw->len);
+
+		free(fw_data, M_CXGBE);
+		break;
+	}
+	case CHELSIO_T4_GET_MEM:
+		rc = read_card_mem(sc, (struct t4_mem_range *)data);
+		break;
 	default:
 		rc = EINVAL;
 	}
@@ -3621,14 +5193,247 @@ t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
 	return (rc);
 }
 
+#ifndef TCP_OFFLOAD_DISABLE
+static int
+toe_capability(struct port_info *pi, int enable)
+{
+	int rc;
+	struct adapter *sc = pi->adapter;
+
+	ADAPTER_LOCK_ASSERT_OWNED(sc);
+
+	if (!is_offload(sc))
+		return (ENODEV);
+
+	if (enable) {
+		if (isset(&sc->offload_map, pi->port_id))
+			return (0);
+
+		if (sc->offload_map == 0) {
+			rc = activate_uld(sc, ULD_TOM, &sc->tom);
+			if (rc != 0)
+				return (rc);
+		}
+
+		setbit(&sc->offload_map, pi->port_id);
+	} else {
+		if (!isset(&sc->offload_map, pi->port_id))
+			return (0);
+
+		clrbit(&sc->offload_map, pi->port_id);
+
+		if (sc->offload_map == 0) {
+			rc = deactivate_uld(&sc->tom);
+			if (rc != 0) {
+				setbit(&sc->offload_map, pi->port_id);
+				return (rc);
+			}
+		}
+	}
+
+	return (0);
+}
+
+/*
+ * Add an upper layer driver to the global list.
+ */
+int
+t4_register_uld(struct uld_info *ui)
+{
+	int rc = 0;
+	struct uld_info *u;
+
+	mtx_lock(&t4_uld_list_lock);
+	SLIST_FOREACH(u, &t4_uld_list, link) {
+	    if (u->uld_id == ui->uld_id) {
+		    rc = EEXIST;
+		    goto done;
+	    }
+	}
+
+	SLIST_INSERT_HEAD(&t4_uld_list, ui, link);
+	ui->refcount = 0;
+done:
+	mtx_unlock(&t4_uld_list_lock);
+	return (rc);
+}
+
+int
+t4_unregister_uld(struct uld_info *ui)
+{
+	int rc = EINVAL;
+	struct uld_info *u;
+
+	mtx_lock(&t4_uld_list_lock);
+
+	SLIST_FOREACH(u, &t4_uld_list, link) {
+	    if (u == ui) {
+		    if (ui->refcount > 0) {
+			    rc = EBUSY;
+			    goto done;
+		    }
+
+		    SLIST_REMOVE(&t4_uld_list, ui, uld_info, link);
+		    rc = 0;
+		    goto done;
+	    }
+	}
+done:
+	mtx_unlock(&t4_uld_list_lock);
+	return (rc);
+}
+
+static int
+activate_uld(struct adapter *sc, int id, struct uld_softc *usc)
+{
+	int rc = EAGAIN;
+	struct uld_info *ui;
+
+	mtx_lock(&t4_uld_list_lock);
+
+	SLIST_FOREACH(ui, &t4_uld_list, link) {
+		if (ui->uld_id == id) {
+			rc = ui->attach(sc, &usc->softc);
+			if (rc == 0) {
+				KASSERT(usc->softc != NULL,
+				    ("%s: ULD %d has no state", __func__, id));
+				ui->refcount++;
+				usc->uld = ui;
+			}
+			goto done;
+		}
+	}
+done:
+	mtx_unlock(&t4_uld_list_lock);
+
+	return (rc);
+}
+
+static int
+deactivate_uld(struct uld_softc *usc)
+{
+	int rc;
+
+	mtx_lock(&t4_uld_list_lock);
+
+	if (usc->uld == NULL || usc->softc == NULL) {
+		rc = EINVAL;
+		goto done;
+	}
+
+	rc = usc->uld->detach(usc->softc);
+	if (rc == 0) {
+		KASSERT(usc->uld->refcount > 0,
+		    ("%s: ULD has bad refcount", __func__));
+		usc->uld->refcount--;
+		usc->uld = NULL;
+		usc->softc = NULL;
+	}
+done:
+	mtx_unlock(&t4_uld_list_lock);
+
+	return (rc);
+}
+#endif
+
+/*
+ * Come up with reasonable defaults for some of the tunables, provided they're
+ * not set by the user (in which case we'll use the values as is).
+ */
+static void
+tweak_tunables(void)
+{
+	int nc = mp_ncpus;	/* our snapshot of the number of CPUs */
+
+	if (t4_ntxq10g < 1)
+		t4_ntxq10g = min(nc, NTXQ_10G);
+
+	if (t4_ntxq1g < 1)
+		t4_ntxq1g = min(nc, NTXQ_1G);
+
+	if (t4_nrxq10g < 1)
+		t4_nrxq10g = min(nc, NRXQ_10G);
+
+	if (t4_nrxq1g < 1)
+		t4_nrxq1g = min(nc, NRXQ_1G);
+
+#ifndef TCP_OFFLOAD_DISABLE
+	if (t4_nofldtxq10g < 1)
+		t4_nofldtxq10g = min(nc, NOFLDTXQ_10G);
+
+	if (t4_nofldtxq1g < 1)
+		t4_nofldtxq1g = min(nc, NOFLDTXQ_1G);
+
+	if (t4_nofldrxq10g < 1)
+		t4_nofldrxq10g = min(nc, NOFLDRXQ_10G);
+
+	if (t4_nofldrxq1g < 1)
+		t4_nofldrxq1g = min(nc, NOFLDRXQ_1G);
+#endif
+
+	if (t4_tmr_idx_10g < 0 || t4_tmr_idx_10g >= SGE_NTIMERS)
+		t4_tmr_idx_10g = TMR_IDX_10G;
+
+	if (t4_pktc_idx_10g < -1 || t4_pktc_idx_10g >= SGE_NCOUNTERS)
+		t4_pktc_idx_10g = PKTC_IDX_10G;
+
+	if (t4_tmr_idx_1g < 0 || t4_tmr_idx_1g >= SGE_NTIMERS)
+		t4_tmr_idx_1g = TMR_IDX_1G;
+
+	if (t4_pktc_idx_1g < -1 || t4_pktc_idx_1g >= SGE_NCOUNTERS)
+		t4_pktc_idx_1g = PKTC_IDX_1G;
+
+	if (t4_qsize_txq < 128)
+		t4_qsize_txq = 128;
+
+	if (t4_qsize_rxq < 128)
+		t4_qsize_rxq = 128;
+	while (t4_qsize_rxq & 7)
+		t4_qsize_rxq++;
+
+	t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
+}
+
 static int
 t4_mod_event(module_t mod, int cmd, void *arg)
 {
+	int rc = 0;
 
-	if (cmd == MOD_LOAD)
+	switch (cmd) {
+	case MOD_LOAD:
 		t4_sge_modload();
+		mtx_init(&t4_list_lock, "T4 adapters", 0, MTX_DEF);
+		SLIST_INIT(&t4_list);
+#ifndef TCP_OFFLOAD_DISABLE
+		mtx_init(&t4_uld_list_lock, "T4 ULDs", 0, MTX_DEF);
+		SLIST_INIT(&t4_uld_list);
+#endif
+		tweak_tunables();
+		break;
 
-	return (0);
+	case MOD_UNLOAD:
+#ifndef TCP_OFFLOAD_DISABLE
+		mtx_lock(&t4_uld_list_lock);
+		if (!SLIST_EMPTY(&t4_uld_list)) {
+			rc = EBUSY;
+			mtx_unlock(&t4_uld_list_lock);
+			break;
+		}
+		mtx_unlock(&t4_uld_list_lock);
+		mtx_destroy(&t4_uld_list_lock);
+#endif
+		mtx_lock(&t4_list_lock);
+		if (!SLIST_EMPTY(&t4_list)) {
+			rc = EBUSY;
+			mtx_unlock(&t4_list_lock);
+			break;
+		}
+		mtx_unlock(&t4_list_lock);
+		mtx_destroy(&t4_list_lock);
+		break;
+	}
+
+	return (rc);
 }
 
 static devclass_t t4_devclass;
diff --git a/sys/dev/cxgbe/t4_sge.c b/sys/dev/cxgbe/t4_sge.c
index b676799..41630e4 100644
--- a/sys/dev/cxgbe/t4_sge.c
+++ b/sys/dev/cxgbe/t4_sge.c
@@ -38,6 +38,7 @@ __FBSDID("$FreeBSD$");
 #include <sys/queue.h>
 #include <sys/taskqueue.h>
 #include <sys/sysctl.h>
+#include <sys/smp.h>
 #include <net/bpf.h>
 #include <net/ethernet.h>
 #include <net/if.h>
@@ -50,7 +51,7 @@ __FBSDID("$FreeBSD$");
 #include "common/t4_regs.h"
 #include "common/t4_regs_values.h"
 #include "common/t4_msg.h"
-#include "common/t4fw_interface.h"
+#include "t4_l2t.h"
 
 struct fl_buf_info {
 	int size;
@@ -91,12 +92,15 @@ struct sgl {
 	bus_dma_segment_t seg[TX_SGL_SEGS];
 };
 
-static void t4_evt_rx(void *);
-static void t4_eth_rx(void *);
+static int service_iq(struct sge_iq *, int);
+static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t,
+    int *);
+static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *);
 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int,
-    int, iq_intr_handler_t *, char *);
-static inline void init_fl(struct sge_fl *, int, char *);
-static inline void init_eq(struct sge_eq *, int, char *);
+    int, char *);
+static inline void init_fl(struct sge_fl *, int, int, char *);
+static inline void init_eq(struct sge_eq *, int, int, uint8_t, uint16_t,
+    char *);
 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *,
     bus_addr_t *, void **);
 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
@@ -104,26 +108,41 @@ static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
 static int alloc_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *,
     int, int);
 static int free_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *);
-static int alloc_intrq(struct adapter *, int, int, int);
-static int free_intrq(struct sge_iq *);
-static int alloc_fwq(struct adapter *, int);
-static int free_fwq(struct sge_iq *);
-static int alloc_rxq(struct port_info *, struct sge_rxq *, int, int);
+static int alloc_fwq(struct adapter *);
+static int free_fwq(struct adapter *);
+static int alloc_mgmtq(struct adapter *);
+static int free_mgmtq(struct adapter *);
+static int alloc_rxq(struct port_info *, struct sge_rxq *, int, int,
+    struct sysctl_oid *);
 static int free_rxq(struct port_info *, struct sge_rxq *);
-static int alloc_ctrlq(struct adapter *, struct sge_ctrlq *, int);
-static int free_ctrlq(struct adapter *, struct sge_ctrlq *);
-static int alloc_txq(struct port_info *, struct sge_txq *, int);
+#ifndef TCP_OFFLOAD_DISABLE
+static int alloc_ofld_rxq(struct port_info *, struct sge_ofld_rxq *, int, int,
+    struct sysctl_oid *);
+static int free_ofld_rxq(struct port_info *, struct sge_ofld_rxq *);
+#endif
+static int ctrl_eq_alloc(struct adapter *, struct sge_eq *);
+static int eth_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *);
+#ifndef TCP_OFFLOAD_DISABLE
+static int ofld_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *);
+#endif
+static int alloc_eq(struct adapter *, struct port_info *, struct sge_eq *);
+static int free_eq(struct adapter *, struct sge_eq *);
+static int alloc_wrq(struct adapter *, struct port_info *, struct sge_wrq *,
+    struct sysctl_oid *);
+static int free_wrq(struct adapter *, struct sge_wrq *);
+static int alloc_txq(struct port_info *, struct sge_txq *, int,
+    struct sysctl_oid *);
 static int free_txq(struct port_info *, struct sge_txq *);
 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int);
 static inline bool is_new_response(const struct sge_iq *, struct rsp_ctrl **);
 static inline void iq_next(struct sge_iq *);
 static inline void ring_fl_db(struct adapter *, struct sge_fl *);
-static void refill_fl(struct adapter *, struct sge_fl *, int, int);
+static int refill_fl(struct adapter *, struct sge_fl *, int);
+static void refill_sfl(void *);
 static int alloc_fl_sdesc(struct sge_fl *);
 static void free_fl_sdesc(struct sge_fl *);
-static int alloc_tx_maps(struct sge_txq *);
-static void free_tx_maps(struct sge_txq *);
 static void set_fl_tag_idx(struct sge_fl *, int);
+static void add_fl_to_sfl(struct adapter *, struct sge_fl *);
 
 static int get_pkt_sgl(struct sge_txq *, struct mbuf **, struct sgl *, int);
 static int free_pkt_sgl(struct sge_txq *, struct sgl *);
@@ -141,15 +160,13 @@ static inline int reclaimable(struct sge_eq *);
 static int reclaim_tx_descs(struct sge_txq *, int, int);
 static void write_eqflush_wr(struct sge_eq *);
 static __be64 get_flit(bus_dma_segment_t *, int, int);
-static int handle_sge_egr_update(struct adapter *,
-    const struct cpl_sge_egr_update *);
-static void handle_cpl(struct adapter *, struct sge_iq *);
+static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *,
+    struct mbuf *);
+static int handle_fw_rpl(struct sge_iq *, const struct rss_header *,
+    struct mbuf *);
 
-static int ctrl_tx(struct adapter *, struct sge_ctrlq *, struct mbuf *);
 static int sysctl_uint16(SYSCTL_HANDLER_ARGS);
 
-extern void filter_rpl(struct adapter *, const struct cpl_set_tcb_rpl *);
-
 /*
  * Called on MOD_LOAD and fills up fl_buf_info[].
  */
@@ -181,46 +198,103 @@ t4_sge_modload(void)
  *	We do not initialize any of the queues here, instead the driver
  *	top-level must request them individually.
  */
-void
+int
 t4_sge_init(struct adapter *sc)
 {
 	struct sge *s = &sc->sge;
-	int i;
+	int i, rc = 0;
+	uint32_t ctrl_mask, ctrl_val, hpsize, v;
+
+	ctrl_mask = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE |
+	    V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
+	    F_EGRSTATUSPAGESIZE;
+	ctrl_val = V_PKTSHIFT(FL_PKTSHIFT) | F_RXPKTCPLMODE |
+	    V_INGPADBOUNDARY(ilog2(FL_ALIGN) - 5) |
+	    V_EGRSTATUSPAGESIZE(SPG_LEN == 128);
+
+	hpsize = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
+	    V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
+	    V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
+	    V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
+	    V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
+	    V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
+	    V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
+	    V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
+
+	if (sc->flags & MASTER_PF) {
+		int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200};
+		int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */
+
+		t4_set_reg_field(sc, A_SGE_CONTROL, ctrl_mask, ctrl_val);
+		t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, hpsize);
+		for (i = 0; i < FL_BUF_SIZES; i++) {
+			t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i),
+			    FL_BUF_SIZE(i));
+		}
+
+		t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD,
+		    V_THRESHOLD_0(intr_pktcount[0]) |
+		    V_THRESHOLD_1(intr_pktcount[1]) |
+		    V_THRESHOLD_2(intr_pktcount[2]) |
+		    V_THRESHOLD_3(intr_pktcount[3]));
+
+		t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1,
+		    V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) |
+		    V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])));
+		t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3,
+		    V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) |
+		    V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])));
+		t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5,
+		    V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) |
+		    V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])));
+	}
+
+	v = t4_read_reg(sc, A_SGE_CONTROL);
+	if ((v & ctrl_mask) != ctrl_val) {
+		device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", v);
+		rc = EINVAL;
+	}
 
-	t4_set_reg_field(sc, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT) |
-			 V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
-			 F_EGRSTATUSPAGESIZE,
-			 V_INGPADBOUNDARY(ilog2(FL_ALIGN) - 5) |
-			 V_PKTSHIFT(FL_PKTSHIFT) |
-			 F_RXPKTCPLMODE |
-			 V_EGRSTATUSPAGESIZE(SPG_LEN == 128));
-	t4_set_reg_field(sc, A_SGE_HOST_PAGE_SIZE,
-			 V_HOSTPAGESIZEPF0(M_HOSTPAGESIZEPF0),
-			 V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10));
+	v = t4_read_reg(sc, A_SGE_HOST_PAGE_SIZE);
+	if (v != hpsize) {
+		device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", v);
+		rc = EINVAL;
+	}
 
 	for (i = 0; i < FL_BUF_SIZES; i++) {
-		t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i),
-		    FL_BUF_SIZE(i));
+		v = t4_read_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i));
+		if (v != FL_BUF_SIZE(i)) {
+			device_printf(sc->dev,
+			    "invalid SGE_FL_BUFFER_SIZE[%d](0x%x)\n", i, v);
+			rc = EINVAL;
+		}
 	}
 
-	i = t4_read_reg(sc, A_SGE_CONM_CTRL);
-	s->fl_starve_threshold = G_EGRTHRESHOLD(i) * 2 + 1;
+	v = t4_read_reg(sc, A_SGE_CONM_CTRL);
+	s->fl_starve_threshold = G_EGRTHRESHOLD(v) * 2 + 1;
+
+	v = t4_read_reg(sc, A_SGE_INGRESS_RX_THRESHOLD);
+	sc->sge.counter_val[0] = G_THRESHOLD_0(v);
+	sc->sge.counter_val[1] = G_THRESHOLD_1(v);
+	sc->sge.counter_val[2] = G_THRESHOLD_2(v);
+	sc->sge.counter_val[3] = G_THRESHOLD_3(v);
+
+	v = t4_read_reg(sc, A_SGE_TIMER_VALUE_0_AND_1);
+	sc->sge.timer_val[0] = G_TIMERVALUE0(v) / core_ticks_per_usec(sc);
+	sc->sge.timer_val[1] = G_TIMERVALUE1(v) / core_ticks_per_usec(sc);
+	v = t4_read_reg(sc, A_SGE_TIMER_VALUE_2_AND_3);
+	sc->sge.timer_val[2] = G_TIMERVALUE2(v) / core_ticks_per_usec(sc);
+	sc->sge.timer_val[3] = G_TIMERVALUE3(v) / core_ticks_per_usec(sc);
+	v = t4_read_reg(sc, A_SGE_TIMER_VALUE_4_AND_5);
+	sc->sge.timer_val[4] = G_TIMERVALUE4(v) / core_ticks_per_usec(sc);
+	sc->sge.timer_val[5] = G_TIMERVALUE5(v) / core_ticks_per_usec(sc);
 
-	t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD,
-		     V_THRESHOLD_0(s->counter_val[0]) |
-		     V_THRESHOLD_1(s->counter_val[1]) |
-		     V_THRESHOLD_2(s->counter_val[2]) |
-		     V_THRESHOLD_3(s->counter_val[3]));
+	t4_register_cpl_handler(sc, CPL_FW4_MSG, handle_fw_rpl);
+	t4_register_cpl_handler(sc, CPL_FW6_MSG, handle_fw_rpl);
+	t4_register_cpl_handler(sc, CPL_SGE_EGR_UPDATE, handle_sge_egr_update);
+	t4_register_cpl_handler(sc, CPL_RX_PKT, t4_eth_rx);
 
-	t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1,
-		     V_TIMERVALUE0(us_to_core_ticks(sc, s->timer_val[0])) |
-		     V_TIMERVALUE1(us_to_core_ticks(sc, s->timer_val[1])));
-	t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3,
-		     V_TIMERVALUE2(us_to_core_ticks(sc, s->timer_val[2])) |
-		     V_TIMERVALUE3(us_to_core_ticks(sc, s->timer_val[3])));
-	t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5,
-		     V_TIMERVALUE4(us_to_core_ticks(sc, s->timer_val[4])) |
-		     V_TIMERVALUE5(us_to_core_ticks(sc, s->timer_val[5])));
+	return (rc);
 }
 
 int
@@ -250,8 +324,7 @@ t4_destroy_dma_tag(struct adapter *sc)
 }
 
 /*
- * Allocate and initialize the firmware event queue, control queues, and the
- * interrupt queues.  The adapter owns all of these queues.
+ * Allocate and initialize the firmware event queue and the management queue.
  *
  * Returns errno on failure.  Resources allocated up to that point may still be
  * allocated.  Caller is responsible for cleanup in case this function fails.
@@ -259,110 +332,32 @@ t4_destroy_dma_tag(struct adapter *sc)
 int
 t4_setup_adapter_queues(struct adapter *sc)
 {
-	int i, j, rc, intr_idx, qsize;
-	struct sge_iq *iq;
-	struct sge_ctrlq *ctrlq;
-	iq_intr_handler_t *handler;
-	char name[16];
+	int rc;
 
 	ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
 
-	if (sysctl_ctx_init(&sc->ctx) == 0) {
-		struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
-		struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
-
-		sc->oid_fwq = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO,
-		    "fwq", CTLFLAG_RD, NULL, "firmware event queue");
-		sc->oid_ctrlq = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO,
-		    "ctrlq", CTLFLAG_RD, NULL, "ctrl queues");
-		sc->oid_intrq = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO,
-		    "intrq", CTLFLAG_RD, NULL, "interrupt queues");
-	}
-
-	/*
-	 * Interrupt queues
-	 */
-	intr_idx = sc->intr_count - NINTRQ(sc);
-	if (sc->flags & INTR_SHARED) {
-		qsize = max((sc->sge.nrxq + 1) * 2, INTR_IQ_QSIZE);
-		for (i = 0; i < NINTRQ(sc); i++, intr_idx++) {
-			snprintf(name, sizeof(name), "%s intrq%d",
-			    device_get_nameunit(sc->dev), i);
-
-			iq = &sc->sge.intrq[i];
-			init_iq(iq, sc, 0, 0, qsize, INTR_IQ_ESIZE, NULL, name);
-			rc = alloc_intrq(sc, i % sc->params.nports, i,
-			    intr_idx);
-
-			if (rc != 0) {
-				device_printf(sc->dev,
-				    "failed to create %s: %d\n", name, rc);
-				return (rc);
-			}
-		}
-	} else {
-		int qidx = 0;
-		struct port_info *pi;
-
-		for (i = 0; i < sc->params.nports; i++) {
-			pi = sc->port[i];
-			qsize = max((pi->nrxq + 1) * 2, INTR_IQ_QSIZE);
-			for (j = 0; j < pi->nrxq; j++, qidx++, intr_idx++) {
-				snprintf(name, sizeof(name), "%s intrq%d",
-				    device_get_nameunit(pi->dev), j);
-
-				iq = &sc->sge.intrq[qidx];
-				init_iq(iq, sc, 0, 0, qsize, INTR_IQ_ESIZE,
-				    NULL, name);
-				rc = alloc_intrq(sc, i, qidx, intr_idx);
-
-				if (rc != 0) {
-					device_printf(sc->dev,
-					    "failed to create %s: %d\n",
-					    name, rc);
-					return (rc);
-				}
-			}
-		}
-	}
+	sysctl_ctx_init(&sc->ctx);
+	sc->flags |= ADAP_SYSCTL_CTX;
 
 	/*
 	 * Firmware event queue
 	 */
-	snprintf(name, sizeof(name), "%s fwq", device_get_nameunit(sc->dev));
-	if (sc->intr_count > T4_EXTRA_INTR) {
-		handler = NULL;
-		intr_idx = 1;
-	} else {
-		handler = t4_evt_rx;
-		intr_idx = 0;
-	}
-
-	iq = &sc->sge.fwq;
-	init_iq(iq, sc, 0, 0, FW_IQ_QSIZE, FW_IQ_ESIZE, handler, name);
-	rc = alloc_fwq(sc, intr_idx);
+	rc = alloc_fwq(sc);
 	if (rc != 0) {
 		device_printf(sc->dev,
 		    "failed to create firmware event queue: %d\n", rc);
-
 		return (rc);
 	}
 
 	/*
-	 * Control queues - one per port.
+	 * Management queue.  This is just a control queue that uses the fwq as
+	 * its associated iq.
 	 */
-	ctrlq = &sc->sge.ctrlq[0];
-	for (i = 0; i < sc->params.nports; i++, ctrlq++) {
-		snprintf(name, sizeof(name), "%s ctrlq%d",
-		    device_get_nameunit(sc->dev), i);
-		init_eq(&ctrlq->eq, CTRL_EQ_QSIZE, name);
-
-		rc = alloc_ctrlq(sc, ctrlq, i);
-		if (rc != 0) {
-			device_printf(sc->dev,
-			    "failed to create control queue %d: %d\n", i, rc);
-			return (rc);
-		}
+	rc = alloc_mgmtq(sc);
+	if (rc != 0) {
+		device_printf(sc->dev,
+		    "failed to create management queue: %d\n", rc);
+		return (rc);
 	}
 
 	return (rc);
@@ -374,86 +369,278 @@ t4_setup_adapter_queues(struct adapter *sc)
 int
 t4_teardown_adapter_queues(struct adapter *sc)
 {
-	int i;
-	struct sge_iq *iq;
 
 	ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
 
-	/* Do this before freeing the queues */
-	if (sc->oid_fwq || sc->oid_ctrlq || sc->oid_intrq) {
+	/* Do this before freeing the queue */
+	if (sc->flags & ADAP_SYSCTL_CTX) {
 		sysctl_ctx_free(&sc->ctx);
-		sc->oid_fwq = NULL;
-		sc->oid_ctrlq = NULL;
-		sc->oid_intrq = NULL;
+		sc->flags &= ~ADAP_SYSCTL_CTX;
 	}
 
-	for (i = 0; i < sc->params.nports; i++)
-		free_ctrlq(sc, &sc->sge.ctrlq[i]);
+	free_mgmtq(sc);
+	free_fwq(sc);
+
+	return (0);
+}
+
+static inline int
+first_vector(struct port_info *pi)
+{
+	struct adapter *sc = pi->adapter;
+	int rc = T4_EXTRA_INTR, i;
+
+	if (sc->intr_count == 1)
+		return (0);
 
-	iq = &sc->sge.fwq;
-	free_fwq(iq);
+	for_each_port(sc, i) {
+		if (i == pi->port_id)
+			break;
+
+#ifndef TCP_OFFLOAD_DISABLE
+		if (sc->flags & INTR_DIRECT)
+			rc += pi->nrxq + pi->nofldrxq;
+		else
+			rc += max(pi->nrxq, pi->nofldrxq);
+#else
+		/*
+		 * Not compiled with offload support and intr_count > 1.  Only
+		 * NIC queues exist and they'd better be taking direct
+		 * interrupts.
+		 */
+		KASSERT(sc->flags & INTR_DIRECT,
+		    ("%s: intr_count %d, !INTR_DIRECT", __func__,
+		    sc->intr_count));
 
-	for (i = 0; i < NINTRQ(sc); i++) {
-		iq = &sc->sge.intrq[i];
-		free_intrq(iq);
+		rc += pi->nrxq;
+#endif
 	}
 
-	return (0);
+	return (rc);
+}
+
+/*
+ * Given an arbitrary "index," come up with an iq that can be used by other
+ * queues (of this port) for interrupt forwarding, SGE egress updates, etc.
+ * The iq returned is guaranteed to be something that takes direct interrupts.
+ */
+static struct sge_iq *
+port_intr_iq(struct port_info *pi, int idx)
+{
+	struct adapter *sc = pi->adapter;
+	struct sge *s = &sc->sge;
+	struct sge_iq *iq = NULL;
+
+	if (sc->intr_count == 1)
+		return (&sc->sge.fwq);
+
+#ifndef TCP_OFFLOAD_DISABLE
+	if (sc->flags & INTR_DIRECT) {
+		idx %= pi->nrxq + pi->nofldrxq;
+		
+		if (idx >= pi->nrxq) {
+			idx -= pi->nrxq;
+			iq = &s->ofld_rxq[pi->first_ofld_rxq + idx].iq;
+		} else
+			iq = &s->rxq[pi->first_rxq + idx].iq;
+
+	} else {
+		idx %= max(pi->nrxq, pi->nofldrxq);
+
+		if (pi->nrxq >= pi->nofldrxq)
+			iq = &s->rxq[pi->first_rxq + idx].iq;
+		else
+			iq = &s->ofld_rxq[pi->first_ofld_rxq + idx].iq;
+	}
+#else
+	/*
+	 * Not compiled with offload support and intr_count > 1.  Only NIC
+	 * queues exist and they'd better be taking direct interrupts.
+	 */
+	KASSERT(sc->flags & INTR_DIRECT,
+	    ("%s: intr_count %d, !INTR_DIRECT", __func__, sc->intr_count));
+
+	idx %= pi->nrxq;
+	iq = &s->rxq[pi->first_rxq + idx].iq;
+#endif
+
+	KASSERT(iq->flags & IQ_INTR, ("%s: EDOOFUS", __func__));
+	return (iq);
 }
 
 int
-t4_setup_eth_queues(struct port_info *pi)
+t4_setup_port_queues(struct port_info *pi)
 {
-	int rc = 0, i, intr_idx;
+	int rc = 0, i, j, intr_idx, iqid;
 	struct sge_rxq *rxq;
 	struct sge_txq *txq;
+	struct sge_wrq *ctrlq;
+#ifndef TCP_OFFLOAD_DISABLE
+	struct sge_ofld_rxq *ofld_rxq;
+	struct sge_wrq *ofld_txq;
+#endif
 	char name[16];
 	struct adapter *sc = pi->adapter;
+	struct sysctl_oid *oid = device_get_sysctl_tree(pi->dev), *oid2 = NULL;
+	struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
 
-	if (sysctl_ctx_init(&pi->ctx) == 0) {
-		struct sysctl_oid *oid = device_get_sysctl_tree(pi->dev);
-		struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
+	oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "rxq", CTLFLAG_RD,
+	    NULL, "rx queues");
 
-		pi->oid_rxq = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO,
-		    "rxq", CTLFLAG_RD, NULL, "rx queues");
-		pi->oid_txq = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO,
-		    "txq", CTLFLAG_RD, NULL, "tx queues");
+#ifndef TCP_OFFLOAD_DISABLE
+	if (is_offload(sc)) {
+		oid2 = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_rxq",
+		    CTLFLAG_RD, NULL,
+		    "rx queues for offloaded TCP connections");
 	}
+#endif
+
+	/* Interrupt vector to start from (when using multiple vectors) */
+	intr_idx = first_vector(pi);
 
+	/*
+	 * First pass over all rx queues (NIC and TOE):
+	 * a) initialize iq and fl
+	 * b) allocate queue iff it will take direct interrupts.
+	 */
 	for_each_rxq(pi, i, rxq) {
 
 		snprintf(name, sizeof(name), "%s rxq%d-iq",
 		    device_get_nameunit(pi->dev), i);
-		init_iq(&rxq->iq, sc, pi->tmr_idx, pi->pktc_idx,
-		    pi->qsize_rxq, RX_IQ_ESIZE, t4_eth_rx, name);
+		init_iq(&rxq->iq, sc, pi->tmr_idx, pi->pktc_idx, pi->qsize_rxq,
+		    RX_IQ_ESIZE, name);
 
 		snprintf(name, sizeof(name), "%s rxq%d-fl",
 		    device_get_nameunit(pi->dev), i);
-		init_fl(&rxq->fl, pi->qsize_rxq / 8, name);
+		init_fl(&rxq->fl, pi->qsize_rxq / 8, pi->ifp->if_mtu, name);
+
+		if (sc->flags & INTR_DIRECT
+#ifndef TCP_OFFLOAD_DISABLE
+		    || (sc->intr_count > 1 && pi->nrxq >= pi->nofldrxq)
+#endif
+		   ) {
+			rxq->iq.flags |= IQ_INTR;
+			rc = alloc_rxq(pi, rxq, intr_idx, i, oid);
+			if (rc != 0)
+				goto done;
+			intr_idx++;
+		}
+	}
 
-		intr_idx = pi->first_rxq + i;
-		if (sc->flags & INTR_SHARED)
-			intr_idx %= NINTRQ(sc);
+#ifndef TCP_OFFLOAD_DISABLE
+	for_each_ofld_rxq(pi, i, ofld_rxq) {
 
-		rc = alloc_rxq(pi, rxq, intr_idx, i);
+		snprintf(name, sizeof(name), "%s ofld_rxq%d-iq",
+		    device_get_nameunit(pi->dev), i);
+		init_iq(&ofld_rxq->iq, sc, pi->tmr_idx, pi->pktc_idx,
+		    pi->qsize_rxq, RX_IQ_ESIZE, name);
+
+		snprintf(name, sizeof(name), "%s ofld_rxq%d-fl",
+		    device_get_nameunit(pi->dev), i);
+		init_fl(&ofld_rxq->fl, pi->qsize_rxq / 8, MJUM16BYTES, name);
+
+		if (sc->flags & INTR_DIRECT ||
+		    (sc->intr_count > 1 && pi->nofldrxq > pi->nrxq)) {
+			ofld_rxq->iq.flags |= IQ_INTR;
+			rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid2);
+			if (rc != 0)
+				goto done;
+			intr_idx++;
+		}
+	}
+#endif
+
+	/*
+	 * Second pass over all rx queues (NIC and TOE).  The queues forwarding
+	 * their interrupts are allocated now.
+	 */
+	j = 0;
+	for_each_rxq(pi, i, rxq) {
+		if (rxq->iq.flags & IQ_INTR)
+			continue;
+
+		intr_idx = port_intr_iq(pi, j)->abs_id;
+
+		rc = alloc_rxq(pi, rxq, intr_idx, i, oid);
+		if (rc != 0)
+			goto done;
+		j++;
+	}
+
+#ifndef TCP_OFFLOAD_DISABLE
+	for_each_ofld_rxq(pi, i, ofld_rxq) {
+		if (ofld_rxq->iq.flags & IQ_INTR)
+			continue;
+
+		intr_idx = port_intr_iq(pi, j)->abs_id;
+
+		rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid2);
 		if (rc != 0)
 			goto done;
+		j++;
 	}
+#endif
 
+	/*
+	 * Now the tx queues.  Only one pass needed.
+	 */
+	oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD,
+	    NULL, "tx queues");
+	j = 0;
 	for_each_txq(pi, i, txq) {
+		uint16_t iqid;
+
+		iqid = port_intr_iq(pi, j)->cntxt_id;
 
 		snprintf(name, sizeof(name), "%s txq%d",
 		    device_get_nameunit(pi->dev), i);
-		init_eq(&txq->eq, pi->qsize_txq, name);
+		init_eq(&txq->eq, EQ_ETH, pi->qsize_txq, pi->tx_chan, iqid,
+		    name);
 
-		rc = alloc_txq(pi, txq, i);
+		rc = alloc_txq(pi, txq, i, oid);
 		if (rc != 0)
 			goto done;
+		j++;
 	}
 
+#ifndef TCP_OFFLOAD_DISABLE
+	oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_txq",
+	    CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections");
+	for_each_ofld_txq(pi, i, ofld_txq) {
+		uint16_t iqid;
+
+		iqid = port_intr_iq(pi, j)->cntxt_id;
+
+		snprintf(name, sizeof(name), "%s ofld_txq%d",
+		    device_get_nameunit(pi->dev), i);
+		init_eq(&ofld_txq->eq, EQ_OFLD, pi->qsize_txq, pi->tx_chan,
+		    iqid, name);
+
+		snprintf(name, sizeof(name), "%d", i);
+		oid2 = SYSCTL_ADD_NODE(&pi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO,
+		    name, CTLFLAG_RD, NULL, "offload tx queue");
+
+		rc = alloc_wrq(sc, pi, ofld_txq, oid2);
+		if (rc != 0)
+			goto done;
+		j++;
+	}
+#endif
+
+	/*
+	 * Finally, the control queue.
+	 */
+	oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD,
+	    NULL, "ctrl queue");
+	ctrlq = &sc->sge.ctrlq[pi->port_id];
+	iqid = port_intr_iq(pi, 0)->cntxt_id;
+	snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(pi->dev));
+	init_eq(&ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid, name);
+	rc = alloc_wrq(sc, pi, ctrlq, oid);
+
 done:
 	if (rc)
-		t4_teardown_eth_queues(pi);
+		t4_teardown_port_queues(pi);
 
 	return (rc);
 }
@@ -462,90 +649,91 @@ done:
  * Idempotent
  */
 int
-t4_teardown_eth_queues(struct port_info *pi)
+t4_teardown_port_queues(struct port_info *pi)
 {
 	int i;
+	struct adapter *sc = pi->adapter;
 	struct sge_rxq *rxq;
 	struct sge_txq *txq;
+#ifndef TCP_OFFLOAD_DISABLE
+	struct sge_ofld_rxq *ofld_rxq;
+	struct sge_wrq *ofld_txq;
+#endif
 
 	/* Do this before freeing the queues */
-	if (pi->oid_txq || pi->oid_rxq) {
+	if (pi->flags & PORT_SYSCTL_CTX) {
 		sysctl_ctx_free(&pi->ctx);
-		pi->oid_txq = pi->oid_rxq = NULL;
+		pi->flags &= ~PORT_SYSCTL_CTX;
 	}
 
+	/*
+	 * Take down all the tx queues first, as they reference the rx queues
+	 * (for egress updates, etc.).
+	 */
+
+	free_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
+
 	for_each_txq(pi, i, txq) {
 		free_txq(pi, txq);
 	}
 
+#ifndef TCP_OFFLOAD_DISABLE
+	for_each_ofld_txq(pi, i, ofld_txq) {
+		free_wrq(sc, ofld_txq);
+	}
+#endif
+
+	/*
+	 * Then take down the rx queues that forward their interrupts, as they
+	 * reference other rx queues.
+	 */
+
+	for_each_rxq(pi, i, rxq) {
+		if ((rxq->iq.flags & IQ_INTR) == 0)
+			free_rxq(pi, rxq);
+	}
+
+#ifndef TCP_OFFLOAD_DISABLE
+	for_each_ofld_rxq(pi, i, ofld_rxq) {
+		if ((ofld_rxq->iq.flags & IQ_INTR) == 0)
+			free_ofld_rxq(pi, ofld_rxq);
+	}
+#endif
+
+	/*
+	 * Then take down the rx queues that take direct interrupts.
+	 */
+
 	for_each_rxq(pi, i, rxq) {
-		free_rxq(pi, rxq);
+		if (rxq->iq.flags & IQ_INTR)
+			free_rxq(pi, rxq);
 	}
 
+#ifndef TCP_OFFLOAD_DISABLE
+	for_each_ofld_rxq(pi, i, ofld_rxq) {
+		if (ofld_rxq->iq.flags & IQ_INTR)
+			free_ofld_rxq(pi, ofld_rxq);
+	}
+#endif
+
 	return (0);
 }
 
-/* Deals with errors and the first (and only) interrupt queue */
+/*
+ * Deals with errors and the firmware event queue.  All data rx queues forward
+ * their interrupt to the firmware event queue.
+ */
 void
 t4_intr_all(void *arg)
 {
 	struct adapter *sc = arg;
+	struct sge_iq *fwq = &sc->sge.fwq;
 
 	t4_intr_err(arg);
-	t4_intr(&sc->sge.intrq[0]);
-}
-
-/* Deals with interrupts, and a few CPLs, on the given interrupt queue */
-void
-t4_intr(void *arg)
-{
-	struct sge_iq *iq = arg, *q;
-	struct adapter *sc = iq->adapter;
-	struct rsp_ctrl *ctrl;
-	const struct rss_header *rss;
-	int ndesc_pending = 0, ndesc_total = 0;
-	int qid, rsp_type;
-
-	if (!atomic_cmpset_32(&iq->state, IQS_IDLE, IQS_BUSY))
-		return;
-
-	while (is_new_response(iq, &ctrl)) {
-
-		rmb();
-
-		rss = (const void *)iq->cdesc;
-		rsp_type = G_RSPD_TYPE(ctrl->u.type_gen);
-
-		if (__predict_false(rsp_type == X_RSPD_TYPE_CPL)) {
-			handle_cpl(sc, iq);
-			goto nextdesc;
-		}
-
-		qid = ntohl(ctrl->pldbuflen_qid) - sc->sge.iq_start;
-		q = sc->sge.iqmap[qid];
-
-		if (atomic_cmpset_32(&q->state, IQS_IDLE, IQS_BUSY)) {
-			q->handler(q);
-			atomic_cmpset_32(&q->state, IQS_BUSY, IQS_IDLE);
-		}
-
-nextdesc:	ndesc_total++;
-		if (++ndesc_pending >= iq->qsize / 4) {
-			t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS),
-			    V_CIDXINC(ndesc_pending) |
-			    V_INGRESSQID(iq->cntxt_id) |
-			    V_SEINTARM(
-				V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
-			ndesc_pending = 0;
-		}
-
-		iq_next(iq);
+	if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) {
+		service_iq(fwq, 0);
+		atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE);
 	}
-
-	t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndesc_pending) |
-	    V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
-
-	atomic_cmpset_32(&iq->state, IQS_BUSY, IQS_IDLE);
 }
 
 /* Deals with error interrupts */
@@ -558,259 +746,452 @@ t4_intr_err(void *arg)
 	t4_slow_intr_handler(sc);
 }
 
-/* Deals with the firmware event queue */
 void
 t4_intr_evt(void *arg)
 {
 	struct sge_iq *iq = arg;
 
-	if (atomic_cmpset_32(&iq->state, IQS_IDLE, IQS_BUSY)) {
-		t4_evt_rx(arg);
-		atomic_cmpset_32(&iq->state, IQS_BUSY, IQS_IDLE);
+	if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
+		service_iq(iq, 0);
+		atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
 	}
 }
 
-static void
-t4_evt_rx(void *arg)
+void
+t4_intr(void *arg)
 {
 	struct sge_iq *iq = arg;
+
+	if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
+		service_iq(iq, 0);
+		atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
+	}
+}
+
+/*
+ * Deals with anything and everything on the given ingress queue.
+ */
+static int
+service_iq(struct sge_iq *iq, int budget)
+{
+	struct sge_iq *q;
+	struct sge_rxq *rxq = (void *)iq;	/* Use iff iq is part of rxq */
+	struct sge_fl *fl = &rxq->fl;		/* Use iff IQ_HAS_FL */
 	struct adapter *sc = iq->adapter;
 	struct rsp_ctrl *ctrl;
-	int ndesc_pending = 0, ndesc_total = 0;
+	const struct rss_header *rss;
+	int ndescs = 0, limit, fl_bufs_used = 0;
+	int rsp_type;
+	uint32_t lq;
+	struct mbuf *m0;
+	STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql);
+
+	limit = budget ? budget : iq->qsize / 8;
+
+	KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
+
+	/*
+	 * We always come back and check the descriptor ring for new indirect
+	 * interrupts and other responses after running a single handler.
+	 */
+	for (;;) {
+		while (is_new_response(iq, &ctrl)) {
+
+			rmb();
+
+			m0 = NULL;
+			rsp_type = G_RSPD_TYPE(ctrl->u.type_gen);
+			lq = be32toh(ctrl->pldbuflen_qid);
+			rss = (const void *)iq->cdesc;
+
+			switch (rsp_type) {
+			case X_RSPD_TYPE_FLBUF:
+
+				KASSERT(iq->flags & IQ_HAS_FL,
+				    ("%s: data for an iq (%p) with no freelist",
+				    __func__, iq));
+
+				m0 = get_fl_payload(sc, fl, lq, &fl_bufs_used);
+#ifdef T4_PKT_TIMESTAMP
+				/*
+				 * 60 bit timestamp for the payload is
+				 * *(uint64_t *)m0->m_pktdat.  Note that it is
+				 * in the leading free-space in the mbuf.  The
+				 * kernel can clobber it during a pullup,
+				 * m_copymdata, etc.  You need to make sure that
+				 * the mbuf reaches you unmolested if you care
+				 * about the timestamp.
+				 */
+				*(uint64_t *)m0->m_pktdat =
+				    be64toh(ctrl->u.last_flit) &
+				    0xfffffffffffffff;
+#endif
+
+				/* fall through */
+
+			case X_RSPD_TYPE_CPL:
+				KASSERT(rss->opcode < NUM_CPL_CMDS,
+				    ("%s: bad opcode %02x.", __func__,
+				    rss->opcode));
+				sc->cpl_handler[rss->opcode](iq, rss, m0);
+				break;
+
+			case X_RSPD_TYPE_INTR:
+
+				/*
+				 * Interrupts should be forwarded only to queues
+				 * that are not forwarding their interrupts.
+				 * This means service_iq can recurse but only 1
+				 * level deep.
+				 */
+				KASSERT(budget == 0,
+				    ("%s: budget %u, rsp_type %u", __func__,
+				    budget, rsp_type));
+
+				q = sc->sge.iqmap[lq - sc->sge.iq_start];
+				if (atomic_cmpset_int(&q->state, IQS_IDLE,
+				    IQS_BUSY)) {
+					if (service_iq(q, q->qsize / 8) == 0) {
+						atomic_cmpset_int(&q->state,
+						    IQS_BUSY, IQS_IDLE);
+					} else {
+						STAILQ_INSERT_TAIL(&iql, q,
+						    link);
+					}
+				}
+				break;
 
-	KASSERT(iq == &sc->sge.fwq, ("%s: unexpected ingress queue", __func__));
+			default:
+				panic("%s: rsp_type %u", __func__, rsp_type);
+			}
 
-	while (is_new_response(iq, &ctrl)) {
-		int rsp_type;
+			iq_next(iq);
+			if (++ndescs == limit) {
+				t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS),
+				    V_CIDXINC(ndescs) |
+				    V_INGRESSQID(iq->cntxt_id) |
+				    V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
+				ndescs = 0;
+
+				if (fl_bufs_used > 0) {
+					FL_LOCK(fl);
+					fl->needed += fl_bufs_used;
+					refill_fl(sc, fl, fl->cap / 8);
+					FL_UNLOCK(fl);
+					fl_bufs_used = 0;
+				}
 
-		rmb();
+				if (budget)
+					return (EINPROGRESS);
+			}
+		}
 
-		rsp_type = G_RSPD_TYPE(ctrl->u.type_gen);
-		if (__predict_false(rsp_type != X_RSPD_TYPE_CPL))
-			panic("%s: unexpected rsp_type %d", __func__, rsp_type);
+		if (STAILQ_EMPTY(&iql))
+			break;
 
-		handle_cpl(sc, iq);
+		/*
+		 * Process the head only, and send it to the back of the list if
+		 * it's still not done.
+		 */
+		q = STAILQ_FIRST(&iql);
+		STAILQ_REMOVE_HEAD(&iql, link);
+		if (service_iq(q, q->qsize / 8) == 0)
+			atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE);
+		else
+			STAILQ_INSERT_TAIL(&iql, q, link);
+	}
 
-		ndesc_total++;
-		if (++ndesc_pending >= iq->qsize / 4) {
-			t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS),
-			    V_CIDXINC(ndesc_pending) |
-			    V_INGRESSQID(iq->cntxt_id) |
-			    V_SEINTARM(
-				V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
-			ndesc_pending = 0;
+#ifdef INET
+	if (iq->flags & IQ_LRO_ENABLED) {
+		struct lro_ctrl *lro = &rxq->lro;
+		struct lro_entry *l;
+
+		while (!SLIST_EMPTY(&lro->lro_active)) {
+			l = SLIST_FIRST(&lro->lro_active);
+			SLIST_REMOVE_HEAD(&lro->lro_active, next);
+			tcp_lro_flush(lro, l);
 		}
+	}
+#endif
+
+	t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndescs) |
+	    V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
+
+	if (iq->flags & IQ_HAS_FL) {
+		int starved;
 
-		iq_next(iq);
+		FL_LOCK(fl);
+		fl->needed += fl_bufs_used;
+		starved = refill_fl(sc, fl, fl->cap / 4);
+		FL_UNLOCK(fl);
+		if (__predict_false(starved != 0))
+			add_fl_to_sfl(sc, fl);
 	}
 
-	t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndesc_pending) |
-	    V_INGRESSQID(iq->cntxt_id) | V_SEINTARM(iq->intr_params));
+	return (0);
 }
 
+
 #ifdef T4_PKT_TIMESTAMP
 #define RX_COPY_THRESHOLD (MINCLSIZE - 8)
 #else
 #define RX_COPY_THRESHOLD MINCLSIZE
 #endif
 
-static void
-t4_eth_rx(void *arg)
+static struct mbuf *
+get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf,
+    int *fl_bufs_used)
 {
-	struct sge_rxq *rxq = arg;
-	struct sge_iq *iq = arg;
-	struct adapter *sc = iq->adapter;
-	struct rsp_ctrl *ctrl;
-	struct ifnet *ifp = rxq->ifp;
-	struct sge_fl *fl = &rxq->fl;
-	struct fl_sdesc *sd = &fl->sdesc[fl->cidx], *sd_next;
-	const struct rss_header *rss;
-	const struct cpl_rx_pkt *cpl;
-	uint32_t len;
-	int ndescs = 0, i;
 	struct mbuf *m0, *m;
-#ifdef INET
-	struct lro_ctrl *lro = &rxq->lro;
-	struct lro_entry *l;
-#endif
+	struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
+	unsigned int nbuf, len;
 
-	prefetch(sd->m);
-	prefetch(sd->cl);
+	/*
+	 * No assertion for the fl lock because we don't need it.  This routine
+	 * is called only from the rx interrupt handler and it only updates
+	 * fl->cidx.  (Contrast that with fl->pidx/fl->needed which could be
+	 * updated in the rx interrupt handler or the starvation helper routine.
+	 * That's why code that manipulates fl->pidx/fl->needed needs the fl
+	 * lock but this routine does not).
+	 */
 
-	iq->intr_next = iq->intr_params;
-	while (is_new_response(iq, &ctrl)) {
+	if (__predict_false((len_newbuf & F_RSPD_NEWBUF) == 0))
+		panic("%s: cannot handle packed frames", __func__);
+	len = G_RSPD_LEN(len_newbuf);
 
-		rmb();
+	m0 = sd->m;
+	sd->m = NULL;	/* consumed */
 
-		rss = (const void *)iq->cdesc;
-		i = G_RSPD_TYPE(ctrl->u.type_gen);
+	bus_dmamap_sync(fl->tag[sd->tag_idx], sd->map, BUS_DMASYNC_POSTREAD);
+	m_init(m0, NULL, 0, M_NOWAIT, MT_DATA, M_PKTHDR);
+#ifdef T4_PKT_TIMESTAMP
+	/* Leave room for a timestamp */
+	m0->m_data += 8;
+#endif
 
-		KASSERT(i == X_RSPD_TYPE_FLBUF && rss->opcode == CPL_RX_PKT,
-		    ("%s: unexpected type %d CPL opcode 0x%x",
-		    __func__, i, rss->opcode));
+	if (len < RX_COPY_THRESHOLD) {
+		/* copy data to mbuf, buffer will be recycled */
+		bcopy(sd->cl, mtod(m0, caddr_t), len);
+		m0->m_len = len;
+	} else {
+		bus_dmamap_unload(fl->tag[sd->tag_idx], sd->map);
+		m_cljset(m0, sd->cl, FL_BUF_TYPE(sd->tag_idx));
+		sd->cl = NULL;	/* consumed */
+		m0->m_len = min(len, FL_BUF_SIZE(sd->tag_idx));
+	}
+	m0->m_pkthdr.len = len;
 
-		sd_next = sd + 1;
-		if (__predict_false(fl->cidx + 1 == fl->cap))
-			sd_next = fl->sdesc;
-		prefetch(sd_next->m);
-		prefetch(sd_next->cl);
+	sd++;
+	if (__predict_false(++fl->cidx == fl->cap)) {
+		sd = fl->sdesc;
+		fl->cidx = 0;
+	}
 
-		cpl = (const void *)(rss + 1);
+	m = m0;
+	len -= m->m_len;
+	nbuf = 1;	/* # of fl buffers used */
 
-		m0 = sd->m;
+	while (len > 0) {
+		m->m_next = sd->m;
 		sd->m = NULL;	/* consumed */
-
-		len = be32toh(ctrl->pldbuflen_qid);
-		if (__predict_false((len & F_RSPD_NEWBUF) == 0))
-			panic("%s: cannot handle packed frames", __func__);
-		len = G_RSPD_LEN(len);
+		m = m->m_next;
 
 		bus_dmamap_sync(fl->tag[sd->tag_idx], sd->map,
 		    BUS_DMASYNC_POSTREAD);
 
-		m_init(m0, NULL, 0, M_NOWAIT, MT_DATA, M_PKTHDR);
-
-#ifdef T4_PKT_TIMESTAMP
-		*mtod(m0, uint64_t *) =
-		    be64toh(ctrl->u.last_flit & 0xfffffffffffffff);
-		m0->m_data += 8;
-
-		/*
-		 * 60 bit timestamp value is *(uint64_t *)m0->m_pktdat.  Note
-		 * that it is in the leading free-space (see M_LEADINGSPACE) in
-		 * the mbuf.  The kernel can clobber it during a pullup,
-		 * m_copymdata, etc.  You need to make sure that the mbuf
-		 * reaches you unmolested if you care about the timestamp.
-		 */
-#endif
-
-		if (len < RX_COPY_THRESHOLD) {
-			/* copy data to mbuf, buffer will be recycled */
-			bcopy(sd->cl, mtod(m0, caddr_t), len);
-			m0->m_len = len;
+		m_init(m, NULL, 0, M_NOWAIT, MT_DATA, 0);
+		if (len <= MLEN) {
+			bcopy(sd->cl, mtod(m, caddr_t), len);
+			m->m_len = len;
 		} else {
-			bus_dmamap_unload(fl->tag[sd->tag_idx], sd->map);
-			m_cljset(m0, sd->cl, FL_BUF_TYPE(sd->tag_idx));
+			bus_dmamap_unload(fl->tag[sd->tag_idx],
+			    sd->map);
+			m_cljset(m, sd->cl, FL_BUF_TYPE(sd->tag_idx));
 			sd->cl = NULL;	/* consumed */
-			m0->m_len = min(len, FL_BUF_SIZE(sd->tag_idx));
+			m->m_len = min(len, FL_BUF_SIZE(sd->tag_idx));
 		}
 
-		len -= FL_PKTSHIFT;
-		m0->m_len -= FL_PKTSHIFT;
-		m0->m_data += FL_PKTSHIFT;
-
-		m0->m_pkthdr.len = len;
-		m0->m_pkthdr.rcvif = ifp;
-		m0->m_flags |= M_FLOWID;
-		m0->m_pkthdr.flowid = rss->hash_val;
-
-		if (cpl->csum_calc && !cpl->err_vec &&
-		    ifp->if_capenable & IFCAP_RXCSUM) {
-			m0->m_pkthdr.csum_flags |= (CSUM_IP_CHECKED |
-			    CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
-			if (cpl->ip_frag)
-				m0->m_pkthdr.csum_data = be16toh(cpl->csum);
-			else
-				m0->m_pkthdr.csum_data = 0xffff;
-			rxq->rxcsum++;
-		}
-
-		if (cpl->vlan_ex) {
-			m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan);
-			m0->m_flags |= M_VLANTAG;
-			rxq->vlan_extraction++;
-		}
-
-		i = 1;	/* # of fl sdesc used */
-		sd = sd_next;
-		if (__predict_false(++fl->cidx == fl->cap))
+		sd++;
+		if (__predict_false(++fl->cidx == fl->cap)) {
+			sd = fl->sdesc;
 			fl->cidx = 0;
+		}
 
-		len -= m0->m_len;
-		m = m0;
-		while (len) {
-			i++;
-
-			sd_next = sd + 1;
-			if (__predict_false(fl->cidx + 1 == fl->cap))
-				sd_next = fl->sdesc;
-			prefetch(sd_next->m);
-			prefetch(sd_next->cl);
-
-			m->m_next = sd->m;
-			sd->m = NULL;	/* consumed */
-			m = m->m_next;
-
-			bus_dmamap_sync(fl->tag[sd->tag_idx], sd->map,
-			    BUS_DMASYNC_POSTREAD);
-
-			m_init(m, NULL, 0, M_NOWAIT, MT_DATA, 0);
-			if (len <= MLEN) {
-				bcopy(sd->cl, mtod(m, caddr_t), len);
-				m->m_len = len;
-			} else {
-				bus_dmamap_unload(fl->tag[sd->tag_idx],
-				    sd->map);
-				m_cljset(m, sd->cl, FL_BUF_TYPE(sd->tag_idx));
-				sd->cl = NULL;	/* consumed */
-				m->m_len = min(len, FL_BUF_SIZE(sd->tag_idx));
-			}
+		len -= m->m_len;
+		nbuf++;
+	}
 
-			i++;
-			sd = sd_next;
-			if (__predict_false(++fl->cidx == fl->cap))
-				fl->cidx = 0;
+	(*fl_bufs_used) += nbuf;
 
-			len -= m->m_len;
-		}
+	return (m0);
+}
 
+static int
+t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
+{
+	struct sge_rxq *rxq = (void *)iq;
+	struct ifnet *ifp = rxq->ifp;
+	const struct cpl_rx_pkt *cpl = (const void *)(rss + 1);
 #ifdef INET
-		if (cpl->l2info & htobe32(F_RXF_LRO) &&
-		    rxq->flags & RXQ_LRO_ENABLED &&
-		    tcp_lro_rx(lro, m0, 0) == 0) {
-			/* queued for LRO */
-		} else
+	struct lro_ctrl *lro = &rxq->lro;
 #endif
-		ifp->if_input(ifp, m0);
 
-		FL_LOCK(fl);
-		fl->needed += i;
-		if (fl->needed >= 32)
-			refill_fl(sc, fl, 64, 32);
-		FL_UNLOCK(fl);
+	KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__,
+	    rss->opcode));
 
-		if (++ndescs > 32) {
-			t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS),
-			    V_CIDXINC(ndescs) |
-			    V_INGRESSQID((u32)iq->cntxt_id) |
-			    V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
-			ndescs = 0;
-		}
+	m0->m_pkthdr.len -= FL_PKTSHIFT;
+	m0->m_len -= FL_PKTSHIFT;
+	m0->m_data += FL_PKTSHIFT;
+
+	m0->m_pkthdr.rcvif = ifp;
+	m0->m_flags |= M_FLOWID;
+	m0->m_pkthdr.flowid = rss->hash_val;
 
-		iq_next(iq);
+	if (cpl->csum_calc && !cpl->err_vec &&
+	    ifp->if_capenable & IFCAP_RXCSUM) {
+		m0->m_pkthdr.csum_flags |= (CSUM_IP_CHECKED |
+		    CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
+		if (cpl->ip_frag)
+			m0->m_pkthdr.csum_data = be16toh(cpl->csum);
+		else
+			m0->m_pkthdr.csum_data = 0xffff;
+		rxq->rxcsum++;
 	}
 
-#ifdef INET
-	while (!SLIST_EMPTY(&lro->lro_active)) {
-		l = SLIST_FIRST(&lro->lro_active);
-		SLIST_REMOVE_HEAD(&lro->lro_active, next);
-		tcp_lro_flush(lro, l);
+	if (cpl->vlan_ex) {
+		m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan);
+		m0->m_flags |= M_VLANTAG;
+		rxq->vlan_extraction++;
 	}
-#endif
 
-	t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndescs) |
-	    V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_next));
+#ifdef INET
+	if (cpl->l2info & htobe32(F_RXF_LRO) &&
+	    iq->flags & IQ_LRO_ENABLED &&
+	    tcp_lro_rx(lro, m0, 0) == 0) {
+		/* queued for LRO */
+	} else
+#endif
+	ifp->if_input(ifp, m0);
 
-	FL_LOCK(fl);
-	if (fl->needed >= 32)
-		refill_fl(sc, fl, 128, 8);
-	FL_UNLOCK(fl);
+	return (0);
 }
 
 int
 t4_mgmt_tx(struct adapter *sc, struct mbuf *m)
 {
-	return ctrl_tx(sc, &sc->sge.ctrlq[0], m);
+	return t4_wrq_tx(sc, &sc->sge.mgmtq, m);
+}
+
+/*
+ * Doesn't fail.  Holds on to work requests it can't send right away.
+ */
+int
+t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct mbuf *m0)
+{
+	struct sge_eq *eq = &wrq->eq;
+	int can_reclaim;
+	caddr_t dst;
+	struct mbuf *wr, *next;
+
+	TXQ_LOCK_ASSERT_OWNED(wrq);
+	KASSERT((eq->flags & EQ_TYPEMASK) == EQ_OFLD ||
+	    (eq->flags & EQ_TYPEMASK) == EQ_CTRL,
+	    ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK));
+
+	if (__predict_true(m0 != NULL)) {
+		if (wrq->head)
+			wrq->tail->m_nextpkt = m0;
+		else
+			wrq->head = m0;
+		while (m0->m_nextpkt)
+			m0 = m0->m_nextpkt;
+		wrq->tail = m0;
+	}
+
+	can_reclaim = reclaimable(eq);
+	if (__predict_false(eq->flags & EQ_STALLED)) {
+		if (can_reclaim < tx_resume_threshold(eq))
+			return (0);
+		eq->flags &= ~EQ_STALLED;
+		eq->unstalled++;
+	}
+	eq->cidx += can_reclaim;
+	eq->avail += can_reclaim;
+	if (__predict_false(eq->cidx >= eq->cap))
+		eq->cidx -= eq->cap;
+
+	for (wr = wrq->head; wr; wr = next) {
+		int ndesc;
+		struct mbuf *m;
+
+		next = wr->m_nextpkt;
+		wr->m_nextpkt = NULL;
+
+		M_ASSERTPKTHDR(wr);
+		KASSERT(wr->m_pkthdr.len > 0 && (wr->m_pkthdr.len & 0x7) == 0,
+		    ("%s: work request len %d.", __func__, wr->m_pkthdr.len));
+
+		if (wr->m_pkthdr.len > SGE_MAX_WR_LEN) {
+#ifdef INVARIANTS
+			panic("%s: oversized work request", __func__);
+#else
+			log(LOG_ERR, "%s: %s work request too long (%d)",
+			    device_get_nameunit(sc->dev), __func__,
+			    wr->m_pkthdr.len);
+			m_freem(wr);
+			continue;
+#endif
+		}
+
+		ndesc = howmany(wr->m_pkthdr.len, EQ_ESIZE);
+		if (eq->avail < ndesc) {
+			wr->m_nextpkt = next;
+			wrq->no_desc++;
+			break;
+		}
+
+		dst = (void *)&eq->desc[eq->pidx];
+		for (m = wr; m; m = m->m_next)
+			copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
+
+		eq->pidx += ndesc;
+		eq->avail -= ndesc;
+		if (__predict_false(eq->pidx >= eq->cap))
+			eq->pidx -= eq->cap;
+
+		eq->pending += ndesc;
+		if (eq->pending > 16)
+			ring_eq_db(sc, eq);
+
+		wrq->tx_wrs++;
+		m_freem(wr);
+
+		if (eq->avail < 8) {
+			can_reclaim = reclaimable(eq);
+			eq->cidx += can_reclaim;
+			eq->avail += can_reclaim;
+			if (__predict_false(eq->cidx >= eq->cap))
+				eq->cidx -= eq->cap;
+		}
+	}
+
+	if (eq->pending)
+		ring_eq_db(sc, eq);
+
+	if (wr == NULL)
+		wrq->head = wrq->tail = NULL;
+	else {
+		wrq->head = wr;
+
+		KASSERT(wrq->tail->m_nextpkt == NULL,
+		    ("%s: wrq->tail grew a tail of its own", __func__));
+
+		eq->flags |= EQ_STALLED;
+		if (callout_pending(&eq->tx_callout) == 0)
+			callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq);
+	}
+
+	return (0);
 }
 
 /* Per-packet header in a coalesced tx WR, before the SGL starts (in flits) */
@@ -852,6 +1233,8 @@ t4_eth_tx(struct ifnet *ifp, struct sge_txq *txq, struct mbuf *m)
 
 	TXQ_LOCK_ASSERT_OWNED(txq);
 	KASSERT(m, ("%s: called with nothing to do.", __func__));
+	KASSERT((eq->flags & EQ_TYPEMASK) == EQ_ETH,
+	    ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK));
 
 	prefetch(&eq->desc[eq->pidx]);
 	prefetch(&txq->sdesc[eq->pidx]);
@@ -859,8 +1242,25 @@ t4_eth_tx(struct ifnet *ifp, struct sge_txq *txq, struct mbuf *m)
 	txpkts.npkt = 0;/* indicates there's nothing in txpkts */
 	coalescing = 0;
 
-	if (eq->avail < 8)
-		reclaim_tx_descs(txq, 0, 8);
+	can_reclaim = reclaimable(eq);
+	if (__predict_false(eq->flags & EQ_STALLED)) {
+		if (can_reclaim < tx_resume_threshold(eq)) {
+			txq->m = m;
+			return (0);
+		}
+		eq->flags &= ~EQ_STALLED;
+		eq->unstalled++;
+	}
+
+	if (__predict_false(eq->flags & EQ_DOOMED)) {
+		m_freem(m);
+		while ((m = buf_ring_dequeue_sc(txq->br)) != NULL)
+			m_freem(m);
+		return (ENETDOWN);
+	}
+
+	if (eq->avail < 8 && can_reclaim)
+		reclaim_tx_descs(txq, can_reclaim, 32);
 
 	for (; m; m = next ? next : drbr_dequeue(ifp, br)) {
 
@@ -938,15 +1338,13 @@ t4_eth_tx(struct ifnet *ifp, struct sge_txq *txq, struct mbuf *m)
 		ETHER_BPF_MTAP(ifp, m);
 		if (sgl.nsegs == 0)
 			m_freem(m);
-
 doorbell:
-		/* Fewer and fewer doorbells as the queue fills up */
-		if (eq->pending >= (1 << (fls(eq->qsize - eq->avail) / 2)))
+		if (eq->pending >= 64)
 		    ring_eq_db(sc, eq);
 
 		can_reclaim = reclaimable(eq);
 		if (can_reclaim >= 32)
-			reclaim_tx_descs(txq, can_reclaim, 32);
+			reclaim_tx_descs(txq, can_reclaim, 64);
 	}
 
 	if (txpkts.npkt > 0)
@@ -957,14 +1355,17 @@ doorbell:
 	 * This can happen when we're short of tx descriptors (no_desc) or maybe
 	 * even DMA maps (no_dmamap).  Either way, a credit flush and reclaim
 	 * will get things going again.
-	 *
-	 * If eq->avail is already 0 we know a credit flush was requested in the
-	 * WR that reduced it to 0 so we don't need another flush (we don't have
-	 * any descriptor for a flush WR anyway, duh).
 	 */
-	if (m && eq->avail > 0 && !(eq->flags & EQ_CRFLUSHED)) {
+	if (m && !(eq->flags & EQ_CRFLUSHED)) {
 		struct tx_sdesc *txsd = &txq->sdesc[eq->pidx];
 
+		/*
+		 * If EQ_CRFLUSHED is not set then we know we have at least one
+		 * available descriptor because any WR that reduces eq->avail to
+		 * 0 also sets EQ_CRFLUSHED.
+		 */
+		KASSERT(eq->avail > 0, ("%s: no space for eqflush.", __func__));
+
 		txsd->desc_used = 1;
 		txsd->credits = 0;
 		write_eqflush_wr(eq);
@@ -974,9 +1375,10 @@ doorbell:
 	if (eq->pending)
 		ring_eq_db(sc, eq);
 
-	can_reclaim = reclaimable(eq);
-	if (can_reclaim >= 32)
-		reclaim_tx_descs(txq, can_reclaim, 128);
+	reclaim_tx_descs(txq, 0, 128);
+
+	if (eq->flags & EQ_STALLED && callout_pending(&eq->tx_callout) == 0)
+		callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq);
 
 	return (0);
 }
@@ -987,24 +1389,29 @@ t4_update_fl_bufsize(struct ifnet *ifp)
 	struct port_info *pi = ifp->if_softc;
 	struct sge_rxq *rxq;
 	struct sge_fl *fl;
-	int i;
+	int i, bufsize;
 
+	/* large enough for a frame even when VLAN extraction is disabled */
+	bufsize = FL_PKTSHIFT + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
+	    ifp->if_mtu;
 	for_each_rxq(pi, i, rxq) {
 		fl = &rxq->fl;
 
 		FL_LOCK(fl);
-		set_fl_tag_idx(fl, ifp->if_mtu);
+		set_fl_tag_idx(fl, bufsize);
 		FL_UNLOCK(fl);
 	}
 }
 
-/*
- * A non-NULL handler indicates this iq will not receive direct interrupts, the
- * handler will be invoked by an interrupt queue.
- */
+int
+can_resume_tx(struct sge_eq *eq)
+{
+	return (reclaimable(eq) >= tx_resume_threshold(eq));
+}
+
 static inline void
 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
-    int qsize, int esize, iq_intr_handler_t *handler, char *name)
+    int qsize, int esize, char *name)
 {
 	KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS,
 	    ("%s: bad tmr_idx %d", __func__, tmr_idx));
@@ -1018,22 +1425,32 @@ init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
 	iq->intr_pktc_idx = pktc_idx;
 	iq->qsize = roundup(qsize, 16);		/* See FW_IQ_CMD/iqsize */
 	iq->esize = max(esize, 16);		/* See FW_IQ_CMD/iqesize */
-	iq->handler = handler;
 	strlcpy(iq->lockname, name, sizeof(iq->lockname));
 }
 
 static inline void
-init_fl(struct sge_fl *fl, int qsize, char *name)
+init_fl(struct sge_fl *fl, int qsize, int bufsize, char *name)
 {
 	fl->qsize = qsize;
 	strlcpy(fl->lockname, name, sizeof(fl->lockname));
+	set_fl_tag_idx(fl, bufsize);
 }
 
 static inline void
-init_eq(struct sge_eq *eq, int qsize, char *name)
+init_eq(struct sge_eq *eq, int eqtype, int qsize, uint8_t tx_chan,
+    uint16_t iqid, char *name)
 {
+	KASSERT(tx_chan < NCHAN, ("%s: bad tx channel %d", __func__, tx_chan));
+	KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype));
+
+	eq->flags = eqtype & EQ_TYPEMASK;
+	eq->tx_chan = tx_chan;
+	eq->iqid = iqid;
 	eq->qsize = qsize;
 	strlcpy(eq->lockname, name, sizeof(eq->lockname));
+
+	TASK_INIT(&eq->tx_task, 0, t4_tx_task, eq);
+	callout_init(&eq->tx_callout, CALLOUT_MPSAFE);
 }
 
 static int
@@ -1090,9 +1507,9 @@ free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map,
  * Returns errno on failure.  Resources allocated up to that point may still be
  * allocated.  Caller is responsible for cleanup in case this function fails.
  *
- * If the ingress queue will take interrupts directly (iq->handler == NULL) then
+ * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then
  * the intr_idx specifies the vector, starting from 0.  Otherwise it specifies
- * the index of the interrupt queue to which its interrupts will be forwarded.
+ * the abs_id of the ingress queue to which its interrupts should be forwarded.
  */
 static int
 alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl,
@@ -1122,16 +1539,12 @@ alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl,
 	if (iq == &sc->sge.fwq)
 		v |= F_FW_IQ_CMD_IQASYNCH;
 
-	if (iq->handler) {
-		KASSERT(intr_idx < NINTRQ(sc),
-		    ("%s: invalid indirect intr_idx %d", __func__, intr_idx));
-		v |= F_FW_IQ_CMD_IQANDST;
-		v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.intrq[intr_idx].abs_id);
-	} else {
+	if (iq->flags & IQ_INTR) {
 		KASSERT(intr_idx < sc->intr_count,
 		    ("%s: invalid direct intr_idx %d", __func__, intr_idx));
-		v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx);
-	}
+	} else
+		v |= F_FW_IQ_CMD_IQANDST;
+	v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx);
 
 	c.type_to_iqandstindex = htobe32(v |
 	    V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
@@ -1176,7 +1589,6 @@ alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl,
 		/* Allocate space for one software descriptor per buffer. */
 		fl->cap = (fl->qsize - SPG_LEN / RX_FL_ESIZE) * 8;
 		FL_LOCK(fl);
-		set_fl_tag_idx(fl, pi->ifp->if_mtu);
 		rc = alloc_fl_sdesc(fl);
 		FL_UNLOCK(fl);
 		if (rc != 0) {
@@ -1186,8 +1598,9 @@ alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl,
 			return (rc);
 		}
 		fl->needed = fl->cap;
+		fl->lowat = roundup(sc->sge.fl_starve_threshold, 8);
 
-		c.iqns_to_fl0congen =
+		c.iqns_to_fl0congen |=
 		    htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
 			F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
 			F_FW_IQ_CMD_FL0PADEN);
@@ -1217,12 +1630,13 @@ alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl,
 	iq->intr_next = iq->intr_params;
 	iq->cntxt_id = be16toh(c.iqid);
 	iq->abs_id = be16toh(c.physiqid);
-	iq->flags |= (IQ_ALLOCATED | IQ_STARTED);
+	iq->flags |= IQ_ALLOCATED;
 
 	cntxt_id = iq->cntxt_id - sc->sge.iq_start;
-	KASSERT(cntxt_id < sc->sge.niq,
-	    ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__,
-	    cntxt_id, sc->sge.niq - 1));
+	if (cntxt_id >= sc->sge.niq) {
+		panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__,
+		    cntxt_id, sc->sge.niq - 1);
+	}
 	sc->sge.iqmap[cntxt_id] = iq;
 
 	if (fl) {
@@ -1230,29 +1644,28 @@ alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl,
 		fl->pidx = fl->cidx = 0;
 
 		cntxt_id = fl->cntxt_id - sc->sge.eq_start;
-		KASSERT(cntxt_id < sc->sge.neq,
-		    ("%s: fl->cntxt_id (%d) more than the max (%d)", __func__,
-		    cntxt_id, sc->sge.neq - 1));
+		if (cntxt_id >= sc->sge.neq) {
+			panic("%s: fl->cntxt_id (%d) more than the max (%d)",
+			    __func__, cntxt_id, sc->sge.neq - 1);
+		}
 		sc->sge.eqmap[cntxt_id] = (void *)fl;
 
 		FL_LOCK(fl);
-		/* Just enough to make sure it doesn't starve right away. */
-		refill_fl(sc, fl, roundup(sc->sge.fl_starve_threshold, 8), 8);
+		/* Enough to make sure the SGE doesn't think it's starved */
+		refill_fl(sc, fl, fl->lowat);
 		FL_UNLOCK(fl);
+
+		iq->flags |= IQ_HAS_FL;
 	}
 
 	/* Enable IQ interrupts */
-	atomic_store_rel_32(&iq->state, IQS_IDLE);
+	atomic_store_rel_int(&iq->state, IQS_IDLE);
 	t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_SEINTARM(iq->intr_params) |
 	    V_INGRESSQID(iq->cntxt_id));
 
 	return (0);
 }
 
-/*
- * This can be called with the iq/fl in any state - fully allocated and
- * functional, partially allocated, even all-zeroed out.
- */
 static int
 free_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl)
 {
@@ -1265,23 +1678,7 @@ free_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl)
 
 	dev = pi ? pi->dev : sc->dev;
 
-	if (iq->flags & IQ_STARTED) {
-		rc = -t4_iq_start_stop(sc, sc->mbox, 0, sc->pf, 0,
-		    iq->cntxt_id, fl ? fl->cntxt_id : 0xffff, 0xffff);
-		if (rc != 0) {
-			device_printf(dev,
-			    "failed to stop queue %p: %d\n", iq, rc);
-			return (rc);
-		}
-		iq->flags &= ~IQ_STARTED;
-
-		/* Synchronize with the interrupt handler */
-		while (!atomic_cmpset_32(&iq->state, IQS_IDLE, IQS_DISABLED))
-			pause("iqfree", hz / 1000);
-	}
-
 	if (iq->flags & IQ_ALLOCATED) {
-
 		rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0,
 		    FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id,
 		    fl ? fl->cntxt_id : 0xffff, 0xffff);
@@ -1322,76 +1719,84 @@ free_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl)
 }
 
 static int
-alloc_intrq(struct adapter *sc, int port_idx, int intrq_idx, int intr_idx)
+alloc_fwq(struct adapter *sc)
 {
-	int rc;
-	struct sysctl_oid *oid;
-	struct sysctl_oid_list *children;
+	int rc, intr_idx;
+	struct sge_iq *fwq = &sc->sge.fwq;
 	char name[16];
-	struct sge_iq *intrq = &sc->sge.intrq[intrq_idx];
+	struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
+	struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
 
-	rc = alloc_iq_fl(sc->port[port_idx], intrq, NULL, intr_idx, -1);
-	if (rc != 0)
+	snprintf(name, sizeof(name), "%s fwq", device_get_nameunit(sc->dev));
+	init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE, FW_IQ_ESIZE, name);
+	fwq->flags |= IQ_INTR;	/* always */
+	intr_idx = sc->intr_count > 1 ? 1 : 0;
+	rc = alloc_iq_fl(sc->port[0], fwq, NULL, intr_idx, -1);
+	if (rc != 0) {
+		device_printf(sc->dev,
+		    "failed to create firmware event queue: %d\n", rc);
 		return (rc);
+	}
 
-	children = SYSCTL_CHILDREN(sc->oid_intrq);
-
-	snprintf(name, sizeof(name), "%d", intrq_idx);
-	oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, name, CTLFLAG_RD,
-	    NULL, "interrupt queue");
+	oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD,
+	    NULL, "firmware event queue");
 	children = SYSCTL_CHILDREN(oid);
 
+	SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id",
+	    CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I",
+	    "absolute id of the queue");
+	SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id",
+	    CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I",
+	    "SGE context id of the queue");
 	SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx",
-	    CTLTYPE_INT | CTLFLAG_RD, &intrq->cidx, 0, sysctl_uint16, "I",
+	    CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I",
 	    "consumer index");
 
-	return (rc);
+	return (0);
 }
 
 static int
-free_intrq(struct sge_iq *iq)
+free_fwq(struct adapter *sc)
 {
-	return free_iq_fl(NULL, iq, NULL);
-
+	return free_iq_fl(NULL, &sc->sge.fwq, NULL);
 }
 
 static int
-alloc_fwq(struct adapter *sc, int intr_idx)
+alloc_mgmtq(struct adapter *sc)
 {
 	int rc;
-	struct sysctl_oid_list *children;
-	struct sge_iq *fwq = &sc->sge.fwq;
-
-	rc = alloc_iq_fl(sc->port[0], fwq, NULL, intr_idx, -1);
-	if (rc != 0)
-		return (rc);
+	struct sge_wrq *mgmtq = &sc->sge.mgmtq;
+	char name[16];
+	struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
+	struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
 
-	children = SYSCTL_CHILDREN(sc->oid_fwq);
+	oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD,
+	    NULL, "management queue");
 
-	SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id",
-	    CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I",
-	    "absolute id of the queue");
-	SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id",
-	    CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I",
-	    "SGE context id of the queue");
-	SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx",
-	    CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I",
-	    "consumer index");
+	snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev));
+	init_eq(&mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan,
+	    sc->sge.fwq.cntxt_id, name);
+	rc = alloc_wrq(sc, NULL, mgmtq, oid);
+	if (rc != 0) {
+		device_printf(sc->dev,
+		    "failed to create management queue: %d\n", rc);
+		return (rc);
+	}
 
-	return (rc);
+	return (0);
 }
 
 static int
-free_fwq(struct sge_iq *iq)
+free_mgmtq(struct adapter *sc)
 {
-	return free_iq_fl(NULL, iq, NULL);
+	return free_wrq(sc, &sc->sge.mgmtq);
 }
 
 static int
-alloc_rxq(struct port_info *pi, struct sge_rxq *rxq, int intr_idx, int idx)
+alloc_rxq(struct port_info *pi, struct sge_rxq *rxq, int intr_idx, int idx,
+    struct sysctl_oid *oid)
 {
 	int rc;
-	struct sysctl_oid *oid;
 	struct sysctl_oid_list *children;
 	char name[16];
 
@@ -1400,7 +1805,7 @@ alloc_rxq(struct port_info *pi, struct sge_rxq *rxq, int intr_idx, int idx)
 		return (rc);
 
 	FL_LOCK(&rxq->fl);
-	refill_fl(pi->adapter, &rxq->fl, rxq->fl.needed / 8, 8);
+	refill_fl(pi->adapter, &rxq->fl, rxq->fl.needed / 8);
 	FL_UNLOCK(&rxq->fl);
 
 #ifdef INET
@@ -1410,11 +1815,11 @@ alloc_rxq(struct port_info *pi, struct sge_rxq *rxq, int intr_idx, int idx)
 	rxq->lro.ifp = pi->ifp; /* also indicates LRO init'ed */
 
 	if (pi->ifp->if_capenable & IFCAP_LRO)
-		rxq->flags |= RXQ_LRO_ENABLED;
+		rxq->iq.flags |= IQ_LRO_ENABLED;
 #endif
 	rxq->ifp = pi->ifp;
 
-	children = SYSCTL_CHILDREN(pi->oid_rxq);
+	children = SYSCTL_CHILDREN(oid);
 
 	snprintf(name, sizeof(name), "%d", idx);
 	oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
@@ -1477,32 +1882,71 @@ free_rxq(struct port_info *pi, struct sge_rxq *rxq)
 	return (rc);
 }
 
+#ifndef TCP_OFFLOAD_DISABLE
 static int
-alloc_ctrlq(struct adapter *sc, struct sge_ctrlq *ctrlq, int idx)
+alloc_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq,
+    int intr_idx, int idx, struct sysctl_oid *oid)
 {
-	int rc, cntxt_id;
-	size_t len;
-	struct fw_eq_ctrl_cmd c;
-	struct sge_eq *eq = &ctrlq->eq;
-	char name[16];
-	struct sysctl_oid *oid;
+	int rc;
 	struct sysctl_oid_list *children;
+	char name[16];
 
-	mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
-
-	len = eq->qsize * CTRL_EQ_ESIZE;
-	rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map,
-	    &eq->ba, (void **)&eq->desc);
-	if (rc)
+	rc = alloc_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx,
+	    1 << pi->tx_chan);
+	if (rc != 0)
 		return (rc);
 
-	eq->cap = eq->qsize - SPG_LEN / CTRL_EQ_ESIZE;
-	eq->spg = (void *)&eq->desc[eq->cap];
-	eq->avail = eq->cap - 1;	/* one less to avoid cidx = pidx */
-	if (sc->flags & INTR_SHARED)
-		eq->iqid = sc->sge.intrq[idx % NINTRQ(sc)].cntxt_id;
-	else
-		eq->iqid = sc->sge.intrq[sc->port[idx]->first_rxq].cntxt_id;
+	children = SYSCTL_CHILDREN(oid);
+
+	snprintf(name, sizeof(name), "%d", idx);
+	oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
+	    NULL, "rx queue");
+	children = SYSCTL_CHILDREN(oid);
+
+	SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id",
+	    CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16,
+	    "I", "absolute id of the queue");
+	SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id",
+	    CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cntxt_id, 0, sysctl_uint16,
+	    "I", "SGE context id of the queue");
+	SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx",
+	    CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I",
+	    "consumer index");
+
+	children = SYSCTL_CHILDREN(oid);
+	oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "fl", CTLFLAG_RD,
+	    NULL, "freelist");
+	children = SYSCTL_CHILDREN(oid);
+
+	SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id",
+	    CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->fl.cntxt_id, 0, sysctl_uint16,
+	    "I", "SGE context id of the queue");
+	SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
+	    &ofld_rxq->fl.cidx, 0, "consumer index");
+	SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "pidx", CTLFLAG_RD,
+	    &ofld_rxq->fl.pidx, 0, "producer index");
+
+	return (rc);
+}
+
+static int
+free_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq)
+{
+	int rc;
+
+	rc = free_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl);
+	if (rc == 0)
+		bzero(ofld_rxq, sizeof(*ofld_rxq));
+
+	return (rc);
+}
+#endif
+
+static int
+ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
+{
+	int rc, cntxt_id;
+	struct fw_eq_ctrl_cmd c;
 
 	bzero(&c, sizeof(c));
 
@@ -1515,7 +1959,7 @@ alloc_ctrlq(struct adapter *sc, struct sge_ctrlq *ctrlq, int idx)
 	c.physeqid_pkd = htobe32(0);
 	c.fetchszm_to_iqid =
 	    htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
-		V_FW_EQ_CTRL_CMD_PCIECHN(sc->port[idx]->tx_chan) |
+		V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
 		F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
 	c.dcaen_to_eqsize =
 	    htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
@@ -1527,51 +1971,191 @@ alloc_ctrlq(struct adapter *sc, struct sge_ctrlq *ctrlq, int idx)
 	rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
 	if (rc != 0) {
 		device_printf(sc->dev,
-		    "failed to create control queue %d: %d\n", idx, rc);
+		    "failed to create control queue %d: %d\n", eq->tx_chan, rc);
 		return (rc);
 	}
+	eq->flags |= EQ_ALLOCATED;
 
-	eq->pidx = eq->cidx = 0;
 	eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid));
-	eq->flags |= (EQ_ALLOCATED | EQ_STARTED);
+	cntxt_id = eq->cntxt_id - sc->sge.eq_start;
+	if (cntxt_id >= sc->sge.neq)
+	    panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
+		cntxt_id, sc->sge.neq - 1);
+	sc->sge.eqmap[cntxt_id] = eq;
+
+	return (rc);
+}
+
+static int
+eth_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq)
+{
+	int rc, cntxt_id;
+	struct fw_eq_eth_cmd c;
+
+	bzero(&c, sizeof(c));
 
+	c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
+	    F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
+	    V_FW_EQ_ETH_CMD_VFN(0));
+	c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
+	    F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
+	c.viid_pkd = htobe32(V_FW_EQ_ETH_CMD_VIID(pi->viid));
+	c.fetchszm_to_iqid =
+	    htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
+		V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
+		V_FW_EQ_ETH_CMD_IQID(eq->iqid));
+	c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
+		      V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
+		      V_FW_EQ_ETH_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) |
+		      V_FW_EQ_ETH_CMD_EQSIZE(eq->qsize));
+	c.eqaddr = htobe64(eq->ba);
+
+	rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
+	if (rc != 0) {
+		device_printf(pi->dev,
+		    "failed to create Ethernet egress queue: %d\n", rc);
+		return (rc);
+	}
+	eq->flags |= EQ_ALLOCATED;
+
+	eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
 	cntxt_id = eq->cntxt_id - sc->sge.eq_start;
-	KASSERT(cntxt_id < sc->sge.neq,
-	    ("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
-	    cntxt_id, sc->sge.neq - 1));
+	if (cntxt_id >= sc->sge.neq)
+	    panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
+		cntxt_id, sc->sge.neq - 1);
 	sc->sge.eqmap[cntxt_id] = eq;
 
-	children = SYSCTL_CHILDREN(sc->oid_ctrlq);
+	return (rc);
+}
 
-	snprintf(name, sizeof(name), "%d", idx);
-	oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, name, CTLFLAG_RD,
-	    NULL, "ctrl queue");
-	children = SYSCTL_CHILDREN(oid);
+#ifndef TCP_OFFLOAD_DISABLE
+static int
+ofld_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq)
+{
+	int rc, cntxt_id;
+	struct fw_eq_ofld_cmd c;
 
-	SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "pidx",
-	    CTLTYPE_INT | CTLFLAG_RD, &ctrlq->eq.pidx, 0, sysctl_uint16, "I",
-	    "producer index");
-	SYSCTL_ADD_UINT(&sc->ctx, children, OID_AUTO, "no_desc", CTLFLAG_RD,
-	    &ctrlq->no_desc, 0,
-	    "# of times ctrlq ran out of hardware descriptors");
+	bzero(&c, sizeof(c));
+
+	c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST |
+	    F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) |
+	    V_FW_EQ_OFLD_CMD_VFN(0));
+	c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC |
+	    F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
+	c.fetchszm_to_iqid =
+		htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
+		    V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
+		    F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
+	c.dcaen_to_eqsize =
+	    htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
+		V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
+		V_FW_EQ_OFLD_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) |
+		V_FW_EQ_OFLD_CMD_EQSIZE(eq->qsize));
+	c.eqaddr = htobe64(eq->ba);
+
+	rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
+	if (rc != 0) {
+		device_printf(pi->dev,
+		    "failed to create egress queue for TCP offload: %d\n", rc);
+		return (rc);
+	}
+	eq->flags |= EQ_ALLOCATED;
+
+	eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd));
+	cntxt_id = eq->cntxt_id - sc->sge.eq_start;
+	if (cntxt_id >= sc->sge.neq)
+	    panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
+		cntxt_id, sc->sge.neq - 1);
+	sc->sge.eqmap[cntxt_id] = eq;
+
+	return (rc);
+}
+#endif
+
+static int
+alloc_eq(struct adapter *sc, struct port_info *pi, struct sge_eq *eq)
+{
+	int rc;
+	size_t len;
+
+	mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
+
+	len = eq->qsize * EQ_ESIZE;
+	rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map,
+	    &eq->ba, (void **)&eq->desc);
+	if (rc)
+		return (rc);
+
+	eq->cap = eq->qsize - SPG_LEN / EQ_ESIZE;
+	eq->spg = (void *)&eq->desc[eq->cap];
+	eq->avail = eq->cap - 1;	/* one less to avoid cidx = pidx */
+	eq->pidx = eq->cidx = 0;
+
+	switch (eq->flags & EQ_TYPEMASK) {
+	case EQ_CTRL:
+		rc = ctrl_eq_alloc(sc, eq);
+		break;
+
+	case EQ_ETH:
+		rc = eth_eq_alloc(sc, pi, eq);
+		break;
+
+#ifndef TCP_OFFLOAD_DISABLE
+	case EQ_OFLD:
+		rc = ofld_eq_alloc(sc, pi, eq);
+		break;
+#endif
+
+	default:
+		panic("%s: invalid eq type %d.", __func__,
+		    eq->flags & EQ_TYPEMASK);
+	}
+	if (rc != 0) {
+		device_printf(sc->dev,
+		    "failed to allocate egress queue(%d): %d",
+		    eq->flags & EQ_TYPEMASK, rc);
+	}
+
+	eq->tx_callout.c_cpu = eq->cntxt_id % mp_ncpus;
 
 	return (rc);
 }
 
 static int
-free_ctrlq(struct adapter *sc, struct sge_ctrlq *ctrlq)
+free_eq(struct adapter *sc, struct sge_eq *eq)
 {
 	int rc;
-	struct sge_eq *eq = &ctrlq->eq;
 
-	if (eq->flags & (EQ_ALLOCATED | EQ_STARTED)) {
-		rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id);
+	if (eq->flags & EQ_ALLOCATED) {
+		switch (eq->flags & EQ_TYPEMASK) {
+		case EQ_CTRL:
+			rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0,
+			    eq->cntxt_id);
+			break;
+
+		case EQ_ETH:
+			rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0,
+			    eq->cntxt_id);
+			break;
+
+#ifndef TCP_OFFLOAD_DISABLE
+		case EQ_OFLD:
+			rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0,
+			    eq->cntxt_id);
+			break;
+#endif
+
+		default:
+			panic("%s: invalid eq type %d.", __func__,
+			    eq->flags & EQ_TYPEMASK);
+		}
 		if (rc != 0) {
 			device_printf(sc->dev,
-			    "failed to free ctrl queue %p: %d\n", eq, rc);
+			    "failed to free egress queue (%d): %d\n",
+			    eq->flags & EQ_TYPEMASK, rc);
 			return (rc);
 		}
-		eq->flags &= ~(EQ_ALLOCATED | EQ_STARTED);
+		eq->flags &= ~EQ_ALLOCATED;
 	}
 
 	free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc);
@@ -1579,47 +2163,77 @@ free_ctrlq(struct adapter *sc, struct sge_ctrlq *ctrlq)
 	if (mtx_initialized(&eq->eq_lock))
 		mtx_destroy(&eq->eq_lock);
 
-	bzero(ctrlq, sizeof(*ctrlq));
+	bzero(eq, sizeof(*eq));
 	return (0);
 }
 
 static int
-alloc_txq(struct port_info *pi, struct sge_txq *txq, int idx)
+alloc_wrq(struct adapter *sc, struct port_info *pi, struct sge_wrq *wrq,
+    struct sysctl_oid *oid)
 {
-	int rc, cntxt_id;
-	size_t len;
+	int rc;
+	struct sysctl_ctx_list *ctx = pi ? &pi->ctx : &sc->ctx;
+	struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
+
+	rc = alloc_eq(sc, pi, &wrq->eq);
+	if (rc)
+		return (rc);
+
+	wrq->adapter = sc;
+
+	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
+	    &wrq->eq.cntxt_id, 0, "SGE context id of the queue");
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
+	    CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I",
+	    "consumer index");
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx",
+	    CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I",
+	    "producer index");
+	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs", CTLFLAG_RD,
+	    &wrq->tx_wrs, "# of work requests");
+	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "no_desc", CTLFLAG_RD,
+	    &wrq->no_desc, 0,
+	    "# of times queue ran out of hardware descriptors");
+	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "unstalled", CTLFLAG_RD,
+	    &wrq->eq.unstalled, 0, "# of times queue recovered after stall");
+
+
+	return (rc);
+}
+
+static int
+free_wrq(struct adapter *sc, struct sge_wrq *wrq)
+{
+	int rc;
+
+	rc = free_eq(sc, &wrq->eq);
+	if (rc)
+		return (rc);
+
+	bzero(wrq, sizeof(*wrq));
+	return (0);
+}
+
+static int
+alloc_txq(struct port_info *pi, struct sge_txq *txq, int idx,
+    struct sysctl_oid *oid)
+{
+	int rc;
 	struct adapter *sc = pi->adapter;
-	struct fw_eq_eth_cmd c;
 	struct sge_eq *eq = &txq->eq;
 	char name[16];
-	struct sysctl_oid *oid;
-	struct sysctl_oid_list *children;
-	struct sge_iq *intrq;
-
-	txq->ifp = pi->ifp;
-	TASK_INIT(&txq->resume_tx, 0, cxgbe_txq_start, txq);
-
-	mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
+	struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
 
-	len = eq->qsize * TX_EQ_ESIZE;
-	rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map,
-	    &eq->ba, (void **)&eq->desc);
+	rc = alloc_eq(sc, pi, eq);
 	if (rc)
 		return (rc);
 
-	eq->cap = eq->qsize - SPG_LEN / TX_EQ_ESIZE;
-	eq->spg = (void *)&eq->desc[eq->cap];
-	eq->avail = eq->cap - 1;	/* one less to avoid cidx = pidx */
+	txq->ifp = pi->ifp;
+
 	txq->sdesc = malloc(eq->cap * sizeof(struct tx_sdesc), M_CXGBE,
 	    M_ZERO | M_WAITOK);
 	txq->br = buf_ring_alloc(eq->qsize, M_CXGBE, M_WAITOK, &eq->eq_lock);
 
-	intrq = &sc->sge.intrq[0];
-	if (sc->flags & INTR_SHARED)
-		eq->iqid = intrq[(pi->first_txq + idx) % NINTRQ(sc)].cntxt_id;
-	else
-		eq->iqid = intrq[pi->first_rxq + (idx % pi->nrxq)].cntxt_id;
-
 	rc = bus_dma_tag_create(sc->dmat, 1, 0, BUS_SPACE_MAXADDR,
 	    BUS_SPACE_MAXADDR, NULL, NULL, 64 * 1024, TX_SGL_SEGS,
 	    BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, NULL, &txq->tx_tag);
@@ -1629,49 +2243,18 @@ alloc_txq(struct port_info *pi, struct sge_txq *txq, int idx)
 		return (rc);
 	}
 
-	rc = alloc_tx_maps(txq);
+	/*
+	 * We can stuff ~10 frames in an 8-descriptor txpkts WR (8 is the SGE
+	 * limit for any WR).  txq->no_dmamap events shouldn't occur if maps is
+	 * sized for the worst case.
+	 */
+	rc = t4_alloc_tx_maps(&txq->txmaps, txq->tx_tag, eq->qsize * 10 / 8,
+	    M_WAITOK);
 	if (rc != 0) {
 		device_printf(sc->dev, "failed to setup tx DMA maps: %d\n", rc);
 		return (rc);
 	}
 
-	bzero(&c, sizeof(c));
-
-	c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
-	    F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
-	    V_FW_EQ_ETH_CMD_VFN(0));
-	c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
-	    F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
-	c.viid_pkd = htobe32(V_FW_EQ_ETH_CMD_VIID(pi->viid));
-	c.fetchszm_to_iqid =
-	    htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
-		V_FW_EQ_ETH_CMD_PCIECHN(pi->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
-		V_FW_EQ_ETH_CMD_IQID(eq->iqid));
-	c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
-		      V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
-		      V_FW_EQ_ETH_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) |
-		      V_FW_EQ_ETH_CMD_EQSIZE(eq->qsize));
-	c.eqaddr = htobe64(eq->ba);
-
-	rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
-	if (rc != 0) {
-		device_printf(pi->dev,
-		    "failed to create egress queue: %d\n", rc);
-		return (rc);
-	}
-
-	eq->pidx = eq->cidx = 0;
-	eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
-	eq->flags |= (EQ_ALLOCATED | EQ_STARTED);
-
-	cntxt_id = eq->cntxt_id - sc->sge.eq_start;
-	KASSERT(cntxt_id < sc->sge.neq,
-	    ("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
-	    cntxt_id, sc->sge.neq - 1));
-	sc->sge.eqmap[cntxt_id] = eq;
-
-	children = SYSCTL_CHILDREN(pi->oid_txq);
-
 	snprintf(name, sizeof(name), "%d", idx);
 	oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
 	    NULL, "tx queue");
@@ -1709,7 +2292,9 @@ alloc_txq(struct port_info *pi, struct sge_txq *txq, int idx)
 	SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "no_desc", CTLFLAG_RD,
 	    &txq->no_desc, 0, "# of times txq ran out of hardware descriptors");
 	SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "egr_update", CTLFLAG_RD,
-	    &txq->egr_update, 0, "egress update notifications from the SGE");
+	    &eq->egr_update, 0, "egress update notifications from the SGE");
+	SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "unstalled", CTLFLAG_RD,
+	    &eq->unstalled, 0, "# of times txq recovered after stall");
 
 	return (rc);
 }
@@ -1721,52 +2306,20 @@ free_txq(struct port_info *pi, struct sge_txq *txq)
 	struct adapter *sc = pi->adapter;
 	struct sge_eq *eq = &txq->eq;
 
-	if (eq->flags & (EQ_ALLOCATED | EQ_STARTED)) {
-
-		/*
-		 * Wait for the response to a credit flush if there's one
-		 * pending.  Clearing the flag tells handle_sge_egr_update or
-		 * cxgbe_txq_start (depending on how far the response has made
-		 * it) that they should ignore the response and wake up free_txq
-		 * instead.
-		 *
-		 * The interface has been marked down by the time we get here
-		 * (both IFF_UP and IFF_DRV_RUNNING cleared).  qflush has
-		 * emptied the tx buf_rings and we know nothing new is being
-		 * queued for tx so we don't have to worry about a new credit
-		 * flush request.
-		 */
-		TXQ_LOCK(txq);
-		if (eq->flags & EQ_CRFLUSHED) {
-			eq->flags &= ~EQ_CRFLUSHED;
-			msleep(txq, &eq->eq_lock, 0, "crflush", 0);
-		}
-		TXQ_UNLOCK(txq);
-
-		rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id);
-		if (rc != 0) {
-			device_printf(pi->dev,
-			    "failed to free egress queue %p: %d\n", eq, rc);
-			return (rc);
-		}
-		eq->flags &= ~(EQ_ALLOCATED | EQ_STARTED);
-	}
-
-	free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc);
+	rc = free_eq(sc, eq);
+	if (rc)
+		return (rc);
 
 	free(txq->sdesc, M_CXGBE);
 
-	if (txq->maps)
-		free_tx_maps(txq);
+	if (txq->txmaps.maps)
+		t4_free_tx_maps(&txq->txmaps, txq->tx_tag);
 
 	buf_ring_free(txq->br, M_CXGBE);
 
 	if (txq->tx_tag)
 		bus_dma_tag_destroy(txq->tx_tag);
 
-	if (mtx_initialized(&eq->eq_lock))
-		mtx_destroy(&eq->eq_lock);
-
 	bzero(txq, sizeof(*txq));
 	return (0);
 }
@@ -1822,11 +2375,13 @@ ring_fl_db(struct adapter *sc, struct sge_fl *fl)
 }
 
 /*
- * Fill up the freelist by upto nbufs and ring its doorbell if the number of
- * buffers ready to be handed to the hardware >= dbthresh.
+ * Fill up the freelist by upto nbufs and maybe ring its doorbell.
+ *
+ * Returns non-zero to indicate that it should be added to the list of starving
+ * freelists.
  */
-static void
-refill_fl(struct adapter *sc, struct sge_fl *fl, int nbufs, int dbthresh)
+static int
+refill_fl(struct adapter *sc, struct sge_fl *fl, int nbufs)
 {
 	__be64 *d = &fl->desc[fl->pidx];
 	struct fl_sdesc *sd = &fl->sdesc[fl->pidx];
@@ -1837,7 +2392,7 @@ refill_fl(struct adapter *sc, struct sge_fl *fl, int nbufs, int dbthresh)
 
 	FL_LOCK_ASSERT_OWNED(fl);
 
-	if (nbufs < 0 || nbufs > fl->needed)
+	if (nbufs > fl->needed)
 		nbufs = fl->needed;
 
 	while (nbufs--) {
@@ -1918,8 +2473,35 @@ recycled:
 		}
 	}
 
-	if (fl->pending >= dbthresh)
+	if (fl->pending >= 8)
 		ring_fl_db(sc, fl);
+
+	return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING));
+}
+
+/*
+ * Attempt to refill all starving freelists.
+ */
+static void
+refill_sfl(void *arg)
+{
+	struct adapter *sc = arg;
+	struct sge_fl *fl, *fl_temp;
+
+	mtx_lock(&sc->sfl_lock);
+	TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) {
+		FL_LOCK(fl);
+		refill_fl(sc, fl, 64);
+		if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) {
+			TAILQ_REMOVE(&sc->sfl, fl, link);
+			fl->flags &= ~FL_STARVING;
+		}
+		FL_UNLOCK(fl);
+	}
+
+	if (!TAILQ_EMPTY(&sc->sfl))
+		callout_schedule(&sc->sfl_callout, hz / 5);
+	mtx_unlock(&sc->sfl_lock);
 }
 
 static int
@@ -1993,27 +2575,22 @@ free_fl_sdesc(struct sge_fl *fl)
 	fl->sdesc = NULL;
 }
 
-static int
-alloc_tx_maps(struct sge_txq *txq)
+int
+t4_alloc_tx_maps(struct tx_maps *txmaps, bus_dma_tag_t tx_tag, int count,
+    int flags)
 {
 	struct tx_map *txm;
-	int i, rc, count;
+	int i, rc;
 
-	/*
-	 * We can stuff ~10 frames in an 8-descriptor txpkts WR (8 is the SGE
-	 * limit for any WR).  txq->no_dmamap events shouldn't occur if maps is
-	 * sized for the worst case.
-	 */
-	count = txq->eq.qsize * 10 / 8;
-	txq->map_total = txq->map_avail = count;
-	txq->map_cidx = txq->map_pidx = 0;
+	txmaps->map_total = txmaps->map_avail = count;
+	txmaps->map_cidx = txmaps->map_pidx = 0;
 
-	txq->maps = malloc(count * sizeof(struct tx_map), M_CXGBE,
-	    M_ZERO | M_WAITOK);
+	txmaps->maps = malloc(count * sizeof(struct tx_map), M_CXGBE,
+	    M_ZERO | flags);
 
-	txm = txq->maps;
+	txm = txmaps->maps;
 	for (i = 0; i < count; i++, txm++) {
-		rc = bus_dmamap_create(txq->tx_tag, 0, &txm->map);
+		rc = bus_dmamap_create(tx_tag, 0, &txm->map);
 		if (rc != 0)
 			goto failed;
 	}
@@ -2022,36 +2599,36 @@ alloc_tx_maps(struct sge_txq *txq)
 failed:
 	while (--i >= 0) {
 		txm--;
-		bus_dmamap_destroy(txq->tx_tag, txm->map);
+		bus_dmamap_destroy(tx_tag, txm->map);
 	}
-	KASSERT(txm == txq->maps, ("%s: EDOOFUS", __func__));
+	KASSERT(txm == txmaps->maps, ("%s: EDOOFUS", __func__));
 
-	free(txq->maps, M_CXGBE);
-	txq->maps = NULL;
+	free(txmaps->maps, M_CXGBE);
+	txmaps->maps = NULL;
 
 	return (rc);
 }
 
-static void
-free_tx_maps(struct sge_txq *txq)
+void
+t4_free_tx_maps(struct tx_maps *txmaps, bus_dma_tag_t tx_tag)
 {
 	struct tx_map *txm;
 	int i;
 
-	txm = txq->maps;
-	for (i = 0; i < txq->map_total; i++, txm++) {
+	txm = txmaps->maps;
+	for (i = 0; i < txmaps->map_total; i++, txm++) {
 
 		if (txm->m) {
-			bus_dmamap_unload(txq->tx_tag, txm->map);
+			bus_dmamap_unload(tx_tag, txm->map);
 			m_freem(txm->m);
 			txm->m = NULL;
 		}
 
-		bus_dmamap_destroy(txq->tx_tag, txm->map);
+		bus_dmamap_destroy(tx_tag, txm->map);
 	}
 
-	free(txq->maps, M_CXGBE);
-	txq->maps = NULL;
+	free(txmaps->maps, M_CXGBE);
+	txmaps->maps = NULL;
 }
 
 /*
@@ -2060,7 +2637,7 @@ free_tx_maps(struct sge_txq *txq)
  * of immediate data.
  */
 #define IMM_LEN ( \
-      2 * TX_EQ_ESIZE \
+      2 * EQ_ESIZE \
     - sizeof(struct fw_eth_tx_pkt_wr) \
     - sizeof(struct cpl_tx_pkt_core))
 
@@ -2078,6 +2655,7 @@ get_pkt_sgl(struct sge_txq *txq, struct mbuf **fp, struct sgl *sgl,
     int sgl_only)
 {
 	struct mbuf *m = *fp;
+	struct tx_maps *txmaps;
 	struct tx_map *txm;
 	int rc, defragged = 0, n;
 
@@ -2091,11 +2669,12 @@ start:	sgl->nsegs = 0;
 	if (m->m_pkthdr.len <= IMM_LEN && !sgl_only)
 		return (0);	/* nsegs = 0 tells caller to use imm. tx */
 
-	if (txq->map_avail == 0) {
+	txmaps = &txq->txmaps;
+	if (txmaps->map_avail == 0) {
 		txq->no_dmamap++;
 		return (ENOMEM);
 	}
-	txm = &txq->maps[txq->map_pidx];
+	txm = &txmaps->maps[txmaps->map_pidx];
 
 	if (m->m_pkthdr.tso_segsz && m->m_len < 50) {
 		*fp = m_pullup(m, 50);
@@ -2119,9 +2698,9 @@ start:	sgl->nsegs = 0;
 		return (rc);
 
 	txm->m = m;
-	txq->map_avail--;
-	if (++txq->map_pidx == txq->map_total)
-		txq->map_pidx = 0;
+	txmaps->map_avail--;
+	if (++txmaps->map_pidx == txmaps->map_total)
+		txmaps->map_pidx = 0;
 
 	KASSERT(sgl->nsegs > 0 && sgl->nsegs <= TX_SGL_SEGS,
 	    ("%s: bad DMA mapping (%d segments)", __func__, sgl->nsegs));
@@ -2145,6 +2724,7 @@ start:	sgl->nsegs = 0;
 static int
 free_pkt_sgl(struct sge_txq *txq, struct sgl *sgl)
 {
+	struct tx_maps *txmaps;
 	struct tx_map *txm;
 
 	TXQ_LOCK_ASSERT_OWNED(txq);
@@ -2152,15 +2732,17 @@ free_pkt_sgl(struct sge_txq *txq, struct sgl *sgl)
 	if (sgl->nsegs == 0)
 		return (0);	/* didn't use any map */
 
+	txmaps = &txq->txmaps;
+
 	/* 1 pkt uses exactly 1 map, back it out */
 
-	txq->map_avail++;
-	if (txq->map_pidx > 0)
-		txq->map_pidx--;
+	txmaps->map_avail++;
+	if (txmaps->map_pidx > 0)
+		txmaps->map_pidx--;
 	else
-		txq->map_pidx = txq->map_total - 1;
+		txmaps->map_pidx = txmaps->map_total - 1;
 
-	txm = &txq->maps[txq->map_pidx];
+	txm = &txmaps->maps[txmaps->map_pidx];
 	bus_dmamap_unload(txq->tx_tag, txm->map);
 	txm->m = NULL;
 
@@ -2206,11 +2788,14 @@ write_txpkt_wr(struct port_info *pi, struct sge_txq *txq, struct mbuf *m,
 	/* Firmware work request header */
 	wr = (void *)&eq->desc[eq->pidx];
 	wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
-	    V_FW_WR_IMMDLEN(ctrl));
+	    V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
 	ctrl = V_FW_WR_LEN16(howmany(nflits, 2));
-	if (eq->avail == ndesc && !(eq->flags & EQ_CRFLUSHED)) {
-		ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ;
-		eq->flags |= EQ_CRFLUSHED;
+	if (eq->avail == ndesc) {
+		if (!(eq->flags & EQ_CRFLUSHED)) {
+			ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ;
+			eq->flags |= EQ_CRFLUSHED;
+		}
+		eq->flags |= EQ_STALLED;
 	}
 
 	wr->equiq_to_len16 = htobe32(ctrl);
@@ -2325,6 +2910,8 @@ add_to_txpkts(struct port_info *pi, struct sge_txq *txq, struct txpkts *txpkts,
 
 	TXQ_LOCK_ASSERT_OWNED(txq);
 
+	KASSERT(sgl->nsegs, ("%s: can't coalesce imm data", __func__));
+
 	if (txpkts->npkt > 0) {
 		flits = TXPKTS_PKT_HDR + sgl->nflits;
 		can_coalesce = m->m_pkthdr.tso_segsz == 0 &&
@@ -2397,12 +2984,14 @@ write_txpkts_wr(struct sge_txq *txq, struct txpkts *txpkts)
 	ndesc = howmany(txpkts->nflits, 8);
 
 	wr = (void *)&eq->desc[eq->pidx];
-	wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR) |
-	    V_FW_WR_IMMDLEN(0)); /* immdlen does not matter in this WR */
+	wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
 	ctrl = V_FW_WR_LEN16(howmany(txpkts->nflits, 2));
-	if (eq->avail == ndesc && !(eq->flags & EQ_CRFLUSHED)) {
-		ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ;
-		eq->flags |= EQ_CRFLUSHED;
+	if (eq->avail == ndesc) {
+		if (!(eq->flags & EQ_CRFLUSHED)) {
+			ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ;
+			eq->flags |= EQ_CRFLUSHED;
+		}
+		eq->flags |= EQ_STALLED;
 	}
 	wr->equiq_to_len16 = htobe32(ctrl);
 	wr->plen = htobe16(txpkts->plen);
@@ -2616,7 +3205,7 @@ reclaimable(struct sge_eq *eq)
 	unsigned int cidx;
 
 	cidx = eq->spg->cidx;	/* stable snapshot */
-	cidx = be16_to_cpu(cidx);
+	cidx = be16toh(cidx);
 
 	if (cidx >= eq->cidx)
 		return (cidx - eq->cidx);
@@ -2634,11 +3223,12 @@ static int
 reclaim_tx_descs(struct sge_txq *txq, int can_reclaim, int n)
 {
 	struct tx_sdesc *txsd;
+	struct tx_maps *txmaps;
 	struct tx_map *txm;
 	unsigned int reclaimed, maps;
 	struct sge_eq *eq = &txq->eq;
 
-	EQ_LOCK_ASSERT_OWNED(eq);
+	TXQ_LOCK_ASSERT_OWNED(txq);
 
 	if (can_reclaim == 0)
 		can_reclaim = reclaimable(eq);
@@ -2665,7 +3255,8 @@ reclaim_tx_descs(struct sge_txq *txq, int can_reclaim, int n)
 			eq->cidx -= eq->cap;
 	}
 
-	txm = &txq->maps[txq->map_cidx];
+	txmaps = &txq->txmaps;
+	txm = &txmaps->maps[txmaps->map_cidx];
 	if (maps)
 		prefetch(txm->m);
 
@@ -2673,16 +3264,16 @@ reclaim_tx_descs(struct sge_txq *txq, int can_reclaim, int n)
 	KASSERT(eq->avail < eq->cap,	/* avail tops out at (cap - 1) */
 	    ("%s: too many descriptors available", __func__));
 
-	txq->map_avail += maps;
-	KASSERT(txq->map_avail <= txq->map_total,
+	txmaps->map_avail += maps;
+	KASSERT(txmaps->map_avail <= txmaps->map_total,
 	    ("%s: too many maps available", __func__));
 
 	while (maps--) {
 		struct tx_map *next;
 
 		next = txm + 1;
-		if (__predict_false(txq->map_cidx + 1 == txq->map_total))
-			next = txq->maps;
+		if (__predict_false(txmaps->map_cidx + 1 == txmaps->map_total))
+			next = txmaps->maps;
 		prefetch(next->m);
 
 		bus_dmamap_unload(txq->tx_tag, txm->map);
@@ -2690,8 +3281,8 @@ reclaim_tx_descs(struct sge_txq *txq, int can_reclaim, int n)
 		txm->m = NULL;
 
 		txm = next;
-		if (__predict_false(++txq->map_cidx == txq->map_total))
-			txq->map_cidx = 0;
+		if (__predict_false(++txmaps->map_cidx == txmaps->map_total))
+			txmaps->map_cidx = 0;
 	}
 
 	return (reclaimed);
@@ -2704,6 +3295,7 @@ write_eqflush_wr(struct sge_eq *eq)
 
 	EQ_LOCK_ASSERT_OWNED(eq);
 	KASSERT(eq->avail > 0, ("%s: no descriptors left.", __func__));
+	KASSERT(!(eq->flags & EQ_CRFLUSHED), ("%s: flushed already", __func__));
 
 	wr = (void *)&eq->desc[eq->pidx];
 	bzero(wr, sizeof(*wr));
@@ -2711,7 +3303,7 @@ write_eqflush_wr(struct sge_eq *eq)
 	wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(sizeof(*wr) / 16) |
 	    F_FW_WR_EQUEQ | F_FW_WR_EQUIQ);
 
-	eq->flags |= EQ_CRFLUSHED;
+	eq->flags |= (EQ_CRFLUSHED | EQ_STALLED);
 	eq->pending++;
 	eq->avail--;
 	if (++eq->pidx == eq->cap)
@@ -2743,118 +3335,73 @@ get_flit(bus_dma_segment_t *sgl, int nsegs, int idx)
 }
 
 static void
-set_fl_tag_idx(struct sge_fl *fl, int mtu)
+set_fl_tag_idx(struct sge_fl *fl, int bufsize)
 {
 	int i;
 
-	FL_LOCK_ASSERT_OWNED(fl);
-
 	for (i = 0; i < FL_BUF_SIZES - 1; i++) {
-		if (FL_BUF_SIZE(i) >= (mtu + FL_PKTSHIFT))
+		if (FL_BUF_SIZE(i) >= bufsize)
 			break;
 	}
 
 	fl->tag_idx = i;
 }
 
-static int
-handle_sge_egr_update(struct adapter *sc, const struct cpl_sge_egr_update *cpl)
-{
-	unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid));
-	struct sge *s = &sc->sge;
-	struct sge_txq *txq;
-	struct port_info *pi;
-
-	txq = (void *)s->eqmap[qid - s->eq_start];
-	TXQ_LOCK(txq);
-	if (txq->eq.flags & EQ_CRFLUSHED) {
-		pi = txq->ifp->if_softc;
-		taskqueue_enqueue(pi->tq, &txq->resume_tx);
-		txq->egr_update++;
-	} else
-		wakeup_one(txq);	/* txq is going away, wakeup free_txq */
-	TXQ_UNLOCK(txq);
-
-	return (0);
-}
-
 static void
-handle_cpl(struct adapter *sc, struct sge_iq *iq)
+add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl)
 {
-	const struct rss_header *rss = (const void *)iq->cdesc;
-	const struct cpl_fw6_msg *cpl = (const void *)(rss + 1);
-
-	switch (rss->opcode) {
-	case CPL_FW4_MSG:
-	case CPL_FW6_MSG:
-		if (cpl->type == FW6_TYPE_CMD_RPL)
-			t4_handle_fw_rpl(sc, cpl->data);
-		break;
-
-	case CPL_SGE_EGR_UPDATE:
-		handle_sge_egr_update(sc, (const void *)cpl);
-		break;
-
-	case CPL_SET_TCB_RPL:
-		filter_rpl(sc, (const void *)cpl);
-		break;
-
-	default:
-		panic("%s: unexpected CPL opcode 0x%x", __func__, rss->opcode);
+	mtx_lock(&sc->sfl_lock);
+	FL_LOCK(fl);
+	if ((fl->flags & FL_DOOMED) == 0) {
+		fl->flags |= FL_STARVING;
+		TAILQ_INSERT_TAIL(&sc->sfl, fl, link);
+		callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc);
 	}
+	FL_UNLOCK(fl);
+	mtx_unlock(&sc->sfl_lock);
 }
 
-/*
- * m0 is freed on successful transmission.
- */
 static int
-ctrl_tx(struct adapter *sc, struct sge_ctrlq *ctrlq, struct mbuf *m0)
+handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss,
+    struct mbuf *m)
 {
-	struct sge_eq *eq = &ctrlq->eq;
-	int rc = 0, ndesc;
-	int can_reclaim;
-	caddr_t dst;
-	struct mbuf *m;
-
-	M_ASSERTPKTHDR(m0);
+	const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1);
+	unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid));
+	struct adapter *sc = iq->adapter;
+	struct sge *s = &sc->sge;
+	struct sge_eq *eq;
 
-	if (m0->m_pkthdr.len > SGE_MAX_WR_LEN) {
-		log(LOG_ERR, "%s: %s work request too long (%d)",
-		    device_get_nameunit(sc->dev), __func__, m0->m_pkthdr.len);
-		return (EMSGSIZE);
-	}
-	ndesc = howmany(m0->m_pkthdr.len, CTRL_EQ_ESIZE);
+	KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
+	    rss->opcode));
 
+	eq = s->eqmap[qid - s->eq_start];
 	EQ_LOCK(eq);
+	KASSERT(eq->flags & EQ_CRFLUSHED,
+	    ("%s: unsolicited egress update", __func__));
+	eq->flags &= ~EQ_CRFLUSHED;
+	eq->egr_update++;
+
+	if (__predict_false(eq->flags & EQ_DOOMED))
+		wakeup_one(eq);
+	else if (eq->flags & EQ_STALLED && can_resume_tx(eq))
+		taskqueue_enqueue(sc->tq[eq->tx_chan], &eq->tx_task);
+	EQ_UNLOCK(eq);
 
-	can_reclaim = reclaimable(eq);
-	eq->cidx += can_reclaim;
-	eq->avail += can_reclaim;
-	if (__predict_false(eq->cidx >= eq->cap))
-		eq->cidx -= eq->cap;
-
-	if (eq->avail < ndesc) {
-		rc = EAGAIN;
-		ctrlq->no_desc++;
-		goto failed;
-	}
+	return (0);
+}
 
-	dst = (void *)&eq->desc[eq->pidx];
-	for (m = m0; m; m = m->m_next)
-		copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
+static int
+handle_fw_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
+{
+	const struct cpl_fw6_msg *cpl = (const void *)(rss + 1);
 
-	eq->pidx += ndesc;
-	if (__predict_false(eq->pidx >= eq->cap))
-		eq->pidx -= eq->cap;
+	KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
+	    rss->opcode));
 
-	eq->pending += ndesc;
-	ring_eq_db(sc, eq);
-failed:
-	EQ_UNLOCK(eq);
-	if (rc == 0)
-		m_freem(m0);
+	if (cpl->type == FW6_TYPE_CMD_RPL)
+		t4_handle_fw_rpl(iq->adapter, cpl->data);
 
-	return (rc);
+	return (0);
 }
 
 static int
diff --git a/sys/dev/dc/dcphy.c b/sys/dev/dc/dcphy.c
index ab44993..a05f2ed 100644
--- a/sys/dev/dc/dcphy.c
+++ b/sys/dev/dc/dcphy.c
@@ -95,7 +95,7 @@ static device_method_t dcphy_methods[] = {
 	DEVMETHOD(device_attach,	dcphy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t dcphy_devclass;
diff --git a/sys/dev/dc/if_dc.c b/sys/dev/dc/if_dc.c
index b9ea19a..0ace34e 100644
--- a/sys/dev/dc/if_dc.c
+++ b/sys/dev/dc/if_dc.c
@@ -337,17 +337,13 @@ static device_method_t dc_methods[] = {
 	DEVMETHOD(device_resume,	dc_resume),
 	DEVMETHOD(device_shutdown,	dc_shutdown),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	dc_miibus_readreg),
 	DEVMETHOD(miibus_writereg,	dc_miibus_writereg),
 	DEVMETHOD(miibus_statchg,	dc_miibus_statchg),
 	DEVMETHOD(miibus_mediainit,	dc_miibus_mediainit),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t dc_driver = {
diff --git a/sys/dev/dc/pnphy.c b/sys/dev/dc/pnphy.c
index 6546acd..98e721d 100644
--- a/sys/dev/dc/pnphy.c
+++ b/sys/dev/dc/pnphy.c
@@ -74,7 +74,7 @@ static device_method_t pnphy_methods[] = {
 	DEVMETHOD(device_attach,	pnphy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t pnphy_devclass;
diff --git a/sys/dev/dcons/dcons_os.c b/sys/dev/dcons/dcons_os.c
index d638d41..a37d64c 100644
--- a/sys/dev/dcons/dcons_os.c
+++ b/sys/dev/dcons/dcons_os.c
@@ -109,6 +109,8 @@ static cn_init_t	dcons_cninit;
 static cn_term_t	dcons_cnterm;
 static cn_getc_t	dcons_cngetc;
 static cn_putc_t	dcons_cnputc;
+static cn_grab_t	dcons_cngrab;
+static cn_ungrab_t	dcons_cnungrab;
 
 CONSOLE_DRIVER(dcons);
 
@@ -246,6 +248,16 @@ dcons_cnterm(struct consdev *cp)
 {
 }
 
+static void
+dcons_cngrab(struct consdev *cp)
+{
+}
+
+static void
+dcons_cnungrab(struct consdev *cp)
+{
+}
+
 static int
 dcons_cngetc(struct consdev *cp)
 {
diff --git a/sys/dev/de/if_de.c b/sys/dev/de/if_de.c
index a9b9f31..5970bcd 100644
--- a/sys/dev/de/if_de.c
+++ b/sys/dev/de/if_de.c
@@ -1567,7 +1567,7 @@ tulip_null_media_poll(tulip_softc_t * const sc, tulip_mediapoll_event_t event)
 #endif
 }
 
-__inline static void
+static inline void
 tulip_21140_mediainit(tulip_softc_t * const sc, tulip_media_info_t * const mip,
     tulip_media_t const media, unsigned gpdata, unsigned cmdmode)
 {
diff --git a/sys/dev/drm/i915_drv.h b/sys/dev/drm/i915_drv.h
index 4ae5e5c..3896732 100644
--- a/sys/dev/drm/i915_drv.h
+++ b/sys/dev/drm/i915_drv.h
@@ -560,7 +560,7 @@ extern void opregion_enable_asle(struct drm_device *dev);
 		LOCK_TEST_WITH_RETURN(dev, file_priv);			\
 } while (0)
 
-#if defined(__FreeBSD__)
+#if defined(__FreeBSD__) && !defined(__bool_true_false_are_defined)
 typedef boolean_t bool;
 #endif
 
diff --git a/sys/dev/drm/mga_drv.h b/sys/dev/drm/mga_drv.h
index 61b6e82..01c5c9d 100644
--- a/sys/dev/drm/mga_drv.h
+++ b/sys/dev/drm/mga_drv.h
@@ -288,7 +288,7 @@ do {									\
 do {									\
 	if ( MGA_VERBOSE ) {						\
 		DRM_INFO( "BEGIN_DMA( %d )\n", (n) );		\
-		DRM_INFO( "   space=0x%x req=0x%Zx\n",			\
+		DRM_INFO( "   space=0x%x req=0x%zx\n",			\
 			  dev_priv->prim.space, (n) * DMA_BLOCK_SIZE );	\
 	}								\
 	prim = dev_priv->prim.start;					\
@@ -338,7 +338,7 @@ do {									\
 #define DMA_WRITE( offset, val )					\
 do {									\
 	if ( MGA_VERBOSE ) {						\
-		DRM_INFO( "   DMA_WRITE( 0x%08x ) at 0x%04Zx\n",	\
+		DRM_INFO( "   DMA_WRITE( 0x%08x ) at 0x%04zx\n",	\
 			  (u32)(val), write + (offset) * sizeof(u32) );	\
 	}								\
 	*(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val;	\
diff --git a/sys/dev/drm/radeon_state.c b/sys/dev/drm/radeon_state.c
index 8061501..b334a88 100644
--- a/sys/dev/drm/radeon_state.c
+++ b/sys/dev/drm/radeon_state.c
@@ -1745,7 +1745,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
 	DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width);
 
 	do {
-		DRM_DEBUG("tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
+		DRM_DEBUG("tex: ofs=0x%x p=%d f=%d x=%d y=%d w=%d h=%d\n",
 			  tex->offset >> 10, tex->pitch, tex->format,
 			  image->x, image->y, image->width, image->height);
 
diff --git a/sys/dev/e1000/e1000_80003es2lan.c b/sys/dev/e1000/e1000_80003es2lan.c
index 01b9e6d..bdbb31c 100644
--- a/sys/dev/e1000/e1000_80003es2lan.c
+++ b/sys/dev/e1000/e1000_80003es2lan.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -47,18 +47,18 @@ static void e1000_release_phy_80003es2lan(struct e1000_hw *hw);
 static s32  e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw);
 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw);
 static s32  e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
-                                                   u32 offset,
-                                                   u16 *data);
+						   u32 offset,
+						   u16 *data);
 static s32  e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
-                                                    u32 offset,
-                                                    u16 data);
+						    u32 offset,
+						    u16 data);
 static s32  e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
-                                        u16 words, u16 *data);
+					u16 words, u16 *data);
 static s32  e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw);
 static s32  e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw);
 static s32  e1000_get_cable_length_80003es2lan(struct e1000_hw *hw);
 static s32  e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
-                                               u16 *duplex);
+					       u16 *duplex);
 static s32  e1000_reset_hw_80003es2lan(struct e1000_hw *hw);
 static s32  e1000_init_hw_80003es2lan(struct e1000_hw *hw);
 static s32  e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
@@ -68,9 +68,9 @@ static s32  e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
 static s32  e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
 static s32  e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
 static s32  e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
-                                            u16 *data);
+					    u16 *data);
 static s32  e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
-                                             u16 data);
+					     u16 data);
 static s32  e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw);
 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
@@ -85,8 +85,8 @@ static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
 static const u16 e1000_gg82563_cable_length_table[] = {
 	0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
-                (sizeof(e1000_gg82563_cable_length_table) / \
-                 sizeof(e1000_gg82563_cable_length_table[0]))
+		(sizeof(e1000_gg82563_cable_length_table) / \
+		 sizeof(e1000_gg82563_cable_length_table[0]))
 
 /**
  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
@@ -100,34 +100,34 @@ static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
 	DEBUGFUNC("e1000_init_phy_params_80003es2lan");
 
 	if (hw->phy.media_type != e1000_media_type_copper) {
-		phy->type        = e1000_phy_none;
+		phy->type = e1000_phy_none;
 		goto out;
 	} else {
 		phy->ops.power_up = e1000_power_up_phy_copper;
 		phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
 	}
 
-	phy->addr                = 1;
-	phy->autoneg_mask        = AUTONEG_ADVERTISE_SPEED_DEFAULT;
-	phy->reset_delay_us      = 100;
-	phy->type                = e1000_phy_gg82563;
-
-	phy->ops.acquire            = e1000_acquire_phy_80003es2lan;
-	phy->ops.check_polarity     = e1000_check_polarity_m88;
-	phy->ops.check_reset_block  = e1000_check_reset_block_generic;
-	phy->ops.commit             = e1000_phy_sw_reset_generic;
-	phy->ops.get_cfg_done       = e1000_get_cfg_done_80003es2lan;
-	phy->ops.get_info           = e1000_get_phy_info_m88;
-	phy->ops.release            = e1000_release_phy_80003es2lan;
-	phy->ops.reset              = e1000_phy_hw_reset_generic;
-	phy->ops.set_d3_lplu_state  = e1000_set_d3_lplu_state_generic;
+	phy->addr		= 1;
+	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;
+	phy->reset_delay_us	= 100;
+	phy->type		= e1000_phy_gg82563;
+
+	phy->ops.acquire	= e1000_acquire_phy_80003es2lan;
+	phy->ops.check_polarity	= e1000_check_polarity_m88;
+	phy->ops.check_reset_block = e1000_check_reset_block_generic;
+	phy->ops.commit		= e1000_phy_sw_reset_generic;
+	phy->ops.get_cfg_done	= e1000_get_cfg_done_80003es2lan;
+	phy->ops.get_info	= e1000_get_phy_info_m88;
+	phy->ops.release	= e1000_release_phy_80003es2lan;
+	phy->ops.reset		= e1000_phy_hw_reset_generic;
+	phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
 
 	phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan;
-	phy->ops.get_cable_length   = e1000_get_cable_length_80003es2lan;
-	phy->ops.read_reg           = e1000_read_phy_reg_gg82563_80003es2lan;
-	phy->ops.write_reg          = e1000_write_phy_reg_gg82563_80003es2lan;
+	phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan;
+	phy->ops.read_reg	= e1000_read_phy_reg_gg82563_80003es2lan;
+	phy->ops.write_reg	= e1000_write_phy_reg_gg82563_80003es2lan;
 
-	phy->ops.cfg_on_link_up    = e1000_cfg_on_link_up_80003es2lan;
+	phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan;
 
 	/* This can only be done after all function pointers are setup. */
 	ret_val = e1000_get_phy_id(hw);
@@ -154,19 +154,19 @@ static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
 
 	DEBUGFUNC("e1000_init_nvm_params_80003es2lan");
 
-	nvm->opcode_bits        = 8;
-	nvm->delay_usec         = 1;
+	nvm->opcode_bits = 8;
+	nvm->delay_usec = 1;
 	switch (nvm->override) {
 	case e1000_nvm_override_spi_large:
-		nvm->page_size    = 32;
+		nvm->page_size = 32;
 		nvm->address_bits = 16;
 		break;
 	case e1000_nvm_override_spi_small:
-		nvm->page_size    = 8;
+		nvm->page_size = 8;
 		nvm->address_bits = 8;
 		break;
 	default:
-		nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
+		nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 		break;
 	}
@@ -174,7 +174,7 @@ static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
 	nvm->type = e1000_nvm_eeprom_spi;
 
 	size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
-	                  E1000_EECD_SIZE_EX_SHIFT);
+		     E1000_EECD_SIZE_EX_SHIFT);
 
 	/*
 	 * Added to a constant, "size" becomes the left-shift value
@@ -185,16 +185,16 @@ static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
 	/* EEPROM access above 16k is unsupported */
 	if (size > 14)
 		size = 14;
-	nvm->word_size	= 1 << size;
+	nvm->word_size = 1 << size;
 
 	/* Function Pointers */
-	nvm->ops.acquire           = e1000_acquire_nvm_80003es2lan;
-	nvm->ops.read              = e1000_read_nvm_eerd;
-	nvm->ops.release           = e1000_release_nvm_80003es2lan;
-	nvm->ops.update            = e1000_update_nvm_checksum_generic;
+	nvm->ops.acquire	= e1000_acquire_nvm_80003es2lan;
+	nvm->ops.read		= e1000_read_nvm_eerd;
+	nvm->ops.release	= e1000_release_nvm_80003es2lan;
+	nvm->ops.update		= e1000_update_nvm_checksum_generic;
 	nvm->ops.valid_led_default = e1000_valid_led_default_generic;
-	nvm->ops.validate          = e1000_validate_nvm_checksum_generic;
-	nvm->ops.write             = e1000_write_nvm_80003es2lan;
+	nvm->ops.validate	= e1000_validate_nvm_checksum_generic;
+	nvm->ops.write		= e1000_write_nvm_80003es2lan;
 
 	return E1000_SUCCESS;
 }
@@ -215,13 +215,13 @@ static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
 		hw->phy.media_type = e1000_media_type_internal_serdes;
 		mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
 		mac->ops.setup_physical_interface =
-			e1000_setup_fiber_serdes_link_generic;
+					e1000_setup_fiber_serdes_link_generic;
 		break;
 	default:
 		hw->phy.media_type = e1000_media_type_copper;
 		mac->ops.check_for_link = e1000_check_for_copper_link_generic;
 		mac->ops.setup_physical_interface =
-			e1000_setup_copper_link_80003es2lan;
+					e1000_setup_copper_link_80003es2lan;
 		break;
 	}
 
@@ -234,9 +234,8 @@ static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
 	/* FWSM register */
 	mac->has_fwsm = TRUE;
 	/* ARC supported; valid only if manageability features are enabled. */
-	mac->arc_subsystem_valid =
-	        (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
-	                ? TRUE : FALSE;
+	mac->arc_subsystem_valid = (E1000_READ_REG(hw, E1000_FWSM) &
+				    E1000_FWSM_MODE_MASK) ? TRUE : FALSE;
 	/* Adaptive IFS not supported */
 	mac->adaptive_ifs = FALSE;
 
@@ -330,7 +329,7 @@ static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
 }
 
 /**
- *  e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
+ *  e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
  *  @hw: pointer to the HW structure
  *
  *  Acquire the semaphore to access the Kumeran interface.
@@ -348,7 +347,7 @@ static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
 }
 
 /**
- *  e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
+ *  e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
  *  @hw: pointer to the HW structure
  *
  *  Release the semaphore used to access the Kumeran interface
@@ -488,7 +487,7 @@ static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
  *  Read the GG82563 PHY register.
  **/
 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
-                                                  u32 offset, u16 *data)
+						  u32 offset, u16 *data)
 {
 	s32 ret_val;
 	u32 page_select;
@@ -538,14 +537,14 @@ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 		usec_delay(200);
 
 		ret_val = e1000_read_phy_reg_mdic(hw,
-		                                  MAX_PHY_REG_ADDRESS & offset,
-		                                  data);
+						  MAX_PHY_REG_ADDRESS & offset,
+						  data);
 
 		usec_delay(200);
 	} else {
 		ret_val = e1000_read_phy_reg_mdic(hw,
-		                                  MAX_PHY_REG_ADDRESS & offset,
-		                                  data);
+						  MAX_PHY_REG_ADDRESS & offset,
+						  data);
 	}
 
 	e1000_release_phy_80003es2lan(hw);
@@ -563,7 +562,7 @@ out:
  *  Write to the GG82563 PHY register.
  **/
 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
-                                                   u32 offset, u16 data)
+						   u32 offset, u16 data)
 {
 	s32 ret_val;
 	u32 page_select;
@@ -613,14 +612,14 @@ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 		usec_delay(200);
 
 		ret_val = e1000_write_phy_reg_mdic(hw,
-		                                  MAX_PHY_REG_ADDRESS & offset,
-		                                  data);
+						  MAX_PHY_REG_ADDRESS & offset,
+						  data);
 
 		usec_delay(200);
 	} else {
 		ret_val = e1000_write_phy_reg_mdic(hw,
-		                                  MAX_PHY_REG_ADDRESS & offset,
-		                                  data);
+						  MAX_PHY_REG_ADDRESS & offset,
+						  data);
 	}
 
 	e1000_release_phy_80003es2lan(hw);
@@ -639,7 +638,7 @@ out:
  *  Write "words" of data to the ESB2 NVM.
  **/
 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
-                            u16 words, u16 *data)
+				       u16 words, u16 *data)
 {
 	DEBUGFUNC("e1000_write_nvm_80003es2lan");
 
@@ -729,11 +728,10 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
 	usec_delay(1);
 
 	if (hw->phy.autoneg_wait_to_complete) {
-		DEBUGOUT("Waiting for forced speed/duplex link "
-		         "on GG82563 phy.\n");
+		DEBUGOUT("Waiting for forced speed/duplex link on GG82563 phy.\n");
 
 		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
-		                                     100000, &link);
+						     100000, &link);
 		if (ret_val)
 			goto out;
 
@@ -749,12 +747,13 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
 
 		/* Try once more */
 		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
-		                                     100000, &link);
+						     100000, &link);
 		if (ret_val)
 			goto out;
 	}
 
-	ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
+	ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
+				       &phy_data);
 	if (ret_val)
 		goto out;
 
@@ -773,7 +772,8 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
 	 * duplex.
 	 */
 	phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
-	ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
+	ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
+					phy_data);
 
 out:
 	return ret_val;
@@ -826,21 +826,20 @@ out:
  *  Retrieve the current speed and duplex configuration.
  **/
 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
-                                              u16 *duplex)
+					      u16 *duplex)
 {
 	s32 ret_val;
 
 	DEBUGFUNC("e1000_get_link_up_info_80003es2lan");
 
 	if (hw->phy.media_type == e1000_media_type_copper) {
-		ret_val = e1000_get_speed_and_duplex_copper_generic(hw,
-		                                                    speed,
-		                                                    duplex);
+		ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
+								    duplex);
 		hw->phy.ops.cfg_on_link_up(hw);
 	} else {
 		ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,
-		                                                  speed,
-		                                                  duplex);
+								  speed,
+								  duplex);
 	}
 
 	return ret_val;
@@ -939,21 +938,21 @@ static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
 
 	/* Disable IBIST slave mode (far-end loopback) */
 	e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
-	                                &kum_reg_data);
+					&kum_reg_data);
 	kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
 	e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
-	                                 kum_reg_data);
+					 kum_reg_data);
 
 	/* Set the transmit descriptor write-back policy */
 	reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
 	reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
-	           E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
+		   E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 	E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
 
 	/* ...for both queues. */
 	reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
 	reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
-	           E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
+		   E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 	E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
 
 	/* Enable retransmit on late collisions */
@@ -981,9 +980,9 @@ static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
 	hw->dev_spec._80003es2lan.mdic_wa_enable = TRUE;
 
 	ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
-	                              E1000_KMRNCTRLSTA_OFFSET >>
-	                              E1000_KMRNCTRLSTA_OFFSET_SHIFT,
-	                              &i);
+						 E1000_KMRNCTRLSTA_OFFSET >>
+						 E1000_KMRNCTRLSTA_OFFSET_SHIFT,
+						 &i);
 	if (!ret_val) {
 		if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
 		     E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
@@ -1056,11 +1055,7 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
 
 	DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan");
 
-	if (phy->reset_disable)
-		goto skip_reset;
-
-	ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
-				     &data);
+	ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
 	if (ret_val)
 		goto out;
 
@@ -1068,8 +1063,7 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
 	/* Use 25MHz for both link down and 1000Base-T for Tx clock. */
 	data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
 
-	ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
-				      data);
+	ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
 	if (ret_val)
 		goto out;
 
@@ -1122,7 +1116,6 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
 		goto out;
 	}
 
-skip_reset:
 	/* Bypass Rx and Tx FIFO's */
 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
 					E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
@@ -1132,14 +1125,12 @@ skip_reset:
 		goto out;
 
 	ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
-	                              E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
-	                              &data);
+				E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, &data);
 	if (ret_val)
 		goto out;
 	data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
-	                               E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
-	                               data);
+				E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, data);
 	if (ret_val)
 		goto out;
 
@@ -1169,18 +1160,18 @@ skip_reset:
 		/* Enable Electrical Idle on the PHY */
 		data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
 		ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
-		                                data);
+						data);
 		if (ret_val)
 			goto out;
 
 		ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
-		                               &data);
+					       &data);
 		if (ret_val)
 			goto out;
 
 		data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
 		ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
-		                                data);
+						data);
 		if (ret_val)
 			goto out;
 	}
@@ -1228,27 +1219,25 @@ static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
 	 * polling the phy; this fixes erroneous timeouts at 10Mbps.
 	 */
 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
-	                                           0xFFFF);
+						   0xFFFF);
 	if (ret_val)
 		goto out;
 	ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
-	                                          &reg_data);
+						  &reg_data);
 	if (ret_val)
 		goto out;
 	reg_data |= 0x3F;
 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
-	                                           reg_data);
+						   reg_data);
 	if (ret_val)
 		goto out;
 	ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
-	                              E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
-	                              &reg_data);
+				E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, &reg_data);
 	if (ret_val)
 		goto out;
 	reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
-	                               E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
-	                               reg_data);
+				E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, reg_data);
 	if (ret_val)
 		goto out;
 
@@ -1279,9 +1268,8 @@ static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
 	DEBUGFUNC("e1000_configure_on_link_up");
 
 	if (hw->phy.media_type == e1000_media_type_copper) {
-		ret_val = e1000_get_speed_and_duplex_copper_generic(hw,
-		                                                    &speed,
-		                                                    &duplex);
+		ret_val = e1000_get_speed_and_duplex_copper_generic(hw, &speed,
+								    &duplex);
 		if (ret_val)
 			goto out;
 
@@ -1314,8 +1302,8 @@ static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
 
 	reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
-	                               E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
-	                               reg_data);
+				       E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
+				       reg_data);
 	if (ret_val)
 		goto out;
 
@@ -1327,12 +1315,12 @@ static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
 
 	do {
 		ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
-		                               &reg_data);
+					       &reg_data);
 		if (ret_val)
 			goto out;
 
 		ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
-		                               &reg_data2);
+					       &reg_data2);
 		if (ret_val)
 			goto out;
 		i++;
@@ -1343,7 +1331,8 @@ static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
 	else
 		reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
 
-	ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
+	ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
+					reg_data);
 
 out:
 	return ret_val;
@@ -1367,8 +1356,7 @@ static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
 
 	reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
-	                               E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
-	                               reg_data);
+				E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, reg_data);
 	if (ret_val)
 		goto out;
 
@@ -1380,19 +1368,20 @@ static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
 
 	do {
 		ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
-		                               &reg_data);
+					       &reg_data);
 		if (ret_val)
 			goto out;
 
 		ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
-		                               &reg_data2);
+					       &reg_data2);
 		if (ret_val)
 			goto out;
 		i++;
 	} while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
 
 	reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
-	ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
+	ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
+					reg_data);
 
 out:
 	return ret_val;
@@ -1409,7 +1398,7 @@ out:
  *  Release the semaphore before exiting.
  **/
 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
-                                           u16 *data)
+					   u16 *data)
 {
 	u32 kmrnctrlsta;
 	s32 ret_val = E1000_SUCCESS;
@@ -1421,8 +1410,9 @@ static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
 		goto out;
 
 	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
-	               E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
+		       E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
 	E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
+	E1000_WRITE_FLUSH(hw);
 
 	usec_delay(2);
 
@@ -1446,7 +1436,7 @@ out:
  *  before exiting.
  **/
 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
-                                            u16 data)
+					    u16 data)
 {
 	u32 kmrnctrlsta;
 	s32 ret_val = E1000_SUCCESS;
@@ -1458,8 +1448,9 @@ static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
 		goto out;
 
 	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
-	               E1000_KMRNCTRLSTA_OFFSET) | data;
+		       E1000_KMRNCTRLSTA_OFFSET) | data;
 	E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
+	E1000_WRITE_FLUSH(hw);
 
 	usec_delay(2);
 
diff --git a/sys/dev/e1000/e1000_80003es2lan.h b/sys/dev/e1000/e1000_80003es2lan.h
index 7d147f1..157468e 100644
--- a/sys/dev/e1000/e1000_80003es2lan.h
+++ b/sys/dev/e1000/e1000_80003es2lan.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -35,48 +35,47 @@
 #ifndef _E1000_80003ES2LAN_H_
 #define _E1000_80003ES2LAN_H_
 
-#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL       0x00
-#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL        0x02
-#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL         0x10
-#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE  0x1F
+#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL	0x00
+#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL	0x02
+#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL	0x10
+#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE	0x1F
 
-#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS    0x0008
-#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS    0x0800
-#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING   0x0010
+#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS	0x0008
+#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS	0x0800
+#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING	0x0010
 
 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
-#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT   0x0000
-#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE          0x2000
+#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT	0x0000
+#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE		0x2000
 
-#define E1000_KMRNCTRLSTA_OPMODE_MASK            0x000C
-#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO     0x0004
+#define E1000_KMRNCTRLSTA_OPMODE_MASK		0x000C
+#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO	0x0004
 
 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
-#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN        0x00010000
+#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN	0x00010000
 
-#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN       0x8
-#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN     0x9
+#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN	0x8
+#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN	0x9
 
 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
-#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE  0x0002 /* 1=Reversal Disabled */
-#define GG82563_PSCR_CROSSOVER_MODE_MASK        0x0060
-#define GG82563_PSCR_CROSSOVER_MODE_MDI         0x0000 /* 00=Manual MDI */
-#define GG82563_PSCR_CROSSOVER_MODE_MDIX        0x0020 /* 01=Manual MDIX */
-#define GG82563_PSCR_CROSSOVER_MODE_AUTO        0x0060 /* 11=Auto crossover */
+#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE	0x0002 /* 1=Reversal Disabled */
+#define GG82563_PSCR_CROSSOVER_MODE_MASK	0x0060
+#define GG82563_PSCR_CROSSOVER_MODE_MDI		0x0000 /* 00=Manual MDI */
+#define GG82563_PSCR_CROSSOVER_MODE_MDIX	0x0020 /* 01=Manual MDIX */
+#define GG82563_PSCR_CROSSOVER_MODE_AUTO	0x0060 /* 11=Auto crossover */
 
 /* PHY Specific Control Register 2 (Page 0, Register 26) */
-#define GG82563_PSCR2_REVERSE_AUTO_NEG          0x2000
-                                               /* 1=Reverse Auto-Negotiation */
+#define GG82563_PSCR2_REVERSE_AUTO_NEG		0x2000 /* 1=Reverse Auto-Nego */
 
 /* MAC Specific Control Register (Page 2, Register 21) */
 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
-#define GG82563_MSCR_TX_CLK_MASK                0x0007
-#define GG82563_MSCR_TX_CLK_10MBPS_2_5          0x0004
-#define GG82563_MSCR_TX_CLK_100MBPS_25          0x0005
-#define GG82563_MSCR_TX_CLK_1000MBPS_2_5        0x0006
-#define GG82563_MSCR_TX_CLK_1000MBPS_25         0x0007
+#define GG82563_MSCR_TX_CLK_MASK		0x0007
+#define GG82563_MSCR_TX_CLK_10MBPS_2_5		0x0004
+#define GG82563_MSCR_TX_CLK_100MBPS_25		0x0005
+#define GG82563_MSCR_TX_CLK_1000MBPS_2_5	0x0006
+#define GG82563_MSCR_TX_CLK_1000MBPS_25		0x0007
 
-#define GG82563_MSCR_ASSERT_CRS_ON_TX           0x0010 /* 1=Assert */
+#define GG82563_MSCR_ASSERT_CRS_ON_TX		0x0010 /* 1=Assert */
 
 /* DSP Distance Register (Page 5, Register 26) */
 /*
@@ -86,19 +85,19 @@
  * 3 = 110-140M
  * 4 = >140M
  */
-#define GG82563_DSPD_CABLE_LENGTH               0x0007
+#define GG82563_DSPD_CABLE_LENGTH		0x0007
 
 /* Kumeran Mode Control Register (Page 193, Register 16) */
-#define GG82563_KMCR_PASS_FALSE_CARRIER         0x0800
+#define GG82563_KMCR_PASS_FALSE_CARRIER		0x0800
 
 /* Max number of times Kumeran read/write should be validated */
-#define GG82563_MAX_KMRN_RETRY                  0x5
+#define GG82563_MAX_KMRN_RETRY			0x5
 
 /* Power Management Control Register (Page 193, Register 20) */
-#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE     0x0001
-                                          /* 1=Enable SERDES Electrical Idle */
+/* 1=Enable SERDES Electrical Idle */
+#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE	0x0001
 
 /* In-Band Control Register (Page 194, Register 18) */
-#define GG82563_ICR_DIS_PADDING                 0x0010 /* Disable Padding */
+#define GG82563_ICR_DIS_PADDING			0x0010 /* Disable Padding */
 
 #endif
diff --git a/sys/dev/e1000/e1000_82540.c b/sys/dev/e1000/e1000_82540.c
index 35018ce..141b92e 100644
--- a/sys/dev/e1000/e1000_82540.c
+++ b/sys/dev/e1000/e1000_82540.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -68,23 +68,23 @@ static s32 e1000_init_phy_params_82540(struct e1000_hw *hw)
 	struct e1000_phy_info *phy = &hw->phy;
 	s32 ret_val = E1000_SUCCESS;
 
-	phy->addr                      = 1;
-	phy->autoneg_mask              = AUTONEG_ADVERTISE_SPEED_DEFAULT;
-	phy->reset_delay_us            = 10000;
-	phy->type                      = e1000_phy_m88;
+	phy->addr		= 1;
+	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;
+	phy->reset_delay_us	= 10000;
+	phy->type		= e1000_phy_m88;
 
 	/* Function Pointers */
-	phy->ops.check_polarity        = e1000_check_polarity_m88;
-	phy->ops.commit                = e1000_phy_sw_reset_generic;
-	phy->ops.force_speed_duplex    = e1000_phy_force_speed_duplex_m88;
-	phy->ops.get_cable_length      = e1000_get_cable_length_m88;
-	phy->ops.get_cfg_done          = e1000_get_cfg_done_generic;
-	phy->ops.read_reg              = e1000_read_phy_reg_m88;
-	phy->ops.reset                 = e1000_phy_hw_reset_generic;
-	phy->ops.write_reg             = e1000_write_phy_reg_m88;
-	phy->ops.get_info              = e1000_get_phy_info_m88;
-	phy->ops.power_up              = e1000_power_up_phy_copper;
-	phy->ops.power_down            = e1000_power_down_phy_copper_82540;
+	phy->ops.check_polarity	= e1000_check_polarity_m88;
+	phy->ops.commit		= e1000_phy_sw_reset_generic;
+	phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
+	phy->ops.get_cable_length = e1000_get_cable_length_m88;
+	phy->ops.get_cfg_done	= e1000_get_cfg_done_generic;
+	phy->ops.read_reg	= e1000_read_phy_reg_m88;
+	phy->ops.reset		= e1000_phy_hw_reset_generic;
+	phy->ops.write_reg	= e1000_write_phy_reg_m88;
+	phy->ops.get_info	= e1000_get_phy_info_m88;
+	phy->ops.power_up	= e1000_power_up_phy_copper;
+	phy->ops.power_down	= e1000_power_down_phy_copper_82540;
 
 	ret_val = e1000_get_phy_id(hw);
 	if (ret_val)
@@ -121,32 +121,32 @@ static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw)
 
 	DEBUGFUNC("e1000_init_nvm_params_82540");
 
-	nvm->type               = e1000_nvm_eeprom_microwire;
-	nvm->delay_usec         = 50;
-	nvm->opcode_bits        = 3;
+	nvm->type = e1000_nvm_eeprom_microwire;
+	nvm->delay_usec = 50;
+	nvm->opcode_bits = 3;
 	switch (nvm->override) {
 	case e1000_nvm_override_microwire_large:
-		nvm->address_bits       = 8;
-		nvm->word_size          = 256;
+		nvm->address_bits = 8;
+		nvm->word_size = 256;
 		break;
 	case e1000_nvm_override_microwire_small:
-		nvm->address_bits       = 6;
-		nvm->word_size          = 64;
+		nvm->address_bits = 6;
+		nvm->word_size = 64;
 		break;
 	default:
-		nvm->address_bits       = eecd & E1000_EECD_SIZE ? 8 : 6;
-		nvm->word_size          = eecd & E1000_EECD_SIZE ? 256 : 64;
+		nvm->address_bits = eecd & E1000_EECD_SIZE ? 8 : 6;
+		nvm->word_size = eecd & E1000_EECD_SIZE ? 256 : 64;
 		break;
 	}
 
 	/* Function Pointers */
-	nvm->ops.acquire            = e1000_acquire_nvm_generic;
-	nvm->ops.read               = e1000_read_nvm_microwire;
-	nvm->ops.release            = e1000_release_nvm_generic;
-	nvm->ops.update             = e1000_update_nvm_checksum_generic;
-	nvm->ops.valid_led_default  = e1000_valid_led_default_generic;
-	nvm->ops.validate           = e1000_validate_nvm_checksum_generic;
-	nvm->ops.write              = e1000_write_nvm_microwire;
+	nvm->ops.acquire	= e1000_acquire_nvm_generic;
+	nvm->ops.read		= e1000_read_nvm_microwire;
+	nvm->ops.release	= e1000_release_nvm_generic;
+	nvm->ops.update		= e1000_update_nvm_checksum_generic;
+	nvm->ops.valid_led_default = e1000_valid_led_default_generic;
+	nvm->ops.validate	= e1000_validate_nvm_checksum_generic;
+	nvm->ops.write		= e1000_write_nvm_microwire;
 
 	return E1000_SUCCESS;
 }
@@ -198,9 +198,9 @@ static s32 e1000_init_mac_params_82540(struct e1000_hw *hw)
 	mac->ops.setup_link = e1000_setup_link_generic;
 	/* physical interface setup */
 	mac->ops.setup_physical_interface =
-	        (hw->phy.media_type == e1000_media_type_copper)
-	                ? e1000_setup_copper_link_82540
-	                : e1000_setup_fiber_serdes_link_82540;
+		(hw->phy.media_type == e1000_media_type_copper)
+			? e1000_setup_copper_link_82540
+			: e1000_setup_fiber_serdes_link_82540;
 	/* check for link */
 	switch (hw->phy.media_type) {
 	case e1000_media_type_copper:
@@ -219,9 +219,9 @@ static s32 e1000_init_mac_params_82540(struct e1000_hw *hw)
 	}
 	/* link info */
 	mac->ops.get_link_up_info =
-	        (hw->phy.media_type == e1000_media_type_copper)
-	                ? e1000_get_speed_and_duplex_copper_generic
-	                : e1000_get_speed_and_duplex_fiber_serdes_generic;
+		(hw->phy.media_type == e1000_media_type_copper)
+			? e1000_get_speed_and_duplex_copper_generic
+			: e1000_get_speed_and_duplex_fiber_serdes_generic;
 	/* multicast address update */
 	mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 	/* writing VFTA */
@@ -374,7 +374,7 @@ static s32 e1000_init_hw_82540(struct e1000_hw *hw)
 
 	txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
 	txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
-	         E1000_TXDCTL_FULL_TX_DESC_WB;
+		  E1000_TXDCTL_FULL_TX_DESC_WB;
 	E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
 
 	/*
@@ -427,11 +427,13 @@ static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw)
 
 	if (hw->mac.type == e1000_82545_rev_3 ||
 	    hw->mac.type == e1000_82546_rev_3) {
-		ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &data);
+		ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
+					       &data);
 		if (ret_val)
 			goto out;
 		data |= 0x00000008;
-		ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, data);
+		ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
+						data);
 		if (ret_val)
 			goto out;
 	}
@@ -508,9 +510,8 @@ static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw)
 	if (nvm_data != NVM_RESERVED_WORD) {
 		/* Adjust serdes output amplitude only. */
 		nvm_data &= NVM_SERDES_AMPLITUDE_MASK;
-		ret_val = hw->phy.ops.write_reg(hw,
-		                             M88E1000_PHY_EXT_CTRL,
-		                             nvm_data);
+		ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_EXT_CTRL,
+						nvm_data);
 		if (ret_val)
 			goto out;
 	}
@@ -535,9 +536,8 @@ static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw)
 
 	/* Set PHY register 30, page 5, bit 8 to 0 */
 
-	ret_val = hw->phy.ops.read_reg(hw,
-	                            M88E1000_PHY_PAGE_SELECT,
-	                            &default_page);
+	ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_PAGE_SELECT,
+				       &default_page);
 	if (ret_val)
 		goto out;
 
@@ -570,7 +570,7 @@ static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw)
 		goto out;
 
 	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
-	                              default_page);
+					default_page);
 
 out:
 	return ret_val;
@@ -587,7 +587,6 @@ out:
  **/
 static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw)
 {
-	struct e1000_phy_info *phy = &hw->phy;
 	s32 ret_val = E1000_SUCCESS;
 	u16 nvm_data;
 
@@ -604,20 +603,18 @@ static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw)
 
 	if ((nvm_data != NVM_RESERVED_WORD) && (nvm_data & NVM_PHY_CLASS_A)) {
 		ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
-		                              0x000B);
+						0x000B);
 		if (ret_val) {
 			ret_val = -E1000_ERR_PHY;
 			goto out;
 		}
-		ret_val = hw->phy.ops.write_reg(hw,
-		                              M88E1000_PHY_GEN_CONTROL,
-		                              0x8104);
+		ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL,
+						0x8104);
 		if (ret_val) {
 			ret_val = -E1000_ERR_PHY;
 			goto out;
 		}
 
-		phy->reset_disable = FALSE;
 	}
 
 out:
diff --git a/sys/dev/e1000/e1000_82541.c b/sys/dev/e1000/e1000_82541.c
index 7c9605b..d13611e 100644
--- a/sys/dev/e1000/e1000_82541.c
+++ b/sys/dev/e1000/e1000_82541.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -300,7 +300,7 @@ void e1000_init_function_pointers_82541(struct e1000_hw *hw)
  **/
 static s32 e1000_reset_hw_82541(struct e1000_hw *hw)
 {
-	u32 ledctl, ctrl, manc;
+	u32 ledctl, ctrl, icr, manc;
 
 	DEBUGFUNC("e1000_reset_hw_82541");
 
@@ -364,7 +364,7 @@ static s32 e1000_reset_hw_82541(struct e1000_hw *hw)
 	E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
 
 	/* Clear any pending interrupt events. */
-	E1000_READ_REG(hw, E1000_ICR);
+	icr = E1000_READ_REG(hw, E1000_ICR);
 
 	return E1000_SUCCESS;
 }
@@ -390,7 +390,7 @@ static s32 e1000_init_hw_82541(struct e1000_hw *hw)
 		DEBUGOUT("Error initializing identification LED\n");
 		/* This is not fatal and we should not stop init due to this */
 	}
-
+        
 	/* Storing the Speed Power Down  value for later use */
 	ret_val = hw->phy.ops.read_reg(hw,
 	                               IGP01E1000_GMII_FIFO,
@@ -549,8 +549,6 @@ static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw)
 	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
 
-	hw->phy.reset_disable = FALSE;
-
 	/* Earlier revs of the IGP phy require us to force MDI. */
 	if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) {
 		dev_spec->dsp_config = e1000_dsp_config_disabled;
diff --git a/sys/dev/e1000/e1000_82543.c b/sys/dev/e1000/e1000_82543.c
index 2cf6029..1507da5 100644
--- a/sys/dev/e1000/e1000_82543.c
+++ b/sys/dev/e1000/e1000_82543.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -901,7 +901,7 @@ static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw)
  **/
 static s32 e1000_reset_hw_82543(struct e1000_hw *hw)
 {
-	u32 ctrl;
+	u32 ctrl, icr;
 	s32 ret_val = E1000_SUCCESS;
 
 	DEBUGFUNC("e1000_reset_hw_82543");
@@ -943,7 +943,7 @@ static s32 e1000_reset_hw_82543(struct e1000_hw *hw)
 
 	/* Masking off and clearing any pending interrupts */
 	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
-	E1000_READ_REG(hw, E1000_ICR);
+	icr = E1000_READ_REG(hw, E1000_ICR);
 
 	return ret_val;
 }
@@ -1079,7 +1079,6 @@ static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw)
 		ret_val = hw->phy.ops.reset(hw);
 		if (ret_val)
 			goto out;
-		hw->phy.reset_disable = FALSE;
 	} else {
 		ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
 		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
diff --git a/sys/dev/e1000/e1000_82571.c b/sys/dev/e1000/e1000_82571.c
index 5d5cbaa..a2982b9 100644
--- a/sys/dev/e1000/e1000_82571.c
+++ b/sys/dev/e1000/e1000_82571.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -57,12 +57,12 @@ static s32  e1000_init_mac_params_82571(struct e1000_hw *hw);
 static s32  e1000_acquire_nvm_82571(struct e1000_hw *hw);
 static void e1000_release_nvm_82571(struct e1000_hw *hw);
 static s32  e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
-                                  u16 words, u16 *data);
+				  u16 words, u16 *data);
 static s32  e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
 static s32  e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
 static s32  e1000_get_cfg_done_82571(struct e1000_hw *hw);
 static s32  e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
-                                          bool active);
+					  bool active);
 static s32  e1000_reset_hw_82571(struct e1000_hw *hw);
 static s32  e1000_init_hw_82571(struct e1000_hw *hw);
 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
@@ -83,12 +83,12 @@ static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
 static s32  e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
 static s32  e1000_set_d0_lplu_state_82574(struct e1000_hw *hw,
-                                          bool active);
+					  bool active);
 static s32  e1000_set_d3_lplu_state_82574(struct e1000_hw *hw,
-                                          bool active);
+					  bool active);
 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
 static s32  e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
-                                       u16 words, u16 *data);
+				       u16 words, u16 *data);
 static s32  e1000_read_mac_addr_82571(struct e1000_hw *hw);
 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
 
@@ -108,61 +108,61 @@ static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
 		goto out;
 	}
 
-	phy->addr                        = 1;
-	phy->autoneg_mask                = AUTONEG_ADVERTISE_SPEED_DEFAULT;
-	phy->reset_delay_us              = 100;
+	phy->addr			= 1;
+	phy->autoneg_mask		= AUTONEG_ADVERTISE_SPEED_DEFAULT;
+	phy->reset_delay_us		= 100;
 
-	phy->ops.check_reset_block       = e1000_check_reset_block_generic;
-	phy->ops.reset                   = e1000_phy_hw_reset_generic;
-	phy->ops.set_d0_lplu_state       = e1000_set_d0_lplu_state_82571;
-	phy->ops.set_d3_lplu_state       = e1000_set_d3_lplu_state_generic;
-	phy->ops.power_up                = e1000_power_up_phy_copper;
-	phy->ops.power_down              = e1000_power_down_phy_copper_82571;
+	phy->ops.check_reset_block	= e1000_check_reset_block_generic;
+	phy->ops.reset			= e1000_phy_hw_reset_generic;
+	phy->ops.set_d0_lplu_state	= e1000_set_d0_lplu_state_82571;
+	phy->ops.set_d3_lplu_state	= e1000_set_d3_lplu_state_generic;
+	phy->ops.power_up		= e1000_power_up_phy_copper;
+	phy->ops.power_down		= e1000_power_down_phy_copper_82571;
 
 	switch (hw->mac.type) {
 	case e1000_82571:
 	case e1000_82572:
-		phy->type                   = e1000_phy_igp_2;
-		phy->ops.get_cfg_done       = e1000_get_cfg_done_82571;
-		phy->ops.get_info           = e1000_get_phy_info_igp;
-		phy->ops.check_polarity     = e1000_check_polarity_igp;
+		phy->type		= e1000_phy_igp_2;
+		phy->ops.get_cfg_done	= e1000_get_cfg_done_82571;
+		phy->ops.get_info	= e1000_get_phy_info_igp;
+		phy->ops.check_polarity	= e1000_check_polarity_igp;
 		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
-		phy->ops.get_cable_length   = e1000_get_cable_length_igp_2;
-		phy->ops.read_reg           = e1000_read_phy_reg_igp;
-		phy->ops.write_reg          = e1000_write_phy_reg_igp;
-		phy->ops.acquire            = e1000_get_hw_semaphore_82571;
-		phy->ops.release            = e1000_put_hw_semaphore_82571;
+		phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
+		phy->ops.read_reg	= e1000_read_phy_reg_igp;
+		phy->ops.write_reg	= e1000_write_phy_reg_igp;
+		phy->ops.acquire	= e1000_get_hw_semaphore_82571;
+		phy->ops.release	= e1000_put_hw_semaphore_82571;
 		break;
 	case e1000_82573:
-		phy->type                   = e1000_phy_m88;
-		phy->ops.get_cfg_done       = e1000_get_cfg_done_generic;
-		phy->ops.get_info           = e1000_get_phy_info_m88;
-		phy->ops.check_polarity     = e1000_check_polarity_m88;
-		phy->ops.commit             = e1000_phy_sw_reset_generic;
+		phy->type		= e1000_phy_m88;
+		phy->ops.get_cfg_done	= e1000_get_cfg_done_generic;
+		phy->ops.get_info	= e1000_get_phy_info_m88;
+		phy->ops.check_polarity	= e1000_check_polarity_m88;
+		phy->ops.commit		= e1000_phy_sw_reset_generic;
 		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
-		phy->ops.get_cable_length   = e1000_get_cable_length_m88;
-		phy->ops.read_reg           = e1000_read_phy_reg_m88;
-		phy->ops.write_reg          = e1000_write_phy_reg_m88;
-		phy->ops.acquire            = e1000_get_hw_semaphore_82571;
-		phy->ops.release            = e1000_put_hw_semaphore_82571;
+		phy->ops.get_cable_length = e1000_get_cable_length_m88;
+		phy->ops.read_reg	= e1000_read_phy_reg_m88;
+		phy->ops.write_reg	= e1000_write_phy_reg_m88;
+		phy->ops.acquire	= e1000_get_hw_semaphore_82571;
+		phy->ops.release	= e1000_put_hw_semaphore_82571;
 		break;
 	case e1000_82574:
 	case e1000_82583:
 		E1000_MUTEX_INIT(&hw->dev_spec._82571.swflag_mutex);
 
-		phy->type                   = e1000_phy_bm;
-		phy->ops.get_cfg_done       = e1000_get_cfg_done_generic;
-		phy->ops.get_info           = e1000_get_phy_info_m88;
-		phy->ops.check_polarity     = e1000_check_polarity_m88;
-		phy->ops.commit             = e1000_phy_sw_reset_generic;
+		phy->type		= e1000_phy_bm;
+		phy->ops.get_cfg_done	= e1000_get_cfg_done_generic;
+		phy->ops.get_info	= e1000_get_phy_info_m88;
+		phy->ops.check_polarity	= e1000_check_polarity_m88;
+		phy->ops.commit		= e1000_phy_sw_reset_generic;
 		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
-		phy->ops.get_cable_length   = e1000_get_cable_length_m88;
-		phy->ops.read_reg           = e1000_read_phy_reg_bm2;
-		phy->ops.write_reg          = e1000_write_phy_reg_bm2;
-		phy->ops.acquire            = e1000_get_hw_semaphore_82574;
-		phy->ops.release            = e1000_put_hw_semaphore_82574;
-		phy->ops.set_d0_lplu_state  = e1000_set_d0_lplu_state_82574;
-		phy->ops.set_d3_lplu_state  = e1000_set_d3_lplu_state_82574;
+		phy->ops.get_cable_length = e1000_get_cable_length_m88;
+		phy->ops.read_reg	= e1000_read_phy_reg_bm2;
+		phy->ops.write_reg	= e1000_write_phy_reg_bm2;
+		phy->ops.acquire	= e1000_get_hw_semaphore_82574;
+		phy->ops.release	= e1000_put_hw_semaphore_82574;
+		phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
+		phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
 		break;
 	default:
 		ret_val = -E1000_ERR_PHY;
@@ -253,7 +253,7 @@ static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 	default:
 		nvm->type = e1000_nvm_eeprom_spi;
 		size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
-		                  E1000_EECD_SIZE_EX_SHIFT);
+			     E1000_EECD_SIZE_EX_SHIFT);
 		/*
 		 * Added to a constant, "size" becomes the left-shift value
 		 * for setting word_size.
@@ -263,7 +263,7 @@ static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 		/* EEPROM access above 16k is unsupported */
 		if (size > 14)
 			size = 14;
-		nvm->word_size	= 1 << size;
+		nvm->word_size = 1 << size;
 		break;
 	}
 
@@ -279,11 +279,11 @@ static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 		nvm->ops.release = e1000_release_nvm_82571;
 		break;
 	}
-	nvm->ops.read          = e1000_read_nvm_eerd;
-	nvm->ops.update        = e1000_update_nvm_checksum_82571;
-	nvm->ops.validate      = e1000_validate_nvm_checksum_82571;
+	nvm->ops.read = e1000_read_nvm_eerd;
+	nvm->ops.update = e1000_update_nvm_checksum_82571;
+	nvm->ops.validate = e1000_validate_nvm_checksum_82571;
 	nvm->ops.valid_led_default = e1000_valid_led_default_82571;
-	nvm->ops.write         = e1000_write_nvm_82571;
+	nvm->ops.write = e1000_write_nvm_82571;
 
 	return E1000_SUCCESS;
 }
@@ -363,8 +363,6 @@ static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
 	mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
 	/* ID LED init */
 	mac->ops.id_led_init = e1000_id_led_init_generic;
-	/* blink LED */
-	mac->ops.blink_led = e1000_blink_led_generic;
 	/* setup LED */
 	mac->ops.setup_led = e1000_setup_led_generic;
 	/* cleanup LED */
@@ -380,6 +378,7 @@ static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
 		mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 		mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 		mac->ops.led_on = e1000_led_on_generic;
+		mac->ops.blink_led = e1000_blink_led_generic;
 
 		/* FWSM register */
 		mac->has_fwsm = TRUE;
@@ -387,9 +386,8 @@ static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
 		 * ARC supported; valid only if manageability features are
 		 * enabled.
 		 */
-		mac->arc_subsystem_valid =
-			(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
-			? TRUE : FALSE;
+		mac->arc_subsystem_valid = (E1000_READ_REG(hw, E1000_FWSM) &
+					   E1000_FWSM_MODE_MASK) ? TRUE : FALSE;
 		break;
 	case e1000_82574:
 	case e1000_82583:
@@ -400,6 +398,7 @@ static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
 	default:
 		mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 		mac->ops.led_on = e1000_led_on_generic;
+		mac->ops.blink_led = e1000_blink_led_generic;
 
 		/* FWSM register */
 		mac->has_fwsm = TRUE;
@@ -420,8 +419,8 @@ static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
 
 		if (!(swsm2 & E1000_SWSM2_LOCK)) {
 			/* Only do this for the first interface on this card */
-			E1000_WRITE_REG(hw, E1000_SWSM2,
-			    swsm2 | E1000_SWSM2_LOCK);
+			E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 |
+					E1000_SWSM2_LOCK);
 			force_clear_smbi = TRUE;
 		} else
 			force_clear_smbi = FALSE;
@@ -746,8 +745,8 @@ static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
 	if (!active) {
 		data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
 	} else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
-	           (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
-	           (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
+		   (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
+		   (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
 		data |= E1000_PHY_CTRL_NOND0A_LPLU;
 	}
 
@@ -816,7 +815,7 @@ static void e1000_release_nvm_82571(struct e1000_hw *hw)
  *  EEPROM will most likely contain an invalid checksum.
  **/
 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
-                                 u16 *data)
+				 u16 *data)
 {
 	s32 ret_val = E1000_SUCCESS;
 
@@ -941,7 +940,7 @@ static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
  *  EEPROM will most likely contain an invalid checksum.
  **/
 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
-                                      u16 words, u16 *data)
+				      u16 words, u16 *data)
 {
 	struct e1000_nvm_info *nvm = &hw->nvm;
 	u32 i, eewr = 0;
@@ -1039,22 +1038,22 @@ static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
 	if (active) {
 		data |= IGP02E1000_PM_D0_LPLU;
 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
-		                             data);
+					     data);
 		if (ret_val)
 			goto out;
 
 		/* When LPLU is enabled, we should disable SmartSpeed */
 		ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-		                            &data);
+					    &data);
 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 		ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-		                             data);
+					     data);
 		if (ret_val)
 			goto out;
 	} else {
 		data &= ~IGP02E1000_PM_D0_LPLU;
 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
-		                             data);
+					     data);
 		/*
 		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 		 * during Dx states where the power conservation is most
@@ -1063,28 +1062,28 @@ static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
 		 */
 		if (phy->smart_speed == e1000_smart_speed_on) {
 			ret_val = phy->ops.read_reg(hw,
-			                            IGP01E1000_PHY_PORT_CONFIG,
-			                            &data);
+						    IGP01E1000_PHY_PORT_CONFIG,
+						    &data);
 			if (ret_val)
 				goto out;
 
 			data |= IGP01E1000_PSCFR_SMART_SPEED;
 			ret_val = phy->ops.write_reg(hw,
-			                             IGP01E1000_PHY_PORT_CONFIG,
-			                             data);
+						     IGP01E1000_PHY_PORT_CONFIG,
+						     data);
 			if (ret_val)
 				goto out;
 		} else if (phy->smart_speed == e1000_smart_speed_off) {
 			ret_val = phy->ops.read_reg(hw,
-			                            IGP01E1000_PHY_PORT_CONFIG,
-			                            &data);
+						    IGP01E1000_PHY_PORT_CONFIG,
+						    &data);
 			if (ret_val)
 				goto out;
 
 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 			ret_val = phy->ops.write_reg(hw,
-			                             IGP01E1000_PHY_PORT_CONFIG,
-			                             data);
+						     IGP01E1000_PHY_PORT_CONFIG,
+						     data);
 			if (ret_val)
 				goto out;
 		}
@@ -1255,8 +1254,7 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw)
 	/* Set the transmit descriptor write-back policy */
 	reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
 	reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
-	           E1000_TXDCTL_FULL_TX_DESC_WB |
-	           E1000_TXDCTL_COUNT_DESC;
+		   E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 	E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
 
 	/* ...for both queues. */
@@ -1273,8 +1271,8 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw)
 	default:
 		reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
 		reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
-		           E1000_TXDCTL_FULL_TX_DESC_WB |
-		           E1000_TXDCTL_COUNT_DESC;
+			   E1000_TXDCTL_FULL_TX_DESC_WB |
+			   E1000_TXDCTL_COUNT_DESC;
 		E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
 		break;
 	}
@@ -1320,6 +1318,10 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
 	case e1000_82572:
 		reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
 		break;
+	case e1000_82574:
+	case e1000_82583:
+		reg |= (1 << 26);
+		break;
 	default:
 		break;
 	}
@@ -1527,12 +1529,12 @@ bool e1000_check_phy_82574(struct e1000_hw *hw)
 	 * read the Base1000T status register If both are max then PHY is hung.
 	 */
 	ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
-	                               &receive_errors);
+				       &receive_errors);
 	if (ret_val)
 		goto out;
 	if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
 		ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
-		                               &status_1kbt);
+					       &status_1kbt);
 		if (ret_val)
 			goto out;
 		if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
@@ -1640,7 +1642,8 @@ static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
 		 * mode.  This prevents drivers from twiddling their thumbs
 		 * if another tool failed to take it out of loopback mode.
 		 */
-		E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
+		E1000_WRITE_REG(hw, E1000_SCTL,
+				E1000_SCTL_DISABLE_SERDES_LOOPBACK);
 		break;
 	default:
 		break;
@@ -1664,7 +1667,7 @@ static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
  *
  *  1) down
  *  2) autoneg_progress
- *  3) autoneg_complete (the link sucessfully autonegotiated)
+ *  3) autoneg_complete (the link successfully autonegotiated)
  *  4) forced_up (the link has been forced up, it did not autonegotiate)
  *
  **/
@@ -1763,7 +1766,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
 					break;
 				}
 				mac->serdes_link_state =
-				e1000_serdes_link_forced_up;
+						e1000_serdes_link_forced_up;
 				mac->serdes_has_link = TRUE;
 				DEBUGOUT("AN_PROG   -> FORCED_UP\n");
 			}
@@ -1777,10 +1780,10 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
 			 * up.
 			 */
 			E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
-			E1000_WRITE_REG(hw, E1000_CTRL,
-			    (ctrl & ~E1000_CTRL_SLU));
+			E1000_WRITE_REG(hw, E1000_CTRL, (ctrl &
+					~E1000_CTRL_SLU));
 			mac->serdes_link_state =
-			    e1000_serdes_link_autoneg_progress;
+					e1000_serdes_link_autoneg_progress;
 			mac->serdes_has_link = FALSE;
 			DEBUGOUT("DOWN      -> AN_PROG\n");
 			break;
@@ -1804,7 +1807,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
 				      (rxcw & E1000_RXCW_C))) {
 					mac->serdes_has_link = FALSE;
 					mac->serdes_link_state =
-					    e1000_serdes_link_down;
+							e1000_serdes_link_down;
 					DEBUGOUT("ANYSTATE  -> DOWN\n");
 					break;
 				}
@@ -1815,7 +1818,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
 				txcw |= E1000_TXCW_ANE;
 				E1000_WRITE_REG(hw, E1000_TXCW, txcw);
 				mac->serdes_link_state =
-				    e1000_serdes_link_autoneg_progress;
+					e1000_serdes_link_autoneg_progress;
 				mac->serdes_has_link = FALSE;
 				DEBUGOUT("ANYSTATE  -> AN_PROG\n");
 			}
@@ -1905,7 +1908,7 @@ void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
 		 * Eventually the LAA will be in RAR[0] and RAR[14].
 		 */
 		e1000_rar_set_generic(hw, hw->mac.addr,
-		                      hw->mac.rar_entry_count - 1);
+				      hw->mac.rar_entry_count - 1);
 	return;
 }
 
diff --git a/sys/dev/e1000/e1000_82575.c b/sys/dev/e1000/e1000_82575.c
index 8407f7c..75fe0a4 100644
--- a/sys/dev/e1000/e1000_82575.c
+++ b/sys/dev/e1000/e1000_82575.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -51,32 +51,34 @@ static void e1000_release_nvm_82575(struct e1000_hw *hw);
 static s32  e1000_check_for_link_82575(struct e1000_hw *hw);
 static s32  e1000_get_cfg_done_82575(struct e1000_hw *hw);
 static s32  e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
-                                         u16 *duplex);
+					 u16 *duplex);
 static s32  e1000_init_hw_82575(struct e1000_hw *hw);
 static s32  e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
 static s32  e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
-                                           u16 *data);
+					   u16 *data);
 static s32  e1000_reset_hw_82575(struct e1000_hw *hw);
 static s32  e1000_reset_hw_82580(struct e1000_hw *hw);
 static s32  e1000_read_phy_reg_82580(struct e1000_hw *hw,
-                                    u32 offset, u16 *data);
+				     u32 offset, u16 *data);
 static s32  e1000_write_phy_reg_82580(struct e1000_hw *hw,
-                                     u32 offset, u16 data);
+				      u32 offset, u16 data);
 static s32  e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
-                                          bool active);
+					  bool active);
 static s32  e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
-                                          bool active);
+					  bool active);
 static s32  e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
-                                          bool active);
+					  bool active);
 static s32  e1000_setup_copper_link_82575(struct e1000_hw *hw);
 static s32  e1000_setup_serdes_link_82575(struct e1000_hw *hw);
+static s32  e1000_get_media_type_82575(struct e1000_hw *hw);
+static s32  e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
 static s32  e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
 static s32  e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
-                                            u32 offset, u16 data);
+					    u32 offset, u16 data);
 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
 static s32  e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
 static s32  e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
-                                                 u16 *speed, u16 *duplex);
+						 u16 *speed, u16 *duplex);
 static s32  e1000_get_phy_id_82575(struct e1000_hw *hw);
 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
@@ -91,15 +93,28 @@ static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
 static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
-						u16 offset);
+						 u16 offset);
 static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
-						u16 offset);
+						   u16 offset);
 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
-
-static const u16 e1000_82580_rxpbs_table[] =
-	{ 36, 72, 144, 1, 2, 4, 8, 16,
-	  35, 70, 140 };
+static void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
+static void e1000_clear_vfta_i350(struct e1000_hw *hw);
+
+static void e1000_i2c_start(struct e1000_hw *hw);
+static void e1000_i2c_stop(struct e1000_hw *hw);
+static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
+static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
+static s32 e1000_get_i2c_ack(struct e1000_hw *hw);
+static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
+static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
+static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
+static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
+static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
+static bool e1000_get_i2c_data(u32 *i2cctl);
+
+static const u16 e1000_82580_rxpbs_table[] = {
+	36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
 #define E1000_82580_RXPBS_TABLE_SIZE \
 	(sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
 
@@ -155,22 +170,22 @@ static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
 	phy->ops.power_up   = e1000_power_up_phy_copper;
 	phy->ops.power_down = e1000_power_down_phy_copper_82575;
 
-	phy->autoneg_mask           = AUTONEG_ADVERTISE_SPEED_DEFAULT;
-	phy->reset_delay_us         = 100;
+	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;
+	phy->reset_delay_us	= 100;
 
-	phy->ops.acquire            = e1000_acquire_phy_82575;
-	phy->ops.check_reset_block  = e1000_check_reset_block_generic;
-	phy->ops.commit             = e1000_phy_sw_reset_generic;
-	phy->ops.get_cfg_done       = e1000_get_cfg_done_82575;
-	phy->ops.release            = e1000_release_phy_82575;
+	phy->ops.acquire	= e1000_acquire_phy_82575;
+	phy->ops.check_reset_block = e1000_check_reset_block_generic;
+	phy->ops.commit		= e1000_phy_sw_reset_generic;
+	phy->ops.get_cfg_done	= e1000_get_cfg_done_82575;
+	phy->ops.release	= e1000_release_phy_82575;
 
 	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 
 	if (e1000_sgmii_active_82575(hw)) {
-		phy->ops.reset      = e1000_phy_hw_reset_sgmii_82575;
+		phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
 		ctrl_ext |= E1000_CTRL_I2C_ENA;
 	} else {
-		phy->ops.reset      = e1000_phy_hw_reset_generic;
+		phy->ops.reset = e1000_phy_hw_reset_generic;
 		ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 	}
 
@@ -178,14 +193,14 @@ static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
 	e1000_reset_mdicnfg_82580(hw);
 
 	if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
-		phy->ops.read_reg   = e1000_read_phy_reg_sgmii_82575;
-		phy->ops.write_reg  = e1000_write_phy_reg_sgmii_82575;
+		phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
+		phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
 	} else if (hw->mac.type >= e1000_82580) {
-		phy->ops.read_reg   = e1000_read_phy_reg_82580;
-		phy->ops.write_reg  = e1000_write_phy_reg_82580;
+		phy->ops.read_reg = e1000_read_phy_reg_82580;
+		phy->ops.write_reg = e1000_write_phy_reg_82580;
 	} else {
-		phy->ops.read_reg   = e1000_read_phy_reg_igp;
-		phy->ops.write_reg  = e1000_write_phy_reg_igp;
+		phy->ops.read_reg = e1000_read_phy_reg_igp;
+		phy->ops.write_reg = e1000_write_phy_reg_igp;
 	}
 
 	/* Set phy->phy_addr and phy->id. */
@@ -197,36 +212,38 @@ static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
 	case M88E1112_E_PHY_ID:
 	case M88E1340M_E_PHY_ID:
 	case M88E1111_I_PHY_ID:
-		phy->type                   = e1000_phy_m88;
-		phy->ops.check_polarity     = e1000_check_polarity_m88;
-		phy->ops.get_info           = e1000_get_phy_info_m88;
+		phy->type		= e1000_phy_m88;
+		phy->ops.check_polarity	= e1000_check_polarity_m88;
+		phy->ops.get_info	= e1000_get_phy_info_m88;
 		if (phy->id == I347AT4_E_PHY_ID ||
 		    phy->id == M88E1112_E_PHY_ID ||
 		    phy->id == M88E1340M_E_PHY_ID)
-			phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
+			phy->ops.get_cable_length =
+					 e1000_get_cable_length_m88_gen2;
 		else
 			phy->ops.get_cable_length = e1000_get_cable_length_m88;
 		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 		break;
 	case IGP03E1000_E_PHY_ID:
 	case IGP04E1000_E_PHY_ID:
-		phy->type                   = e1000_phy_igp_3;
-		phy->ops.check_polarity     = e1000_check_polarity_igp;
-		phy->ops.get_info           = e1000_get_phy_info_igp;
-		phy->ops.get_cable_length   = e1000_get_cable_length_igp_2;
+		phy->type = e1000_phy_igp_3;
+		phy->ops.check_polarity = e1000_check_polarity_igp;
+		phy->ops.get_info = e1000_get_phy_info_igp;
+		phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
-		phy->ops.set_d0_lplu_state  = e1000_set_d0_lplu_state_82575;
-		phy->ops.set_d3_lplu_state  = e1000_set_d3_lplu_state_generic;
+		phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
+		phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
 		break;
 	case I82580_I_PHY_ID:
 	case I350_I_PHY_ID:
-		phy->type                   = e1000_phy_82580;
-		phy->ops.check_polarity     = e1000_check_polarity_82577;
-		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82577;
-		phy->ops.get_cable_length   = e1000_get_cable_length_82577;
-		phy->ops.get_info           = e1000_get_phy_info_82577;
-		phy->ops.set_d0_lplu_state  = e1000_set_d0_lplu_state_82580;
-		phy->ops.set_d3_lplu_state  = e1000_set_d3_lplu_state_82580;
+		phy->type = e1000_phy_82580;
+		phy->ops.check_polarity = e1000_check_polarity_82577;
+		phy->ops.force_speed_duplex =
+					 e1000_phy_force_speed_duplex_82577;
+		phy->ops.get_cable_length = e1000_get_cable_length_82577;
+		phy->ops.get_info = e1000_get_phy_info_82577;
+		phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
+		phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 		break;
 	default:
 		ret_val = -E1000_ERR_PHY;
@@ -250,27 +267,33 @@ s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
 	DEBUGFUNC("e1000_init_nvm_params_82575");
 
 	size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
-	             E1000_EECD_SIZE_EX_SHIFT);
+		     E1000_EECD_SIZE_EX_SHIFT);
 	/*
 	 * Added to a constant, "size" becomes the left-shift value
 	 * for setting word_size.
 	 */
 	size += NVM_WORD_SIZE_BASE_SHIFT;
 
+	/* Just in case size is out of range, cap it to the largest
+	 * EEPROM size supported
+	 */
+	if (size > 15)
+		size = 15;
+
 	nvm->word_size = 1 << size;
-	nvm->opcode_bits        = 8;
-	nvm->delay_usec         = 1;
+	nvm->opcode_bits = 8;
+	nvm->delay_usec = 1;
 	switch (nvm->override) {
 	case e1000_nvm_override_spi_large:
-		nvm->page_size    = 32;
+		nvm->page_size = 32;
 		nvm->address_bits = 16;
 		break;
 	case e1000_nvm_override_spi_small:
-		nvm->page_size    = 8;
+		nvm->page_size = 8;
 		nvm->address_bits = 8;
 		break;
 	default:
-		nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
+		nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 		break;
 	}
@@ -281,17 +304,17 @@ s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
 		nvm->page_size = 128;
 
 	/* Function Pointers */
-	nvm->ops.acquire    = e1000_acquire_nvm_82575;
-	nvm->ops.release    = e1000_release_nvm_82575;
+	nvm->ops.acquire = e1000_acquire_nvm_82575;
+	nvm->ops.release = e1000_release_nvm_82575;
 	if (nvm->word_size < (1 << 15))
-		nvm->ops.read    = e1000_read_nvm_eerd;
+		nvm->ops.read = e1000_read_nvm_eerd;
 	else
-		nvm->ops.read    = e1000_read_nvm_spi;
+		nvm->ops.read = e1000_read_nvm_spi;
 
-	nvm->ops.write              = e1000_write_nvm_spi;
-	nvm->ops.validate           = e1000_validate_nvm_checksum_generic;
-	nvm->ops.update             = e1000_update_nvm_checksum_generic;
-	nvm->ops.valid_led_default  = e1000_valid_led_default_82575;
+	nvm->ops.write = e1000_write_nvm_spi;
+	nvm->ops.validate = e1000_validate_nvm_checksum_generic;
+	nvm->ops.update = e1000_update_nvm_checksum_generic;
+	nvm->ops.valid_led_default = e1000_valid_led_default_82575;
 
 	/* override genric family function pointers for specific descendants */
 	switch (hw->mac.type) {
@@ -318,34 +341,11 @@ static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
 {
 	struct e1000_mac_info *mac = &hw->mac;
 	struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
-	u32 ctrl_ext = 0;
 
 	DEBUGFUNC("e1000_init_mac_params_82575");
 
-	/* Set media type */
-        /*
-	 * The 82575 uses bits 22:23 for link mode. The mode can be changed
-         * based on the EEPROM. We cannot rely upon device ID. There
-         * is no distinguishable difference between fiber and internal
-         * SerDes mode on the 82575. There can be an external PHY attached
-         * on the SGMII interface. For this, we'll set sgmii_active to TRUE.
-         */
-	hw->phy.media_type = e1000_media_type_copper;
-	dev_spec->sgmii_active = FALSE;
-
-	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
-	switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
-	case E1000_CTRL_EXT_LINK_MODE_SGMII:
-		dev_spec->sgmii_active = TRUE;
-		break;
-	case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
-	case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
-		hw->phy.media_type = e1000_media_type_internal_serdes;
-		break;
-	default:
-		break;
-	}
-
+	/* Derives media type */
+	e1000_get_media_type_82575(hw);
 	/* Set mta register count */
 	mac->mta_reg_count = 128;
 	/* Set uta register count */
@@ -368,8 +368,8 @@ static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
 	mac->has_fwsm = TRUE;
 	/* ARC supported; valid only if manageability features are enabled. */
 	mac->arc_subsystem_valid =
-	        (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
-	                ? TRUE : FALSE;
+		(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
+			? TRUE : FALSE;
 
 	/* Function pointers */
 
@@ -386,9 +386,8 @@ static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
 	mac->ops.setup_link = e1000_setup_link_generic;
 	/* physical interface link setup */
 	mac->ops.setup_physical_interface =
-	        (hw->phy.media_type == e1000_media_type_copper)
-	                ? e1000_setup_copper_link_82575
-	                : e1000_setup_serdes_link_82575;
+		(hw->phy.media_type == e1000_media_type_copper)
+		? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
 	/* physical interface shutdown */
 	mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
 	/* physical interface power up */
@@ -403,10 +402,17 @@ static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
 	mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
 	/* multicast address update */
 	mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
-	/* writing VFTA */
-	mac->ops.write_vfta = e1000_write_vfta_generic;
-	/* clearing VFTA */
-	mac->ops.clear_vfta = e1000_clear_vfta_generic;
+	if (hw->mac.type == e1000_i350) {
+		/* writing VFTA */
+		mac->ops.write_vfta = e1000_write_vfta_i350;
+		/* clearing VFTA */
+		mac->ops.clear_vfta = e1000_clear_vfta_i350;
+	} else {
+		/* writing VFTA */
+		mac->ops.write_vfta = e1000_write_vfta_generic;
+		/* clearing VFTA */
+		mac->ops.clear_vfta = e1000_clear_vfta_generic;
+	}
 	/* ID LED init */
 	mac->ops.id_led_init = e1000_id_led_init_generic;
 	/* blink LED */
@@ -499,7 +505,7 @@ static void e1000_release_phy_82575(struct e1000_hw *hw)
  *  interface and stores the retrieved information in data.
  **/
 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
-                                          u16 *data)
+					  u16 *data)
 {
 	s32 ret_val = -E1000_ERR_PARAM;
 
@@ -532,7 +538,7 @@ out:
  *  media independent interface.
  **/
 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
-                                           u16 data)
+					   u16 data)
 {
 	s32 ret_val = -E1000_ERR_PARAM;
 
@@ -611,7 +617,7 @@ static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
 	/* Power on sgmii phy if it is disabled */
 	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 	E1000_WRITE_REG(hw, E1000_CTRL_EXT,
-	                ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
+			ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
 	E1000_WRITE_FLUSH(hw);
 	msec_delay(300);
 
@@ -623,8 +629,7 @@ static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
 		ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 		if (ret_val == E1000_SUCCESS) {
 			DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
-			          phy_id,
-			          phy->addr);
+				  phy_id, phy->addr);
 			/*
 			 * At the time of this writing, The M88 part is
 			 * the only supported SGMII PHY product.
@@ -633,7 +638,7 @@ static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
 				break;
 		} else {
 			DEBUGOUT1("PHY address %u was unreadable\n",
-			          phy->addr);
+				  phy->addr);
 		}
 	}
 
@@ -719,22 +724,22 @@ static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 	if (active) {
 		data |= IGP02E1000_PM_D0_LPLU;
 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
-		                             data);
+					     data);
 		if (ret_val)
 			goto out;
 
 		/* When LPLU is enabled, we should disable SmartSpeed */
 		ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-		                            &data);
+					    &data);
 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 		ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-		                             data);
+					     data);
 		if (ret_val)
 			goto out;
 	} else {
 		data &= ~IGP02E1000_PM_D0_LPLU;
 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
-		                             data);
+					     data);
 		/*
 		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 		 * during Dx states where the power conservation is most
@@ -743,28 +748,28 @@ static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 		 */
 		if (phy->smart_speed == e1000_smart_speed_on) {
 			ret_val = phy->ops.read_reg(hw,
-			                            IGP01E1000_PHY_PORT_CONFIG,
-			                            &data);
+						    IGP01E1000_PHY_PORT_CONFIG,
+						    &data);
 			if (ret_val)
 				goto out;
 
 			data |= IGP01E1000_PSCFR_SMART_SPEED;
 			ret_val = phy->ops.write_reg(hw,
-			                             IGP01E1000_PHY_PORT_CONFIG,
-			                             data);
+						     IGP01E1000_PHY_PORT_CONFIG,
+						     data);
 			if (ret_val)
 				goto out;
 		} else if (phy->smart_speed == e1000_smart_speed_off) {
 			ret_val = phy->ops.read_reg(hw,
-			                            IGP01E1000_PHY_PORT_CONFIG,
-			                            &data);
+						    IGP01E1000_PHY_PORT_CONFIG,
+						    &data);
 			if (ret_val)
 				goto out;
 
 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 			ret_val = phy->ops.write_reg(hw,
-			                             IGP01E1000_PHY_PORT_CONFIG,
-			                             data);
+						     IGP01E1000_PHY_PORT_CONFIG,
+						     data);
 			if (ret_val)
 				goto out;
 		}
@@ -811,11 +816,10 @@ static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
 		 * important.  During driver activity we should enable
 		 * SmartSpeed, so performance is maintained.
 		 */
-		if (phy->smart_speed == e1000_smart_speed_on) {
+		if (phy->smart_speed == e1000_smart_speed_on)
 			data |= E1000_82580_PM_SPD;
-		} else if (phy->smart_speed == e1000_smart_speed_off) {
+		else if (phy->smart_speed == e1000_smart_speed_off)
 			data &= ~E1000_82580_PM_SPD;
-		}
 	}
 
 	E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
@@ -854,14 +858,13 @@ s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
 		 * important.  During driver activity we should enable
 		 * SmartSpeed, so performance is maintained.
 		 */
-		if (phy->smart_speed == e1000_smart_speed_on) {
+		if (phy->smart_speed == e1000_smart_speed_on)
 			data |= E1000_82580_PM_SPD;
-		} else if (phy->smart_speed == e1000_smart_speed_off) {
+		else if (phy->smart_speed == e1000_smart_speed_off)
 			data &= ~E1000_82580_PM_SPD;
-		}
 	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
-	           (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
-	           (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
+		   (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
+		   (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 		data |= E1000_82580_PM_D3_LPLU;
 		/* When LPLU is enabled, we should disable SmartSpeed */
 		data &= ~E1000_82580_PM_SPD;
@@ -889,7 +892,37 @@ static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
 	ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 	if (ret_val)
 		goto out;
-	ret_val = e1000_acquire_nvm_generic(hw);
+
+	/*
+	 * Check if there is some access
+	 * error this access may hook on
+	 */
+	if (hw->mac.type == e1000_i350) {
+		u32 eecd = E1000_READ_REG(hw, E1000_EECD);
+		if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
+		    E1000_EECD_TIMEOUT)) {
+			/* Clear all access error flags */
+			E1000_WRITE_REG(hw, E1000_EECD, eecd |
+					E1000_EECD_ERROR_CLR);
+			DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
+		}
+	}
+	if (hw->mac.type == e1000_82580) {
+		u32 eecd = E1000_READ_REG(hw, E1000_EECD);
+		if (eecd & E1000_EECD_BLOCKED) {
+			/* Clear access error flag */
+			E1000_WRITE_REG(hw, E1000_EECD, eecd |
+					E1000_EECD_BLOCKED);
+			DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
+		}
+	}
+
+
+	switch (hw->mac.type) {
+	default:
+		ret_val = e1000_acquire_nvm_generic(hw);
+	}
+
 	if (ret_val)
 		e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 
@@ -908,6 +941,10 @@ static void e1000_release_nvm_82575(struct e1000_hw *hw)
 {
 	DEBUGFUNC("e1000_release_nvm_82575");
 
+	switch (hw->mac.type) {
+	default:
+		e1000_release_nvm_generic(hw);
+	}
 	e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 }
 
@@ -977,8 +1014,8 @@ static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
 
 	DEBUGFUNC("e1000_release_swfw_sync_82575");
 
-	while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS);
-	/* Empty */
+	while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
+		; /* Empty */
 
 	swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
 	swfw_sync &= ~mask;
@@ -1039,7 +1076,7 @@ static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
  *  Otherwise, use the generic function to get the link speed and duplex info.
  **/
 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
-                                        u16 *duplex)
+					u16 *duplex)
 {
 	s32 ret_val;
 
@@ -1047,10 +1084,10 @@ static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
 
 	if (hw->phy.media_type != e1000_media_type_copper)
 		ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
-		                                               duplex);
+							       duplex);
 	else
 		ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
-		                                                    duplex);
+								    duplex);
 
 	return ret_val;
 }
@@ -1071,7 +1108,7 @@ static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
 
 	if (hw->phy.media_type != e1000_media_type_copper) {
 		ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
-		                                               &duplex);
+							       &duplex);
 		/*
 		 * Use this flag to determine if link needs to be checked or
 		 * not.  If we have link clear the flag so that we do not
@@ -1124,7 +1161,7 @@ static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
  *  duplex, then store the values in the pointers provided.
  **/
 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
-                                                u16 *speed, u16 *duplex)
+						u16 *speed, u16 *duplex)
 {
 	struct e1000_mac_info *mac = &hw->mac;
 	u32 pcs;
@@ -1152,20 +1189,18 @@ static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
 		mac->serdes_has_link = TRUE;
 
 		/* Detect and store PCS speed */
-		if (pcs & E1000_PCS_LSTS_SPEED_1000) {
+		if (pcs & E1000_PCS_LSTS_SPEED_1000)
 			*speed = SPEED_1000;
-		} else if (pcs & E1000_PCS_LSTS_SPEED_100) {
+		else if (pcs & E1000_PCS_LSTS_SPEED_100)
 			*speed = SPEED_100;
-		} else {
+		else
 			*speed = SPEED_10;
-		}
 
 		/* Detect and store PCS duplex */
-		if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
+		if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
 			*duplex = FULL_DUPLEX;
-		} else {
+		else
 			*duplex = HALF_DUPLEX;
-		}
 	}
 
 	return E1000_SUCCESS;
@@ -1225,15 +1260,13 @@ static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
 	 * on the last TLP read/write transaction when MAC is reset.
 	 */
 	ret_val = e1000_disable_pcie_master_generic(hw);
-	if (ret_val) {
+	if (ret_val)
 		DEBUGOUT("PCI-E Master disable polling has failed.\n");
-	}
 
 	/* set the completion timeout for interface */
 	ret_val = e1000_set_pcie_completion_timeout(hw);
-	if (ret_val) {
+	if (ret_val)
 		DEBUGOUT("PCI-E Set completion timeout has failed.\n");
-	}
 
 	DEBUGOUT("Masking off all interrupts\n");
 	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
@@ -1314,6 +1347,9 @@ static s32 e1000_init_hw_82575(struct e1000_hw *hw)
 	/* Setup link and flow control */
 	ret_val = mac->ops.setup_link(hw);
 
+	/* Set the default MTU size */
+	hw->dev_spec._82575.mtu = 1500;
+
 	/*
 	 * Clear all of the statistics registers (clear on read).  It is
 	 * important that we do this after we have tried to establish link
@@ -1349,7 +1385,7 @@ static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
 	if (ret_val)
 		goto out;
 
-	if (e1000_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
+	if (e1000_sgmii_active_82575(hw)) {
 		/* allow time for SFP cage time to power up phy */
 		msec_delay(300);
 
@@ -1400,12 +1436,14 @@ static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
 {
 	u32 ctrl_ext, ctrl_reg, reg;
 	bool pcs_autoneg;
+	s32 ret_val = E1000_SUCCESS;
+	u16 data;
 
 	DEBUGFUNC("e1000_setup_serdes_link_82575");
 
 	if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
 	    !e1000_sgmii_active_82575(hw))
-		return E1000_SUCCESS;
+		return ret_val;
 
 	/*
 	 * On the 82575, SerDes loopback mode persists until it is
@@ -1444,13 +1482,25 @@ static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
 		pcs_autoneg = FALSE;
 		/* fall through to default case */
 	default:
+		if (hw->mac.type == e1000_82575 ||
+		    hw->mac.type == e1000_82576) {
+			ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
+			if (ret_val) {
+				DEBUGOUT("NVM Read Error\n");
+				return ret_val;
+			}
+
+			if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
+				pcs_autoneg = FALSE;
+		}
+
 		/*
 		 * non-SGMII modes only supports a speed of 1000/Full for the
 		 * link so it is best to just force the MAC and let the pcs
 		 * link either autoneg or be forced to 1000/Full
 		 */
 		ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
-		            E1000_CTRL_FD | E1000_CTRL_FRCDPX;
+			    E1000_CTRL_FD | E1000_CTRL_FRCDPX;
 
 		/* set speed of 1000/Full if speed/duplex is forced */
 		reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
@@ -1466,7 +1516,7 @@ static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
 	 * However, both are supported by the hardware and some drivers/tools.
 	 */
 	reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
-	         E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
+		 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
 
 	/*
 	 * We force flow control to prevent the CTRL register values from being
@@ -1481,7 +1531,7 @@ static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
 		DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
 	} else {
 		/* Set PCS register for forced link */
-		reg |= E1000_PCS_LCTL_FSD;        /* Force Speed */
+		reg |= E1000_PCS_LCTL_FSD;	/* Force Speed */
 		DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
 	}
 
@@ -1490,7 +1540,216 @@ static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
 	if (!e1000_sgmii_active_82575(hw))
 		e1000_force_mac_fc_generic(hw);
 
-	return E1000_SUCCESS;
+	return ret_val;
+}
+
+/**
+ *  e1000_get_media_type_82575 - derives current media type.
+ *  @hw: pointer to the HW structure
+ *
+ *  The media type is chosen reflecting few settings.
+ *  The following are taken into account:
+ *  - link mode set in the current port Init Control Word #3
+ *  - current link mode settings in CSR register
+ *  - MDIO vs. I2C PHY control interface chosen
+ *  - SFP module media type
+ **/
+static s32 e1000_get_media_type_82575(struct e1000_hw *hw)
+{
+	u32 lan_id = 0;
+	s32 ret_val = E1000_ERR_CONFIG;
+	struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
+	u32 ctrl_ext = 0;
+	u32 current_link_mode = 0;
+	u16 init_ctrl_wd_3 = 0;
+	u8 init_ctrl_wd_3_offset = 0;
+	u8 init_ctrl_wd_3_bit_offset = 0;
+
+	/* Set internal phy as default */
+	dev_spec->sgmii_active = FALSE;
+	dev_spec->module_plugged = FALSE;
+
+	/*
+	 * Check if NVM access method is attached already.
+	 * If it is then Init Control Word #3 is considered
+	 * otherwise runtime CSR register content is taken.
+	 */
+
+	/* Get CSR setting */
+	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
+
+	/* Get link mode setting */
+	if ((hw->nvm.ops.read) && (hw->nvm.ops.read != e1000_null_read_nvm)) {
+		/* Take link mode from EEPROM */
+
+		/*
+		 * Get LAN port ID to derive its
+		 * adequate Init Control Word #3
+		 */
+		lan_id = ((E1000_READ_REG(hw, E1000_STATUS) &
+		      E1000_STATUS_LAN_ID_MASK) >> E1000_STATUS_LAN_ID_OFFSET);
+		/*
+		 * Derive Init Control Word #3 offset
+		 * and mask to pick up link mode setting.
+		 */
+		if (hw->mac.type < e1000_82580) {
+			init_ctrl_wd_3_offset = lan_id ?
+			   NVM_INIT_CONTROL3_PORT_A : NVM_INIT_CONTROL3_PORT_B;
+			init_ctrl_wd_3_bit_offset = NVM_WORD24_LNK_MODE_OFFSET;
+		} else {
+			init_ctrl_wd_3_offset =
+					    NVM_82580_LAN_FUNC_OFFSET(lan_id) +
+					    NVM_INIT_CONTROL3_PORT_A;
+			init_ctrl_wd_3_bit_offset =
+					      NVM_WORD24_82580_LNK_MODE_OFFSET;
+		}
+		/* Read Init Control Word #3*/
+		hw->nvm.ops.read(hw, init_ctrl_wd_3_offset, 1, &init_ctrl_wd_3);
+		current_link_mode = init_ctrl_wd_3;
+		/*
+		 * Switch to CSR for all but internal PHY.
+		 */
+		if ((init_ctrl_wd_3 << (E1000_CTRL_EXT_LINK_MODE_OFFSET -
+		    init_ctrl_wd_3_bit_offset)) !=
+		    E1000_CTRL_EXT_LINK_MODE_GMII) {
+			current_link_mode = ctrl_ext;
+			init_ctrl_wd_3_bit_offset =
+					      E1000_CTRL_EXT_LINK_MODE_OFFSET;
+		}
+	} else {
+		/* Take link mode from CSR */
+		current_link_mode = ctrl_ext;
+		init_ctrl_wd_3_bit_offset = E1000_CTRL_EXT_LINK_MODE_OFFSET;
+	}
+
+	/*
+	 * Align link mode bits to
+	 * their CTRL_EXT location.
+	 */
+	current_link_mode <<= (E1000_CTRL_EXT_LINK_MODE_OFFSET -
+			       init_ctrl_wd_3_bit_offset);
+	current_link_mode &= E1000_CTRL_EXT_LINK_MODE_MASK;
+
+	switch (current_link_mode) {
+
+	case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
+		hw->phy.media_type = e1000_media_type_internal_serdes;
+		current_link_mode = E1000_CTRL_EXT_LINK_MODE_1000BASE_KX;
+		break;
+	case E1000_CTRL_EXT_LINK_MODE_GMII:
+		hw->phy.media_type = e1000_media_type_copper;
+		current_link_mode = E1000_CTRL_EXT_LINK_MODE_GMII;
+		break;
+	case E1000_CTRL_EXT_LINK_MODE_SGMII:
+	case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
+		/* Get phy control interface type set (MDIO vs. I2C)*/
+		if (e1000_sgmii_uses_mdio_82575(hw)) {
+			hw->phy.media_type = e1000_media_type_copper;
+			dev_spec->sgmii_active = TRUE;
+			current_link_mode = E1000_CTRL_EXT_LINK_MODE_SGMII;
+		} else {
+			ret_val = e1000_set_sfp_media_type_82575(hw);
+			if (ret_val != E1000_SUCCESS)
+				goto out;
+			if (hw->phy.media_type ==
+				e1000_media_type_internal_serdes) {
+				current_link_mode =
+					 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
+			} else if (hw->phy.media_type ==
+				e1000_media_type_copper) {
+				current_link_mode =
+					       E1000_CTRL_EXT_LINK_MODE_SGMII;
+			}
+		}
+		break;
+	default:
+		DEBUGOUT("Link mode mask doesn't fit bit field size\n");
+		goto out;
+	}
+	/*
+	 * Do not change current link mode setting
+	 * if media type is fibre or has not been
+	 * recognized.
+	 */
+	if ((hw->phy.media_type != e1000_media_type_unknown) &&
+	    (hw->phy.media_type != e1000_media_type_fiber)) {
+		/* Update link mode */
+		ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
+		E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext |
+				current_link_mode);
+	}
+
+	ret_val = E1000_SUCCESS;
+out:
+	/*
+	 * If media type was not identified then return media type
+	 * defined by the CTRL_EXT settings.
+	 */
+	if (hw->phy.media_type == e1000_media_type_unknown) {
+		if (current_link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII)
+			hw->phy.media_type = e1000_media_type_copper;
+		else
+			hw->phy.media_type = e1000_media_type_internal_serdes;
+	}
+
+	return ret_val;
+}
+
+/**
+ *  e1000_set_sfp_media_type_82575 - derives SFP module media type.
+ *  @hw: pointer to the HW structure
+ *
+ *  The media type is chosen based on SFP module.
+ *  compatibility flags retrieved from SFP ID EEPROM.
+ **/
+static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
+{
+	s32 ret_val = E1000_ERR_CONFIG;
+	u32 ctrl_ext = 0;
+	struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
+	struct sfp_e1000_flags eth_flags = {0};
+	u8 tranceiver_type = 0;
+
+	/* Turn I2C interface ON */
+	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
+	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
+
+	/* Read SFP module data */
+	ret_val = e1000_read_sfp_data_byte(hw,
+			E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
+			&tranceiver_type);
+	if (ret_val != E1000_SUCCESS)
+		goto out;
+	ret_val = e1000_read_sfp_data_byte(hw,
+			E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
+			(u8 *)&eth_flags);
+	if (ret_val != E1000_SUCCESS)
+		goto out;
+	/*
+	 * Check if there is some SFP
+	 * module plugged and powered
+	 */
+	if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
+	    (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
+		dev_spec->module_plugged = TRUE;
+		if (eth_flags.e1000_base_lx || eth_flags.e1000_base_sx) {
+			hw->phy.media_type = e1000_media_type_internal_serdes;
+		} else if (eth_flags.e1000_base_t) {
+			dev_spec->sgmii_active = TRUE;
+			hw->phy.media_type = e1000_media_type_copper;
+		} else {
+				hw->phy.media_type = e1000_media_type_unknown;
+				DEBUGOUT("PHY module has not been recognized\n");
+				goto out;
+		}
+	} else {
+		hw->phy.media_type = e1000_media_type_unknown;
+	}
+	ret_val = E1000_SUCCESS;
+out:
+	/* Restore I2C interface setting */
+	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
+	return ret_val;
 }
 
 /**
@@ -1514,7 +1773,7 @@ static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
 	}
 
 	if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
-		switch(hw->phy.media_type) {
+		switch (hw->phy.media_type) {
 		case e1000_media_type_internal_serdes:
 			*data = ID_LED_DEFAULT_82575_SERDES;
 			break;
@@ -1549,7 +1808,7 @@ static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
  *  Inits recommended HW defaults after a reset when there is no EEPROM
  *  detected. This is only for the 82575.
  **/
-static s32 e1000_reset_init_script_82575(struct e1000_hw* hw)
+static s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
 {
 	DEBUGFUNC("e1000_reset_init_script_82575");
 
@@ -1736,7 +1995,7 @@ void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
 	for (i = 0; i < 4; i++) {
 		rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
 		E1000_WRITE_REG(hw, E1000_RXDCTL(i),
-		                rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
+				rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
 	}
 	/* Poll all queues to verify they have shut down */
 	for (ms_wait = 0; ms_wait < 10; ms_wait++) {
@@ -1822,14 +2081,14 @@ static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
 	 * 16ms to 55ms
 	 */
 	ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
-	                                  &pcie_devctl2);
+					  &pcie_devctl2);
 	if (ret_val)
 		goto out;
 
 	pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
 
 	ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
-	                                   &pcie_devctl2);
+					   &pcie_devctl2);
 out:
 	/* disable completion timeout resend */
 	gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
@@ -1852,20 +2111,35 @@ void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
 
 	switch (hw->mac.type) {
 	case e1000_82576:
-	case e1000_i350:
 		dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
 		if (enable) {
 			dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
 				   E1000_DTXSWC_VLAN_SPOOF_MASK);
 			/* The PF can spoof - it has to in order to
 			 * support emulation mode NICs */
-			dtxswc ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
+			dtxswc ^= (1 << pf | 1 << (pf +
+				   E1000_DTXSWC_VLAN_SPOOF_SHIFT));
 		} else {
 			dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
 				    E1000_DTXSWC_VLAN_SPOOF_MASK);
 		}
 		E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
 		break;
+	case e1000_i350:
+		dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
+		if (enable) {
+			dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
+				   E1000_DTXSWC_VLAN_SPOOF_MASK);
+			/* The PF can spoof - it has to in order to
+			 * support emulation mode NICs
+			 */
+			dtxswc ^= (1 << pf | 1 << (pf +
+				   E1000_DTXSWC_VLAN_SPOOF_SHIFT));
+		} else {
+			dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
+				    E1000_DTXSWC_VLAN_SPOOF_MASK);
+		}
+		E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
 	default:
 		break;
 	}
@@ -1983,7 +2257,7 @@ out:
  *  e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
  *  @hw: pointer to the HW structure
  *
- *  This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
+ *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
  *  the values found in the EEPROM.  This addresses an issue in which these
  *  bits are not restored from EEPROM after reset.
  **/
@@ -2001,8 +2275,8 @@ static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
 		goto out;
 
 	ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
-	                           NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
-	                           &nvm_data);
+				   NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
+				   &nvm_data);
 	if (ret_val) {
 		DEBUGOUT("NVM Read Error\n");
 		goto out;
@@ -2057,17 +2331,18 @@ static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
 	msec_delay(10);
 
 	/* Determine whether or not a global dev reset is requested */
-	if (global_device_reset &&
-		e1000_acquire_swfw_sync_82575(hw, swmbsw_mask))
+	if (global_device_reset && e1000_acquire_swfw_sync_82575(hw,
+	    swmbsw_mask))
 			global_device_reset = FALSE;
 
-	if (global_device_reset &&
-		!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STAT_DEV_RST_SET))
+	if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
+	    E1000_STAT_DEV_RST_SET))
 		ctrl |= E1000_CTRL_DEV_RST;
 	else
 		ctrl |= E1000_CTRL_RST;
 
 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
+	E1000_WRITE_FLUSH(hw);
 
 	/* Add delay to insure DEV_RST has time to complete */
 	if (global_device_reset)
@@ -2192,7 +2467,7 @@ s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
 	}
 	checksum = (u16) NVM_SUM - checksum;
 	ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
-				&checksum);
+				    &checksum);
 	if (ret_val)
 		DEBUGOUT("NVM Write Error while updating checksum.\n");
 
@@ -2232,7 +2507,7 @@ static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
 	for (j = 0; j < eeprom_regions_count; j++) {
 		nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
 		ret_val = e1000_validate_nvm_checksum_with_offset(hw,
-								nvm_offset);
+								  nvm_offset);
 		if (ret_val != E1000_SUCCESS)
 			goto out;
 	}
@@ -2259,8 +2534,7 @@ static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
 
 	ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
 	if (ret_val) {
-		DEBUGOUT("NVM Read Error while updating checksum"
-			" compatibility bit.\n");
+		DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
 		goto out;
 	}
 
@@ -2268,10 +2542,9 @@ static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
 		/* set compatibility bit to validate checksums appropriately */
 		nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
 		ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
-					&nvm_data);
+					    &nvm_data);
 		if (ret_val) {
-			DEBUGOUT("NVM Write Error while updating checksum"
-				" compatibility bit.\n");
+			DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
 			goto out;
 		}
 	}
@@ -2279,9 +2552,8 @@ static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
 	for (j = 0; j < 4; j++) {
 		nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
 		ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
-		if (ret_val) {
+		if (ret_val)
 			goto out;
-		}
 	}
 
 out:
@@ -2307,7 +2579,7 @@ static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
 	for (j = 0; j < 4; j++) {
 		nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
 		ret_val = e1000_validate_nvm_checksum_with_offset(hw,
-								nvm_offset);
+								  nvm_offset);
 		if (ret_val != E1000_SUCCESS)
 			goto out;
 	}
@@ -2353,37 +2625,628 @@ out:
 s32 e1000_set_eee_i350(struct e1000_hw *hw)
 {
 	s32 ret_val = E1000_SUCCESS;
-	u32 ipcnfg, eeer, ctrl_ext;
+	u32 ipcnfg, eeer;
 
 	DEBUGFUNC("e1000_set_eee_i350");
 
-	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
-	if ((hw->mac.type != e1000_i350) ||
-	    (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK))
+	if ((hw->mac.type < e1000_i350) ||
+	    (hw->phy.media_type != e1000_media_type_copper))
 		goto out;
 	ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
 	eeer = E1000_READ_REG(hw, E1000_EEER);
 
 	/* enable or disable per user setting */
 	if (!(hw->dev_spec._82575.eee_disable)) {
-		ipcnfg |= (E1000_IPCNFG_EEE_1G_AN |
-		           E1000_IPCNFG_EEE_100M_AN);
-		eeer |= (E1000_EEER_TX_LPI_EN |
-		         E1000_EEER_RX_LPI_EN |
-		         E1000_EEER_LPI_FC);
+		ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
+		eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
+			 E1000_EEER_LPI_FC);
 
 	} else {
-		ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
-		            E1000_IPCNFG_EEE_100M_AN);
-		eeer &= ~(E1000_EEER_TX_LPI_EN |
-		          E1000_EEER_RX_LPI_EN |
-		          E1000_EEER_LPI_FC);
+		ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
+		eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
+			  E1000_EEER_LPI_FC);
 	}
 	E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
 	E1000_WRITE_REG(hw, E1000_EEER, eeer);
-			E1000_READ_REG(hw, E1000_IPCNFG);
-			E1000_READ_REG(hw, E1000_EEER);
+	E1000_READ_REG(hw, E1000_IPCNFG);
+	E1000_READ_REG(hw, E1000_EEER);
 out:
 
 	return ret_val;
 }
+
+/* Due to a hw errata, if the host tries to  configure the VFTA register
+ * while performing queries from the BMC or DMA, then the VFTA in some
+ * cases won't be written.
+ */
+
+/**
+ *  e1000_clear_vfta_i350 - Clear VLAN filter table
+ *  @hw: pointer to the HW structure
+ *
+ *  Clears the register array which contains the VLAN filter table by
+ *  setting all the values to 0.
+ **/
+void e1000_clear_vfta_i350(struct e1000_hw *hw)
+{
+	u32 offset;
+	int i;
+
+	DEBUGFUNC("e1000_clear_vfta_350");
+
+	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
+		for (i = 0; i < 10; i++)
+			E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
+
+		E1000_WRITE_FLUSH(hw);
+	}
+}
+
+/**
+ *  e1000_write_vfta_i350 - Write value to VLAN filter table
+ *  @hw: pointer to the HW structure
+ *  @offset: register offset in VLAN filter table
+ *  @value: register value written to VLAN filter table
+ *
+ *  Writes value at the given offset in the register array which stores
+ *  the VLAN filter table.
+ **/
+void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
+{
+	int i;
+
+	DEBUGFUNC("e1000_write_vfta_350");
+
+	for (i = 0; i < 10; i++)
+		E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
+
+	E1000_WRITE_FLUSH(hw);
+}
+
+
+/**
+ *  e1000_set_i2c_bb - Enable I2C bit-bang
+ *  @hw: pointer to the HW structure
+ *
+ *  Enable I2C bit-bang interface
+ *
+ **/
+s32 e1000_set_i2c_bb(struct e1000_hw *hw)
+{
+	s32 ret_val = E1000_SUCCESS;
+	u32 ctrl_ext, i2cparams;
+
+	DEBUGFUNC("e1000_set_i2c_bb");
+
+	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
+	ctrl_ext |= E1000_CTRL_I2C_ENA;
+	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
+	E1000_WRITE_FLUSH(hw);
+
+	i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
+	i2cparams |= E1000_I2CBB_EN;
+	i2cparams |= E1000_I2C_DATA_OE_N;
+	i2cparams |= E1000_I2C_CLK_OE_N;
+	E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
+	E1000_WRITE_FLUSH(hw);
+
+	return ret_val;
+}
+
+/**
+ *  e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
+ *  @hw: pointer to hardware structure
+ *  @byte_offset: byte offset to read
+ *  @data: value read
+ *
+ *  Performs byte read operation over I2C interface at
+ *  a specified device address.
+ **/
+s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
+				u8 dev_addr, u8 *data)
+{
+	s32 status = E1000_SUCCESS;
+	u32 max_retry = 10;
+	u32 retry = 1;
+	u16 swfw_mask = 0;
+
+	bool nack = 1;
+
+	DEBUGFUNC("e1000_read_i2c_byte_generic");
+
+	swfw_mask = E1000_SWFW_PHY0_SM;
+
+	do {
+		if (e1000_acquire_swfw_sync_82575(hw, swfw_mask)
+		    != E1000_SUCCESS) {
+			status = E1000_ERR_SWFW_SYNC;
+			goto read_byte_out;
+		}
+
+		e1000_i2c_start(hw);
+
+		/* Device Address and write indication */
+		status = e1000_clock_out_i2c_byte(hw, dev_addr);
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		status = e1000_get_i2c_ack(hw);
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		status = e1000_clock_out_i2c_byte(hw, byte_offset);
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		status = e1000_get_i2c_ack(hw);
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		e1000_i2c_start(hw);
+
+		/* Device Address and read indication */
+		status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		status = e1000_get_i2c_ack(hw);
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		status = e1000_clock_in_i2c_byte(hw, data);
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		status = e1000_clock_out_i2c_bit(hw, nack);
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		e1000_i2c_stop(hw);
+		break;
+
+fail:
+		e1000_release_swfw_sync_82575(hw, swfw_mask);
+		msec_delay(100);
+		e1000_i2c_bus_clear(hw);
+		retry++;
+		if (retry < max_retry)
+			DEBUGOUT("I2C byte read error - Retrying.\n");
+		else
+			DEBUGOUT("I2C byte read error.\n");
+
+	} while (retry < max_retry);
+
+	e1000_release_swfw_sync_82575(hw, swfw_mask);
+
+read_byte_out:
+
+	return status;
+}
+
+/**
+ *  e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
+ *  @hw: pointer to hardware structure
+ *  @byte_offset: byte offset to write
+ *  @data: value to write
+ *
+ *  Performs byte write operation over I2C interface at
+ *  a specified device address.
+ **/
+s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
+				 u8 dev_addr, u8 data)
+{
+	s32 status = E1000_SUCCESS;
+	u32 max_retry = 1;
+	u32 retry = 0;
+	u16 swfw_mask = 0;
+
+	DEBUGFUNC("e1000_write_i2c_byte_generic");
+
+	swfw_mask = E1000_SWFW_PHY0_SM;
+
+	if (e1000_acquire_swfw_sync_82575(hw, swfw_mask) != E1000_SUCCESS) {
+		status = E1000_ERR_SWFW_SYNC;
+		goto write_byte_out;
+	}
+
+	do {
+		e1000_i2c_start(hw);
+
+		status = e1000_clock_out_i2c_byte(hw, dev_addr);
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		status = e1000_get_i2c_ack(hw);
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		status = e1000_clock_out_i2c_byte(hw, byte_offset);
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		status = e1000_get_i2c_ack(hw);
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		status = e1000_clock_out_i2c_byte(hw, data);
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		status = e1000_get_i2c_ack(hw);
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		e1000_i2c_stop(hw);
+		break;
+
+fail:
+		e1000_i2c_bus_clear(hw);
+		retry++;
+		if (retry < max_retry)
+			DEBUGOUT("I2C byte write error - Retrying.\n");
+		else
+			DEBUGOUT("I2C byte write error.\n");
+	} while (retry < max_retry);
+
+	e1000_release_swfw_sync_82575(hw, swfw_mask);
+
+write_byte_out:
+
+	return status;
+}
+
+/**
+ *  e1000_i2c_start - Sets I2C start condition
+ *  @hw: pointer to hardware structure
+ *
+ *  Sets I2C start condition (High -> Low on SDA while SCL is High)
+ **/
+static void e1000_i2c_start(struct e1000_hw *hw)
+{
+	u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
+
+	DEBUGFUNC("e1000_i2c_start");
+
+	/* Start condition must begin with data and clock high */
+	e1000_set_i2c_data(hw, &i2cctl, 1);
+	e1000_raise_i2c_clk(hw, &i2cctl);
+
+	/* Setup time for start condition (4.7us) */
+	usec_delay(E1000_I2C_T_SU_STA);
+
+	e1000_set_i2c_data(hw, &i2cctl, 0);
+
+	/* Hold time for start condition (4us) */
+	usec_delay(E1000_I2C_T_HD_STA);
+
+	e1000_lower_i2c_clk(hw, &i2cctl);
+
+	/* Minimum low period of clock is 4.7 us */
+	usec_delay(E1000_I2C_T_LOW);
+
+}
+
+/**
+ *  e1000_i2c_stop - Sets I2C stop condition
+ *  @hw: pointer to hardware structure
+ *
+ *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
+ **/
+static void e1000_i2c_stop(struct e1000_hw *hw)
+{
+	u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
+
+	DEBUGFUNC("e1000_i2c_stop");
+
+	/* Stop condition must begin with data low and clock high */
+	e1000_set_i2c_data(hw, &i2cctl, 0);
+	e1000_raise_i2c_clk(hw, &i2cctl);
+
+	/* Setup time for stop condition (4us) */
+	usec_delay(E1000_I2C_T_SU_STO);
+
+	e1000_set_i2c_data(hw, &i2cctl, 1);
+
+	/* bus free time between stop and start (4.7us)*/
+	usec_delay(E1000_I2C_T_BUF);
+}
+
+/**
+ *  e1000_clock_in_i2c_byte - Clocks in one byte via I2C
+ *  @hw: pointer to hardware structure
+ *  @data: data byte to clock in
+ *
+ *  Clocks in one byte data via I2C data/clock
+ **/
+static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
+{
+	s32 i;
+	bool bit = 0;
+
+	DEBUGFUNC("e1000_clock_in_i2c_byte");
+
+	*data = 0;
+	for (i = 7; i >= 0; i--) {
+		e1000_clock_in_i2c_bit(hw, &bit);
+		*data |= bit << i;
+	}
+
+	return E1000_SUCCESS;
+}
+
+/**
+ *  e1000_clock_out_i2c_byte - Clocks out one byte via I2C
+ *  @hw: pointer to hardware structure
+ *  @data: data byte clocked out
+ *
+ *  Clocks out one byte data via I2C data/clock
+ **/
+static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
+{
+	s32 status = E1000_SUCCESS;
+	s32 i;
+	u32 i2cctl;
+	bool bit = 0;
+
+	DEBUGFUNC("e1000_clock_out_i2c_byte");
+
+	for (i = 7; i >= 0; i--) {
+		bit = (data >> i) & 0x1;
+		status = e1000_clock_out_i2c_bit(hw, bit);
+
+		if (status != E1000_SUCCESS)
+			break;
+	}
+
+	/* Release SDA line (set high) */
+	i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
+
+	i2cctl |= E1000_I2C_DATA_OE_N;
+	E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
+	E1000_WRITE_FLUSH(hw);
+
+	return status;
+}
+
+/**
+ *  e1000_get_i2c_ack - Polls for I2C ACK
+ *  @hw: pointer to hardware structure
+ *
+ *  Clocks in/out one bit via I2C data/clock
+ **/
+static s32 e1000_get_i2c_ack(struct e1000_hw *hw)
+{
+	s32 status = E1000_SUCCESS;
+	u32 i = 0;
+	u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
+	u32 timeout = 10;
+	bool ack = 1;
+
+	DEBUGFUNC("e1000_get_i2c_ack");
+
+	e1000_raise_i2c_clk(hw, &i2cctl);
+
+	/* Minimum high period of clock is 4us */
+	usec_delay(E1000_I2C_T_HIGH);
+
+	/* Wait until SCL returns high */
+	for (i = 0; i < timeout; i++) {
+		usec_delay(1);
+		i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
+		if (i2cctl & E1000_I2C_CLK_IN)
+			break;
+	}
+	if (!(i2cctl & E1000_I2C_CLK_IN))
+		return E1000_ERR_I2C;
+
+	ack = e1000_get_i2c_data(&i2cctl);
+	if (ack == 1) {
+		DEBUGOUT("I2C ack was not received.\n");
+		status = E1000_ERR_I2C;
+	}
+
+	e1000_lower_i2c_clk(hw, &i2cctl);
+
+	/* Minimum low period of clock is 4.7 us */
+	usec_delay(E1000_I2C_T_LOW);
+
+	return status;
+}
+
+/**
+ *  e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
+ *  @hw: pointer to hardware structure
+ *  @data: read data value
+ *
+ *  Clocks in one bit via I2C data/clock
+ **/
+static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
+{
+	u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
+
+	DEBUGFUNC("e1000_clock_in_i2c_bit");
+
+	e1000_raise_i2c_clk(hw, &i2cctl);
+
+	/* Minimum high period of clock is 4us */
+	usec_delay(E1000_I2C_T_HIGH);
+
+	i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
+	*data = e1000_get_i2c_data(&i2cctl);
+
+	e1000_lower_i2c_clk(hw, &i2cctl);
+
+	/* Minimum low period of clock is 4.7 us */
+	usec_delay(E1000_I2C_T_LOW);
+
+	return E1000_SUCCESS;
+}
+
+/**
+ *  e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
+ *  @hw: pointer to hardware structure
+ *  @data: data value to write
+ *
+ *  Clocks out one bit via I2C data/clock
+ **/
+static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
+{
+	s32 status;
+	u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
+
+	DEBUGFUNC("e1000_clock_out_i2c_bit");
+
+	status = e1000_set_i2c_data(hw, &i2cctl, data);
+	if (status == E1000_SUCCESS) {
+		e1000_raise_i2c_clk(hw, &i2cctl);
+
+		/* Minimum high period of clock is 4us */
+		usec_delay(E1000_I2C_T_HIGH);
+
+		e1000_lower_i2c_clk(hw, &i2cctl);
+
+		/* Minimum low period of clock is 4.7 us.
+		 * This also takes care of the data hold time.
+		 */
+		usec_delay(E1000_I2C_T_LOW);
+	} else {
+		status = E1000_ERR_I2C;
+		DEBUGOUT1("I2C data was not set to %X\n", data);
+	}
+
+	return status;
+}
+/**
+ *  e1000_raise_i2c_clk - Raises the I2C SCL clock
+ *  @hw: pointer to hardware structure
+ *  @i2cctl: Current value of I2CCTL register
+ *
+ *  Raises the I2C clock line '0'->'1'
+ **/
+static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
+{
+	DEBUGFUNC("e1000_raise_i2c_clk");
+
+	*i2cctl |= E1000_I2C_CLK_OUT;
+	*i2cctl &= ~E1000_I2C_CLK_OE_N;
+	E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
+	E1000_WRITE_FLUSH(hw);
+
+	/* SCL rise time (1000ns) */
+	usec_delay(E1000_I2C_T_RISE);
+}
+
+/**
+ *  e1000_lower_i2c_clk - Lowers the I2C SCL clock
+ *  @hw: pointer to hardware structure
+ *  @i2cctl: Current value of I2CCTL register
+ *
+ *  Lowers the I2C clock line '1'->'0'
+ **/
+static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
+{
+
+	DEBUGFUNC("e1000_lower_i2c_clk");
+
+	*i2cctl &= ~E1000_I2C_CLK_OUT;
+	*i2cctl &= ~E1000_I2C_CLK_OE_N;
+	E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
+	E1000_WRITE_FLUSH(hw);
+
+	/* SCL fall time (300ns) */
+	usec_delay(E1000_I2C_T_FALL);
+}
+
+/**
+ *  e1000_set_i2c_data - Sets the I2C data bit
+ *  @hw: pointer to hardware structure
+ *  @i2cctl: Current value of I2CCTL register
+ *  @data: I2C data value (0 or 1) to set
+ *
+ *  Sets the I2C data bit
+ **/
+static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
+{
+	s32 status = E1000_SUCCESS;
+
+	DEBUGFUNC("e1000_set_i2c_data");
+
+	if (data)
+		*i2cctl |= E1000_I2C_DATA_OUT;
+	else
+		*i2cctl &= ~E1000_I2C_DATA_OUT;
+
+	*i2cctl &= ~E1000_I2C_DATA_OE_N;
+	*i2cctl |= E1000_I2C_CLK_OE_N;
+	E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
+	E1000_WRITE_FLUSH(hw);
+
+	/* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
+	usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
+
+	*i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
+	if (data != e1000_get_i2c_data(i2cctl)) {
+		status = E1000_ERR_I2C;
+		DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
+	}
+
+	return status;
+}
+
+/**
+ *  e1000_get_i2c_data - Reads the I2C SDA data bit
+ *  @hw: pointer to hardware structure
+ *  @i2cctl: Current value of I2CCTL register
+ *
+ *  Returns the I2C data bit value
+ **/
+static bool e1000_get_i2c_data(u32 *i2cctl)
+{
+	bool data;
+
+	DEBUGFUNC("e1000_get_i2c_data");
+
+	if (*i2cctl & E1000_I2C_DATA_IN)
+		data = 1;
+	else
+		data = 0;
+
+	return data;
+}
+
+/**
+ *  e1000_i2c_bus_clear - Clears the I2C bus
+ *  @hw: pointer to hardware structure
+ *
+ *  Clears the I2C bus by sending nine clock pulses.
+ *  Used when data line is stuck low.
+ **/
+void e1000_i2c_bus_clear(struct e1000_hw *hw)
+{
+	u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
+	u32 i;
+
+	DEBUGFUNC("e1000_i2c_bus_clear");
+
+	e1000_i2c_start(hw);
+
+	e1000_set_i2c_data(hw, &i2cctl, 1);
+
+	for (i = 0; i < 9; i++) {
+		e1000_raise_i2c_clk(hw, &i2cctl);
+
+		/* Min high period of clock is 4us */
+		usec_delay(E1000_I2C_T_HIGH);
+
+		e1000_lower_i2c_clk(hw, &i2cctl);
+
+		/* Min low period of clock is 4.7us*/
+		usec_delay(E1000_I2C_T_LOW);
+	}
+
+	e1000_i2c_start(hw);
+
+	/* Put the i2c bus back to default state */
+	e1000_i2c_stop(hw);
+}
+
diff --git a/sys/dev/e1000/e1000_82575.h b/sys/dev/e1000/e1000_82575.h
index 529325b..4b2b245 100644
--- a/sys/dev/e1000/e1000_82575.h
+++ b/sys/dev/e1000/e1000_82575.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -35,10 +35,10 @@
 #ifndef _E1000_82575_H_
 #define _E1000_82575_H_
 
-#define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \
-                                     (ID_LED_DEF1_DEF2 <<  8) | \
-                                     (ID_LED_DEF1_DEF2 <<  4) | \
-                                     (ID_LED_OFF1_ON2))
+#define ID_LED_DEFAULT_82575_SERDES	((ID_LED_DEF1_DEF2 << 12) | \
+					 (ID_LED_DEF1_DEF2 <<  8) | \
+					 (ID_LED_DEF1_DEF2 <<  4) | \
+					 (ID_LED_OFF1_ON2))
 /*
  * Receive Address Register Count
  * Number of high/low register pairs in the RAR.  The RAR (Receive Address
@@ -49,13 +49,13 @@
  * For 82576, there are an additional set of RARs that begin at an offset
  * separate from the first set of RARs.
  */
-#define E1000_RAR_ENTRIES_82575        16
-#define E1000_RAR_ENTRIES_82576        24
-#define E1000_RAR_ENTRIES_82580        24
-#define E1000_RAR_ENTRIES_I350         32
-#define E1000_SW_SYNCH_MB              0x00000100
-#define E1000_STAT_DEV_RST_SET         0x00100000
-#define E1000_CTRL_DEV_RST             0x20000000
+#define E1000_RAR_ENTRIES_82575	16
+#define E1000_RAR_ENTRIES_82576	24
+#define E1000_RAR_ENTRIES_82580	24
+#define E1000_RAR_ENTRIES_I350	32
+#define E1000_SW_SYNCH_MB	0x00000100
+#define E1000_STAT_DEV_RST_SET	0x00100000
+#define E1000_CTRL_DEV_RST	0x20000000
 
 #ifdef E1000_BIT_FIELDS
 struct e1000_adv_data_desc {
@@ -63,137 +63,138 @@ struct e1000_adv_data_desc {
 	union {
 		u32 data;
 		struct {
-			u32 datalen :16; /* Data buffer length */
-			u32 rsvd    :4;
-			u32 dtyp    :4;  /* Descriptor type */
-			u32 dcmd    :8;  /* Descriptor command */
+			u32 datalen:16; /* Data buffer length */
+			u32 rsvd:4;
+			u32 dtyp:4;  /* Descriptor type */
+			u32 dcmd:8;  /* Descriptor command */
 		} config;
 	} lower;
 	union {
 		u32 data;
 		struct {
-			u32 status  :4;  /* Descriptor status */
-			u32 idx     :4;
-			u32 popts   :6;  /* Packet Options */
-			u32 paylen  :18; /* Payload length */
+			u32 status:4;  /* Descriptor status */
+			u32 idx:4;
+			u32 popts:6;  /* Packet Options */
+			u32 paylen:18; /* Payload length */
 		} options;
 	} upper;
 };
 
-#define E1000_TXD_DTYP_ADV_C    0x2  /* Advanced Context Descriptor */
-#define E1000_TXD_DTYP_ADV_D    0x3  /* Advanced Data Descriptor */
-#define E1000_ADV_TXD_CMD_DEXT  0x20 /* Descriptor extension (0 = legacy) */
-#define E1000_ADV_TUCMD_IPV4    0x2  /* IP Packet Type: 1=IPv4 */
-#define E1000_ADV_TUCMD_IPV6    0x0  /* IP Packet Type: 0=IPv6 */
-#define E1000_ADV_TUCMD_L4T_UDP 0x0  /* L4 Packet TYPE of UDP */
-#define E1000_ADV_TUCMD_L4T_TCP 0x4  /* L4 Packet TYPE of TCP */
-#define E1000_ADV_TUCMD_MKRREQ  0x10 /* Indicates markers are required */
-#define E1000_ADV_DCMD_EOP      0x1  /* End of Packet */
-#define E1000_ADV_DCMD_IFCS     0x2  /* Insert FCS (Ethernet CRC) */
-#define E1000_ADV_DCMD_RS       0x8  /* Report Status */
-#define E1000_ADV_DCMD_VLE      0x40 /* Add VLAN tag */
-#define E1000_ADV_DCMD_TSE      0x80 /* TCP Seg enable */
+#define E1000_TXD_DTYP_ADV_C	0x2  /* Advanced Context Descriptor */
+#define E1000_TXD_DTYP_ADV_D	0x3  /* Advanced Data Descriptor */
+#define E1000_ADV_TXD_CMD_DEXT	0x20 /* Descriptor extension (0 = legacy) */
+#define E1000_ADV_TUCMD_IPV4	0x2  /* IP Packet Type: 1=IPv4 */
+#define E1000_ADV_TUCMD_IPV6	0x0  /* IP Packet Type: 0=IPv6 */
+#define E1000_ADV_TUCMD_L4T_UDP	0x0  /* L4 Packet TYPE of UDP */
+#define E1000_ADV_TUCMD_L4T_TCP	0x4  /* L4 Packet TYPE of TCP */
+#define E1000_ADV_TUCMD_MKRREQ	0x10 /* Indicates markers are required */
+#define E1000_ADV_DCMD_EOP	0x1  /* End of Packet */
+#define E1000_ADV_DCMD_IFCS	0x2  /* Insert FCS (Ethernet CRC) */
+#define E1000_ADV_DCMD_RS	0x8  /* Report Status */
+#define E1000_ADV_DCMD_VLE	0x40 /* Add VLAN tag */
+#define E1000_ADV_DCMD_TSE	0x80 /* TCP Seg enable */
 /* Extended Device Control */
-#define E1000_CTRL_EXT_NSICR    0x00000001 /* Disable Intr Clear all on read */
+#define E1000_CTRL_EXT_NSICR	0x00000001 /* Disable Intr Clear all on read */
 
 struct e1000_adv_context_desc {
 	union {
 		u32 ip_config;
 		struct {
-			u32 iplen    :9;
-			u32 maclen   :7;
-			u32 vlan_tag :16;
+			u32 iplen:9;
+			u32 maclen:7;
+			u32 vlan_tag:16;
 		} fields;
 	} ip_setup;
 	u32 seq_num;
 	union {
 		u64 l4_config;
 		struct {
-			u32 mkrloc :9;
-			u32 tucmd  :11;
-			u32 dtyp   :4;
-			u32 adv    :8;
-			u32 rsvd   :4;
-			u32 idx    :4;
-			u32 l4len  :8;
-			u32 mss    :16;
+			u32 mkrloc:9;
+			u32 tucmd:11;
+			u32 dtyp:4;
+			u32 adv:8;
+			u32 rsvd:4;
+			u32 idx:4;
+			u32 l4len:8;
+			u32 mss:16;
 		} fields;
 	} l4_setup;
 };
 #endif
 
 /* SRRCTL bit definitions */
-#define E1000_SRRCTL_BSIZEPKT_SHIFT                     10 /* Shift _right_ */
-#define E1000_SRRCTL_BSIZEHDRSIZE_MASK                  0x00000F00
-#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT                 2  /* Shift _left_ */
-#define E1000_SRRCTL_DESCTYPE_LEGACY                    0x00000000
-#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF                0x02000000
-#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT                 0x04000000
-#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS          0x0A000000
-#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION           0x06000000
+#define E1000_SRRCTL_BSIZEPKT_SHIFT		10 /* Shift _right_ */
+#define E1000_SRRCTL_BSIZEHDRSIZE_MASK		0x00000F00
+#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT		2  /* Shift _left_ */
+#define E1000_SRRCTL_DESCTYPE_LEGACY		0x00000000
+#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF	0x02000000
+#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT		0x04000000
+#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS	0x0A000000
+#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION	0x06000000
 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
-#define E1000_SRRCTL_DESCTYPE_MASK                      0x0E000000
-#define E1000_SRRCTL_TIMESTAMP                          0x40000000
-#define E1000_SRRCTL_DROP_EN                            0x80000000
-
-#define E1000_SRRCTL_BSIZEPKT_MASK      0x0000007F
-#define E1000_SRRCTL_BSIZEHDR_MASK      0x00003F00
-
-#define E1000_TX_HEAD_WB_ENABLE   0x1
-#define E1000_TX_SEQNUM_WB_ENABLE 0x2
-
-#define E1000_MRQC_ENABLE_RSS_4Q            0x00000002
-#define E1000_MRQC_ENABLE_VMDQ              0x00000003
-#define E1000_MRQC_ENABLE_VMDQ_RSS_2Q       0x00000005
-#define E1000_MRQC_RSS_FIELD_IPV4_UDP       0x00400000
-#define E1000_MRQC_RSS_FIELD_IPV6_UDP       0x00800000
-#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX    0x01000000
-#define E1000_MRQC_ENABLE_RSS_8Q            0x00000002
-
-#define E1000_VMRCTL_MIRROR_PORT_SHIFT      8
-#define E1000_VMRCTL_MIRROR_DSTPORT_MASK    (7 << E1000_VMRCTL_MIRROR_PORT_SHIFT)
-#define E1000_VMRCTL_POOL_MIRROR_ENABLE     (1 << 0)
-#define E1000_VMRCTL_UPLINK_MIRROR_ENABLE   (1 << 1)
-#define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE (1 << 2)
+#define E1000_SRRCTL_DESCTYPE_MASK		0x0E000000
+#define E1000_SRRCTL_TIMESTAMP			0x40000000
+#define E1000_SRRCTL_DROP_EN			0x80000000
+
+#define E1000_SRRCTL_BSIZEPKT_MASK		0x0000007F
+#define E1000_SRRCTL_BSIZEHDR_MASK		0x00003F00
+
+#define E1000_TX_HEAD_WB_ENABLE		0x1
+#define E1000_TX_SEQNUM_WB_ENABLE	0x2
+
+#define E1000_MRQC_ENABLE_RSS_4Q		0x00000002
+#define E1000_MRQC_ENABLE_VMDQ			0x00000003
+#define E1000_MRQC_ENABLE_VMDQ_RSS_2Q		0x00000005
+#define E1000_MRQC_RSS_FIELD_IPV4_UDP		0x00400000
+#define E1000_MRQC_RSS_FIELD_IPV6_UDP		0x00800000
+#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX	0x01000000
+#define E1000_MRQC_ENABLE_RSS_8Q		0x00000002
+
+#define E1000_VMRCTL_MIRROR_PORT_SHIFT		8
+#define E1000_VMRCTL_MIRROR_DSTPORT_MASK	(7 << \
+						 E1000_VMRCTL_MIRROR_PORT_SHIFT)
+#define E1000_VMRCTL_POOL_MIRROR_ENABLE		(1 << 0)
+#define E1000_VMRCTL_UPLINK_MIRROR_ENABLE	(1 << 1)
+#define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE	(1 << 2)
 
 #define E1000_EICR_TX_QUEUE ( \
-    E1000_EICR_TX_QUEUE0 |    \
-    E1000_EICR_TX_QUEUE1 |    \
-    E1000_EICR_TX_QUEUE2 |    \
-    E1000_EICR_TX_QUEUE3)
+	E1000_EICR_TX_QUEUE0 |    \
+	E1000_EICR_TX_QUEUE1 |    \
+	E1000_EICR_TX_QUEUE2 |    \
+	E1000_EICR_TX_QUEUE3)
 
 #define E1000_EICR_RX_QUEUE ( \
-    E1000_EICR_RX_QUEUE0 |    \
-    E1000_EICR_RX_QUEUE1 |    \
-    E1000_EICR_RX_QUEUE2 |    \
-    E1000_EICR_RX_QUEUE3)
+	E1000_EICR_RX_QUEUE0 |    \
+	E1000_EICR_RX_QUEUE1 |    \
+	E1000_EICR_RX_QUEUE2 |    \
+	E1000_EICR_RX_QUEUE3)
 
-#define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE
-#define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE
+#define E1000_EIMS_RX_QUEUE	E1000_EICR_RX_QUEUE
+#define E1000_EIMS_TX_QUEUE	E1000_EICR_TX_QUEUE
 
 #define EIMS_ENABLE_MASK ( \
-    E1000_EIMS_RX_QUEUE  | \
-    E1000_EIMS_TX_QUEUE  | \
-    E1000_EIMS_TCP_TIMER | \
-    E1000_EIMS_OTHER)
+	E1000_EIMS_RX_QUEUE  | \
+	E1000_EIMS_TX_QUEUE  | \
+	E1000_EIMS_TCP_TIMER | \
+	E1000_EIMS_OTHER)
 
 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
-#define E1000_IMIR_PORT_IM_EN     0x00010000  /* TCP port enable */
-#define E1000_IMIR_PORT_BP        0x00020000  /* TCP port check bypass */
-#define E1000_IMIREXT_SIZE_BP     0x00001000  /* Packet size bypass */
-#define E1000_IMIREXT_CTRL_URG    0x00002000  /* Check URG bit in header */
-#define E1000_IMIREXT_CTRL_ACK    0x00004000  /* Check ACK bit in header */
-#define E1000_IMIREXT_CTRL_PSH    0x00008000  /* Check PSH bit in header */
-#define E1000_IMIREXT_CTRL_RST    0x00010000  /* Check RST bit in header */
-#define E1000_IMIREXT_CTRL_SYN    0x00020000  /* Check SYN bit in header */
-#define E1000_IMIREXT_CTRL_FIN    0x00040000  /* Check FIN bit in header */
-#define E1000_IMIREXT_CTRL_BP     0x00080000  /* Bypass check of ctrl bits */
+#define E1000_IMIR_PORT_IM_EN	0x00010000  /* TCP port enable */
+#define E1000_IMIR_PORT_BP	0x00020000  /* TCP port check bypass */
+#define E1000_IMIREXT_SIZE_BP	0x00001000  /* Packet size bypass */
+#define E1000_IMIREXT_CTRL_URG	0x00002000  /* Check URG bit in header */
+#define E1000_IMIREXT_CTRL_ACK	0x00004000  /* Check ACK bit in header */
+#define E1000_IMIREXT_CTRL_PSH	0x00008000  /* Check PSH bit in header */
+#define E1000_IMIREXT_CTRL_RST	0x00010000  /* Check RST bit in header */
+#define E1000_IMIREXT_CTRL_SYN	0x00020000  /* Check SYN bit in header */
+#define E1000_IMIREXT_CTRL_FIN	0x00040000  /* Check FIN bit in header */
+#define E1000_IMIREXT_CTRL_BP	0x00080000  /* Bypass check of ctrl bits */
 
 /* Receive Descriptor - Advanced */
 union e1000_adv_rx_desc {
 	struct {
-		__le64 pkt_addr;             /* Packet buffer address */
-		__le64 hdr_addr;             /* Header buffer address */
+		__le64 pkt_addr; /* Packet buffer address */
+		__le64 hdr_addr; /* Header buffer address */
 	} read;
 	struct {
 		struct {
@@ -206,74 +207,74 @@ union e1000_adv_rx_desc {
 				} hs_rss;
 			} lo_dword;
 			union {
-				__le32 rss;          /* RSS Hash */
+				__le32 rss; /* RSS Hash */
 				struct {
-					__le16 ip_id;    /* IP id */
-					__le16 csum;     /* Packet Checksum */
+					__le16 ip_id; /* IP id */
+					__le16 csum; /* Packet Checksum */
 				} csum_ip;
 			} hi_dword;
 		} lower;
 		struct {
-			__le32 status_error;     /* ext status/error */
-			__le16 length;           /* Packet length */
-			__le16 vlan;             /* VLAN tag */
+			__le32 status_error; /* ext status/error */
+			__le16 length; /* Packet length */
+			__le16 vlan; /* VLAN tag */
 		} upper;
 	} wb;  /* writeback */
 };
 
-#define E1000_RXDADV_RSSTYPE_MASK        0x0000000F
-#define E1000_RXDADV_RSSTYPE_SHIFT       12
-#define E1000_RXDADV_HDRBUFLEN_MASK      0x7FE0
-#define E1000_RXDADV_HDRBUFLEN_SHIFT     5
-#define E1000_RXDADV_SPLITHEADER_EN      0x00001000
-#define E1000_RXDADV_SPH                 0x8000
-#define E1000_RXDADV_STAT_TS             0x10000 /* Pkt was time stamped */
-#define E1000_RXDADV_STAT_TSIP           0x08000 /* timestamp in packet */
-#define E1000_RXDADV_ERR_HBO             0x00800000
+#define E1000_RXDADV_RSSTYPE_MASK	0x0000000F
+#define E1000_RXDADV_RSSTYPE_SHIFT	12
+#define E1000_RXDADV_HDRBUFLEN_MASK	0x7FE0
+#define E1000_RXDADV_HDRBUFLEN_SHIFT	5
+#define E1000_RXDADV_SPLITHEADER_EN	0x00001000
+#define E1000_RXDADV_SPH		0x8000
+#define E1000_RXDADV_STAT_TS		0x10000 /* Pkt was time stamped */
+#define E1000_RXDADV_STAT_TSIP		0x08000 /* timestamp in packet */
+#define E1000_RXDADV_ERR_HBO		0x00800000
 
 /* RSS Hash results */
-#define E1000_RXDADV_RSSTYPE_NONE        0x00000000
-#define E1000_RXDADV_RSSTYPE_IPV4_TCP    0x00000001
-#define E1000_RXDADV_RSSTYPE_IPV4        0x00000002
-#define E1000_RXDADV_RSSTYPE_IPV6_TCP    0x00000003
-#define E1000_RXDADV_RSSTYPE_IPV6_EX     0x00000004
-#define E1000_RXDADV_RSSTYPE_IPV6        0x00000005
+#define E1000_RXDADV_RSSTYPE_NONE	0x00000000
+#define E1000_RXDADV_RSSTYPE_IPV4_TCP	0x00000001
+#define E1000_RXDADV_RSSTYPE_IPV4	0x00000002
+#define E1000_RXDADV_RSSTYPE_IPV6_TCP	0x00000003
+#define E1000_RXDADV_RSSTYPE_IPV6_EX	0x00000004
+#define E1000_RXDADV_RSSTYPE_IPV6	0x00000005
 #define E1000_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
-#define E1000_RXDADV_RSSTYPE_IPV4_UDP    0x00000007
-#define E1000_RXDADV_RSSTYPE_IPV6_UDP    0x00000008
+#define E1000_RXDADV_RSSTYPE_IPV4_UDP	0x00000007
+#define E1000_RXDADV_RSSTYPE_IPV6_UDP	0x00000008
 #define E1000_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
 
 /* RSS Packet Types as indicated in the receive descriptor */
-#define E1000_RXDADV_PKTTYPE_NONE        0x00000000
-#define E1000_RXDADV_PKTTYPE_IPV4        0x00000010 /* IPV4 hdr present */
-#define E1000_RXDADV_PKTTYPE_IPV4_EX     0x00000020 /* IPV4 hdr + extensions */
-#define E1000_RXDADV_PKTTYPE_IPV6        0x00000040 /* IPV6 hdr present */
-#define E1000_RXDADV_PKTTYPE_IPV6_EX     0x00000080 /* IPV6 hdr + extensions */
-#define E1000_RXDADV_PKTTYPE_TCP         0x00000100 /* TCP hdr present */
-#define E1000_RXDADV_PKTTYPE_UDP         0x00000200 /* UDP hdr present */
-#define E1000_RXDADV_PKTTYPE_SCTP        0x00000400 /* SCTP hdr present */
-#define E1000_RXDADV_PKTTYPE_NFS         0x00000800 /* NFS hdr present */
-
-#define E1000_RXDADV_PKTTYPE_IPSEC_ESP   0x00001000 /* IPSec ESP */
-#define E1000_RXDADV_PKTTYPE_IPSEC_AH    0x00002000 /* IPSec AH */
-#define E1000_RXDADV_PKTTYPE_LINKSEC     0x00004000 /* LinkSec Encap */
-#define E1000_RXDADV_PKTTYPE_ETQF        0x00008000 /* PKTTYPE is ETQF index */
-#define E1000_RXDADV_PKTTYPE_ETQF_MASK   0x00000070 /* ETQF has 8 indices */
-#define E1000_RXDADV_PKTTYPE_ETQF_SHIFT  4          /* Right-shift 4 bits */
+#define E1000_RXDADV_PKTTYPE_NONE	0x00000000
+#define E1000_RXDADV_PKTTYPE_IPV4	0x00000010 /* IPV4 hdr present */
+#define E1000_RXDADV_PKTTYPE_IPV4_EX	0x00000020 /* IPV4 hdr + extensions */
+#define E1000_RXDADV_PKTTYPE_IPV6	0x00000040 /* IPV6 hdr present */
+#define E1000_RXDADV_PKTTYPE_IPV6_EX	0x00000080 /* IPV6 hdr + extensions */
+#define E1000_RXDADV_PKTTYPE_TCP	0x00000100 /* TCP hdr present */
+#define E1000_RXDADV_PKTTYPE_UDP	0x00000200 /* UDP hdr present */
+#define E1000_RXDADV_PKTTYPE_SCTP	0x00000400 /* SCTP hdr present */
+#define E1000_RXDADV_PKTTYPE_NFS	0x00000800 /* NFS hdr present */
+
+#define E1000_RXDADV_PKTTYPE_IPSEC_ESP	0x00001000 /* IPSec ESP */
+#define E1000_RXDADV_PKTTYPE_IPSEC_AH	0x00002000 /* IPSec AH */
+#define E1000_RXDADV_PKTTYPE_LINKSEC	0x00004000 /* LinkSec Encap */
+#define E1000_RXDADV_PKTTYPE_ETQF	0x00008000 /* PKTTYPE is ETQF index */
+#define E1000_RXDADV_PKTTYPE_ETQF_MASK	0x00000070 /* ETQF has 8 indices */
+#define E1000_RXDADV_PKTTYPE_ETQF_SHIFT	4 /* Right-shift 4 bits */
 
 /* LinkSec results */
 /* Security Processing bit Indication */
-#define E1000_RXDADV_LNKSEC_STATUS_SECP         0x00020000
-#define E1000_RXDADV_LNKSEC_ERROR_BIT_MASK      0x18000000
-#define E1000_RXDADV_LNKSEC_ERROR_NO_SA_MATCH   0x08000000
-#define E1000_RXDADV_LNKSEC_ERROR_REPLAY_ERROR  0x10000000
-#define E1000_RXDADV_LNKSEC_ERROR_BAD_SIG       0x18000000
-
-#define E1000_RXDADV_IPSEC_STATUS_SECP          0x00020000
-#define E1000_RXDADV_IPSEC_ERROR_BIT_MASK       0x18000000
-#define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL       0x08000000
-#define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH         0x10000000
-#define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED  0x18000000
+#define E1000_RXDADV_LNKSEC_STATUS_SECP		0x00020000
+#define E1000_RXDADV_LNKSEC_ERROR_BIT_MASK	0x18000000
+#define E1000_RXDADV_LNKSEC_ERROR_NO_SA_MATCH	0x08000000
+#define E1000_RXDADV_LNKSEC_ERROR_REPLAY_ERROR	0x10000000
+#define E1000_RXDADV_LNKSEC_ERROR_BAD_SIG	0x18000000
+
+#define E1000_RXDADV_IPSEC_STATUS_SECP			0x00020000
+#define E1000_RXDADV_IPSEC_ERROR_BIT_MASK		0x18000000
+#define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL	0x08000000
+#define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH		0x10000000
+#define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED	0x18000000
 
 /* Transmit Descriptor - Advanced */
 union e1000_adv_tx_desc {
@@ -290,25 +291,26 @@ union e1000_adv_tx_desc {
 };
 
 /* Adv Transmit Descriptor Config Masks */
-#define E1000_ADVTXD_DTYP_CTXT    0x00200000 /* Advanced Context Descriptor */
-#define E1000_ADVTXD_DTYP_DATA    0x00300000 /* Advanced Data Descriptor */
-#define E1000_ADVTXD_DCMD_EOP     0x01000000 /* End of Packet */
-#define E1000_ADVTXD_DCMD_IFCS    0x02000000 /* Insert FCS (Ethernet CRC) */
-#define E1000_ADVTXD_DCMD_RS      0x08000000 /* Report Status */
-#define E1000_ADVTXD_DCMD_DDTYP_ISCSI  0x10000000 /* DDP hdr type or iSCSI */
-#define E1000_ADVTXD_DCMD_DEXT    0x20000000 /* Descriptor extension (1=Adv) */
-#define E1000_ADVTXD_DCMD_VLE     0x40000000 /* VLAN pkt enable */
-#define E1000_ADVTXD_DCMD_TSE     0x80000000 /* TCP Seg enable */
-#define E1000_ADVTXD_MAC_LINKSEC  0x00040000 /* Apply LinkSec on packet */
-#define E1000_ADVTXD_MAC_TSTAMP   0x00080000 /* IEEE1588 Timestamp packet */
-#define E1000_ADVTXD_STAT_SN_CRC  0x00000002 /* NXTSEQ/SEED present in WB */
-#define E1000_ADVTXD_IDX_SHIFT    4  /* Adv desc Index shift */
-#define E1000_ADVTXD_POPTS_ISCO_1ST  0x00000000 /* 1st TSO of iSCSI PDU */
-#define E1000_ADVTXD_POPTS_ISCO_MDL  0x00000800 /* Middle TSO of iSCSI PDU */
-#define E1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
-#define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU*/
-#define E1000_ADVTXD_POPTS_IPSEC     0x00000400 /* IPSec offload request */
-#define E1000_ADVTXD_PAYLEN_SHIFT    14 /* Adv desc PAYLEN shift */
+#define E1000_ADVTXD_DTYP_CTXT	0x00200000 /* Advanced Context Descriptor */
+#define E1000_ADVTXD_DTYP_DATA	0x00300000 /* Advanced Data Descriptor */
+#define E1000_ADVTXD_DCMD_EOP	0x01000000 /* End of Packet */
+#define E1000_ADVTXD_DCMD_IFCS	0x02000000 /* Insert FCS (Ethernet CRC) */
+#define E1000_ADVTXD_DCMD_RS	0x08000000 /* Report Status */
+#define E1000_ADVTXD_DCMD_DDTYP_ISCSI	0x10000000 /* DDP hdr type or iSCSI */
+#define E1000_ADVTXD_DCMD_DEXT	0x20000000 /* Descriptor extension (1=Adv) */
+#define E1000_ADVTXD_DCMD_VLE	0x40000000 /* VLAN pkt enable */
+#define E1000_ADVTXD_DCMD_TSE	0x80000000 /* TCP Seg enable */
+#define E1000_ADVTXD_MAC_LINKSEC	0x00040000 /* Apply LinkSec on pkt */
+#define E1000_ADVTXD_MAC_TSTAMP		0x00080000 /* IEEE1588 Timestamp pkt */
+#define E1000_ADVTXD_STAT_SN_CRC	0x00000002 /* NXTSEQ/SEED prsnt in WB */
+#define E1000_ADVTXD_IDX_SHIFT		4  /* Adv desc Index shift */
+#define E1000_ADVTXD_POPTS_ISCO_1ST	0x00000000 /* 1st TSO of iSCSI PDU */
+#define E1000_ADVTXD_POPTS_ISCO_MDL	0x00000800 /* Middle TSO of iSCSI PDU */
+#define E1000_ADVTXD_POPTS_ISCO_LAST	0x00001000 /* Last TSO of iSCSI PDU */
+/* 1st & Last TSO-full iSCSI PDU*/
+#define E1000_ADVTXD_POPTS_ISCO_FULL	0x00001800
+#define E1000_ADVTXD_POPTS_IPSEC	0x00000400 /* IPSec offload request */
+#define E1000_ADVTXD_PAYLEN_SHIFT	14 /* Adv desc PAYLEN shift */
 
 /* Context descriptors */
 struct e1000_adv_tx_context_desc {
@@ -318,65 +320,66 @@ struct e1000_adv_tx_context_desc {
 	__le32 mss_l4len_idx;
 };
 
-#define E1000_ADVTXD_MACLEN_SHIFT    9  /* Adv ctxt desc mac len shift */
-#define E1000_ADVTXD_VLAN_SHIFT     16  /* Adv ctxt vlan tag shift */
-#define E1000_ADVTXD_TUCMD_IPV4    0x00000400  /* IP Packet Type: 1=IPv4 */
-#define E1000_ADVTXD_TUCMD_IPV6    0x00000000  /* IP Packet Type: 0=IPv6 */
-#define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000  /* L4 Packet TYPE of UDP */
-#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800  /* L4 Packet TYPE of TCP */
-#define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000  /* L4 Packet TYPE of SCTP */
-#define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP    0x00002000 /* IPSec Type ESP */
+#define E1000_ADVTXD_MACLEN_SHIFT	9  /* Adv ctxt desc mac len shift */
+#define E1000_ADVTXD_VLAN_SHIFT		16  /* Adv ctxt vlan tag shift */
+#define E1000_ADVTXD_TUCMD_IPV4		0x00000400  /* IP Packet Type: 1=IPv4 */
+#define E1000_ADVTXD_TUCMD_IPV6		0x00000000  /* IP Packet Type: 0=IPv6 */
+#define E1000_ADVTXD_TUCMD_L4T_UDP	0x00000000  /* L4 Packet TYPE of UDP */
+#define E1000_ADVTXD_TUCMD_L4T_TCP	0x00000800  /* L4 Packet TYPE of TCP */
+#define E1000_ADVTXD_TUCMD_L4T_SCTP	0x00001000  /* L4 Packet TYPE of SCTP */
+#define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP	0x00002000 /* IPSec Type ESP */
 /* IPSec Encrypt Enable for ESP */
-#define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN  0x00004000
-#define E1000_ADVTXD_TUCMD_MKRREQ  0x00002000 /* Req requires Markers and CRC */
-#define E1000_ADVTXD_L4LEN_SHIFT     8  /* Adv ctxt L4LEN shift */
-#define E1000_ADVTXD_MSS_SHIFT      16  /* Adv ctxt MSS shift */
+#define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN	0x00004000
+/* Req requires Markers and CRC */
+#define E1000_ADVTXD_TUCMD_MKRREQ	0x00002000
+#define E1000_ADVTXD_L4LEN_SHIFT	8  /* Adv ctxt L4LEN shift */
+#define E1000_ADVTXD_MSS_SHIFT		16  /* Adv ctxt MSS shift */
 /* Adv ctxt IPSec SA IDX mask */
-#define E1000_ADVTXD_IPSEC_SA_INDEX_MASK     0x000000FF
+#define E1000_ADVTXD_IPSEC_SA_INDEX_MASK	0x000000FF
 /* Adv ctxt IPSec ESP len mask */
-#define E1000_ADVTXD_IPSEC_ESP_LEN_MASK      0x000000FF
+#define E1000_ADVTXD_IPSEC_ESP_LEN_MASK		0x000000FF
 
 /* Additional Transmit Descriptor Control definitions */
-#define E1000_TXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Tx Queue */
-#define E1000_TXDCTL_SWFLSH        0x04000000 /* Tx Desc. write-back flushing */
+#define E1000_TXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Tx Queue */
+#define E1000_TXDCTL_SWFLSH		0x04000000 /* Tx Desc. wbk flushing */
 /* Tx Queue Arbitration Priority 0=low, 1=high */
-#define E1000_TXDCTL_PRIORITY      0x08000000
+#define E1000_TXDCTL_PRIORITY		0x08000000
 
 /* Additional Receive Descriptor Control definitions */
-#define E1000_RXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Rx Queue */
-#define E1000_RXDCTL_SWFLSH        0x04000000 /* Rx Desc. write-back flushing */
+#define E1000_RXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Rx Queue */
+#define E1000_RXDCTL_SWFLSH		0x04000000 /* Rx Desc. wbk flushing */
 
 /* Direct Cache Access (DCA) definitions */
-#define E1000_DCA_CTRL_DCA_ENABLE  0x00000000 /* DCA Enable */
-#define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
+#define E1000_DCA_CTRL_DCA_ENABLE	0x00000000 /* DCA Enable */
+#define E1000_DCA_CTRL_DCA_DISABLE	0x00000001 /* DCA Disable */
 
-#define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
-#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
+#define E1000_DCA_CTRL_DCA_MODE_CB1	0x00 /* DCA Mode CB1 */
+#define E1000_DCA_CTRL_DCA_MODE_CB2	0x02 /* DCA Mode CB2 */
 
-#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
-#define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
-#define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
-#define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
+#define E1000_DCA_RXCTRL_CPUID_MASK	0x0000001F /* Rx CPUID Mask */
+#define E1000_DCA_RXCTRL_DESC_DCA_EN	(1 << 5) /* DCA Rx Desc enable */
+#define E1000_DCA_RXCTRL_HEAD_DCA_EN	(1 << 6) /* DCA Rx Desc header ena */
+#define E1000_DCA_RXCTRL_DATA_DCA_EN	(1 << 7) /* DCA Rx Desc payload ena */
 
-#define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
-#define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
-#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
+#define E1000_DCA_TXCTRL_CPUID_MASK	0x0000001F /* Tx CPUID Mask */
+#define E1000_DCA_TXCTRL_DESC_DCA_EN	(1 << 5) /* DCA Tx Desc enable */
+#define E1000_DCA_TXCTRL_TX_WB_RO_EN	(1 << 11) /* Tx Desc writeback RO bit */
 
-#define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
-#define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
-#define E1000_DCA_TXCTRL_CPUID_SHIFT_82576 24 /* Tx CPUID */
-#define E1000_DCA_RXCTRL_CPUID_SHIFT_82576 24 /* Rx CPUID */
+#define E1000_DCA_TXCTRL_CPUID_MASK_82576	0xFF000000 /* Tx CPUID Mask */
+#define E1000_DCA_RXCTRL_CPUID_MASK_82576	0xFF000000 /* Rx CPUID Mask */
+#define E1000_DCA_TXCTRL_CPUID_SHIFT_82576	24 /* Tx CPUID */
+#define E1000_DCA_RXCTRL_CPUID_SHIFT_82576	24 /* Rx CPUID */
 
 /* Additional interrupt register bit definitions */
-#define E1000_ICR_LSECPNS       0x00000020          /* PN threshold - server */
-#define E1000_IMS_LSECPNS       E1000_ICR_LSECPNS   /* PN threshold - server */
-#define E1000_ICS_LSECPNS       E1000_ICR_LSECPNS   /* PN threshold - server */
+#define E1000_ICR_LSECPNS	0x00000020 /* PN threshold - server */
+#define E1000_IMS_LSECPNS	E1000_ICR_LSECPNS /* PN threshold - server */
+#define E1000_ICS_LSECPNS	E1000_ICR_LSECPNS /* PN threshold - server */
 
 /* ETQF register bit definitions */
-#define E1000_ETQF_FILTER_ENABLE   (1 << 26)
-#define E1000_ETQF_IMM_INT         (1 << 29)
-#define E1000_ETQF_1588            (1 << 30)
-#define E1000_ETQF_QUEUE_ENABLE    (1 << 31)
+#define E1000_ETQF_FILTER_ENABLE	(1 << 26)
+#define E1000_ETQF_IMM_INT		(1 << 29)
+#define E1000_ETQF_1588			(1 << 30)
+#define E1000_ETQF_QUEUE_ENABLE		(1 << 31)
 /*
  * ETQF filter list: one static filter per filter consumer. This is
  *                   to avoid filter collisions later. Add new filters
@@ -385,87 +388,89 @@ struct e1000_adv_tx_context_desc {
  * Current filters:
  *    EAPOL 802.1x (0x888e): Filter 0
  */
-#define E1000_ETQF_FILTER_EAPOL          0
-
-#define E1000_FTQF_VF_BP               0x00008000
-#define E1000_FTQF_1588_TIME_STAMP     0x08000000
-#define E1000_FTQF_MASK                0xF0000000
-#define E1000_FTQF_MASK_PROTO_BP       0x10000000
-#define E1000_FTQF_MASK_SOURCE_ADDR_BP 0x20000000
-#define E1000_FTQF_MASK_DEST_ADDR_BP   0x40000000
-#define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000
-
-#define E1000_NVM_APME_82575          0x0400
-#define MAX_NUM_VFS                   8
-
-#define E1000_DTXSWC_MAC_SPOOF_MASK   0x000000FF /* Per VF MAC spoof control */
-#define E1000_DTXSWC_VLAN_SPOOF_MASK  0x0000FF00 /* Per VF VLAN spoof control */
-#define E1000_DTXSWC_LLE_MASK         0x00FF0000 /* Per VF Local LB enables */
-#define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
-#define E1000_DTXSWC_LLE_SHIFT        16
-#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31)  /* global VF LB enable */
+#define E1000_ETQF_FILTER_EAPOL		0
+
+#define E1000_FTQF_VF_BP		0x00008000
+#define E1000_FTQF_1588_TIME_STAMP	0x08000000
+#define E1000_FTQF_MASK			0xF0000000
+#define E1000_FTQF_MASK_PROTO_BP	0x10000000
+#define E1000_FTQF_MASK_SOURCE_ADDR_BP	0x20000000
+#define E1000_FTQF_MASK_DEST_ADDR_BP	0x40000000
+#define E1000_FTQF_MASK_SOURCE_PORT_BP	0x80000000
+
+#define E1000_NVM_APME_82575		0x0400
+#define MAX_NUM_VFS			7
+
+#define E1000_DTXSWC_MAC_SPOOF_MASK	0x000000FF /* Per VF MAC spoof cntrl */
+#define E1000_DTXSWC_VLAN_SPOOF_MASK	0x0000FF00 /* Per VF VLAN spoof cntrl */
+#define E1000_DTXSWC_LLE_MASK		0x00FF0000 /* Per VF Local LB enables */
+#define E1000_DTXSWC_VLAN_SPOOF_SHIFT	8
+#define E1000_DTXSWC_LLE_SHIFT		16
+#define E1000_DTXSWC_VMDQ_LOOPBACK_EN	(1 << 31)  /* global VF LB enable */
 
 /* Easy defines for setting default pool, would normally be left a zero */
-#define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
-#define E1000_VT_CTL_DEFAULT_POOL_MASK  (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
+#define E1000_VT_CTL_DEFAULT_POOL_SHIFT	7
+#define E1000_VT_CTL_DEFAULT_POOL_MASK	(0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
 
 /* Other useful VMD_CTL register defines */
-#define E1000_VT_CTL_IGNORE_MAC         (1 << 28)
-#define E1000_VT_CTL_DISABLE_DEF_POOL   (1 << 29)
-#define E1000_VT_CTL_VM_REPL_EN         (1 << 30)
+#define E1000_VT_CTL_IGNORE_MAC		(1 << 28)
+#define E1000_VT_CTL_DISABLE_DEF_POOL	(1 << 29)
+#define E1000_VT_CTL_VM_REPL_EN		(1 << 30)
 
 /* Per VM Offload register setup */
-#define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */
-#define E1000_VMOLR_LPE        0x00010000 /* Accept Long packet */
-#define E1000_VMOLR_RSSE       0x00020000 /* Enable RSS */
-#define E1000_VMOLR_AUPE       0x01000000 /* Accept untagged packets */
-#define E1000_VMOLR_ROMPE      0x02000000 /* Accept overflow multicast */
-#define E1000_VMOLR_ROPE       0x04000000 /* Accept overflow unicast */
-#define E1000_VMOLR_BAM        0x08000000 /* Accept Broadcast packets */
-#define E1000_VMOLR_MPME       0x10000000 /* Multicast promiscuous mode */
-#define E1000_VMOLR_STRVLAN    0x40000000 /* Vlan stripping enable */
-#define E1000_VMOLR_STRCRC     0x80000000 /* CRC stripping enable */
-
-#define E1000_VMOLR_VPE        0x00800000 /* VLAN promiscuous enable */
-#define E1000_VMOLR_UPE        0x20000000 /* Unicast promisuous enable */
-#define E1000_DVMOLR_HIDVLAN   0x20000000 /* Vlan hiding enable */
-#define E1000_DVMOLR_STRVLAN   0x40000000 /* Vlan stripping enable */
-#define E1000_DVMOLR_STRCRC    0x80000000 /* CRC stripping enable */
-
-#define E1000_PBRWAC_WALPB     0x00000007 /* Wrap around event on LAN Rx PB */
-#define E1000_PBRWAC_PBE       0x00000008 /* Rx packet buffer empty */
-
-#define E1000_VLVF_ARRAY_SIZE     32
-#define E1000_VLVF_VLANID_MASK    0x00000FFF
-#define E1000_VLVF_POOLSEL_SHIFT  12
-#define E1000_VLVF_POOLSEL_MASK   (0xFF << E1000_VLVF_POOLSEL_SHIFT)
-#define E1000_VLVF_LVLAN          0x00100000
-#define E1000_VLVF_VLANID_ENABLE  0x80000000
-
-#define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
-#define E1000_VMVIR_VLANA_NEVER   0x80000000 /* Never insert VLAN tag */
-
-#define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
-
-#define E1000_IOVCTL 0x05BBC
-#define E1000_IOVCTL_REUSE_VFQ 0x00000001
-
-#define E1000_RPLOLR_STRVLAN   0x40000000
-#define E1000_RPLOLR_STRCRC    0x80000000
-
-#define E1000_TCTL_EXT_COLD       0x000FFC00
-#define E1000_TCTL_EXT_COLD_SHIFT 10
-
-#define E1000_DTXCTL_8023LL     0x0004
-#define E1000_DTXCTL_VLAN_ADDED 0x0008
-#define E1000_DTXCTL_OOS_ENABLE 0x0010
-#define E1000_DTXCTL_MDP_EN     0x0020
-#define E1000_DTXCTL_SPOOF_INT  0x0040
-
-#define ALL_QUEUES   0xFFFF
+#define E1000_VMOLR_RLPML_MASK	0x00003FFF /* Long Packet Maximum Length mask */
+#define E1000_VMOLR_LPE		0x00010000 /* Accept Long packet */
+#define E1000_VMOLR_RSSE	0x00020000 /* Enable RSS */
+#define E1000_VMOLR_AUPE	0x01000000 /* Accept untagged packets */
+#define E1000_VMOLR_ROMPE	0x02000000 /* Accept overflow multicast */
+#define E1000_VMOLR_ROPE	0x04000000 /* Accept overflow unicast */
+#define E1000_VMOLR_BAM		0x08000000 /* Accept Broadcast packets */
+#define E1000_VMOLR_MPME	0x10000000 /* Multicast promiscuous mode */
+#define E1000_VMOLR_STRVLAN	0x40000000 /* Vlan stripping enable */
+#define E1000_VMOLR_STRCRC	0x80000000 /* CRC stripping enable */
+
+#define E1000_VMOLR_VPE		0x00800000 /* VLAN promiscuous enable */
+#define E1000_VMOLR_UPE		0x20000000 /* Unicast promisuous enable */
+#define E1000_DVMOLR_HIDVLAN	0x20000000 /* Vlan hiding enable */
+#define E1000_DVMOLR_STRVLAN	0x40000000 /* Vlan stripping enable */
+#define E1000_DVMOLR_STRCRC	0x80000000 /* CRC stripping enable */
+
+#define E1000_PBRWAC_WALPB	0x00000007 /* Wrap around event on LAN Rx PB */
+#define E1000_PBRWAC_PBE	0x00000008 /* Rx packet buffer empty */
+
+#define E1000_VLVF_ARRAY_SIZE		32
+#define E1000_VLVF_VLANID_MASK		0x00000FFF
+#define E1000_VLVF_POOLSEL_SHIFT	12
+#define E1000_VLVF_POOLSEL_MASK		(0xFF << E1000_VLVF_POOLSEL_SHIFT)
+#define E1000_VLVF_LVLAN		0x00100000
+#define E1000_VLVF_VLANID_ENABLE	0x80000000
+
+#define E1000_VMVIR_VLANA_DEFAULT	0x40000000 /* Always use default VLAN */
+#define E1000_VMVIR_VLANA_NEVER		0x80000000 /* Never insert VLAN tag */
+
+#define E1000_VF_INIT_TIMEOUT	200 /* Number of retries to clear RSTI */
+
+#define E1000_IOVCTL		0x05BBC
+#define E1000_IOVCTL_REUSE_VFQ	0x00000001
+
+#define E1000_RPLOLR_STRVLAN	0x40000000
+#define E1000_RPLOLR_STRCRC	0x80000000
+
+#define E1000_TCTL_EXT_COLD	0x000FFC00
+#define E1000_TCTL_EXT_COLD_SHIFT	10
+
+#define E1000_DTXCTL_8023LL	0x0004
+#define E1000_DTXCTL_VLAN_ADDED	0x0008
+#define E1000_DTXCTL_OOS_ENABLE	0x0010
+#define E1000_DTXCTL_MDP_EN	0x0020
+#define E1000_DTXCTL_SPOOF_INT	0x0040
+
+#define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT	(1 << 14)
+
+#define ALL_QUEUES		0xFFFF
 
 /* Rx packet buffer size defines */
-#define E1000_RXPBS_SIZE_MASK_82576  0x0000007F
+#define E1000_RXPBS_SIZE_MASK_82576	0x0000007F
 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable);
 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf);
 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable);
@@ -484,4 +489,23 @@ void e1000_rlpml_set_vf(struct e1000_hw *, u16);
 s32 e1000_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type type);
 u16 e1000_rxpbs_adjust_82580(u32 data);
 s32 e1000_set_eee_i350(struct e1000_hw *);
+
+/* I2C SDA and SCL timing parameters for standard mode */
+#define E1000_I2C_T_HD_STA	4
+#define E1000_I2C_T_LOW		5
+#define E1000_I2C_T_HIGH	4
+#define E1000_I2C_T_SU_STA	5
+#define E1000_I2C_T_HD_DATA	5
+#define E1000_I2C_T_SU_DATA	1
+#define E1000_I2C_T_RISE	1
+#define E1000_I2C_T_FALL	1
+#define E1000_I2C_T_SU_STO	4
+#define E1000_I2C_T_BUF		5
+
+s32 e1000_set_i2c_bb(struct e1000_hw *hw);
+s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
+				u8 dev_addr, u8 *data);
+s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
+				 u8 dev_addr, u8 data);
+void e1000_i2c_bus_clear(struct e1000_hw *hw);
 #endif /* _E1000_82575_H_ */
diff --git a/sys/dev/e1000/e1000_api.c b/sys/dev/e1000/e1000_api.c
index b470cdd..fdfc4bb 100644
--- a/sys/dev/e1000/e1000_api.c
+++ b/sys/dev/e1000/e1000_api.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -277,7 +277,6 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
 	case E1000_DEV_ID_ICH10_D_BM_LM:
 	case E1000_DEV_ID_ICH10_D_BM_LF:
 	case E1000_DEV_ID_ICH10_D_BM_V:
-	case E1000_DEV_ID_ICH10_HANKSVILLE:
 		mac->type = e1000_ich10lan;
 		break;
 	case E1000_DEV_ID_PCH_D_HV_DM:
@@ -293,7 +292,6 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
 	case E1000_DEV_ID_82575EB_COPPER:
 	case E1000_DEV_ID_82575EB_FIBER_SERDES:
 	case E1000_DEV_ID_82575GB_QUAD_COPPER:
-	case E1000_DEV_ID_82575GB_QUAD_COPPER_PM:
 		mac->type = e1000_82575;
 		break;
 	case E1000_DEV_ID_82576:
@@ -322,6 +320,7 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
 	case E1000_DEV_ID_I350_FIBER:
 	case E1000_DEV_ID_I350_SERDES:
 	case E1000_DEV_ID_I350_SGMII:
+	case E1000_DEV_ID_I350_DA4:
 		mac->type = e1000_i350;
 		break;
 	case E1000_DEV_ID_82576_VF:
@@ -343,10 +342,10 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
  *  e1000_setup_init_funcs - Initializes function pointers
  *  @hw: pointer to the HW structure
  *  @init_device: TRUE will initialize the rest of the function pointers
- *                 getting the device ready for use.  FALSE will only set
- *                 MAC type and the function pointers for the other init
- *                 functions.  Passing FALSE will not generate any hardware
- *                 reads or writes.
+ *		  getting the device ready for use.  FALSE will only set
+ *		  MAC type and the function pointers for the other init
+ *		  functions.  Passing FALSE will not generate any hardware
+ *		  reads or writes.
  *
  *  This function must be called by a driver in order to use the rest
  *  of the 'shared' code files. Called by drivers only.
@@ -518,11 +517,11 @@ void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
  *  The caller must have a packed mc_addr_list of multicast addresses.
  **/
 void e1000_update_mc_addr_list(struct e1000_hw *hw, u8 *mc_addr_list,
-                               u32 mc_addr_count)
+			       u32 mc_addr_count)
 {
 	if (hw->mac.ops.update_mc_addr_list)
 		hw->mac.ops.update_mc_addr_list(hw, mc_addr_list,
-		                                mc_addr_count);
+						mc_addr_count);
 }
 
 /**
@@ -856,12 +855,12 @@ bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
  *  It also does alignment considerations to do the writes in most efficient
  *  way.  Also fills up the sum of the buffer in *buffer parameter.
  **/
-s32 e1000_mng_host_if_write(struct e1000_hw * hw, u8 *buffer, u16 length,
-                            u16 offset, u8 *sum)
+s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length,
+			    u16 offset, u8 *sum)
 {
 	if (hw->mac.ops.mng_host_if_write)
 		return hw->mac.ops.mng_host_if_write(hw, buffer, length,
-		                                     offset, sum);
+						     offset, sum);
 
 	return E1000_NOT_IMPLEMENTED;
 }
@@ -874,7 +873,7 @@ s32 e1000_mng_host_if_write(struct e1000_hw * hw, u8 *buffer, u16 length,
  *  Writes the command header after does the checksum calculation.
  **/
 s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
-                               struct e1000_host_mng_command_header *hdr)
+			       struct e1000_host_mng_command_header *hdr)
 {
 	if (hw->mac.ops.mng_write_cmd_header)
 		return hw->mac.ops.mng_write_cmd_header(hw, hdr);
@@ -892,7 +891,7 @@ s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
  *  and also checks whether the previous command is completed.  It busy waits
  *  in case of previous command is not completed.
  **/
-s32 e1000_mng_enable_host_if(struct e1000_hw * hw)
+s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
 {
 	if (hw->mac.ops.mng_enable_host_if)
 		return hw->mac.ops.mng_enable_host_if(hw);
@@ -1277,7 +1276,7 @@ s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
  *  This is a function pointer entry point called by drivers.
  **/
 s32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, u32 offset,
-                              u8 data)
+			      u8 data)
 {
 	return e1000_write_8bit_ctrl_reg_generic(hw, reg, offset, data);
 }
diff --git a/sys/dev/e1000/e1000_api.h b/sys/dev/e1000/e1000_api.h
index 2621a6e..70aaa15 100644
--- a/sys/dev/e1000/e1000_api.h
+++ b/sys/dev/e1000/e1000_api.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -37,90 +37,87 @@
 
 #include "e1000_hw.h"
 
-extern void    e1000_init_function_pointers_82542(struct e1000_hw *hw);
-extern void    e1000_init_function_pointers_82543(struct e1000_hw *hw);
-extern void    e1000_init_function_pointers_82540(struct e1000_hw *hw);
-extern void    e1000_init_function_pointers_82571(struct e1000_hw *hw);
-extern void    e1000_init_function_pointers_82541(struct e1000_hw *hw);
-extern void    e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw);
-extern void    e1000_init_function_pointers_ich8lan(struct e1000_hw *hw);
-extern void    e1000_init_function_pointers_82575(struct e1000_hw *hw);
-extern void    e1000_rx_fifo_flush_82575(struct e1000_hw *hw);
-extern void    e1000_init_function_pointers_vf(struct e1000_hw *hw);
-extern void    e1000_power_up_fiber_serdes_link(struct e1000_hw *hw);
-extern void    e1000_shutdown_fiber_serdes_link(struct e1000_hw *hw);
+extern void e1000_init_function_pointers_82542(struct e1000_hw *hw);
+extern void e1000_init_function_pointers_82543(struct e1000_hw *hw);
+extern void e1000_init_function_pointers_82540(struct e1000_hw *hw);
+extern void e1000_init_function_pointers_82571(struct e1000_hw *hw);
+extern void e1000_init_function_pointers_82541(struct e1000_hw *hw);
+extern void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw);
+extern void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw);
+extern void e1000_init_function_pointers_82575(struct e1000_hw *hw);
+extern void e1000_rx_fifo_flush_82575(struct e1000_hw *hw);
+extern void e1000_init_function_pointers_vf(struct e1000_hw *hw);
+extern void e1000_power_up_fiber_serdes_link(struct e1000_hw *hw);
+extern void e1000_shutdown_fiber_serdes_link(struct e1000_hw *hw);
 
-s32  e1000_set_mac_type(struct e1000_hw *hw);
-s32  e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device);
-s32  e1000_init_mac_params(struct e1000_hw *hw);
-s32  e1000_init_nvm_params(struct e1000_hw *hw);
-s32  e1000_init_phy_params(struct e1000_hw *hw);
-s32  e1000_init_mbx_params(struct e1000_hw *hw);
-s32  e1000_get_bus_info(struct e1000_hw *hw);
+s32 e1000_set_mac_type(struct e1000_hw *hw);
+s32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device);
+s32 e1000_init_mac_params(struct e1000_hw *hw);
+s32 e1000_init_nvm_params(struct e1000_hw *hw);
+s32 e1000_init_phy_params(struct e1000_hw *hw);
+s32 e1000_init_mbx_params(struct e1000_hw *hw);
+s32 e1000_get_bus_info(struct e1000_hw *hw);
 void e1000_clear_vfta(struct e1000_hw *hw);
 void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value);
-s32  e1000_force_mac_fc(struct e1000_hw *hw);
-s32  e1000_check_for_link(struct e1000_hw *hw);
-s32  e1000_reset_hw(struct e1000_hw *hw);
-s32  e1000_init_hw(struct e1000_hw *hw);
-s32  e1000_setup_link(struct e1000_hw *hw);
-s32  e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed,
-                                u16 *duplex);
-s32  e1000_disable_pcie_master(struct e1000_hw *hw);
+s32 e1000_force_mac_fc(struct e1000_hw *hw);
+s32 e1000_check_for_link(struct e1000_hw *hw);
+s32 e1000_reset_hw(struct e1000_hw *hw);
+s32 e1000_init_hw(struct e1000_hw *hw);
+s32 e1000_setup_link(struct e1000_hw *hw);
+s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex);
+s32 e1000_disable_pcie_master(struct e1000_hw *hw);
 void e1000_config_collision_dist(struct e1000_hw *hw);
 void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
-u32  e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr);
-void e1000_update_mc_addr_list(struct e1000_hw *hw,
-                               u8 *mc_addr_list, u32 mc_addr_count);
-s32  e1000_setup_led(struct e1000_hw *hw);
-s32  e1000_cleanup_led(struct e1000_hw *hw);
-s32  e1000_check_reset_block(struct e1000_hw *hw);
-s32  e1000_blink_led(struct e1000_hw *hw);
-s32  e1000_led_on(struct e1000_hw *hw);
-s32  e1000_led_off(struct e1000_hw *hw);
+u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr);
+void e1000_update_mc_addr_list(struct e1000_hw *hw, u8 *mc_addr_list,
+			       u32 mc_addr_count);
+s32 e1000_setup_led(struct e1000_hw *hw);
+s32 e1000_cleanup_led(struct e1000_hw *hw);
+s32 e1000_check_reset_block(struct e1000_hw *hw);
+s32 e1000_blink_led(struct e1000_hw *hw);
+s32 e1000_led_on(struct e1000_hw *hw);
+s32 e1000_led_off(struct e1000_hw *hw);
 s32 e1000_id_led_init(struct e1000_hw *hw);
 void e1000_reset_adaptive(struct e1000_hw *hw);
 void e1000_update_adaptive(struct e1000_hw *hw);
-s32  e1000_get_cable_length(struct e1000_hw *hw);
-s32  e1000_validate_mdi_setting(struct e1000_hw *hw);
-s32  e1000_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data);
-s32  e1000_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data);
-s32  e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg,
-                               u32 offset, u8 data);
-s32  e1000_get_phy_info(struct e1000_hw *hw);
+s32 e1000_get_cable_length(struct e1000_hw *hw);
+s32 e1000_validate_mdi_setting(struct e1000_hw *hw);
+s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data);
+s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data);
+s32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, u32 offset,
+			      u8 data);
+s32 e1000_get_phy_info(struct e1000_hw *hw);
 void e1000_release_phy(struct e1000_hw *hw);
-s32  e1000_acquire_phy(struct e1000_hw *hw);
-s32  e1000_cfg_on_link_up(struct e1000_hw *hw);
-s32  e1000_phy_hw_reset(struct e1000_hw *hw);
-s32  e1000_phy_commit(struct e1000_hw *hw);
+s32 e1000_acquire_phy(struct e1000_hw *hw);
+s32 e1000_cfg_on_link_up(struct e1000_hw *hw);
+s32 e1000_phy_hw_reset(struct e1000_hw *hw);
+s32 e1000_phy_commit(struct e1000_hw *hw);
 void e1000_power_up_phy(struct e1000_hw *hw);
 void e1000_power_down_phy(struct e1000_hw *hw);
-s32  e1000_read_mac_addr(struct e1000_hw *hw);
-s32  e1000_read_pba_string(struct e1000_hw *hw, u8 *pba_num, 
-                           u32 pba_num_size);
-s32  e1000_read_pba_length(struct e1000_hw *hw, u32 *pba_num_size);
+s32 e1000_read_mac_addr(struct e1000_hw *hw);
+s32 e1000_read_pba_string(struct e1000_hw *hw, u8 *pba_num, u32 pba_num_size);
+s32 e1000_read_pba_length(struct e1000_hw *hw, u32 *pba_num_size);
 void e1000_reload_nvm(struct e1000_hw *hw);
-s32  e1000_update_nvm_checksum(struct e1000_hw *hw);
-s32  e1000_validate_nvm_checksum(struct e1000_hw *hw);
-s32  e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
-s32  e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
-s32  e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
-s32  e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words,
-                     u16 *data);
-s32  e1000_wait_autoneg(struct e1000_hw *hw);
-s32  e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
-s32  e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
+s32 e1000_update_nvm_checksum(struct e1000_hw *hw);
+s32 e1000_validate_nvm_checksum(struct e1000_hw *hw);
+s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
+s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
+s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
+s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
+s32 e1000_wait_autoneg(struct e1000_hw *hw);
+s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
+s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
 bool e1000_check_mng_mode(struct e1000_hw *hw);
 bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw);
-s32  e1000_mng_enable_host_if(struct e1000_hw *hw);
-s32  e1000_mng_host_if_write(struct e1000_hw *hw,
-                             u8 *buffer, u16 length, u16 offset, u8 *sum);
-s32  e1000_mng_write_cmd_header(struct e1000_hw *hw,
-                                struct e1000_host_mng_command_header *hdr);
-s32  e1000_mng_write_dhcp_info(struct e1000_hw * hw,
-                                    u8 *buffer, u16 length);
+s32 e1000_mng_enable_host_if(struct e1000_hw *hw);
+s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length,
+			    u16 offset, u8 *sum);
+s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
+			       struct e1000_host_mng_command_header *hdr);
+s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
 u32  e1000_translate_register_82542(u32 reg);
 
+
 /*
  * TBI_ACCEPT macro definition:
  *
@@ -152,14 +149,15 @@ u32  e1000_translate_register_82542(u32 reg);
 /* The carrier extension symbol, as received by the NIC. */
 #define CARRIER_EXTENSION   0x0F
 
-#define TBI_ACCEPT(a, status, errors, length, last_byte, min_frame_size, max_frame_size) \
-    (e1000_tbi_sbp_enabled_82543(a) && \
-     (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
-     ((last_byte) == CARRIER_EXTENSION) && \
-     (((status) & E1000_RXD_STAT_VP) ? \
-          (((length) > (min_frame_size - VLAN_TAG_SIZE)) && \
-           ((length) <= (max_frame_size + 1))) : \
-          (((length) > min_frame_size) && \
-           ((length) <= (max_frame_size + VLAN_TAG_SIZE + 1)))))
+#define TBI_ACCEPT(a, status, errors, length, last_byte, \
+		   min_frame_size, max_frame_size) \
+	(e1000_tbi_sbp_enabled_82543(a) && \
+	 (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
+	 ((last_byte) == CARRIER_EXTENSION) && \
+	 (((status) & E1000_RXD_STAT_VP) ? \
+	  (((length) > (min_frame_size - VLAN_TAG_SIZE)) && \
+	  ((length) <= (max_frame_size + 1))) : \
+	  (((length) > min_frame_size) && \
+	  ((length) <= (max_frame_size + VLAN_TAG_SIZE + 1)))))
 
 #endif
diff --git a/sys/dev/e1000/e1000_defines.h b/sys/dev/e1000/e1000_defines.h
index fd6a128..69ef386 100644
--- a/sys/dev/e1000/e1000_defines.h
+++ b/sys/dev/e1000/e1000_defines.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -41,815 +41,826 @@
 
 /* Definitions for power management and wakeup registers */
 /* Wake Up Control */
-#define E1000_WUC_APME       0x00000001 /* APM Enable */
-#define E1000_WUC_PME_EN     0x00000002 /* PME Enable */
-#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
-#define E1000_WUC_APMPME     0x00000008 /* Assert PME on APM Wakeup */
-#define E1000_WUC_LSCWE      0x00000010 /* Link Status wake up enable */
-#define E1000_WUC_PPROXYE    0x00000010 /* Protocol Proxy Enable */
-#define E1000_WUC_LSCWO      0x00000020 /* Link Status wake up override */
-#define E1000_WUC_SPM        0x80000000 /* Enable SPM */
-#define E1000_WUC_PHY_WAKE   0x00000100 /* if PHY supports wakeup */
-#define E1000_WUC_FLX6_PHY  0x4000 /* Flexible Filter 6 Enable */
-#define E1000_WUC_FLX7_PHY  0x8000 /* Flexible Filter 7 Enable */
+#define E1000_WUC_APME		0x00000001 /* APM Enable */
+#define E1000_WUC_PME_EN	0x00000002 /* PME Enable */
+#define E1000_WUC_PME_STATUS	0x00000004 /* PME Status */
+#define E1000_WUC_APMPME	0x00000008 /* Assert PME on APM Wakeup */
+#define E1000_WUC_LSCWE		0x00000010 /* Link Status wake up enable */
+#define E1000_WUC_PPROXYE	0x00000010 /* Protocol Proxy Enable */
+#define E1000_WUC_LSCWO		0x00000020 /* Link Status wake up override */
+#define E1000_WUC_SPM		0x80000000 /* Enable SPM */
+#define E1000_WUC_PHY_WAKE	0x00000100 /* if PHY supports wakeup */
+#define E1000_WUC_FLX6_PHY	0x4000 /* Flexible Filter 6 Enable */
+#define E1000_WUC_FLX7_PHY	0x8000 /* Flexible Filter 7 Enable */
 
 /* Wake Up Filter Control */
-#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
-#define E1000_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
-#define E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
-#define E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
-#define E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
-#define E1000_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
-#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
-#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
+#define E1000_WUFC_LNKC	0x00000001 /* Link Status Change Wakeup Enable */
+#define E1000_WUFC_MAG	0x00000002 /* Magic Packet Wakeup Enable */
+#define E1000_WUFC_EX	0x00000004 /* Directed Exact Wakeup Enable */
+#define E1000_WUFC_MC	0x00000008 /* Directed Multicast Wakeup Enable */
+#define E1000_WUFC_BC	0x00000010 /* Broadcast Wakeup Enable */
+#define E1000_WUFC_ARP	0x00000020 /* ARP Request Packet Wakeup Enable */
+#define E1000_WUFC_IPV4	0x00000040 /* Directed IPv4 Packet Wakeup Enable */
+#define E1000_WUFC_IPV6	0x00000080 /* Directed IPv6 Packet Wakeup Enable */
 #define E1000_WUFC_IGNORE_TCO_PHY 0x00000800 /* Ignore WakeOn TCO packets */
-#define E1000_WUFC_FLX0_PHY      0x00001000 /* Flexible Filter 0 Enable */
-#define E1000_WUFC_FLX1_PHY      0x00002000 /* Flexible Filter 1 Enable */
-#define E1000_WUFC_FLX2_PHY      0x00004000 /* Flexible Filter 2 Enable */
-#define E1000_WUFC_FLX3_PHY      0x00008000 /* Flexible Filter 3 Enable */
-#define E1000_WUFC_FLX4_PHY      0x00000200 /* Flexible Filter 4 Enable */
-#define E1000_WUFC_FLX5_PHY      0x00000400 /* Flexible Filter 5 Enable */
-#define E1000_WUFC_IGNORE_TCO   0x00008000 /* Ignore WakeOn TCO packets */
-#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
-#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
-#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
-#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
-#define E1000_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
-#define E1000_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
-#define E1000_WUFC_FLX6 0x00400000 /* Flexible Filter 6 Enable */
-#define E1000_WUFC_FLX7 0x00800000 /* Flexible Filter 7 Enable */
-#define E1000_WUFC_FW_RST 0x80000000 /* Wake on FW Reset Enable */
-#define E1000_WUFC_ALL_FILTERS_PHY_4 0x0000F0FF /*Mask for all wakeup filters*/
-#define E1000_WUFC_FLX_OFFSET_PHY 12 /* Offset to the Flexible Filters bits */
-#define E1000_WUFC_FLX_FILTERS_PHY_4 0x0000F000 /*Mask for 4 flexible filters*/
-#define E1000_WUFC_ALL_FILTERS_PHY_6 0x0000F6FF /*Mask for 6 wakeup filters */
-#define E1000_WUFC_FLX_FILTERS_PHY_6 0x0000F600 /*Mask for 6 flexible filters*/
-#define E1000_WUFC_ALL_FILTERS  0x000F00FF /* Mask for all wakeup filters */
-#define E1000_WUFC_ALL_FILTERS_6  0x003F00FF /* Mask for all 6 wakeup filters*/
-#define E1000_WUFC_ALL_FILTERS_8  0x00FF00FF /* Mask for all 8 wakeup filters*/
-#define E1000_WUFC_FLX_OFFSET   16 /* Offset to the Flexible Filters bits */
-#define E1000_WUFC_FLX_FILTERS  0x000F0000 /*Mask for the 4 flexible filters */
-#define E1000_WUFC_FLX_FILTERS_6  0x003F0000 /* Mask for 6 flexible filters */
-#define E1000_WUFC_FLX_FILTERS_8  0x00FF0000 /* Mask for 8 flexible filters */
+#define E1000_WUFC_FLX0_PHY	0x00001000 /* Flexible Filter 0 Enable */
+#define E1000_WUFC_FLX1_PHY	0x00002000 /* Flexible Filter 1 Enable */
+#define E1000_WUFC_FLX2_PHY	0x00004000 /* Flexible Filter 2 Enable */
+#define E1000_WUFC_FLX3_PHY	0x00008000 /* Flexible Filter 3 Enable */
+#define E1000_WUFC_FLX4_PHY	0x00000200 /* Flexible Filter 4 Enable */
+#define E1000_WUFC_FLX5_PHY	0x00000400 /* Flexible Filter 5 Enable */
+#define E1000_WUFC_IGNORE_TCO	0x00008000 /* Ignore WakeOn TCO packets */
+#define E1000_WUFC_FLX0		0x00010000 /* Flexible Filter 0 Enable */
+#define E1000_WUFC_FLX1		0x00020000 /* Flexible Filter 1 Enable */
+#define E1000_WUFC_FLX2		0x00040000 /* Flexible Filter 2 Enable */
+#define E1000_WUFC_FLX3		0x00080000 /* Flexible Filter 3 Enable */
+#define E1000_WUFC_FLX4		0x00100000 /* Flexible Filter 4 Enable */
+#define E1000_WUFC_FLX5		0x00200000 /* Flexible Filter 5 Enable */
+#define E1000_WUFC_FLX6		0x00400000 /* Flexible Filter 6 Enable */
+#define E1000_WUFC_FLX7		0x00800000 /* Flexible Filter 7 Enable */
+#define E1000_WUFC_FW_RST	0x80000000 /* Wake on FW Reset Enable */
+#define E1000_WUFC_ALL_FILTERS_PHY_4	0x0000F0FF /* wakeup filters mask */
+#define E1000_WUFC_FLX_OFFSET_PHY	12 /* Flexible Filters bits offset */
+#define E1000_WUFC_FLX_FILTERS_PHY_4	0x0000F000 /* 4 flexible filters mask */
+#define E1000_WUFC_ALL_FILTERS_PHY_6	0x0000F6FF /* 6 wakeup filters mask */
+#define E1000_WUFC_FLX_FILTERS_PHY_6	0x0000F600 /* 6 flexible filters mask */
+#define E1000_WUFC_ALL_FILTERS		0x000F00FF /* all wakeup filters mask */
+#define E1000_WUFC_ALL_FILTERS_6	0x003F00FF /* Mask all 6 wu filters */
+#define E1000_WUFC_ALL_FILTERS_8	0x00FF00FF /* Mask all 8 wu filters */
+#define E1000_WUFC_FLX_OFFSET		16 /* Flexible Filters bits offset */
+#define E1000_WUFC_FLX_FILTERS		0x000F0000 /* 4 flexible filters mask */
+#define E1000_WUFC_FLX_FILTERS_6	0x003F0000 /* 6 flexible filters mask */
+#define E1000_WUFC_FLX_FILTERS_8	0x00FF0000 /* 8 flexible filters mask */
 /*
  * For 82576 to utilize Extended filter masks in addition to
  * existing (filter) masks
  */
-#define E1000_WUFC_EXT_FLX_FILTERS      0x00300000 /* Ext. FLX filter mask */
+#define E1000_WUFC_EXT_FLX_FILTERS	0x00300000 /* Ext. FLX filter mask */
 
 /* Wake Up Status */
-#define E1000_WUS_LNKC         E1000_WUFC_LNKC
-#define E1000_WUS_MAG          E1000_WUFC_MAG
-#define E1000_WUS_EX           E1000_WUFC_EX
-#define E1000_WUS_MC           E1000_WUFC_MC
-#define E1000_WUS_BC           E1000_WUFC_BC
-#define E1000_WUS_ARP          E1000_WUFC_ARP
-#define E1000_WUS_IPV4         E1000_WUFC_IPV4
-#define E1000_WUS_IPV6         E1000_WUFC_IPV6
-#define E1000_WUS_FLX0_PHY      E1000_WUFC_FLX0_PHY
-#define E1000_WUS_FLX1_PHY      E1000_WUFC_FLX1_PHY
-#define E1000_WUS_FLX2_PHY      E1000_WUFC_FLX2_PHY
-#define E1000_WUS_FLX3_PHY      E1000_WUFC_FLX3_PHY
-#define E1000_WUS_FLX_FILTERS_PHY_4        E1000_WUFC_FLX_FILTERS_PHY_4
-#define E1000_WUS_FLX0         E1000_WUFC_FLX0
-#define E1000_WUS_FLX1         E1000_WUFC_FLX1
-#define E1000_WUS_FLX2         E1000_WUFC_FLX2
-#define E1000_WUS_FLX3         E1000_WUFC_FLX3
-#define E1000_WUS_FLX4         E1000_WUFC_FLX4
-#define E1000_WUS_FLX5         E1000_WUFC_FLX5
-#define E1000_WUS_FLX6         E1000_WUFC_FLX6
-#define E1000_WUS_FLX7         E1000_WUFC_FLX7
-#define E1000_WUS_FLX4_PHY         E1000_WUFC_FLX4_PHY
-#define E1000_WUS_FLX5_PHY         E1000_WUFC_FLX5_PHY
-#define E1000_WUS_FLX6_PHY         0x0400
-#define E1000_WUS_FLX7_PHY         0x0800
-#define E1000_WUS_FLX_FILTERS  E1000_WUFC_FLX_FILTERS
-#define E1000_WUS_FLX_FILTERS_6  E1000_WUFC_FLX_FILTERS_6
-#define E1000_WUS_FLX_FILTERS_8  E1000_WUFC_FLX_FILTERS_8
-#define E1000_WUS_FLX_FILTERS_PHY_6  E1000_WUFC_FLX_FILTERS_PHY_6
+#define E1000_WUS_LNKC		E1000_WUFC_LNKC
+#define E1000_WUS_MAG		E1000_WUFC_MAG
+#define E1000_WUS_EX		E1000_WUFC_EX
+#define E1000_WUS_MC		E1000_WUFC_MC
+#define E1000_WUS_BC		E1000_WUFC_BC
+#define E1000_WUS_ARP		E1000_WUFC_ARP
+#define E1000_WUS_IPV4		E1000_WUFC_IPV4
+#define E1000_WUS_IPV6		E1000_WUFC_IPV6
+#define E1000_WUS_FLX0_PHY	E1000_WUFC_FLX0_PHY
+#define E1000_WUS_FLX1_PHY	E1000_WUFC_FLX1_PHY
+#define E1000_WUS_FLX2_PHY	E1000_WUFC_FLX2_PHY
+#define E1000_WUS_FLX3_PHY	E1000_WUFC_FLX3_PHY
+#define E1000_WUS_FLX_FILTERS_PHY_4	E1000_WUFC_FLX_FILTERS_PHY_4
+#define E1000_WUS_FLX0		E1000_WUFC_FLX0
+#define E1000_WUS_FLX1		E1000_WUFC_FLX1
+#define E1000_WUS_FLX2		E1000_WUFC_FLX2
+#define E1000_WUS_FLX3		E1000_WUFC_FLX3
+#define E1000_WUS_FLX4		E1000_WUFC_FLX4
+#define E1000_WUS_FLX5		E1000_WUFC_FLX5
+#define E1000_WUS_FLX6		E1000_WUFC_FLX6
+#define E1000_WUS_FLX7		E1000_WUFC_FLX7
+#define E1000_WUS_FLX4_PHY	E1000_WUFC_FLX4_PHY
+#define E1000_WUS_FLX5_PHY	E1000_WUFC_FLX5_PHY
+#define E1000_WUS_FLX6_PHY	0x0400
+#define E1000_WUS_FLX7_PHY	0x0800
+#define E1000_WUS_FLX_FILTERS	E1000_WUFC_FLX_FILTERS
+#define E1000_WUS_FLX_FILTERS_6		E1000_WUFC_FLX_FILTERS_6
+#define E1000_WUS_FLX_FILTERS_8		E1000_WUFC_FLX_FILTERS_8
+#define E1000_WUS_FLX_FILTERS_PHY_6	E1000_WUFC_FLX_FILTERS_PHY_6
 
 /* Wake Up Packet Length */
-#define E1000_WUPL_LENGTH_MASK 0x0FFF   /* Only the lower 12 bits are valid */
+#define E1000_WUPL_LENGTH_MASK	0x0FFF   /* Only the lower 12 bits are valid */
 
 /* Four Flexible Filters are supported */
-#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
+#define E1000_FLEXIBLE_FILTER_COUNT_MAX		4
 /* Six Flexible Filters are supported */
-#define E1000_FLEXIBLE_FILTER_COUNT_MAX_6   6
+#define E1000_FLEXIBLE_FILTER_COUNT_MAX_6	6
 /* Eight Flexible Filters are supported */
-#define E1000_FLEXIBLE_FILTER_COUNT_MAX_8   8
+#define E1000_FLEXIBLE_FILTER_COUNT_MAX_8	8
 /* Two Extended Flexible Filters are supported (82576) */
-#define E1000_EXT_FLEXIBLE_FILTER_COUNT_MAX     2
-#define E1000_FHFT_LENGTH_OFFSET        0xFC /* Length byte in FHFT */
-#define E1000_FHFT_LENGTH_MASK          0x0FF /* Length in lower byte */
+#define E1000_EXT_FLEXIBLE_FILTER_COUNT_MAX	2
+#define E1000_FHFT_LENGTH_OFFSET	0xFC /* Length byte in FHFT */
+#define E1000_FHFT_LENGTH_MASK		0x0FF /* Length in lower byte */
 
 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
-#define E1000_FLEXIBLE_FILTER_SIZE_MAX  128
+#define E1000_FLEXIBLE_FILTER_SIZE_MAX	128
 
-#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
-#define E1000_FFLT_SIZE_6 E1000_FLEXIBLE_FILTER_COUNT_MAX_6
-#define E1000_FFLT_SIZE_8 E1000_FLEXIBLE_FILTER_COUNT_MAX_8
-#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
-#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
+#define E1000_FFLT_SIZE		E1000_FLEXIBLE_FILTER_COUNT_MAX
+#define E1000_FFLT_SIZE_6	E1000_FLEXIBLE_FILTER_COUNT_MAX_6
+#define E1000_FFLT_SIZE_8	E1000_FLEXIBLE_FILTER_COUNT_MAX_8
+#define E1000_FFMT_SIZE		E1000_FLEXIBLE_FILTER_SIZE_MAX
+#define E1000_FFVT_SIZE		E1000_FLEXIBLE_FILTER_SIZE_MAX
 
 /* Extended Device Control */
-#define E1000_CTRL_EXT_GPI0_EN   0x00000001 /* Maps SDP4 to GPI0 */
-#define E1000_CTRL_EXT_GPI1_EN   0x00000002 /* Maps SDP5 to GPI1 */
-#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
-#define E1000_CTRL_EXT_GPI2_EN   0x00000004 /* Maps SDP6 to GPI2 */
-#define E1000_CTRL_EXT_GPI3_EN   0x00000008 /* Maps SDP7 to GPI3 */
+#define E1000_CTRL_EXT_GPI0_EN		0x00000001 /* Maps SDP4 to GPI0 */
+#define E1000_CTRL_EXT_GPI1_EN		0x00000002 /* Maps SDP5 to GPI1 */
+#define E1000_CTRL_EXT_PHYINT_EN	E1000_CTRL_EXT_GPI1_EN
+#define E1000_CTRL_EXT_GPI2_EN		0x00000004 /* Maps SDP6 to GPI2 */
+#define E1000_CTRL_EXT_GPI3_EN		0x00000008 /* Maps SDP7 to GPI3 */
 /* Reserved (bits 4,5) in >= 82575 */
-#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Definable Pin 4 */
-#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Definable Pin 5 */
-#define E1000_CTRL_EXT_PHY_INT   E1000_CTRL_EXT_SDP5_DATA
-#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Definable Pin 6 */
-#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */
+#define E1000_CTRL_EXT_SDP4_DATA	0x00000010 /* SW Definable Pin 4 data */
+#define E1000_CTRL_EXT_SDP5_DATA	0x00000020 /* SW Definable Pin 5 data */
+#define E1000_CTRL_EXT_PHY_INT		E1000_CTRL_EXT_SDP5_DATA
+#define E1000_CTRL_EXT_SDP6_DATA	0x00000040 /* SW Definable Pin 6 data */
+#define E1000_CTRL_EXT_SDP3_DATA	0x00000080 /* SW Definable Pin 3 data */
 /* SDP 4/5 (bits 8,9) are reserved in >= 82575 */
-#define E1000_CTRL_EXT_SDP4_DIR  0x00000100 /* Direction of SDP4 0=in 1=out */
-#define E1000_CTRL_EXT_SDP5_DIR  0x00000200 /* Direction of SDP5 0=in 1=out */
-#define E1000_CTRL_EXT_SDP6_DIR  0x00000400 /* Direction of SDP6 0=in 1=out */
-#define E1000_CTRL_EXT_SDP3_DIR  0x00000800 /* Direction of SDP3 0=in 1=out */
-#define E1000_CTRL_EXT_ASDCHK    0x00001000 /* Initiate an ASD sequence */
-#define E1000_CTRL_EXT_EE_RST    0x00002000 /* Reinitialize from EEPROM */
-#define E1000_CTRL_EXT_IPS       0x00004000 /* Invert Power State */
+#define E1000_CTRL_EXT_SDP4_DIR	0x00000100 /* Direction of SDP4 0=in 1=out */
+#define E1000_CTRL_EXT_SDP5_DIR	0x00000200 /* Direction of SDP5 0=in 1=out */
+#define E1000_CTRL_EXT_SDP6_DIR	0x00000400 /* Direction of SDP6 0=in 1=out */
+#define E1000_CTRL_EXT_SDP3_DIR	0x00000800 /* Direction of SDP3 0=in 1=out */
+#define E1000_CTRL_EXT_ASDCHK	0x00001000 /* Initiate an ASD sequence */
+#define E1000_CTRL_EXT_EE_RST	0x00002000 /* Reinitialize from EEPROM */
+#define E1000_CTRL_EXT_IPS	0x00004000 /* Invert Power State */
 /* Physical Func Reset Done Indication */
-#define E1000_CTRL_EXT_PFRSTD    0x00004000
-#define E1000_CTRL_EXT_SPD_BYPS  0x00008000 /* Speed Select Bypass */
-#define E1000_CTRL_EXT_RO_DIS    0x00020000 /* Relaxed Ordering disable */
-#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */
-#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
-#define E1000_CTRL_EXT_LINK_MODE_82580_MASK 0x01C00000 /*82580 bit 24:22*/
-#define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX  0x00400000
-#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
-#define E1000_CTRL_EXT_LINK_MODE_TBI  0x00C00000
-#define E1000_CTRL_EXT_LINK_MODE_KMRN    0x00000000
-#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES  0x00C00000
-#define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES  0x00800000
-#define E1000_CTRL_EXT_LINK_MODE_SGMII   0x00800000
-#define E1000_CTRL_EXT_EIAME          0x01000000
-#define E1000_CTRL_EXT_IRCA           0x00000001
-#define E1000_CTRL_EXT_WR_WMARK_MASK  0x03000000
-#define E1000_CTRL_EXT_WR_WMARK_256   0x00000000
-#define E1000_CTRL_EXT_WR_WMARK_320   0x01000000
-#define E1000_CTRL_EXT_WR_WMARK_384   0x02000000
-#define E1000_CTRL_EXT_WR_WMARK_448   0x03000000
-#define E1000_CTRL_EXT_CANC           0x04000000 /* Int delay cancellation */
-#define E1000_CTRL_EXT_DRV_LOAD       0x10000000 /* Driver loaded bit for FW */
+#define E1000_CTRL_EXT_PFRSTD	0x00004000
+#define E1000_CTRL_EXT_SPD_BYPS	0x00008000 /* Speed Select Bypass */
+#define E1000_CTRL_EXT_RO_DIS	0x00020000 /* Relaxed Ordering disable */
+#define E1000_CTRL_EXT_DMA_DYN_CLK_EN	0x00080000 /* DMA Dynamic Clk Gating */
+#define E1000_CTRL_EXT_LINK_MODE_MASK	0x00C00000
+/* Offset of the link mode field in Ctrl Ext register */
+#define E1000_CTRL_EXT_LINK_MODE_OFFSET	22
+#define E1000_CTRL_EXT_LINK_MODE_82580_MASK	0x01C00000 /*82580 bit 24:22*/
+#define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX	0x00400000
+#define E1000_CTRL_EXT_LINK_MODE_GMII	0x00000000
+#define E1000_CTRL_EXT_LINK_MODE_TBI	0x00C00000
+#define E1000_CTRL_EXT_LINK_MODE_KMRN	0x00000000
+#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES	0x00C00000
+#define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES	0x00800000
+#define E1000_CTRL_EXT_LINK_MODE_SGMII	0x00800000
+#define E1000_CTRL_EXT_EIAME		0x01000000
+#define E1000_CTRL_EXT_IRCA		0x00000001
+#define E1000_CTRL_EXT_WR_WMARK_MASK	0x03000000
+#define E1000_CTRL_EXT_WR_WMARK_256	0x00000000
+#define E1000_CTRL_EXT_WR_WMARK_320	0x01000000
+#define E1000_CTRL_EXT_WR_WMARK_384	0x02000000
+#define E1000_CTRL_EXT_WR_WMARK_448	0x03000000
+#define E1000_CTRL_EXT_CANC		0x04000000 /* Int delay cancellation */
+#define E1000_CTRL_EXT_DRV_LOAD		0x10000000 /* Drv loaded bit for FW */
 /* IAME enable bit (27) was removed in >= 82575 */
-#define E1000_CTRL_EXT_IAME          0x08000000 /* Int acknowledge Auto-mask */
-#define E1000_CRTL_EXT_PB_PAREN       0x01000000 /* packet buffer parity error
-                                                  * detection enabled */
-#define E1000_CTRL_EXT_DF_PAREN       0x02000000 /* descriptor FIFO parity
-                                                  * error detection enable */
-#define E1000_CTRL_EXT_GHOST_PAREN    0x40000000
-#define E1000_CTRL_EXT_PBA_CLR        0x80000000 /* PBA Clear */
-#define E1000_CTRL_EXT_LSECCK         0x00001000
-#define E1000_CTRL_EXT_PHYPDEN        0x00100000
-#define E1000_I2CCMD_REG_ADDR_SHIFT   16
-#define E1000_I2CCMD_REG_ADDR         0x00FF0000
-#define E1000_I2CCMD_PHY_ADDR_SHIFT   24
-#define E1000_I2CCMD_PHY_ADDR         0x07000000
-#define E1000_I2CCMD_OPCODE_READ      0x08000000
-#define E1000_I2CCMD_OPCODE_WRITE     0x00000000
-#define E1000_I2CCMD_RESET            0x10000000
-#define E1000_I2CCMD_READY            0x20000000
-#define E1000_I2CCMD_INTERRUPT_ENA    0x40000000
-#define E1000_I2CCMD_ERROR            0x80000000
-#define E1000_MAX_SGMII_PHY_REG_ADDR  255
-#define E1000_I2CCMD_PHY_TIMEOUT      200
-#define E1000_IVAR_VALID        0x80
-#define E1000_GPIE_NSICR        0x00000001
-#define E1000_GPIE_MSIX_MODE    0x00000010
-#define E1000_GPIE_EIAME        0x40000000
-#define E1000_GPIE_PBA          0x80000000
+#define E1000_CTRL_EXT_IAME		0x08000000 /* Int ACK Auto-mask */
+/* packet buffer parity error detection enabled */
+#define E1000_CRTL_EXT_PB_PAREN		0x01000000
+/* descriptor FIFO parity error detection enable */
+#define E1000_CTRL_EXT_DF_PAREN		0x02000000
+#define E1000_CTRL_EXT_GHOST_PAREN	0x40000000
+#define E1000_CTRL_EXT_PBA_CLR		0x80000000 /* PBA Clear */
+#define E1000_CTRL_EXT_LSECCK		0x00001000
+#define E1000_CTRL_EXT_PHYPDEN		0x00100000
+#define E1000_I2CCMD_REG_ADDR_SHIFT	16
+#define E1000_I2CCMD_REG_ADDR		0x00FF0000
+#define E1000_I2CCMD_PHY_ADDR_SHIFT	24
+#define E1000_I2CCMD_PHY_ADDR		0x07000000
+#define E1000_I2CCMD_OPCODE_READ	0x08000000
+#define E1000_I2CCMD_OPCODE_WRITE	0x00000000
+#define E1000_I2CCMD_RESET		0x10000000
+#define E1000_I2CCMD_READY		0x20000000
+#define E1000_I2CCMD_INTERRUPT_ENA	0x40000000
+#define E1000_I2CCMD_ERROR		0x80000000
+#define E1000_I2CCMD_SFP_DATA_ADDR(a)	(0x0000 + (a))
+#define E1000_I2CCMD_SFP_DIAG_ADDR(a)	(0x0100 + (a))
+#define E1000_MAX_SGMII_PHY_REG_ADDR	255
+#define E1000_I2CCMD_PHY_TIMEOUT	200
+#define E1000_IVAR_VALID	0x80
+#define E1000_GPIE_NSICR	0x00000001
+#define E1000_GPIE_MSIX_MODE	0x00000010
+#define E1000_GPIE_EIAME	0x40000000
+#define E1000_GPIE_PBA		0x80000000
 
 /* Receive Descriptor bit definitions */
-#define E1000_RXD_STAT_DD       0x01    /* Descriptor Done */
-#define E1000_RXD_STAT_EOP      0x02    /* End of Packet */
-#define E1000_RXD_STAT_IXSM     0x04    /* Ignore checksum */
-#define E1000_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
-#define E1000_RXD_STAT_UDPCS    0x10    /* UDP xsum calculated */
-#define E1000_RXD_STAT_TCPCS    0x20    /* TCP xsum calculated */
-#define E1000_RXD_STAT_IPCS     0x40    /* IP xsum calculated */
-#define E1000_RXD_STAT_PIF      0x80    /* passed in-exact filter */
-#define E1000_RXD_STAT_CRCV     0x100   /* Speculative CRC Valid */
-#define E1000_RXD_STAT_IPIDV    0x200   /* IP identification valid */
-#define E1000_RXD_STAT_UDPV     0x400   /* Valid UDP checksum */
-#define E1000_RXD_STAT_DYNINT   0x800   /* Pkt caused INT via DYNINT */
-#define E1000_RXD_STAT_ACK      0x8000  /* ACK Packet indication */
-#define E1000_RXD_ERR_CE        0x01    /* CRC Error */
-#define E1000_RXD_ERR_SE        0x02    /* Symbol Error */
-#define E1000_RXD_ERR_SEQ       0x04    /* Sequence Error */
-#define E1000_RXD_ERR_CXE       0x10    /* Carrier Extension Error */
-#define E1000_RXD_ERR_TCPE      0x20    /* TCP/UDP Checksum Error */
-#define E1000_RXD_ERR_IPE       0x40    /* IP Checksum Error */
-#define E1000_RXD_ERR_RXE       0x80    /* Rx Data Error */
-#define E1000_RXD_SPC_VLAN_MASK 0x0FFF  /* VLAN ID is in lower 12 bits */
-#define E1000_RXD_SPC_PRI_MASK  0xE000  /* Priority is in upper 3 bits */
-#define E1000_RXD_SPC_PRI_SHIFT 13
-#define E1000_RXD_SPC_CFI_MASK  0x1000  /* CFI is bit 12 */
-#define E1000_RXD_SPC_CFI_SHIFT 12
-
-#define E1000_RXDEXT_STATERR_LB    0x00040000
-#define E1000_RXDEXT_STATERR_CE    0x01000000
-#define E1000_RXDEXT_STATERR_SE    0x02000000
-#define E1000_RXDEXT_STATERR_SEQ   0x04000000
-#define E1000_RXDEXT_STATERR_CXE   0x10000000
-#define E1000_RXDEXT_STATERR_TCPE  0x20000000
-#define E1000_RXDEXT_STATERR_IPE   0x40000000
-#define E1000_RXDEXT_STATERR_RXE   0x80000000
-
-#define E1000_RXDEXT_LSECH                0x01000000
-#define E1000_RXDEXT_LSECE_MASK           0x60000000
-#define E1000_RXDEXT_LSECE_NO_ERROR       0x00000000
-#define E1000_RXDEXT_LSECE_NO_SA_MATCH    0x20000000
-#define E1000_RXDEXT_LSECE_REPLAY_DETECT  0x40000000
-#define E1000_RXDEXT_LSECE_BAD_SIG        0x60000000
+#define E1000_RXD_STAT_DD	0x01    /* Descriptor Done */
+#define E1000_RXD_STAT_EOP	0x02    /* End of Packet */
+#define E1000_RXD_STAT_IXSM	0x04    /* Ignore checksum */
+#define E1000_RXD_STAT_VP	0x08    /* IEEE VLAN Packet */
+#define E1000_RXD_STAT_UDPCS	0x10    /* UDP xsum calculated */
+#define E1000_RXD_STAT_TCPCS	0x20    /* TCP xsum calculated */
+#define E1000_RXD_STAT_IPCS	0x40    /* IP xsum calculated */
+#define E1000_RXD_STAT_PIF	0x80    /* passed in-exact filter */
+#define E1000_RXD_STAT_CRCV	0x100   /* Speculative CRC Valid */
+#define E1000_RXD_STAT_IPIDV	0x200   /* IP identification valid */
+#define E1000_RXD_STAT_UDPV	0x400   /* Valid UDP checksum */
+#define E1000_RXD_STAT_DYNINT	0x800   /* Pkt caused INT via DYNINT */
+#define E1000_RXD_STAT_ACK	0x8000  /* ACK Packet indication */
+#define E1000_RXD_ERR_CE	0x01    /* CRC Error */
+#define E1000_RXD_ERR_SE	0x02    /* Symbol Error */
+#define E1000_RXD_ERR_SEQ	0x04    /* Sequence Error */
+#define E1000_RXD_ERR_CXE	0x10    /* Carrier Extension Error */
+#define E1000_RXD_ERR_TCPE	0x20    /* TCP/UDP Checksum Error */
+#define E1000_RXD_ERR_IPE	0x40    /* IP Checksum Error */
+#define E1000_RXD_ERR_RXE	0x80    /* Rx Data Error */
+#define E1000_RXD_SPC_VLAN_MASK	0x0FFF  /* VLAN ID is in lower 12 bits */
+#define E1000_RXD_SPC_PRI_MASK	0xE000  /* Priority is in upper 3 bits */
+#define E1000_RXD_SPC_PRI_SHIFT	13
+#define E1000_RXD_SPC_CFI_MASK	0x1000  /* CFI is bit 12 */
+#define E1000_RXD_SPC_CFI_SHIFT	12
+
+#define E1000_RXDEXT_STATERR_LB		0x00040000
+#define E1000_RXDEXT_STATERR_CE		0x01000000
+#define E1000_RXDEXT_STATERR_SE		0x02000000
+#define E1000_RXDEXT_STATERR_SEQ	0x04000000
+#define E1000_RXDEXT_STATERR_CXE	0x10000000
+#define E1000_RXDEXT_STATERR_TCPE	0x20000000
+#define E1000_RXDEXT_STATERR_IPE	0x40000000
+#define E1000_RXDEXT_STATERR_RXE	0x80000000
+
+#define E1000_RXDEXT_LSECH		0x01000000
+#define E1000_RXDEXT_LSECE_MASK		0x60000000
+#define E1000_RXDEXT_LSECE_NO_ERROR	0x00000000
+#define E1000_RXDEXT_LSECE_NO_SA_MATCH	0x20000000
+#define E1000_RXDEXT_LSECE_REPLAY_DETECT 0x40000000
+#define E1000_RXDEXT_LSECE_BAD_SIG	0x60000000
 
 /* mask to determine if packets should be dropped due to frame errors */
 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \
-    E1000_RXD_ERR_CE  |                \
-    E1000_RXD_ERR_SE  |                \
-    E1000_RXD_ERR_SEQ |                \
-    E1000_RXD_ERR_CXE |                \
-    E1000_RXD_ERR_RXE)
+	E1000_RXD_ERR_CE  |		\
+	E1000_RXD_ERR_SE  |		\
+	E1000_RXD_ERR_SEQ |		\
+	E1000_RXD_ERR_CXE |		\
+	E1000_RXD_ERR_RXE)
 
 /* Same mask, but for extended and packet split descriptors */
 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
-    E1000_RXDEXT_STATERR_CE  |            \
-    E1000_RXDEXT_STATERR_SE  |            \
-    E1000_RXDEXT_STATERR_SEQ |            \
-    E1000_RXDEXT_STATERR_CXE |            \
-    E1000_RXDEXT_STATERR_RXE)
-
-#define E1000_MRQC_ENABLE_MASK                 0x00000007
-#define E1000_MRQC_ENABLE_RSS_2Q               0x00000001
-#define E1000_MRQC_ENABLE_RSS_INT              0x00000004
-#define E1000_MRQC_RSS_FIELD_MASK              0xFFFF0000
-#define E1000_MRQC_RSS_FIELD_IPV4_TCP          0x00010000
-#define E1000_MRQC_RSS_FIELD_IPV4              0x00020000
-#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX       0x00040000
-#define E1000_MRQC_RSS_FIELD_IPV6_EX           0x00080000
-#define E1000_MRQC_RSS_FIELD_IPV6              0x00100000
-#define E1000_MRQC_RSS_FIELD_IPV6_TCP          0x00200000
-
-#define E1000_RXDPS_HDRSTAT_HDRSP              0x00008000
-#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK        0x000003FF
+	E1000_RXDEXT_STATERR_CE  |	\
+	E1000_RXDEXT_STATERR_SE  |	\
+	E1000_RXDEXT_STATERR_SEQ |	\
+	E1000_RXDEXT_STATERR_CXE |	\
+	E1000_RXDEXT_STATERR_RXE)
+
+#define E1000_MRQC_ENABLE_MASK			0x00000007
+#define E1000_MRQC_ENABLE_RSS_2Q		0x00000001
+#define E1000_MRQC_ENABLE_RSS_INT		0x00000004
+#define E1000_MRQC_RSS_FIELD_MASK		0xFFFF0000
+#define E1000_MRQC_RSS_FIELD_IPV4_TCP		0x00010000
+#define E1000_MRQC_RSS_FIELD_IPV4		0x00020000
+#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX	0x00040000
+#define E1000_MRQC_RSS_FIELD_IPV6_EX		0x00080000
+#define E1000_MRQC_RSS_FIELD_IPV6		0x00100000
+#define E1000_MRQC_RSS_FIELD_IPV6_TCP		0x00200000
+
+#define E1000_RXDPS_HDRSTAT_HDRSP		0x00008000
+#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK		0x000003FF
 
 /* Management Control */
-#define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
-#define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
-#define E1000_MANC_R_ON_FORCE    0x00000004 /* Reset on Force TCO - RO */
-#define E1000_MANC_RMCP_EN       0x00000100 /* Enable RCMP 026Fh Filtering */
-#define E1000_MANC_0298_EN       0x00000200 /* Enable RCMP 0298h Filtering */
-#define E1000_MANC_IPV4_EN       0x00000400 /* Enable IPv4 */
-#define E1000_MANC_IPV6_EN       0x00000800 /* Enable IPv6 */
-#define E1000_MANC_SNAP_EN       0x00001000 /* Accept LLC/SNAP */
-#define E1000_MANC_ARP_EN        0x00002000 /* Enable ARP Request Filtering */
+#define E1000_MANC_SMBUS_EN	0x00000001 /* SMBus Enabled - RO */
+#define E1000_MANC_ASF_EN	0x00000002 /* ASF Enabled - RO */
+#define E1000_MANC_R_ON_FORCE	0x00000004 /* Reset on Force TCO - RO */
+#define E1000_MANC_RMCP_EN	0x00000100 /* Enable RCMP 026Fh Filtering */
+#define E1000_MANC_0298_EN	0x00000200 /* Enable RCMP 0298h Filtering */
+#define E1000_MANC_IPV4_EN	0x00000400 /* Enable IPv4 */
+#define E1000_MANC_IPV6_EN	0x00000800 /* Enable IPv6 */
+#define E1000_MANC_SNAP_EN	0x00001000 /* Accept LLC/SNAP */
+#define E1000_MANC_ARP_EN	0x00002000 /* Enable ARP Request Filtering */
 /* Enable Neighbor Discovery Filtering */
-#define E1000_MANC_NEIGHBOR_EN   0x00004000
-#define E1000_MANC_ARP_RES_EN    0x00008000 /* Enable ARP response Filtering */
-#define E1000_MANC_TCO_RESET     0x00010000 /* TCO Reset Occurred */
-#define E1000_MANC_RCV_TCO_EN    0x00020000 /* Receive TCO Packets Enabled */
+#define E1000_MANC_NEIGHBOR_EN	0x00004000
+#define E1000_MANC_ARP_RES_EN	0x00008000 /* Enable ARP response Filtering */
+#define E1000_MANC_TCO_RESET	0x00010000 /* TCO Reset Occurred */
+#define E1000_MANC_RCV_TCO_EN	0x00020000 /* Receive TCO Packets Enabled */
 #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
-#define E1000_MANC_RCV_ALL       0x00080000 /* Receive All Enabled */
-#define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */
+#define E1000_MANC_RCV_ALL	0x00080000 /* Receive All Enabled */
+#define E1000_MANC_BLK_PHY_RST_ON_IDE	0x00040000 /* Block phy resets */
 /* Enable MAC address filtering */
-#define E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000
+#define E1000_MANC_EN_MAC_ADDR_FILTER	0x00100000
 /* Enable MNG packets to host memory */
-#define E1000_MANC_EN_MNG2HOST   0x00200000
+#define E1000_MANC_EN_MNG2HOST		0x00200000
 /* Enable IP address filtering */
-#define E1000_MANC_EN_IP_ADDR_FILTER    0x00400000
-#define E1000_MANC_EN_XSUM_FILTER   0x00800000 /* Enable checksum filtering */
-#define E1000_MANC_BR_EN            0x01000000 /* Enable broadcast filtering */
-#define E1000_MANC_SMB_REQ       0x01000000 /* SMBus Request */
-#define E1000_MANC_SMB_GNT       0x02000000 /* SMBus Grant */
-#define E1000_MANC_SMB_CLK_IN    0x04000000 /* SMBus Clock In */
-#define E1000_MANC_SMB_DATA_IN   0x08000000 /* SMBus Data In */
-#define E1000_MANC_SMB_DATA_OUT  0x10000000 /* SMBus Data Out */
-#define E1000_MANC_SMB_CLK_OUT   0x20000000 /* SMBus Clock Out */
-#define E1000_MANC_MPROXYE       0x40000000 /* Mngment Proxy Enable */
-#define E1000_MANC_EN_BMC2OS     0x10000000 /* OS2BMC is enabled or not */
-
-#define E1000_MANC_SMB_DATA_OUT_SHIFT  28 /* SMBus Data Out Shift */
-#define E1000_MANC_SMB_CLK_OUT_SHIFT   29 /* SMBus Clock Out Shift */
-
-#define E1000_MANC2H_PORT_623    0x00000020 /* Port 0x26f */
-#define E1000_MANC2H_PORT_664    0x00000040 /* Port 0x298 */
-#define E1000_MDEF_PORT_623      0x00000800 /* Port 0x26f */
-#define E1000_MDEF_PORT_664      0x00000400 /* Port 0x298 */
+#define E1000_MANC_EN_IP_ADDR_FILTER	0x00400000
+#define E1000_MANC_EN_XSUM_FILTER	0x00800000 /* Ena checksum filtering */
+#define E1000_MANC_BR_EN		0x01000000 /* Ena broadcast filtering */
+#define E1000_MANC_SMB_REQ		0x01000000 /* SMBus Request */
+#define E1000_MANC_SMB_GNT		0x02000000 /* SMBus Grant */
+#define E1000_MANC_SMB_CLK_IN		0x04000000 /* SMBus Clock In */
+#define E1000_MANC_SMB_DATA_IN		0x08000000 /* SMBus Data In */
+#define E1000_MANC_SMB_DATA_OUT		0x10000000 /* SMBus Data Out */
+#define E1000_MANC_SMB_CLK_OUT		0x20000000 /* SMBus Clock Out */
+#define E1000_MANC_MPROXYE		0x40000000 /* Mngment Proxy Enable */
+#define E1000_MANC_EN_BMC2OS		0x10000000 /* OS2BMC is enabld or not */
+
+#define E1000_MANC_SMB_DATA_OUT_SHIFT	28 /* SMBus Data Out Shift */
+#define E1000_MANC_SMB_CLK_OUT_SHIFT	29 /* SMBus Clock Out Shift */
+
+#define E1000_MANC2H_PORT_623		0x00000020 /* Port 0x26f */
+#define E1000_MANC2H_PORT_664		0x00000040 /* Port 0x298 */
+#define E1000_MDEF_PORT_623		0x00000800 /* Port 0x26f */
+#define E1000_MDEF_PORT_664		0x00000400 /* Port 0x298 */
 
 /* Receive Control */
-#define E1000_RCTL_RST            0x00000001    /* Software reset */
-#define E1000_RCTL_EN             0x00000002    /* enable */
-#define E1000_RCTL_SBP            0x00000004    /* store bad packet */
-#define E1000_RCTL_UPE            0x00000008    /* unicast promisc enable */
-#define E1000_RCTL_MPE            0x00000010    /* multicast promisc enable */
-#define E1000_RCTL_LPE            0x00000020    /* long packet enable */
-#define E1000_RCTL_LBM_NO         0x00000000    /* no loopback mode */
-#define E1000_RCTL_LBM_MAC        0x00000040    /* MAC loopback mode */
-#define E1000_RCTL_LBM_SLP        0x00000080    /* serial link loopback mode */
-#define E1000_RCTL_LBM_TCVR       0x000000C0    /* tcvr loopback mode */
-#define E1000_RCTL_DTYP_MASK      0x00000C00    /* Descriptor type mask */
-#define E1000_RCTL_DTYP_PS        0x00000400    /* Packet Split descriptor */
-#define E1000_RCTL_RDMTS_HALF     0x00000000    /* Rx desc min thresh size */
-#define E1000_RCTL_RDMTS_QUAT     0x00000100    /* Rx desc min thresh size */
-#define E1000_RCTL_RDMTS_EIGTH    0x00000200    /* Rx desc min thresh size */
-#define E1000_RCTL_MO_SHIFT       12            /* multicast offset shift */
-#define E1000_RCTL_MO_0           0x00000000    /* multicast offset 11:0 */
-#define E1000_RCTL_MO_1           0x00001000    /* multicast offset 12:1 */
-#define E1000_RCTL_MO_2           0x00002000    /* multicast offset 13:2 */
-#define E1000_RCTL_MO_3           0x00003000    /* multicast offset 15:4 */
-#define E1000_RCTL_MDR            0x00004000    /* multicast desc ring 0 */
-#define E1000_RCTL_BAM            0x00008000    /* broadcast enable */
+#define E1000_RCTL_RST		0x00000001 /* Software reset */
+#define E1000_RCTL_EN		0x00000002 /* enable */
+#define E1000_RCTL_SBP		0x00000004 /* store bad packet */
+#define E1000_RCTL_UPE		0x00000008 /* unicast promisc enable */
+#define E1000_RCTL_MPE		0x00000010 /* multicast promisc enable */
+#define E1000_RCTL_LPE		0x00000020 /* long packet enable */
+#define E1000_RCTL_LBM_NO	0x00000000 /* no loopback mode */
+#define E1000_RCTL_LBM_MAC	0x00000040 /* MAC loopback mode */
+#define E1000_RCTL_LBM_SLP	0x00000080 /* serial link loopback mode */
+#define E1000_RCTL_LBM_TCVR	0x000000C0 /* tcvr loopback mode */
+#define E1000_RCTL_DTYP_MASK	0x00000C00 /* Descriptor type mask */
+#define E1000_RCTL_DTYP_PS	0x00000400 /* Packet Split descriptor */
+#define E1000_RCTL_RDMTS_HALF	0x00000000 /* Rx desc min thresh size */
+#define E1000_RCTL_RDMTS_QUAT	0x00000100 /* Rx desc min thresh size */
+#define E1000_RCTL_RDMTS_EIGTH	0x00000200 /* Rx desc min thresh size */
+#define E1000_RCTL_MO_SHIFT	12 /* multicast offset shift */
+#define E1000_RCTL_MO_0		0x00000000 /* multicast offset 11:0 */
+#define E1000_RCTL_MO_1		0x00001000 /* multicast offset 12:1 */
+#define E1000_RCTL_MO_2		0x00002000 /* multicast offset 13:2 */
+#define E1000_RCTL_MO_3		0x00003000 /* multicast offset 15:4 */
+#define E1000_RCTL_MDR		0x00004000 /* multicast desc ring 0 */
+#define E1000_RCTL_BAM		0x00008000 /* broadcast enable */
 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
-#define E1000_RCTL_SZ_2048        0x00000000    /* Rx buffer size 2048 */
-#define E1000_RCTL_SZ_1024        0x00010000    /* Rx buffer size 1024 */
-#define E1000_RCTL_SZ_512         0x00020000    /* Rx buffer size 512 */
-#define E1000_RCTL_SZ_256         0x00030000    /* Rx buffer size 256 */
+#define E1000_RCTL_SZ_2048	0x00000000 /* Rx buffer size 2048 */
+#define E1000_RCTL_SZ_1024	0x00010000 /* Rx buffer size 1024 */
+#define E1000_RCTL_SZ_512	0x00020000 /* Rx buffer size 512 */
+#define E1000_RCTL_SZ_256	0x00030000 /* Rx buffer size 256 */
 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
-#define E1000_RCTL_SZ_16384       0x00010000    /* Rx buffer size 16384 */
-#define E1000_RCTL_SZ_8192        0x00020000    /* Rx buffer size 8192 */
-#define E1000_RCTL_SZ_4096        0x00030000    /* Rx buffer size 4096 */
-#define E1000_RCTL_VFE            0x00040000    /* vlan filter enable */
-#define E1000_RCTL_CFIEN          0x00080000    /* canonical form enable */
-#define E1000_RCTL_CFI            0x00100000    /* canonical form indicator */
-#define E1000_RCTL_DPF            0x00400000    /* discard pause frames */
-#define E1000_RCTL_PMCF           0x00800000    /* pass MAC control frames */
-#define E1000_RCTL_BSEX           0x02000000    /* Buffer size extension */
-#define E1000_RCTL_SECRC          0x04000000    /* Strip Ethernet CRC */
-#define E1000_RCTL_FLXBUF_MASK    0x78000000    /* Flexible buffer size */
-#define E1000_RCTL_FLXBUF_SHIFT   27            /* Flexible buffer shift */
+#define E1000_RCTL_SZ_16384	0x00010000 /* Rx buffer size 16384 */
+#define E1000_RCTL_SZ_8192	0x00020000 /* Rx buffer size 8192 */
+#define E1000_RCTL_SZ_4096	0x00030000 /* Rx buffer size 4096 */
+#define E1000_RCTL_VFE		0x00040000 /* vlan filter enable */
+#define E1000_RCTL_CFIEN	0x00080000 /* canonical form enable */
+#define E1000_RCTL_CFI		0x00100000 /* canonical form indicator */
+#define E1000_RCTL_DPF		0x00400000 /* discard pause frames */
+#define E1000_RCTL_PMCF		0x00800000 /* pass MAC control frames */
+#define E1000_RCTL_BSEX		0x02000000 /* Buffer size extension */
+#define E1000_RCTL_SECRC	0x04000000 /* Strip Ethernet CRC */
+#define E1000_RCTL_FLXBUF_MASK	0x78000000 /* Flexible buffer size */
+#define E1000_RCTL_FLXBUF_SHIFT	27 /* Flexible buffer shift */
 
 /*
  * Use byte values for the following shift parameters
  * Usage:
  *     psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
- *                  E1000_PSRCTL_BSIZE0_MASK) |
- *                ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
- *                  E1000_PSRCTL_BSIZE1_MASK) |
- *                ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
- *                  E1000_PSRCTL_BSIZE2_MASK) |
- *                ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
- *                  E1000_PSRCTL_BSIZE3_MASK))
+ *		  E1000_PSRCTL_BSIZE0_MASK) |
+ *		((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
+ *		  E1000_PSRCTL_BSIZE1_MASK) |
+ *		((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
+ *		  E1000_PSRCTL_BSIZE2_MASK) |
+ *		((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
+ *		  E1000_PSRCTL_BSIZE3_MASK))
  * where value0 = [128..16256],  default=256
  *       value1 = [1024..64512], default=4096
  *       value2 = [0..64512],    default=4096
  *       value3 = [0..64512],    default=0
  */
 
-#define E1000_PSRCTL_BSIZE0_MASK   0x0000007F
-#define E1000_PSRCTL_BSIZE1_MASK   0x00003F00
-#define E1000_PSRCTL_BSIZE2_MASK   0x003F0000
-#define E1000_PSRCTL_BSIZE3_MASK   0x3F000000
+#define E1000_PSRCTL_BSIZE0_MASK	0x0000007F
+#define E1000_PSRCTL_BSIZE1_MASK	0x00003F00
+#define E1000_PSRCTL_BSIZE2_MASK	0x003F0000
+#define E1000_PSRCTL_BSIZE3_MASK	0x3F000000
 
-#define E1000_PSRCTL_BSIZE0_SHIFT  7            /* Shift _right_ 7 */
-#define E1000_PSRCTL_BSIZE1_SHIFT  2            /* Shift _right_ 2 */
-#define E1000_PSRCTL_BSIZE2_SHIFT  6            /* Shift _left_ 6 */
-#define E1000_PSRCTL_BSIZE3_SHIFT 14            /* Shift _left_ 14 */
+#define E1000_PSRCTL_BSIZE0_SHIFT	7    /* Shift _right_ 7 */
+#define E1000_PSRCTL_BSIZE1_SHIFT	2    /* Shift _right_ 2 */
+#define E1000_PSRCTL_BSIZE2_SHIFT	6    /* Shift _left_ 6 */
+#define E1000_PSRCTL_BSIZE3_SHIFT	14   /* Shift _left_ 14 */
 
 /* SWFW_SYNC Definitions */
-#define E1000_SWFW_EEP_SM   0x01
-#define E1000_SWFW_PHY0_SM  0x02
-#define E1000_SWFW_PHY1_SM  0x04
-#define E1000_SWFW_CSR_SM   0x08
-#define E1000_SWFW_PHY2_SM  0x20
-#define E1000_SWFW_PHY3_SM  0x40
-#define E1000_SWFW_SW_MNG_SM 0x400
+#define E1000_SWFW_EEP_SM	0x01
+#define E1000_SWFW_PHY0_SM	0x02
+#define E1000_SWFW_PHY1_SM	0x04
+#define E1000_SWFW_CSR_SM	0x08
+#define E1000_SWFW_PHY2_SM	0x20
+#define E1000_SWFW_PHY3_SM	0x40
+#define E1000_SWFW_SW_MNG_SM	0x400
 
 /* FACTPS Definitions */
-#define E1000_FACTPS_LFS    0x40000000  /* LAN Function Select */
+#define E1000_FACTPS_LFS	0x40000000  /* LAN Function Select */
 /* Device Control */
-#define E1000_CTRL_FD       0x00000001  /* Full duplex.0=half; 1=full */
-#define E1000_CTRL_BEM      0x00000002  /* Endian Mode.0=little,1=big */
-#define E1000_CTRL_PRIOR    0x00000004  /* Priority on PCI. 0=rx,1=fair */
+#define E1000_CTRL_FD		0x00000001  /* Full duplex.0=half; 1=full */
+#define E1000_CTRL_BEM		0x00000002  /* Endian Mode.0=little,1=big */
+#define E1000_CTRL_PRIOR	0x00000004  /* Priority on PCI. 0=rx,1=fair */
 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */
-#define E1000_CTRL_LRST     0x00000008  /* Link reset. 0=normal,1=reset */
-#define E1000_CTRL_TME      0x00000010  /* Test mode. 0=normal,1=test */
-#define E1000_CTRL_SLE      0x00000020  /* Serial Link on 0=dis,1=en */
-#define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
-#define E1000_CTRL_SLU      0x00000040  /* Set link up (Force Link) */
-#define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
-#define E1000_CTRL_SPD_SEL  0x00000300  /* Speed Select Mask */
-#define E1000_CTRL_SPD_10   0x00000000  /* Force 10Mb */
-#define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */
-#define E1000_CTRL_SPD_1000 0x00000200  /* Force 1Gb */
-#define E1000_CTRL_BEM32    0x00000400  /* Big Endian 32 mode */
-#define E1000_CTRL_FRCSPD   0x00000800  /* Force Speed */
-#define E1000_CTRL_FRCDPX   0x00001000  /* Force Duplex */
-#define E1000_CTRL_D_UD_EN  0x00002000  /* Dock/Undock enable */
-#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock
-                                             * indication in SDP[0] */
-#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through
-                                               * PHYRST_N pin */
-#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external
-                                           * LINK_0 and LINK_1 pins */
-#define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */
-#define E1000_CTRL_LANPHYPC_VALUE    0x00020000 /* SW value of LANPHYPC */
-#define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */
-#define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */
-#define E1000_CTRL_SWDPIN2  0x00100000  /* SWDPIN 2 value */
-#define E1000_CTRL_ADVD3WUC 0x00100000  /* D3 WUC */
-#define E1000_CTRL_SWDPIN3  0x00200000  /* SWDPIN 3 value */
-#define E1000_CTRL_SWDPIO0  0x00400000  /* SWDPIN 0 Input or output */
-#define E1000_CTRL_SWDPIO1  0x00800000  /* SWDPIN 1 input or output */
-#define E1000_CTRL_SWDPIO2  0x01000000  /* SWDPIN 2 input or output */
-#define E1000_CTRL_SWDPIO3  0x02000000  /* SWDPIN 3 input or output */
-#define E1000_CTRL_RST      0x04000000  /* Global reset */
-#define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */
-#define E1000_CTRL_TFCE     0x10000000  /* Transmit flow control enable */
-#define E1000_CTRL_RTE      0x20000000  /* Routing tag enable */
-#define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */
-#define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */
-#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to ME */
-#define E1000_CTRL_I2C_ENA  0x02000000  /* I2C enable */
+#define E1000_CTRL_LRST		0x00000008  /* Link reset. 0=normal,1=reset */
+#define E1000_CTRL_TME		0x00000010  /* Test mode. 0=normal,1=test */
+#define E1000_CTRL_SLE		0x00000020  /* Serial Link on 0=dis,1=en */
+#define E1000_CTRL_ASDE		0x00000020  /* Auto-speed detect enable */
+#define E1000_CTRL_SLU		0x00000040  /* Set link up (Force Link) */
+#define E1000_CTRL_ILOS		0x00000080  /* Invert Loss-Of Signal */
+#define E1000_CTRL_SPD_SEL	0x00000300  /* Speed Select Mask */
+#define E1000_CTRL_SPD_10	0x00000000  /* Force 10Mb */
+#define E1000_CTRL_SPD_100	0x00000100  /* Force 100Mb */
+#define E1000_CTRL_SPD_1000	0x00000200  /* Force 1Gb */
+#define E1000_CTRL_BEM32	0x00000400  /* Big Endian 32 mode */
+#define E1000_CTRL_FRCSPD	0x00000800  /* Force Speed */
+#define E1000_CTRL_FRCDPX	0x00001000  /* Force Duplex */
+#define E1000_CTRL_D_UD_EN	0x00002000  /* Dock/Undock enable */
+/* Defined polarity of Dock/Undock indication in SDP[0] */
+#define E1000_CTRL_D_UD_POLARITY	0x00004000
+/* Reset both PHY ports, through PHYRST_N pin */
+#define E1000_CTRL_FORCE_PHY_RESET	0x00008000
+/* enable link status from external LINK_0 and LINK_1 pins */
+#define E1000_CTRL_EXT_LINK_EN		0x00010000
+#define E1000_CTRL_LANPHYPC_OVERRIDE	0x00010000 /* SW control of LANPHYPC */
+#define E1000_CTRL_LANPHYPC_VALUE	0x00020000 /* SW value of LANPHYPC */
+#define E1000_CTRL_SWDPIN0	0x00040000 /* SWDPIN 0 value */
+#define E1000_CTRL_SWDPIN1	0x00080000 /* SWDPIN 1 value */
+#define E1000_CTRL_SWDPIN2	0x00100000 /* SWDPIN 2 value */
+#define E1000_CTRL_ADVD3WUC	0x00100000 /* D3 WUC */
+#define E1000_CTRL_SWDPIN3	0x00200000 /* SWDPIN 3 value */
+#define E1000_CTRL_SWDPIO0	0x00400000 /* SWDPIN 0 Input or output */
+#define E1000_CTRL_SWDPIO1	0x00800000 /* SWDPIN 1 input or output */
+#define E1000_CTRL_SWDPIO2	0x01000000 /* SWDPIN 2 input or output */
+#define E1000_CTRL_SWDPIO3	0x02000000 /* SWDPIN 3 input or output */
+#define E1000_CTRL_RST		0x04000000 /* Global reset */
+#define E1000_CTRL_RFCE		0x08000000 /* Receive Flow Control enable */
+#define E1000_CTRL_TFCE		0x10000000 /* Transmit flow control enable */
+#define E1000_CTRL_RTE		0x20000000 /* Routing tag enable */
+#define E1000_CTRL_VME		0x40000000 /* IEEE VLAN mode enable */
+#define E1000_CTRL_PHY_RST	0x80000000 /* PHY Reset */
+#define E1000_CTRL_SW2FW_INT	0x02000000 /* Initiate an interrupt to ME */
+#define E1000_CTRL_I2C_ENA	0x02000000 /* I2C enable */
 
 /*
  * Bit definitions for the Management Data IO (MDIO) and Management Data
  * Clock (MDC) pins in the Device Control Register.
  */
-#define E1000_CTRL_PHY_RESET_DIR  E1000_CTRL_SWDPIO0
-#define E1000_CTRL_PHY_RESET      E1000_CTRL_SWDPIN0
-#define E1000_CTRL_MDIO_DIR       E1000_CTRL_SWDPIO2
-#define E1000_CTRL_MDIO           E1000_CTRL_SWDPIN2
-#define E1000_CTRL_MDC_DIR        E1000_CTRL_SWDPIO3
-#define E1000_CTRL_MDC            E1000_CTRL_SWDPIN3
-#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
-#define E1000_CTRL_PHY_RESET4     E1000_CTRL_EXT_SDP4_DATA
-
-#define E1000_CONNSW_ENRGSRC             0x4
-#define E1000_PCS_CFG_PCS_EN             8
-#define E1000_PCS_LCTL_FLV_LINK_UP       1
-#define E1000_PCS_LCTL_FSV_10            0
-#define E1000_PCS_LCTL_FSV_100           2
-#define E1000_PCS_LCTL_FSV_1000          4
-#define E1000_PCS_LCTL_FDV_FULL          8
-#define E1000_PCS_LCTL_FSD               0x10
-#define E1000_PCS_LCTL_FORCE_LINK        0x20
-#define E1000_PCS_LCTL_LOW_LINK_LATCH    0x40
-#define E1000_PCS_LCTL_FORCE_FCTRL       0x80
-#define E1000_PCS_LCTL_AN_ENABLE         0x10000
-#define E1000_PCS_LCTL_AN_RESTART        0x20000
-#define E1000_PCS_LCTL_AN_TIMEOUT        0x40000
-#define E1000_PCS_LCTL_AN_SGMII_BYPASS   0x80000
-#define E1000_PCS_LCTL_AN_SGMII_TRIGGER  0x100000
-#define E1000_PCS_LCTL_FAST_LINK_TIMER   0x1000000
-#define E1000_PCS_LCTL_LINK_OK_FIX       0x2000000
-#define E1000_PCS_LCTL_CRS_ON_NI         0x4000000
-#define E1000_ENABLE_SERDES_LOOPBACK     0x0410
-
-#define E1000_PCS_LSTS_LINK_OK           1
-#define E1000_PCS_LSTS_SPEED_10          0
-#define E1000_PCS_LSTS_SPEED_100         2
-#define E1000_PCS_LSTS_SPEED_1000        4
-#define E1000_PCS_LSTS_DUPLEX_FULL       8
-#define E1000_PCS_LSTS_SYNK_OK           0x10
-#define E1000_PCS_LSTS_AN_COMPLETE       0x10000
-#define E1000_PCS_LSTS_AN_PAGE_RX        0x20000
-#define E1000_PCS_LSTS_AN_TIMED_OUT      0x40000
-#define E1000_PCS_LSTS_AN_REMOTE_FAULT   0x80000
-#define E1000_PCS_LSTS_AN_ERROR_RWS      0x100000
+#define E1000_CTRL_PHY_RESET_DIR	E1000_CTRL_SWDPIO0
+#define E1000_CTRL_PHY_RESET		E1000_CTRL_SWDPIN0
+#define E1000_CTRL_MDIO_DIR		E1000_CTRL_SWDPIO2
+#define E1000_CTRL_MDIO			E1000_CTRL_SWDPIN2
+#define E1000_CTRL_MDC_DIR		E1000_CTRL_SWDPIO3
+#define E1000_CTRL_MDC			E1000_CTRL_SWDPIN3
+#define E1000_CTRL_PHY_RESET_DIR4	E1000_CTRL_EXT_SDP4_DIR
+#define E1000_CTRL_PHY_RESET4		E1000_CTRL_EXT_SDP4_DATA
+
+#define E1000_CONNSW_ENRGSRC		0x4
+#define E1000_PCS_CFG_PCS_EN		8
+#define E1000_PCS_LCTL_FLV_LINK_UP	1
+#define E1000_PCS_LCTL_FSV_10		0
+#define E1000_PCS_LCTL_FSV_100		2
+#define E1000_PCS_LCTL_FSV_1000		4
+#define E1000_PCS_LCTL_FDV_FULL		8
+#define E1000_PCS_LCTL_FSD		0x10
+#define E1000_PCS_LCTL_FORCE_LINK	0x20
+#define E1000_PCS_LCTL_LOW_LINK_LATCH	0x40
+#define E1000_PCS_LCTL_FORCE_FCTRL	0x80
+#define E1000_PCS_LCTL_AN_ENABLE	0x10000
+#define E1000_PCS_LCTL_AN_RESTART	0x20000
+#define E1000_PCS_LCTL_AN_TIMEOUT	0x40000
+#define E1000_PCS_LCTL_AN_SGMII_BYPASS	0x80000
+#define E1000_PCS_LCTL_AN_SGMII_TRIGGER	0x100000
+#define E1000_PCS_LCTL_FAST_LINK_TIMER	0x1000000
+#define E1000_PCS_LCTL_LINK_OK_FIX	0x2000000
+#define E1000_PCS_LCTL_CRS_ON_NI	0x4000000
+#define E1000_ENABLE_SERDES_LOOPBACK	0x0410
+
+#define E1000_PCS_LSTS_LINK_OK		1
+#define E1000_PCS_LSTS_SPEED_10		0
+#define E1000_PCS_LSTS_SPEED_100	2
+#define E1000_PCS_LSTS_SPEED_1000	4
+#define E1000_PCS_LSTS_DUPLEX_FULL	8
+#define E1000_PCS_LSTS_SYNK_OK		0x10
+#define E1000_PCS_LSTS_AN_COMPLETE	0x10000
+#define E1000_PCS_LSTS_AN_PAGE_RX	0x20000
+#define E1000_PCS_LSTS_AN_TIMED_OUT	0x40000
+#define E1000_PCS_LSTS_AN_REMOTE_FAULT	0x80000
+#define E1000_PCS_LSTS_AN_ERROR_RWS	0x100000
 
 /* Device Status */
-#define E1000_STATUS_FD         0x00000001      /* Full duplex.0=half,1=full */
-#define E1000_STATUS_LU         0x00000002      /* Link up.0=no,1=link */
-#define E1000_STATUS_FUNC_MASK  0x0000000C      /* PCI Function Mask */
-#define E1000_STATUS_FUNC_SHIFT 2
-#define E1000_STATUS_FUNC_0     0x00000000      /* Function 0 */
-#define E1000_STATUS_FUNC_1     0x00000004      /* Function 1 */
-#define E1000_STATUS_TXOFF      0x00000010      /* transmission paused */
-#define E1000_STATUS_TBIMODE    0x00000020      /* TBI mode */
-#define E1000_STATUS_SPEED_MASK 0x000000C0
-#define E1000_STATUS_SPEED_10   0x00000000      /* Speed 10Mb/s */
-#define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */
-#define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */
-#define E1000_STATUS_LAN_INIT_DONE 0x00000200  /* Lan Init Completion by NVM */
-#define E1000_STATUS_ASDV       0x00000300      /* Auto speed detect value */
-#define E1000_STATUS_PHYRA      0x00000400      /* PHY Reset Asserted */
-#define E1000_STATUS_DOCK_CI    0x00000800      /* Change in Dock/Undock state.
-                                                 * Clear on write '0'. */
-#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */
-#define E1000_STATUS_MTXCKOK    0x00000400      /* MTX clock running OK */
-#define E1000_STATUS_PCI66      0x00000800      /* In 66Mhz slot */
-#define E1000_STATUS_BUS64      0x00001000      /* In 64 bit slot */
-#define E1000_STATUS_PCIX_MODE  0x00002000      /* PCI-X mode */
-#define E1000_STATUS_PCIX_SPEED 0x0000C000      /* PCI-X bus speed */
-#define E1000_STATUS_BMC_SKU_0  0x00100000 /* BMC USB redirect disabled */
-#define E1000_STATUS_BMC_SKU_1  0x00200000 /* BMC SRAM disabled */
-#define E1000_STATUS_BMC_SKU_2  0x00400000 /* BMC SDRAM disabled */
-#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
-#define E1000_STATUS_BMC_LITE   0x01000000 /* BMC external code execution
-                                            * disabled */
-#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
-#define E1000_STATUS_FUSE_8       0x04000000
-#define E1000_STATUS_FUSE_9       0x08000000
-#define E1000_STATUS_SERDES0_DIS  0x10000000 /* SERDES disabled on port 0 */
-#define E1000_STATUS_SERDES1_DIS  0x20000000 /* SERDES disabled on port 1 */
+#define E1000_STATUS_FD			0x00000001 /* Duplex 0=half 1=full */
+#define E1000_STATUS_LU			0x00000002 /* Link up.0=no,1=link */
+#define E1000_STATUS_FUNC_MASK		0x0000000C /* PCI Function Mask */
+#define E1000_STATUS_FUNC_SHIFT		2
+#define E1000_STATUS_FUNC_0		0x00000000 /* Function 0 */
+#define E1000_STATUS_FUNC_1		0x00000004 /* Function 1 */
+#define E1000_STATUS_TXOFF		0x00000010 /* transmission paused */
+#define E1000_STATUS_TBIMODE		0x00000020 /* TBI mode */
+#define E1000_STATUS_SPEED_MASK		0x000000C0
+#define E1000_STATUS_SPEED_10		0x00000000 /* Speed 10Mb/s */
+#define E1000_STATUS_SPEED_100		0x00000040 /* Speed 100Mb/s */
+#define E1000_STATUS_SPEED_1000		0x00000080 /* Speed 1000Mb/s */
+#define E1000_STATUS_LAN_INIT_DONE	0x00000200 /* Lan Init Compltn by NVM */
+#define E1000_STATUS_ASDV		0x00000300 /* Auto speed detect value */
+#define E1000_STATUS_PHYRA		0x00000400 /* PHY Reset Asserted */
+/* Change in Dock/Undock state clear on write '0'. */
+#define E1000_STATUS_DOCK_CI		0x00000800
+#define E1000_STATUS_GIO_MASTER_ENABLE	0x00080000 /* Master request status */
+#define E1000_STATUS_MTXCKOK		0x00000400 /* MTX clock running OK */
+#define E1000_STATUS_PCI66		0x00000800 /* In 66Mhz slot */
+#define E1000_STATUS_BUS64		0x00001000 /* In 64 bit slot */
+#define E1000_STATUS_PCIX_MODE		0x00002000 /* PCI-X mode */
+#define E1000_STATUS_PCIX_SPEED		0x0000C000 /* PCI-X bus speed */
+#define E1000_STATUS_BMC_SKU_0		0x00100000 /* BMC USB redirect disbld */
+#define E1000_STATUS_BMC_SKU_1		0x00200000 /* BMC SRAM disabled */
+#define E1000_STATUS_BMC_SKU_2		0x00400000 /* BMC SDRAM disabled */
+#define E1000_STATUS_BMC_CRYPTO		0x00800000 /* BMC crypto disabled */
+/* BMC external code execution disabled */
+#define E1000_STATUS_BMC_LITE		0x01000000
+#define E1000_STATUS_RGMII_ENABLE	0x02000000 /* RGMII disabled */
+#define E1000_STATUS_FUSE_8		0x04000000
+#define E1000_STATUS_FUSE_9		0x08000000
+#define E1000_STATUS_SERDES0_DIS	0x10000000 /* SERDES disbld on port 0 */
+#define E1000_STATUS_SERDES1_DIS	0x20000000 /* SERDES disbld on port 1 */
 
 /* Constants used to interpret the masked PCI-X bus speed. */
-#define E1000_STATUS_PCIX_SPEED_66  0x00000000 /* PCI-X bus speed 50-66 MHz */
-#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
-#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /*PCI-X bus speed 100-133 MHz*/
+#define E1000_STATUS_PCIX_SPEED_66	0x00000000 /* PCI-X bus spd 50-66MHz */
+#define E1000_STATUS_PCIX_SPEED_100	0x00004000 /* PCI-X bus spd 66-100MHz */
+#define E1000_STATUS_PCIX_SPEED_133	0x00008000 /* PCI-X bus spd 100-133MHz*/
 
-#define SPEED_10    10
-#define SPEED_100   100
-#define SPEED_1000  1000
-#define HALF_DUPLEX 1
-#define FULL_DUPLEX 2
+#define SPEED_10	10
+#define SPEED_100	100
+#define SPEED_1000	1000
+#define HALF_DUPLEX	1
+#define FULL_DUPLEX	2
 
-#define PHY_FORCE_TIME   20
+#define PHY_FORCE_TIME	20
 
-#define ADVERTISE_10_HALF                 0x0001
-#define ADVERTISE_10_FULL                 0x0002
-#define ADVERTISE_100_HALF                0x0004
-#define ADVERTISE_100_FULL                0x0008
-#define ADVERTISE_1000_HALF               0x0010 /* Not used, just FYI */
-#define ADVERTISE_1000_FULL               0x0020
+#define ADVERTISE_10_HALF		0x0001
+#define ADVERTISE_10_FULL		0x0002
+#define ADVERTISE_100_HALF		0x0004
+#define ADVERTISE_100_FULL		0x0008
+#define ADVERTISE_1000_HALF		0x0010 /* Not used, just FYI */
+#define ADVERTISE_1000_FULL		0x0020
 
 /* 1000/H is not supported, nor spec-compliant. */
-#define E1000_ALL_SPEED_DUPLEX  (ADVERTISE_10_HALF |   ADVERTISE_10_FULL | \
-                                ADVERTISE_100_HALF |  ADVERTISE_100_FULL | \
-                                                     ADVERTISE_1000_FULL)
-#define E1000_ALL_NOT_GIG       (ADVERTISE_10_HALF |   ADVERTISE_10_FULL | \
-                                ADVERTISE_100_HALF |  ADVERTISE_100_FULL)
-#define E1000_ALL_100_SPEED    (ADVERTISE_100_HALF |  ADVERTISE_100_FULL)
-#define E1000_ALL_10_SPEED      (ADVERTISE_10_HALF |   ADVERTISE_10_FULL)
-#define E1000_ALL_FULL_DUPLEX   (ADVERTISE_10_FULL |  ADVERTISE_100_FULL | \
-                                                     ADVERTISE_1000_FULL)
-#define E1000_ALL_HALF_DUPLEX   (ADVERTISE_10_HALF |  ADVERTISE_100_HALF)
-
-#define AUTONEG_ADVERTISE_SPEED_DEFAULT   E1000_ALL_SPEED_DUPLEX
+#define E1000_ALL_SPEED_DUPLEX	( \
+	ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
+	ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
+#define E1000_ALL_NOT_GIG	( \
+	ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
+	ADVERTISE_100_FULL)
+#define E1000_ALL_100_SPEED	(ADVERTISE_100_HALF | ADVERTISE_100_FULL)
+#define E1000_ALL_10_SPEED	(ADVERTISE_10_HALF | ADVERTISE_10_FULL)
+#define E1000_ALL_FULL_DUPLEX	( \
+	ADVERTISE_10_FULL | ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
+#define E1000_ALL_HALF_DUPLEX	(ADVERTISE_10_HALF | ADVERTISE_100_HALF)
+
+#define AUTONEG_ADVERTISE_SPEED_DEFAULT		E1000_ALL_SPEED_DUPLEX
 
 /* LED Control */
-#define E1000_PHY_LED0_MODE_MASK          0x00000007
-#define E1000_PHY_LED0_IVRT               0x00000008
-#define E1000_PHY_LED0_BLINK              0x00000010
-#define E1000_PHY_LED0_MASK               0x0000001F
-
-#define E1000_LEDCTL_LED0_MODE_MASK       0x0000000F
-#define E1000_LEDCTL_LED0_MODE_SHIFT      0
-#define E1000_LEDCTL_LED0_BLINK_RATE      0x00000020
-#define E1000_LEDCTL_LED0_IVRT            0x00000040
-#define E1000_LEDCTL_LED0_BLINK           0x00000080
-#define E1000_LEDCTL_LED1_MODE_MASK       0x00000F00
-#define E1000_LEDCTL_LED1_MODE_SHIFT      8
-#define E1000_LEDCTL_LED1_BLINK_RATE      0x00002000
-#define E1000_LEDCTL_LED1_IVRT            0x00004000
-#define E1000_LEDCTL_LED1_BLINK           0x00008000
-#define E1000_LEDCTL_LED2_MODE_MASK       0x000F0000
-#define E1000_LEDCTL_LED2_MODE_SHIFT      16
-#define E1000_LEDCTL_LED2_BLINK_RATE      0x00200000
-#define E1000_LEDCTL_LED2_IVRT            0x00400000
-#define E1000_LEDCTL_LED2_BLINK           0x00800000
-#define E1000_LEDCTL_LED3_MODE_MASK       0x0F000000
-#define E1000_LEDCTL_LED3_MODE_SHIFT      24
-#define E1000_LEDCTL_LED3_BLINK_RATE      0x20000000
-#define E1000_LEDCTL_LED3_IVRT            0x40000000
-#define E1000_LEDCTL_LED3_BLINK           0x80000000
-
-#define E1000_LEDCTL_MODE_LINK_10_1000  0x0
-#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
-#define E1000_LEDCTL_MODE_LINK_UP       0x2
-#define E1000_LEDCTL_MODE_ACTIVITY      0x3
-#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
-#define E1000_LEDCTL_MODE_LINK_10       0x5
-#define E1000_LEDCTL_MODE_LINK_100      0x6
-#define E1000_LEDCTL_MODE_LINK_1000     0x7
-#define E1000_LEDCTL_MODE_PCIX_MODE     0x8
-#define E1000_LEDCTL_MODE_FULL_DUPLEX   0x9
-#define E1000_LEDCTL_MODE_COLLISION     0xA
-#define E1000_LEDCTL_MODE_BUS_SPEED     0xB
-#define E1000_LEDCTL_MODE_BUS_SIZE      0xC
-#define E1000_LEDCTL_MODE_PAUSED        0xD
-#define E1000_LEDCTL_MODE_LED_ON        0xE
-#define E1000_LEDCTL_MODE_LED_OFF       0xF
+#define E1000_PHY_LED0_MODE_MASK	0x00000007
+#define E1000_PHY_LED0_IVRT		0x00000008
+#define E1000_PHY_LED0_BLINK		0x00000010
+#define E1000_PHY_LED0_MASK		0x0000001F
+
+#define E1000_LEDCTL_LED0_MODE_MASK	0x0000000F
+#define E1000_LEDCTL_LED0_MODE_SHIFT	0
+#define E1000_LEDCTL_LED0_BLINK_RATE	0x00000020
+#define E1000_LEDCTL_LED0_IVRT		0x00000040
+#define E1000_LEDCTL_LED0_BLINK		0x00000080
+#define E1000_LEDCTL_LED1_MODE_MASK	0x00000F00
+#define E1000_LEDCTL_LED1_MODE_SHIFT	8
+#define E1000_LEDCTL_LED1_BLINK_RATE	0x00002000
+#define E1000_LEDCTL_LED1_IVRT		0x00004000
+#define E1000_LEDCTL_LED1_BLINK		0x00008000
+#define E1000_LEDCTL_LED2_MODE_MASK	0x000F0000
+#define E1000_LEDCTL_LED2_MODE_SHIFT	16
+#define E1000_LEDCTL_LED2_BLINK_RATE	0x00200000
+#define E1000_LEDCTL_LED2_IVRT		0x00400000
+#define E1000_LEDCTL_LED2_BLINK		0x00800000
+#define E1000_LEDCTL_LED3_MODE_MASK	0x0F000000
+#define E1000_LEDCTL_LED3_MODE_SHIFT	24
+#define E1000_LEDCTL_LED3_BLINK_RATE	0x20000000
+#define E1000_LEDCTL_LED3_IVRT		0x40000000
+#define E1000_LEDCTL_LED3_BLINK		0x80000000
+
+#define E1000_LEDCTL_MODE_LINK_10_1000	0x0
+#define E1000_LEDCTL_MODE_LINK_100_1000	0x1
+#define E1000_LEDCTL_MODE_LINK_UP	0x2
+#define E1000_LEDCTL_MODE_ACTIVITY	0x3
+#define E1000_LEDCTL_MODE_LINK_ACTIVITY	0x4
+#define E1000_LEDCTL_MODE_LINK_10	0x5
+#define E1000_LEDCTL_MODE_LINK_100	0x6
+#define E1000_LEDCTL_MODE_LINK_1000	0x7
+#define E1000_LEDCTL_MODE_PCIX_MODE	0x8
+#define E1000_LEDCTL_MODE_FULL_DUPLEX	0x9
+#define E1000_LEDCTL_MODE_COLLISION	0xA
+#define E1000_LEDCTL_MODE_BUS_SPEED	0xB
+#define E1000_LEDCTL_MODE_BUS_SIZE	0xC
+#define E1000_LEDCTL_MODE_PAUSED	0xD
+#define E1000_LEDCTL_MODE_LED_ON	0xE
+#define E1000_LEDCTL_MODE_LED_OFF	0xF
 
 /* Transmit Descriptor bit definitions */
-#define E1000_TXD_DTYP_D     0x00100000 /* Data Descriptor */
-#define E1000_TXD_DTYP_C     0x00000000 /* Context Descriptor */
-#define E1000_TXD_POPTS_SHIFT 8         /* POPTS shift */
-#define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
-#define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
-#define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */
-#define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
-#define E1000_TXD_CMD_IC     0x04000000 /* Insert Checksum */
-#define E1000_TXD_CMD_RS     0x08000000 /* Report Status */
-#define E1000_TXD_CMD_RPS    0x10000000 /* Report Packet Sent */
-#define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
-#define E1000_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
-#define E1000_TXD_CMD_IDE    0x80000000 /* Enable Tidv register */
-#define E1000_TXD_STAT_DD    0x00000001 /* Descriptor Done */
-#define E1000_TXD_STAT_EC    0x00000002 /* Excess Collisions */
-#define E1000_TXD_STAT_LC    0x00000004 /* Late Collisions */
-#define E1000_TXD_STAT_TU    0x00000008 /* Transmit underrun */
-#define E1000_TXD_CMD_TCP    0x01000000 /* TCP packet */
-#define E1000_TXD_CMD_IP     0x02000000 /* IP packet */
-#define E1000_TXD_CMD_TSE    0x04000000 /* TCP Seg enable */
-#define E1000_TXD_STAT_TC    0x00000004 /* Tx Underrun */
+#define E1000_TXD_DTYP_D	0x00100000 /* Data Descriptor */
+#define E1000_TXD_DTYP_C	0x00000000 /* Context Descriptor */
+#define E1000_TXD_POPTS_SHIFT	8          /* POPTS shift */
+#define E1000_TXD_POPTS_IXSM	0x01       /* Insert IP checksum */
+#define E1000_TXD_POPTS_TXSM	0x02       /* Insert TCP/UDP checksum */
+#define E1000_TXD_CMD_EOP	0x01000000 /* End of Packet */
+#define E1000_TXD_CMD_IFCS	0x02000000 /* Insert FCS (Ethernet CRC) */
+#define E1000_TXD_CMD_IC	0x04000000 /* Insert Checksum */
+#define E1000_TXD_CMD_RS	0x08000000 /* Report Status */
+#define E1000_TXD_CMD_RPS	0x10000000 /* Report Packet Sent */
+#define E1000_TXD_CMD_DEXT	0x20000000 /* Desc extension (0 = legacy) */
+#define E1000_TXD_CMD_VLE	0x40000000 /* Add VLAN tag */
+#define E1000_TXD_CMD_IDE	0x80000000 /* Enable Tidv register */
+#define E1000_TXD_STAT_DD	0x00000001 /* Descriptor Done */
+#define E1000_TXD_STAT_EC	0x00000002 /* Excess Collisions */
+#define E1000_TXD_STAT_LC	0x00000004 /* Late Collisions */
+#define E1000_TXD_STAT_TU	0x00000008 /* Transmit underrun */
+#define E1000_TXD_CMD_TCP	0x01000000 /* TCP packet */
+#define E1000_TXD_CMD_IP	0x02000000 /* IP packet */
+#define E1000_TXD_CMD_TSE	0x04000000 /* TCP Seg enable */
+#define E1000_TXD_STAT_TC	0x00000004 /* Tx Underrun */
 /* Extended desc bits for Linksec and timesync */
-#define E1000_TXD_CMD_LINKSEC     0x10000000 /* Apply LinkSec on packet */
-#define E1000_TXD_EXTCMD_TSTAMP   0x00000010 /* IEEE1588 Timestamp packet */
+#define E1000_TXD_CMD_LINKSEC	0x10000000 /* Apply LinkSec on packet */
+#define E1000_TXD_EXTCMD_TSTAMP	0x00000010 /* IEEE1588 Timestamp packet */
 
 /* Transmit Control */
-#define E1000_TCTL_RST    0x00000001    /* software reset */
-#define E1000_TCTL_EN     0x00000002    /* enable Tx */
-#define E1000_TCTL_BCE    0x00000004    /* busy check enable */
-#define E1000_TCTL_PSP    0x00000008    /* pad short packets */
-#define E1000_TCTL_CT     0x00000ff0    /* collision threshold */
-#define E1000_TCTL_COLD   0x003ff000    /* collision distance */
-#define E1000_TCTL_SWXOFF 0x00400000    /* SW Xoff transmission */
-#define E1000_TCTL_PBE    0x00800000    /* Packet Burst Enable */
-#define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
-#define E1000_TCTL_NRTU   0x02000000    /* No Re-transmit on underrun */
-#define E1000_TCTL_MULR   0x10000000    /* Multiple request support */
+#define E1000_TCTL_RST		0x00000001 /* software reset */
+#define E1000_TCTL_EN		0x00000002 /* enable Tx */
+#define E1000_TCTL_BCE		0x00000004 /* busy check enable */
+#define E1000_TCTL_PSP		0x00000008 /* pad short packets */
+#define E1000_TCTL_CT		0x00000ff0 /* collision threshold */
+#define E1000_TCTL_COLD		0x003ff000 /* collision distance */
+#define E1000_TCTL_SWXOFF	0x00400000 /* SW Xoff transmission */
+#define E1000_TCTL_PBE		0x00800000 /* Packet Burst Enable */
+#define E1000_TCTL_RTLC		0x01000000 /* Re-transmit on late collision */
+#define E1000_TCTL_NRTU		0x02000000 /* No Re-transmit on underrun */
+#define E1000_TCTL_MULR		0x10000000 /* Multiple request support */
 
 /* Transmit Arbitration Count */
-#define E1000_TARC0_ENABLE     0x00000400   /* Enable Tx Queue 0 */
+#define E1000_TARC0_ENABLE	0x00000400 /* Enable Tx Queue 0 */
 
 /* SerDes Control */
-#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
+#define E1000_SCTL_DISABLE_SERDES_LOOPBACK	0x0400
 
 /* Receive Checksum Control */
-#define E1000_RXCSUM_PCSS_MASK 0x000000FF   /* Packet Checksum Start */
-#define E1000_RXCSUM_IPOFL     0x00000100   /* IPv4 checksum offload */
-#define E1000_RXCSUM_TUOFL     0x00000200   /* TCP / UDP checksum offload */
-#define E1000_RXCSUM_IPV6OFL   0x00000400   /* IPv6 checksum offload */
-#define E1000_RXCSUM_CRCOFL    0x00000800   /* CRC32 offload enable */
-#define E1000_RXCSUM_IPPCSE    0x00001000   /* IP payload checksum enable */
-#define E1000_RXCSUM_PCSD      0x00002000   /* packet checksum disabled */
+#define E1000_RXCSUM_PCSS_MASK	0x000000FF /* Packet Checksum Start */
+#define E1000_RXCSUM_IPOFL	0x00000100 /* IPv4 checksum offload */
+#define E1000_RXCSUM_TUOFL	0x00000200 /* TCP / UDP checksum offload */
+#define E1000_RXCSUM_IPV6OFL	0x00000400 /* IPv6 checksum offload */
+#define E1000_RXCSUM_CRCOFL	0x00000800 /* CRC32 offload enable */
+#define E1000_RXCSUM_IPPCSE	0x00001000 /* IP payload checksum enable */
+#define E1000_RXCSUM_PCSD	0x00002000 /* packet checksum disabled */
 
 /* Header split receive */
-#define E1000_RFCTL_ISCSI_DIS           0x00000001
-#define E1000_RFCTL_ISCSI_DWC_MASK      0x0000003E
-#define E1000_RFCTL_ISCSI_DWC_SHIFT     1
-#define E1000_RFCTL_NFSW_DIS            0x00000040
-#define E1000_RFCTL_NFSR_DIS            0x00000080
-#define E1000_RFCTL_NFS_VER_MASK        0x00000300
-#define E1000_RFCTL_NFS_VER_SHIFT       8
-#define E1000_RFCTL_IPV6_DIS            0x00000400
-#define E1000_RFCTL_IPV6_XSUM_DIS       0x00000800
-#define E1000_RFCTL_ACK_DIS             0x00001000
-#define E1000_RFCTL_ACKD_DIS            0x00002000
-#define E1000_RFCTL_IPFRSP_DIS          0x00004000
-#define E1000_RFCTL_EXTEN               0x00008000
-#define E1000_RFCTL_IPV6_EX_DIS         0x00010000
-#define E1000_RFCTL_NEW_IPV6_EXT_DIS    0x00020000
-#define E1000_RFCTL_LEF                 0x00040000
+#define E1000_RFCTL_ISCSI_DIS		0x00000001
+#define E1000_RFCTL_ISCSI_DWC_MASK	0x0000003E
+#define E1000_RFCTL_ISCSI_DWC_SHIFT	1
+#define E1000_RFCTL_NFSW_DIS		0x00000040
+#define E1000_RFCTL_NFSR_DIS		0x00000080
+#define E1000_RFCTL_NFS_VER_MASK	0x00000300
+#define E1000_RFCTL_NFS_VER_SHIFT	8
+#define E1000_RFCTL_IPV6_DIS		0x00000400
+#define E1000_RFCTL_IPV6_XSUM_DIS	0x00000800
+#define E1000_RFCTL_ACK_DIS		0x00001000
+#define E1000_RFCTL_ACKD_DIS		0x00002000
+#define E1000_RFCTL_IPFRSP_DIS		0x00004000
+#define E1000_RFCTL_EXTEN		0x00008000
+#define E1000_RFCTL_IPV6_EX_DIS		0x00010000
+#define E1000_RFCTL_NEW_IPV6_EXT_DIS	0x00020000
+#define E1000_RFCTL_LEF			0x00040000
 
 /* Collision related configuration parameters */
-#define E1000_COLLISION_THRESHOLD       15
-#define E1000_CT_SHIFT                  4
-#define E1000_COLLISION_DISTANCE        63
-#define E1000_COLD_SHIFT                12
+#define E1000_COLLISION_THRESHOLD	15
+#define E1000_CT_SHIFT			4
+#define E1000_COLLISION_DISTANCE	63
+#define E1000_COLD_SHIFT		12
 
 /* Default values for the transmit IPG register */
-#define DEFAULT_82542_TIPG_IPGT        10
-#define DEFAULT_82543_TIPG_IPGT_FIBER  9
-#define DEFAULT_82543_TIPG_IPGT_COPPER 8
+#define DEFAULT_82542_TIPG_IPGT		10
+#define DEFAULT_82543_TIPG_IPGT_FIBER	9
+#define DEFAULT_82543_TIPG_IPGT_COPPER	8
 
-#define E1000_TIPG_IPGT_MASK  0x000003FF
-#define E1000_TIPG_IPGR1_MASK 0x000FFC00
-#define E1000_TIPG_IPGR2_MASK 0x3FF00000
+#define E1000_TIPG_IPGT_MASK		0x000003FF
+#define E1000_TIPG_IPGR1_MASK		0x000FFC00
+#define E1000_TIPG_IPGR2_MASK		0x3FF00000
 
-#define DEFAULT_82542_TIPG_IPGR1 2
-#define DEFAULT_82543_TIPG_IPGR1 8
-#define E1000_TIPG_IPGR1_SHIFT  10
+#define DEFAULT_82542_TIPG_IPGR1	2
+#define DEFAULT_82543_TIPG_IPGR1	8
+#define E1000_TIPG_IPGR1_SHIFT		10
 
-#define DEFAULT_82542_TIPG_IPGR2 10
-#define DEFAULT_82543_TIPG_IPGR2 6
-#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
-#define E1000_TIPG_IPGR2_SHIFT  20
+#define DEFAULT_82542_TIPG_IPGR2	10
+#define DEFAULT_82543_TIPG_IPGR2	6
+#define DEFAULT_80003ES2LAN_TIPG_IPGR2	7
+#define E1000_TIPG_IPGR2_SHIFT		20
 
 /* Ethertype field values */
-#define ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.3ac packet */
+#define ETHERNET_IEEE_VLAN_TYPE		0x8100  /* 802.3ac packet */
 
-#define ETHERNET_FCS_SIZE       4
-#define MAX_JUMBO_FRAME_SIZE    0x3F00
+#define ETHERNET_FCS_SIZE		4
+#define MAX_JUMBO_FRAME_SIZE		0x3F00
 
 /* Extended Configuration Control and Size */
-#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP      0x00000020
-#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE       0x00000001
-#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE       0x00000008
-#define E1000_EXTCNF_CTRL_SWFLAG                 0x00000020
-#define E1000_EXTCNF_CTRL_GATE_PHY_CFG           0x00000080
-#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK   0x00FF0000
-#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT          16
-#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK   0x0FFF0000
-#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT          16
-
-#define E1000_PHY_CTRL_SPD_EN             0x00000001
-#define E1000_PHY_CTRL_D0A_LPLU           0x00000002
-#define E1000_PHY_CTRL_NOND0A_LPLU        0x00000004
-#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
-#define E1000_PHY_CTRL_GBE_DISABLE        0x00000040
-
-#define E1000_KABGTXD_BGSQLBIAS           0x00050000
+#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP	0x00000020
+#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE	0x00000001
+#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE	0x00000008
+#define E1000_EXTCNF_CTRL_SWFLAG		0x00000020
+#define E1000_EXTCNF_CTRL_GATE_PHY_CFG		0x00000080
+#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK	0x00FF0000
+#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT	16
+#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK	0x0FFF0000
+#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT	16
+
+#define E1000_PHY_CTRL_SPD_EN			0x00000001
+#define E1000_PHY_CTRL_D0A_LPLU			0x00000002
+#define E1000_PHY_CTRL_NOND0A_LPLU		0x00000004
+#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE	0x00000008
+#define E1000_PHY_CTRL_GBE_DISABLE		0x00000040
+
+#define E1000_KABGTXD_BGSQLBIAS			0x00050000
 
 /* PBA constants */
-#define E1000_PBA_6K  0x0006    /* 6KB */
-#define E1000_PBA_8K  0x0008    /* 8KB */
-#define E1000_PBA_10K 0x000A    /* 10KB */
-#define E1000_PBA_12K 0x000C    /* 12KB */
-#define E1000_PBA_14K 0x000E    /* 14KB */
-#define E1000_PBA_16K 0x0010    /* 16KB */
-#define E1000_PBA_18K 0x0012
-#define E1000_PBA_20K 0x0014
-#define E1000_PBA_22K 0x0016
-#define E1000_PBA_24K 0x0018
-#define E1000_PBA_26K 0x001A
-#define E1000_PBA_30K 0x001E
-#define E1000_PBA_32K 0x0020
-#define E1000_PBA_34K 0x0022
-#define E1000_PBA_35K 0x0023
-#define E1000_PBA_38K 0x0026
-#define E1000_PBA_40K 0x0028
-#define E1000_PBA_48K 0x0030    /* 48KB */
-#define E1000_PBA_64K 0x0040    /* 64KB */
-
-#define E1000_PBS_16K E1000_PBA_16K
-#define E1000_PBS_24K E1000_PBA_24K
-
-#define IFS_MAX       80
-#define IFS_MIN       40
-#define IFS_RATIO     4
-#define IFS_STEP      10
-#define MIN_NUM_XMITS 1000
+#define E1000_PBA_6K		0x0006    /* 6KB */
+#define E1000_PBA_8K		0x0008    /* 8KB */
+#define E1000_PBA_10K		0x000A    /* 10KB */
+#define E1000_PBA_12K		0x000C    /* 12KB */
+#define E1000_PBA_14K		0x000E    /* 14KB */
+#define E1000_PBA_16K		0x0010    /* 16KB */
+#define E1000_PBA_18K		0x0012
+#define E1000_PBA_20K		0x0014
+#define E1000_PBA_22K		0x0016
+#define E1000_PBA_24K		0x0018
+#define E1000_PBA_26K		0x001A
+#define E1000_PBA_30K		0x001E
+#define E1000_PBA_32K		0x0020
+#define E1000_PBA_34K		0x0022
+#define E1000_PBA_35K		0x0023
+#define E1000_PBA_38K		0x0026
+#define E1000_PBA_40K		0x0028
+#define E1000_PBA_48K		0x0030    /* 48KB */
+#define E1000_PBA_64K		0x0040    /* 64KB */
+
+#define E1000_PBA_RXA_MASK	0xFFFF;
+
+#define E1000_PBS_16K		E1000_PBA_16K
+#define E1000_PBS_24K		E1000_PBA_24K
+
+#define IFS_MAX			80
+#define IFS_MIN			40
+#define IFS_RATIO		4
+#define IFS_STEP		10
+#define MIN_NUM_XMITS		1000
 
 /* SW Semaphore Register */
-#define E1000_SWSM_SMBI         0x00000001 /* Driver Semaphore bit */
-#define E1000_SWSM_SWESMBI      0x00000002 /* FW Semaphore bit */
-#define E1000_SWSM_WMNG         0x00000004 /* Wake MNG Clock */
-#define E1000_SWSM_DRV_LOAD     0x00000008 /* Driver Loaded Bit */
+#define E1000_SWSM_SMBI		0x00000001 /* Driver Semaphore bit */
+#define E1000_SWSM_SWESMBI	0x00000002 /* FW Semaphore bit */
+#define E1000_SWSM_WMNG		0x00000004 /* Wake MNG Clock */
+#define E1000_SWSM_DRV_LOAD	0x00000008 /* Driver Loaded Bit */
 
-#define E1000_SWSM2_LOCK        0x00000002 /* Secondary driver semaphore bit */
+#define E1000_SWSM2_LOCK	0x00000002 /* Secondary driver semaphore bit */
 
 /* Interrupt Cause Read */
-#define E1000_ICR_TXDW          0x00000001 /* Transmit desc written back */
-#define E1000_ICR_TXQE          0x00000002 /* Transmit Queue empty */
-#define E1000_ICR_LSC           0x00000004 /* Link Status Change */
-#define E1000_ICR_RXSEQ         0x00000008 /* Rx sequence error */
-#define E1000_ICR_RXDMT0        0x00000010 /* Rx desc min. threshold (0) */
-#define E1000_ICR_RXO           0x00000040 /* Rx overrun */
-#define E1000_ICR_RXT0          0x00000080 /* Rx timer intr (ring 0) */
-#define E1000_ICR_VMMB          0x00000100 /* VM MB event */
-#define E1000_ICR_MDAC          0x00000200 /* MDIO access complete */
-#define E1000_ICR_RXCFG         0x00000400 /* Rx /c/ ordered set */
-#define E1000_ICR_GPI_EN0       0x00000800 /* GP Int 0 */
-#define E1000_ICR_GPI_EN1       0x00001000 /* GP Int 1 */
-#define E1000_ICR_GPI_EN2       0x00002000 /* GP Int 2 */
-#define E1000_ICR_GPI_EN3       0x00004000 /* GP Int 3 */
-#define E1000_ICR_TXD_LOW       0x00008000
-#define E1000_ICR_SRPD          0x00010000
-#define E1000_ICR_ACK           0x00020000 /* Receive Ack frame */
-#define E1000_ICR_MNG           0x00040000 /* Manageability event */
-#define E1000_ICR_DOCK          0x00080000 /* Dock/Undock */
-#define E1000_ICR_DRSTA         0x40000000 /* Device Reset Asserted */
-#define E1000_ICR_INT_ASSERTED  0x80000000 /* If this bit asserted, the driver
-                                            * should claim the interrupt */
-#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* Q0 Rx desc FIFO parity error */
-#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* Q0 Tx desc FIFO parity error */
-#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity err */
-#define E1000_ICR_PB_PAR        0x00800000 /* packet buffer parity error */
-#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* Q1 Rx desc FIFO parity error */
-#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* Q1 Tx desc FIFO parity error */
-#define E1000_ICR_ALL_PARITY    0x03F00000 /* all parity error bits */
-#define E1000_ICR_DSW           0x00000020 /* FW changed the status of DISSW
-                                            * bit in the FWSM */
-#define E1000_ICR_PHYINT        0x00001000 /* LAN connected device generates
-                                            * an interrupt */
-#define E1000_ICR_DOUTSYNC      0x10000000 /* NIC DMA out of sync */
-#define E1000_ICR_EPRST         0x00100000 /* ME hardware reset occurs */
-#define E1000_ICR_RXQ0          0x00100000 /* Rx Queue 0 Interrupt */
-#define E1000_ICR_RXQ1          0x00200000 /* Rx Queue 1 Interrupt */
-#define E1000_ICR_TXQ0          0x00400000 /* Tx Queue 0 Interrupt */
-#define E1000_ICR_TXQ1          0x00800000 /* Tx Queue 1 Interrupt */
-#define E1000_ICR_OTHER         0x01000000 /* Other Interrupts */
-#define E1000_ICR_FER           0x00400000 /* Fatal Error */
-
-#define E1000_ICR_THS           0x00800000 /* ICR.THS: Thermal Sensor Event*/
-#define E1000_ICR_MDDET         0x10000000 /* Malicious Driver Detect */
+#define E1000_ICR_TXDW		0x00000001 /* Transmit desc written back */
+#define E1000_ICR_TXQE		0x00000002 /* Transmit Queue empty */
+#define E1000_ICR_LSC		0x00000004 /* Link Status Change */
+#define E1000_ICR_RXSEQ		0x00000008 /* Rx sequence error */
+#define E1000_ICR_RXDMT0	0x00000010 /* Rx desc min. threshold (0) */
+#define E1000_ICR_RXO		0x00000040 /* Rx overrun */
+#define E1000_ICR_RXT0		0x00000080 /* Rx timer intr (ring 0) */
+#define E1000_ICR_VMMB		0x00000100 /* VM MB event */
+#define E1000_ICR_MDAC		0x00000200 /* MDIO access complete */
+#define E1000_ICR_RXCFG		0x00000400 /* Rx /c/ ordered set */
+#define E1000_ICR_GPI_EN0	0x00000800 /* GP Int 0 */
+#define E1000_ICR_GPI_EN1	0x00001000 /* GP Int 1 */
+#define E1000_ICR_GPI_EN2	0x00002000 /* GP Int 2 */
+#define E1000_ICR_GPI_EN3	0x00004000 /* GP Int 3 */
+#define E1000_ICR_TXD_LOW	0x00008000
+#define E1000_ICR_SRPD		0x00010000
+#define E1000_ICR_ACK		0x00020000 /* Receive Ack frame */
+#define E1000_ICR_MNG		0x00040000 /* Manageability event */
+#define E1000_ICR_DOCK		0x00080000 /* Dock/Undock */
+#define E1000_ICR_DRSTA		0x40000000 /* Device Reset Asserted */
+/* If this bit asserted, the driver should claim the interrupt */
+#define E1000_ICR_INT_ASSERTED	0x80000000
+#define E1000_ICR_RXD_FIFO_PAR0	0x00100000 /* Q0 Rx desc FIFO parity error */
+#define E1000_ICR_TXD_FIFO_PAR0	0x00200000 /* Q0 Tx desc FIFO parity error */
+#define E1000_ICR_HOST_ARB_PAR	0x00400000 /* host arb read buffer parity err */
+#define E1000_ICR_PB_PAR	0x00800000 /* packet buffer parity error */
+#define E1000_ICR_RXD_FIFO_PAR1	0x01000000 /* Q1 Rx desc FIFO parity error */
+#define E1000_ICR_TXD_FIFO_PAR1	0x02000000 /* Q1 Tx desc FIFO parity error */
+#define E1000_ICR_ALL_PARITY	0x03F00000 /* all parity error bits */
+/* FW changed the status of DISSW bit in the FWSM */
+#define E1000_ICR_DSW		0x00000020
+/* LAN connected device generates an interrupt */
+#define E1000_ICR_PHYINT	0x00001000
+#define E1000_ICR_DOUTSYNC	0x10000000 /* NIC DMA out of sync */
+#define E1000_ICR_EPRST		0x00100000 /* ME hardware reset occurs */
+#define E1000_ICR_RXQ0		0x00100000 /* Rx Queue 0 Interrupt */
+#define E1000_ICR_RXQ1		0x00200000 /* Rx Queue 1 Interrupt */
+#define E1000_ICR_TXQ0		0x00400000 /* Tx Queue 0 Interrupt */
+#define E1000_ICR_TXQ1		0x00800000 /* Tx Queue 1 Interrupt */
+#define E1000_ICR_OTHER		0x01000000 /* Other Interrupts */
+#define E1000_ICR_FER		0x00400000 /* Fatal Error */
+
+#define E1000_ICR_THS		0x00800000 /* ICR.THS: Thermal Sensor Event*/
+#define E1000_ICR_MDDET		0x10000000 /* Malicious Driver Detect */
+
+#define E1000_ITR_MASK		0x000FFFFF /* ITR value bitfield */
+#define E1000_ITR_MULT		256 /* ITR mulitplier in nsec */
+
 /* PBA ECC Register */
-#define E1000_PBA_ECC_COUNTER_MASK  0xFFF00000 /* ECC counter mask */
-#define E1000_PBA_ECC_COUNTER_SHIFT 20         /* ECC counter shift value */
-#define E1000_PBA_ECC_CORR_EN   0x00000001 /* Enable ECC error correction */
-#define E1000_PBA_ECC_STAT_CLR  0x00000002 /* Clear ECC error counter */
-#define E1000_PBA_ECC_INT_EN    0x00000004 /* Enable ICR bit 5 on ECC error */
+#define E1000_PBA_ECC_COUNTER_MASK	0xFFF00000 /* ECC counter mask */
+#define E1000_PBA_ECC_COUNTER_SHIFT	20 /* ECC counter shift value */
+#define E1000_PBA_ECC_CORR_EN	0x00000001 /* Enable ECC error correction */
+#define E1000_PBA_ECC_STAT_CLR	0x00000002 /* Clear ECC error counter */
+#define E1000_PBA_ECC_INT_EN	0x00000004 /* Enable ICR bit 5 on ECC error */
 
 /* Extended Interrupt Cause Read */
-#define E1000_EICR_RX_QUEUE0    0x00000001 /* Rx Queue 0 Interrupt */
-#define E1000_EICR_RX_QUEUE1    0x00000002 /* Rx Queue 1 Interrupt */
-#define E1000_EICR_RX_QUEUE2    0x00000004 /* Rx Queue 2 Interrupt */
-#define E1000_EICR_RX_QUEUE3    0x00000008 /* Rx Queue 3 Interrupt */
-#define E1000_EICR_TX_QUEUE0    0x00000100 /* Tx Queue 0 Interrupt */
-#define E1000_EICR_TX_QUEUE1    0x00000200 /* Tx Queue 1 Interrupt */
-#define E1000_EICR_TX_QUEUE2    0x00000400 /* Tx Queue 2 Interrupt */
-#define E1000_EICR_TX_QUEUE3    0x00000800 /* Tx Queue 3 Interrupt */
-#define E1000_EICR_TCP_TIMER    0x40000000 /* TCP Timer */
-#define E1000_EICR_OTHER        0x80000000 /* Interrupt Cause Active */
+#define E1000_EICR_RX_QUEUE0	0x00000001 /* Rx Queue 0 Interrupt */
+#define E1000_EICR_RX_QUEUE1	0x00000002 /* Rx Queue 1 Interrupt */
+#define E1000_EICR_RX_QUEUE2	0x00000004 /* Rx Queue 2 Interrupt */
+#define E1000_EICR_RX_QUEUE3	0x00000008 /* Rx Queue 3 Interrupt */
+#define E1000_EICR_TX_QUEUE0	0x00000100 /* Tx Queue 0 Interrupt */
+#define E1000_EICR_TX_QUEUE1	0x00000200 /* Tx Queue 1 Interrupt */
+#define E1000_EICR_TX_QUEUE2	0x00000400 /* Tx Queue 2 Interrupt */
+#define E1000_EICR_TX_QUEUE3	0x00000800 /* Tx Queue 3 Interrupt */
+#define E1000_EICR_TCP_TIMER	0x40000000 /* TCP Timer */
+#define E1000_EICR_OTHER	0x80000000 /* Interrupt Cause Active */
 /* TCP Timer */
-#define E1000_TCPTIMER_KS       0x00000100 /* KickStart */
-#define E1000_TCPTIMER_COUNT_ENABLE       0x00000200 /* Count Enable */
-#define E1000_TCPTIMER_COUNT_FINISH       0x00000400 /* Count finish */
-#define E1000_TCPTIMER_LOOP     0x00000800 /* Loop */
+#define E1000_TCPTIMER_KS	0x00000100 /* KickStart */
+#define E1000_TCPTIMER_COUNT_ENABLE	0x00000200 /* Count Enable */
+#define E1000_TCPTIMER_COUNT_FINISH	0x00000400 /* Count finish */
+#define E1000_TCPTIMER_LOOP	0x00000800 /* Loop */
 
 /*
  * This defines the bits that are set in the Interrupt Mask
@@ -858,8 +869,8 @@
  *   o RXSEQ  = Receive Sequence Error
  */
 #define POLL_IMS_ENABLE_MASK ( \
-    E1000_IMS_RXDMT0 |    \
-    E1000_IMS_RXSEQ)
+	E1000_IMS_RXDMT0 |    \
+	E1000_IMS_RXSEQ)
 
 /*
  * This defines the bits that are set in the Interrupt Mask
@@ -871,142 +882,142 @@
  *   o LSC    = Link Status Change
  */
 #define IMS_ENABLE_MASK ( \
-    E1000_IMS_RXT0   |    \
-    E1000_IMS_TXDW   |    \
-    E1000_IMS_RXDMT0 |    \
-    E1000_IMS_RXSEQ  |    \
-    E1000_IMS_LSC)
+	E1000_IMS_RXT0   |    \
+	E1000_IMS_TXDW   |    \
+	E1000_IMS_RXDMT0 |    \
+	E1000_IMS_RXSEQ  |    \
+	E1000_IMS_LSC)
 
 /* Interrupt Mask Set */
-#define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Tx desc written back */
-#define E1000_IMS_TXQE      E1000_ICR_TXQE      /* Transmit Queue empty */
-#define E1000_IMS_LSC       E1000_ICR_LSC       /* Link Status Change */
-#define E1000_IMS_VMMB      E1000_ICR_VMMB      /* Mail box activity */
-#define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ     /* Rx sequence error */
-#define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0    /* Rx desc min. threshold */
-#define E1000_IMS_RXO       E1000_ICR_RXO       /* Rx overrun */
-#define E1000_IMS_RXT0      E1000_ICR_RXT0      /* Rx timer intr */
-#define E1000_IMS_MDAC      E1000_ICR_MDAC      /* MDIO access complete */
-#define E1000_IMS_RXCFG     E1000_ICR_RXCFG     /* Rx /c/ ordered set */
-#define E1000_IMS_GPI_EN0   E1000_ICR_GPI_EN0   /* GP Int 0 */
-#define E1000_IMS_GPI_EN1   E1000_ICR_GPI_EN1   /* GP Int 1 */
-#define E1000_IMS_GPI_EN2   E1000_ICR_GPI_EN2   /* GP Int 2 */
-#define E1000_IMS_GPI_EN3   E1000_ICR_GPI_EN3   /* GP Int 3 */
-#define E1000_IMS_TXD_LOW   E1000_ICR_TXD_LOW
-#define E1000_IMS_SRPD      E1000_ICR_SRPD
-#define E1000_IMS_ACK       E1000_ICR_ACK       /* Receive Ack frame */
-#define E1000_IMS_MNG       E1000_ICR_MNG       /* Manageability event */
-#define E1000_IMS_DOCK      E1000_ICR_DOCK      /* Dock/Undock */
-#define E1000_IMS_DRSTA     E1000_ICR_DRSTA     /* Device Reset Asserted */
-#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO
-                                                         * parity error */
-#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO
-                                                         * parity error */
-#define E1000_IMS_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR  /* host arb read buffer
-                                                         * parity error */
-#define E1000_IMS_PB_PAR        E1000_ICR_PB_PAR        /* packet buffer parity
-                                                         * error */
-#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO
-                                                         * parity error */
-#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO
-                                                         * parity error */
-#define E1000_IMS_DSW       E1000_ICR_DSW
-#define E1000_IMS_PHYINT    E1000_ICR_PHYINT
-#define E1000_IMS_DOUTSYNC  E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
-#define E1000_IMS_EPRST     E1000_ICR_EPRST
-#define E1000_IMS_RXQ0          E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */
-#define E1000_IMS_RXQ1          E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */
-#define E1000_IMS_TXQ0          E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */
-#define E1000_IMS_TXQ1          E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */
-#define E1000_IMS_OTHER         E1000_ICR_OTHER /* Other Interrupts */
-#define E1000_IMS_FER           E1000_ICR_FER /* Fatal Error */
-
-#define E1000_IMS_THS           E1000_ICR_THS /* ICR.TS: Thermal Sensor Event*/
-#define E1000_IMS_MDDET         E1000_ICR_MDDET /* Malicious Driver Detect */
+#define E1000_IMS_TXDW		E1000_ICR_TXDW    /* Tx desc written back */
+#define E1000_IMS_TXQE		E1000_ICR_TXQE    /* Transmit Queue empty */
+#define E1000_IMS_LSC		E1000_ICR_LSC     /* Link Status Change */
+#define E1000_IMS_VMMB		E1000_ICR_VMMB    /* Mail box activity */
+#define E1000_IMS_RXSEQ		E1000_ICR_RXSEQ   /* Rx sequence error */
+#define E1000_IMS_RXDMT0	E1000_ICR_RXDMT0  /* Rx desc min. threshold */
+#define E1000_IMS_RXO		E1000_ICR_RXO     /* Rx overrun */
+#define E1000_IMS_RXT0		E1000_ICR_RXT0    /* Rx timer intr */
+#define E1000_IMS_MDAC		E1000_ICR_MDAC    /* MDIO access complete */
+#define E1000_IMS_RXCFG		E1000_ICR_RXCFG   /* Rx /c/ ordered set */
+#define E1000_IMS_GPI_EN0	E1000_ICR_GPI_EN0 /* GP Int 0 */
+#define E1000_IMS_GPI_EN1	E1000_ICR_GPI_EN1 /* GP Int 1 */
+#define E1000_IMS_GPI_EN2	E1000_ICR_GPI_EN2 /* GP Int 2 */
+#define E1000_IMS_GPI_EN3	E1000_ICR_GPI_EN3 /* GP Int 3 */
+#define E1000_IMS_TXD_LOW	E1000_ICR_TXD_LOW
+#define E1000_IMS_SRPD		E1000_ICR_SRPD
+#define E1000_IMS_ACK		E1000_ICR_ACK     /* Receive Ack frame */
+#define E1000_IMS_MNG		E1000_ICR_MNG     /* Manageability event */
+#define E1000_IMS_DOCK		E1000_ICR_DOCK    /* Dock/Undock */
+#define E1000_IMS_DRSTA		E1000_ICR_DRSTA   /* Device Reset Asserted */
+/* Q0 Rx desc FIFO parity error */
+#define E1000_IMS_RXD_FIFO_PAR0	E1000_ICR_RXD_FIFO_PAR0
+/* Q0 Tx desc FIFO parity error */
+#define E1000_IMS_TXD_FIFO_PAR0	E1000_ICR_TXD_FIFO_PAR0
+/* host arb read buffer parity error */
+#define E1000_IMS_HOST_ARB_PAR	E1000_ICR_HOST_ARB_PAR
+/* packet buffer parity error */
+#define E1000_IMS_PB_PAR	E1000_ICR_PB_PAR
+/* Q1 Rx desc FIFO parity error */
+#define E1000_IMS_RXD_FIFO_PAR1	E1000_ICR_RXD_FIFO_PAR1
+/* Q1 Tx desc FIFO parity error */
+#define E1000_IMS_TXD_FIFO_PAR1	E1000_ICR_TXD_FIFO_PAR1
+#define E1000_IMS_DSW		E1000_ICR_DSW
+#define E1000_IMS_PHYINT	E1000_ICR_PHYINT
+#define E1000_IMS_DOUTSYNC	E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
+#define E1000_IMS_EPRST		E1000_ICR_EPRST
+#define E1000_IMS_RXQ0		E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */
+#define E1000_IMS_RXQ1		E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */
+#define E1000_IMS_TXQ0		E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */
+#define E1000_IMS_TXQ1		E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */
+#define E1000_IMS_OTHER		E1000_ICR_OTHER /* Other Interrupts */
+#define E1000_IMS_FER		E1000_ICR_FER /* Fatal Error */
+
+#define E1000_IMS_THS		E1000_ICR_THS /* ICR.TS: Thermal Sensor Event*/
+#define E1000_IMS_MDDET		E1000_ICR_MDDET /* Malicious Driver Detect */
 /* Extended Interrupt Mask Set */
-#define E1000_EIMS_RX_QUEUE0    E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
-#define E1000_EIMS_RX_QUEUE1    E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
-#define E1000_EIMS_RX_QUEUE2    E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
-#define E1000_EIMS_RX_QUEUE3    E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
-#define E1000_EIMS_TX_QUEUE0    E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
-#define E1000_EIMS_TX_QUEUE1    E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
-#define E1000_EIMS_TX_QUEUE2    E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
-#define E1000_EIMS_TX_QUEUE3    E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
-#define E1000_EIMS_TCP_TIMER    E1000_EICR_TCP_TIMER /* TCP Timer */
-#define E1000_EIMS_OTHER        E1000_EICR_OTHER   /* Interrupt Cause Active */
+#define E1000_EIMS_RX_QUEUE0	E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
+#define E1000_EIMS_RX_QUEUE1	E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
+#define E1000_EIMS_RX_QUEUE2	E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
+#define E1000_EIMS_RX_QUEUE3	E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
+#define E1000_EIMS_TX_QUEUE0	E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
+#define E1000_EIMS_TX_QUEUE1	E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
+#define E1000_EIMS_TX_QUEUE2	E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
+#define E1000_EIMS_TX_QUEUE3	E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
+#define E1000_EIMS_TCP_TIMER	E1000_EICR_TCP_TIMER /* TCP Timer */
+#define E1000_EIMS_OTHER	E1000_EICR_OTHER   /* Interrupt Cause Active */
 
 /* Interrupt Cause Set */
-#define E1000_ICS_TXDW      E1000_ICR_TXDW      /* Tx desc written back */
-#define E1000_ICS_TXQE      E1000_ICR_TXQE      /* Transmit Queue empty */
-#define E1000_ICS_LSC       E1000_ICR_LSC       /* Link Status Change */
-#define E1000_ICS_RXSEQ     E1000_ICR_RXSEQ     /* Rx sequence error */
-#define E1000_ICS_RXDMT0    E1000_ICR_RXDMT0    /* Rx desc min. threshold */
-#define E1000_ICS_RXO       E1000_ICR_RXO       /* Rx overrun */
-#define E1000_ICS_RXT0      E1000_ICR_RXT0      /* Rx timer intr */
-#define E1000_ICS_MDAC      E1000_ICR_MDAC      /* MDIO access complete */
-#define E1000_ICS_RXCFG     E1000_ICR_RXCFG     /* Rx /c/ ordered set */
-#define E1000_ICS_GPI_EN0   E1000_ICR_GPI_EN0   /* GP Int 0 */
-#define E1000_ICS_GPI_EN1   E1000_ICR_GPI_EN1   /* GP Int 1 */
-#define E1000_ICS_GPI_EN2   E1000_ICR_GPI_EN2   /* GP Int 2 */
-#define E1000_ICS_GPI_EN3   E1000_ICR_GPI_EN3   /* GP Int 3 */
-#define E1000_ICS_TXD_LOW   E1000_ICR_TXD_LOW
-#define E1000_ICS_SRPD      E1000_ICR_SRPD
-#define E1000_ICS_ACK       E1000_ICR_ACK       /* Receive Ack frame */
-#define E1000_ICS_MNG       E1000_ICR_MNG       /* Manageability event */
-#define E1000_ICS_DOCK      E1000_ICR_DOCK      /* Dock/Undock */
-#define E1000_ICS_DRSTA     E1000_ICR_DRSTA     /* Device Reset Aserted */
-#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO
-                                                         * parity error */
-#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO
-                                                         * parity error */
-#define E1000_ICS_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR  /* host arb read buffer
-                                                         * parity error */
-#define E1000_ICS_PB_PAR        E1000_ICR_PB_PAR        /* packet buffer parity
-                                                         * error */
-#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO
-                                                         * parity error */
-#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO
-                                                         * parity error */
-#define E1000_ICS_DSW       E1000_ICR_DSW
-#define E1000_ICS_DOUTSYNC  E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
-#define E1000_ICS_PHYINT    E1000_ICR_PHYINT
-#define E1000_ICS_EPRST     E1000_ICR_EPRST
+#define E1000_ICS_TXDW		E1000_ICR_TXDW      /* Tx desc written back */
+#define E1000_ICS_TXQE		E1000_ICR_TXQE      /* Transmit Queue empty */
+#define E1000_ICS_LSC		E1000_ICR_LSC       /* Link Status Change */
+#define E1000_ICS_RXSEQ		E1000_ICR_RXSEQ     /* Rx sequence error */
+#define E1000_ICS_RXDMT0	E1000_ICR_RXDMT0    /* Rx desc min. threshold */
+#define E1000_ICS_RXO		E1000_ICR_RXO       /* Rx overrun */
+#define E1000_ICS_RXT0		E1000_ICR_RXT0      /* Rx timer intr */
+#define E1000_ICS_MDAC		E1000_ICR_MDAC      /* MDIO access complete */
+#define E1000_ICS_RXCFG		E1000_ICR_RXCFG     /* Rx /c/ ordered set */
+#define E1000_ICS_GPI_EN0	E1000_ICR_GPI_EN0   /* GP Int 0 */
+#define E1000_ICS_GPI_EN1	E1000_ICR_GPI_EN1   /* GP Int 1 */
+#define E1000_ICS_GPI_EN2	E1000_ICR_GPI_EN2   /* GP Int 2 */
+#define E1000_ICS_GPI_EN3	E1000_ICR_GPI_EN3   /* GP Int 3 */
+#define E1000_ICS_TXD_LOW	E1000_ICR_TXD_LOW
+#define E1000_ICS_SRPD		E1000_ICR_SRPD
+#define E1000_ICS_ACK		E1000_ICR_ACK       /* Receive Ack frame */
+#define E1000_ICS_MNG		E1000_ICR_MNG       /* Manageability event */
+#define E1000_ICS_DOCK		E1000_ICR_DOCK      /* Dock/Undock */
+#define E1000_ICS_DRSTA		E1000_ICR_DRSTA     /* Device Reset Aserted */
+/* Q0 Rx desc FIFO parity error */
+#define E1000_ICS_RXD_FIFO_PAR0	E1000_ICR_RXD_FIFO_PAR0
+/* Q0 Tx desc FIFO parity error */
+#define E1000_ICS_TXD_FIFO_PAR0	E1000_ICR_TXD_FIFO_PAR0
+/* host arb read buffer parity error */
+#define E1000_ICS_HOST_ARB_PAR	E1000_ICR_HOST_ARB_PAR
+/* packet buffer parity error */
+#define E1000_ICS_PB_PAR	E1000_ICR_PB_PAR
+/* Q1 Rx desc FIFO parity error */
+#define E1000_ICS_RXD_FIFO_PAR1	E1000_ICR_RXD_FIFO_PAR1
+/* Q1 Tx desc FIFO parity error */
+#define E1000_ICS_TXD_FIFO_PAR1	E1000_ICR_TXD_FIFO_PAR1
+#define E1000_ICS_DSW		E1000_ICR_DSW
+#define E1000_ICS_DOUTSYNC	E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
+#define E1000_ICS_PHYINT	E1000_ICR_PHYINT
+#define E1000_ICS_EPRST		E1000_ICR_EPRST
 
 /* Extended Interrupt Cause Set */
-#define E1000_EICS_RX_QUEUE0    E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
-#define E1000_EICS_RX_QUEUE1    E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
-#define E1000_EICS_RX_QUEUE2    E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
-#define E1000_EICS_RX_QUEUE3    E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
-#define E1000_EICS_TX_QUEUE0    E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
-#define E1000_EICS_TX_QUEUE1    E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
-#define E1000_EICS_TX_QUEUE2    E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
-#define E1000_EICS_TX_QUEUE3    E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
-#define E1000_EICS_TCP_TIMER    E1000_EICR_TCP_TIMER /* TCP Timer */
-#define E1000_EICS_OTHER        E1000_EICR_OTHER   /* Interrupt Cause Active */
-
-#define E1000_EITR_ITR_INT_MASK 0x0000FFFF
+#define E1000_EICS_RX_QUEUE0	E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
+#define E1000_EICS_RX_QUEUE1	E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
+#define E1000_EICS_RX_QUEUE2	E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
+#define E1000_EICS_RX_QUEUE3	E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
+#define E1000_EICS_TX_QUEUE0	E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
+#define E1000_EICS_TX_QUEUE1	E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
+#define E1000_EICS_TX_QUEUE2	E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
+#define E1000_EICS_TX_QUEUE3	E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
+#define E1000_EICS_TCP_TIMER	E1000_EICR_TCP_TIMER /* TCP Timer */
+#define E1000_EICS_OTHER	E1000_EICR_OTHER   /* Interrupt Cause Active */
+
+#define E1000_EITR_ITR_INT_MASK	0x0000FFFF
 /* E1000_EITR_CNT_IGNR is only for 82576 and newer */
-#define E1000_EITR_CNT_IGNR     0x80000000 /* Don't reset counters on write */
+#define E1000_EITR_CNT_IGNR	0x80000000 /* Don't reset counters on write */
 
 /* Transmit Descriptor Control */
-#define E1000_TXDCTL_PTHRESH    0x0000003F /* TXDCTL Prefetch Threshold */
-#define E1000_TXDCTL_HTHRESH    0x00003F00 /* TXDCTL Host Threshold */
-#define E1000_TXDCTL_WTHRESH    0x003F0000 /* TXDCTL Writeback Threshold */
-#define E1000_TXDCTL_GRAN       0x01000000 /* TXDCTL Granularity */
-#define E1000_TXDCTL_LWTHRESH   0xFE000000 /* TXDCTL Low Threshold */
-#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
+#define E1000_TXDCTL_PTHRESH	0x0000003F /* TXDCTL Prefetch Threshold */
+#define E1000_TXDCTL_HTHRESH	0x00003F00 /* TXDCTL Host Threshold */
+#define E1000_TXDCTL_WTHRESH	0x003F0000 /* TXDCTL Writeback Threshold */
+#define E1000_TXDCTL_GRAN	0x01000000 /* TXDCTL Granularity */
+#define E1000_TXDCTL_LWTHRESH	0xFE000000 /* TXDCTL Low Threshold */
+#define E1000_TXDCTL_FULL_TX_DESC_WB	0x01010000 /* GRAN=1, WTHRESH=1 */
 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
 /* Enable the counting of descriptors still to be processed. */
-#define E1000_TXDCTL_COUNT_DESC 0x00400000
+#define E1000_TXDCTL_COUNT_DESC	0x00400000
 
 /* Flow Control Constants */
-#define FLOW_CONTROL_ADDRESS_LOW  0x00C28001
-#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
-#define FLOW_CONTROL_TYPE         0x8808
+#define FLOW_CONTROL_ADDRESS_LOW	0x00C28001
+#define FLOW_CONTROL_ADDRESS_HIGH	0x00000100
+#define FLOW_CONTROL_TYPE		0x8808
 
 /* 802.1q VLAN Packet Size */
-#define VLAN_TAG_SIZE              4    /* 802.3ac tag (not DMA'd) */
-#define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */
+#define VLAN_TAG_SIZE			4    /* 802.3ac tag (not DMA'd) */
+#define E1000_VLAN_FILTER_TBL_SIZE	128  /* VLAN Filter Table (4096 bits) */
 
 /* Receive Address */
 /*
@@ -1016,529 +1027,550 @@
  * (RAR[15]) for our directed address used by controllers with
  * manageability enabled, allowing us room for 15 multicast addresses.
  */
-#define E1000_RAR_ENTRIES     15
-#define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */
-#define E1000_RAL_MAC_ADDR_LEN 4
-#define E1000_RAH_MAC_ADDR_LEN 2
-#define E1000_RAH_QUEUE_MASK_82575 0x000C0000
-#define E1000_RAH_POOL_MASK     0x03FC0000
-#define E1000_RAH_POOL_SHIFT    18
-#define E1000_RAH_POOL_1        0x00040000
+#define E1000_RAR_ENTRIES	15
+#define E1000_RAH_AV		0x80000000 /* Receive descriptor valid */
+#define E1000_RAL_MAC_ADDR_LEN	4
+#define E1000_RAH_MAC_ADDR_LEN	2
+#define E1000_RAH_QUEUE_MASK_82575	0x000C0000
+#define E1000_RAH_POOL_MASK	0x03FC0000
+#define E1000_RAH_POOL_SHIFT	18
+#define E1000_RAH_POOL_1	0x00040000
 
 /* Error Codes */
-#define E1000_SUCCESS      0
-#define E1000_ERR_NVM      1
-#define E1000_ERR_PHY      2
-#define E1000_ERR_CONFIG   3
-#define E1000_ERR_PARAM    4
-#define E1000_ERR_MAC_INIT 5
-#define E1000_ERR_PHY_TYPE 6
-#define E1000_ERR_RESET   9
-#define E1000_ERR_MASTER_REQUESTS_PENDING 10
-#define E1000_ERR_HOST_INTERFACE_COMMAND 11
-#define E1000_BLK_PHY_RESET   12
-#define E1000_ERR_SWFW_SYNC 13
-#define E1000_NOT_IMPLEMENTED 14
-#define E1000_ERR_MBX      15
-#define E1000_ERR_INVALID_ARGUMENT  16
-#define E1000_ERR_NO_SPACE          17
-#define E1000_ERR_NVM_PBA_SECTION   18
+#define E1000_SUCCESS			0
+#define E1000_ERR_NVM			1
+#define E1000_ERR_PHY			2
+#define E1000_ERR_CONFIG		3
+#define E1000_ERR_PARAM			4
+#define E1000_ERR_MAC_INIT		5
+#define E1000_ERR_PHY_TYPE		6
+#define E1000_ERR_RESET			9
+#define E1000_ERR_MASTER_REQUESTS_PENDING	10
+#define E1000_ERR_HOST_INTERFACE_COMMAND	11
+#define E1000_BLK_PHY_RESET		12
+#define E1000_ERR_SWFW_SYNC		13
+#define E1000_NOT_IMPLEMENTED		14
+#define E1000_ERR_MBX			15
+#define E1000_ERR_INVALID_ARGUMENT	16
+#define E1000_ERR_NO_SPACE		17
+#define E1000_ERR_NVM_PBA_SECTION	18
+#define E1000_ERR_I2C			19
+#define E1000_ERR_INVM_VALUE_NOT_FOUND	20
 
 /* Loop limit on how long we wait for auto-negotiation to complete */
-#define FIBER_LINK_UP_LIMIT               50
-#define COPPER_LINK_UP_LIMIT              10
-#define PHY_AUTO_NEG_LIMIT                45
-#define PHY_FORCE_LIMIT                   20
+#define FIBER_LINK_UP_LIMIT		50
+#define COPPER_LINK_UP_LIMIT		10
+#define PHY_AUTO_NEG_LIMIT		45
+#define PHY_FORCE_LIMIT			20
 /* Number of 100 microseconds we wait for PCI Express master disable */
-#define MASTER_DISABLE_TIMEOUT      800
+#define MASTER_DISABLE_TIMEOUT		800
 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
-#define PHY_CFG_TIMEOUT             100
+#define PHY_CFG_TIMEOUT			100
 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
-#define MDIO_OWNERSHIP_TIMEOUT      10
+#define MDIO_OWNERSHIP_TIMEOUT		10
 /* Number of milliseconds for NVM auto read done after MAC reset. */
-#define AUTO_READ_DONE_TIMEOUT      10
+#define AUTO_READ_DONE_TIMEOUT		10
 
 /* Flow Control */
-#define E1000_FCRTH_RTH  0x0000FFF8     /* Mask Bits[15:3] for RTH */
-#define E1000_FCRTH_XFCE 0x80000000     /* External Flow Control Enable */
-#define E1000_FCRTL_RTL  0x0000FFF8     /* Mask Bits[15:3] for RTL */
-#define E1000_FCRTL_XONE 0x80000000     /* Enable XON frame transmission */
+#define E1000_FCRTH_RTH		0x0000FFF8 /* Mask Bits[15:3] for RTH */
+#define E1000_FCRTH_XFCE	0x80000000 /* External Flow Control Enable */
+#define E1000_FCRTL_RTL		0x0000FFF8 /* Mask Bits[15:3] for RTL */
+#define E1000_FCRTL_XONE	0x80000000 /* Enable XON frame transmission */
 
 /* Transmit Configuration Word */
-#define E1000_TXCW_FD         0x00000020        /* TXCW full duplex */
-#define E1000_TXCW_HD         0x00000040        /* TXCW half duplex */
-#define E1000_TXCW_PAUSE      0x00000080        /* TXCW sym pause request */
-#define E1000_TXCW_ASM_DIR    0x00000100        /* TXCW astm pause direction */
-#define E1000_TXCW_PAUSE_MASK 0x00000180        /* TXCW pause request mask */
-#define E1000_TXCW_RF         0x00003000        /* TXCW remote fault */
-#define E1000_TXCW_NP         0x00008000        /* TXCW next page */
-#define E1000_TXCW_CW         0x0000ffff        /* TxConfigWord mask */
-#define E1000_TXCW_TXC        0x40000000        /* Transmit Config control */
-#define E1000_TXCW_ANE        0x80000000        /* Auto-neg enable */
+#define E1000_TXCW_FD		0x00000020 /* TXCW full duplex */
+#define E1000_TXCW_HD		0x00000040 /* TXCW half duplex */
+#define E1000_TXCW_PAUSE	0x00000080 /* TXCW sym pause request */
+#define E1000_TXCW_ASM_DIR	0x00000100 /* TXCW astm pause direction */
+#define E1000_TXCW_PAUSE_MASK	0x00000180 /* TXCW pause request mask */
+#define E1000_TXCW_RF		0x00003000 /* TXCW remote fault */
+#define E1000_TXCW_NP		0x00008000 /* TXCW next page */
+#define E1000_TXCW_CW		0x0000ffff /* TxConfigWord mask */
+#define E1000_TXCW_TXC		0x40000000 /* Transmit Config control */
+#define E1000_TXCW_ANE		0x80000000 /* Auto-neg enable */
 
 /* Receive Configuration Word */
-#define E1000_RXCW_CW         0x0000ffff        /* RxConfigWord mask */
-#define E1000_RXCW_NC         0x04000000        /* Receive config no carrier */
-#define E1000_RXCW_IV         0x08000000        /* Receive config invalid */
-#define E1000_RXCW_CC         0x10000000        /* Receive config change */
-#define E1000_RXCW_C          0x20000000        /* Receive config */
-#define E1000_RXCW_SYNCH      0x40000000        /* Receive config synch */
-#define E1000_RXCW_ANC        0x80000000        /* Auto-neg complete */
-
-#define E1000_TSYNCTXCTL_VALID    0x00000001 /* Tx timestamp valid */
-#define E1000_TSYNCTXCTL_ENABLED  0x00000010 /* enable Tx timestamping */
-
-#define E1000_TSYNCRXCTL_VALID      0x00000001 /* Rx timestamp valid */
-#define E1000_TSYNCRXCTL_TYPE_MASK  0x0000000E /* Rx type mask */
-#define E1000_TSYNCRXCTL_TYPE_L2_V2       0x00
-#define E1000_TSYNCRXCTL_TYPE_L4_V1       0x02
-#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2    0x04
-#define E1000_TSYNCRXCTL_TYPE_ALL         0x08
-#define E1000_TSYNCRXCTL_TYPE_EVENT_V2    0x0A
-#define E1000_TSYNCRXCTL_ENABLED    0x00000010 /* enable Rx timestamping */
-
-#define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK   0x000000FF
-#define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE       0x00
-#define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE  0x01
-#define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE   0x02
-#define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03
-#define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04
-
-#define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK               0x00000F00
-#define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE                 0x0000
-#define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE            0x0100
-#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE       0x0200
-#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE      0x0300
-#define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE             0x0800
-#define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE           0x0900
-#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE  0x0A00
-#define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE             0x0B00
-#define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE           0x0C00
-#define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE           0x0D00
-
-#define E1000_TIMINCA_16NS_SHIFT 24
+#define E1000_RXCW_CW		0x0000ffff /* RxConfigWord mask */
+#define E1000_RXCW_NC		0x04000000 /* Receive config no carrier */
+#define E1000_RXCW_IV		0x08000000 /* Receive config invalid */
+#define E1000_RXCW_CC		0x10000000 /* Receive config change */
+#define E1000_RXCW_C		0x20000000 /* Receive config */
+#define E1000_RXCW_SYNCH	0x40000000 /* Receive config synch */
+#define E1000_RXCW_ANC		0x80000000 /* Auto-neg complete */
+
+#define E1000_TSYNCTXCTL_VALID		0x00000001 /* Tx timestamp valid */
+#define E1000_TSYNCTXCTL_ENABLED	0x00000010 /* enable Tx timestamping */
+
+#define E1000_TSYNCRXCTL_VALID		0x00000001 /* Rx timestamp valid */
+#define E1000_TSYNCRXCTL_TYPE_MASK	0x0000000E /* Rx type mask */
+#define E1000_TSYNCRXCTL_TYPE_L2_V2	0x00
+#define E1000_TSYNCRXCTL_TYPE_L4_V1	0x02
+#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2	0x04
+#define E1000_TSYNCRXCTL_TYPE_ALL	0x08
+#define E1000_TSYNCRXCTL_TYPE_EVENT_V2	0x0A
+#define E1000_TSYNCRXCTL_ENABLED	0x00000010 /* enable Rx timestamping */
+
+#define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK		0x000000FF
+#define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE		0x00
+#define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE	0x01
+#define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE	0x02
+#define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE	0x03
+#define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE	0x04
+
+#define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK		0x00000F00
+#define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE		0x0000
+#define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE	0x0100
+#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE	0x0200
+#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE	0x0300
+#define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE	0x0800
+#define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE	0x0900
+#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00
+#define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE	0x0B00
+#define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE	0x0C00
+#define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE	0x0D00
+
+#define E1000_TIMINCA_16NS_SHIFT	24
 /* TUPLE Filtering Configuration */
-#define E1000_TTQF_DISABLE_MASK   0xF0008000     /* TTQF Disable Mask */
-#define E1000_TTQF_QUEUE_ENABLE   0x100          /* TTQF Queue Enable Bit */
-#define E1000_TTQF_PROTOCOL_MASK  0xFF           /* TTQF Protocol Mask */
+#define E1000_TTQF_DISABLE_MASK		0xF0008000 /* TTQF Disable Mask */
+#define E1000_TTQF_QUEUE_ENABLE		0x100   /* TTQF Queue Enable Bit */
+#define E1000_TTQF_PROTOCOL_MASK	0xFF    /* TTQF Protocol Mask */
 /* TTQF TCP Bit, shift with E1000_TTQF_PROTOCOL SHIFT */
-#define E1000_TTQF_PROTOCOL_TCP   0x0
+#define E1000_TTQF_PROTOCOL_TCP		0x0
 /* TTQF UDP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
-#define E1000_TTQF_PROTOCOL_UDP   0x1
+#define E1000_TTQF_PROTOCOL_UDP		0x1
 /* TTQF SCTP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
-#define E1000_TTQF_PROTOCOL_SCTP  0x2
-#define E1000_TTQF_PROTOCOL_SHIFT 5              /* TTQF Protocol Shift */
-#define E1000_TTQF_QUEUE_SHIFT    16             /* TTQF Queue Shfit */
-#define E1000_TTQF_RX_QUEUE_MASK  0x70000        /* TTQF Queue Mask */
-#define E1000_TTQF_MASK_ENABLE    0x10000000     /* TTQF Mask Enable Bit */
-#define E1000_IMIR_CLEAR_MASK     0xF001FFFF     /* IMIR Reg Clear Mask */
-#define E1000_IMIR_PORT_BYPASS    0x20000        /* IMIR Port Bypass Bit */
-#define E1000_IMIR_PRIORITY_SHIFT 29             /* IMIR Priority Shift */
-#define E1000_IMIREXT_CLEAR_MASK  0x7FFFF        /* IMIREXT Reg Clear Mask */
-
-#define E1000_MDICNFG_EXT_MDIO    0x80000000      /* MDI ext/int destination */
-#define E1000_MDICNFG_COM_MDIO    0x40000000      /* MDI shared w/ lan 0 */
-#define E1000_MDICNFG_PHY_MASK    0x03E00000
-#define E1000_MDICNFG_PHY_SHIFT   21
-
-#define E1000_THSTAT_LOW_EVENT      0x20000000  /* Low thermal threshold */
-#define E1000_THSTAT_MID_EVENT      0x00200000  /* Mid thermal threshold */
-#define E1000_THSTAT_HIGH_EVENT     0x00002000  /* High thermal threshold */
-#define E1000_THSTAT_PWR_DOWN       0x00000001  /* Power Down Event */
-#define E1000_THSTAT_LINK_THROTTLE  0x00000002  /* Link Speed Throttle Event */
-
-/* Powerville EEE defines */
-#define E1000_IPCNFG_EEE_1G_AN      0x00000008  /* IPCNFG EEE Enable 1G AN */
-#define E1000_IPCNFG_EEE_100M_AN    0x00000004  /* IPCNFG EEE Enable 100M AN */
-#define E1000_EEER_TX_LPI_EN        0x00010000  /* EEER Tx LPI Enable */
-#define E1000_EEER_RX_LPI_EN        0x00020000  /* EEER Rx LPI Enable */
-#define E1000_EEER_LPI_FC           0x00040000  /* EEER Enable on Flow Control*/
+#define E1000_TTQF_PROTOCOL_SCTP	0x2
+#define E1000_TTQF_PROTOCOL_SHIFT	5       /* TTQF Protocol Shift */
+#define E1000_TTQF_QUEUE_SHIFT		16      /* TTQF Queue Shfit */
+#define E1000_TTQF_RX_QUEUE_MASK	0x70000 /* TTQF Queue Mask */
+#define E1000_TTQF_MASK_ENABLE		0x10000000 /* TTQF Mask Enable Bit */
+#define E1000_IMIR_CLEAR_MASK		0xF001FFFF /* IMIR Reg Clear Mask */
+#define E1000_IMIR_PORT_BYPASS		0x20000 /* IMIR Port Bypass Bit */
+#define E1000_IMIR_PRIORITY_SHIFT	29 /* IMIR Priority Shift */
+#define E1000_IMIREXT_CLEAR_MASK	0x7FFFF /* IMIREXT Reg Clear Mask */
+
+#define E1000_MDICNFG_EXT_MDIO		0x80000000 /* MDI ext/int destination */
+#define E1000_MDICNFG_COM_MDIO		0x40000000 /* MDI shared w/ lan 0 */
+#define E1000_MDICNFG_PHY_MASK		0x03E00000
+#define E1000_MDICNFG_PHY_SHIFT		21
+
+#define E1000_THSTAT_LOW_EVENT		0x20000000 /* Low thermal threshold */
+#define E1000_THSTAT_MID_EVENT		0x00200000 /* Mid thermal threshold */
+#define E1000_THSTAT_HIGH_EVENT		0x00002000 /* High thermal threshold */
+#define E1000_THSTAT_PWR_DOWN		0x00000001 /* Power Down Event */
+#define E1000_THSTAT_LINK_THROTTLE	0x00000002 /* Link Spd Throttle Event */
+
+/* I350 EEE defines */
+#define E1000_IPCNFG_EEE_1G_AN		0x00000008 /* IPCNFG EEE Ena 1G AN */
+#define E1000_IPCNFG_EEE_100M_AN	0x00000004 /* IPCNFG EEE Ena 100M AN */
+#define E1000_EEER_TX_LPI_EN		0x00010000 /* EEER Tx LPI Enable */
+#define E1000_EEER_RX_LPI_EN		0x00020000 /* EEER Rx LPI Enable */
+#define E1000_EEER_LPI_FC		0x00040000 /* EEER Ena on Flow Cntrl */
 /* EEE status */
-#define E1000_EEER_EEE_NEG          0x20000000  /* EEE capability negotiated */
-#define E1000_EEER_RX_LPI_STATUS    0x40000000  /* Rx in LPI state */
-#define E1000_EEER_TX_LPI_STATUS    0x80000000  /* Tx in LPI state */
+#define E1000_EEER_EEE_NEG		0x20000000 /* EEE capability nego */
+#define E1000_EEER_RX_LPI_STATUS	0x40000000 /* Rx in LPI state */
+#define E1000_EEER_TX_LPI_STATUS	0x80000000 /* Tx in LPI state */
 
 /* PCI Express Control */
-#define E1000_GCR_RXD_NO_SNOOP          0x00000001
-#define E1000_GCR_RXDSCW_NO_SNOOP       0x00000002
-#define E1000_GCR_RXDSCR_NO_SNOOP       0x00000004
-#define E1000_GCR_TXD_NO_SNOOP          0x00000008
-#define E1000_GCR_TXDSCW_NO_SNOOP       0x00000010
-#define E1000_GCR_TXDSCR_NO_SNOOP       0x00000020
-#define E1000_GCR_CMPL_TMOUT_MASK       0x0000F000
-#define E1000_GCR_CMPL_TMOUT_10ms       0x00001000
-#define E1000_GCR_CMPL_TMOUT_RESEND     0x00010000
-#define E1000_GCR_CAP_VER2              0x00040000
-
-#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP         | \
-                           E1000_GCR_RXDSCW_NO_SNOOP      | \
-                           E1000_GCR_RXDSCR_NO_SNOOP      | \
-                           E1000_GCR_TXD_NO_SNOOP         | \
-                           E1000_GCR_TXDSCW_NO_SNOOP      | \
-                           E1000_GCR_TXDSCR_NO_SNOOP)
+#define E1000_GCR_RXD_NO_SNOOP		0x00000001
+#define E1000_GCR_RXDSCW_NO_SNOOP	0x00000002
+#define E1000_GCR_RXDSCR_NO_SNOOP	0x00000004
+#define E1000_GCR_TXD_NO_SNOOP		0x00000008
+#define E1000_GCR_TXDSCW_NO_SNOOP	0x00000010
+#define E1000_GCR_TXDSCR_NO_SNOOP	0x00000020
+#define E1000_GCR_CMPL_TMOUT_MASK	0x0000F000
+#define E1000_GCR_CMPL_TMOUT_10ms	0x00001000
+#define E1000_GCR_CMPL_TMOUT_RESEND	0x00010000
+#define E1000_GCR_CAP_VER2		0x00040000
+
+#define PCIE_NO_SNOOP_ALL	(E1000_GCR_RXD_NO_SNOOP | \
+				 E1000_GCR_RXDSCW_NO_SNOOP | \
+				 E1000_GCR_RXDSCR_NO_SNOOP | \
+				 E1000_GCR_TXD_NO_SNOOP    | \
+				 E1000_GCR_TXDSCW_NO_SNOOP | \
+				 E1000_GCR_TXDSCR_NO_SNOOP)
+
+/* mPHY address control and data registers */
+#define E1000_MPHY_ADDR_CTL		0x0024 /* Address Control Reg */
+#define E1000_MPHY_ADDR_CTL_OFFSET_MASK	0xFFFF0000
+#define E1000_MPHY_DATA			0x0E10 /* Data Register */
+
+/* AFE CSR Offset for PCS CLK */
+#define E1000_MPHY_PCS_CLK_REG_OFFSET	0x0004
+/* Override for near end digital loopback. */
+#define E1000_MPHY_PCS_CLK_REG_DIGINELBEN	0x10
 
 /* PHY Control Register */
-#define MII_CR_SPEED_SELECT_MSB 0x0040  /* bits 6,13: 10=1000, 01=100, 00=10 */
-#define MII_CR_COLL_TEST_ENABLE 0x0080  /* Collision test enable */
-#define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
-#define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
-#define MII_CR_ISOLATE          0x0400  /* Isolate PHY from MII */
-#define MII_CR_POWER_DOWN       0x0800  /* Power down */
-#define MII_CR_AUTO_NEG_EN      0x1000  /* Auto Neg Enable */
-#define MII_CR_SPEED_SELECT_LSB 0x2000  /* bits 6,13: 10=1000, 01=100, 00=10 */
-#define MII_CR_LOOPBACK         0x4000  /* 0 = normal, 1 = loopback */
-#define MII_CR_RESET            0x8000  /* 0 = normal, 1 = PHY reset */
-#define MII_CR_SPEED_1000       0x0040
-#define MII_CR_SPEED_100        0x2000
-#define MII_CR_SPEED_10         0x0000
+#define MII_CR_SPEED_SELECT_MSB	0x0040  /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define MII_CR_COLL_TEST_ENABLE	0x0080  /* Collision test enable */
+#define MII_CR_FULL_DUPLEX	0x0100  /* FDX =1, half duplex =0 */
+#define MII_CR_RESTART_AUTO_NEG	0x0200  /* Restart auto negotiation */
+#define MII_CR_ISOLATE		0x0400  /* Isolate PHY from MII */
+#define MII_CR_POWER_DOWN	0x0800  /* Power down */
+#define MII_CR_AUTO_NEG_EN	0x1000  /* Auto Neg Enable */
+#define MII_CR_SPEED_SELECT_LSB	0x2000  /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define MII_CR_LOOPBACK		0x4000  /* 0 = normal, 1 = loopback */
+#define MII_CR_RESET		0x8000  /* 0 = normal, 1 = PHY reset */
+#define MII_CR_SPEED_1000	0x0040
+#define MII_CR_SPEED_100	0x2000
+#define MII_CR_SPEED_10		0x0000
 
 /* PHY Status Register */
-#define MII_SR_EXTENDED_CAPS     0x0001 /* Extended register capabilities */
-#define MII_SR_JABBER_DETECT     0x0002 /* Jabber Detected */
-#define MII_SR_LINK_STATUS       0x0004 /* Link Status 1 = link */
-#define MII_SR_AUTONEG_CAPS      0x0008 /* Auto Neg Capable */
-#define MII_SR_REMOTE_FAULT      0x0010 /* Remote Fault Detect */
-#define MII_SR_AUTONEG_COMPLETE  0x0020 /* Auto Neg Complete */
+#define MII_SR_EXTENDED_CAPS	0x0001 /* Extended register capabilities */
+#define MII_SR_JABBER_DETECT	0x0002 /* Jabber Detected */
+#define MII_SR_LINK_STATUS	0x0004 /* Link Status 1 = link */
+#define MII_SR_AUTONEG_CAPS	0x0008 /* Auto Neg Capable */
+#define MII_SR_REMOTE_FAULT	0x0010 /* Remote Fault Detect */
+#define MII_SR_AUTONEG_COMPLETE	0x0020 /* Auto Neg Complete */
 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
-#define MII_SR_EXTENDED_STATUS   0x0100 /* Ext. status info in Reg 0x0F */
-#define MII_SR_100T2_HD_CAPS     0x0200 /* 100T2 Half Duplex Capable */
-#define MII_SR_100T2_FD_CAPS     0x0400 /* 100T2 Full Duplex Capable */
-#define MII_SR_10T_HD_CAPS       0x0800 /* 10T   Half Duplex Capable */
-#define MII_SR_10T_FD_CAPS       0x1000 /* 10T   Full Duplex Capable */
-#define MII_SR_100X_HD_CAPS      0x2000 /* 100X  Half Duplex Capable */
-#define MII_SR_100X_FD_CAPS      0x4000 /* 100X  Full Duplex Capable */
-#define MII_SR_100T4_CAPS        0x8000 /* 100T4 Capable */
+#define MII_SR_EXTENDED_STATUS	0x0100 /* Ext. status info in Reg 0x0F */
+#define MII_SR_100T2_HD_CAPS	0x0200 /* 100T2 Half Duplex Capable */
+#define MII_SR_100T2_FD_CAPS	0x0400 /* 100T2 Full Duplex Capable */
+#define MII_SR_10T_HD_CAPS	0x0800 /* 10T   Half Duplex Capable */
+#define MII_SR_10T_FD_CAPS	0x1000 /* 10T   Full Duplex Capable */
+#define MII_SR_100X_HD_CAPS	0x2000 /* 100X  Half Duplex Capable */
+#define MII_SR_100X_FD_CAPS	0x4000 /* 100X  Full Duplex Capable */
+#define MII_SR_100T4_CAPS	0x8000 /* 100T4 Capable */
 
 /* Autoneg Advertisement Register */
-#define NWAY_AR_SELECTOR_FIELD   0x0001   /* indicates IEEE 802.3 CSMA/CD */
-#define NWAY_AR_10T_HD_CAPS      0x0020   /* 10T   Half Duplex Capable */
-#define NWAY_AR_10T_FD_CAPS      0x0040   /* 10T   Full Duplex Capable */
-#define NWAY_AR_100TX_HD_CAPS    0x0080   /* 100TX Half Duplex Capable */
-#define NWAY_AR_100TX_FD_CAPS    0x0100   /* 100TX Full Duplex Capable */
-#define NWAY_AR_100T4_CAPS       0x0200   /* 100T4 Capable */
-#define NWAY_AR_PAUSE            0x0400   /* Pause operation desired */
-#define NWAY_AR_ASM_DIR          0x0800   /* Asymmetric Pause Direction bit */
-#define NWAY_AR_REMOTE_FAULT     0x2000   /* Remote Fault detected */
-#define NWAY_AR_NEXT_PAGE        0x8000   /* Next Page ability supported */
+#define NWAY_AR_SELECTOR_FIELD	0x0001   /* indicates IEEE 802.3 CSMA/CD */
+#define NWAY_AR_10T_HD_CAPS	0x0020   /* 10T   Half Duplex Capable */
+#define NWAY_AR_10T_FD_CAPS	0x0040   /* 10T   Full Duplex Capable */
+#define NWAY_AR_100TX_HD_CAPS	0x0080   /* 100TX Half Duplex Capable */
+#define NWAY_AR_100TX_FD_CAPS	0x0100   /* 100TX Full Duplex Capable */
+#define NWAY_AR_100T4_CAPS	0x0200   /* 100T4 Capable */
+#define NWAY_AR_PAUSE		0x0400   /* Pause operation desired */
+#define NWAY_AR_ASM_DIR		0x0800   /* Asymmetric Pause Direction bit */
+#define NWAY_AR_REMOTE_FAULT	0x2000   /* Remote Fault detected */
+#define NWAY_AR_NEXT_PAGE	0x8000   /* Next Page ability supported */
 
 /* Link Partner Ability Register (Base Page) */
-#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
-#define NWAY_LPAR_10T_HD_CAPS    0x0020 /* LP is 10T   Half Duplex Capable */
-#define NWAY_LPAR_10T_FD_CAPS    0x0040 /* LP is 10T   Full Duplex Capable */
-#define NWAY_LPAR_100TX_HD_CAPS  0x0080 /* LP is 100TX Half Duplex Capable */
-#define NWAY_LPAR_100TX_FD_CAPS  0x0100 /* LP is 100TX Full Duplex Capable */
-#define NWAY_LPAR_100T4_CAPS     0x0200 /* LP is 100T4 Capable */
-#define NWAY_LPAR_PAUSE          0x0400 /* LP Pause operation desired */
-#define NWAY_LPAR_ASM_DIR        0x0800 /* LP Asymmetric Pause Direction bit */
-#define NWAY_LPAR_REMOTE_FAULT   0x2000 /* LP has detected Remote Fault */
-#define NWAY_LPAR_ACKNOWLEDGE    0x4000 /* LP has rx'd link code word */
-#define NWAY_LPAR_NEXT_PAGE      0x8000 /* Next Page ability supported */
+#define NWAY_LPAR_SELECTOR_FIELD	0x0000 /* LP protocol selector field */
+#define NWAY_LPAR_10T_HD_CAPS		0x0020 /* LP 10T Half Dplx Capable */
+#define NWAY_LPAR_10T_FD_CAPS		0x0040 /* LP 10T Full Dplx Capable */
+#define NWAY_LPAR_100TX_HD_CAPS		0x0080 /* LP 100TX Half Dplx Capable */
+#define NWAY_LPAR_100TX_FD_CAPS		0x0100 /* LP 100TX Full Dplx Capable */
+#define NWAY_LPAR_100T4_CAPS		0x0200 /* LP is 100T4 Capable */
+#define NWAY_LPAR_PAUSE			0x0400 /* LP Pause operation desired */
+#define NWAY_LPAR_ASM_DIR		0x0800 /* LP Asym Pause Direction bit */
+#define NWAY_LPAR_REMOTE_FAULT		0x2000 /* LP detected Remote Fault */
+#define NWAY_LPAR_ACKNOWLEDGE		0x4000 /* LP rx'd link code word */
+#define NWAY_LPAR_NEXT_PAGE		0x8000 /* Next Page ability supported */
 
 /* Autoneg Expansion Register */
-#define NWAY_ER_LP_NWAY_CAPS      0x0001 /* LP has Auto Neg Capability */
-#define NWAY_ER_PAGE_RXD          0x0002 /* LP is 10T   Half Duplex Capable */
-#define NWAY_ER_NEXT_PAGE_CAPS    0x0004 /* LP is 10T   Full Duplex Capable */
-#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
-#define NWAY_ER_PAR_DETECT_FAULT  0x0010 /* LP is 100TX Full Duplex Capable */
+#define NWAY_ER_LP_NWAY_CAPS		0x0001 /* LP has Auto Neg Capability */
+#define NWAY_ER_PAGE_RXD		0x0002 /* LP 10T Half Dplx Capable */
+#define NWAY_ER_NEXT_PAGE_CAPS		0x0004 /* LP 10T Full Dplx Capable */
+#define NWAY_ER_LP_NEXT_PAGE_CAPS	0x0008 /* LP 100TX Half Dplx Capable */
+#define NWAY_ER_PAR_DETECT_FAULT	0x0010 /* LP 100TX Full Dplx Capable */
 
 /* 1000BASE-T Control Register */
-#define CR_1000T_ASYM_PAUSE      0x0080 /* Advertise asymmetric pause bit */
-#define CR_1000T_HD_CAPS         0x0100 /* Advertise 1000T HD capability */
-#define CR_1000T_FD_CAPS         0x0200 /* Advertise 1000T FD capability  */
-#define CR_1000T_REPEATER_DTE    0x0400 /* 1=Repeater/switch device port */
-                                        /* 0=DTE device */
-#define CR_1000T_MS_VALUE        0x0800 /* 1=Configure PHY as Master */
-                                        /* 0=Configure PHY as Slave */
-#define CR_1000T_MS_ENABLE      0x1000 /* 1=Master/Slave manual config value */
-                                        /* 0=Automatic Master/Slave config */
+#define CR_1000T_ASYM_PAUSE	0x0080 /* Advertise asymmetric pause bit */
+#define CR_1000T_HD_CAPS	0x0100 /* Advertise 1000T HD capability */
+#define CR_1000T_FD_CAPS	0x0200 /* Advertise 1000T FD capability  */
+/* 1=Repeater/switch device port 0=DTE device */
+#define CR_1000T_REPEATER_DTE	0x0400
+/* 1=Configure PHY as Master 0=Configure PHY as Slave */
+#define CR_1000T_MS_VALUE	0x0800
+/* 1=Master/Slave manual config value 0=Automatic Master/Slave config */
+#define CR_1000T_MS_ENABLE	0x1000
 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
-#define CR_1000T_TEST_MODE_1     0x2000 /* Transmit Waveform test */
-#define CR_1000T_TEST_MODE_2     0x4000 /* Master Transmit Jitter test */
-#define CR_1000T_TEST_MODE_3     0x6000 /* Slave Transmit Jitter test */
-#define CR_1000T_TEST_MODE_4     0x8000 /* Transmitter Distortion test */
+#define CR_1000T_TEST_MODE_1	0x2000 /* Transmit Waveform test */
+#define CR_1000T_TEST_MODE_2	0x4000 /* Master Transmit Jitter test */
+#define CR_1000T_TEST_MODE_3	0x6000 /* Slave Transmit Jitter test */
+#define CR_1000T_TEST_MODE_4	0x8000 /* Transmitter Distortion test */
 
 /* 1000BASE-T Status Register */
-#define SR_1000T_IDLE_ERROR_CNT   0x00FF /* Num idle errors since last read */
-#define SR_1000T_ASYM_PAUSE_DIR  0x0100 /* LP asymmetric pause direction bit */
-#define SR_1000T_LP_HD_CAPS       0x0400 /* LP is 1000T HD capable */
-#define SR_1000T_LP_FD_CAPS       0x0800 /* LP is 1000T FD capable */
-#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
-#define SR_1000T_LOCAL_RX_STATUS  0x2000 /* Local receiver OK */
-#define SR_1000T_MS_CONFIG_RES    0x4000 /* 1=Local Tx is Master, 0=Slave */
-#define SR_1000T_MS_CONFIG_FAULT  0x8000 /* Master/Slave config fault */
+#define SR_1000T_IDLE_ERROR_CNT		0x00FF /* Num idle err since last rd */
+#define SR_1000T_ASYM_PAUSE_DIR		0x0100 /* LP asym pause direction bit */
+#define SR_1000T_LP_HD_CAPS		0x0400 /* LP is 1000T HD capable */
+#define SR_1000T_LP_FD_CAPS		0x0800 /* LP is 1000T FD capable */
+#define SR_1000T_REMOTE_RX_STATUS	0x1000 /* Remote receiver OK */
+#define SR_1000T_LOCAL_RX_STATUS	0x2000 /* Local receiver OK */
+#define SR_1000T_MS_CONFIG_RES		0x4000 /* 1=Local Tx Master, 0=Slave */
+#define SR_1000T_MS_CONFIG_FAULT	0x8000 /* Master/Slave config fault */
 
-#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
+#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT	5
 
 /* PHY 1000 MII Register/Bit Definitions */
 /* PHY Registers defined by IEEE */
-#define PHY_CONTROL      0x00 /* Control Register */
-#define PHY_STATUS       0x01 /* Status Register */
-#define PHY_ID1          0x02 /* Phy Id Reg (word 1) */
-#define PHY_ID2          0x03 /* Phy Id Reg (word 2) */
-#define PHY_AUTONEG_ADV  0x04 /* Autoneg Advertisement */
-#define PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */
-#define PHY_AUTONEG_EXP  0x06 /* Autoneg Expansion Reg */
-#define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */
-#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
-#define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
-#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
-#define PHY_EXT_STATUS   0x0F /* Extended Status Reg */
-
-#define PHY_CONTROL_LB   0x4000 /* PHY Loopback bit */
+#define PHY_CONTROL		0x00 /* Control Register */
+#define PHY_STATUS		0x01 /* Status Register */
+#define PHY_ID1			0x02 /* Phy Id Reg (word 1) */
+#define PHY_ID2			0x03 /* Phy Id Reg (word 2) */
+#define PHY_AUTONEG_ADV		0x04 /* Autoneg Advertisement */
+#define PHY_LP_ABILITY		0x05 /* Link Partner Ability (Base Page) */
+#define PHY_AUTONEG_EXP		0x06 /* Autoneg Expansion Reg */
+#define PHY_NEXT_PAGE_TX	0x07 /* Next Page Tx */
+#define PHY_LP_NEXT_PAGE	0x08 /* Link Partner Next Page */
+#define PHY_1000T_CTRL		0x09 /* 1000Base-T Control Reg */
+#define PHY_1000T_STATUS	0x0A /* 1000Base-T Status Reg */
+#define PHY_EXT_STATUS		0x0F /* Extended Status Reg */
+
+#define PHY_CONTROL_LB		0x4000 /* PHY Loopback bit */
 
 /* NVM Control */
-#define E1000_EECD_SK        0x00000001 /* NVM Clock */
-#define E1000_EECD_CS        0x00000002 /* NVM Chip Select */
-#define E1000_EECD_DI        0x00000004 /* NVM Data In */
-#define E1000_EECD_DO        0x00000008 /* NVM Data Out */
-#define E1000_EECD_FWE_MASK  0x00000030
-#define E1000_EECD_FWE_DIS   0x00000010 /* Disable FLASH writes */
-#define E1000_EECD_FWE_EN    0x00000020 /* Enable FLASH writes */
-#define E1000_EECD_FWE_SHIFT 4
-#define E1000_EECD_REQ       0x00000040 /* NVM Access Request */
-#define E1000_EECD_GNT       0x00000080 /* NVM Access Grant */
-#define E1000_EECD_PRES      0x00000100 /* NVM Present */
-#define E1000_EECD_SIZE      0x00000200 /* NVM Size (0=64 word 1=256 word) */
+#define E1000_EECD_SK		0x00000001 /* NVM Clock */
+#define E1000_EECD_CS		0x00000002 /* NVM Chip Select */
+#define E1000_EECD_DI		0x00000004 /* NVM Data In */
+#define E1000_EECD_DO		0x00000008 /* NVM Data Out */
+#define E1000_EECD_FWE_MASK	0x00000030
+#define E1000_EECD_FWE_DIS	0x00000010 /* Disable FLASH writes */
+#define E1000_EECD_FWE_EN	0x00000020 /* Enable FLASH writes */
+#define E1000_EECD_FWE_SHIFT	4
+#define E1000_EECD_REQ		0x00000040 /* NVM Access Request */
+#define E1000_EECD_GNT		0x00000080 /* NVM Access Grant */
+#define E1000_EECD_PRES		0x00000100 /* NVM Present */
+#define E1000_EECD_SIZE		0x00000200 /* NVM Size (0=64 word 1=256 word) */
+#define E1000_EECD_BLOCKED	0x00008000 /* Bit banging access blocked flag */
+#define E1000_EECD_ABORT	0x00010000 /* NVM operation aborted flag */
+#define E1000_EECD_TIMEOUT	0x00020000 /* NVM read operation timeout flag */
+#define E1000_EECD_ERROR_CLR	0x00040000 /* NVM error status clear bit */
 /* NVM Addressing bits based on type 0=small, 1=large */
-#define E1000_EECD_ADDR_BITS 0x00000400
-#define E1000_EECD_TYPE      0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
+#define E1000_EECD_ADDR_BITS	0x00000400
+#define E1000_EECD_TYPE		0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
 #ifndef E1000_NVM_GRANT_ATTEMPTS
-#define E1000_NVM_GRANT_ATTEMPTS   1000 /* NVM # attempts to gain grant */
+#define E1000_NVM_GRANT_ATTEMPTS	1000 /* NVM # attempts to gain grant */
 #endif
-#define E1000_EECD_AUTO_RD          0x00000200  /* NVM Auto Read done */
-#define E1000_EECD_SIZE_EX_MASK     0x00007800  /* NVM Size */
-#define E1000_EECD_SIZE_EX_SHIFT     11
-#define E1000_EECD_NVADDS    0x00018000 /* NVM Address Size */
-#define E1000_EECD_SELSHAD   0x00020000 /* Select Shadow RAM */
-#define E1000_EECD_INITSRAM  0x00040000 /* Initialize Shadow RAM */
-#define E1000_EECD_FLUPD     0x00080000 /* Update FLASH */
-#define E1000_EECD_AUPDEN    0x00100000 /* Enable Autonomous FLASH update */
-#define E1000_EECD_SHADV     0x00200000 /* Shadow RAM Data Valid */
-#define E1000_EECD_SEC1VAL   0x00400000 /* Sector One Valid */
-#define E1000_EECD_SECVAL_SHIFT      22
-#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
-
-#define E1000_NVM_SWDPIN0   0x0001   /* SWDPIN 0 NVM Value */
-#define E1000_NVM_LED_LOGIC 0x0020   /* Led Logic Word */
-#define E1000_NVM_RW_REG_DATA   16  /* Offset to data in NVM read/write regs */
-#define E1000_NVM_RW_REG_DONE   2    /* Offset to READ/WRITE done bit */
-#define E1000_NVM_RW_REG_START  1    /* Start operation */
-#define E1000_NVM_RW_ADDR_SHIFT 2    /* Shift to the address bits */
-#define E1000_NVM_POLL_WRITE    1    /* Flag for polling for write complete */
-#define E1000_NVM_POLL_READ     0    /* Flag for polling for read complete */
-#define E1000_FLASH_UPDATES  2000
+#define E1000_EECD_AUTO_RD		0x00000200  /* NVM Auto Read done */
+#define E1000_EECD_SIZE_EX_MASK		0x00007800  /* NVM Size */
+#define E1000_EECD_SIZE_EX_SHIFT	11
+#define E1000_EECD_NVADDS		0x00018000 /* NVM Address Size */
+#define E1000_EECD_SELSHAD		0x00020000 /* Select Shadow RAM */
+#define E1000_EECD_INITSRAM		0x00040000 /* Initialize Shadow RAM */
+#define E1000_EECD_FLUPD		0x00080000 /* Update FLASH */
+#define E1000_EECD_AUPDEN		0x00100000 /* Ena Auto FLASH update */
+#define E1000_EECD_SHADV		0x00200000 /* Shadow RAM Data Valid */
+#define E1000_EECD_SEC1VAL		0x00400000 /* Sector One Valid */
+#define E1000_EECD_SECVAL_SHIFT		22
+#define E1000_EECD_SEC1VAL_VALID_MASK	(E1000_EECD_AUTO_RD | E1000_EECD_PRES)
+
+#define E1000_NVM_SWDPIN0	0x0001 /* SWDPIN 0 NVM Value */
+#define E1000_NVM_LED_LOGIC	0x0020 /* Led Logic Word */
+#define E1000_NVM_RW_REG_DATA	16  /* Offset to data in NVM read/write regs */
+#define E1000_NVM_RW_REG_DONE	2   /* Offset to READ/WRITE done bit */
+#define E1000_NVM_RW_REG_START	1   /* Start operation */
+#define E1000_NVM_RW_ADDR_SHIFT	2   /* Shift to the address bits */
+#define E1000_NVM_POLL_WRITE	1   /* Flag for polling for write complete */
+#define E1000_NVM_POLL_READ	0   /* Flag for polling for read complete */
+#define E1000_FLASH_UPDATES	2000
 
 /* NVM Word Offsets */
-#define NVM_COMPAT                 0x0003
-#define NVM_ID_LED_SETTINGS        0x0004
-#define NVM_VERSION                0x0005
-#define NVM_SERDES_AMPLITUDE       0x0006 /* SERDES output amplitude */
-#define NVM_PHY_CLASS_WORD         0x0007
-#define NVM_INIT_CONTROL1_REG      0x000A
-#define NVM_INIT_CONTROL2_REG      0x000F
-#define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010
-#define NVM_INIT_CONTROL3_PORT_B   0x0014
-#define NVM_INIT_3GIO_3            0x001A
-#define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020
-#define NVM_INIT_CONTROL3_PORT_A   0x0024
-#define NVM_CFG                    0x0012
-#define NVM_FLASH_VERSION          0x0032
-#define NVM_ALT_MAC_ADDR_PTR       0x0037
-#define NVM_CHECKSUM_REG           0x003F
-#define NVM_COMPATIBILITY_REG_3    0x0003
-#define NVM_COMPATIBILITY_BIT_MASK 0x8000
-
-#define E1000_NVM_CFG_DONE_PORT_0  0x040000 /* MNG config cycle done */
-#define E1000_NVM_CFG_DONE_PORT_1  0x080000 /* ...for second port */
-#define E1000_NVM_CFG_DONE_PORT_2  0x100000 /* ...for third port */
-#define E1000_NVM_CFG_DONE_PORT_3  0x200000 /* ...for fourth port */
-
-#define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0)
+#define NVM_COMPAT			0x0003
+#define NVM_ID_LED_SETTINGS		0x0004
+#define NVM_VERSION			0x0005
+#define NVM_SERDES_AMPLITUDE		0x0006 /* SERDES output amplitude */
+#define NVM_PHY_CLASS_WORD		0x0007
+#define NVM_INIT_CONTROL1_REG		0x000A
+#define NVM_INIT_CONTROL2_REG		0x000F
+#define NVM_SWDEF_PINS_CTRL_PORT_1	0x0010
+#define NVM_INIT_CONTROL3_PORT_B	0x0014
+#define NVM_INIT_3GIO_3			0x001A
+#define NVM_SWDEF_PINS_CTRL_PORT_0	0x0020
+#define NVM_INIT_CONTROL3_PORT_A	0x0024
+#define NVM_CFG				0x0012
+#define NVM_FLASH_VERSION		0x0032
+#define NVM_ALT_MAC_ADDR_PTR		0x0037
+#define NVM_CHECKSUM_REG		0x003F
+#define NVM_COMPATIBILITY_REG_3		0x0003
+#define NVM_COMPATIBILITY_BIT_MASK	0x8000
+
+#define E1000_NVM_CFG_DONE_PORT_0	0x040000 /* MNG config cycle done */
+#define E1000_NVM_CFG_DONE_PORT_1	0x080000 /* ...for second port */
+#define E1000_NVM_CFG_DONE_PORT_2	0x100000 /* ...for third port */
+#define E1000_NVM_CFG_DONE_PORT_3	0x200000 /* ...for fourth port */
+
+#define NVM_82580_LAN_FUNC_OFFSET(a)	(a ? (0x40 + (0x40 * a)) : 0)
 
 /* Mask bits for fields in Word 0x24 of the NVM */
-#define NVM_WORD24_COM_MDIO         0x0008 /* MDIO interface shared */
-#define NVM_WORD24_EXT_MDIO         0x0004 /* MDIO accesses routed external */
+#define NVM_WORD24_COM_MDIO		0x0008 /* MDIO interface shared */
+#define NVM_WORD24_EXT_MDIO		0x0004 /* MDIO accesses routed extrnl */
+/* Offset of Link Mode bits for 82575 up to Kawela */
+#define NVM_WORD24_LNK_MODE_OFFSET	8
+/* Offset of Link Mode bits for 82580 up */
+#define NVM_WORD24_82580_LNK_MODE_OFFSET	4
+
 
 /* Mask bits for fields in Word 0x0f of the NVM */
-#define NVM_WORD0F_PAUSE_MASK       0x3000
-#define NVM_WORD0F_PAUSE            0x1000
-#define NVM_WORD0F_ASM_DIR          0x2000
-#define NVM_WORD0F_ANE              0x0800
-#define NVM_WORD0F_SWPDIO_EXT_MASK  0x00F0
-#define NVM_WORD0F_LPLU             0x0001
+#define NVM_WORD0F_PAUSE_MASK		0x3000
+#define NVM_WORD0F_PAUSE		0x1000
+#define NVM_WORD0F_ASM_DIR		0x2000
+#define NVM_WORD0F_ANE			0x0800
+#define NVM_WORD0F_SWPDIO_EXT_MASK	0x00F0
+#define NVM_WORD0F_LPLU			0x0001
 
 /* Mask bits for fields in Word 0x1a of the NVM */
-#define NVM_WORD1A_ASPM_MASK  0x000C
+#define NVM_WORD1A_ASPM_MASK		0x000C
 
 /* Mask bits for fields in Word 0x03 of the EEPROM */
-#define NVM_COMPAT_LOM    0x0800
+#define NVM_COMPAT_LOM			0x0800
 
 /* length of string needed to store PBA number */
-#define E1000_PBANUM_LENGTH             11
+#define E1000_PBANUM_LENGTH		11
 
 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
-#define NVM_SUM                    0xBABA
-
-#define NVM_MAC_ADDR_OFFSET        0
-#define NVM_PBA_OFFSET_0           8
-#define NVM_PBA_OFFSET_1           9
-#define NVM_PBA_PTR_GUARD          0xFAFA
-#define NVM_RESERVED_WORD          0xFFFF
-#define NVM_PHY_CLASS_A            0x8000
-#define NVM_SERDES_AMPLITUDE_MASK  0x000F
-#define NVM_SIZE_MASK              0x1C00
-#define NVM_SIZE_SHIFT             10
-#define NVM_WORD_SIZE_BASE_SHIFT   6
-#define NVM_SWDPIO_EXT_SHIFT       4
+#define NVM_SUM				0xBABA
+
+#define NVM_MAC_ADDR_OFFSET		0
+#define NVM_PBA_OFFSET_0		8
+#define NVM_PBA_OFFSET_1		9
+#define NVM_PBA_PTR_GUARD		0xFAFA
+#define NVM_RESERVED_WORD		0xFFFF
+#define NVM_PHY_CLASS_A			0x8000
+#define NVM_SERDES_AMPLITUDE_MASK	0x000F
+#define NVM_SIZE_MASK			0x1C00
+#define NVM_SIZE_SHIFT			10
+#define NVM_WORD_SIZE_BASE_SHIFT	6
+#define NVM_SWDPIO_EXT_SHIFT		4
 
 /* NVM Commands - Microwire */
-#define NVM_READ_OPCODE_MICROWIRE  0x6  /* NVM read opcode */
-#define NVM_WRITE_OPCODE_MICROWIRE 0x5  /* NVM write opcode */
-#define NVM_ERASE_OPCODE_MICROWIRE 0x7  /* NVM erase opcode */
-#define NVM_EWEN_OPCODE_MICROWIRE  0x13 /* NVM erase/write enable */
-#define NVM_EWDS_OPCODE_MICROWIRE  0x10 /* NVM erase/write disable */
+#define NVM_READ_OPCODE_MICROWIRE	0x6  /* NVM read opcode */
+#define NVM_WRITE_OPCODE_MICROWIRE	0x5  /* NVM write opcode */
+#define NVM_ERASE_OPCODE_MICROWIRE	0x7  /* NVM erase opcode */
+#define NVM_EWEN_OPCODE_MICROWIRE	0x13 /* NVM erase/write enable */
+#define NVM_EWDS_OPCODE_MICROWIRE	0x10 /* NVM erase/write disable */
 
 /* NVM Commands - SPI */
-#define NVM_MAX_RETRY_SPI          5000 /* Max wait of 5ms, for RDY signal */
-#define NVM_READ_OPCODE_SPI        0x03 /* NVM read opcode */
-#define NVM_WRITE_OPCODE_SPI       0x02 /* NVM write opcode */
-#define NVM_A8_OPCODE_SPI          0x08 /* opcode bit-3 = address bit-8 */
-#define NVM_WREN_OPCODE_SPI        0x06 /* NVM set Write Enable latch */
-#define NVM_WRDI_OPCODE_SPI        0x04 /* NVM reset Write Enable latch */
-#define NVM_RDSR_OPCODE_SPI        0x05 /* NVM read Status register */
-#define NVM_WRSR_OPCODE_SPI        0x01 /* NVM write Status register */
+#define NVM_MAX_RETRY_SPI	5000 /* Max wait of 5ms, for RDY signal */
+#define NVM_READ_OPCODE_SPI	0x03 /* NVM read opcode */
+#define NVM_WRITE_OPCODE_SPI	0x02 /* NVM write opcode */
+#define NVM_A8_OPCODE_SPI	0x08 /* opcode bit-3 = address bit-8 */
+#define NVM_WREN_OPCODE_SPI	0x06 /* NVM set Write Enable latch */
+#define NVM_WRDI_OPCODE_SPI	0x04 /* NVM reset Write Enable latch */
+#define NVM_RDSR_OPCODE_SPI	0x05 /* NVM read Status register */
+#define NVM_WRSR_OPCODE_SPI	0x01 /* NVM write Status register */
 
 /* SPI NVM Status Register */
-#define NVM_STATUS_RDY_SPI         0x01
-#define NVM_STATUS_WEN_SPI         0x02
-#define NVM_STATUS_BP0_SPI         0x04
-#define NVM_STATUS_BP1_SPI         0x08
-#define NVM_STATUS_WPEN_SPI        0x80
+#define NVM_STATUS_RDY_SPI	0x01
+#define NVM_STATUS_WEN_SPI	0x02
+#define NVM_STATUS_BP0_SPI	0x04
+#define NVM_STATUS_BP1_SPI	0x08
+#define NVM_STATUS_WPEN_SPI	0x80
 
 /* Word definitions for ID LED Settings */
-#define ID_LED_RESERVED_0000 0x0000
-#define ID_LED_RESERVED_FFFF 0xFFFF
-#define ID_LED_DEFAULT       ((ID_LED_OFF1_ON2  << 12) | \
-                              (ID_LED_OFF1_OFF2 <<  8) | \
-                              (ID_LED_DEF1_DEF2 <<  4) | \
-                              (ID_LED_DEF1_DEF2))
-#define ID_LED_DEF1_DEF2     0x1
-#define ID_LED_DEF1_ON2      0x2
-#define ID_LED_DEF1_OFF2     0x3
-#define ID_LED_ON1_DEF2      0x4
-#define ID_LED_ON1_ON2       0x5
-#define ID_LED_ON1_OFF2      0x6
-#define ID_LED_OFF1_DEF2     0x7
-#define ID_LED_OFF1_ON2      0x8
-#define ID_LED_OFF1_OFF2     0x9
-
-#define IGP_ACTIVITY_LED_MASK   0xFFFFF0FF
-#define IGP_ACTIVITY_LED_ENABLE 0x0300
-#define IGP_LED3_MODE           0x07000000
+#define ID_LED_RESERVED_0000	0x0000
+#define ID_LED_RESERVED_FFFF	0xFFFF
+#define ID_LED_DEFAULT		((ID_LED_OFF1_ON2  << 12) | \
+				 (ID_LED_OFF1_OFF2 <<  8) | \
+				 (ID_LED_DEF1_DEF2 <<  4) | \
+				 (ID_LED_DEF1_DEF2))
+#define ID_LED_DEF1_DEF2	0x1
+#define ID_LED_DEF1_ON2		0x2
+#define ID_LED_DEF1_OFF2	0x3
+#define ID_LED_ON1_DEF2		0x4
+#define ID_LED_ON1_ON2		0x5
+#define ID_LED_ON1_OFF2		0x6
+#define ID_LED_OFF1_DEF2	0x7
+#define ID_LED_OFF1_ON2		0x8
+#define ID_LED_OFF1_OFF2	0x9
+
+#define IGP_ACTIVITY_LED_MASK	0xFFFFF0FF
+#define IGP_ACTIVITY_LED_ENABLE	0x0300
+#define IGP_LED3_MODE		0x07000000
 
 /* PCI/PCI-X/PCI-EX Config space */
-#define PCIX_COMMAND_REGISTER        0xE6
-#define PCIX_STATUS_REGISTER_LO      0xE8
-#define PCIX_STATUS_REGISTER_HI      0xEA
-#define PCI_HEADER_TYPE_REGISTER     0x0E
-#define PCIE_LINK_STATUS             0x12
-#define PCIE_DEVICE_CONTROL2         0x28
-
-#define PCIX_COMMAND_MMRBC_MASK      0x000C
-#define PCIX_COMMAND_MMRBC_SHIFT     0x2
-#define PCIX_STATUS_HI_MMRBC_MASK    0x0060
-#define PCIX_STATUS_HI_MMRBC_SHIFT   0x5
-#define PCIX_STATUS_HI_MMRBC_4K      0x3
-#define PCIX_STATUS_HI_MMRBC_2K      0x2
-#define PCIX_STATUS_LO_FUNC_MASK     0x7
-#define PCI_HEADER_TYPE_MULTIFUNC    0x80
-#define PCIE_LINK_WIDTH_MASK         0x3F0
-#define PCIE_LINK_WIDTH_SHIFT        4
-#define PCIE_LINK_SPEED_MASK         0x0F
-#define PCIE_LINK_SPEED_2500         0x01
-#define PCIE_LINK_SPEED_5000         0x02
-#define PCIE_DEVICE_CONTROL2_16ms    0x0005
+#define PCIX_COMMAND_REGISTER		0xE6
+#define PCIX_STATUS_REGISTER_LO		0xE8
+#define PCIX_STATUS_REGISTER_HI		0xEA
+#define PCI_HEADER_TYPE_REGISTER	0x0E
+#define PCIE_LINK_STATUS		0x12
+#define PCIE_DEVICE_CONTROL2		0x28
+
+#define PCIX_COMMAND_MMRBC_MASK		0x000C
+#define PCIX_COMMAND_MMRBC_SHIFT	0x2
+#define PCIX_STATUS_HI_MMRBC_MASK	0x0060
+#define PCIX_STATUS_HI_MMRBC_SHIFT	0x5
+#define PCIX_STATUS_HI_MMRBC_4K		0x3
+#define PCIX_STATUS_HI_MMRBC_2K		0x2
+#define PCIX_STATUS_LO_FUNC_MASK	0x7
+#define PCI_HEADER_TYPE_MULTIFUNC	0x80
+#define PCIE_LINK_WIDTH_MASK		0x3F0
+#define PCIE_LINK_WIDTH_SHIFT		4
+#define PCIE_LINK_SPEED_MASK		0x0F
+#define PCIE_LINK_SPEED_2500		0x01
+#define PCIE_LINK_SPEED_5000		0x02
+#define PCIE_DEVICE_CONTROL2_16ms	0x0005
 
 #ifndef ETH_ADDR_LEN
-#define ETH_ADDR_LEN                 6
+#define ETH_ADDR_LEN			6
 #endif
 
-#define PHY_REVISION_MASK      0xFFFFFFF0
-#define MAX_PHY_REG_ADDRESS    0x1F  /* 5 bit address bus (0-0x1F) */
-#define MAX_PHY_MULTI_PAGE_REG 0xF
+#define PHY_REVISION_MASK		0xFFFFFFF0
+#define MAX_PHY_REG_ADDRESS		0x1F  /* 5 bit address bus (0-0x1F) */
+#define MAX_PHY_MULTI_PAGE_REG		0xF
 
 /* Bit definitions for valid PHY IDs. */
 /*
  * I = Integrated
  * E = External
  */
-#define M88E1000_E_PHY_ID    0x01410C50
-#define M88E1000_I_PHY_ID    0x01410C30
-#define M88E1011_I_PHY_ID    0x01410C20
-#define IGP01E1000_I_PHY_ID  0x02A80380
-#define M88E1011_I_REV_4     0x04
-#define M88E1111_I_PHY_ID    0x01410CC0
-#define M88E1112_E_PHY_ID    0x01410C90
-#define I347AT4_E_PHY_ID     0x01410DC0
-#define M88E1340M_E_PHY_ID   0x01410DF0
-#define GG82563_E_PHY_ID     0x01410CA0
-#define IGP03E1000_E_PHY_ID  0x02A80390
-#define IFE_E_PHY_ID         0x02A80330
-#define IFE_PLUS_E_PHY_ID    0x02A80320
-#define IFE_C_E_PHY_ID       0x02A80310
-#define BME1000_E_PHY_ID     0x01410CB0
-#define BME1000_E_PHY_ID_R2  0x01410CB1
-#define I82577_E_PHY_ID 0x01540050
-#define I82578_E_PHY_ID 0x004DD040
-#define I82579_E_PHY_ID    0x01540090
-#define I82580_I_PHY_ID      0x015403A0
-#define I350_I_PHY_ID        0x015403B0
-#define IGP04E1000_E_PHY_ID  0x02A80391
-#define M88_VENDOR           0x0141
+#define M88E1000_E_PHY_ID	0x01410C50
+#define M88E1000_I_PHY_ID	0x01410C30
+#define M88E1011_I_PHY_ID	0x01410C20
+#define IGP01E1000_I_PHY_ID	0x02A80380
+#define M88E1011_I_REV_4	0x04
+#define M88E1111_I_PHY_ID	0x01410CC0
+#define M88E1112_E_PHY_ID	0x01410C90
+#define I347AT4_E_PHY_ID	0x01410DC0
+#define M88E1340M_E_PHY_ID	0x01410DF0
+#define GG82563_E_PHY_ID	0x01410CA0
+#define IGP03E1000_E_PHY_ID	0x02A80390
+#define IFE_E_PHY_ID		0x02A80330
+#define IFE_PLUS_E_PHY_ID	0x02A80320
+#define IFE_C_E_PHY_ID		0x02A80310
+#define BME1000_E_PHY_ID	0x01410CB0
+#define BME1000_E_PHY_ID_R2	0x01410CB1
+#define I82577_E_PHY_ID		0x01540050
+#define I82578_E_PHY_ID		0x004DD040
+#define I82579_E_PHY_ID		0x01540090
+#define I82580_I_PHY_ID		0x015403A0
+#define I350_I_PHY_ID		0x015403B0
+#define IGP04E1000_E_PHY_ID	0x02A80391
+#define M88_VENDOR		0x0141
 
 /* M88E1000 Specific Registers */
-#define M88E1000_PHY_SPEC_CTRL     0x10  /* PHY Specific Control Register */
-#define M88E1000_PHY_SPEC_STATUS   0x11  /* PHY Specific Status Register */
-#define M88E1000_INT_ENABLE        0x12  /* Interrupt Enable Register */
-#define M88E1000_INT_STATUS        0x13  /* Interrupt Status Register */
-#define M88E1000_EXT_PHY_SPEC_CTRL 0x14  /* Extended PHY Specific Control */
-#define M88E1000_RX_ERR_CNTR       0x15  /* Receive Error Counter */
-
-#define M88E1000_PHY_EXT_CTRL      0x1A  /* PHY extend control register */
-#define M88E1000_PHY_PAGE_SELECT   0x1D  /* Reg 29 for page number setting */
-#define M88E1000_PHY_GEN_CONTROL   0x1E  /* Its meaning depends on reg 29 */
-#define M88E1000_PHY_VCO_REG_BIT8  0x100 /* Bits 8 & 11 are adjusted for */
-#define M88E1000_PHY_VCO_REG_BIT11 0x800    /* improved BER performance */
+#define M88E1000_PHY_SPEC_CTRL		0x10  /* PHY Specific Control Reg */
+#define M88E1000_PHY_SPEC_STATUS	0x11  /* PHY Specific Status Reg */
+#define M88E1000_INT_ENABLE		0x12  /* Interrupt Enable Reg */
+#define M88E1000_INT_STATUS		0x13  /* Interrupt Status Reg */
+#define M88E1000_EXT_PHY_SPEC_CTRL	0x14  /* Extended PHY Specific Cntrl */
+#define M88E1000_RX_ERR_CNTR		0x15  /* Receive Error Counter */
+
+#define M88E1000_PHY_EXT_CTRL		0x1A  /* PHY extend control register */
+#define M88E1000_PHY_PAGE_SELECT	0x1D  /* Reg 29 for pg number setting */
+#define M88E1000_PHY_GEN_CONTROL	0x1E  /* meaning depends on reg 29 */
+#define M88E1000_PHY_VCO_REG_BIT8	0x100 /* Bits 8 & 11 are adjusted for */
+#define M88E1000_PHY_VCO_REG_BIT11	0x800 /* improved BER performance */
 
 /* M88E1000 PHY Specific Control Register */
-#define M88E1000_PSCR_JABBER_DISABLE    0x0001 /* 1=Jabber Function disabled */
-#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */
-#define M88E1000_PSCR_SQE_TEST          0x0004 /* 1=SQE Test enabled */
+#define M88E1000_PSCR_JABBER_DISABLE	0x0001 /* 1=Jabber Function disabled */
+#define M88E1000_PSCR_POLARITY_REVERSAL	0x0002 /* 1=Polarity Reverse enabled */
+#define M88E1000_PSCR_SQE_TEST		0x0004 /* 1=SQE Test enabled */
 /* 1=CLK125 low, 0=CLK125 toggling */
-#define M88E1000_PSCR_CLK125_DISABLE    0x0010
-#define M88E1000_PSCR_MDI_MANUAL_MODE  0x0000 /* MDI Crossover Mode bits 6:5 */
-                                               /* Manual MDI configuration */
-#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020  /* Manual MDIX configuration */
+#define M88E1000_PSCR_CLK125_DISABLE	0x0010
+/* MDI Crossover Mode bits 6:5 Manual MDI configuration */
+#define M88E1000_PSCR_MDI_MANUAL_MODE	0x0000
+#define M88E1000_PSCR_MDIX_MANUAL_MODE	0x0020  /* Manual MDIX configuration */
 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
-#define M88E1000_PSCR_AUTO_X_1000T     0x0040
+#define M88E1000_PSCR_AUTO_X_1000T	0x0040
 /* Auto crossover enabled all speeds */
-#define M88E1000_PSCR_AUTO_X_MODE      0x0060
+#define M88E1000_PSCR_AUTO_X_MODE	0x0060
 /*
  * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
  * 0=Normal 10BASE-T Rx Threshold
  */
-#define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080
+#define M88E1000_PSCR_EN_10BT_EXT_DIST	0x0080
 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
-#define M88E1000_PSCR_MII_5BIT_ENABLE      0x0100
-#define M88E1000_PSCR_SCRAMBLER_DISABLE    0x0200 /* 1=Scrambler disable */
-#define M88E1000_PSCR_FORCE_LINK_GOOD      0x0400 /* 1=Force link good */
-#define M88E1000_PSCR_ASSERT_CRS_ON_TX     0x0800 /* 1=Assert CRS on Tx */
+#define M88E1000_PSCR_MII_5BIT_ENABLE	0x0100
+#define M88E1000_PSCR_SCRAMBLER_DISABLE	0x0200 /* 1=Scrambler disable */
+#define M88E1000_PSCR_FORCE_LINK_GOOD	0x0400 /* 1=Force link good */
+#define M88E1000_PSCR_ASSERT_CRS_ON_TX	0x0800 /* 1=Assert CRS on Tx */
 
 /* M88E1000 PHY Specific Status Register */
-#define M88E1000_PSSR_JABBER             0x0001 /* 1=Jabber */
-#define M88E1000_PSSR_REV_POLARITY       0x0002 /* 1=Polarity reversed */
-#define M88E1000_PSSR_DOWNSHIFT          0x0020 /* 1=Downshifted */
-#define M88E1000_PSSR_MDIX               0x0040 /* 1=MDIX; 0=MDI */
+#define M88E1000_PSSR_JABBER		0x0001 /* 1=Jabber */
+#define M88E1000_PSSR_REV_POLARITY	0x0002 /* 1=Polarity reversed */
+#define M88E1000_PSSR_DOWNSHIFT		0x0020 /* 1=Downshifted */
+#define M88E1000_PSSR_MDIX		0x0040 /* 1=MDIX; 0=MDI */
 /*
  * 0 = <50M
  * 1 = 50-80M
@@ -1546,62 +1578,62 @@
  * 3 = 110-140M
  * 4 = >140M
  */
-#define M88E1000_PSSR_CABLE_LENGTH       0x0380
-#define M88E1000_PSSR_LINK               0x0400 /* 1=Link up, 0=Link down */
-#define M88E1000_PSSR_SPD_DPLX_RESOLVED  0x0800 /* 1=Speed & Duplex resolved */
-#define M88E1000_PSSR_PAGE_RCVD          0x1000 /* 1=Page received */
-#define M88E1000_PSSR_DPLX               0x2000 /* 1=Duplex 0=Half Duplex */
-#define M88E1000_PSSR_SPEED              0xC000 /* Speed, bits 14:15 */
-#define M88E1000_PSSR_10MBS              0x0000 /* 00=10Mbs */
-#define M88E1000_PSSR_100MBS             0x4000 /* 01=100Mbs */
-#define M88E1000_PSSR_1000MBS            0x8000 /* 10=1000Mbs */
-
-#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
+#define M88E1000_PSSR_CABLE_LENGTH	0x0380
+#define M88E1000_PSSR_LINK		0x0400 /* 1=Link up, 0=Link down */
+#define M88E1000_PSSR_SPD_DPLX_RESOLVED	0x0800 /* 1=Speed & Duplex resolved */
+#define M88E1000_PSSR_PAGE_RCVD		0x1000 /* 1=Page received */
+#define M88E1000_PSSR_DPLX		0x2000 /* 1=Duplex 0=Half Duplex */
+#define M88E1000_PSSR_SPEED		0xC000 /* Speed, bits 14:15 */
+#define M88E1000_PSSR_10MBS		0x0000 /* 00=10Mbs */
+#define M88E1000_PSSR_100MBS		0x4000 /* 01=100Mbs */
+#define M88E1000_PSSR_1000MBS		0x8000 /* 10=1000Mbs */
+
+#define M88E1000_PSSR_CABLE_LENGTH_SHIFT	7
 
 /* M88E1000 Extended PHY Specific Control Register */
-#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
+#define M88E1000_EPSCR_FIBER_LOOPBACK	0x4000 /* 1=Fiber loopback */
 /*
  * 1 = Lost lock detect enabled.
  * Will assert lost lock and bring
  * link down if idle not seen
  * within 1ms in 1000BASE-T
  */
-#define M88E1000_EPSCR_DOWN_NO_IDLE   0x8000
+#define M88E1000_EPSCR_DOWN_NO_IDLE	0x8000
 /*
  * Number of times we will attempt to autonegotiate before downshifting if we
  * are the master
  */
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X   0x0400
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X   0x0800
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X   0x0C00
+#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK	0x0C00
+#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X	0x0000
+#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X	0x0400
+#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X	0x0800
+#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X	0x0C00
 /*
  * Number of times we will attempt to autonegotiate before downshifting if we
  * are the slave
  */
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK  0x0300
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS   0x0000
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X    0x0100
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X    0x0200
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X    0x0300
-#define M88E1000_EPSCR_TX_CLK_2_5       0x0060 /* 2.5 MHz TX_CLK */
-#define M88E1000_EPSCR_TX_CLK_25        0x0070 /* 25  MHz TX_CLK */
-#define M88E1000_EPSCR_TX_CLK_0         0x0000 /* NO  TX_CLK */
+#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK	0x0300
+#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS	0x0000
+#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X	0x0100
+#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X	0x0200
+#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X	0x0300
+#define M88E1000_EPSCR_TX_CLK_2_5	0x0060 /* 2.5 MHz TX_CLK */
+#define M88E1000_EPSCR_TX_CLK_25	0x0070 /* 25  MHz TX_CLK */
+#define M88E1000_EPSCR_TX_CLK_0		0x0000 /* NO  TX_CLK */
 
 /* M88E1111 Specific Registers */
-#define M88E1111_PHY_PAGE_SELECT1       0x16  /* for registers 0-28 */
-#define M88E1111_PHY_PAGE_SELECT2       0x1D  /* for registers 30-31 */
+#define M88E1111_PHY_PAGE_SELECT1	0x16  /* for registers 0-28 */
+#define M88E1111_PHY_PAGE_SELECT2	0x1D  /* for registers 30-31 */
 
 /* M88E1111 page select register mask */
-#define M88E1111_PHY_PAGE_SELECT_MASK1  0xFF
-#define M88E1111_PHY_PAGE_SELECT_MASK2  0x3F
+#define M88E1111_PHY_PAGE_SELECT_MASK1	0xFF
+#define M88E1111_PHY_PAGE_SELECT_MASK2	0x3F
 
 /* Intel I347AT4 Registers */
 
-#define I347AT4_PCDL            0x10 /* PHY Cable Diagnostics Length */
-#define I347AT4_PCDC            0x15 /* PHY Cable Diagnostics Control */
-#define I347AT4_PAGE_SELECT     0x16
+#define I347AT4_PCDL		0x10 /* PHY Cable Diagnostics Length */
+#define I347AT4_PCDC		0x15 /* PHY Cable Diagnostics Control */
+#define I347AT4_PAGE_SELECT	0x16
 
 /* I347AT4 Extended PHY Specific Control Register */
 
@@ -1609,213 +1641,220 @@
  * Number of times we will attempt to autonegotiate before downshifting if we
  * are the master
  */
-#define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800
-#define I347AT4_PSCR_DOWNSHIFT_MASK   0x7000
-#define I347AT4_PSCR_DOWNSHIFT_1X     0x0000
-#define I347AT4_PSCR_DOWNSHIFT_2X     0x1000
-#define I347AT4_PSCR_DOWNSHIFT_3X     0x2000
-#define I347AT4_PSCR_DOWNSHIFT_4X     0x3000
-#define I347AT4_PSCR_DOWNSHIFT_5X     0x4000
-#define I347AT4_PSCR_DOWNSHIFT_6X     0x5000
-#define I347AT4_PSCR_DOWNSHIFT_7X     0x6000
-#define I347AT4_PSCR_DOWNSHIFT_8X     0x7000
+#define I347AT4_PSCR_DOWNSHIFT_ENABLE	0x0800
+#define I347AT4_PSCR_DOWNSHIFT_MASK	0x7000
+#define I347AT4_PSCR_DOWNSHIFT_1X	0x0000
+#define I347AT4_PSCR_DOWNSHIFT_2X	0x1000
+#define I347AT4_PSCR_DOWNSHIFT_3X	0x2000
+#define I347AT4_PSCR_DOWNSHIFT_4X	0x3000
+#define I347AT4_PSCR_DOWNSHIFT_5X	0x4000
+#define I347AT4_PSCR_DOWNSHIFT_6X	0x5000
+#define I347AT4_PSCR_DOWNSHIFT_7X	0x6000
+#define I347AT4_PSCR_DOWNSHIFT_8X	0x7000
 
 /* I347AT4 PHY Cable Diagnostics Control */
-#define I347AT4_PCDC_CABLE_LENGTH_UNIT  0x0400 /* 0=cm 1=meters */
+#define I347AT4_PCDC_CABLE_LENGTH_UNIT	0x0400 /* 0=cm 1=meters */
 
 /* M88E1112 only registers */
-#define M88E1112_VCT_DSP_DISTANCE       0x001A
+#define M88E1112_VCT_DSP_DISTANCE	0x001A
 
 /* M88EC018 Rev 2 specific DownShift settings */
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK  0x0E00
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X    0x0000
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X    0x0200
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X    0x0400
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X    0x0600
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X    0x0800
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X    0x0A00
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X    0x0C00
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X    0x0E00
-
-#define I82578_EPSCR_DOWNSHIFT_ENABLE          0x0020
-#define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK    0x001C
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK	0x0E00
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X	0x0000
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X	0x0200
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X	0x0400
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X	0x0600
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X	0x0800
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X	0x0A00
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X	0x0C00
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X	0x0E00
+
+#define I82578_EPSCR_DOWNSHIFT_ENABLE		0x0020
+#define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK	0x001C
 
 /* BME1000 PHY Specific Control Register */
-#define BME1000_PSCR_ENABLE_DOWNSHIFT   0x0800 /* 1 = enable downshift */
+#define BME1000_PSCR_ENABLE_DOWNSHIFT	0x0800 /* 1 = enable downshift */
 
 /*
  * Bits...
  * 15-5: page
  * 4-0: register offset
  */
-#define GG82563_PAGE_SHIFT        5
-#define GG82563_REG(page, reg)    \
-        (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
-#define GG82563_MIN_ALT_REG       30
+#define GG82563_PAGE_SHIFT	5
+#define GG82563_REG(page, reg)	\
+	(((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
+#define GG82563_MIN_ALT_REG	30
 
 /* GG82563 Specific Registers */
-#define GG82563_PHY_SPEC_CTRL           \
-        GG82563_REG(0, 16) /* PHY Specific Control */
-#define GG82563_PHY_SPEC_STATUS         \
-        GG82563_REG(0, 17) /* PHY Specific Status */
-#define GG82563_PHY_INT_ENABLE          \
-        GG82563_REG(0, 18) /* Interrupt Enable */
-#define GG82563_PHY_SPEC_STATUS_2       \
-        GG82563_REG(0, 19) /* PHY Specific Status 2 */
-#define GG82563_PHY_RX_ERR_CNTR         \
-        GG82563_REG(0, 21) /* Receive Error Counter */
-#define GG82563_PHY_PAGE_SELECT         \
-        GG82563_REG(0, 22) /* Page Select */
-#define GG82563_PHY_SPEC_CTRL_2         \
-        GG82563_REG(0, 26) /* PHY Specific Control 2 */
-#define GG82563_PHY_PAGE_SELECT_ALT     \
-        GG82563_REG(0, 29) /* Alternate Page Select */
-#define GG82563_PHY_TEST_CLK_CTRL       \
-        GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
-
-#define GG82563_PHY_MAC_SPEC_CTRL       \
-        GG82563_REG(2, 21) /* MAC Specific Control Register */
-#define GG82563_PHY_MAC_SPEC_CTRL_2     \
-        GG82563_REG(2, 26) /* MAC Specific Control 2 */
-
-#define GG82563_PHY_DSP_DISTANCE    \
-        GG82563_REG(5, 26) /* DSP Distance */
+#define GG82563_PHY_SPEC_CTRL		GG82563_REG(0, 16) /* PHY Spec Cntrl */
+#define GG82563_PHY_SPEC_STATUS		GG82563_REG(0, 17) /* PHY Spec Status */
+#define GG82563_PHY_INT_ENABLE		GG82563_REG(0, 18) /* Interrupt Ena */
+#define GG82563_PHY_SPEC_STATUS_2	GG82563_REG(0, 19) /* PHY Spec Stat2 */
+#define GG82563_PHY_RX_ERR_CNTR		GG82563_REG(0, 21) /* Rx Err Counter */
+#define GG82563_PHY_PAGE_SELECT		GG82563_REG(0, 22) /* Page Select */
+#define GG82563_PHY_SPEC_CTRL_2		GG82563_REG(0, 26) /* PHY Spec Cntrl2 */
+#define GG82563_PHY_PAGE_SELECT_ALT	GG82563_REG(0, 29) /* Alt Page Select */
+/* Test Clock Control (use reg. 29 to select) */
+#define GG82563_PHY_TEST_CLK_CTRL	GG82563_REG(0, 30)
+
+/* MAC Specific Control Register */
+#define GG82563_PHY_MAC_SPEC_CTRL	GG82563_REG(2, 21)
+#define GG82563_PHY_MAC_SPEC_CTRL_2	GG82563_REG(2, 26) /* MAC Spec Ctrl 2 */
+
+#define GG82563_PHY_DSP_DISTANCE	GG82563_REG(5, 26) /* DSP Distance */
 
 /* Page 193 - Port Control Registers */
-#define GG82563_PHY_KMRN_MODE_CTRL   \
-        GG82563_REG(193, 16) /* Kumeran Mode Control */
-#define GG82563_PHY_PORT_RESET          \
-        GG82563_REG(193, 17) /* Port Reset */
-#define GG82563_PHY_REVISION_ID         \
-        GG82563_REG(193, 18) /* Revision ID */
-#define GG82563_PHY_DEVICE_ID           \
-        GG82563_REG(193, 19) /* Device ID */
-#define GG82563_PHY_PWR_MGMT_CTRL       \
-        GG82563_REG(193, 20) /* Power Management Control */
-#define GG82563_PHY_RATE_ADAPT_CTRL     \
-        GG82563_REG(193, 25) /* Rate Adaptation Control */
+/* Kumeran Mode Control */
+#define GG82563_PHY_KMRN_MODE_CTRL	GG82563_REG(193, 16)
+#define GG82563_PHY_PORT_RESET		GG82563_REG(193, 17) /* Port Reset */
+#define GG82563_PHY_REVISION_ID		GG82563_REG(193, 18) /* Revision ID */
+#define GG82563_PHY_DEVICE_ID		GG82563_REG(193, 19) /* Device ID */
+#define GG82563_PHY_PWR_MGMT_CTRL	GG82563_REG(193, 20) /* Pwr Mgt Ctrl */
+/* Rate Adaptation Control */
+#define GG82563_PHY_RATE_ADAPT_CTRL	GG82563_REG(193, 25)
 
 /* Page 194 - KMRN Registers */
-#define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
-        GG82563_REG(194, 16) /* FIFO's Control/Status */
-#define GG82563_PHY_KMRN_CTRL           \
-        GG82563_REG(194, 17) /* Control */
-#define GG82563_PHY_INBAND_CTRL         \
-        GG82563_REG(194, 18) /* Inband Control */
-#define GG82563_PHY_KMRN_DIAGNOSTIC     \
-        GG82563_REG(194, 19) /* Diagnostic */
-#define GG82563_PHY_ACK_TIMEOUTS        \
-        GG82563_REG(194, 20) /* Acknowledge Timeouts */
-#define GG82563_PHY_ADV_ABILITY         \
-        GG82563_REG(194, 21) /* Advertised Ability */
-#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
-        GG82563_REG(194, 23) /* Link Partner Advertised Ability */
-#define GG82563_PHY_ADV_NEXT_PAGE       \
-        GG82563_REG(194, 24) /* Advertised Next Page */
-#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
-        GG82563_REG(194, 25) /* Link Partner Advertised Next page */
-#define GG82563_PHY_KMRN_MISC           \
-        GG82563_REG(194, 26) /* Misc. */
+/* FIFO's Control/Status */
+#define GG82563_PHY_KMRN_FIFO_CTRL_STAT	GG82563_REG(194, 16)
+#define GG82563_PHY_KMRN_CTRL		GG82563_REG(194, 17) /* Control */
+#define GG82563_PHY_INBAND_CTRL		GG82563_REG(194, 18) /* Inband Ctrl */
+#define GG82563_PHY_KMRN_DIAGNOSTIC	GG82563_REG(194, 19) /* Diagnostic */
+#define GG82563_PHY_ACK_TIMEOUTS	GG82563_REG(194, 20) /* Ack Timeouts */
+#define GG82563_PHY_ADV_ABILITY		GG82563_REG(194, 21) /* Adver Ability */
+/* Link Partner Advertised Ability */
+#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY	GG82563_REG(194, 23)
+#define GG82563_PHY_ADV_NEXT_PAGE	GG82563_REG(194, 24) /* Adver Next Pg */
+/* Link Partner Advertised Next page */
+#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE	GG82563_REG(194, 25)
+#define GG82563_PHY_KMRN_MISC		GG82563_REG(194, 26) /* Misc. */
 
 /* MDI Control */
-#define E1000_MDIC_DATA_MASK 0x0000FFFF
-#define E1000_MDIC_REG_MASK  0x001F0000
-#define E1000_MDIC_REG_SHIFT 16
-#define E1000_MDIC_PHY_MASK  0x03E00000
-#define E1000_MDIC_PHY_SHIFT 21
-#define E1000_MDIC_OP_WRITE  0x04000000
-#define E1000_MDIC_OP_READ   0x08000000
-#define E1000_MDIC_READY     0x10000000
-#define E1000_MDIC_INT_EN    0x20000000
-#define E1000_MDIC_ERROR     0x40000000
-#define E1000_MDIC_DEST      0x80000000
+#define E1000_MDIC_DATA_MASK	0x0000FFFF
+#define E1000_MDIC_REG_MASK	0x001F0000
+#define E1000_MDIC_REG_SHIFT	16
+#define E1000_MDIC_PHY_MASK	0x03E00000
+#define E1000_MDIC_PHY_SHIFT	21
+#define E1000_MDIC_OP_WRITE	0x04000000
+#define E1000_MDIC_OP_READ	0x08000000
+#define E1000_MDIC_READY	0x10000000
+#define E1000_MDIC_INT_EN	0x20000000
+#define E1000_MDIC_ERROR	0x40000000
+#define E1000_MDIC_DEST		0x80000000
 
 /* SerDes Control */
-#define E1000_GEN_CTL_READY             0x80000000
-#define E1000_GEN_CTL_ADDRESS_SHIFT     8
-#define E1000_GEN_POLL_TIMEOUT          640
+#define E1000_GEN_CTL_READY		0x80000000
+#define E1000_GEN_CTL_ADDRESS_SHIFT	8
+#define E1000_GEN_POLL_TIMEOUT		640
 
 /* LinkSec register fields */
-#define E1000_LSECTXCAP_SUM_MASK        0x00FF0000
-#define E1000_LSECTXCAP_SUM_SHIFT       16
-#define E1000_LSECRXCAP_SUM_MASK        0x00FF0000
-#define E1000_LSECRXCAP_SUM_SHIFT       16
-
-#define E1000_LSECTXCTRL_EN_MASK        0x00000003
-#define E1000_LSECTXCTRL_DISABLE        0x0
-#define E1000_LSECTXCTRL_AUTH           0x1
-#define E1000_LSECTXCTRL_AUTH_ENCRYPT   0x2
-#define E1000_LSECTXCTRL_AISCI          0x00000020
-#define E1000_LSECTXCTRL_PNTHRSH_MASK   0xFFFFFF00
-#define E1000_LSECTXCTRL_RSV_MASK       0x000000D8
-
-#define E1000_LSECRXCTRL_EN_MASK        0x0000000C
-#define E1000_LSECRXCTRL_EN_SHIFT       2
-#define E1000_LSECRXCTRL_DISABLE        0x0
-#define E1000_LSECRXCTRL_CHECK          0x1
-#define E1000_LSECRXCTRL_STRICT         0x2
-#define E1000_LSECRXCTRL_DROP           0x3
-#define E1000_LSECRXCTRL_PLSH           0x00000040
-#define E1000_LSECRXCTRL_RP             0x00000080
-#define E1000_LSECRXCTRL_RSV_MASK       0xFFFFFF33
+#define E1000_LSECTXCAP_SUM_MASK	0x00FF0000
+#define E1000_LSECTXCAP_SUM_SHIFT	16
+#define E1000_LSECRXCAP_SUM_MASK	0x00FF0000
+#define E1000_LSECRXCAP_SUM_SHIFT	16
+
+#define E1000_LSECTXCTRL_EN_MASK	0x00000003
+#define E1000_LSECTXCTRL_DISABLE	0x0
+#define E1000_LSECTXCTRL_AUTH		0x1
+#define E1000_LSECTXCTRL_AUTH_ENCRYPT	0x2
+#define E1000_LSECTXCTRL_AISCI		0x00000020
+#define E1000_LSECTXCTRL_PNTHRSH_MASK	0xFFFFFF00
+#define E1000_LSECTXCTRL_RSV_MASK	0x000000D8
+
+#define E1000_LSECRXCTRL_EN_MASK	0x0000000C
+#define E1000_LSECRXCTRL_EN_SHIFT	2
+#define E1000_LSECRXCTRL_DISABLE	0x0
+#define E1000_LSECRXCTRL_CHECK		0x1
+#define E1000_LSECRXCTRL_STRICT		0x2
+#define E1000_LSECRXCTRL_DROP		0x3
+#define E1000_LSECRXCTRL_PLSH		0x00000040
+#define E1000_LSECRXCTRL_RP		0x00000080
+#define E1000_LSECRXCTRL_RSV_MASK	0xFFFFFF33
 
 /* Tx Rate-Scheduler Config fields */
 #define E1000_RTTBCNRC_RS_ENA		0x80000000
 #define E1000_RTTBCNRC_RF_DEC_MASK	0x00003FFF
-#define E1000_RTTBCNRC_RF_INT_SHIFT     14
+#define E1000_RTTBCNRC_RF_INT_SHIFT	14
 #define E1000_RTTBCNRC_RF_INT_MASK	\
 	(E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT)
 
 /* DMA Coalescing register fields */
-#define E1000_DMACR_DMACWT_MASK         0x00003FFF /* DMA Coalescing
-                                                    * Watchdog Timer */
-#define E1000_DMACR_DMACTHR_MASK        0x00FF0000 /* DMA Coalescing Rx
-                                                    * Threshold */
-#define E1000_DMACR_DMACTHR_SHIFT       16
-#define E1000_DMACR_DMAC_LX_MASK        0x30000000 /* Lx when no PCIe
-                                                    * transactions */
-#define E1000_DMACR_DMAC_LX_SHIFT       28
-#define E1000_DMACR_DMAC_EN             0x80000000 /* Enable DMA Coalescing */
-
-#define E1000_DMCTXTH_DMCTTHR_MASK      0x00000FFF /* DMA Coalescing Transmit
-                                                    * Threshold */
-
-#define E1000_DMCTLX_TTLX_MASK          0x00000FFF /* Time to LX request */
-
-#define E1000_DMCRTRH_UTRESH_MASK       0x0007FFFF /* Rx Traffic Rate
-                                                    * Threshold */
-#define E1000_DMCRTRH_LRPRCW            0x80000000 /* Rx packet rate in
-                                                    * current window */
-
-#define E1000_DMCCNT_CCOUNT_MASK        0x01FFFFFF /* DMA Coal Rx Traffic
-                                                    * Current Cnt */
-
-#define E1000_FCRTC_RTH_COAL_MASK       0x0003FFF0 /* Flow ctrl Rx Threshold
-                                                    * High val */
-#define E1000_FCRTC_RTH_COAL_SHIFT      4
-#define E1000_PCIEMISC_LX_DECISION      0x00000080 /* Lx power decision based
-                                                      on DMA coal */
+/* DMA Coalescing Watchdog Timer */
+#define E1000_DMACR_DMACWT_MASK		0x00003FFF
+/* DMA Coalescing Rx Threshold */
+#define E1000_DMACR_DMACTHR_MASK	0x00FF0000
+#define E1000_DMACR_DMACTHR_SHIFT	16
+/* Lx when no PCIe transactions */
+#define E1000_DMACR_DMAC_LX_MASK	0x30000000
+#define E1000_DMACR_DMAC_LX_SHIFT	28
+#define E1000_DMACR_DMAC_EN		0x80000000 /* Enable DMA Coalescing */
+
+/* DMA Coalescing Transmit Threshold */
+#define E1000_DMCTXTH_DMCTTHR_MASK	0x00000FFF
+
+#define E1000_DMCTLX_TTLX_MASK		0x00000FFF /* Time to LX request */
+
+/* Rx Traffic Rate Threshold */
+#define E1000_DMCRTRH_UTRESH_MASK	0x0007FFFF
+/* Rx packet rate in current window */
+#define E1000_DMCRTRH_LRPRCW		0x80000000
+
+/* DMA Coal Rx Traffic Current Count */
+#define E1000_DMCCNT_CCOUNT_MASK	0x01FFFFFF
+
+/* Flow ctrl Rx Threshold High val */
+#define E1000_FCRTC_RTH_COAL_MASK	0x0003FFF0
+#define E1000_FCRTC_RTH_COAL_SHIFT	4
+/* Lx power decision based on DMA coal */
+#define E1000_PCIEMISC_LX_DECISION	0x00000080
+
+#define E1000_LTRC_EEEMS_EN		0x00000005 /* Enable EEE LTR max send */
+#define E1000_RXPBS_SIZE_I210_MASK	0x0000003F /* Rx packet buffer size */
+/* Minimum time for 1000BASE-T where no data will be transmit following move out
+ * of EEE LPI Tx state
+ */
+#define E1000_TW_SYSTEM_1000_MASK	0x000000FF
+/* Minimum time for 100BASE-T where no data will be transmit following move out
+ * of EEE LPI Tx state
+ */
+#define E1000_TW_SYSTEM_100_MASK	0x0000FF00
+#define E1000_TW_SYSTEM_100_SHIFT	8
+#define E1000_LTRMINV_LTRV_MASK		0x000003FF /* LTR minimum value */
+#define E1000_LTRMAXV_LTRV_MASK		0x000003FF /* LTR maximum value */
+#define E1000_LTRMINV_SCALE_MASK	0x00001C00 /* LTR minimum scale */
+#define E1000_LTRMINV_SCALE_SHIFT	10
+/* Reg val to set scale to 1024 nsec */
+#define E1000_LTRMINV_SCALE_1024	2
+/* Reg val to set scale to 32768 nsec */
+#define E1000_LTRMINV_SCALE_32768	3
+#define E1000_LTRMAXV_SCALE_MASK	0x00001C00 /* LTR maximum scale */
+#define E1000_LTRMAXV_SCALE_SHIFT	10
+/* Reg val to set scale to 1024 nsec */
+#define E1000_LTRMAXV_SCALE_1024	2
+/* Reg val to set scale to 32768 nsec */
+#define E1000_LTRMAXV_SCALE_32768	3
+#define E1000_DOBFFCTL_OBFFTHR_MASK	0x000000FF /* OBFF threshold */
+#define E1000_DOBFFCTL_EXIT_ACT_MASK	0x01000000 /* Exit active CB */
 
 /* Proxy Filer Control */
-#define E1000_PROXYFC_D0               0x00000001  /* Enable offload in D0 */
-#define E1000_PROXYFC_EX               0x00000004  /* Directed exact proxy */
-#define E1000_PROXYFC_MC               0x00000008  /* Directed Multicast
-                                                    * Proxy */
-#define E1000_PROXYFC_BC               0x00000010  /* Broadcast Proxy Enable */
-#define E1000_PROXYFC_ARP_DIRECTED     0x00000020  /* Directed ARP Proxy
-                                                    * Enable */
-#define E1000_PROXYFC_IPV4             0x00000040  /* Directed IPv4 Enable */
-#define E1000_PROXYFC_IPV6             0x00000080  /* Directed IPv6 Enable */
-#define E1000_PROXYFC_NS               0x00000200  /* IPv4 Neighborhood
-                                                    * Solicitation */
-#define E1000_PROXYFC_ARP              0x00000800  /* ARP Request Proxy
-                                                    * Enable */
+#define E1000_PROXYFC_D0		0x00000001 /* Enable offload in D0 */
+#define E1000_PROXYFC_EX		0x00000004 /* Directed exact proxy */
+#define E1000_PROXYFC_MC		0x00000008 /* Directed MC Proxy */
+#define E1000_PROXYFC_BC		0x00000010 /* Broadcast Proxy Enable */
+#define E1000_PROXYFC_ARP_DIRECTED	0x00000020 /* Directed ARP Proxy Ena */
+#define E1000_PROXYFC_IPV4		0x00000040 /* Directed IPv4 Enable */
+#define E1000_PROXYFC_IPV6		0x00000080 /* Directed IPv6 Enable */
+#define E1000_PROXYFC_NS		0x00000200 /* IPv4 NBRHD Solicitation */
+#define E1000_PROXYFC_ARP		0x00000800 /* ARP Request Proxy Ena */
 /* Proxy Status */
-#define E1000_PROXYS_CLEAR             0xFFFFFFFF  /* Clear */
+#define E1000_PROXYS_CLEAR		0xFFFFFFFF /* Clear */
 
 /* Firmware Status */
-#define E1000_FWSTS_FWRI               0x80000000 /* Firmware Reset
-                                                   * Indication */
-
-
+#define E1000_FWSTS_FWRI		0x80000000 /* FW Reset Indication */
+/* VF Control */
+#define E1000_VTCTRL_RST		0x04000000 /* Reset VF */
+
+#define E1000_STATUS_LAN_ID_MASK	0x00000000C /* Mask for Lan ID field */
+/* Lan ID bit field offset in status register */
+#define E1000_STATUS_LAN_ID_OFFSET	2
+#define E1000_VFTA_ENTRIES		128
 #endif /* _E1000_DEFINES_H_ */
diff --git a/sys/dev/e1000/e1000_hw.h b/sys/dev/e1000/e1000_hw.h
index 686a5d8..16cfa8f 100644
--- a/sys/dev/e1000/e1000_hw.h
+++ b/sys/dev/e1000/e1000_hw.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -41,139 +41,138 @@
 
 struct e1000_hw;
 
-#define E1000_DEV_ID_82542                    0x1000
-#define E1000_DEV_ID_82543GC_FIBER            0x1001
-#define E1000_DEV_ID_82543GC_COPPER           0x1004
-#define E1000_DEV_ID_82544EI_COPPER           0x1008
-#define E1000_DEV_ID_82544EI_FIBER            0x1009
-#define E1000_DEV_ID_82544GC_COPPER           0x100C
-#define E1000_DEV_ID_82544GC_LOM              0x100D
-#define E1000_DEV_ID_82540EM                  0x100E
-#define E1000_DEV_ID_82540EM_LOM              0x1015
-#define E1000_DEV_ID_82540EP_LOM              0x1016
-#define E1000_DEV_ID_82540EP                  0x1017
-#define E1000_DEV_ID_82540EP_LP               0x101E
-#define E1000_DEV_ID_82545EM_COPPER           0x100F
-#define E1000_DEV_ID_82545EM_FIBER            0x1011
-#define E1000_DEV_ID_82545GM_COPPER           0x1026
-#define E1000_DEV_ID_82545GM_FIBER            0x1027
-#define E1000_DEV_ID_82545GM_SERDES           0x1028
-#define E1000_DEV_ID_82546EB_COPPER           0x1010
-#define E1000_DEV_ID_82546EB_FIBER            0x1012
-#define E1000_DEV_ID_82546EB_QUAD_COPPER      0x101D
-#define E1000_DEV_ID_82546GB_COPPER           0x1079
-#define E1000_DEV_ID_82546GB_FIBER            0x107A
-#define E1000_DEV_ID_82546GB_SERDES           0x107B
-#define E1000_DEV_ID_82546GB_PCIE             0x108A
-#define E1000_DEV_ID_82546GB_QUAD_COPPER      0x1099
-#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
-#define E1000_DEV_ID_82541EI                  0x1013
-#define E1000_DEV_ID_82541EI_MOBILE           0x1018
-#define E1000_DEV_ID_82541ER_LOM              0x1014
-#define E1000_DEV_ID_82541ER                  0x1078
-#define E1000_DEV_ID_82541GI                  0x1076
-#define E1000_DEV_ID_82541GI_LF               0x107C
-#define E1000_DEV_ID_82541GI_MOBILE           0x1077
-#define E1000_DEV_ID_82547EI                  0x1019
-#define E1000_DEV_ID_82547EI_MOBILE           0x101A
-#define E1000_DEV_ID_82547GI                  0x1075
-#define E1000_DEV_ID_82571EB_COPPER           0x105E
-#define E1000_DEV_ID_82571EB_FIBER            0x105F
-#define E1000_DEV_ID_82571EB_SERDES           0x1060
-#define E1000_DEV_ID_82571EB_SERDES_DUAL      0x10D9
-#define E1000_DEV_ID_82571EB_SERDES_QUAD      0x10DA
-#define E1000_DEV_ID_82571EB_QUAD_COPPER      0x10A4
-#define E1000_DEV_ID_82571PT_QUAD_COPPER      0x10D5
-#define E1000_DEV_ID_82571EB_QUAD_FIBER       0x10A5
-#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP   0x10BC
-#define E1000_DEV_ID_82572EI_COPPER           0x107D
-#define E1000_DEV_ID_82572EI_FIBER            0x107E
-#define E1000_DEV_ID_82572EI_SERDES           0x107F
-#define E1000_DEV_ID_82572EI                  0x10B9
-#define E1000_DEV_ID_82573E                   0x108B
-#define E1000_DEV_ID_82573E_IAMT              0x108C
-#define E1000_DEV_ID_82573L                   0x109A
-#define E1000_DEV_ID_82574L                   0x10D3
-#define E1000_DEV_ID_82574LA                  0x10F6
-#define E1000_DEV_ID_82583V                   0x150C
-#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT   0x1096
-#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT   0x1098
-#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT   0x10BA
-#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT   0x10BB
-#define E1000_DEV_ID_ICH8_82567V_3            0x1501
-#define E1000_DEV_ID_ICH8_IGP_M_AMT           0x1049
-#define E1000_DEV_ID_ICH8_IGP_AMT             0x104A
-#define E1000_DEV_ID_ICH8_IGP_C               0x104B
-#define E1000_DEV_ID_ICH8_IFE                 0x104C
-#define E1000_DEV_ID_ICH8_IFE_GT              0x10C4
-#define E1000_DEV_ID_ICH8_IFE_G               0x10C5
-#define E1000_DEV_ID_ICH8_IGP_M               0x104D
-#define E1000_DEV_ID_ICH9_IGP_M               0x10BF
-#define E1000_DEV_ID_ICH9_IGP_M_AMT           0x10F5
-#define E1000_DEV_ID_ICH9_IGP_M_V             0x10CB
-#define E1000_DEV_ID_ICH9_IGP_AMT             0x10BD
-#define E1000_DEV_ID_ICH9_BM                  0x10E5
-#define E1000_DEV_ID_ICH9_IGP_C               0x294C
-#define E1000_DEV_ID_ICH9_IFE                 0x10C0
-#define E1000_DEV_ID_ICH9_IFE_GT              0x10C3
-#define E1000_DEV_ID_ICH9_IFE_G               0x10C2
-#define E1000_DEV_ID_ICH10_R_BM_LM            0x10CC
-#define E1000_DEV_ID_ICH10_R_BM_LF            0x10CD
-#define E1000_DEV_ID_ICH10_R_BM_V             0x10CE
-#define E1000_DEV_ID_ICH10_HANKSVILLE         0xF0FE
-#define E1000_DEV_ID_ICH10_D_BM_LM            0x10DE
-#define E1000_DEV_ID_ICH10_D_BM_LF            0x10DF
-#define E1000_DEV_ID_ICH10_D_BM_V             0x1525
-
-#define E1000_DEV_ID_PCH_M_HV_LM              0x10EA
-#define E1000_DEV_ID_PCH_M_HV_LC              0x10EB
-#define E1000_DEV_ID_PCH_D_HV_DM              0x10EF
-#define E1000_DEV_ID_PCH_D_HV_DC              0x10F0
-#define E1000_DEV_ID_PCH2_LV_LM               0x1502
-#define E1000_DEV_ID_PCH2_LV_V                0x1503
-#define E1000_DEV_ID_82576                    0x10C9
-#define E1000_DEV_ID_82576_FIBER              0x10E6
-#define E1000_DEV_ID_82576_SERDES             0x10E7
-#define E1000_DEV_ID_82576_QUAD_COPPER        0x10E8
-#define E1000_DEV_ID_82576_QUAD_COPPER_ET2    0x1526
-#define E1000_DEV_ID_82576_NS                 0x150A
-#define E1000_DEV_ID_82576_NS_SERDES          0x1518
-#define E1000_DEV_ID_82576_SERDES_QUAD        0x150D
-#define E1000_DEV_ID_82576_VF                 0x10CA
-#define E1000_DEV_ID_I350_VF                  0x1520
-#define E1000_DEV_ID_82575EB_COPPER           0x10A7
-#define E1000_DEV_ID_82575EB_FIBER_SERDES     0x10A9
-#define E1000_DEV_ID_82575GB_QUAD_COPPER      0x10D6
-#define E1000_DEV_ID_82575GB_QUAD_COPPER_PM   0x10E2
-#define E1000_DEV_ID_82580_COPPER             0x150E
-#define E1000_DEV_ID_82580_FIBER              0x150F
-#define E1000_DEV_ID_82580_SERDES             0x1510
-#define E1000_DEV_ID_82580_SGMII              0x1511
-#define E1000_DEV_ID_82580_COPPER_DUAL        0x1516
-#define E1000_DEV_ID_82580_QUAD_FIBER         0x1527
-#define E1000_DEV_ID_I350_COPPER              0x1521
-#define E1000_DEV_ID_I350_FIBER               0x1522
-#define E1000_DEV_ID_I350_SERDES              0x1523
-#define E1000_DEV_ID_I350_SGMII               0x1524
-#define E1000_DEV_ID_DH89XXCC_SGMII           0x0438
-#define E1000_DEV_ID_DH89XXCC_SERDES          0x043A
-#define E1000_DEV_ID_DH89XXCC_BACKPLANE       0x043C
-#define E1000_DEV_ID_DH89XXCC_SFP             0x0440
-#define E1000_REVISION_0 0
-#define E1000_REVISION_1 1
-#define E1000_REVISION_2 2
-#define E1000_REVISION_3 3
-#define E1000_REVISION_4 4
-
-#define E1000_FUNC_0     0
-#define E1000_FUNC_1     1
-#define E1000_FUNC_2     2
-#define E1000_FUNC_3     3
-
-#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
-#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
-#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2   6
-#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3   9
+#define E1000_DEV_ID_82542			0x1000
+#define E1000_DEV_ID_82543GC_FIBER		0x1001
+#define E1000_DEV_ID_82543GC_COPPER		0x1004
+#define E1000_DEV_ID_82544EI_COPPER		0x1008
+#define E1000_DEV_ID_82544EI_FIBER		0x1009
+#define E1000_DEV_ID_82544GC_COPPER		0x100C
+#define E1000_DEV_ID_82544GC_LOM		0x100D
+#define E1000_DEV_ID_82540EM			0x100E
+#define E1000_DEV_ID_82540EM_LOM		0x1015
+#define E1000_DEV_ID_82540EP_LOM		0x1016
+#define E1000_DEV_ID_82540EP			0x1017
+#define E1000_DEV_ID_82540EP_LP			0x101E
+#define E1000_DEV_ID_82545EM_COPPER		0x100F
+#define E1000_DEV_ID_82545EM_FIBER		0x1011
+#define E1000_DEV_ID_82545GM_COPPER		0x1026
+#define E1000_DEV_ID_82545GM_FIBER		0x1027
+#define E1000_DEV_ID_82545GM_SERDES		0x1028
+#define E1000_DEV_ID_82546EB_COPPER		0x1010
+#define E1000_DEV_ID_82546EB_FIBER		0x1012
+#define E1000_DEV_ID_82546EB_QUAD_COPPER	0x101D
+#define E1000_DEV_ID_82546GB_COPPER		0x1079
+#define E1000_DEV_ID_82546GB_FIBER		0x107A
+#define E1000_DEV_ID_82546GB_SERDES		0x107B
+#define E1000_DEV_ID_82546GB_PCIE		0x108A
+#define E1000_DEV_ID_82546GB_QUAD_COPPER	0x1099
+#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3	0x10B5
+#define E1000_DEV_ID_82541EI			0x1013
+#define E1000_DEV_ID_82541EI_MOBILE		0x1018
+#define E1000_DEV_ID_82541ER_LOM		0x1014
+#define E1000_DEV_ID_82541ER			0x1078
+#define E1000_DEV_ID_82541GI			0x1076
+#define E1000_DEV_ID_82541GI_LF			0x107C
+#define E1000_DEV_ID_82541GI_MOBILE		0x1077
+#define E1000_DEV_ID_82547EI			0x1019
+#define E1000_DEV_ID_82547EI_MOBILE		0x101A
+#define E1000_DEV_ID_82547GI			0x1075
+#define E1000_DEV_ID_82571EB_COPPER		0x105E
+#define E1000_DEV_ID_82571EB_FIBER		0x105F
+#define E1000_DEV_ID_82571EB_SERDES		0x1060
+#define E1000_DEV_ID_82571EB_SERDES_DUAL	0x10D9
+#define E1000_DEV_ID_82571EB_SERDES_QUAD	0x10DA
+#define E1000_DEV_ID_82571EB_QUAD_COPPER	0x10A4
+#define E1000_DEV_ID_82571PT_QUAD_COPPER	0x10D5
+#define E1000_DEV_ID_82571EB_QUAD_FIBER		0x10A5
+#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP	0x10BC
+#define E1000_DEV_ID_82572EI_COPPER		0x107D
+#define E1000_DEV_ID_82572EI_FIBER		0x107E
+#define E1000_DEV_ID_82572EI_SERDES		0x107F
+#define E1000_DEV_ID_82572EI			0x10B9
+#define E1000_DEV_ID_82573E			0x108B
+#define E1000_DEV_ID_82573E_IAMT		0x108C
+#define E1000_DEV_ID_82573L			0x109A
+#define E1000_DEV_ID_82574L			0x10D3
+#define E1000_DEV_ID_82574LA			0x10F6
+#define E1000_DEV_ID_82583V			0x150C
+#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT	0x1096
+#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT	0x1098
+#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT	0x10BA
+#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT	0x10BB
+#define E1000_DEV_ID_ICH8_82567V_3		0x1501
+#define E1000_DEV_ID_ICH8_IGP_M_AMT		0x1049
+#define E1000_DEV_ID_ICH8_IGP_AMT		0x104A
+#define E1000_DEV_ID_ICH8_IGP_C			0x104B
+#define E1000_DEV_ID_ICH8_IFE			0x104C
+#define E1000_DEV_ID_ICH8_IFE_GT		0x10C4
+#define E1000_DEV_ID_ICH8_IFE_G			0x10C5
+#define E1000_DEV_ID_ICH8_IGP_M			0x104D
+#define E1000_DEV_ID_ICH9_IGP_M			0x10BF
+#define E1000_DEV_ID_ICH9_IGP_M_AMT		0x10F5
+#define E1000_DEV_ID_ICH9_IGP_M_V		0x10CB
+#define E1000_DEV_ID_ICH9_IGP_AMT		0x10BD
+#define E1000_DEV_ID_ICH9_BM			0x10E5
+#define E1000_DEV_ID_ICH9_IGP_C			0x294C
+#define E1000_DEV_ID_ICH9_IFE			0x10C0
+#define E1000_DEV_ID_ICH9_IFE_GT		0x10C3
+#define E1000_DEV_ID_ICH9_IFE_G			0x10C2
+#define E1000_DEV_ID_ICH10_R_BM_LM		0x10CC
+#define E1000_DEV_ID_ICH10_R_BM_LF		0x10CD
+#define E1000_DEV_ID_ICH10_R_BM_V		0x10CE
+#define E1000_DEV_ID_ICH10_D_BM_LM		0x10DE
+#define E1000_DEV_ID_ICH10_D_BM_LF		0x10DF
+#define E1000_DEV_ID_ICH10_D_BM_V		0x1525
+
+#define E1000_DEV_ID_PCH_M_HV_LM		0x10EA
+#define E1000_DEV_ID_PCH_M_HV_LC		0x10EB
+#define E1000_DEV_ID_PCH_D_HV_DM		0x10EF
+#define E1000_DEV_ID_PCH_D_HV_DC		0x10F0
+#define E1000_DEV_ID_PCH2_LV_LM			0x1502
+#define E1000_DEV_ID_PCH2_LV_V			0x1503
+#define E1000_DEV_ID_82576			0x10C9
+#define E1000_DEV_ID_82576_FIBER		0x10E6
+#define E1000_DEV_ID_82576_SERDES		0x10E7
+#define E1000_DEV_ID_82576_QUAD_COPPER		0x10E8
+#define E1000_DEV_ID_82576_QUAD_COPPER_ET2	0x1526
+#define E1000_DEV_ID_82576_NS			0x150A
+#define E1000_DEV_ID_82576_NS_SERDES		0x1518
+#define E1000_DEV_ID_82576_SERDES_QUAD		0x150D
+#define E1000_DEV_ID_82576_VF			0x10CA
+#define E1000_DEV_ID_I350_VF			0x1520
+#define E1000_DEV_ID_82575EB_COPPER		0x10A7
+#define E1000_DEV_ID_82575EB_FIBER_SERDES	0x10A9
+#define E1000_DEV_ID_82575GB_QUAD_COPPER	0x10D6
+#define E1000_DEV_ID_82580_COPPER		0x150E
+#define E1000_DEV_ID_82580_FIBER		0x150F
+#define E1000_DEV_ID_82580_SERDES		0x1510
+#define E1000_DEV_ID_82580_SGMII		0x1511
+#define E1000_DEV_ID_82580_COPPER_DUAL		0x1516
+#define E1000_DEV_ID_82580_QUAD_FIBER		0x1527
+#define E1000_DEV_ID_I350_COPPER		0x1521
+#define E1000_DEV_ID_I350_FIBER			0x1522
+#define E1000_DEV_ID_I350_SERDES		0x1523
+#define E1000_DEV_ID_I350_SGMII			0x1524
+#define E1000_DEV_ID_I350_DA4			0x1546
+#define E1000_DEV_ID_DH89XXCC_SGMII		0x0438
+#define E1000_DEV_ID_DH89XXCC_SERDES		0x043A
+#define E1000_DEV_ID_DH89XXCC_BACKPLANE		0x043C
+#define E1000_DEV_ID_DH89XXCC_SFP		0x0440
+#define E1000_REVISION_0	0
+#define E1000_REVISION_1	1
+#define E1000_REVISION_2	2
+#define E1000_REVISION_3	3
+#define E1000_REVISION_4	4
+
+#define E1000_FUNC_0		0
+#define E1000_FUNC_1		1
+#define E1000_FUNC_2		2
+#define E1000_FUNC_3		3
+
+#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0	0
+#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1	3
+#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2	6
+#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3	9
 
 enum e1000_mac_type {
 	e1000_undefined = 0,
@@ -342,9 +341,9 @@ enum e1000_serdes_link_state {
 struct e1000_rx_desc {
 	__le64 buffer_addr; /* Address of the descriptor's data buffer */
 	__le16 length;      /* Length of data DMAed into data buffer */
-	__le16 csum;        /* Packet checksum */
-	u8  status;         /* Descriptor status */
-	u8  errors;         /* Descriptor Errors */
+	__le16 csum; /* Packet checksum */
+	u8  status;  /* Descriptor status */
+	u8  errors;  /* Descriptor Errors */
 	__le16 special;
 };
 
@@ -356,9 +355,9 @@ union e1000_rx_desc_extended {
 	} read;
 	struct {
 		struct {
-			__le32 mrq;           /* Multiple Rx Queues */
+			__le32 mrq; /* Multiple Rx Queues */
 			union {
-				__le32 rss;         /* RSS Hash */
+				__le32 rss; /* RSS Hash */
 				struct {
 					__le16 ip_id;  /* IP id */
 					__le16 csum;   /* Packet Checksum */
@@ -368,7 +367,7 @@ union e1000_rx_desc_extended {
 		struct {
 			__le32 status_error;  /* ext status/error */
 			__le16 length;
-			__le16 vlan;          /* VLAN tag */
+			__le16 vlan; /* VLAN tag */
 		} upper;
 	} wb;  /* writeback */
 };
@@ -382,9 +381,9 @@ union e1000_rx_desc_packet_split {
 	} read;
 	struct {
 		struct {
-			__le32 mrq;           /* Multiple Rx Queues */
+			__le32 mrq;  /* Multiple Rx Queues */
 			union {
-				__le32 rss;           /* RSS Hash */
+				__le32 rss; /* RSS Hash */
 				struct {
 					__le16 ip_id;    /* IP id */
 					__le16 csum;     /* Packet Checksum */
@@ -393,8 +392,8 @@ union e1000_rx_desc_packet_split {
 		} lower;
 		struct {
 			__le32 status_error;  /* ext status/error */
-			__le16 length0;       /* length of buffer 0 */
-			__le16 vlan;          /* VLAN tag */
+			__le16 length0;  /* length of buffer 0 */
+			__le16 vlan;  /* VLAN tag */
 		} middle;
 		struct {
 			__le16 header_status;
@@ -410,16 +409,16 @@ struct e1000_tx_desc {
 	union {
 		__le32 data;
 		struct {
-			__le16 length;    /* Data buffer length */
-			u8 cso;           /* Checksum offset */
-			u8 cmd;           /* Descriptor control */
+			__le16 length;  /* Data buffer length */
+			u8 cso;  /* Checksum offset */
+			u8 cmd;  /* Descriptor control */
 		} flags;
 	} lower;
 	union {
 		__le32 data;
 		struct {
-			u8 status;        /* Descriptor status */
-			u8 css;           /* Checksum start */
+			u8 status; /* Descriptor status */
+			u8 css;  /* Checksum start */
 			__le16 special;
 		} fields;
 	} upper;
@@ -430,37 +429,37 @@ struct e1000_context_desc {
 	union {
 		__le32 ip_config;
 		struct {
-			u8 ipcss;         /* IP checksum start */
-			u8 ipcso;         /* IP checksum offset */
-			__le16 ipcse;     /* IP checksum end */
+			u8 ipcss;  /* IP checksum start */
+			u8 ipcso;  /* IP checksum offset */
+			__le16 ipcse;  /* IP checksum end */
 		} ip_fields;
 	} lower_setup;
 	union {
 		__le32 tcp_config;
 		struct {
-			u8 tucss;         /* TCP checksum start */
-			u8 tucso;         /* TCP checksum offset */
-			__le16 tucse;     /* TCP checksum end */
+			u8 tucss;  /* TCP checksum start */
+			u8 tucso;  /* TCP checksum offset */
+			__le16 tucse;  /* TCP checksum end */
 		} tcp_fields;
 	} upper_setup;
 	__le32 cmd_and_length;
 	union {
 		__le32 data;
 		struct {
-			u8 status;        /* Descriptor status */
-			u8 hdr_len;       /* Header length */
-			__le16 mss;       /* Maximum segment size */
+			u8 status;  /* Descriptor status */
+			u8 hdr_len;  /* Header length */
+			__le16 mss;  /* Maximum segment size */
 		} fields;
 	} tcp_seg_setup;
 };
 
 /* Offload data descriptor */
 struct e1000_data_desc {
-	__le64 buffer_addr;   /* Address of the descriptor's buffer address */
+	__le64 buffer_addr;  /* Address of the descriptor's buffer address */
 	union {
 		__le32 data;
 		struct {
-			__le16 length;    /* Data buffer length */
+			__le16 length;  /* Data buffer length */
 			u8 typ_len_ext;
 			u8 cmd;
 		} flags;
@@ -468,8 +467,8 @@ struct e1000_data_desc {
 	union {
 		__le32 data;
 		struct {
-			u8 status;        /* Descriptor status */
-			u8 popts;         /* Packet Options */
+			u8 status;  /* Descriptor status */
+			u8 popts;  /* Packet Options */
 			__le16 special;
 		} fields;
 	} upper;
@@ -553,6 +552,10 @@ struct e1000_hw_stats {
 	u64 scvpc;
 	u64 hrmpc;
 	u64 doosync;
+	u64 o2bgptc;
+	u64 o2bspc;
+	u64 b2ospc;
+	u64 b2ogprc;
 };
 
 struct e1000_vf_stats {
@@ -611,7 +614,7 @@ struct e1000_host_command_header {
 	u8 checksum;
 };
 
-#define E1000_HI_MAX_DATA_LENGTH     252
+#define E1000_HI_MAX_DATA_LENGTH	252
 struct e1000_host_command_info {
 	struct e1000_host_command_header command_header;
 	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
@@ -626,7 +629,7 @@ struct e1000_host_mng_command_header {
 	u16 command_length;
 };
 
-#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
+#define E1000_HI_MAX_MNG_DATA_LENGTH	0x6F8
 struct e1000_host_mng_command_info {
 	struct e1000_host_mng_command_header command_header;
 	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
@@ -668,11 +671,26 @@ struct e1000_mac_operations {
 	s32  (*validate_mdi_setting)(struct e1000_hw *);
 	s32  (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
 	s32  (*mng_write_cmd_header)(struct e1000_hw *hw,
-                      struct e1000_host_mng_command_header*);
+				     struct e1000_host_mng_command_header*);
 	s32  (*mng_enable_host_if)(struct e1000_hw *);
 	s32  (*wait_autoneg)(struct e1000_hw *);
 };
 
+/*
+ * When to use various PHY register access functions:
+ *
+ *                 Func   Caller
+ *   Function      Does   Does    When to use
+ *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *   X_reg         L,P,A  n/a     for simple PHY reg accesses
+ *   X_reg_locked  P,A    L       for multiple accesses of different regs
+ *                                on different pages
+ *   X_reg_page    A      L,P     for multiple accesses of different regs
+ *                                on the same page
+ *
+ * Where X=[read|write], L=locking, P=sets page, A=register access
+ *
+ */
 struct e1000_phy_operations {
 	s32  (*init_params)(struct e1000_hw *);
 	s32  (*acquire)(struct e1000_hw *);
@@ -684,16 +702,21 @@ struct e1000_phy_operations {
 	s32  (*get_cfg_done)(struct e1000_hw *hw);
 	s32  (*get_cable_length)(struct e1000_hw *);
 	s32  (*get_info)(struct e1000_hw *);
+	s32  (*set_page)(struct e1000_hw *, u16);
 	s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 	s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
+	s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
 	void (*release)(struct e1000_hw *);
 	s32  (*reset)(struct e1000_hw *);
 	s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 	s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 	s32  (*write_reg)(struct e1000_hw *, u32, u16);
 	s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
+	s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
 	void (*power_up)(struct e1000_hw *);
 	void (*power_down)(struct e1000_hw *);
+	s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
+	s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
 };
 
 struct e1000_nvm_operations {
@@ -781,7 +804,6 @@ struct e1000_phy_info {
 	bool disable_polarity_correction;
 	bool is_mdix;
 	bool polarity_correction;
-	bool reset_disable;
 	bool speed_downgraded;
 	bool autoneg_wait_to_complete;
 };
@@ -811,14 +833,14 @@ struct e1000_bus_info {
 };
 
 struct e1000_fc_info {
-	u32 high_water;          /* Flow control high-water mark */
-	u32 low_water;           /* Flow control low-water mark */
-	u16 pause_time;          /* Flow control pause timer */
-	u16 refresh_time;        /* Flow control refresh timer */
-	bool send_xon;           /* Flow control send XON */
-	bool strict_ieee;        /* Strict IEEE mode */
-	enum e1000_fc_mode current_mode; /* FC mode in effect */
-	enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
+	u32 high_water;  /* Flow control high-water mark */
+	u32 low_water;  /* Flow control low-water mark */
+	u16 pause_time;  /* Flow control pause timer */
+	u16 refresh_time;  /* Flow control refresh timer */
+	bool send_xon;  /* Flow control send XON */
+	bool strict_ieee;  /* Strict IEEE mode */
+	enum e1000_fc_mode current_mode;  /* FC mode in effect */
+	enum e1000_fc_mode requested_mode;  /* FC mode requested by caller */
 };
 
 struct e1000_mbx_operations {
@@ -889,13 +911,15 @@ struct e1000_dev_spec_ich8lan {
 	E1000_MUTEX nvm_mutex;
 	E1000_MUTEX swflag_mutex;
 	bool nvm_k1_enabled;
-	bool eee_disable;
+	int eee_disable;
 };
 
 struct e1000_dev_spec_82575 {
 	bool sgmii_active;
 	bool global_device_reset;
-	bool eee_disable;
+	int eee_disable;
+	bool module_plugged;
+	u32 mtu;
 };
 
 struct e1000_dev_spec_vf {
diff --git a/sys/dev/e1000/e1000_ich8lan.c b/sys/dev/e1000/e1000_ich8lan.c
index 8218908..aa4802c 100644
--- a/sys/dev/e1000/e1000_ich8lan.c
+++ b/sys/dev/e1000/e1000_ich8lan.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -76,23 +76,23 @@ static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
-                                              u8 *mc_addr_list,
-                                              u32 mc_addr_count);
+					      u8 *mc_addr_list,
+					      u32 mc_addr_count);
 static s32  e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
 static s32  e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
 static s32  e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 static s32  e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
-                                            bool active);
+					    bool active);
 static s32  e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
-                                            bool active);
+					    bool active);
 static s32  e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
-                                   u16 words, u16 *data);
+				   u16 words, u16 *data);
 static s32  e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
-                                    u16 words, u16 *data);
+				    u16 words, u16 *data);
 static s32  e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
 static s32  e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
 static s32  e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
-                                            u16 *data);
+					    u16 *data);
 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 static s32  e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
 static s32  e1000_reset_hw_ich8lan(struct e1000_hw *hw);
@@ -100,7 +100,7 @@ static s32  e1000_init_hw_ich8lan(struct e1000_hw *hw);
 static s32  e1000_setup_link_ich8lan(struct e1000_hw *hw);
 static s32  e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 static s32  e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
-                                           u16 *speed, u16 *duplex);
+					   u16 *speed, u16 *duplex);
 static s32  e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 static s32  e1000_led_on_ich8lan(struct e1000_hw *hw);
 static s32  e1000_led_off_ich8lan(struct e1000_hw *hw);
@@ -116,17 +116,17 @@ static s32  e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw);
 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 static s32  e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 static s32  e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
-                                          u32 offset, u8 *data);
+					  u32 offset, u8 *data);
 static s32  e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
-                                          u8 size, u16 *data);
+					  u8 size, u16 *data);
 static s32  e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
-                                          u32 offset, u16 *data);
+					  u32 offset, u16 *data);
 static s32  e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
-                                                 u32 offset, u8 byte);
+						 u32 offset, u8 byte);
 static s32  e1000_write_flash_byte_ich8lan(struct e1000_hw *hw,
-                                           u32 offset, u8 data);
+					   u32 offset, u8 data);
 static s32  e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
-                                           u8 size, u16 data);
+					   u8 size, u16 data);
 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
@@ -135,20 +135,23 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
+#if defined(NAHUM6_HW) && (defined(LTR_SUPPORT) || defined(OBFF_SUPPORT))
+
+#endif /* NAHUM6_HW && (LTR_SUPPORT || OBFF_SUPPORT) */
 
 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 /* Offset 04h HSFSTS */
 union ich8_hws_flash_status {
 	struct ich8_hsfsts {
-		u16 flcdone    :1; /* bit 0 Flash Cycle Done */
-		u16 flcerr     :1; /* bit 1 Flash Cycle Error */
-		u16 dael       :1; /* bit 2 Direct Access error Log */
-		u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
-		u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
-		u16 reserved1  :2; /* bit 13:6 Reserved */
-		u16 reserved2  :6; /* bit 13:6 Reserved */
-		u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
-		u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
+		u16 flcdone:1; /* bit 0 Flash Cycle Done */
+		u16 flcerr:1; /* bit 1 Flash Cycle Error */
+		u16 dael:1; /* bit 2 Direct Access error Log */
+		u16 berasesz:2; /* bit 4:3 Sector Erase Size */
+		u16 flcinprog:1; /* bit 5 flash cycle in Progress */
+		u16 reserved1:2; /* bit 13:6 Reserved */
+		u16 reserved2:6; /* bit 13:6 Reserved */
+		u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
+		u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
 	} hsf_status;
 	u16 regval;
 };
@@ -157,11 +160,11 @@ union ich8_hws_flash_status {
 /* Offset 06h FLCTL */
 union ich8_hws_flash_ctrl {
 	struct ich8_hsflctl {
-		u16 flcgo      :1;   /* 0 Flash Cycle Go */
-		u16 flcycle    :2;   /* 2:1 Flash Cycle */
-		u16 reserved   :5;   /* 7:3 Reserved  */
-		u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
-		u16 flockdn    :6;   /* 15:10 Reserved */
+		u16 flcgo:1;   /* 0 Flash Cycle Go */
+		u16 flcycle:2;   /* 2:1 Flash Cycle */
+		u16 reserved:5;   /* 7:3 Reserved  */
+		u16 fldbcount:2;   /* 9:8 Flash Data Byte Count */
+		u16 flockdn:6;   /* 15:10 Reserved */
 	} hsf_ctrl;
 	u16 regval;
 };
@@ -169,14 +172,30 @@ union ich8_hws_flash_ctrl {
 /* ICH Flash Region Access Permissions */
 union ich8_hws_flash_regacc {
 	struct ich8_flracc {
-		u32 grra      :8; /* 0:7 GbE region Read Access */
-		u32 grwa      :8; /* 8:15 GbE region Write Access */
-		u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
-		u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
+		u32 grra:8; /* 0:7 GbE region Read Access */
+		u32 grwa:8; /* 8:15 GbE region Write Access */
+		u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
+		u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
 	} hsf_flregacc;
 	u16 regval;
 };
 
+static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw)
+{
+	u32 ctrl;
+
+	DEBUGFUNC("e1000_toggle_lanphypc_value_ich8lan");
+
+	ctrl = E1000_READ_REG(hw, E1000_CTRL);
+	ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
+	ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
+	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
+	E1000_WRITE_FLUSH(hw);
+	usec_delay(10);
+	ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
+	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
+}
+
 /**
  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
  *  @hw: pointer to the HW structure
@@ -186,70 +205,66 @@ union ich8_hws_flash_regacc {
 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 {
 	struct e1000_phy_info *phy = &hw->phy;
-	u32 ctrl, fwsm;
 	s32 ret_val = E1000_SUCCESS;
 
 	DEBUGFUNC("e1000_init_phy_params_pchlan");
 
-	phy->addr                     = 1;
-	phy->reset_delay_us           = 100;
-
-	phy->ops.acquire              = e1000_acquire_swflag_ich8lan;
-	phy->ops.check_reset_block    = e1000_check_reset_block_ich8lan;
-	phy->ops.get_cfg_done         = e1000_get_cfg_done_ich8lan;
-	phy->ops.read_reg             = e1000_read_phy_reg_hv;
-	phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
-	phy->ops.release              = e1000_release_swflag_ich8lan;
-	phy->ops.reset                = e1000_phy_hw_reset_ich8lan;
-	phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
-	phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
-	phy->ops.write_reg            = e1000_write_phy_reg_hv;
-	phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
-	phy->ops.power_up             = e1000_power_up_phy_copper;
-	phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
-	phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
+	phy->addr		= 1;
+	phy->reset_delay_us	= 100;
+
+	phy->ops.acquire	= e1000_acquire_swflag_ich8lan;
+	phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
+	phy->ops.get_cfg_done	= e1000_get_cfg_done_ich8lan;
+	phy->ops.set_page	= e1000_set_page_igp;
+	phy->ops.read_reg	= e1000_read_phy_reg_hv;
+	phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
+	phy->ops.read_reg_page	= e1000_read_phy_reg_page_hv;
+	phy->ops.release	= e1000_release_swflag_ich8lan;
+	phy->ops.reset		= e1000_phy_hw_reset_ich8lan;
+	phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
+	phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
+	phy->ops.write_reg	= e1000_write_phy_reg_hv;
+	phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
+	phy->ops.write_reg_page	= e1000_write_phy_reg_page_hv;
+	phy->ops.power_up	= e1000_power_up_phy_copper;
+	phy->ops.power_down	= e1000_power_down_phy_copper_ich8lan;
+	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;
 
-	/*
-	 * The MAC-PHY interconnect may still be in SMBus mode
-	 * after Sx->S0.  If the manageability engine (ME) is
-	 * disabled, then toggle the LANPHYPC Value bit to force
-	 * the interconnect to PCIe mode.
-	 */
-	fwsm = E1000_READ_REG(hw, E1000_FWSM);
-	if (!(fwsm & E1000_ICH_FWSM_FW_VALID) &&
-	    !(hw->phy.ops.check_reset_block(hw))) {
-		ctrl = E1000_READ_REG(hw, E1000_CTRL);
-		ctrl |=  E1000_CTRL_LANPHYPC_OVERRIDE;
-		ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
-		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
-		usec_delay(10);
-		ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
-		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
+	if (!hw->phy.ops.check_reset_block(hw)) {
+		u32 fwsm = E1000_READ_REG(hw, E1000_FWSM);
+
+		/*
+		 * The MAC-PHY interconnect may still be in SMBus mode after
+		 * Sx->S0.  If resetting the PHY is not blocked, toggle the
+		 * LANPHYPC Value bit to force the interconnect to PCIe mode.
+		 */
+		e1000_toggle_lanphypc_value_ich8lan(hw);
 		msec_delay(50);
 
 		/*
 		 * Gate automatic PHY configuration by hardware on
 		 * non-managed 82579
 		 */
-		if (hw->mac.type == e1000_pch2lan)
+		if ((hw->mac.type == e1000_pch2lan) &&
+		    !(fwsm & E1000_ICH_FWSM_FW_VALID))
 			e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
-	}
 
-	/*
-	 * Reset the PHY before any acccess to it.  Doing so, ensures that
-	 * the PHY is in a known good state before we read/write PHY registers.
-	 * The generic reset is sufficient here, because we haven't determined
-	 * the PHY type yet.
-	 */
-	ret_val = e1000_phy_hw_reset_generic(hw);
-	if (ret_val)
-		goto out;
+		/*
+		 * Reset the PHY before any access to it.  Doing so, ensures
+		 * that the PHY is in a known good state before we read/write
+		 * PHY registers.  The generic reset is sufficient here,
+		 * because we haven't determined the PHY type yet.
+		 */
+		ret_val = e1000_phy_hw_reset_generic(hw);
+		if (ret_val)
+			goto out;
 
-	/* Ungate automatic PHY configuration on non-managed 82579 */
-	if ((hw->mac.type == e1000_pch2lan)  &&
-	    !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
-		msec_delay(10);
-		e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
+		/* Ungate automatic PHY configuration on non-managed 82579 */
+		if ((hw->mac.type == e1000_pch2lan) &&
+		    !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
+			msec_delay(10);
+			e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
+		}
 	}
 
 	phy->id = e1000_phy_unknown;
@@ -315,21 +330,21 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 
 	DEBUGFUNC("e1000_init_phy_params_ich8lan");
 
-	phy->addr                     = 1;
-	phy->reset_delay_us           = 100;
-
-	phy->ops.acquire              = e1000_acquire_swflag_ich8lan;
-	phy->ops.check_reset_block    = e1000_check_reset_block_ich8lan;
-	phy->ops.get_cable_length     = e1000_get_cable_length_igp_2;
-	phy->ops.get_cfg_done         = e1000_get_cfg_done_ich8lan;
-	phy->ops.read_reg             = e1000_read_phy_reg_igp;
-	phy->ops.release              = e1000_release_swflag_ich8lan;
-	phy->ops.reset                = e1000_phy_hw_reset_ich8lan;
-	phy->ops.set_d0_lplu_state    = e1000_set_d0_lplu_state_ich8lan;
-	phy->ops.set_d3_lplu_state    = e1000_set_d3_lplu_state_ich8lan;
-	phy->ops.write_reg            = e1000_write_phy_reg_igp;
-	phy->ops.power_up             = e1000_power_up_phy_copper;
-	phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
+	phy->addr		= 1;
+	phy->reset_delay_us	= 100;
+
+	phy->ops.acquire	= e1000_acquire_swflag_ich8lan;
+	phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
+	phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
+	phy->ops.get_cfg_done	= e1000_get_cfg_done_ich8lan;
+	phy->ops.read_reg	= e1000_read_phy_reg_igp;
+	phy->ops.release	= e1000_release_swflag_ich8lan;
+	phy->ops.reset		= e1000_phy_hw_reset_ich8lan;
+	phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
+	phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
+	phy->ops.write_reg	= e1000_write_phy_reg_igp;
+	phy->ops.power_up	= e1000_power_up_phy_copper;
+	phy->ops.power_down	= e1000_power_down_phy_copper_ich8lan;
 
 	/*
 	 * We may need to do this twice - once for IGP and if that fails,
@@ -438,7 +453,7 @@ static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 	 * size represents two separate NVM banks.
 	 */
 	nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
-	                          << FLASH_SECTOR_ADDR_SHIFT;
+				<< FLASH_SECTOR_ADDR_SHIFT;
 	nvm->flash_bank_size /= 2;
 	/* Adjust to word count */
 	nvm->flash_bank_size /= sizeof(u16);
@@ -455,13 +470,13 @@ static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 	E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
 
 	/* Function Pointers */
-	nvm->ops.acquire       = e1000_acquire_nvm_ich8lan;
-	nvm->ops.release       = e1000_release_nvm_ich8lan;
-	nvm->ops.read          = e1000_read_nvm_ich8lan;
-	nvm->ops.update        = e1000_update_nvm_checksum_ich8lan;
+	nvm->ops.acquire	= e1000_acquire_nvm_ich8lan;
+	nvm->ops.release	= e1000_release_nvm_ich8lan;
+	nvm->ops.read		= e1000_read_nvm_ich8lan;
+	nvm->ops.update		= e1000_update_nvm_checksum_ich8lan;
 	nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
-	nvm->ops.validate      = e1000_validate_nvm_checksum_ich8lan;
-	nvm->ops.write         = e1000_write_nvm_ich8lan;
+	nvm->ops.validate	= e1000_validate_nvm_checksum_ich8lan;
+	nvm->ops.write		= e1000_write_nvm_ich8lan;
 
 out:
 	return ret_val;
@@ -477,7 +492,6 @@ out:
 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 {
 	struct e1000_mac_info *mac = &hw->mac;
-	u16 pci_cfg;
 
 	DEBUGFUNC("e1000_init_mac_params_ich8lan");
 
@@ -549,9 +563,6 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 			e1000_update_mc_addr_list_pch2lan;
 		/* fall-through */
 	case e1000_pchlan:
-		/* save PCH revision_id */
-		e1000_read_pci_cfg(hw, 0x2, &pci_cfg);
-		hw->revision_id = (u8)(pci_cfg &= 0x000F);
 		/* check management mode */
 		mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 		/* ID LED init */
@@ -568,6 +579,11 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 		break;
 	}
 
+#if defined(NAHUM6_HW) && (defined(LTR_SUPPORT) || defined(OBFF_SUPPORT))
+	if (mac->type == e1000_pch_lpt) {
+	}
+
+#endif /* NAHUM6_HW && (LTR_SUPPORT || OBFF_SUPPORT) */
 	/* Enable PCS Lock-loss workaround for ICH8 */
 	if (mac->type == e1000_ich8lan)
 		e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE);
@@ -589,6 +605,7 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
  **/
 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 {
+	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 	s32 ret_val = E1000_SUCCESS;
 	u16 phy_reg;
 
@@ -601,7 +618,7 @@ static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 	if (ret_val)
 		goto out;
 
-	if (hw->dev_spec.ich8lan.eee_disable)
+	if (dev_spec->eee_disable)
 		phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
 	else
 		phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
@@ -624,6 +641,7 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 	struct e1000_mac_info *mac = &hw->mac;
 	s32 ret_val;
 	bool link;
+	u16 phy_reg;
 
 	DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
 
@@ -653,21 +671,46 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 			goto out;
 	}
 
+#if defined(NAHUM6_HW) && (defined(LTR_SUPPORT) || defined(OBFF_SUPPORT))
+	if (hw->mac.type == e1000_pch_lpt) {
+	}
+
+#endif /* NAHUM6_HW && (LTR_SUPPORT || OBFF_SUPPORT) */
 	if (!link)
 		goto out; /* No link detected */
 
 	mac->get_link_status = FALSE;
 
-	if (hw->phy.type == e1000_phy_82578) {
-		ret_val = e1000_link_stall_workaround_hv(hw);
-		if (ret_val)
-			goto out;
-	}
-
-	if (hw->mac.type == e1000_pch2lan) {
+	switch (hw->mac.type) {
+	case e1000_pch2lan:
 		ret_val = e1000_k1_workaround_lv(hw);
 		if (ret_val)
 			goto out;
+		/* fall-thru */
+	case e1000_pchlan:
+		if (hw->phy.type == e1000_phy_82578) {
+			ret_val = e1000_link_stall_workaround_hv(hw);
+			if (ret_val)
+				goto out;
+		}
+
+		/*
+		 * Workaround for PCHx parts in half-duplex:
+		 * Set the number of preambles removed from the packet
+		 * when it is passed from the PHY to the MAC to prevent
+		 * the MAC from misinterpreting the packet type.
+		 */
+		hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
+		phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
+
+		if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
+		    E1000_STATUS_FD)
+			phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
+
+		hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
+		break;
+	default:
+		break;
 	}
 
 	/*
@@ -794,7 +837,7 @@ static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 	}
 
 	if (!timeout) {
-		DEBUGOUT("SW/FW/HW has locked the resource for too long.\n");
+		DEBUGOUT("SW has already locked the resource.\n");
 		ret_val = -E1000_ERR_CONFIG;
 		goto out;
 	}
@@ -814,7 +857,8 @@ static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 	}
 
 	if (!timeout) {
-		DEBUGOUT("Failed to acquire the semaphore.\n");
+		DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
+			  E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
 		extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 		E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 		ret_val = -E1000_ERR_CONFIG;
@@ -918,8 +962,8 @@ static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
 	 * from network order (big endian) to little endian
 	 */
 	rar_low = ((u32) addr[0] |
-	           ((u32) addr[1] << 8) |
-	           ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
+		   ((u32) addr[1] << 8) |
+		   ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
 
 	rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
 
@@ -963,22 +1007,38 @@ static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
  *  The caller must have a packed mc_addr_list of multicast addresses.
  **/
 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
-                                              u8 *mc_addr_list,
-                                              u32 mc_addr_count)
+					      u8 *mc_addr_list,
+					      u32 mc_addr_count)
 {
+	u16 phy_reg = 0;
 	int i;
+	s32 ret_val;
 
 	DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
 
 	e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
 
+	ret_val = hw->phy.ops.acquire(hw);
+	if (ret_val)
+		return;
+
+	ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
+	if (ret_val)
+		goto release;
+
 	for (i = 0; i < hw->mac.mta_reg_count; i++) {
-		hw->phy.ops.write_reg(hw, BM_MTA(i),
-		                   (u16)(hw->mac.mta_shadow[i] & 0xFFFF));
-		hw->phy.ops.write_reg(hw, (BM_MTA(i) + 1),
-		                      (u16)((hw->mac.mta_shadow[i] >> 16) &
-		                       0xFFFF));
+		hw->phy.ops.write_reg_page(hw, BM_MTA(i),
+					   (u16)(hw->mac.mta_shadow[i] &
+						 0xFFFF));
+		hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
+					   (u16)((hw->mac.mta_shadow[i] >> 16) &
+						 0xFFFF));
 	}
+
+	e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
+
+release:
+	hw->phy.ops.release(hw);
 }
 
 /**
@@ -995,13 +1055,10 @@ static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 
 	DEBUGFUNC("e1000_check_reset_block_ich8lan");
 
-	if (hw->phy.reset_disable)
-		return E1000_BLK_PHY_RESET;
-
 	fwsm = E1000_READ_REG(hw, E1000_FWSM);
 
 	return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS
-	                                        : E1000_BLK_PHY_RESET;
+						: E1000_BLK_PHY_RESET;
 }
 
 /**
@@ -1187,46 +1244,46 @@ static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
 	if (link) {
 		if (hw->phy.type == e1000_phy_82578) {
 			ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
-			                                      &status_reg);
+							      &status_reg);
 			if (ret_val)
 				goto release;
 
 			status_reg &= BM_CS_STATUS_LINK_UP |
-			              BM_CS_STATUS_RESOLVED |
-			              BM_CS_STATUS_SPEED_MASK;
+				      BM_CS_STATUS_RESOLVED |
+				      BM_CS_STATUS_SPEED_MASK;
 
 			if (status_reg == (BM_CS_STATUS_LINK_UP |
-			                   BM_CS_STATUS_RESOLVED |
-			                   BM_CS_STATUS_SPEED_1000))
+					   BM_CS_STATUS_RESOLVED |
+					   BM_CS_STATUS_SPEED_1000))
 				k1_enable = FALSE;
 		}
 
 		if (hw->phy.type == e1000_phy_82577) {
 			ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
-			                                      &status_reg);
+							      &status_reg);
 			if (ret_val)
 				goto release;
 
 			status_reg &= HV_M_STATUS_LINK_UP |
-			              HV_M_STATUS_AUTONEG_COMPLETE |
-			              HV_M_STATUS_SPEED_MASK;
+				      HV_M_STATUS_AUTONEG_COMPLETE |
+				      HV_M_STATUS_SPEED_MASK;
 
 			if (status_reg == (HV_M_STATUS_LINK_UP |
-			                   HV_M_STATUS_AUTONEG_COMPLETE |
-			                   HV_M_STATUS_SPEED_1000))
+					   HV_M_STATUS_AUTONEG_COMPLETE |
+					   HV_M_STATUS_SPEED_1000))
 				k1_enable = FALSE;
 		}
 
 		/* Link stall fix for link up */
 		ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
-		                                       0x0100);
+						       0x0100);
 		if (ret_val)
 			goto release;
 
 	} else {
 		/* Link stall fix for link down */
 		ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
-		                                       0x4100);
+						       0x4100);
 		if (ret_val)
 			goto release;
 	}
@@ -1259,9 +1316,8 @@ s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
 
 	DEBUGFUNC("e1000_configure_k1_ich8lan");
 
-	ret_val = e1000_read_kmrn_reg_locked(hw,
-	                                     E1000_KMRNCTRLSTA_K1_CONFIG,
-	                                     &kmrn_reg);
+	ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
+					     &kmrn_reg);
 	if (ret_val)
 		goto out;
 
@@ -1270,9 +1326,8 @@ s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
 	else
 		kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
 
-	ret_val = e1000_write_kmrn_reg_locked(hw,
-	                                      E1000_KMRNCTRLSTA_K1_CONFIG,
-	                                      kmrn_reg);
+	ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
+					      kmrn_reg);
 	if (ret_val)
 		goto out;
 
@@ -1285,9 +1340,11 @@ s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
 	E1000_WRITE_REG(hw, E1000_CTRL, reg);
 
 	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
+	E1000_WRITE_FLUSH(hw);
 	usec_delay(20);
 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
 	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
+	E1000_WRITE_FLUSH(hw);
 	usec_delay(20);
 
 out:
@@ -1303,7 +1360,7 @@ out:
  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
  **/
-s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
+static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
 {
 	s32 ret_val = 0;
 	u32 mac_reg;
@@ -1342,16 +1399,20 @@ s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
 
 		if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
 			oem_reg |= HV_OEM_BITS_LPLU;
+
+		/* Set Restart auto-neg to activate the bits */
+		if (!hw->phy.ops.check_reset_block(hw))
+			oem_reg |= HV_OEM_BITS_RESTART_AN;
 	} else {
-		if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
+		if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
+		    E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
 			oem_reg |= HV_OEM_BITS_GBE_DIS;
 
-		if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
+		if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
+		    E1000_PHY_CTRL_NOND0A_LPLU))
 			oem_reg |= HV_OEM_BITS_LPLU;
 	}
-	/* Restart auto-neg to activate the bits */
-	if (!hw->phy.ops.check_reset_block(hw))
-		oem_reg |= HV_OEM_BITS_RESTART_AN;
+
 	ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
 
 out:
@@ -1362,20 +1423,6 @@ out:
 
 
 /**
- *  e1000_hv_phy_powerdown_workaround_ich8lan - Power down workaround on Sx
- *  @hw: pointer to the HW structure
- **/
-s32 e1000_hv_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
-{
-	DEBUGFUNC("e1000_hv_phy_powerdown_workaround_ich8lan");
-
-	if ((hw->phy.type != e1000_phy_82577) || (hw->revision_id > 2))
-		return E1000_SUCCESS;
-
-	return hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0444);
-}
-
-/**
  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
  *  @hw:   pointer to the HW structure
  **/
@@ -1418,32 +1465,6 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
 			goto out;
 	}
 
-	/* Hanksville M Phy init for IEEE. */
-	if ((hw->revision_id == 2) &&
-	    (hw->phy.type == e1000_phy_82577) &&
-	    ((hw->phy.revision == 2) || (hw->phy.revision == 3))) {
-		hw->phy.ops.write_reg(hw, 0x10, 0x8823);
-		hw->phy.ops.write_reg(hw, 0x11, 0x0018);
-		hw->phy.ops.write_reg(hw, 0x10, 0x8824);
-		hw->phy.ops.write_reg(hw, 0x11, 0x0016);
-		hw->phy.ops.write_reg(hw, 0x10, 0x8825);
-		hw->phy.ops.write_reg(hw, 0x11, 0x001A);
-		hw->phy.ops.write_reg(hw, 0x10, 0x888C);
-		hw->phy.ops.write_reg(hw, 0x11, 0x0007);
-		hw->phy.ops.write_reg(hw, 0x10, 0x888D);
-		hw->phy.ops.write_reg(hw, 0x11, 0x0007);
-		hw->phy.ops.write_reg(hw, 0x10, 0x888E);
-		hw->phy.ops.write_reg(hw, 0x11, 0x0007);
-		hw->phy.ops.write_reg(hw, 0x10, 0x8827);
-		hw->phy.ops.write_reg(hw, 0x11, 0x0001);
-		hw->phy.ops.write_reg(hw, 0x10, 0x8835);
-		hw->phy.ops.write_reg(hw, 0x11, 0x0001);
-		hw->phy.ops.write_reg(hw, 0x10, 0x8834);
-		hw->phy.ops.write_reg(hw, 0x11, 0x0001);
-		hw->phy.ops.write_reg(hw, 0x10, 0x8833);
-		hw->phy.ops.write_reg(hw, 0x11, 0x0002);
-	}
-
 	if (((hw->phy.type == e1000_phy_82577) &&
 	     ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
 	    ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
@@ -1453,26 +1474,13 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
 			goto out;
 
 		/* Preamble tuning for SSC */
-		ret_val = hw->phy.ops.write_reg(hw, PHY_REG(770, 16), 0xA204);
+		ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
+						0xA204);
 		if (ret_val)
 			goto out;
 	}
 
 	if (hw->phy.type == e1000_phy_82578) {
-		if (hw->revision_id < 3) {
-			/* PHY config */
-			ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x29,
-			                                0x66C0);
-			if (ret_val)
-				goto out;
-
-			/* PHY config */
-			ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x1E,
-			                                0xFFFF);
-			if (ret_val)
-				goto out;
-		}
-
 		/*
 		 * Return registers to default by doing a soft reset then
 		 * writing 0x3140 to the control register.
@@ -1480,25 +1488,10 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
 		if (hw->phy.revision < 2) {
 			e1000_phy_sw_reset_generic(hw);
 			ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
-			                                0x3140);
+							0x3140);
 		}
 	}
 
-	if ((hw->revision_id == 2) &&
-	    (hw->phy.type == e1000_phy_82577) &&
-	    ((hw->phy.revision == 2) || (hw->phy.revision == 3))) {
-		/*
-		 * Workaround for OEM (GbE) not operating after reset -
-		 * restart AN (twice)
-		 */
-		ret_val = hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0400);
-		if (ret_val)
-			goto out;
-		ret_val = hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0400);
-		if (ret_val)
-			goto out;
-	}
-
 	/* Select page 0 */
 	ret_val = hw->phy.ops.acquire(hw);
 	if (ret_val)
@@ -1522,12 +1515,11 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
 	ret_val = hw->phy.ops.acquire(hw);
 	if (ret_val)
 		goto out;
-	ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG_REG,
-	                                      &phy_data);
+	ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
 	if (ret_val)
 		goto release;
-	ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG_REG,
-	                                       phy_data & 0x00FF);
+	ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
+					       phy_data & 0x00FF);
 release:
 	hw->phy.ops.release(hw);
 out:
@@ -1541,19 +1533,38 @@ out:
 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
 {
 	u32 mac_reg;
-	u16 i;
+	u16 i, phy_reg = 0;
+	s32 ret_val;
 
 	DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
 
+	ret_val = hw->phy.ops.acquire(hw);
+	if (ret_val)
+		return;
+	ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
+	if (ret_val)
+		goto release;
+
 	/* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
 	for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
 		mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
-		hw->phy.ops.write_reg(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF));
-		hw->phy.ops.write_reg(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF));
+		hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
+					   (u16)(mac_reg & 0xFFFF));
+		hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
+					   (u16)((mac_reg >> 16) & 0xFFFF));
+
 		mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
-		hw->phy.ops.write_reg(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF));
-		hw->phy.ops.write_reg(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0x8000));
+		hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
+					   (u16)(mac_reg & 0xFFFF));
+		hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
+					   (u16)((mac_reg & E1000_RAH_AV)
+						 >> 16));
 	}
+
+	e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
+
+release:
+	hw->phy.ops.release(hw);
 }
 
 static u32 e1000_calc_rx_da_crc(u8 mac[])
@@ -1594,7 +1605,8 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
 
 	/* disable Rx path while enabling/disabling workaround */
 	hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
-	ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
+	ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
+					phy_reg | (1 << 14));
 	if (ret_val)
 		goto out;
 
@@ -1676,11 +1688,12 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
 		ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
 		if (ret_val)
 			goto out;
-		ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xFE00);
+		ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
 		if (ret_val)
 			goto out;
 		hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
-		ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data | (1 << 10));
+		ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
+						(1 << 10));
 		if (ret_val)
 			goto out;
 	} else {
@@ -1737,13 +1750,15 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
 		if (ret_val)
 			goto out;
 		hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
-		ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data & ~(1 << 10));
+		ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
+						~(1 << 10));
 		if (ret_val)
 			goto out;
 	}
 
 	/* re-enable Rx path after enabling/disabling workaround */
-	ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
+	ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
+					~(1 << 14));
 
 out:
 	return ret_val;
@@ -1765,6 +1780,28 @@ static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
 	/* Set MDIO slow mode before any other MDIO access */
 	ret_val = e1000_set_mdio_slow_mode_hv(hw);
 
+	ret_val = hw->phy.ops.acquire(hw);
+	if (ret_val)
+		goto out;
+	ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
+					       I82579_MSE_THRESHOLD);
+	if (ret_val)
+		goto release;
+	/* set MSE higher to enable link to stay up when noise is high */
+	ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
+					       0x0034);
+	if (ret_val)
+		goto release;
+	ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
+					       I82579_MSE_LINK_DOWN);
+	if (ret_val)
+		goto release;
+	/* drop link after 5 times MSE threshold was reached */
+	ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
+					       0x0005);
+release:
+	hw->phy.ops.release(hw);
+
 out:
 	return ret_val;
 }
@@ -1780,6 +1817,7 @@ static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
 	s32 ret_val = E1000_SUCCESS;
 	u16 status_reg = 0;
 	u32 mac_reg;
+	u16 phy_reg;
 
 	DEBUGFUNC("e1000_k1_workaround_lv");
 
@@ -1796,12 +1834,19 @@ static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
 		mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
 		mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
 
-		if (status_reg & HV_M_STATUS_SPEED_1000)
+		ret_val = hw->phy.ops.read_reg(hw, I82579_LPI_CTRL, &phy_reg);
+		if (ret_val)
+			goto out;
+
+		if (status_reg & HV_M_STATUS_SPEED_1000) {
 			mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
-		else
+			phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
+		} else {
 			mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
-
+			phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
+		}
 		E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
+		ret_val = hw->phy.ops.write_reg(hw, I82579_LPI_CTRL, phy_reg);
 	}
 
 out:
@@ -1837,34 +1882,6 @@ static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
 }
 
 /**
- *  e1000_hv_phy_tuning_workaround_ich8lan - This is a Phy tuning work around
- *  needed for Nahum3 + Hanksville testing, requested by HW team
- **/
-static s32 e1000_hv_phy_tuning_workaround_ich8lan(struct e1000_hw *hw)
-{
-	s32 ret_val = E1000_SUCCESS;
-
-	DEBUGFUNC("e1000_hv_phy_tuning_workaround_ich8lan");
-
-	ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
-	if (ret_val)
-		goto out;
-
-	ret_val = hw->phy.ops.write_reg(hw, PHY_REG(770, 16), 0xA204);
-	if (ret_val)
-		goto out;
-
-	ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x29, 0x66C0);
-	if (ret_val)
-		goto out;
-
-	ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x1E, 0xFFFF);
-
-out:
-	return ret_val;
-}
-
-/**
  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
  *  @hw: pointer to the HW structure
  *
@@ -1931,16 +1948,13 @@ static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
 		break;
 	}
 
-	if (hw->device_id == E1000_DEV_ID_ICH10_HANKSVILLE) {
-		ret_val = e1000_hv_phy_tuning_workaround_ich8lan(hw);
-		if (ret_val)
-			goto out;
+	/* Clear the host wakeup bit after lcd reset */
+	if (hw->mac.type >= e1000_pchlan) {
+		hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &reg);
+		reg &= ~BM_WUC_HOST_WU_BIT;
+		hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
 	}
 
-	/* Dummy read to clear the phy wakeup bit after lcd reset */
-	if (hw->mac.type >= e1000_pchlan)
-		hw->phy.ops.read_reg(hw, BM_WUC, &reg);
-
 	/* Configure the LCD with the extended configuration region in NVM */
 	ret_val = e1000_sw_lcd_config_ich8lan(hw);
 	if (ret_val)
@@ -2031,7 +2045,9 @@ static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
 	else
 		oem_reg &= ~HV_OEM_BITS_LPLU;
 
-	oem_reg |= HV_OEM_BITS_RESTART_AN;
+	if (!hw->phy.ops.check_reset_block(hw))
+		oem_reg |= HV_OEM_BITS_RESTART_AN;
+
 	ret_val = hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
 
 out:
@@ -2081,12 +2097,12 @@ static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
 
 		/* When LPLU is enabled, we should disable SmartSpeed */
 		ret_val = phy->ops.read_reg(hw,
-		                            IGP01E1000_PHY_PORT_CONFIG,
-		                            &data);
+					    IGP01E1000_PHY_PORT_CONFIG,
+					    &data);
 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 		ret_val = phy->ops.write_reg(hw,
-		                             IGP01E1000_PHY_PORT_CONFIG,
-		                             data);
+					     IGP01E1000_PHY_PORT_CONFIG,
+					     data);
 		if (ret_val)
 			goto out;
 	} else {
@@ -2104,28 +2120,28 @@ static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
 		 */
 		if (phy->smart_speed == e1000_smart_speed_on) {
 			ret_val = phy->ops.read_reg(hw,
-			                            IGP01E1000_PHY_PORT_CONFIG,
-			                            &data);
+						    IGP01E1000_PHY_PORT_CONFIG,
+						    &data);
 			if (ret_val)
 				goto out;
 
 			data |= IGP01E1000_PSCFR_SMART_SPEED;
 			ret_val = phy->ops.write_reg(hw,
-			                             IGP01E1000_PHY_PORT_CONFIG,
-			                             data);
+						     IGP01E1000_PHY_PORT_CONFIG,
+						     data);
 			if (ret_val)
 				goto out;
 		} else if (phy->smart_speed == e1000_smart_speed_off) {
 			ret_val = phy->ops.read_reg(hw,
-			                            IGP01E1000_PHY_PORT_CONFIG,
-			                            &data);
+						    IGP01E1000_PHY_PORT_CONFIG,
+						    &data);
 			if (ret_val)
 				goto out;
 
 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 			ret_val = phy->ops.write_reg(hw,
-			                             IGP01E1000_PHY_PORT_CONFIG,
-			                             data);
+						     IGP01E1000_PHY_PORT_CONFIG,
+						     data);
 			if (ret_val)
 				goto out;
 		}
@@ -2174,34 +2190,34 @@ static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
 		 */
 		if (phy->smart_speed == e1000_smart_speed_on) {
 			ret_val = phy->ops.read_reg(hw,
-			                            IGP01E1000_PHY_PORT_CONFIG,
-			                            &data);
+						    IGP01E1000_PHY_PORT_CONFIG,
+						    &data);
 			if (ret_val)
 				goto out;
 
 			data |= IGP01E1000_PSCFR_SMART_SPEED;
 			ret_val = phy->ops.write_reg(hw,
-			                             IGP01E1000_PHY_PORT_CONFIG,
-			                             data);
+						     IGP01E1000_PHY_PORT_CONFIG,
+						     data);
 			if (ret_val)
 				goto out;
 		} else if (phy->smart_speed == e1000_smart_speed_off) {
 			ret_val = phy->ops.read_reg(hw,
-			                            IGP01E1000_PHY_PORT_CONFIG,
-			                            &data);
+						    IGP01E1000_PHY_PORT_CONFIG,
+						    &data);
 			if (ret_val)
 				goto out;
 
 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 			ret_val = phy->ops.write_reg(hw,
-			                             IGP01E1000_PHY_PORT_CONFIG,
-			                             data);
+						     IGP01E1000_PHY_PORT_CONFIG,
+						     data);
 			if (ret_val)
 				goto out;
 		}
 	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
-	           (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
-	           (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
+		   (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
+		   (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 		phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
 		E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
 
@@ -2217,15 +2233,15 @@ static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
 
 		/* When LPLU is enabled, we should disable SmartSpeed */
 		ret_val = phy->ops.read_reg(hw,
-		                            IGP01E1000_PHY_PORT_CONFIG,
-		                            &data);
+					    IGP01E1000_PHY_PORT_CONFIG,
+					    &data);
 		if (ret_val)
 			goto out;
 
 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 		ret_val = phy->ops.write_reg(hw,
-		                             IGP01E1000_PHY_PORT_CONFIG,
-		                             data);
+					     IGP01E1000_PHY_PORT_CONFIG,
+					     data);
 	}
 
 out:
@@ -2264,8 +2280,7 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
 
 			goto out;
 		}
-		DEBUGOUT("Unable to determine valid NVM bank via EEC - "
-		         "reading flash signature\n");
+		DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
 		/* fall-thru */
 	default:
 		/* set bank to 0 in case flash read fails */
@@ -2273,7 +2288,7 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
 
 		/* Check bank 0 */
 		ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
-		                                        &sig_byte);
+							&sig_byte);
 		if (ret_val)
 			goto out;
 		if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
@@ -2284,8 +2299,8 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
 
 		/* Check bank 1 */
 		ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
-		                                        bank1_offset,
-		                                        &sig_byte);
+							bank1_offset,
+							&sig_byte);
 		if (ret_val)
 			goto out;
 		if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
@@ -2312,7 +2327,7 @@ out:
  *  Reads a word(s) from the NVM using the flash access registers.
  **/
 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
-                                  u16 *data)
+				  u16 *data)
 {
 	struct e1000_nvm_info *nvm = &hw->nvm;
 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
@@ -2343,13 +2358,12 @@ static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
 
 	ret_val = E1000_SUCCESS;
 	for (i = 0; i < words; i++) {
-		if ((dev_spec->shadow_ram) &&
-		    (dev_spec->shadow_ram[offset+i].modified)) {
+		if (dev_spec->shadow_ram[offset+i].modified) {
 			data[i] = dev_spec->shadow_ram[offset+i].value;
 		} else {
 			ret_val = e1000_read_flash_word_ich8lan(hw,
-			                                        act_offset + i,
-			                                        &word);
+								act_offset + i,
+								&word);
 			if (ret_val)
 				break;
 			data[i] = word;
@@ -2383,8 +2397,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
 
 	/* Check if the flash descriptor is valid */
 	if (hsfsts.hsf_status.fldesvalid == 0) {
-		DEBUGOUT("Flash descriptor invalid.  "
-		         "SW Sequencing must be used.");
+		DEBUGOUT("Flash descriptor invalid.  SW Sequencing must be used.\n");
 		goto out;
 	}
 
@@ -2421,7 +2434,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
 		 */
 		for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
 			hsfsts.regval = E1000_READ_FLASH_REG16(hw,
-			                                      ICH_FLASH_HSFSTS);
+							      ICH_FLASH_HSFSTS);
 			if (hsfsts.hsf_status.flcinprog == 0) {
 				ret_val = E1000_SUCCESS;
 				break;
@@ -2435,9 +2448,9 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
 			 */
 			hsfsts.hsf_status.flcdone = 1;
 			E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
-			                        hsfsts.regval);
+						hsfsts.regval);
 		} else {
-			DEBUGOUT("Flash controller busy, cannot get access");
+			DEBUGOUT("Flash controller busy, cannot get access\n");
 		}
 	}
 
@@ -2490,7 +2503,7 @@ static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
  *  to bytes before read.
  **/
 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
-                                         u16 *data)
+					 u16 *data)
 {
 	s32 ret_val;
 
@@ -2519,7 +2532,7 @@ out:
  *  Reads a single byte from the NVM using the flash access registers.
  **/
 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
-                                         u8 *data)
+					 u8 *data)
 {
 	s32 ret_val = E1000_SUCCESS;
 	u16 word = 0;
@@ -2544,7 +2557,7 @@ out:
  *  Reads a byte or word from the NVM using the flash access registers.
  **/
 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
-                                         u8 size, u16 *data)
+					 u8 size, u16 *data)
 {
 	union ich8_hws_flash_status hsfsts;
 	union ich8_hws_flash_ctrl hsflctl;
@@ -2559,7 +2572,7 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 		goto out;
 
 	flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
-	                    hw->nvm.flash_base_addr;
+			    hw->nvm.flash_base_addr;
 
 	do {
 		usec_delay(1);
@@ -2577,7 +2590,7 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 		E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
 
 		ret_val = e1000_flash_cycle_ich8lan(hw,
-		                                ICH_FLASH_READ_COMMAND_TIMEOUT);
+						ICH_FLASH_READ_COMMAND_TIMEOUT);
 
 		/*
 		 * Check if FCERR is set to 1, if set to 1, clear it
@@ -2600,13 +2613,12 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 			 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
 			 */
 			hsfsts.regval = E1000_READ_FLASH_REG16(hw,
-			                                      ICH_FLASH_HSFSTS);
+							      ICH_FLASH_HSFSTS);
 			if (hsfsts.hsf_status.flcerr == 1) {
 				/* Repeat for some time before giving up. */
 				continue;
 			} else if (hsfsts.hsf_status.flcdone == 0) {
-				DEBUGOUT("Timeout error - flash cycle "
-				         "did not complete.");
+				DEBUGOUT("Timeout error - flash cycle did not complete.\n");
 				break;
 			}
 		}
@@ -2626,7 +2638,7 @@ out:
  *  Writes a byte or word to the NVM using the flash access registers.
  **/
 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
-                                   u16 *data)
+				   u16 *data)
 {
 	struct e1000_nvm_info *nvm = &hw->nvm;
 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
@@ -2720,8 +2732,8 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
 			data = dev_spec->shadow_ram[i].value;
 		} else {
 			ret_val = e1000_read_flash_word_ich8lan(hw, i +
-			                                        old_bank_offset,
-			                                        &data);
+								old_bank_offset,
+								&data);
 			if (ret_val)
 				break;
 		}
@@ -2743,15 +2755,15 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
 		usec_delay(100);
 		/* Write the bytes to the new bank. */
 		ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
-		                                               act_offset,
-		                                               (u8)data);
+							       act_offset,
+							       (u8)data);
 		if (ret_val)
 			break;
 
 		usec_delay(100);
 		ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
-		                                          act_offset + 1,
-		                                          (u8)(data >> 8));
+							  act_offset + 1,
+							  (u8)(data >> 8));
 		if (ret_val)
 			break;
 	}
@@ -2778,8 +2790,8 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
 
 	data &= 0xBFFF;
 	ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
-	                                               act_offset * 2 + 1,
-	                                               (u8)(data >> 8));
+						       act_offset * 2 + 1,
+						       (u8)(data >> 8));
 	if (ret_val)
 		goto release;
 
@@ -2870,7 +2882,7 @@ out:
  *  Writes one/two bytes to the NVM using the flash access registers.
  **/
 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
-                                          u8 size, u16 data)
+					  u8 size, u16 data)
 {
 	union ich8_hws_flash_status hsfsts;
 	union ich8_hws_flash_ctrl hsflctl;
@@ -2886,7 +2898,7 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 		goto out;
 
 	flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
-	                    hw->nvm.flash_base_addr;
+			    hw->nvm.flash_base_addr;
 
 	do {
 		usec_delay(1);
@@ -2915,7 +2927,7 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 		 * and try the whole sequence a few more times else done
 		 */
 		ret_val = e1000_flash_cycle_ich8lan(hw,
-		                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
+					       ICH_FLASH_WRITE_COMMAND_TIMEOUT);
 		if (ret_val == E1000_SUCCESS)
 			break;
 
@@ -2930,8 +2942,7 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 			/* Repeat for some time before giving up. */
 			continue;
 		if (hsfsts.hsf_status.flcdone == 0) {
-			DEBUGOUT("Timeout error - flash cycle "
-				 "did not complete.");
+			DEBUGOUT("Timeout error - flash cycle did not complete.\n");
 			break;
 		}
 	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
@@ -2949,7 +2960,7 @@ out:
  *  Writes a single byte to the NVM using the flash access registers.
  **/
 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
-                                          u8 data)
+					  u8 data)
 {
 	u16 word = (u16)data;
 
@@ -2968,7 +2979,7 @@ static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
  *  Goes through a retry algorithm before giving up.
  **/
 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
-                                                u32 offset, u8 byte)
+						u32 offset, u8 byte)
 {
 	s32 ret_val;
 	u16 program_retries;
@@ -3071,10 +3082,10 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
 			 * Cycle field in hw flash control
 			 */
 			hsflctl.regval = E1000_READ_FLASH_REG16(hw,
-			                                      ICH_FLASH_HSFCTL);
+							      ICH_FLASH_HSFCTL);
 			hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
 			E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
-			                        hsflctl.regval);
+						hsflctl.regval);
 
 			/*
 			 * Write the last 24 bits of an index within the
@@ -3083,10 +3094,10 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
 			 */
 			flash_linear_addr += (j * sector_size);
 			E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
-			                      flash_linear_addr);
+					      flash_linear_addr);
 
 			ret_val = e1000_flash_cycle_ich8lan(hw,
-			                       ICH_FLASH_ERASE_COMMAND_TIMEOUT);
+					       ICH_FLASH_ERASE_COMMAND_TIMEOUT);
 			if (ret_val == E1000_SUCCESS)
 				break;
 
@@ -3130,8 +3141,7 @@ static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
 		goto out;
 	}
 
-	if (*data == ID_LED_RESERVED_0000 ||
-	    *data == ID_LED_RESERVED_FFFF)
+	if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
 		*data = ID_LED_DEFAULT_ICH8LAN;
 
 out:
@@ -3218,7 +3228,7 @@ out:
  *  @hw: pointer to the HW structure
  *
  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
- *  register, so the bus width is hard coded.
+ *  register, so the the bus width is hard coded.
  **/
 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
 {
@@ -3320,10 +3330,11 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
 	ret_val = e1000_acquire_swflag_ich8lan(hw);
 	DEBUGOUT("Issuing a global reset to ich8lan\n");
 	E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
+	/* cannot issue a flush here because it hangs the hardware */
 	msec_delay(20);
 
 	if (!ret_val)
-		e1000_release_swflag_ich8lan(hw);
+		E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
 
 	if (ctrl & E1000_CTRL_PHY_RST) {
 		ret_val = hw->phy.ops.get_cfg_done(hw);
@@ -3393,11 +3404,13 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
 
 	/*
 	 * The 82578 Rx buffer will stall if wakeup is enabled in host and
-	 * the ME.  Reading the BM_WUC register will clear the host wakeup bit.
+	 * the ME.  Disable wakeup by clearing the host wakeup bit.
 	 * Reset the phy after disabling host wakeup to reset the Rx buffer.
 	 */
 	if (hw->phy.type == e1000_phy_82578) {
-		hw->phy.ops.read_reg(hw, BM_WUC, &i);
+		hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
+		i &= ~BM_WUC_HOST_WU_BIT;
+		hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
 		ret_val = e1000_phy_hw_reset_ich8lan(hw);
 		if (ret_val)
 			return ret_val;
@@ -3411,13 +3424,13 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
 	txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
 		 E1000_TXDCTL_FULL_TX_DESC_WB;
 	txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
-	         E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
+		 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
 	E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
 	txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
 	txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
 		 E1000_TXDCTL_FULL_TX_DESC_WB;
 	txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
-	         E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
+		 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
 	E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
 
 	/*
@@ -3557,8 +3570,8 @@ static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
 		E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
 
 		ret_val = hw->phy.ops.write_reg(hw,
-		                             PHY_REG(BM_PORT_CTRL_PAGE, 27),
-		                             hw->fc.pause_time);
+					     PHY_REG(BM_PORT_CTRL_PAGE, 27),
+					     hw->fc.pause_time);
 		if (ret_val)
 			goto out;
 	}
@@ -3596,18 +3609,18 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
 	 * this fixes erroneous timeouts at 10Mbps.
 	 */
 	ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
-	                                       0xFFFF);
+					       0xFFFF);
 	if (ret_val)
 		goto out;
 	ret_val = e1000_read_kmrn_reg_generic(hw,
-	                                      E1000_KMRNCTRLSTA_INBAND_PARAM,
-	                                      &reg_data);
+					      E1000_KMRNCTRLSTA_INBAND_PARAM,
+					      &reg_data);
 	if (ret_val)
 		goto out;
 	reg_data |= 0x3F;
 	ret_val = e1000_write_kmrn_reg_generic(hw,
-	                                       E1000_KMRNCTRLSTA_INBAND_PARAM,
-	                                       reg_data);
+					       E1000_KMRNCTRLSTA_INBAND_PARAM,
+					       reg_data);
 	if (ret_val)
 		goto out;
 
@@ -3631,7 +3644,7 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
 		break;
 	case e1000_phy_ife:
 		ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
-		                               &reg_data);
+					       &reg_data);
 		if (ret_val)
 			goto out;
 
@@ -3650,7 +3663,7 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
 			break;
 		}
 		ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
-		                                reg_data);
+						reg_data);
 		if (ret_val)
 			goto out;
 		break;
@@ -3674,7 +3687,7 @@ out:
  *  gigabit speeds.
  **/
 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
-                                          u16 *duplex)
+					  u16 *duplex)
 {
 	s32 ret_val;
 
@@ -3756,7 +3769,7 @@ static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
 	/* Disable GigE link negotiation */
 	phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
 	phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
-	             E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
+		     E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
 	E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
 
 	/*
@@ -3781,7 +3794,7 @@ out:
  *  /disabled - FALSE).
  **/
 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
-                                                 bool state)
+						 bool state)
 {
 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 
@@ -3823,7 +3836,7 @@ void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
 		/* Disable link */
 		reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
 		reg |= (E1000_PHY_CTRL_GBE_DISABLE |
-		        E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
+			E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
 		E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
 
 		/*
@@ -3837,7 +3850,7 @@ void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
 		hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
 		data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
 		hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
-		                   data | IGP3_VR_CTRL_MODE_SHUTDOWN);
+				      data | IGP3_VR_CTRL_MODE_SHUTDOWN);
 
 		/* Read it back and test */
 		hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
@@ -3863,7 +3876,7 @@ out:
  *  LPLU, Gig disable, MDIC PHY reset):
  *    1) Set Kumeran Near-end loopback
  *    2) Clear Kumeran Near-end loopback
- *  Should only be called for ICH8[m] devices with IGP_3 Phy.
+ *  Should only be called for ICH8[m] devices with any 1G Phy.
  **/
 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
 {
@@ -3873,51 +3886,54 @@ void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
 	DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
 
 	if ((hw->mac.type != e1000_ich8lan) ||
-	    (hw->phy.type != e1000_phy_igp_3))
+	    (hw->phy.type == e1000_phy_ife))
 		goto out;
 
 	ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
-	                                      &reg_data);
+					      &reg_data);
 	if (ret_val)
 		goto out;
 	reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
 	ret_val = e1000_write_kmrn_reg_generic(hw,
-	                                       E1000_KMRNCTRLSTA_DIAG_OFFSET,
-	                                       reg_data);
+					       E1000_KMRNCTRLSTA_DIAG_OFFSET,
+					       reg_data);
 	if (ret_val)
 		goto out;
 	reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
 	ret_val = e1000_write_kmrn_reg_generic(hw,
-	                                       E1000_KMRNCTRLSTA_DIAG_OFFSET,
-	                                       reg_data);
+					       E1000_KMRNCTRLSTA_DIAG_OFFSET,
+					       reg_data);
 out:
 	return;
 }
 
 /**
- *  e1000_disable_gig_wol_ich8lan - disable gig during WoL
+ *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
  *  @hw: pointer to the HW structure
  *
  *  During S0 to Sx transition, it is possible the link remains at gig
  *  instead of negotiating to a lower speed.  Before going to Sx, set
- *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
- *  to a lower speed.
- *
- *  Should only be called for applicable parts.
+ *  'Gig Disable' to force link speed negotiation to a lower speed based on
+ *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
+ *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
+ *  needs to be written.
  **/
-void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw)
+void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
 {
 	u32 phy_ctrl;
 	s32 ret_val;
 
-	DEBUGFUNC("e1000_disable_gig_wol_ich8lan");
+	DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
 
 	phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
-	phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
+	phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
 	E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
+	if (hw->mac.type == e1000_ich8lan)
+		e1000_gig_downshift_workaround_ich8lan(hw);
 
 	if (hw->mac.type >= e1000_pchlan) {
 		e1000_oem_bits_config_ich8lan(hw, FALSE);
+		e1000_phy_hw_reset_ich8lan(hw);
 		ret_val = hw->phy.ops.acquire(hw);
 		if (ret_val)
 			return;
@@ -3929,6 +3945,58 @@ void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw)
 }
 
 /**
+ *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
+ *  @hw: pointer to the HW structure
+ *
+ *  During Sx to S0 transitions on non-managed devices or managed devices
+ *  on which PHY resets are not blocked, if the PHY registers cannot be
+ *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
+ *  the PHY.
+ **/
+void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
+{
+	u16 phy_id1, phy_id2;
+	s32 ret_val;
+
+	DEBUGFUNC("e1000_resume_workarounds_pchlan");
+
+	if ((hw->mac.type != e1000_pch2lan) ||
+	    hw->phy.ops.check_reset_block(hw))
+		return;
+
+	ret_val = hw->phy.ops.acquire(hw);
+	if (ret_val) {
+		DEBUGOUT("Failed to acquire PHY semaphore in resume\n");
+		return;
+	}
+
+	/* Test access to the PHY registers by reading the ID regs */
+	ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_id1);
+	if (ret_val)
+		goto release;
+	ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_id2);
+	if (ret_val)
+		goto release;
+
+	if (hw->phy.id == ((u32)(phy_id1 << 16) |
+			   (u32)(phy_id2 & PHY_REVISION_MASK)))
+		goto release;
+
+	e1000_toggle_lanphypc_value_ich8lan(hw);
+
+	hw->phy.ops.release(hw);
+	msec_delay(50);
+	hw->phy.ops.reset(hw);
+	msec_delay(50);
+	return;
+
+release:
+	hw->phy.ops.release(hw);
+
+	return;
+}
+
+/**
  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
  *  @hw: pointer to the HW structure
  *
@@ -3940,7 +4008,7 @@ static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
 
 	if (hw->phy.type == e1000_phy_ife)
 		return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
-		                             0);
+					     0);
 
 	E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
 	return E1000_SUCCESS;
@@ -3958,7 +4026,7 @@ static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
 
 	if (hw->phy.type == e1000_phy_ife)
 		return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
-		                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
+				(IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
 
 	E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
 	return E1000_SUCCESS;
@@ -3976,7 +4044,7 @@ static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
 
 	if (hw->phy.type == e1000_phy_ife)
 		return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
-		               (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
+			       (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
 
 	E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
 	return E1000_SUCCESS;
@@ -3993,7 +4061,7 @@ static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
 	DEBUGFUNC("e1000_setup_led_pchlan");
 
 	return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
-					(u16)hw->mac.ledctl_mode1);
+				     (u16)hw->mac.ledctl_mode1);
 }
 
 /**
@@ -4007,7 +4075,7 @@ static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
 	DEBUGFUNC("e1000_cleanup_led_pchlan");
 
 	return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
-					(u16)hw->mac.ledctl_default);
+				     (u16)hw->mac.ledctl_default);
 }
 
 /**
@@ -4165,6 +4233,7 @@ static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
 {
 	u16 phy_data;
+	s32 ret_val;
 
 	DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
 
@@ -4188,20 +4257,29 @@ static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
 	if ((hw->phy.type == e1000_phy_82578) ||
 	    (hw->phy.type == e1000_phy_82579) ||
 	    (hw->phy.type == e1000_phy_82577)) {
-		hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
-		hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
-		hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
-		hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
-		hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
-		hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
-		hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
-		hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
-		hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
-		hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
-		hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
-		hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
-		hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
-		hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
+		ret_val = hw->phy.ops.acquire(hw);
+		if (ret_val)
+			return;
+		ret_val = hw->phy.ops.set_page(hw,
+					       HV_STATS_PAGE << IGP_PAGE_SHIFT);
+		if (ret_val)
+			goto release;
+		hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
+		hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
+		hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
+		hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
+		hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
+		hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
+		hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
+		hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
+		hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
+		hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
+		hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
+		hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
+		hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
+		hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
+release:
+		hw->phy.ops.release(hw);
 	}
 }
 
diff --git a/sys/dev/e1000/e1000_ich8lan.h b/sys/dev/e1000/e1000_ich8lan.h
index 200e4090..2eccb30 100644
--- a/sys/dev/e1000/e1000_ich8lan.h
+++ b/sys/dev/e1000/e1000_ich8lan.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -35,182 +35,204 @@
 #ifndef _E1000_ICH8LAN_H_
 #define _E1000_ICH8LAN_H_
 
-#define ICH_FLASH_GFPREG                 0x0000
-#define ICH_FLASH_HSFSTS                 0x0004
-#define ICH_FLASH_HSFCTL                 0x0006
-#define ICH_FLASH_FADDR                  0x0008
-#define ICH_FLASH_FDATA0                 0x0010
+#define ICH_FLASH_GFPREG		0x0000
+#define ICH_FLASH_HSFSTS		0x0004
+#define ICH_FLASH_HSFCTL		0x0006
+#define ICH_FLASH_FADDR			0x0008
+#define ICH_FLASH_FDATA0		0x0010
 
 /* Requires up to 10 seconds when MNG might be accessing part. */
-#define ICH_FLASH_READ_COMMAND_TIMEOUT   10000000
-#define ICH_FLASH_WRITE_COMMAND_TIMEOUT  10000000
-#define ICH_FLASH_ERASE_COMMAND_TIMEOUT  10000000
-#define ICH_FLASH_LINEAR_ADDR_MASK       0x00FFFFFF
-#define ICH_FLASH_CYCLE_REPEAT_COUNT     10
+#define ICH_FLASH_READ_COMMAND_TIMEOUT	10000000
+#define ICH_FLASH_WRITE_COMMAND_TIMEOUT	10000000
+#define ICH_FLASH_ERASE_COMMAND_TIMEOUT	10000000
+#define ICH_FLASH_LINEAR_ADDR_MASK	0x00FFFFFF
+#define ICH_FLASH_CYCLE_REPEAT_COUNT	10
 
-#define ICH_CYCLE_READ                   0
-#define ICH_CYCLE_WRITE                  2
-#define ICH_CYCLE_ERASE                  3
+#define ICH_CYCLE_READ			0
+#define ICH_CYCLE_WRITE			2
+#define ICH_CYCLE_ERASE			3
 
-#define FLASH_GFPREG_BASE_MASK           0x1FFF
-#define FLASH_SECTOR_ADDR_SHIFT          12
+#define FLASH_GFPREG_BASE_MASK		0x1FFF
+#define FLASH_SECTOR_ADDR_SHIFT		12
 
-#define ICH_FLASH_SEG_SIZE_256           256
-#define ICH_FLASH_SEG_SIZE_4K            4096
-#define ICH_FLASH_SEG_SIZE_8K            8192
-#define ICH_FLASH_SEG_SIZE_64K           65536
-#define ICH_FLASH_SECTOR_SIZE            4096
+#define ICH_FLASH_SEG_SIZE_256		256
+#define ICH_FLASH_SEG_SIZE_4K		4096
+#define ICH_FLASH_SEG_SIZE_8K		8192
+#define ICH_FLASH_SEG_SIZE_64K		65536
+#define ICH_FLASH_SECTOR_SIZE		4096
 
-#define ICH_FLASH_REG_MAPSIZE            0x00A0
+#define ICH_FLASH_REG_MAPSIZE		0x00A0
 
-#define E1000_ICH_FWSM_RSPCIPHY          0x00000040 /* Reset PHY on PCI Reset */
-#define E1000_ICH_FWSM_DISSW             0x10000000 /* FW Disables SW Writes */
+#define E1000_ICH_FWSM_RSPCIPHY		0x00000040 /* Reset PHY on PCI Reset */
+#define E1000_ICH_FWSM_DISSW		0x10000000 /* FW Disables SW Writes */
 /* FW established a valid mode */
-#define E1000_ICH_FWSM_FW_VALID          0x00008000
+#define E1000_ICH_FWSM_FW_VALID		0x00008000
+#define E1000_ICH_FWSM_PCIM2PCI		0x01000000 /* ME PCIm-to-PCI active */
+#define E1000_ICH_FWSM_PCIM2PCI_COUNT	2000
 
-#define E1000_ICH_MNG_IAMT_MODE          0x2
+#define E1000_ICH_MNG_IAMT_MODE		0x2
 
-#define E1000_FWSM_PROXY_MODE            0x00000008 /* FW is in proxy mode */
+#define E1000_FWSM_PROXY_MODE		0x00000008 /* FW is in proxy mode */
+#define E1000_FWSM_MEMC			0x00000010 /* ME Messaging capable */
 
 /* Shared Receive Address Registers */
-#define E1000_SHRAL(_i)  (0x05438 + ((_i) * 8))
-#define E1000_SHRAH(_i)  (0x0543C + ((_i) * 8))
-#define E1000_SHRAH_AV   0x80000000 /* Addr Valid bit */
-#define E1000_SHRAH_MAV  0x40000000 /* Multicast Addr Valid bit */
-
-#define E1000_H2ME             0x05B50    /* Host to ME */
-#define E1000_H2ME_LSECREQ     0x00000001 /* Linksec Request */
-#define E1000_H2ME_LSECA       0x00000002 /* Linksec Active */
-#define E1000_H2ME_LSECSF      0x00000004 /* Linksec Failed */
-#define E1000_H2ME_LSECD       0x00000008 /* Linksec Disabled */
-#define E1000_H2ME_SLCAPD      0x00000010 /* Start LCAPD */
-#define E1000_H2ME_IPV4_ARP_EN 0x00000020 /* Arp Offload enable bit */
-#define E1000_H2ME_IPV6_NS_EN  0x00000040 /* NS Offload enable bit */
-
-#define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
-                                 (ID_LED_OFF1_OFF2 <<  8) | \
-                                 (ID_LED_OFF1_ON2  <<  4) | \
-                                 (ID_LED_DEF1_DEF2))
-
-#define E1000_ICH_NVM_SIG_WORD           0x13
-#define E1000_ICH_NVM_SIG_MASK           0xC000
-#define E1000_ICH_NVM_VALID_SIG_MASK     0xC0
-#define E1000_ICH_NVM_SIG_VALUE          0x80
-
-#define E1000_ICH8_LAN_INIT_TIMEOUT      1500
-
-#define E1000_FEXTNVM_SW_CONFIG        1
-#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M */
-
-#define E1000_FEXTNVM4_BEACON_DURATION_MASK    0x7
-#define E1000_FEXTNVM4_BEACON_DURATION_8USEC   0x7
-#define E1000_FEXTNVM4_BEACON_DURATION_16USEC  0x3
-
-#define PCIE_ICH8_SNOOP_ALL   PCIE_NO_SNOOP_ALL
-
-#define E1000_ICH_RAR_ENTRIES            7
-#define E1000_PCH2_RAR_ENTRIES           5 /* RAR[0], SHRA[0-3] */
-
-#define PHY_PAGE_SHIFT 5
-#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
-                           ((reg) & MAX_PHY_REG_ADDRESS))
-#define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
-#define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
-#define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */
-#define IGP3_PM_CTRL    PHY_REG(769, 20) /* Power Management Control */
-
-#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS         0x0002
-#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
-#define IGP3_VR_CTRL_MODE_SHUTDOWN           0x0200
-#define IGP3_PM_CTRL_FORCE_PWR_DOWN          0x0020
+#define E1000_SHRAL(_i)		(0x05438 + ((_i) * 8))
+#define E1000_SHRAH(_i)		(0x0543C + ((_i) * 8))
+#define E1000_SHRAH_AV		0x80000000 /* Addr Valid bit */
+#define E1000_SHRAH_MAV		0x40000000 /* Multicast Addr Valid bit */
+
+#define E1000_H2ME		0x05B50    /* Host to ME */
+#define E1000_H2ME_LSECREQ	0x00000001 /* Linksec Request */
+#define E1000_H2ME_LSECA	0x00000002 /* Linksec Active */
+#define E1000_H2ME_LSECSF	0x00000004 /* Linksec Failed */
+#define E1000_H2ME_LSECD	0x00000008 /* Linksec Disabled */
+#define E1000_H2ME_SLCAPD	0x00000010 /* Start LCAPD */
+#define E1000_H2ME_IPV4_ARP_EN	0x00000020 /* Arp Offload enable bit */
+#define E1000_H2ME_IPV6_NS_EN	0x00000040 /* NS Offload enable bit */
+
+#define ID_LED_DEFAULT_ICH8LAN	((ID_LED_DEF1_DEF2 << 12) | \
+				 (ID_LED_OFF1_OFF2 <<  8) | \
+				 (ID_LED_OFF1_ON2  <<  4) | \
+				 (ID_LED_DEF1_DEF2))
+
+#define E1000_ICH_NVM_SIG_WORD		0x13
+#define E1000_ICH_NVM_SIG_MASK		0xC000
+#define E1000_ICH_NVM_VALID_SIG_MASK	0xC0
+#define E1000_ICH_NVM_SIG_VALUE		0x80
+
+#define E1000_ICH8_LAN_INIT_TIMEOUT	1500
+
+#define E1000_FEXTNVM_SW_CONFIG		1
+#define E1000_FEXTNVM_SW_CONFIG_ICH8M	(1 << 27) /* Bit redefined for ICH8M */
+
+#define E1000_FEXTNVM4_BEACON_DURATION_MASK	0x7
+#define E1000_FEXTNVM4_BEACON_DURATION_8USEC	0x7
+#define E1000_FEXTNVM4_BEACON_DURATION_16USEC	0x3
+
+#define PCIE_ICH8_SNOOP_ALL	PCIE_NO_SNOOP_ALL
+
+#define E1000_ICH_RAR_ENTRIES	7
+#define E1000_PCH2_RAR_ENTRIES	5 /* RAR[0], SHRA[0-3] */
+
+#define PHY_PAGE_SHIFT		5
+#define PHY_REG(page, reg)	(((page) << PHY_PAGE_SHIFT) | \
+				 ((reg) & MAX_PHY_REG_ADDRESS))
+#define IGP3_KMRN_DIAG		PHY_REG(770, 19) /* KMRN Diagnostic */
+#define IGP3_VR_CTRL		PHY_REG(776, 18) /* Voltage Regulator Control */
+#define IGP3_CAPABILITY		PHY_REG(776, 19) /* Capability */
+#define IGP3_PM_CTRL		PHY_REG(769, 20) /* Power Management Control */
+
+#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS		0x0002
+#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK	0x0300
+#define IGP3_VR_CTRL_MODE_SHUTDOWN		0x0200
+#define IGP3_PM_CTRL_FORCE_PWR_DOWN		0x0020
 
 /* PHY Wakeup Registers and defines */
-#define BM_RCTL         PHY_REG(BM_WUC_PAGE, 0)
-#define BM_WUC          PHY_REG(BM_WUC_PAGE, 1)
-#define BM_WUFC         PHY_REG(BM_WUC_PAGE, 2)
-#define BM_WUS          PHY_REG(BM_WUC_PAGE, 3)
-#define BM_RAR_L(_i)    (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
-#define BM_RAR_M(_i)    (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
-#define BM_RAR_H(_i)    (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
-#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
-#define BM_MTA(_i)      (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
-#define BM_IPAV         (BM_PHY_REG(BM_WUC_PAGE, 64))
-#define BM_IP4AT_L(_i)  (BM_PHY_REG(BM_WUC_PAGE, 82 + ((_i) * 2)))
-#define BM_IP4AT_H(_i)  (BM_PHY_REG(BM_WUC_PAGE, 83 + ((_i) * 2)))
-
-#define BM_SHRAL_LOWER(_i) (BM_PHY_REG(BM_WUC_PAGE, 44 + ((_i) * 4)))
-#define BM_SHRAL_UPPER(_i) (BM_PHY_REG(BM_WUC_PAGE, 45 + ((_i) * 4)))
-#define BM_SHRAH_LOWER(_i) (BM_PHY_REG(BM_WUC_PAGE, 46 + ((_i) * 4)))
-#define BM_SHRAH_UPPER(_i) (BM_PHY_REG(BM_WUC_PAGE, 47 + ((_i) * 4)))
-
-#define BM_RCTL_UPE           0x0001          /* Unicast Promiscuous Mode */
-#define BM_RCTL_MPE           0x0002          /* Multicast Promiscuous Mode */
-#define BM_RCTL_MO_SHIFT      3               /* Multicast Offset Shift */
-#define BM_RCTL_MO_MASK       (3 << 3)        /* Multicast Offset Mask */
-#define BM_RCTL_BAM           0x0020          /* Broadcast Accept Mode */
-#define BM_RCTL_PMCF          0x0040          /* Pass MAC Control Frames */
-#define BM_RCTL_RFCE          0x0080          /* Rx Flow Control Enable */
-
-#define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
-#define HV_MUX_DATA_CTRL               PHY_REG(776, 16)
-#define HV_MUX_DATA_CTRL_GEN_TO_MAC    0x0400
-#define HV_MUX_DATA_CTRL_FORCE_SPEED   0x0004
-#define HV_SCC_UPPER            PHY_REG(778, 16) /* Single Collision Count */
-#define HV_SCC_LOWER            PHY_REG(778, 17)
-#define HV_ECOL_UPPER           PHY_REG(778, 18) /* Excessive Collision Count */
-#define HV_ECOL_LOWER           PHY_REG(778, 19)
-#define HV_MCC_UPPER            PHY_REG(778, 20) /* Multiple Collision Count */
-#define HV_MCC_LOWER            PHY_REG(778, 21)
-#define HV_LATECOL_UPPER        PHY_REG(778, 23) /* Late Collision Count */
-#define HV_LATECOL_LOWER        PHY_REG(778, 24)
-#define HV_COLC_UPPER           PHY_REG(778, 25) /* Collision Count */
-#define HV_COLC_LOWER           PHY_REG(778, 26)
-#define HV_DC_UPPER             PHY_REG(778, 27) /* Defer Count */
-#define HV_DC_LOWER             PHY_REG(778, 28)
-#define HV_TNCRS_UPPER          PHY_REG(778, 29) /* Transmit with no CRS */
-#define HV_TNCRS_LOWER          PHY_REG(778, 30)
-
-#define E1000_FCRTV_PCH     0x05F40 /* PCH Flow Control Refresh Timer Value */
-
-#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
-#define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
+#define BM_PORT_GEN_CFG		PHY_REG(BM_PORT_CTRL_PAGE, 17)
+#define BM_RCTL			PHY_REG(BM_WUC_PAGE, 0)
+#define BM_WUC			PHY_REG(BM_WUC_PAGE, 1)
+#define BM_WUFC			PHY_REG(BM_WUC_PAGE, 2)
+#define BM_WUS			PHY_REG(BM_WUC_PAGE, 3)
+#define BM_RAR_L(_i)		(BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
+#define BM_RAR_M(_i)		(BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
+#define BM_RAR_H(_i)		(BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
+#define BM_RAR_CTRL(_i)		(BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
+#define BM_MTA(_i)		(BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
+#define BM_IPAV			(BM_PHY_REG(BM_WUC_PAGE, 64))
+#define BM_IP4AT_L(_i)		(BM_PHY_REG(BM_WUC_PAGE, 82 + ((_i) * 2)))
+#define BM_IP4AT_H(_i)		(BM_PHY_REG(BM_WUC_PAGE, 83 + ((_i) * 2)))
+
+#define BM_SHRAL_LOWER(_i)	(BM_PHY_REG(BM_WUC_PAGE, 44 + ((_i) * 4)))
+#define BM_SHRAL_UPPER(_i)	(BM_PHY_REG(BM_WUC_PAGE, 45 + ((_i) * 4)))
+#define BM_SHRAH_LOWER(_i)	(BM_PHY_REG(BM_WUC_PAGE, 46 + ((_i) * 4)))
+#define BM_SHRAH_UPPER(_i)	(BM_PHY_REG(BM_WUC_PAGE, 47 + ((_i) * 4)))
+
+#define BM_RCTL_UPE		0x0001 /* Unicast Promiscuous Mode */
+#define BM_RCTL_MPE		0x0002 /* Multicast Promiscuous Mode */
+#define BM_RCTL_MO_SHIFT	3      /* Multicast Offset Shift */
+#define BM_RCTL_MO_MASK		(3 << 3) /* Multicast Offset Mask */
+#define BM_RCTL_BAM		0x0020 /* Broadcast Accept Mode */
+#define BM_RCTL_PMCF		0x0040 /* Pass MAC Control Frames */
+#define BM_RCTL_RFCE		0x0080 /* Rx Flow Control Enable */
+
+#define HV_LED_CONFIG		PHY_REG(768, 30) /* LED Configuration */
+#define HV_MUX_DATA_CTRL	PHY_REG(776, 16)
+#define HV_MUX_DATA_CTRL_GEN_TO_MAC	0x0400
+#define HV_MUX_DATA_CTRL_FORCE_SPEED	0x0004
+#define HV_STATS_PAGE	778
+#define HV_SCC_UPPER	PHY_REG(HV_STATS_PAGE, 16) /* Single Collision Count */
+#define HV_SCC_LOWER	PHY_REG(HV_STATS_PAGE, 17)
+#define HV_ECOL_UPPER	PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. Count */
+#define HV_ECOL_LOWER	PHY_REG(HV_STATS_PAGE, 19)
+#define HV_MCC_UPPER	PHY_REG(HV_STATS_PAGE, 20) /* Multiple Coll. Count */
+#define HV_MCC_LOWER	PHY_REG(HV_STATS_PAGE, 21)
+#define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision Count */
+#define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
+#define HV_COLC_UPPER	PHY_REG(HV_STATS_PAGE, 25) /* Collision Count */
+#define HV_COLC_LOWER	PHY_REG(HV_STATS_PAGE, 26)
+#define HV_DC_UPPER	PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */
+#define HV_DC_LOWER	PHY_REG(HV_STATS_PAGE, 28)
+#define HV_TNCRS_UPPER	PHY_REG(HV_STATS_PAGE, 29) /* Transmit with no CRS */
+#define HV_TNCRS_LOWER	PHY_REG(HV_STATS_PAGE, 30)
+
+#define E1000_FCRTV_PCH	0x05F40 /* PCH Flow Control Refresh Timer Value */
+
+/*
+ * For ICH, the name used for NVM word 17h is LED1 Config.
+ * For PCH, the word was re-named to OEM Config.
+ */
+#define E1000_NVM_LED1_CONFIG		0x17   /* NVM LED1/LPLU Config Word */
+#define E1000_NVM_LED1_CONFIG_LPLU_NONDOA 0x0400 /* NVM LPLU in non-D0a Bit */
+#define E1000_NVM_OEM_CONFIG		E1000_NVM_LED1_CONFIG
+#define E1000_NVM_OEM_CONFIG_LPLU_NONDOA E1000_NVM_LED1_CONFIG_LPLU_NONDOA
+
+#define E1000_NVM_K1_CONFIG	0x1B /* NVM K1 Config Word */
+#define E1000_NVM_K1_ENABLE	0x1  /* NVM Enable K1 bit */
 
 /* SMBus Address Phy Register */
-#define HV_SMB_ADDR            PHY_REG(768, 26)
-#define HV_SMB_ADDR_MASK       0x007F
-#define HV_SMB_ADDR_PEC_EN     0x0200
-#define HV_SMB_ADDR_VALID      0x0080
+#define HV_SMB_ADDR		PHY_REG(768, 26)
+#define HV_SMB_ADDR_MASK	0x007F
+#define HV_SMB_ADDR_PEC_EN	0x0200
+#define HV_SMB_ADDR_VALID	0x0080
 
 /* Strapping Option Register - RO */
-#define E1000_STRAP                     0x0000C
-#define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
-#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
+#define E1000_STRAP			0x0000C
+#define E1000_STRAP_SMBUS_ADDRESS_MASK	0x00FE0000
+#define E1000_STRAP_SMBUS_ADDRESS_SHIFT	17
 
 /* OEM Bits Phy Register */
-#define HV_OEM_BITS            PHY_REG(768, 25)
-#define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
-#define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
-#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
+#define HV_OEM_BITS		PHY_REG(768, 25)
+#define HV_OEM_BITS_LPLU	0x0004 /* Low Power Link Up */
+#define HV_OEM_BITS_GBE_DIS	0x0040 /* Gigabit Disable */
+#define HV_OEM_BITS_RESTART_AN	0x0400 /* Restart Auto-negotiation */
 
-#define LCD_CFG_PHY_ADDR_BIT   0x0020 /* Phy address bit from LCD Config word */
+#define LCD_CFG_PHY_ADDR_BIT	0x0020 /* Phy addr bit from LCD Config word */
 
 /* KMRN Mode Control */
-#define HV_KMRN_MODE_CTRL       PHY_REG(769, 16)
-#define HV_KMRN_MDIO_SLOW       0x0400
+#define HV_KMRN_MODE_CTRL	PHY_REG(769, 16)
+#define HV_KMRN_MDIO_SLOW	0x0400
+
+/* KMRN FIFO Control and Status */
+#define HV_KMRN_FIFO_CTRLSTA			PHY_REG(770, 16)
+#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK	0x7000
+#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT	12
 
 /* PHY Power Management Control */
-#define HV_PM_CTRL              PHY_REG(770, 17)
+#define HV_PM_CTRL		PHY_REG(770, 17)
 
-#define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
+#define SW_FLAG_TIMEOUT		1000 /* SW Semaphore flag timeout in ms */
 
 /* PHY Low Power Idle Control */
-#define I82579_LPI_CTRL         PHY_REG(772, 20)
-#define I82579_LPI_CTRL_ENABLE_MASK     0x6000
+#define I82579_LPI_CTRL				PHY_REG(772, 20)
+#define I82579_LPI_CTRL_ENABLE_MASK		0x6000
+#define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT	0x80
 
 /* EMI Registers */
-#define I82579_EMI_ADDR         0x10
-#define I82579_EMI_DATA         0x11
-#define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */
+#define I82579_EMI_ADDR		0x10
+#define I82579_EMI_DATA		0x11
+#define I82579_LPI_UPDATE_TIMER	0x4805 /* in 40ns units + 40 ns base value */
+#define I82579_MSE_THRESHOLD	0x084F /* Mean Square Error Threshold */
+#define I82579_MSE_LINK_DOWN	0x2411 /* MSE count before dropping link */
 
 /*
  * Additional interrupts need to be handled for ICH family:
@@ -219,33 +241,32 @@
  *  EPRST = Manageability reset event
  */
 #define IMS_ICH_ENABLE_MASK (\
-    E1000_IMS_DSW   | \
-    E1000_IMS_PHYINT | \
-    E1000_IMS_EPRST)
+	E1000_IMS_DSW   | \
+	E1000_IMS_PHYINT | \
+	E1000_IMS_EPRST)
 
 /* Additional interrupt register bit definitions */
-#define E1000_ICR_LSECPNC       0x00004000          /* PN threshold - client */
-#define E1000_IMS_LSECPNC       E1000_ICR_LSECPNC   /* PN threshold - client */
-#define E1000_ICS_LSECPNC       E1000_ICR_LSECPNC   /* PN threshold - client */
+#define E1000_ICR_LSECPNC	0x00004000  /* PN threshold - client */
+#define E1000_IMS_LSECPNC	E1000_ICR_LSECPNC   /* PN threshold - client */
+#define E1000_ICS_LSECPNC	E1000_ICR_LSECPNC   /* PN threshold - client */
 
 /* Security Processing bit Indication */
-#define E1000_RXDEXT_LINKSEC_STATUS_LSECH       0x01000000
-#define E1000_RXDEXT_LINKSEC_ERROR_BIT_MASK     0x60000000
-#define E1000_RXDEXT_LINKSEC_ERROR_NO_SA_MATCH  0x20000000
-#define E1000_RXDEXT_LINKSEC_ERROR_REPLAY_ERROR 0x40000000
-#define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG      0x60000000
+#define E1000_RXDEXT_LINKSEC_STATUS_LSECH	0x01000000
+#define E1000_RXDEXT_LINKSEC_ERROR_BIT_MASK	0x60000000
+#define E1000_RXDEXT_LINKSEC_ERROR_NO_SA_MATCH	0x20000000
+#define E1000_RXDEXT_LINKSEC_ERROR_REPLAY_ERROR	0x40000000
+#define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG	0x60000000
 
 /* Receive Address Initial CRC Calculation */
-#define E1000_PCH_RAICC(_n)     (0x05F50 + ((_n) * 4))
+#define E1000_PCH_RAICC(_n)	(0x05F50 + ((_n) * 4))
 
 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
-                                                 bool state);
+						 bool state);
 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
-void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw);
+void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
+void e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
-s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_config);
-s32 e1000_hv_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
 #endif
diff --git a/sys/dev/e1000/e1000_mac.c b/sys/dev/e1000/e1000_mac.c
index b29a38a..4fc2a7c 100644
--- a/sys/dev/e1000/e1000_mac.c
+++ b/sys/dev/e1000/e1000_mac.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -177,8 +177,8 @@ s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
 	/* Bus speed */
 	if (bus->type == e1000_bus_type_pci) {
 		bus->speed = (status & E1000_STATUS_PCI66)
-		             ? e1000_bus_speed_66
-		             : e1000_bus_speed_33;
+			     ? e1000_bus_speed_66
+			     : e1000_bus_speed_33;
 	} else {
 		switch (status & E1000_STATUS_PCIX_SPEED) {
 		case E1000_STATUS_PCIX_SPEED_66:
@@ -198,8 +198,8 @@ s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
 
 	/* Bus width */
 	bus->width = (status & E1000_STATUS_BUS64)
-	             ? e1000_bus_width_64
-	             : e1000_bus_width_32;
+		     ? e1000_bus_width_64
+		     : e1000_bus_width_32;
 
 	/* Which PCI(-X) function? */
 	mac->ops.set_lan_id(hw);
@@ -226,9 +226,8 @@ s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
 
 	bus->type = e1000_bus_type_pci_express;
 
-	ret_val = e1000_read_pcie_cap_reg(hw,
-	                                  PCIE_LINK_STATUS,
-	                                  &pcie_link_status);
+	ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS,
+					  &pcie_link_status);
 	if (ret_val) {
 		bus->width = e1000_bus_width_unknown;
 		bus->speed = e1000_bus_speed_unknown;
@@ -246,8 +245,7 @@ s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
 		}
 
 		bus->width = (enum e1000_bus_width)((pcie_link_status &
-		                                PCIE_LINK_WIDTH_MASK) >>
-		                               PCIE_LINK_WIDTH_SHIFT);
+			      PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT);
 	}
 
 	mac->ops.set_lan_id(hw);
@@ -292,7 +290,7 @@ void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw)
 	if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
 		status = E1000_READ_REG(hw, E1000_STATUS);
 		bus->func = (status & E1000_STATUS_FUNC_MASK)
-		            >> E1000_STATUS_FUNC_SHIFT;
+			    >> E1000_STATUS_FUNC_SHIFT;
 	} else {
 		bus->func = 0;
 	}
@@ -352,7 +350,7 @@ void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
  *  @hw: pointer to the HW structure
  *  @rar_count: receive address registers
  *
- *  Setups the receive address registers by setting the base receive address
+ *  Setup the receive address registers by setting the base receive address
  *  register to the devices MAC address and clearing all the other receive
  *  address registers to 0.
  **/
@@ -399,23 +397,28 @@ s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
 	if (ret_val)
 		goto out;
 
-	/* Check for LOM (vs. NIC) or one of two valid mezzanine cards */
-	if (!((nvm_data & NVM_COMPAT_LOM) ||
-	      (hw->device_id == E1000_DEV_ID_82571EB_SERDES_DUAL) ||
-	      (hw->device_id == E1000_DEV_ID_82571EB_SERDES_QUAD)))
+	/* not supported on older hardware or 82573 */
+	if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573))
+		goto out;
+
+	/*
+	 * Alternate MAC address is handled by the option ROM for 82580
+	 * and newer. SW support not required.
+	 */
+	if (hw->mac.type >= e1000_82580)
 		goto out;
 
 	ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
-	                         &nvm_alt_mac_addr_offset);
+				   &nvm_alt_mac_addr_offset);
 	if (ret_val) {
 		DEBUGOUT("NVM Read Error\n");
 		goto out;
 	}
 
-	if (nvm_alt_mac_addr_offset == 0xFFFF) {
+	if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
+	    (nvm_alt_mac_addr_offset == 0x0000))
 		/* There is no Alternate MAC Address */
 		goto out;
-	}
 
 	if (hw->bus.func == E1000_FUNC_1)
 		nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
@@ -472,9 +475,8 @@ void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
 	 * HW expects these in little endian so we reverse the byte order
 	 * from network order (big endian) to little endian
 	 */
-	rar_low = ((u32) addr[0] |
-	           ((u32) addr[1] << 8) |
-	           ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
+	rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
+		   ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
 
 	rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
 
@@ -503,7 +505,7 @@ void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
  *  The caller must have a packed mc_addr_list of multicast addresses.
  **/
 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
-                                       u8 *mc_addr_list, u32 mc_addr_count)
+				       u8 *mc_addr_list, u32 mc_addr_count)
 {
 	u32 hash_value, hash_bit, hash_reg;
 	int i;
@@ -574,7 +576,7 @@ u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
 	 * values resulting from each mc_filter_type...
 	 * [0] [1] [2] [3] [4] [5]
 	 * 01  AA  00  12  34  56
-	 * LSB                 MSB
+	 * LSB		 MSB
 	 *
 	 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
 	 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
@@ -597,7 +599,7 @@ u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
 	}
 
 	hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
-	                          (((u16) mc_addr[5]) << bit_shift)));
+				  (((u16) mc_addr[5]) << bit_shift)));
 
 	return hash_value;
 }
@@ -627,9 +629,9 @@ void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
 	e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
 	e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
 	cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>
-	             PCIX_COMMAND_MMRBC_SHIFT;
+		     PCIX_COMMAND_MMRBC_SHIFT;
 	stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
-	              PCIX_STATUS_HI_MMRBC_SHIFT;
+		      PCIX_STATUS_HI_MMRBC_SHIFT;
 	if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
 		stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
 	if (cmd_mmrbc > stat_mmrbc) {
@@ -926,12 +928,10 @@ s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
 			if (rxcw & E1000_RXCW_SYNCH) {
 				if (!(rxcw & E1000_RXCW_IV)) {
 					mac->serdes_has_link = TRUE;
-					DEBUGOUT("SERDES: Link up - autoneg "
-					   "completed sucessfully.\n");
+					DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n");
 				} else {
 					mac->serdes_has_link = FALSE;
-					DEBUGOUT("SERDES: Link down - invalid"
-					   "codewords detected in autoneg.\n");
+					DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n");
 				}
 			} else {
 				mac->serdes_has_link = FALSE;
@@ -1423,8 +1423,7 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
 			goto out;
 
 		if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
-			DEBUGOUT("Copper PHY and Auto Neg "
-			         "has not completed.\n");
+			DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
 			goto out;
 		}
 
@@ -1436,11 +1435,11 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
 		 * flow control was negotiated.
 		 */
 		ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
-		                             &mii_nway_adv_reg);
+					       &mii_nway_adv_reg);
 		if (ret_val)
 			goto out;
 		ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
-		                             &mii_nway_lp_ability_reg);
+					       &mii_nway_lp_ability_reg);
 		if (ret_val)
 			goto out;
 
@@ -1485,15 +1484,14 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
 			 * of pause frames.  In this case, we had to advertise
 			 * FULL flow control because we could not advertise Rx
 			 * ONLY. Hence, we must now check to see if we need to
-			 * turn OFF  the TRANSMISSION of PAUSE frames.
+			 * turn OFF the TRANSMISSION of PAUSE frames.
 			 */
 			if (hw->fc.requested_mode == e1000_fc_full) {
 				hw->fc.current_mode = e1000_fc_full;
-				DEBUGOUT("Flow Control = FULL.\r\n");
+				DEBUGOUT("Flow Control = FULL.\n");
 			} else {
 				hw->fc.current_mode = e1000_fc_rx_pause;
-				DEBUGOUT("Flow Control = "
-				         "Rx PAUSE frames only.\r\n");
+				DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
 			}
 		}
 		/*
@@ -1505,11 +1503,11 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
 		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
 		 */
 		else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
-		          (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
-		          (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
-		          (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
+			  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
+			  (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
+			  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
 			hw->fc.current_mode = e1000_fc_tx_pause;
-			DEBUGOUT("Flow Control = Tx PAUSE frames only.\r\n");
+			DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
 		}
 		/*
 		 * For transmitting PAUSE frames ONLY.
@@ -1520,18 +1518,18 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
 		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
 		 */
 		else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
-		         (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
-		         !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
-		         (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
+			 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
+			 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
+			 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
 			hw->fc.current_mode = e1000_fc_rx_pause;
-			DEBUGOUT("Flow Control = Rx PAUSE frames only.\r\n");
+			DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
 		} else {
 			/*
 			 * Per the IEEE spec, at this point flow control
 			 * should be disabled.
 			 */
 			hw->fc.current_mode = e1000_fc_none;
-			DEBUGOUT("Flow Control = NONE.\r\n");
+			DEBUGOUT("Flow Control = NONE.\n");
 		}
 
 		/*
@@ -1573,7 +1571,7 @@ out:
  *  speed and duplex for copper connections.
  **/
 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
-                                              u16 *duplex)
+					      u16 *duplex)
 {
 	u32 status;
 
@@ -1612,7 +1610,7 @@ s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
  *  for fiber/serdes links.
  **/
 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
-                                                    u16 *speed, u16 *duplex)
+						    u16 *speed, u16 *duplex)
 {
 	DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
 
@@ -1843,11 +1841,10 @@ s32 e1000_setup_led_generic(struct e1000_hw *hw)
 		ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
 		hw->mac.ledctl_default = ledctl;
 		/* Turn off LED0 */
-		ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
-		            E1000_LEDCTL_LED0_BLINK |
-		            E1000_LEDCTL_LED0_MODE_MASK);
+		ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |
+			    E1000_LEDCTL_LED0_MODE_MASK);
 		ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
-		           E1000_LEDCTL_LED0_MODE_SHIFT);
+			   E1000_LEDCTL_LED0_MODE_SHIFT);
 		E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
 	} else if (hw->phy.media_type == e1000_media_type_copper) {
 		E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
@@ -1899,7 +1896,7 @@ s32 e1000_blink_led_generic(struct e1000_hw *hw)
 			if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
 			    E1000_LEDCTL_MODE_LED_ON)
 				ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
-				                 (i * 8));
+						 (i * 8));
 	}
 
 	E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
@@ -2090,7 +2087,8 @@ void e1000_update_adaptive_generic(struct e1000_hw *hw)
 				else
 					mac->current_ifs_val +=
 						mac->ifs_step_size;
-				E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val);
+				E1000_WRITE_REG(hw, E1000_AIT,
+						mac->current_ifs_val);
 			}
 		}
 	} else {
@@ -2141,7 +2139,7 @@ out:
  *  completion.
  **/
 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
-                                      u32 offset, u8 data)
+				      u32 offset, u8 data)
 {
 	u32 i, regvalue = 0;
 	s32 ret_val = E1000_SUCCESS;
diff --git a/sys/dev/e1000/e1000_nvm.c b/sys/dev/e1000/e1000_nvm.c
index e10ac8c..d8df089 100644
--- a/sys/dev/e1000/e1000_nvm.c
+++ b/sys/dev/e1000/e1000_nvm.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -313,8 +313,7 @@ static void e1000_standby_nvm(struct e1000_hw *hw)
 		usec_delay(nvm->delay_usec);
 
 		e1000_lower_eec_clk(hw, &eecd);
-	} else
-	if (nvm->type == e1000_nvm_eeprom_spi) {
+	} else if (nvm->type == e1000_nvm_eeprom_spi) {
 		/* Toggle CS to flush commands */
 		eecd |= E1000_EECD_CS;
 		E1000_WRITE_REG(hw, E1000_EECD, eecd);
@@ -394,13 +393,13 @@ static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
 		/* Set CS */
 		eecd |= E1000_EECD_CS;
 		E1000_WRITE_REG(hw, E1000_EECD, eecd);
-	} else
-	if (nvm->type == e1000_nvm_eeprom_spi) {
+	} else if (nvm->type == e1000_nvm_eeprom_spi) {
 		u16 timeout = NVM_MAX_RETRY_SPI;
 
 		/* Clear SK and CS */
 		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 		E1000_WRITE_REG(hw, E1000_EECD, eecd);
+		E1000_WRITE_FLUSH(hw);
 		usec_delay(1);
 
 		/*
@@ -411,7 +410,7 @@ static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
 		 */
 		while (timeout) {
 			e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
-			                         hw->nvm.opcode_bits);
+						 hw->nvm.opcode_bits);
 			spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
 			if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
 				break;
@@ -506,7 +505,7 @@ out:
  *  Reads a 16 bit word from the EEPROM.
  **/
 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
-                             u16 *data)
+			     u16 *data)
 {
 	struct e1000_nvm_info *nvm = &hw->nvm;
 	u32 i = 0;
@@ -593,7 +592,7 @@ s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 			break;
 
 		data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
-		           E1000_NVM_RW_REG_DATA);
+			   E1000_NVM_RW_REG_DATA);
 	}
 
 out:
@@ -646,7 +645,7 @@ s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 
 		/* Send the WRITE ENABLE command (8 bit opcode) */
 		e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
-		                         nvm->opcode_bits);
+					 nvm->opcode_bits);
 
 		e1000_standby_nvm(hw);
 
@@ -660,7 +659,7 @@ s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 		/* Send the Write command (8-bit opcode + addr) */
 		e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
 		e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
-		                         nvm->address_bits);
+					 nvm->address_bits);
 
 		/* Loop to allow for up to whole page write of eeprom */
 		while (widx < words) {
@@ -697,7 +696,7 @@ out:
  *  EEPROM will most likely contain an invalid checksum.
  **/
 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
-                              u16 *data)
+			      u16 *data)
 {
 	struct e1000_nvm_info *nvm = &hw->nvm;
 	s32  ret_val;
@@ -727,7 +726,7 @@ s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
 		goto release;
 
 	e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
-	                         (u16)(nvm->opcode_bits + 2));
+				 (u16)(nvm->opcode_bits + 2));
 
 	e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
 
@@ -735,10 +734,10 @@ s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
 
 	while (words_written < words) {
 		e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
-		                         nvm->opcode_bits);
+					 nvm->opcode_bits);
 
 		e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
-		                         nvm->address_bits);
+					 nvm->address_bits);
 
 		e1000_shift_out_eec_bits(hw, data[words_written], 16);
 
@@ -763,7 +762,7 @@ s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
 	}
 
 	e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
-	                         (u16)(nvm->opcode_bits + 2));
+				 (u16)(nvm->opcode_bits + 2));
 
 	e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
 
@@ -784,7 +783,7 @@ out:
  *  the value in pba_num.
  **/
 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
-                                  u32 pba_num_size)
+				  u32 pba_num_size)
 {
 	s32 ret_val;
 	u16 nvm_data;
diff --git a/sys/dev/e1000/e1000_nvm.h b/sys/dev/e1000/e1000_nvm.h
index 61ea0b1..ed23eb3 100644
--- a/sys/dev/e1000/e1000_nvm.h
+++ b/sys/dev/e1000/e1000_nvm.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -45,25 +45,23 @@ s32  e1000_acquire_nvm_generic(struct e1000_hw *hw);
 s32  e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
 s32  e1000_read_mac_addr_generic(struct e1000_hw *hw);
 s32  e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
-                                   u32 pba_num_size);
+				   u32 pba_num_size);
 s32  e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size);
 s32  e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
 s32  e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset,
-                              u16 words, u16 *data);
+			      u16 words, u16 *data);
 s32  e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words,
-                         u16 *data);
+			 u16 *data);
 s32  e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data);
 s32  e1000_validate_nvm_checksum_generic(struct e1000_hw *hw);
-s32  e1000_write_nvm_eewr(struct e1000_hw *hw, u16 offset,
-                          u16 words, u16 *data);
 s32  e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset,
-                               u16 words, u16 *data);
+			       u16 words, u16 *data);
 s32  e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words,
-                         u16 *data);
+			 u16 *data);
 s32  e1000_update_nvm_checksum_generic(struct e1000_hw *hw);
 void e1000_stop_nvm(struct e1000_hw *hw);
 void e1000_release_nvm_generic(struct e1000_hw *hw);
 
-#define E1000_STM_OPCODE  0xDB00
+#define E1000_STM_OPCODE	0xDB00
 
 #endif
diff --git a/sys/dev/e1000/e1000_osdep.h b/sys/dev/e1000/e1000_osdep.h
index 25231a7..7eb7bb6 100644
--- a/sys/dev/e1000/e1000_osdep.h
+++ b/sys/dev/e1000/e1000_osdep.h
@@ -73,9 +73,11 @@
 
 #define STATIC			static
 #define FALSE			0
-#define false			FALSE 
 #define TRUE			1
+#ifndef __bool_true_false_are_defined
+#define false			FALSE
 #define true			TRUE
+#endif
 #define CMD_MEM_WRT_INVALIDATE	0x0010  /* BIT_4 */
 #define PCI_COMMAND_REGISTER	PCIR_COMMAND
 
@@ -96,7 +98,9 @@ typedef int64_t		s64;
 typedef int32_t		s32;
 typedef int16_t		s16;
 typedef int8_t		s8;
+#ifndef __bool_true_false_are_defined
 typedef boolean_t	bool;
+#endif
 
 #define __le16		u16
 #define __le32		u32
diff --git a/sys/dev/e1000/e1000_phy.c b/sys/dev/e1000/e1000_phy.c
index 40fd2bd..ead72690 100644
--- a/sys/dev/e1000/e1000_phy.c
+++ b/sys/dev/e1000/e1000_phy.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -36,17 +36,17 @@
 
 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
-                                          u16 *data, bool read);
+					  u16 *data, bool read, bool page_set);
 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
-                                          u16 *data, bool read);
+					  u16 *data, bool read);
 
 /* Cable length tables */
 static const u16 e1000_m88_cable_length_table[] = {
 	0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
-                (sizeof(e1000_m88_cable_length_table) / \
-                 sizeof(e1000_m88_cable_length_table[0]))
+		(sizeof(e1000_m88_cable_length_table) / \
+		 sizeof(e1000_m88_cable_length_table[0]))
 
 static const u16 e1000_igp_2_cable_length_table[] = {
 	0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
@@ -58,8 +58,8 @@ static const u16 e1000_igp_2_cable_length_table[] = {
 	100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
 	124};
 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
-                (sizeof(e1000_igp_2_cable_length_table) / \
-                 sizeof(e1000_igp_2_cable_length_table[0]))
+		(sizeof(e1000_igp_2_cable_length_table) / \
+		 sizeof(e1000_igp_2_cable_length_table[0]))
 
 /**
  *  e1000_init_phy_ops_generic - Initialize PHY function pointers
@@ -82,20 +82,35 @@ void e1000_init_phy_ops_generic(struct e1000_hw *hw)
 	phy->ops.get_cfg_done = e1000_null_ops_generic;
 	phy->ops.get_cable_length = e1000_null_ops_generic;
 	phy->ops.get_info = e1000_null_ops_generic;
+	phy->ops.set_page = e1000_null_set_page;
 	phy->ops.read_reg = e1000_null_read_reg;
 	phy->ops.read_reg_locked = e1000_null_read_reg;
+	phy->ops.read_reg_page = e1000_null_read_reg;
 	phy->ops.release = e1000_null_phy_generic;
 	phy->ops.reset = e1000_null_ops_generic;
 	phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
 	phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
 	phy->ops.write_reg = e1000_null_write_reg;
 	phy->ops.write_reg_locked = e1000_null_write_reg;
+	phy->ops.write_reg_page = e1000_null_write_reg;
 	phy->ops.power_up = e1000_null_phy_generic;
 	phy->ops.power_down = e1000_null_phy_generic;
+	phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
+	phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
 	phy->ops.cfg_on_link_up = e1000_null_ops_generic;
 }
 
 /**
+ *  e1000_null_set_page - No-op function, return 0
+ *  @hw: pointer to the HW structure
+ **/
+s32 e1000_null_set_page(struct e1000_hw *hw, u16 data)
+{
+	DEBUGFUNC("e1000_null_set_page");
+	return E1000_SUCCESS;
+}
+
+/**
  *  e1000_null_read_reg - No-op function, return 0
  *  @hw: pointer to the HW structure
  **/
@@ -250,8 +265,8 @@ s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
 	 * PHY to retrieve the desired data.
 	 */
 	mdic = ((offset << E1000_MDIC_REG_SHIFT) |
-	        (phy->addr << E1000_MDIC_PHY_SHIFT) |
-	        (E1000_MDIC_OP_READ));
+		(phy->addr << E1000_MDIC_PHY_SHIFT) |
+		(E1000_MDIC_OP_READ));
 
 	E1000_WRITE_REG(hw, E1000_MDIC, mdic);
 
@@ -316,9 +331,9 @@ s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
 	 * PHY to retrieve the desired data.
 	 */
 	mdic = (((u32)data) |
-	        (offset << E1000_MDIC_REG_SHIFT) |
-	        (phy->addr << E1000_MDIC_PHY_SHIFT) |
-	        (E1000_MDIC_OP_WRITE));
+		(offset << E1000_MDIC_REG_SHIFT) |
+		(phy->addr << E1000_MDIC_PHY_SHIFT) |
+		(E1000_MDIC_OP_WRITE));
 
 	E1000_WRITE_REG(hw, E1000_MDIC, mdic);
 
@@ -377,8 +392,8 @@ s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
 	 * PHY to retrieve the desired data.
 	 */
 	i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
-	          (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
-	          (E1000_I2CCMD_OPCODE_READ));
+		  (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
+		  (E1000_I2CCMD_OPCODE_READ));
 
 	E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
 
@@ -420,6 +435,13 @@ s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
 
 	DEBUGFUNC("e1000_write_phy_reg_i2c");
 
+	/* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
+	if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
+		DEBUGOUT1("PHY I2C Address %d is out of range.\n",
+			  hw->phy.addr);
+		return -E1000_ERR_CONFIG;
+	}
+
 	/* Swap the data bytes for the I2C interface */
 	phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
 
@@ -429,9 +451,9 @@ s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
 	 * PHY to retrieve the desired data.
 	 */
 	i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
-	          (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
-	          E1000_I2CCMD_OPCODE_WRITE |
-	          phy_data_swapped);
+		  (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
+		  E1000_I2CCMD_OPCODE_WRITE |
+		  phy_data_swapped);
 
 	E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
 
@@ -455,6 +477,139 @@ s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
 }
 
 /**
+ *  e1000_read_sfp_data_byte - Reads SFP module data.
+ *  @hw: pointer to the HW structure
+ *  @offset: byte location offset to be read
+ *  @data: read data buffer pointer
+ *
+ *  Reads one byte from SFP module data stored
+ *  in SFP resided EEPROM memory or SFP diagnostic area.
+ *  Function should be called with
+ *  E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
+ *  E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
+ *  access
+ **/
+s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
+{
+	u32 i = 0;
+	u32 i2ccmd = 0;
+	u32 data_local = 0;
+
+	DEBUGFUNC("e1000_read_sfp_data_byte");
+
+	if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
+		DEBUGOUT("I2CCMD command address exceeds upper limit\n");
+		return -E1000_ERR_PHY;
+	}
+
+	/*
+	 * Set up Op-code, EEPROM Address,in the I2CCMD
+	 * register. The MAC will take care of interfacing with the
+	 * EEPROM to retrieve the desired data.
+	 */
+	i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
+		  E1000_I2CCMD_OPCODE_READ);
+
+	E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
+
+	/* Poll the ready bit to see if the I2C read completed */
+	for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
+		usec_delay(50);
+		data_local = E1000_READ_REG(hw, E1000_I2CCMD);
+		if (data_local & E1000_I2CCMD_READY)
+			break;
+	}
+	if (!(data_local & E1000_I2CCMD_READY)) {
+		DEBUGOUT("I2CCMD Read did not complete\n");
+		return -E1000_ERR_PHY;
+	}
+	if (data_local & E1000_I2CCMD_ERROR) {
+		DEBUGOUT("I2CCMD Error bit set\n");
+		return -E1000_ERR_PHY;
+	}
+	*data = (u8) data_local & 0xFF;
+
+	return E1000_SUCCESS;
+}
+
+/**
+ *  e1000_write_sfp_data_byte - Writes SFP module data.
+ *  @hw: pointer to the HW structure
+ *  @offset: byte location offset to write to
+ *  @data: data to write
+ *
+ *  Writes one byte to SFP module data stored
+ *  in SFP resided EEPROM memory or SFP diagnostic area.
+ *  Function should be called with
+ *  E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
+ *  E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
+ *  access
+ **/
+s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)
+{
+	u32 i = 0;
+	u32 i2ccmd = 0;
+	u32 data_local = 0;
+
+	DEBUGFUNC("e1000_write_sfp_data_byte");
+
+	if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
+		DEBUGOUT("I2CCMD command address exceeds upper limit\n");
+		return -E1000_ERR_PHY;
+	}
+	/*
+	 * The programming interface is 16 bits wide
+	 * so we need to read the whole word first
+	 * then update appropriate byte lane and write
+	 * the updated word back.
+	 */
+	/*
+	 * Set up Op-code, EEPROM Address,in the I2CCMD
+	 * register. The MAC will take care of interfacing
+	 * with an EEPROM to write the data given.
+	 */
+	i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
+		  E1000_I2CCMD_OPCODE_READ);
+	/* Set a command to read single word */
+	E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
+	for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
+		usec_delay(50);
+		/*
+		 * Poll the ready bit to see if lastly
+		 * launched I2C operation completed
+		 */
+		i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
+		if (i2ccmd & E1000_I2CCMD_READY) {
+			/* Check if this is READ or WRITE phase */
+			if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) ==
+			    E1000_I2CCMD_OPCODE_READ) {
+				/*
+				 * Write the selected byte
+				 * lane and update whole word
+				 */
+				data_local = i2ccmd & 0xFF00;
+				data_local |= data;
+				i2ccmd = ((offset <<
+					E1000_I2CCMD_REG_ADDR_SHIFT) |
+					E1000_I2CCMD_OPCODE_WRITE | data_local);
+				E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
+			} else {
+				break;
+			}
+		}
+	}
+	if (!(i2ccmd & E1000_I2CCMD_READY)) {
+		DEBUGOUT("I2CCMD Write did not complete\n");
+		return -E1000_ERR_PHY;
+	}
+	if (i2ccmd & E1000_I2CCMD_ERROR) {
+		DEBUGOUT("I2CCMD Error bit set\n");
+		return -E1000_ERR_PHY;
+	}
+	return E1000_SUCCESS;
+}
+
+/**
  *  e1000_read_phy_reg_m88 - Read m88 PHY register
  *  @hw: pointer to the HW structure
  *  @offset: register offset to be read
@@ -478,7 +633,7 @@ s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
 		goto out;
 
 	ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
-	                                  data);
+					  data);
 
 	hw->phy.ops.release(hw);
 
@@ -509,7 +664,7 @@ s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
 		goto out;
 
 	ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
-	                                   data);
+					   data);
 
 	hw->phy.ops.release(hw);
 
@@ -518,6 +673,26 @@ out:
 }
 
 /**
+ *  e1000_set_page_igp - Set page as on IGP-like PHY(s)
+ *  @hw: pointer to the HW structure
+ *  @page: page to set (shifted left when necessary)
+ *
+ *  Sets PHY page required for PHY register access.  Assumes semaphore is
+ *  already acquired.  Note, this function sets phy.addr to 1 so the caller
+ *  must set it appropriately (if necessary) after this function returns.
+ **/
+s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
+{
+	DEBUGFUNC("e1000_set_page_igp");
+
+	DEBUGOUT1("Setting page 0x%x\n", page);
+
+	hw->phy.addr = 1;
+
+	return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
+}
+
+/**
  *  __e1000_read_phy_reg_igp - Read igp PHY register
  *  @hw: pointer to the HW structure
  *  @offset: register offset to be read
@@ -529,7 +704,7 @@ out:
  *  semaphores before exiting.
  **/
 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
-                                    bool locked)
+				    bool locked)
 {
 	s32 ret_val = E1000_SUCCESS;
 
@@ -546,14 +721,14 @@ static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
 
 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
 		ret_val = e1000_write_phy_reg_mdic(hw,
-		                                   IGP01E1000_PHY_PAGE_SELECT,
-		                                   (u16)offset);
+						   IGP01E1000_PHY_PAGE_SELECT,
+						   (u16)offset);
 		if (ret_val)
 			goto release;
 	}
 
 	ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
-	                                  data);
+					  data);
 
 release:
 	if (!locked)
@@ -602,7 +777,7 @@ s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
  *  at the offset.  Release any acquired semaphores before exiting.
  **/
 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
-                                     bool locked)
+				     bool locked)
 {
 	s32 ret_val = E1000_SUCCESS;
 
@@ -619,14 +794,14 @@ static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
 
 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
 		ret_val = e1000_write_phy_reg_mdic(hw,
-		                                   IGP01E1000_PHY_PAGE_SELECT,
-		                                   (u16)offset);
+						   IGP01E1000_PHY_PAGE_SELECT,
+						   (u16)offset);
 		if (ret_val)
 			goto release;
 	}
 
 	ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
-	                                   data);
+					   data);
 
 release:
 	if (!locked)
@@ -676,7 +851,7 @@ s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
  *  Release any acquired semaphores before exiting.
  **/
 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
-                                 bool locked)
+				 bool locked)
 {
 	u32 kmrnctrlsta;
 	s32 ret_val = E1000_SUCCESS;
@@ -693,8 +868,9 @@ static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
 	}
 
 	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
-	               E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
+		       E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
 	E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
+	E1000_WRITE_FLUSH(hw);
 
 	usec_delay(2);
 
@@ -750,7 +926,7 @@ s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
  *  before exiting.
  **/
 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
-                                  bool locked)
+				  bool locked)
 {
 	u32 kmrnctrlsta;
 	s32 ret_val = E1000_SUCCESS;
@@ -767,8 +943,9 @@ static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
 	}
 
 	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
-	               E1000_KMRNCTRLSTA_OFFSET) | data;
+		       E1000_KMRNCTRLSTA_OFFSET) | data;
 	E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
+	E1000_WRITE_FLUSH(hw);
 
 	usec_delay(2);
 
@@ -820,11 +997,6 @@ s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
 
 	DEBUGFUNC("e1000_copper_link_setup_82577");
 
-	if (hw->phy.reset_disable) {
-		ret_val = E1000_SUCCESS;
-		goto out;
-	}
-
 	if (hw->phy.type == e1000_phy_82580) {
 		ret_val = hw->phy.ops.reset(hw);
 		if (ret_val) {
@@ -844,6 +1016,37 @@ s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
 	phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
 
 	ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
+	if (ret_val)
+		goto out;
+
+	/* Resolve Master/Slave mode */
+	ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
+	if (ret_val)
+		goto out;
+
+	/* load defaults for future use */
+	hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
+				   ((phy_data & CR_1000T_MS_VALUE) ?
+				   e1000_ms_force_master :
+				   e1000_ms_force_slave) : e1000_ms_auto;
+
+	switch (hw->phy.ms_type) {
+	case e1000_ms_force_master:
+		phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
+		break;
+	case e1000_ms_force_slave:
+		phy_data |= CR_1000T_MS_ENABLE;
+		phy_data &= ~(CR_1000T_MS_VALUE);
+		break;
+	case e1000_ms_auto:
+		phy_data &= ~CR_1000T_MS_ENABLE;
+	default:
+		break;
+	}
+
+	ret_val = hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
+	if (ret_val)
+		goto out;
 
 out:
 	return ret_val;
@@ -864,10 +1067,6 @@ s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
 
 	DEBUGFUNC("e1000_copper_link_setup_m88");
 
-	if (phy->reset_disable) {
-		ret_val = E1000_SUCCESS;
-		goto out;
-	}
 
 	/* Enable CRS on Tx. This must be set for half-duplex operation. */
 	ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
@@ -931,7 +1130,7 @@ s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
 		 * to 25MHz clock.
 		 */
 		ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
-		                             &phy_data);
+					    &phy_data);
 		if (ret_val)
 			goto out;
 
@@ -945,12 +1144,12 @@ s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
 		} else {
 			/* Configure Master and Slave downshift values */
 			phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
-			             M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
+				     M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
 			phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
-			             M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
+				     M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
 		}
 		ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
-		                             phy_data);
+					     phy_data);
 		if (ret_val)
 			goto out;
 	}
@@ -976,7 +1175,7 @@ s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
 
 	if (phy->type == e1000_phy_82578) {
 		ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
-		                            &phy_data);
+					    &phy_data);
 		if (ret_val)
 			goto out;
 
@@ -984,7 +1183,7 @@ s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
 		phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
 		phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
 		ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
-		                             phy_data);
+					     phy_data);
 		if (ret_val)
 			goto out;
 	}
@@ -1008,10 +1207,6 @@ s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
 
 	DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
 
-	if (phy->reset_disable) {
-		ret_val = E1000_SUCCESS;
-		goto out;
-	}
 
 	/* Enable CRS on Tx. This must be set for half-duplex operation. */
 	ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
@@ -1093,10 +1288,6 @@ s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
 
 	DEBUGFUNC("e1000_copper_link_setup_igp");
 
-	if (phy->reset_disable) {
-		ret_val = E1000_SUCCESS;
-		goto out;
-	}
 
 	ret_val = hw->phy.ops.reset(hw);
 	if (ret_val) {
@@ -1164,15 +1355,15 @@ s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
 		if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
 			/* Disable SmartSpeed */
 			ret_val = phy->ops.read_reg(hw,
-			                             IGP01E1000_PHY_PORT_CONFIG,
-			                             &data);
+						    IGP01E1000_PHY_PORT_CONFIG,
+						    &data);
 			if (ret_val)
 				goto out;
 
 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 			ret_val = phy->ops.write_reg(hw,
-			                             IGP01E1000_PHY_PORT_CONFIG,
-			                             data);
+						     IGP01E1000_PHY_PORT_CONFIG,
+						     data);
 			if (ret_val)
 				goto out;
 
@@ -1278,8 +1469,7 @@ s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
 	if (phy->autoneg_wait_to_complete) {
 		ret_val = hw->mac.ops.wait_autoneg(hw);
 		if (ret_val) {
-			DEBUGOUT("Error while waiting for "
-			         "autoneg to complete\n");
+			DEBUGOUT("Error while waiting for autoneg to complete\n");
 			goto out;
 		}
 	}
@@ -1318,7 +1508,7 @@ s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
 	if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
 		/* Read the MII 1000Base-T Control Register (Address 9). */
 		ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
-		                            &mii_1000t_ctrl_reg);
+					    &mii_1000t_ctrl_reg);
 		if (ret_val)
 			goto out;
 	}
@@ -1337,9 +1527,9 @@ s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
 	 * the  1000Base-T Control Register (Address 9).
 	 */
 	mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
-	                         NWAY_AR_100TX_HD_CAPS |
-	                         NWAY_AR_10T_FD_CAPS   |
-	                         NWAY_AR_10T_HD_CAPS);
+				 NWAY_AR_100TX_HD_CAPS |
+				 NWAY_AR_10T_FD_CAPS   |
+				 NWAY_AR_10T_HD_CAPS);
 	mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
 
 	DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
@@ -1445,9 +1635,8 @@ s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
 	DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
 
 	if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
-		ret_val = phy->ops.write_reg(hw,
-		                              PHY_1000T_CTRL,
-		                              mii_1000t_ctrl_reg);
+		ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
+					     mii_1000t_ctrl_reg);
 		if (ret_val)
 			goto out;
 	}
@@ -1497,10 +1686,8 @@ s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
 	 * Check link status. Wait up to 100 microseconds for link to become
 	 * valid.
 	 */
-	ret_val = e1000_phy_has_link_generic(hw,
-	                                     COPPER_LINK_UP_LIMIT,
-	                                     10,
-	                                     &link);
+	ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
+					     &link);
 	if (ret_val)
 		goto out;
 
@@ -1565,10 +1752,8 @@ s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
 	if (phy->autoneg_wait_to_complete) {
 		DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
 
-		ret_val = e1000_phy_has_link_generic(hw,
-		                                     PHY_FORCE_LIMIT,
-		                                     100000,
-		                                     &link);
+		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
+						     100000, &link);
 		if (ret_val)
 			goto out;
 
@@ -1576,10 +1761,8 @@ s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
 			DEBUGOUT("Link taking longer than expected.\n");
 
 		/* Try once more */
-		ret_val = e1000_phy_has_link_generic(hw,
-		                                     PHY_FORCE_LIMIT,
-		                                     100000,
-		                                     &link);
+		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
+						     100000, &link);
 		if (ret_val)
 			goto out;
 	}
@@ -1641,7 +1824,7 @@ s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
 		DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
 
 		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
-		                                     100000, &link);
+						     100000, &link);
 		if (ret_val)
 			goto out;
 
@@ -1669,7 +1852,7 @@ s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
 
 		/* Try once more */
 		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
-		                                     100000, &link);
+						     100000, &link);
 		if (ret_val)
 			goto out;
 	}
@@ -1755,10 +1938,8 @@ s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
 	if (phy->autoneg_wait_to_complete) {
 		DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
 
-		ret_val = e1000_phy_has_link_generic(hw,
-		                                     PHY_FORCE_LIMIT,
-		                                     100000,
-		                                     &link);
+		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
+						     100000, &link);
 		if (ret_val)
 			goto out;
 
@@ -1766,10 +1947,8 @@ s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
 			DEBUGOUT("Link taking longer than expected.\n");
 
 		/* Try once more */
-		ret_val = e1000_phy_has_link_generic(hw,
-		                                     PHY_FORCE_LIMIT,
-		                                     100000,
-		                                     &link);
+		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
+						     100000, &link);
 		if (ret_val)
 			goto out;
 	}
@@ -1872,7 +2051,7 @@ s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
 	if (!active) {
 		data &= ~IGP02E1000_PM_D3_LPLU;
 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
-		                             data);
+					     data);
 		if (ret_val)
 			goto out;
 		/*
@@ -1883,49 +2062,49 @@ s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
 		 */
 		if (phy->smart_speed == e1000_smart_speed_on) {
 			ret_val = phy->ops.read_reg(hw,
-			                            IGP01E1000_PHY_PORT_CONFIG,
-			                            &data);
+						    IGP01E1000_PHY_PORT_CONFIG,
+						    &data);
 			if (ret_val)
 				goto out;
 
 			data |= IGP01E1000_PSCFR_SMART_SPEED;
 			ret_val = phy->ops.write_reg(hw,
-			                             IGP01E1000_PHY_PORT_CONFIG,
-			                             data);
+						     IGP01E1000_PHY_PORT_CONFIG,
+						     data);
 			if (ret_val)
 				goto out;
 		} else if (phy->smart_speed == e1000_smart_speed_off) {
 			ret_val = phy->ops.read_reg(hw,
-			                             IGP01E1000_PHY_PORT_CONFIG,
-			                             &data);
+						    IGP01E1000_PHY_PORT_CONFIG,
+						    &data);
 			if (ret_val)
 				goto out;
 
 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 			ret_val = phy->ops.write_reg(hw,
-			                             IGP01E1000_PHY_PORT_CONFIG,
-			                             data);
+						     IGP01E1000_PHY_PORT_CONFIG,
+						     data);
 			if (ret_val)
 				goto out;
 		}
 	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
-	           (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
-	           (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
+		   (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
+		   (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 		data |= IGP02E1000_PM_D3_LPLU;
 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
-		                              data);
+					     data);
 		if (ret_val)
 			goto out;
 
 		/* When LPLU is enabled, we should disable SmartSpeed */
 		ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-		                             &data);
+					    &data);
 		if (ret_val)
 			goto out;
 
 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 		ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-		                              data);
+					     data);
 	}
 
 out:
@@ -1953,14 +2132,14 @@ s32 e1000_check_downshift_generic(struct e1000_hw *hw)
 	case e1000_phy_gg82563:
 	case e1000_phy_bm:
 	case e1000_phy_82578:
-		offset	= M88E1000_PHY_SPEC_STATUS;
-		mask	= M88E1000_PSSR_DOWNSHIFT;
+		offset = M88E1000_PHY_SPEC_STATUS;
+		mask = M88E1000_PSSR_DOWNSHIFT;
 		break;
 	case e1000_phy_igp:
 	case e1000_phy_igp_2:
 	case e1000_phy_igp_3:
-		offset	= IGP01E1000_PHY_LINK_HEALTH;
-		mask	= IGP01E1000_PLHR_SS_DOWNGRADE;
+		offset = IGP01E1000_PHY_LINK_HEALTH;
+		mask = IGP01E1000_PLHR_SS_DOWNGRADE;
 		break;
 	default:
 		/* speed downshift not supported */
@@ -1998,8 +2177,8 @@ s32 e1000_check_polarity_m88(struct e1000_hw *hw)
 
 	if (!ret_val)
 		phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
-		                      ? e1000_rev_polarity_reversed
-		                      : e1000_rev_polarity_normal;
+				      ? e1000_rev_polarity_reversed
+				      : e1000_rev_polarity_normal;
 
 	return ret_val;
 }
@@ -2031,23 +2210,23 @@ s32 e1000_check_polarity_igp(struct e1000_hw *hw)
 
 	if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
 	    IGP01E1000_PSSR_SPEED_1000MBPS) {
-		offset	= IGP01E1000_PHY_PCS_INIT_REG;
-		mask	= IGP01E1000_PHY_POLARITY_MASK;
+		offset = IGP01E1000_PHY_PCS_INIT_REG;
+		mask = IGP01E1000_PHY_POLARITY_MASK;
 	} else {
 		/*
 		 * This really only applies to 10Mbps since
 		 * there is no polarity for 100Mbps (always 0).
 		 */
-		offset	= IGP01E1000_PHY_PORT_STATUS;
-		mask	= IGP01E1000_PSSR_POLARITY_REVERSED;
+		offset = IGP01E1000_PHY_PORT_STATUS;
+		mask = IGP01E1000_PSSR_POLARITY_REVERSED;
 	}
 
 	ret_val = phy->ops.read_reg(hw, offset, &data);
 
 	if (!ret_val)
 		phy->cable_polarity = (data & mask)
-		                      ? e1000_rev_polarity_reversed
-		                      : e1000_rev_polarity_normal;
+				      ? e1000_rev_polarity_reversed
+				      : e1000_rev_polarity_normal;
 
 out:
 	return ret_val;
@@ -2082,8 +2261,8 @@ s32 e1000_check_polarity_ife(struct e1000_hw *hw)
 
 	if (!ret_val)
 		phy->cable_polarity = (phy_data & mask)
-		                       ? e1000_rev_polarity_reversed
-		                       : e1000_rev_polarity_normal;
+				       ? e1000_rev_polarity_reversed
+				       : e1000_rev_polarity_normal;
 
 	return ret_val;
 }
@@ -2135,7 +2314,7 @@ s32 e1000_wait_autoneg_generic(struct e1000_hw *hw)
  *  Polls the PHY status register for link, 'iterations' number of times.
  **/
 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
-                               u32 usec_interval, bool *success)
+			       u32 usec_interval, bool *success)
 {
 	s32 ret_val = E1000_SUCCESS;
 	u16 i, phy_status;
@@ -2203,7 +2382,7 @@ s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
 		goto out;
 
 	index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
-	        M88E1000_PSSR_CABLE_LENGTH_SHIFT;
+		M88E1000_PSSR_CABLE_LENGTH_SHIFT;
 	if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
 		ret_val = -E1000_ERR_PHY;
 		goto out;
@@ -2250,14 +2429,14 @@ s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
 		if (ret_val)
 			goto out;
 
-		is_cm = !(phy_data & I347AT4_PCDC_CABLE_LENGTH_UNIT);
+		is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
 
 		/* Populate the phy structure with cable length in meters */
 		phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
 		phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
 		phy->cable_length = phy_data / (is_cm ? 100 : 1);
 
-		/* Reset the page selec	to its original value */
+		/* Reset the page select to its original value */
 		ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
 					     default_page);
 		if (ret_val)
@@ -2327,10 +2506,10 @@ s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
 	u16 cur_agc_index, max_agc_index = 0;
 	u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
 	static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
-	       IGP02E1000_PHY_AGC_A,
-	       IGP02E1000_PHY_AGC_B,
-	       IGP02E1000_PHY_AGC_C,
-	       IGP02E1000_PHY_AGC_D
+		IGP02E1000_PHY_AGC_A,
+		IGP02E1000_PHY_AGC_B,
+		IGP02E1000_PHY_AGC_C,
+		IGP02E1000_PHY_AGC_D
 	};
 
 	DEBUGFUNC("e1000_get_cable_length_igp_2");
@@ -2348,7 +2527,7 @@ s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
 		 * approximate cable length.
 		 */
 		cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
-		                IGP02E1000_AGC_LENGTH_MASK;
+				IGP02E1000_AGC_LENGTH_MASK;
 
 		/* Array index bound check. */
 		if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
@@ -2369,12 +2548,12 @@ s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
 	}
 
 	agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
-	              e1000_igp_2_cable_length_table[max_agc_index]);
+		      e1000_igp_2_cable_length_table[max_agc_index]);
 	agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
 
 	/* Calculate cable length with the error range of +/- 10 meters. */
 	phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
-	                         (agc_value - IGP02E1000_AGC_RANGE) : 0;
+				 (agc_value - IGP02E1000_AGC_RANGE) : 0;
 	phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
 
 	phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
@@ -2423,7 +2602,7 @@ s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
 		goto out;
 
 	phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
-	                           ? TRUE : FALSE;
+				   ? TRUE : FALSE;
 
 	ret_val = e1000_check_polarity_m88(hw);
 	if (ret_val)
@@ -2445,12 +2624,12 @@ s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
 			goto out;
 
 		phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
-		                ? e1000_1000t_rx_status_ok
-		                : e1000_1000t_rx_status_not_ok;
+				? e1000_1000t_rx_status_ok
+				: e1000_1000t_rx_status_not_ok;
 
 		phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
-		                 ? e1000_1000t_rx_status_ok
-		                 : e1000_1000t_rx_status_not_ok;
+				 ? e1000_1000t_rx_status_ok
+				 : e1000_1000t_rx_status_not_ok;
 	} else {
 		/* Set values to "undefined" */
 		phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
@@ -2513,12 +2692,12 @@ s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
 			goto out;
 
 		phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
-		                ? e1000_1000t_rx_status_ok
-		                : e1000_1000t_rx_status_not_ok;
+				? e1000_1000t_rx_status_ok
+				: e1000_1000t_rx_status_not_ok;
 
 		phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
-		                 ? e1000_1000t_rx_status_ok
-		                 : e1000_1000t_rx_status_not_ok;
+				 ? e1000_1000t_rx_status_ok
+				 : e1000_1000t_rx_status_not_ok;
 	} else {
 		phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
 		phy->local_rx = e1000_1000t_rx_status_undefined;
@@ -2558,7 +2737,7 @@ s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
 	if (ret_val)
 		goto out;
 	phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
-	                           ? FALSE : TRUE;
+				   ? FALSE : TRUE;
 
 	if (phy->polarity_correction) {
 		ret_val = e1000_check_polarity_ife(hw);
@@ -2567,8 +2746,8 @@ s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
 	} else {
 		/* Polarity is forced */
 		phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
-		                      ? e1000_rev_polarity_reversed
-		                      : e1000_rev_polarity_normal;
+				      ? e1000_rev_polarity_reversed
+				      : e1000_rev_polarity_normal;
 	}
 
 	ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
@@ -2903,7 +3082,7 @@ s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
 	/* Page 800 works differently than the rest so it has its own func */
 	if (page == BM_WUC_PAGE) {
 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
-		                                         FALSE);
+							 FALSE, FALSE);
 		goto out;
 	}
 
@@ -2927,13 +3106,13 @@ s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
 
 		/* Page is shifted left, PHY expects (page x 32) */
 		ret_val = e1000_write_phy_reg_mdic(hw, page_select,
-		                                   (page << page_shift));
+						   (page << page_shift));
 		if (ret_val)
 			goto out;
 	}
 
 	ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
-	                                   data);
+					   data);
 
 out:
 	hw->phy.ops.release(hw);
@@ -2964,7 +3143,7 @@ s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
 	/* Page 800 works differently than the rest so it has its own func */
 	if (page == BM_WUC_PAGE) {
 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
-		                                         TRUE);
+							 TRUE, FALSE);
 		goto out;
 	}
 
@@ -2988,13 +3167,13 @@ s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
 
 		/* Page is shifted left, PHY expects (page x 32) */
 		ret_val = e1000_write_phy_reg_mdic(hw, page_select,
-		                                   (page << page_shift));
+						   (page << page_shift));
 		if (ret_val)
 			goto out;
 	}
 
 	ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
-	                                  data);
+					  data);
 out:
 	hw->phy.ops.release(hw);
 	return ret_val;
@@ -3015,7 +3194,7 @@ s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
 	s32 ret_val;
 	u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
 
-	DEBUGFUNC("e1000_write_phy_reg_bm2");
+	DEBUGFUNC("e1000_read_phy_reg_bm2");
 
 	ret_val = hw->phy.ops.acquire(hw);
 	if (ret_val)
@@ -3024,7 +3203,7 @@ s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
 	/* Page 800 works differently than the rest so it has its own func */
 	if (page == BM_WUC_PAGE) {
 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
-		                                         TRUE);
+							 TRUE, FALSE);
 		goto out;
 	}
 
@@ -3034,14 +3213,14 @@ s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
 
 		/* Page is shifted left, PHY expects (page x 32) */
 		ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
-		                                   page);
+						   page);
 
 		if (ret_val)
 			goto out;
 	}
 
 	ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
-	                                  data);
+					  data);
 out:
 	hw->phy.ops.release(hw);
 	return ret_val;
@@ -3070,7 +3249,7 @@ s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
 	/* Page 800 works differently than the rest so it has its own func */
 	if (page == BM_WUC_PAGE) {
 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
-		                                         FALSE);
+							 FALSE, FALSE);
 		goto out;
 	}
 
@@ -3079,14 +3258,14 @@ s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
 		/* Page is shifted left, PHY expects (page x 32) */
 		ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
-		                                   page);
+						   page);
 
 		if (ret_val)
 			goto out;
 	}
 
 	ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
-	                                   data);
+					   data);
 
 out:
 	hw->phy.ops.release(hw);
@@ -3094,106 +3273,176 @@ out:
 }
 
 /**
- *  e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register
+ *  e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
  *  @hw: pointer to the HW structure
- *  @offset: register offset to be read or written
- *  @data: pointer to the data to read or write
- *  @read: determines if operation is read or write
- *
- *  Acquires semaphore, if necessary, then reads the PHY register at offset
- *  and storing the retrieved information in data.  Release any acquired
- *  semaphores before exiting. Note that procedure to read the wakeup
- *  registers are different. It works as such:
- *  1) Set page 769, register 17, bit 2 = 1
- *  2) Set page to 800 for host (801 if we were manageability)
- *  3) Write the address using the address opcode (0x11)
- *  4) Read or write the data using the data opcode (0x12)
- *  5) Restore 769_17.2 to its original value
+ *  @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
  *
- *  Assumes semaphore already acquired.
+ *  Assumes semaphore already acquired and phy_reg points to a valid memory
+ *  address to store contents of the BM_WUC_ENABLE_REG register.
  **/
-static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
-                                          u16 *data, bool read)
+s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
 {
 	s32 ret_val;
-	u16 reg = BM_PHY_REG_NUM(offset);
-	u16 phy_reg = 0;
+	u16 temp;
 
-	DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
+	DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm");
 
-	/* Gig must be disabled for MDIO accesses to page 800 */
-	if ((hw->mac.type == e1000_pchlan) &&
-	   (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
-		DEBUGOUT("Attempting to access page 800 while gig enabled.\n");
+	if (!phy_reg) {
+		ret_val = -E1000_ERR_PARAM;
+		goto out;
+	}
 
-	/* All operations in this function are phy address 1 */
+	/* All page select, port ctrl and wakeup registers use phy address 1 */
 	hw->phy.addr = 1;
 
-	/* Set page 769 */
-	e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
-	                         (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
+	/* Select Port Control Registers page */
+	ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
+	if (ret_val) {
+		DEBUGOUT("Could not set Port Control page\n");
+		goto out;
+	}
 
-	ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg);
+	ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
 	if (ret_val) {
-		DEBUGOUT("Could not read PHY page 769\n");
+		DEBUGOUT2("Could not read PHY register %d.%d\n",
+			  BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
 		goto out;
 	}
 
-	/* First clear bit 4 to avoid a power state change */
-	phy_reg &= ~(BM_WUC_HOST_WU_BIT);
-	ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
+	/*
+	 * Enable both PHY wakeup mode and Wakeup register page writes.
+	 * Prevent a power state change by disabling ME and Host PHY wakeup.
+	 */
+	temp = *phy_reg;
+	temp |= BM_WUC_ENABLE_BIT;
+	temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
+
+	ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
 	if (ret_val) {
-		DEBUGOUT("Could not clear PHY page 769 bit 4\n");
+		DEBUGOUT2("Could not write PHY register %d.%d\n",
+			  BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
 		goto out;
 	}
 
-	/* Write bit 2 = 1, and clear bit 4 to 769_17 */
-	ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG,
-	                                   phy_reg | BM_WUC_ENABLE_BIT);
+	/* Select Host Wakeup Registers page */
+	ret_val = e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
+
+	/* caller now able to write registers on the Wakeup registers page */
+out:
+	return ret_val;
+}
+
+/**
+ *  e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
+ *  @hw: pointer to the HW structure
+ *  @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
+ *
+ *  Restore BM_WUC_ENABLE_REG to its original value.
+ *
+ *  Assumes semaphore already acquired and *phy_reg is the contents of the
+ *  BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
+ *  caller.
+ **/
+s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
+{
+	s32 ret_val = E1000_SUCCESS;
+
+	DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm");
+
+	if (!phy_reg)
+		return -E1000_ERR_PARAM;
+
+	/* Select Port Control Registers page */
+	ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
 	if (ret_val) {
-		DEBUGOUT("Could not write PHY page 769 bit 2\n");
+		DEBUGOUT("Could not set Port Control page\n");
 		goto out;
 	}
 
-	/* Select page 800 */
-	ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
-	                                   (BM_WUC_PAGE << IGP_PAGE_SHIFT));
+	/* Restore 769.17 to its original value */
+	ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
+	if (ret_val)
+		DEBUGOUT2("Could not restore PHY register %d.%d\n",
+			  BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
+out:
+	return ret_val;
+}
 
-	/* Write the page 800 offset value using opcode 0x11 */
+/**
+ *  e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
+ *  @hw: pointer to the HW structure
+ *  @offset: register offset to be read or written
+ *  @data: pointer to the data to read or write
+ *  @read: determines if operation is read or write
+ *  @page_set: BM_WUC_PAGE already set and access enabled
+ *
+ *  Read the PHY register at offset and store the retrieved information in
+ *  data, or write data to PHY register at offset.  Note the procedure to
+ *  access the PHY wakeup registers is different than reading the other PHY
+ *  registers. It works as such:
+ *  1) Set 769.17.2 (page 769, register 17, bit 2) = 1
+ *  2) Set page to 800 for host (801 if we were manageability)
+ *  3) Write the address using the address opcode (0x11)
+ *  4) Read or write the data using the data opcode (0x12)
+ *  5) Restore 769.17.2 to its original value
+ *
+ *  Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
+ *  step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
+ *
+ *  Assumes semaphore is already acquired.  When page_set==TRUE, assumes
+ *  the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
+ *  is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
+ **/
+static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
+					  u16 *data, bool read, bool page_set)
+{
+	s32 ret_val;
+	u16 reg = BM_PHY_REG_NUM(offset);
+	u16 phy_reg = 0;
+
+	DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
+
+	/* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
+	if ((hw->mac.type == e1000_pchlan) &&
+	   (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
+		DEBUGOUT1("Attempting to access page %d while gig enabled.\n",
+			  page);
+
+	if (!page_set) {
+		/* Enable access to PHY wakeup registers */
+		ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
+		if (ret_val) {
+			DEBUGOUT("Could not enable PHY wakeup reg access\n");
+			goto out;
+		}
+	}
+
+	DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
+
+	/* Write the Wakeup register page offset value using opcode 0x11 */
 	ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
 	if (ret_val) {
-		DEBUGOUT("Could not write address opcode to page 800\n");
+		DEBUGOUT1("Could not write address opcode to page %d\n", page);
 		goto out;
 	}
 
 	if (read) {
-	        /* Read the page 800 value using opcode 0x12 */
+		/* Read the Wakeup register page value using opcode 0x12 */
 		ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
-		                                  data);
+						  data);
 	} else {
-	        /* Write the page 800 value using opcode 0x12 */
+		/* Write the Wakeup register page value using opcode 0x12 */
 		ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
-		                                   *data);
+						   *data);
 	}
 
 	if (ret_val) {
-		DEBUGOUT("Could not access data value from page 800\n");
+		DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);
 		goto out;
 	}
 
-	/*
-	 * Restore 769_17.2 to its original value
-	 * Set page 769
-	 */
-	e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
-	                         (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
-
-	/* Clear 769_17.2 */
-	ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
-	if (ret_val) {
-		DEBUGOUT("Could not clear PHY page 769 bit 2\n");
-		goto out;
-	}
+	if (!page_set)
+		ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
 
 out:
 	return ret_val;
@@ -3248,11 +3497,12 @@ void e1000_power_down_phy_copper(struct e1000_hw *hw)
  *  semaphore before exiting.
  **/
 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
-                                   bool locked)
+				   bool locked, bool page_set)
 {
 	s32 ret_val;
 	u16 page = BM_PHY_REG_PAGE(offset);
 	u16 reg = BM_PHY_REG_NUM(offset);
+	u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
 
 	DEBUGFUNC("__e1000_read_phy_reg_hv");
 
@@ -3264,39 +3514,38 @@ static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
 
 	/* Page 800 works differently than the rest so it has its own func */
 	if (page == BM_WUC_PAGE) {
-		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
-		                                         data, TRUE);
+		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
+							 TRUE, page_set);
 		goto out;
 	}
 
 	if (page > 0 && page < HV_INTC_FC_PAGE_START) {
 		ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
-		                                         data, TRUE);
+							 data, TRUE);
 		goto out;
 	}
 
-	hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
+	if (!page_set) {
+		if (page == HV_INTC_FC_PAGE_START)
+			page = 0;
 
-	if (page == HV_INTC_FC_PAGE_START)
-		page = 0;
+		if (reg > MAX_PHY_MULTI_PAGE_REG) {
+			/* Page is shifted left, PHY expects (page x 32) */
+			ret_val = e1000_set_page_igp(hw,
+						     (page << IGP_PAGE_SHIFT));
 
-	if (reg > MAX_PHY_MULTI_PAGE_REG) {
-		u32 phy_addr = hw->phy.addr;
+			hw->phy.addr = phy_addr;
 
-		hw->phy.addr = 1;
-
-		/* Page is shifted left, PHY expects (page x 32) */
-		ret_val = e1000_write_phy_reg_mdic(hw,
-					     IGP01E1000_PHY_PAGE_SELECT,
-					     (page << IGP_PAGE_SHIFT));
-		hw->phy.addr = phy_addr;
-
-		if (ret_val)
-			goto out;
+			if (ret_val)
+				goto out;
+		}
 	}
 
+	DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
+		  page << IGP_PAGE_SHIFT, reg);
+
 	ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
-	                                  data);
+					  data);
 out:
 	if (!locked)
 		hw->phy.ops.release(hw);
@@ -3316,7 +3565,7 @@ out:
  **/
 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
 {
-	return __e1000_read_phy_reg_hv(hw, offset, data, FALSE);
+	return __e1000_read_phy_reg_hv(hw, offset, data, FALSE, FALSE);
 }
 
 /**
@@ -3330,7 +3579,21 @@ s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
  **/
 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
 {
-	return __e1000_read_phy_reg_hv(hw, offset, data, TRUE);
+	return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, FALSE);
+}
+
+/**
+ *  e1000_read_phy_reg_page_hv - Read HV PHY register
+ *  @hw: pointer to the HW structure
+ *  @offset: register offset to write to
+ *  @data: data to write at register offset
+ *
+ *  Reads the PHY register at offset and stores the retrieved information
+ *  in data.  Assumes semaphore already acquired and page already set.
+ **/
+s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
+{
+	return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, true);
 }
 
 /**
@@ -3344,11 +3607,12 @@ s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
  *  at the offset.  Release any acquired semaphores before exiting.
  **/
 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
-                                    bool locked)
+				    bool locked, bool page_set)
 {
 	s32 ret_val;
 	u16 page = BM_PHY_REG_PAGE(offset);
 	u16 reg = BM_PHY_REG_NUM(offset);
+	u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
 
 	DEBUGFUNC("__e1000_write_phy_reg_hv");
 
@@ -3360,55 +3624,55 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
 
 	/* Page 800 works differently than the rest so it has its own func */
 	if (page == BM_WUC_PAGE) {
-		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
-		                                         &data, FALSE);
+		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
+							 FALSE, page_set);
 		goto out;
 	}
 
 	if (page > 0 && page < HV_INTC_FC_PAGE_START) {
 		ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
-		                                         &data, FALSE);
+							 &data, FALSE);
 		goto out;
 	}
 
-	hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
+	if (!page_set) {
+		if (page == HV_INTC_FC_PAGE_START)
+			page = 0;
 
-	if (page == HV_INTC_FC_PAGE_START)
-		page = 0;
-
-	/*
-	 * Workaround MDIO accesses being disabled after entering IEEE Power
-	 * Down (whenever bit 11 of the PHY Control register is set)
-	 */
-	if ((hw->phy.type == e1000_phy_82578) &&
-	    (hw->phy.revision >= 1) &&
-	    (hw->phy.addr == 2) &&
-	    ((MAX_PHY_REG_ADDRESS & reg) == 0) &&
-	    (data & (1 << 11))) {
-		u16 data2 = 0x7EFF;
-		ret_val = e1000_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3,
-		                                         &data2, FALSE);
-		if (ret_val)
-			goto out;
-	}
-
-	if (reg > MAX_PHY_MULTI_PAGE_REG) {
-		u32 phy_addr = hw->phy.addr;
+		/*
+		 * Workaround MDIO accesses being disabled after entering IEEE
+		 * Power Down (when bit 11 of the PHY Control register is set)
+		 */
+		if ((hw->phy.type == e1000_phy_82578) &&
+		    (hw->phy.revision >= 1) &&
+		    (hw->phy.addr == 2) &&
+		    ((MAX_PHY_REG_ADDRESS & reg) == 0) &&
+		    (data & (1 << 11))) {
+			u16 data2 = 0x7EFF;
+			ret_val = e1000_access_phy_debug_regs_hv(hw,
+								 (1 << 6) | 0x3,
+								 &data2, FALSE);
+			if (ret_val)
+				goto out;
+		}
 
-		hw->phy.addr = 1;
+		if (reg > MAX_PHY_MULTI_PAGE_REG) {
+			/* Page is shifted left, PHY expects (page x 32) */
+			ret_val = e1000_set_page_igp(hw,
+						     (page << IGP_PAGE_SHIFT));
 
-		/* Page is shifted left, PHY expects (page x 32) */
-		ret_val = e1000_write_phy_reg_mdic(hw,
-					     IGP01E1000_PHY_PAGE_SELECT,
-					     (page << IGP_PAGE_SHIFT));
-		hw->phy.addr = phy_addr;
+			hw->phy.addr = phy_addr;
 
-		if (ret_val)
-			goto out;
+			if (ret_val)
+				goto out;
+		}
 	}
 
+	DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
+		  page << IGP_PAGE_SHIFT, reg);
+
 	ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
-	                                  data);
+					   data);
 
 out:
 	if (!locked)
@@ -3428,7 +3692,7 @@ out:
  **/
 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
 {
-	return __e1000_write_phy_reg_hv(hw, offset, data, FALSE);
+	return __e1000_write_phy_reg_hv(hw, offset, data, FALSE, FALSE);
 }
 
 /**
@@ -3442,7 +3706,21 @@ s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
  **/
 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
 {
-	return __e1000_write_phy_reg_hv(hw, offset, data, TRUE);
+	return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, FALSE);
+}
+
+/**
+ *  e1000_write_phy_reg_page_hv - Write HV PHY register
+ *  @hw: pointer to the HW structure
+ *  @offset: register offset to write to
+ *  @data: data to write at register offset
+ *
+ *  Writes the data to PHY register at the offset.  Assumes semaphore
+ *  already acquired and page already set.
+ **/
+s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
+{
+	return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, true);
 }
 
 /**
@@ -3464,14 +3742,15 @@ static u32 e1000_get_phy_addr_for_hv_page(u32 page)
  *  @hw: pointer to the HW structure
  *  @offset: register offset to be read or written
  *  @data: pointer to the data to be read or written
- *  @read: determines if operation is read or written
+ *  @read: determines if operation is read or write
  *
  *  Reads the PHY register at offset and stores the retreived information
  *  in data.  Assumes semaphore already acquired.  Note that the procedure
- *  to read these regs uses the address port and data port to read/write.
+ *  to access these regs uses the address port and data port to read/write.
+ *  These accesses done with PHY address 2 and without using pages.
  **/
 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
-                                          u16 *data, bool read)
+					  u16 *data, bool read)
 {
 	s32 ret_val;
 	u32 addr_reg = 0;
@@ -3481,7 +3760,7 @@ static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
 
 	/* This takes care of the difference with desktop vs mobile phy */
 	addr_reg = (hw->phy.type == e1000_phy_82578) ?
-	           I82578_ADDR_REG : I82577_ADDR_REG;
+		   I82578_ADDR_REG : I82577_ADDR_REG;
 	data_reg = addr_reg + 1;
 
 	/* All operations in this function are phy address 2 */
@@ -3490,7 +3769,7 @@ static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
 	/* masking with 0x3F to remove the page from offset */
 	ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
 	if (ret_val) {
-		DEBUGOUT("Could not write PHY the HV address register\n");
+		DEBUGOUT("Could not write the Address Offset port register\n");
 		goto out;
 	}
 
@@ -3501,7 +3780,7 @@ static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
 		ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
 
 	if (ret_val) {
-		DEBUGOUT("Could not read data value from HV data register\n");
+		DEBUGOUT("Could not access the Data port register\n");
 		goto out;
 	}
 
@@ -3540,26 +3819,24 @@ s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
 	if (ret_val)
 		goto out;
 
-	data &= BM_CS_STATUS_LINK_UP |
-	        BM_CS_STATUS_RESOLVED |
-	        BM_CS_STATUS_SPEED_MASK;
+	data &= BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
+		BM_CS_STATUS_SPEED_MASK;
 
-	if (data != (BM_CS_STATUS_LINK_UP |
-	             BM_CS_STATUS_RESOLVED |
-	             BM_CS_STATUS_SPEED_1000))
+	if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
+		     BM_CS_STATUS_SPEED_1000))
 		goto out;
 
 	msec_delay(200);
 
 	/* flush the packets in the fifo buffer */
 	ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
-	                                HV_MUX_DATA_CTRL_GEN_TO_MAC |
-	                                HV_MUX_DATA_CTRL_FORCE_SPEED);
+					HV_MUX_DATA_CTRL_GEN_TO_MAC |
+					HV_MUX_DATA_CTRL_FORCE_SPEED);
 	if (ret_val)
 		goto out;
 
 	ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
-	                                HV_MUX_DATA_CTRL_GEN_TO_MAC);
+					HV_MUX_DATA_CTRL_GEN_TO_MAC);
 
 out:
 	return ret_val;
@@ -3585,8 +3862,8 @@ s32 e1000_check_polarity_82577(struct e1000_hw *hw)
 
 	if (!ret_val)
 		phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
-		                      ? e1000_rev_polarity_reversed
-		                      : e1000_rev_polarity_normal;
+				      ? e1000_rev_polarity_reversed
+				      : e1000_rev_polarity_normal;
 
 	return ret_val;
 }
@@ -3621,10 +3898,8 @@ s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
 	if (phy->autoneg_wait_to_complete) {
 		DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
 
-		ret_val = e1000_phy_has_link_generic(hw,
-		                                     PHY_FORCE_LIMIT,
-		                                     100000,
-		                                     &link);
+		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
+						     100000, &link);
 		if (ret_val)
 			goto out;
 
@@ -3632,10 +3907,8 @@ s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
 			DEBUGOUT("Link taking longer than expected.\n");
 
 		/* Try once more */
-		ret_val = e1000_phy_has_link_generic(hw,
-		                                     PHY_FORCE_LIMIT,
-		                                     100000,
-		                                     &link);
+		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
+						     100000, &link);
 		if (ret_val)
 			goto out;
 	}
@@ -3695,12 +3968,12 @@ s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
 			goto out;
 
 		phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
-		                ? e1000_1000t_rx_status_ok
-		                : e1000_1000t_rx_status_not_ok;
+				? e1000_1000t_rx_status_ok
+				: e1000_1000t_rx_status_not_ok;
 
 		phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
-		                 ? e1000_1000t_rx_status_ok
-		                 : e1000_1000t_rx_status_not_ok;
+				 ? e1000_1000t_rx_status_ok
+				 : e1000_1000t_rx_status_not_ok;
 	} else {
 		phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
 		phy->local_rx = e1000_1000t_rx_status_undefined;
@@ -3731,7 +4004,7 @@ s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
 		goto out;
 
 	length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
-	         I82577_DSTATUS_CABLE_LENGTH_SHIFT;
+		 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
 
 	if (length == E1000_CABLE_LENGTH_UNDEFINED)
 		ret_val = -E1000_ERR_PHY;
diff --git a/sys/dev/e1000/e1000_phy.h b/sys/dev/e1000/e1000_phy.h
index 0da4a88..93d0afc 100644
--- a/sys/dev/e1000/e1000_phy.h
+++ b/sys/dev/e1000/e1000_phy.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -40,6 +40,7 @@ s32  e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data);
 void e1000_null_phy_generic(struct e1000_hw *hw);
 s32  e1000_null_lplu_state(struct e1000_hw *hw, bool active);
 s32  e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data);
+s32  e1000_null_set_page(struct e1000_hw *hw, u16 data);
 s32  e1000_check_downshift_generic(struct e1000_hw *hw);
 s32  e1000_check_polarity_m88(struct e1000_hw *hw);
 s32  e1000_check_polarity_igp(struct e1000_hw *hw);
@@ -67,6 +68,7 @@ s32  e1000_phy_hw_reset_generic(struct e1000_hw *hw);
 s32  e1000_phy_reset_dsp_generic(struct e1000_hw *hw);
 s32  e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data);
 s32  e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data);
+s32  e1000_set_page_igp(struct e1000_hw *hw, u16 page);
 s32  e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
 s32  e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data);
 s32  e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
@@ -80,12 +82,14 @@ s32  e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data);
 s32  e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
 s32  e1000_phy_reset_dsp(struct e1000_hw *hw);
 s32  e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
-                                u32 usec_interval, bool *success);
+				u32 usec_interval, bool *success);
 s32  e1000_phy_init_script_igp3(struct e1000_hw *hw);
 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id);
 s32  e1000_determine_phy_address(struct e1000_hw *hw);
 s32  e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
 s32  e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
+s32  e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
+s32  e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
 s32  e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
 s32  e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
 void e1000_power_up_phy_copper(struct e1000_hw *hw);
@@ -94,10 +98,14 @@ s32  e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
 s32  e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
 s32  e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
 s32  e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
+s32  e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data);
+s32  e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data);
 s32  e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
 s32  e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data);
+s32  e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data);
 s32  e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
 s32  e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data);
+s32  e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data);
 s32  e1000_link_stall_workaround_hv(struct e1000_hw *hw);
 s32  e1000_copper_link_setup_82577(struct e1000_hw *hw);
 s32  e1000_check_polarity_82577(struct e1000_hw *hw);
@@ -105,34 +113,34 @@ s32  e1000_get_phy_info_82577(struct e1000_hw *hw);
 s32  e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
 s32  e1000_get_cable_length_82577(struct e1000_hw *hw);
 
-#define E1000_MAX_PHY_ADDR                4
+#define E1000_MAX_PHY_ADDR		8
 
 /* IGP01E1000 Specific Registers */
-#define IGP01E1000_PHY_PORT_CONFIG        0x10 /* Port Config */
-#define IGP01E1000_PHY_PORT_STATUS        0x11 /* Status */
-#define IGP01E1000_PHY_PORT_CTRL          0x12 /* Control */
-#define IGP01E1000_PHY_LINK_HEALTH        0x13 /* PHY Link Health */
-#define IGP01E1000_GMII_FIFO              0x14 /* GMII FIFO */
-#define IGP01E1000_PHY_CHANNEL_QUALITY    0x15 /* PHY Channel Quality */
-#define IGP02E1000_PHY_POWER_MGMT         0x19 /* Power Management */
-#define IGP01E1000_PHY_PAGE_SELECT        0x1F /* Page Select */
-#define BM_PHY_PAGE_SELECT                22   /* Page Select for BM */
-#define IGP_PAGE_SHIFT                    5
-#define PHY_REG_MASK                      0x1F
+#define IGP01E1000_PHY_PORT_CONFIG	0x10 /* Port Config */
+#define IGP01E1000_PHY_PORT_STATUS	0x11 /* Status */
+#define IGP01E1000_PHY_PORT_CTRL	0x12 /* Control */
+#define IGP01E1000_PHY_LINK_HEALTH	0x13 /* PHY Link Health */
+#define IGP01E1000_GMII_FIFO		0x14 /* GMII FIFO */
+#define IGP01E1000_PHY_CHANNEL_QUALITY	0x15 /* PHY Channel Quality */
+#define IGP02E1000_PHY_POWER_MGMT	0x19 /* Power Management */
+#define IGP01E1000_PHY_PAGE_SELECT	0x1F /* Page Select */
+#define BM_PHY_PAGE_SELECT		22   /* Page Select for BM */
+#define IGP_PAGE_SHIFT			5
+#define PHY_REG_MASK			0x1F
 
 /* BM/HV Specific Registers */
-#define BM_PORT_CTRL_PAGE                 769
-#define BM_PORT_GEN_CFG_REG               PHY_REG(BM_PORT_CTRL_PAGE, 17)
-#define BM_PCIE_PAGE                      770
-#define BM_WUC_PAGE                       800
-#define BM_WUC_ADDRESS_OPCODE             0x11
-#define BM_WUC_DATA_OPCODE                0x12
-#define BM_WUC_ENABLE_PAGE                BM_PORT_CTRL_PAGE
-#define BM_WUC_ENABLE_REG                 17
-#define BM_WUC_ENABLE_BIT                 (1 << 2)
-#define BM_WUC_HOST_WU_BIT                (1 << 4)
-
-#define PHY_UPPER_SHIFT                   21
+#define BM_PORT_CTRL_PAGE		769
+#define BM_PCIE_PAGE			770
+#define BM_WUC_PAGE			800
+#define BM_WUC_ADDRESS_OPCODE		0x11
+#define BM_WUC_DATA_OPCODE		0x12
+#define BM_WUC_ENABLE_PAGE		BM_PORT_CTRL_PAGE
+#define BM_WUC_ENABLE_REG		17
+#define BM_WUC_ENABLE_BIT		(1 << 2)
+#define BM_WUC_HOST_WU_BIT		(1 << 4)
+#define BM_WUC_ME_WU_BIT		(1 << 5)
+
+#define PHY_UPPER_SHIFT			21
 #define BM_PHY_REG(page, reg) \
 	(((reg) & MAX_PHY_REG_ADDRESS) |\
 	 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
@@ -144,132 +152,156 @@ s32  e1000_get_cable_length_82577(struct e1000_hw *hw);
 	 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
 		~MAX_PHY_REG_ADDRESS)))
 
-#define HV_INTC_FC_PAGE_START             768
-#define I82578_ADDR_REG                   29
-#define I82577_ADDR_REG                   16
-#define I82577_CFG_REG                    22
-#define I82577_CFG_ASSERT_CRS_ON_TX       (1 << 15)
-#define I82577_CFG_ENABLE_DOWNSHIFT       (3 << 10) /* auto downshift 100/10 */
-#define I82577_CTRL_REG                   23
+#define HV_INTC_FC_PAGE_START		768
+#define I82578_ADDR_REG			29
+#define I82577_ADDR_REG			16
+#define I82577_CFG_REG			22
+#define I82577_CFG_ASSERT_CRS_ON_TX	(1 << 15)
+#define I82577_CFG_ENABLE_DOWNSHIFT	(3 << 10) /* auto downshift 100/10 */
+#define I82577_CTRL_REG			23
 
 /* 82577 specific PHY registers */
-#define I82577_PHY_CTRL_2            18
-#define I82577_PHY_LBK_CTRL          19
-#define I82577_PHY_STATUS_2          26
-#define I82577_PHY_DIAG_STATUS       31
+#define I82577_PHY_CTRL_2		18
+#define I82577_PHY_LBK_CTRL		19
+#define I82577_PHY_STATUS_2		26
+#define I82577_PHY_DIAG_STATUS		31
 
 /* I82577 PHY Status 2 */
-#define I82577_PHY_STATUS2_REV_POLARITY   0x0400
-#define I82577_PHY_STATUS2_MDIX           0x0800
-#define I82577_PHY_STATUS2_SPEED_MASK     0x0300
-#define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
-#define I82577_PHY_STATUS2_SPEED_100MBPS  0x0100
+#define I82577_PHY_STATUS2_REV_POLARITY		0x0400
+#define I82577_PHY_STATUS2_MDIX			0x0800
+#define I82577_PHY_STATUS2_SPEED_MASK		0x0300
+#define I82577_PHY_STATUS2_SPEED_1000MBPS	0x0200
+#define I82577_PHY_STATUS2_SPEED_100MBPS	0x0100
 
 /* I82577 PHY Control 2 */
-#define I82577_PHY_CTRL2_AUTO_MDIX        0x0400
-#define I82577_PHY_CTRL2_FORCE_MDI_MDIX   0x0200
+#define I82577_PHY_CTRL2_AUTO_MDIX		0x0400
+#define I82577_PHY_CTRL2_FORCE_MDI_MDIX		0x0200
 
 /* I82577 PHY Diagnostics Status */
-#define I82577_DSTATUS_CABLE_LENGTH       0x03FC
-#define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
+#define I82577_DSTATUS_CABLE_LENGTH		0x03FC
+#define I82577_DSTATUS_CABLE_LENGTH_SHIFT	2
 
 /* 82580 PHY Power Management */
-#define E1000_82580_PHY_POWER_MGMT        0xE14
-#define E1000_82580_PM_SPD                0x0001 /* Smart Power Down */
-#define E1000_82580_PM_D0_LPLU            0x0002 /* For D0a states */
-#define E1000_82580_PM_D3_LPLU            0x0004 /* For all other states */
+#define E1000_82580_PHY_POWER_MGMT	0xE14
+#define E1000_82580_PM_SPD		0x0001 /* Smart Power Down */
+#define E1000_82580_PM_D0_LPLU		0x0002 /* For D0a states */
+#define E1000_82580_PM_D3_LPLU		0x0004 /* For all other states */
 
 /* BM PHY Copper Specific Control 1 */
-#define BM_CS_CTRL1                       16
-#define BM_CS_CTRL1_ENERGY_DETECT         0x0300 /* Enable Energy Detect */
+#define BM_CS_CTRL1			16
+#define BM_CS_CTRL1_ENERGY_DETECT	0x0300 /* Enable Energy Detect */
 
 /* BM PHY Copper Specific Status */
-#define BM_CS_STATUS                      17
-#define BM_CS_STATUS_ENERGY_DETECT        0x0010 /* Energy Detect Status */
-#define BM_CS_STATUS_LINK_UP              0x0400
-#define BM_CS_STATUS_RESOLVED             0x0800
-#define BM_CS_STATUS_SPEED_MASK           0xC000
-#define BM_CS_STATUS_SPEED_1000           0x8000
+#define BM_CS_STATUS			17
+#define BM_CS_STATUS_ENERGY_DETECT	0x0010 /* Energy Detect Status */
+#define BM_CS_STATUS_LINK_UP		0x0400
+#define BM_CS_STATUS_RESOLVED		0x0800
+#define BM_CS_STATUS_SPEED_MASK		0xC000
+#define BM_CS_STATUS_SPEED_1000		0x8000
 
 /* 82577 Mobile Phy Status Register */
-#define HV_M_STATUS                       26
-#define HV_M_STATUS_AUTONEG_COMPLETE      0x1000
-#define HV_M_STATUS_SPEED_MASK            0x0300
-#define HV_M_STATUS_SPEED_1000            0x0200
-#define HV_M_STATUS_LINK_UP               0x0040
+#define HV_M_STATUS			26
+#define HV_M_STATUS_AUTONEG_COMPLETE	0x1000
+#define HV_M_STATUS_SPEED_MASK		0x0300
+#define HV_M_STATUS_SPEED_1000		0x0200
+#define HV_M_STATUS_LINK_UP		0x0040
 
-#define IGP01E1000_PHY_PCS_INIT_REG       0x00B4
-#define IGP01E1000_PHY_POLARITY_MASK      0x0078
+#define IGP01E1000_PHY_PCS_INIT_REG	0x00B4
+#define IGP01E1000_PHY_POLARITY_MASK	0x0078
 
-#define IGP01E1000_PSCR_AUTO_MDIX         0x1000
-#define IGP01E1000_PSCR_FORCE_MDI_MDIX    0x2000 /* 0=MDI, 1=MDIX */
+#define IGP01E1000_PSCR_AUTO_MDIX	0x1000
+#define IGP01E1000_PSCR_FORCE_MDI_MDIX	0x2000 /* 0=MDI, 1=MDIX */
 
-#define IGP01E1000_PSCFR_SMART_SPEED      0x0080
+#define IGP01E1000_PSCFR_SMART_SPEED	0x0080
 
 /* Enable flexible speed on link-up */
-#define IGP01E1000_GMII_FLEX_SPD          0x0010
-#define IGP01E1000_GMII_SPD               0x0020 /* Enable SPD */
-
-#define IGP02E1000_PM_SPD                 0x0001 /* Smart Power Down */
-#define IGP02E1000_PM_D0_LPLU             0x0002 /* For D0a states */
-#define IGP02E1000_PM_D3_LPLU             0x0004 /* For all other states */
-
-#define IGP01E1000_PLHR_SS_DOWNGRADE      0x8000
-
-#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
-#define IGP01E1000_PSSR_MDIX              0x0800
-#define IGP01E1000_PSSR_SPEED_MASK        0xC000
-#define IGP01E1000_PSSR_SPEED_1000MBPS    0xC000
-
-#define IGP02E1000_PHY_CHANNEL_NUM        4
-#define IGP02E1000_PHY_AGC_A              0x11B1
-#define IGP02E1000_PHY_AGC_B              0x12B1
-#define IGP02E1000_PHY_AGC_C              0x14B1
-#define IGP02E1000_PHY_AGC_D              0x18B1
-
-#define IGP02E1000_AGC_LENGTH_SHIFT       9   /* Course - 15:13, Fine - 12:9 */
-#define IGP02E1000_AGC_LENGTH_MASK        0x7F
-#define IGP02E1000_AGC_RANGE              15
-
-#define IGP03E1000_PHY_MISC_CTRL          0x1B
-#define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET  0x1000 /* Manually Set Duplex */
-
-#define E1000_CABLE_LENGTH_UNDEFINED      0xFF
-
-#define E1000_KMRNCTRLSTA_OFFSET          0x001F0000
-#define E1000_KMRNCTRLSTA_OFFSET_SHIFT    16
-#define E1000_KMRNCTRLSTA_REN             0x00200000
-#define E1000_KMRNCTRLSTA_CTRL_OFFSET     0x1    /* Kumeran Control */
-#define E1000_KMRNCTRLSTA_DIAG_OFFSET     0x3    /* Kumeran Diagnostic */
-#define E1000_KMRNCTRLSTA_TIMEOUTS        0x4    /* Kumeran Timeouts */
-#define E1000_KMRNCTRLSTA_INBAND_PARAM    0x9    /* Kumeran InBand Parameters */
-#define E1000_KMRNCTRLSTA_IBIST_DISABLE   0x0200 /* Kumeran IBIST Disable */
-#define E1000_KMRNCTRLSTA_DIAG_NELPBK     0x1000 /* Nearend Loopback mode */
-#define E1000_KMRNCTRLSTA_K1_CONFIG        0x7
-#define E1000_KMRNCTRLSTA_K1_ENABLE        0x0002
-#define E1000_KMRNCTRLSTA_HD_CTRL         0x10   /* Kumeran HD Control */
-
-#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
-#define IFE_PHY_SPECIAL_CONTROL     0x11 /* 100BaseTx PHY Special Control */
-#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
-#define IFE_PHY_MDIX_CONTROL        0x1C /* MDI/MDI-X Control */
+#define IGP01E1000_GMII_FLEX_SPD	0x0010
+#define IGP01E1000_GMII_SPD		0x0020 /* Enable SPD */
+
+#define IGP02E1000_PM_SPD		0x0001 /* Smart Power Down */
+#define IGP02E1000_PM_D0_LPLU		0x0002 /* For D0a states */
+#define IGP02E1000_PM_D3_LPLU		0x0004 /* For all other states */
+
+#define IGP01E1000_PLHR_SS_DOWNGRADE	0x8000
+
+#define IGP01E1000_PSSR_POLARITY_REVERSED	0x0002
+#define IGP01E1000_PSSR_MDIX		0x0800
+#define IGP01E1000_PSSR_SPEED_MASK	0xC000
+#define IGP01E1000_PSSR_SPEED_1000MBPS	0xC000
+
+#define IGP02E1000_PHY_CHANNEL_NUM	4
+#define IGP02E1000_PHY_AGC_A		0x11B1
+#define IGP02E1000_PHY_AGC_B		0x12B1
+#define IGP02E1000_PHY_AGC_C		0x14B1
+#define IGP02E1000_PHY_AGC_D		0x18B1
+
+#define IGP02E1000_AGC_LENGTH_SHIFT	9   /* Course - 15:13, Fine - 12:9 */
+#define IGP02E1000_AGC_LENGTH_MASK	0x7F
+#define IGP02E1000_AGC_RANGE		15
+
+#define IGP03E1000_PHY_MISC_CTRL	0x1B
+#define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET	0x1000 /* Manually Set Duplex */
+
+#define E1000_CABLE_LENGTH_UNDEFINED	0xFF
+
+#define E1000_KMRNCTRLSTA_OFFSET	0x001F0000
+#define E1000_KMRNCTRLSTA_OFFSET_SHIFT	16
+#define E1000_KMRNCTRLSTA_REN		0x00200000
+#define E1000_KMRNCTRLSTA_CTRL_OFFSET	0x1    /* Kumeran Control */
+#define E1000_KMRNCTRLSTA_DIAG_OFFSET	0x3    /* Kumeran Diagnostic */
+#define E1000_KMRNCTRLSTA_TIMEOUTS	0x4    /* Kumeran Timeouts */
+#define E1000_KMRNCTRLSTA_INBAND_PARAM	0x9    /* Kumeran InBand Parameters */
+#define E1000_KMRNCTRLSTA_IBIST_DISABLE	0x0200 /* Kumeran IBIST Disable */
+#define E1000_KMRNCTRLSTA_DIAG_NELPBK	0x1000 /* Nearend Loopback mode */
+#define E1000_KMRNCTRLSTA_K1_CONFIG	0x7
+#define E1000_KMRNCTRLSTA_K1_ENABLE	0x0002
+#define E1000_KMRNCTRLSTA_HD_CTRL	0x10   /* Kumeran HD Control */
+
+#define IFE_PHY_EXTENDED_STATUS_CONTROL	0x10
+#define IFE_PHY_SPECIAL_CONTROL		0x11 /* 100BaseTx PHY Special Control */
+#define IFE_PHY_SPECIAL_CONTROL_LED	0x1B /* PHY Special and LED Control */
+#define IFE_PHY_MDIX_CONTROL		0x1C /* MDI/MDI-X Control */
 
 /* IFE PHY Extended Status Control */
-#define IFE_PESC_POLARITY_REVERSED    0x0100
+#define IFE_PESC_POLARITY_REVERSED	0x0100
 
 /* IFE PHY Special Control */
-#define IFE_PSC_AUTO_POLARITY_DISABLE      0x0010
-#define IFE_PSC_FORCE_POLARITY             0x0020
-#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100
+#define IFE_PSC_AUTO_POLARITY_DISABLE	0x0010
+#define IFE_PSC_FORCE_POLARITY		0x0020
+#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN	0x0100
 
 /* IFE PHY Special Control and LED Control */
-#define IFE_PSCL_PROBE_MODE            0x0020
-#define IFE_PSCL_PROBE_LEDS_OFF        0x0006 /* Force LEDs 0 and 2 off */
-#define IFE_PSCL_PROBE_LEDS_ON         0x0007 /* Force LEDs 0 and 2 on */
+#define IFE_PSCL_PROBE_MODE		0x0020
+#define IFE_PSCL_PROBE_LEDS_OFF		0x0006 /* Force LEDs 0 and 2 off */
+#define IFE_PSCL_PROBE_LEDS_ON		0x0007 /* Force LEDs 0 and 2 on */
 
 /* IFE PHY MDIX Control */
-#define IFE_PMC_MDIX_STATUS      0x0020 /* 1=MDI-X, 0=MDI */
-#define IFE_PMC_FORCE_MDIX       0x0040 /* 1=force MDI-X, 0=force MDI */
-#define IFE_PMC_AUTO_MDIX        0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
+#define IFE_PMC_MDIX_STATUS		0x0020 /* 1=MDI-X, 0=MDI */
+#define IFE_PMC_FORCE_MDIX		0x0040 /* 1=force MDI-X, 0=force MDI */
+#define IFE_PMC_AUTO_MDIX		0x0080 /* 1=enable auto, 0=disable */
+
+/* SFP modules ID memory locations */
+#define E1000_SFF_IDENTIFIER_OFFSET	0x00
+#define E1000_SFF_IDENTIFIER_SFF	0x02
+#define E1000_SFF_IDENTIFIER_SFP	0x03
+
+#define E1000_SFF_ETH_FLAGS_OFFSET	0x06
+/* Flags for SFP modules compatible with ETH up to 1Gb */
+struct sfp_e1000_flags {
+	u8 e1000_base_sx:1;
+	u8 e1000_base_lx:1;
+	u8 e1000_base_cx:1;
+	u8 e1000_base_t:1;
+	u8 e100_base_lx:1;
+	u8 e100_base_fx:1;
+	u8 e10_base_bx10:1;
+	u8 e10_base_px:1;
+};
+
+/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
+#define E1000_SFF_VENDOR_OUI_TYCO	0x00407600
+#define E1000_SFF_VENDOR_OUI_FTL	0x00906500
+#define E1000_SFF_VENDOR_OUI_AVAGO	0x00176A00
+#define E1000_SFF_VENDOR_OUI_INTEL	0x001B2100
 
 #endif
diff --git a/sys/dev/e1000/e1000_regs.h b/sys/dev/e1000/e1000_regs.h
index f3f265d..2cc89d5 100644
--- a/sys/dev/e1000/e1000_regs.h
+++ b/sys/dev/e1000/e1000_regs.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -35,104 +35,114 @@
 #ifndef _E1000_REGS_H_
 #define _E1000_REGS_H_
 
-#define E1000_CTRL     0x00000  /* Device Control - RW */
-#define E1000_CTRL_DUP 0x00004  /* Device Control Duplicate (Shadow) - RW */
-#define E1000_STATUS   0x00008  /* Device Status - RO */
-#define E1000_EECD     0x00010  /* EEPROM/Flash Control - RW */
-#define E1000_EERD     0x00014  /* EEPROM Read - RW */
-#define E1000_CTRL_EXT 0x00018  /* Extended Device Control - RW */
-#define E1000_FLA      0x0001C  /* Flash Access - RW */
-#define E1000_MDIC     0x00020  /* MDI Control - RW */
-#define E1000_MDICNFG  0x00E04  /* MDI Config - RW */
-#define E1000_REGISTER_SET_SIZE        0x20000 /* CSR Size */
-#define E1000_EEPROM_INIT_CTRL_WORD_2  0x0F /* EEPROM Init Ctrl Word 2 */
-#define E1000_BARCTRL                  0x5BBC /* BAR ctrl reg */
-#define E1000_BARCTRL_FLSIZE           0x0700 /* BAR ctrl Flsize */
-#define E1000_BARCTRL_CSRSIZE          0x2000 /* BAR ctrl CSR size */
-#define E1000_SCTL     0x00024  /* SerDes Control - RW */
-#define E1000_FCAL     0x00028  /* Flow Control Address Low - RW */
-#define E1000_FCAH     0x0002C  /* Flow Control Address High -RW */
-#define E1000_FEXT     0x0002C  /* Future Extended - RW */
-#define E1000_FEXTNVM4 0x00024  /* Future Extended NVM 4 - RW */
-#define E1000_FEXTNVM  0x00028  /* Future Extended NVM - RW */
-#define E1000_FCT      0x00030  /* Flow Control Type - RW */
-#define E1000_CONNSW   0x00034  /* Copper/Fiber switch control - RW */
-#define E1000_VET      0x00038  /* VLAN Ether Type - RW */
-#define E1000_ICR      0x000C0  /* Interrupt Cause Read - R/clr */
-#define E1000_ITR      0x000C4  /* Interrupt Throttling Rate - RW */
-#define E1000_ICS      0x000C8  /* Interrupt Cause Set - WO */
-#define E1000_IMS      0x000D0  /* Interrupt Mask Set - RW */
-#define E1000_IMC      0x000D8  /* Interrupt Mask Clear - WO */
-#define E1000_IAM      0x000E0  /* Interrupt Acknowledge Auto Mask */
-#define E1000_IVAR     0x000E4  /* Interrupt Vector Allocation Register - RW */
-#define E1000_SVCR     0x000F0
-#define E1000_SVT      0x000F4
-#define E1000_RCTL     0x00100  /* Rx Control - RW */
-#define E1000_FCTTV    0x00170  /* Flow Control Transmit Timer Value - RW */
-#define E1000_TXCW     0x00178  /* Tx Configuration Word - RW */
-#define E1000_RXCW     0x00180  /* Rx Configuration Word - RO */
-#define E1000_PBA_ECC  0x01100  /* PBA ECC Register */
-#define E1000_EICR     0x01580  /* Ext. Interrupt Cause Read - R/clr */
-#define E1000_EITR(_n) (0x01680 + (0x4 * (_n)))
-#define E1000_EICS     0x01520  /* Ext. Interrupt Cause Set - W0 */
-#define E1000_EIMS     0x01524  /* Ext. Interrupt Mask Set/Read - RW */
-#define E1000_EIMC     0x01528  /* Ext. Interrupt Mask Clear - WO */
-#define E1000_EIAC     0x0152C  /* Ext. Interrupt Auto Clear - RW */
-#define E1000_EIAM     0x01530  /* Ext. Interrupt Ack Auto Clear Mask - RW */
-#define E1000_GPIE     0x01514  /* General Purpose Interrupt Enable - RW */
-#define E1000_IVAR0    0x01700  /* Interrupt Vector Allocation (array) - RW */
-#define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
-#define E1000_TCTL     0x00400  /* Tx Control - RW */
-#define E1000_TCTL_EXT 0x00404  /* Extended Tx Control - RW */
-#define E1000_TIPG     0x00410  /* Tx Inter-packet gap -RW */
-#define E1000_TBT      0x00448  /* Tx Burst Timer - RW */
-#define E1000_AIT      0x00458  /* Adaptive Interframe Spacing Throttle - RW */
-#define E1000_LEDCTL   0x00E00  /* LED Control - RW */
-#define E1000_EXTCNF_CTRL  0x00F00  /* Extended Configuration Control */
-#define E1000_EXTCNF_SIZE  0x00F08  /* Extended Configuration Size */
-#define E1000_PHY_CTRL     0x00F10  /* PHY Control Register in CSR */
-#define E1000_POEMB        E1000_PHY_CTRL /* PHY OEM Bits */
-#define E1000_PBA      0x01000  /* Packet Buffer Allocation - RW */
-#define E1000_PBS      0x01008  /* Packet Buffer Size */
-#define E1000_EEMNGCTL 0x01010  /* MNG EEprom Control */
-#define E1000_EEARBC   0x01024  /* EEPROM Auto Read Bus Control */
-#define E1000_FLASHT   0x01028  /* FLASH Timer Register */
-#define E1000_EEWR     0x0102C  /* EEPROM Write Register - RW */
-#define E1000_FLSWCTL  0x01030  /* FLASH control register */
-#define E1000_FLSWDATA 0x01034  /* FLASH data register */
-#define E1000_FLSWCNT  0x01038  /* FLASH Access Counter */
-#define E1000_FLOP     0x0103C  /* FLASH Opcode Register */
-#define E1000_I2CCMD   0x01028  /* SFPI2C Command Register - RW */
-#define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */
-#define E1000_WDSTP    0x01040  /* Watchdog Setup - RW */
-#define E1000_SWDSTS   0x01044  /* SW Device Status - RW */
-#define E1000_FRTIMER  0x01048  /* Free Running Timer - RW */
-#define E1000_TCPTIMER 0x0104C  /* TCP Timer - RW */
-#define E1000_VPDDIAG  0x01060  /* VPD Diagnostic - RO */
-#define E1000_ICR_V2   0x01500  /* Interrupt Cause - new location - RC */
-#define E1000_ICS_V2   0x01504  /* Interrupt Cause Set - new location - WO */
-#define E1000_IMS_V2   0x01508  /* Interrupt Mask Set/Read - new location - RW */
-#define E1000_IMC_V2   0x0150C  /* Interrupt Mask Clear - new location - WO */
-#define E1000_IAM_V2   0x01510  /* Interrupt Ack Auto Mask - new location - RW */
-#define E1000_ERT      0x02008  /* Early Rx Threshold - RW */
-#define E1000_FCRTL    0x02160  /* Flow Control Receive Threshold Low - RW */
-#define E1000_FCRTH    0x02168  /* Flow Control Receive Threshold High - RW */
-#define E1000_PSRCTL   0x02170  /* Packet Split Receive Control - RW */
-#define E1000_RDFPCQ(_n)  (0x02430 + (0x4 * (_n)))
-#define E1000_PBRTH    0x02458  /* PB Rx Arbitration Threshold - RW */
-#define E1000_FCRTV    0x02460  /* Flow Control Refresh Timer Value - RW */
+#define E1000_CTRL	0x00000  /* Device Control - RW */
+#define E1000_CTRL_DUP	0x00004  /* Device Control Duplicate (Shadow) - RW */
+#define E1000_STATUS	0x00008  /* Device Status - RO */
+#define E1000_EECD	0x00010  /* EEPROM/Flash Control - RW */
+#define E1000_EERD	0x00014  /* EEPROM Read - RW */
+#define E1000_CTRL_EXT	0x00018  /* Extended Device Control - RW */
+#define E1000_FLA	0x0001C  /* Flash Access - RW */
+#define E1000_MDIC	0x00020  /* MDI Control - RW */
+#define E1000_MDICNFG	0x00E04  /* MDI Config - RW */
+#define E1000_REGISTER_SET_SIZE		0x20000 /* CSR Size */
+#define E1000_EEPROM_INIT_CTRL_WORD_2	0x0F /* EEPROM Init Ctrl Word 2 */
+#define E1000_EEPROM_PCIE_CTRL_WORD_2	0x28 /* EEPROM PCIe Ctrl Word 2 */
+#define E1000_BARCTRL			0x5BBC /* BAR ctrl reg */
+#define E1000_BARCTRL_FLSIZE		0x0700 /* BAR ctrl Flsize */
+#define E1000_BARCTRL_CSRSIZE		0x2000 /* BAR ctrl CSR size */
+#define E1000_I350_BARCTRL		0x5BFC /* BAR ctrl reg */
+#define E1000_SCTL	0x00024  /* SerDes Control - RW */
+#define E1000_FCAL	0x00028  /* Flow Control Address Low - RW */
+#define E1000_FCAH	0x0002C  /* Flow Control Address High -RW */
+#define E1000_FEXT	0x0002C  /* Future Extended - RW */
+#define E1000_FEXTNVM4	0x00024  /* Future Extended NVM 4 - RW */
+#define E1000_FEXTNVM	0x00028  /* Future Extended NVM - RW */
+#define E1000_FCT	0x00030  /* Flow Control Type - RW */
+#define E1000_CONNSW	0x00034  /* Copper/Fiber switch control - RW */
+#define E1000_VET	0x00038  /* VLAN Ether Type - RW */
+#define E1000_ICR	0x000C0  /* Interrupt Cause Read - R/clr */
+#define E1000_ITR	0x000C4  /* Interrupt Throttling Rate - RW */
+#define E1000_ICS	0x000C8  /* Interrupt Cause Set - WO */
+#define E1000_IMS	0x000D0  /* Interrupt Mask Set - RW */
+#define E1000_IMC	0x000D8  /* Interrupt Mask Clear - WO */
+#define E1000_IAM	0x000E0  /* Interrupt Acknowledge Auto Mask */
+#define E1000_IVAR	0x000E4  /* Interrupt Vector Allocation Register - RW */
+#define E1000_SVCR	0x000F0
+#define E1000_SVT	0x000F4
+#define E1000_RCTL	0x00100  /* Rx Control - RW */
+#define E1000_FCTTV	0x00170  /* Flow Control Transmit Timer Value - RW */
+#define E1000_TXCW	0x00178  /* Tx Configuration Word - RW */
+#define E1000_RXCW	0x00180  /* Rx Configuration Word - RO */
+#define E1000_PBA_ECC	0x01100  /* PBA ECC Register */
+#define E1000_EICR	0x01580  /* Ext. Interrupt Cause Read - R/clr */
+#define E1000_EITR(_n)	(0x01680 + (0x4 * (_n)))
+#define E1000_EICS	0x01520  /* Ext. Interrupt Cause Set - W0 */
+#define E1000_EIMS	0x01524  /* Ext. Interrupt Mask Set/Read - RW */
+#define E1000_EIMC	0x01528  /* Ext. Interrupt Mask Clear - WO */
+#define E1000_EIAC	0x0152C  /* Ext. Interrupt Auto Clear - RW */
+#define E1000_EIAM	0x01530  /* Ext. Interrupt Ack Auto Clear Mask - RW */
+#define E1000_GPIE	0x01514  /* General Purpose Interrupt Enable - RW */
+#define E1000_IVAR0	0x01700  /* Interrupt Vector Allocation (array) - RW */
+#define E1000_IVAR_MISC	0x01740 /* IVAR for "other" causes - RW */
+#define E1000_TCTL	0x00400  /* Tx Control - RW */
+#define E1000_TCTL_EXT	0x00404  /* Extended Tx Control - RW */
+#define E1000_TIPG	0x00410  /* Tx Inter-packet gap -RW */
+#define E1000_TBT	0x00448  /* Tx Burst Timer - RW */
+#define E1000_AIT	0x00458  /* Adaptive Interframe Spacing Throttle - RW */
+#define E1000_LEDCTL	0x00E00  /* LED Control - RW */
+#define E1000_EXTCNF_CTRL	0x00F00  /* Extended Configuration Control */
+#define E1000_EXTCNF_SIZE	0x00F08  /* Extended Configuration Size */
+#define E1000_PHY_CTRL	0x00F10  /* PHY Control Register in CSR */
+#define E1000_POEMB	E1000_PHY_CTRL /* PHY OEM Bits */
+#define E1000_PBA	0x01000  /* Packet Buffer Allocation - RW */
+#define E1000_PBS	0x01008  /* Packet Buffer Size */
+#define E1000_EEMNGCTL	0x01010  /* MNG EEprom Control */
+#define E1000_EEARBC	0x01024  /* EEPROM Auto Read Bus Control */
+#define E1000_FLASHT	0x01028  /* FLASH Timer Register */
+#define E1000_EEWR	0x0102C  /* EEPROM Write Register - RW */
+#define E1000_FLSWCTL	0x01030  /* FLASH control register */
+#define E1000_FLSWDATA	0x01034  /* FLASH data register */
+#define E1000_FLSWCNT	0x01038  /* FLASH Access Counter */
+#define E1000_FLOP	0x0103C  /* FLASH Opcode Register */
+#define E1000_I2CCMD	0x01028  /* SFPI2C Command Register - RW */
+#define E1000_I2CPARAMS	0x0102C /* SFPI2C Parameters Register - RW */
+#define E1000_I2CBB_EN	0x00000100  /* I2C - Bit Bang Enable */
+#define E1000_I2C_CLK_OUT	0x00000200  /* I2C- Clock */
+#define E1000_I2C_DATA_OUT	0x00000400  /* I2C- Data Out */
+#define E1000_I2C_DATA_OE_N	0x00000800  /* I2C- Data Output Enable */
+#define E1000_I2C_DATA_IN	0x00001000  /* I2C- Data In */
+#define E1000_I2C_CLK_OE_N	0x00002000  /* I2C- Clock Output Enable */
+#define E1000_I2C_CLK_IN	0x00004000  /* I2C- Clock In */
+#define E1000_I2C_CLK_STRETCH_DIS	0x00008000 /* I2C- Dis Clk Stretching */
+#define E1000_WDSTP	0x01040  /* Watchdog Setup - RW */
+#define E1000_SWDSTS	0x01044  /* SW Device Status - RW */
+#define E1000_FRTIMER	0x01048  /* Free Running Timer - RW */
+#define E1000_TCPTIMER	0x0104C  /* TCP Timer - RW */
+#define E1000_VPDDIAG	0x01060  /* VPD Diagnostic - RO */
+#define E1000_ICR_V2	0x01500  /* Intr Cause - new location - RC */
+#define E1000_ICS_V2	0x01504  /* Intr Cause Set - new location - WO */
+#define E1000_IMS_V2	0x01508  /* Intr Mask Set/Read - new location - RW */
+#define E1000_IMC_V2	0x0150C  /* Intr Mask Clear - new location - WO */
+#define E1000_IAM_V2	0x01510  /* Intr Ack Auto Mask - new location - RW */
+#define E1000_ERT	0x02008  /* Early Rx Threshold - RW */
+#define E1000_FCRTL	0x02160  /* Flow Control Receive Threshold Low - RW */
+#define E1000_FCRTH	0x02168  /* Flow Control Receive Threshold High - RW */
+#define E1000_PSRCTL	0x02170  /* Packet Split Receive Control - RW */
+#define E1000_RDFPCQ(_n)	(0x02430 + (0x4 * (_n)))
+#define E1000_PBRTH	0x02458  /* PB Rx Arbitration Threshold - RW */
+#define E1000_FCRTV	0x02460  /* Flow Control Refresh Timer Value - RW */
 /* Split and Replication Rx Control - RW */
-#define E1000_RDPUMB   0x025CC  /* DMA Rx Descriptor uC Mailbox - RW */
-#define E1000_RDPUAD   0x025D0  /* DMA Rx Descriptor uC Addr Command - RW */
-#define E1000_RDPUWD   0x025D4  /* DMA Rx Descriptor uC Data Write - RW */
-#define E1000_RDPURD   0x025D8  /* DMA Rx Descriptor uC Data Read - RW */
-#define E1000_RDPUCTL  0x025DC  /* DMA Rx Descriptor uC Control - RW */
-#define E1000_PBDIAG   0x02458  /* Packet Buffer Diagnostic - RW */
-#define E1000_RXPBS    0x02404  /* Rx Packet Buffer Size - RW */
-#define E1000_IRPBS 0x02404 /* Same as RXPBS, renamed for newer adapters - RW */
-#define E1000_PBRWAC   0x024E8 /* Rx packet buffer wrap around counter - RO */
-#define E1000_RDTR     0x02820  /* Rx Delay Timer - RW */
-#define E1000_RADV     0x0282C  /* Rx Interrupt Absolute Delay Timer - RW */
+#define E1000_RDPUMB	0x025CC  /* DMA Rx Descriptor uC Mailbox - RW */
+#define E1000_RDPUAD	0x025D0  /* DMA Rx Descriptor uC Addr Command - RW */
+#define E1000_RDPUWD	0x025D4  /* DMA Rx Descriptor uC Data Write - RW */
+#define E1000_RDPURD	0x025D8  /* DMA Rx Descriptor uC Data Read - RW */
+#define E1000_RDPUCTL	0x025DC  /* DMA Rx Descriptor uC Control - RW */
+#define E1000_PBDIAG	0x02458  /* Packet Buffer Diagnostic - RW */
+#define E1000_RXPBS	0x02404  /* Rx Packet Buffer Size - RW */
+#define E1000_IRPBS	0x02404 /* Same as RXPBS, renamed for newer Si - RW */
+#define E1000_PBRWAC	0x024E8 /* Rx packet buffer wrap around counter - RO */
+#define E1000_RDTR	0x02820  /* Rx Delay Timer - RW */
+#define E1000_RADV	0x0282C  /* Rx Interrupt Absolute Delay Timer - RW */
 /*
  * Convenience macros
  *
@@ -141,442 +151,470 @@
  * Example usage:
  * E1000_RDBAL_REG(current_rx_queue)
  */
-#define E1000_RDBAL(_n)      ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \
-                                         (0x0C000 + ((_n) * 0x40)))
-#define E1000_RDBAH(_n)      ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \
-                                         (0x0C004 + ((_n) * 0x40)))
-#define E1000_RDLEN(_n)      ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \
-                                         (0x0C008 + ((_n) * 0x40)))
-#define E1000_SRRCTL(_n)     ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \
-                                         (0x0C00C + ((_n) * 0x40)))
-#define E1000_RDH(_n)        ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \
-                                         (0x0C010 + ((_n) * 0x40)))
-#define E1000_RXCTL(_n)      ((_n) < 4 ? (0x02814 + ((_n) * 0x100)) : \
-                                         (0x0C014 + ((_n) * 0x40)))
-#define E1000_DCA_RXCTRL(_n) E1000_RXCTL(_n)
-#define E1000_RDT(_n)        ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \
-                                         (0x0C018 + ((_n) * 0x40)))
-#define E1000_RXDCTL(_n)     ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \
-                                         (0x0C028 + ((_n) * 0x40)))
-#define E1000_RQDPC(_n)      ((_n) < 4 ? (0x02830 + ((_n) * 0x100)) : \
-                                         (0x0C030 + ((_n) * 0x40)))
-#define E1000_TDBAL(_n)      ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \
-                                         (0x0E000 + ((_n) * 0x40)))
-#define E1000_TDBAH(_n)      ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \
-                                         (0x0E004 + ((_n) * 0x40)))
-#define E1000_TDLEN(_n)      ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \
-                                         (0x0E008 + ((_n) * 0x40)))
-#define E1000_TDH(_n)        ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \
-                                         (0x0E010 + ((_n) * 0x40)))
-#define E1000_TXCTL(_n)      ((_n) < 4 ? (0x03814 + ((_n) * 0x100)) : \
-                                         (0x0E014 + ((_n) * 0x40)))
+#define E1000_RDBAL(_n)	((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \
+			 (0x0C000 + ((_n) * 0x40)))
+#define E1000_RDBAH(_n)	((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \
+			 (0x0C004 + ((_n) * 0x40)))
+#define E1000_RDLEN(_n)	((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \
+			 (0x0C008 + ((_n) * 0x40)))
+#define E1000_SRRCTL(_n)	((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \
+				 (0x0C00C + ((_n) * 0x40)))
+#define E1000_RDH(_n)	((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \
+			 (0x0C010 + ((_n) * 0x40)))
+#define E1000_RXCTL(_n)	((_n) < 4 ? (0x02814 + ((_n) * 0x100)) : \
+			 (0x0C014 + ((_n) * 0x40)))
+#define E1000_DCA_RXCTRL(_n)	E1000_RXCTL(_n)
+#define E1000_RDT(_n)	((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \
+			 (0x0C018 + ((_n) * 0x40)))
+#define E1000_RXDCTL(_n)	((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \
+				 (0x0C028 + ((_n) * 0x40)))
+#define E1000_RQDPC(_n)	((_n) < 4 ? (0x02830 + ((_n) * 0x100)) : \
+			 (0x0C030 + ((_n) * 0x40)))
+#define E1000_TDBAL(_n)	((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \
+			 (0x0E000 + ((_n) * 0x40)))
+#define E1000_TDBAH(_n)	((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \
+			 (0x0E004 + ((_n) * 0x40)))
+#define E1000_TDLEN(_n)	((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \
+			 (0x0E008 + ((_n) * 0x40)))
+#define E1000_TDH(_n)	((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \
+			 (0x0E010 + ((_n) * 0x40)))
+#define E1000_TXCTL(_n)	((_n) < 4 ? (0x03814 + ((_n) * 0x100)) : \
+			 (0x0E014 + ((_n) * 0x40)))
 #define E1000_DCA_TXCTRL(_n) E1000_TXCTL(_n)
-#define E1000_TDT(_n)        ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \
-                                         (0x0E018 + ((_n) * 0x40)))
-#define E1000_TXDCTL(_n)     ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \
-                                         (0x0E028 + ((_n) * 0x40)))
-#define E1000_TDWBAL(_n)     ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) : \
-                                         (0x0E038 + ((_n) * 0x40)))
-#define E1000_TDWBAH(_n)     ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) : \
-                                         (0x0E03C + ((_n) * 0x40)))
-#define E1000_TARC(_n)                   (0x03840 + ((_n) * 0x100))
-#define E1000_RSRPD    0x02C00  /* Rx Small Packet Detect - RW */
-#define E1000_RAID     0x02C08  /* Receive Ack Interrupt Delay - RW */
-#define E1000_TXDMAC   0x03000  /* Tx DMA Control - RW */
-#define E1000_KABGTXD  0x03004  /* AFE Band Gap Transmit Ref Data */
-#define E1000_PSRTYPE(_i)       (0x05480 + ((_i) * 4))
-#define E1000_RAL(_i)  (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
-                                       (0x054E0 + ((_i - 16) * 8)))
-#define E1000_RAH(_i)  (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
-                                       (0x054E4 + ((_i - 16) * 8)))
-#define E1000_SHRAL(_i)         (0x05438 + ((_i) * 8))
-#define E1000_SHRAH(_i)         (0x0543C + ((_i) * 8))
-#define E1000_IP4AT_REG(_i)     (0x05840 + ((_i) * 8))
-#define E1000_IP6AT_REG(_i)     (0x05880 + ((_i) * 4))
-#define E1000_WUPM_REG(_i)      (0x05A00 + ((_i) * 4))
-#define E1000_FFMT_REG(_i)      (0x09000 + ((_i) * 8))
-#define E1000_FFVT_REG(_i)      (0x09800 + ((_i) * 8))
-#define E1000_FFLT_REG(_i)      (0x05F00 + ((_i) * 8))
-#define E1000_PBSLAC   0x03100  /* Packet Buffer Slave Access Control */
-#define E1000_PBSLAD(_n)  (0x03110 + (0x4 * (_n)))  /* Packet Buffer DWORD (_n) */
-#define E1000_TXPBS    0x03404  /* Tx Packet Buffer Size - RW */
-#define E1000_ITPBS   0x03404   /* Same as TXPBS, renamed for newer adpaters - RW */
-#define E1000_TDFH     0x03410  /* Tx Data FIFO Head - RW */
-#define E1000_TDFT     0x03418  /* Tx Data FIFO Tail - RW */
-#define E1000_TDFHS    0x03420  /* Tx Data FIFO Head Saved - RW */
-#define E1000_TDFTS    0x03428  /* Tx Data FIFO Tail Saved - RW */
-#define E1000_TDFPC    0x03430  /* Tx Data FIFO Packet Count - RW */
-#define E1000_TDPUMB   0x0357C  /* DMA Tx Descriptor uC Mail Box - RW */
-#define E1000_TDPUAD   0x03580  /* DMA Tx Descriptor uC Addr Command - RW */
-#define E1000_TDPUWD   0x03584  /* DMA Tx Descriptor uC Data Write - RW */
-#define E1000_TDPURD   0x03588  /* DMA Tx Descriptor uC Data  Read  - RW */
-#define E1000_TDPUCTL  0x0358C  /* DMA Tx Descriptor uC Control - RW */
-#define E1000_DTXCTL   0x03590  /* DMA Tx Control - RW */
-#define E1000_DTXTCPFLGL 0x0359C /* DMA Tx Control flag low - RW */
-#define E1000_DTXTCPFLGH 0x035A0 /* DMA Tx Control flag high - RW */
-#define E1000_DTXMXSZRQ  0x03540 /* DMA Tx Max Total Allow Size Requests - RW */
-#define E1000_TIDV     0x03820  /* Tx Interrupt Delay Value - RW */
-#define E1000_TADV     0x0382C  /* Tx Interrupt Absolute Delay Val - RW */
-#define E1000_TSPMT    0x03830  /* TCP Segmentation PAD & Min Threshold - RW */
-#define E1000_CRCERRS  0x04000  /* CRC Error Count - R/clr */
-#define E1000_ALGNERRC 0x04004  /* Alignment Error Count - R/clr */
-#define E1000_SYMERRS  0x04008  /* Symbol Error Count - R/clr */
-#define E1000_RXERRC   0x0400C  /* Receive Error Count - R/clr */
-#define E1000_MPC      0x04010  /* Missed Packet Count - R/clr */
-#define E1000_SCC      0x04014  /* Single Collision Count - R/clr */
-#define E1000_ECOL     0x04018  /* Excessive Collision Count - R/clr */
-#define E1000_MCC      0x0401C  /* Multiple Collision Count - R/clr */
-#define E1000_LATECOL  0x04020  /* Late Collision Count - R/clr */
-#define E1000_COLC     0x04028  /* Collision Count - R/clr */
-#define E1000_DC       0x04030  /* Defer Count - R/clr */
-#define E1000_TNCRS    0x04034  /* Tx-No CRS - R/clr */
-#define E1000_SEC      0x04038  /* Sequence Error Count - R/clr */
-#define E1000_CEXTERR  0x0403C  /* Carrier Extension Error Count - R/clr */
-#define E1000_RLEC     0x04040  /* Receive Length Error Count - R/clr */
-#define E1000_XONRXC   0x04048  /* XON Rx Count - R/clr */
-#define E1000_XONTXC   0x0404C  /* XON Tx Count - R/clr */
-#define E1000_XOFFRXC  0x04050  /* XOFF Rx Count - R/clr */
-#define E1000_XOFFTXC  0x04054  /* XOFF Tx Count - R/clr */
-#define E1000_FCRUC    0x04058  /* Flow Control Rx Unsupported Count- R/clr */
-#define E1000_PRC64    0x0405C  /* Packets Rx (64 bytes) - R/clr */
-#define E1000_PRC127   0x04060  /* Packets Rx (65-127 bytes) - R/clr */
-#define E1000_PRC255   0x04064  /* Packets Rx (128-255 bytes) - R/clr */
-#define E1000_PRC511   0x04068  /* Packets Rx (255-511 bytes) - R/clr */
-#define E1000_PRC1023  0x0406C  /* Packets Rx (512-1023 bytes) - R/clr */
-#define E1000_PRC1522  0x04070  /* Packets Rx (1024-1522 bytes) - R/clr */
-#define E1000_GPRC     0x04074  /* Good Packets Rx Count - R/clr */
-#define E1000_BPRC     0x04078  /* Broadcast Packets Rx Count - R/clr */
-#define E1000_MPRC     0x0407C  /* Multicast Packets Rx Count - R/clr */
-#define E1000_GPTC     0x04080  /* Good Packets Tx Count - R/clr */
-#define E1000_GORCL    0x04088  /* Good Octets Rx Count Low - R/clr */
-#define E1000_GORCH    0x0408C  /* Good Octets Rx Count High - R/clr */
-#define E1000_GOTCL    0x04090  /* Good Octets Tx Count Low - R/clr */
-#define E1000_GOTCH    0x04094  /* Good Octets Tx Count High - R/clr */
-#define E1000_RNBC     0x040A0  /* Rx No Buffers Count - R/clr */
-#define E1000_RUC      0x040A4  /* Rx Undersize Count - R/clr */
-#define E1000_RFC      0x040A8  /* Rx Fragment Count - R/clr */
-#define E1000_ROC      0x040AC  /* Rx Oversize Count - R/clr */
-#define E1000_RJC      0x040B0  /* Rx Jabber Count - R/clr */
-#define E1000_MGTPRC   0x040B4  /* Management Packets Rx Count - R/clr */
-#define E1000_MGTPDC   0x040B8  /* Management Packets Dropped Count - R/clr */
-#define E1000_MGTPTC   0x040BC  /* Management Packets Tx Count - R/clr */
-#define E1000_TORL     0x040C0  /* Total Octets Rx Low - R/clr */
-#define E1000_TORH     0x040C4  /* Total Octets Rx High - R/clr */
-#define E1000_TOTL     0x040C8  /* Total Octets Tx Low - R/clr */
-#define E1000_TOTH     0x040CC  /* Total Octets Tx High - R/clr */
-#define E1000_TPR      0x040D0  /* Total Packets Rx - R/clr */
-#define E1000_TPT      0x040D4  /* Total Packets Tx - R/clr */
-#define E1000_PTC64    0x040D8  /* Packets Tx (64 bytes) - R/clr */
-#define E1000_PTC127   0x040DC  /* Packets Tx (65-127 bytes) - R/clr */
-#define E1000_PTC255   0x040E0  /* Packets Tx (128-255 bytes) - R/clr */
-#define E1000_PTC511   0x040E4  /* Packets Tx (256-511 bytes) - R/clr */
-#define E1000_PTC1023  0x040E8  /* Packets Tx (512-1023 bytes) - R/clr */
-#define E1000_PTC1522  0x040EC  /* Packets Tx (1024-1522 Bytes) - R/clr */
-#define E1000_MPTC     0x040F0  /* Multicast Packets Tx Count - R/clr */
-#define E1000_BPTC     0x040F4  /* Broadcast Packets Tx Count - R/clr */
-#define E1000_TSCTC    0x040F8  /* TCP Segmentation Context Tx - R/clr */
-#define E1000_TSCTFC   0x040FC  /* TCP Segmentation Context Tx Fail - R/clr */
-#define E1000_IAC      0x04100  /* Interrupt Assertion Count */
-#define E1000_ICRXPTC  0x04104  /* Interrupt Cause Rx Pkt Timer Expire Count */
-#define E1000_ICRXATC  0x04108  /* Interrupt Cause Rx Abs Timer Expire Count */
-#define E1000_ICTXPTC  0x0410C  /* Interrupt Cause Tx Pkt Timer Expire Count */
-#define E1000_ICTXATC  0x04110  /* Interrupt Cause Tx Abs Timer Expire Count */
-#define E1000_ICTXQEC  0x04118  /* Interrupt Cause Tx Queue Empty Count */
-#define E1000_ICTXQMTC 0x0411C  /* Interrupt Cause Tx Queue Min Thresh Count */
-#define E1000_ICRXDMTC 0x04120  /* Interrupt Cause Rx Desc Min Thresh Count */
-#define E1000_ICRXOC   0x04124  /* Interrupt Cause Receiver Overrun Count */
-#define E1000_CRC_OFFSET 0x05F50  /* CRC Offset register */
+#define E1000_TDT(_n)	((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \
+			 (0x0E018 + ((_n) * 0x40)))
+#define E1000_TXDCTL(_n)	((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \
+				 (0x0E028 + ((_n) * 0x40)))
+#define E1000_TDWBAL(_n)	((_n) < 4 ? (0x03838 + ((_n) * 0x100)) : \
+				 (0x0E038 + ((_n) * 0x40)))
+#define E1000_TDWBAH(_n)	((_n) < 4 ? (0x0383C + ((_n) * 0x100)) : \
+				 (0x0E03C + ((_n) * 0x40)))
+#define E1000_TARC(_n)		(0x03840 + ((_n) * 0x100))
+#define E1000_RSRPD		0x02C00  /* Rx Small Packet Detect - RW */
+#define E1000_RAID		0x02C08  /* Receive Ack Interrupt Delay - RW */
+#define E1000_TXDMAC		0x03000  /* Tx DMA Control - RW */
+#define E1000_KABGTXD		0x03004  /* AFE Band Gap Transmit Ref Data */
+#define E1000_PSRTYPE(_i)	(0x05480 + ((_i) * 4))
+#define E1000_RAL(_i)		(((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
+				 (0x054E0 + ((_i - 16) * 8)))
+#define E1000_RAH(_i)		(((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
+				 (0x054E4 + ((_i - 16) * 8)))
+#define E1000_SHRAL(_i)		(0x05438 + ((_i) * 8))
+#define E1000_SHRAH(_i)		(0x0543C + ((_i) * 8))
+#define E1000_IP4AT_REG(_i)	(0x05840 + ((_i) * 8))
+#define E1000_IP6AT_REG(_i)	(0x05880 + ((_i) * 4))
+#define E1000_WUPM_REG(_i)	(0x05A00 + ((_i) * 4))
+#define E1000_FFMT_REG(_i)	(0x09000 + ((_i) * 8))
+#define E1000_FFVT_REG(_i)	(0x09800 + ((_i) * 8))
+#define E1000_FFLT_REG(_i)	(0x05F00 + ((_i) * 8))
+#define E1000_PBSLAC		0x03100  /* Pkt Buffer Slave Access Control */
+#define E1000_PBSLAD(_n)	(0x03110 + (0x4 * (_n)))  /* Pkt Buffer DWORD */
+#define E1000_TXPBS		0x03404  /* Tx Packet Buffer Size - RW */
+/* Same as TXPBS, renamed for newer Si - RW */
+#define E1000_ITPBS		0x03404
+#define E1000_TDFH		0x03410  /* Tx Data FIFO Head - RW */
+#define E1000_TDFT		0x03418  /* Tx Data FIFO Tail - RW */
+#define E1000_TDFHS		0x03420  /* Tx Data FIFO Head Saved - RW */
+#define E1000_TDFTS		0x03428  /* Tx Data FIFO Tail Saved - RW */
+#define E1000_TDFPC		0x03430  /* Tx Data FIFO Packet Count - RW */
+#define E1000_TDPUMB		0x0357C  /* DMA Tx Desc uC Mail Box - RW */
+#define E1000_TDPUAD		0x03580  /* DMA Tx Desc uC Addr Command - RW */
+#define E1000_TDPUWD		0x03584  /* DMA Tx Desc uC Data Write - RW */
+#define E1000_TDPURD		0x03588  /* DMA Tx Desc uC Data  Read  - RW */
+#define E1000_TDPUCTL		0x0358C  /* DMA Tx Desc uC Control - RW */
+#define E1000_DTXCTL		0x03590  /* DMA Tx Control - RW */
+#define E1000_DTXTCPFLGL	0x0359C /* DMA Tx Control flag low - RW */
+#define E1000_DTXTCPFLGH	0x035A0 /* DMA Tx Control flag high - RW */
+/* DMA Tx Max Total Allow Size Reqs - RW */
+#define E1000_DTXMXSZRQ		0x03540
+#define E1000_TIDV	0x03820  /* Tx Interrupt Delay Value - RW */
+#define E1000_TADV	0x0382C  /* Tx Interrupt Absolute Delay Val - RW */
+#define E1000_TSPMT	0x03830  /* TCP Segmentation PAD & Min Threshold - RW */
+#define E1000_CRCERRS	0x04000  /* CRC Error Count - R/clr */
+#define E1000_ALGNERRC	0x04004  /* Alignment Error Count - R/clr */
+#define E1000_SYMERRS	0x04008  /* Symbol Error Count - R/clr */
+#define E1000_RXERRC	0x0400C  /* Receive Error Count - R/clr */
+#define E1000_MPC	0x04010  /* Missed Packet Count - R/clr */
+#define E1000_SCC	0x04014  /* Single Collision Count - R/clr */
+#define E1000_ECOL	0x04018  /* Excessive Collision Count - R/clr */
+#define E1000_MCC	0x0401C  /* Multiple Collision Count - R/clr */
+#define E1000_LATECOL	0x04020  /* Late Collision Count - R/clr */
+#define E1000_COLC	0x04028  /* Collision Count - R/clr */
+#define E1000_DC	0x04030  /* Defer Count - R/clr */
+#define E1000_TNCRS	0x04034  /* Tx-No CRS - R/clr */
+#define E1000_SEC	0x04038  /* Sequence Error Count - R/clr */
+#define E1000_CEXTERR	0x0403C  /* Carrier Extension Error Count - R/clr */
+#define E1000_RLEC	0x04040  /* Receive Length Error Count - R/clr */
+#define E1000_XONRXC	0x04048  /* XON Rx Count - R/clr */
+#define E1000_XONTXC	0x0404C  /* XON Tx Count - R/clr */
+#define E1000_XOFFRXC	0x04050  /* XOFF Rx Count - R/clr */
+#define E1000_XOFFTXC	0x04054  /* XOFF Tx Count - R/clr */
+#define E1000_FCRUC	0x04058  /* Flow Control Rx Unsupported Count- R/clr */
+#define E1000_PRC64	0x0405C  /* Packets Rx (64 bytes) - R/clr */
+#define E1000_PRC127	0x04060  /* Packets Rx (65-127 bytes) - R/clr */
+#define E1000_PRC255	0x04064  /* Packets Rx (128-255 bytes) - R/clr */
+#define E1000_PRC511	0x04068  /* Packets Rx (255-511 bytes) - R/clr */
+#define E1000_PRC1023	0x0406C  /* Packets Rx (512-1023 bytes) - R/clr */
+#define E1000_PRC1522	0x04070  /* Packets Rx (1024-1522 bytes) - R/clr */
+#define E1000_GPRC	0x04074  /* Good Packets Rx Count - R/clr */
+#define E1000_BPRC	0x04078  /* Broadcast Packets Rx Count - R/clr */
+#define E1000_MPRC	0x0407C  /* Multicast Packets Rx Count - R/clr */
+#define E1000_GPTC	0x04080  /* Good Packets Tx Count - R/clr */
+#define E1000_GORCL	0x04088  /* Good Octets Rx Count Low - R/clr */
+#define E1000_GORCH	0x0408C  /* Good Octets Rx Count High - R/clr */
+#define E1000_GOTCL	0x04090  /* Good Octets Tx Count Low - R/clr */
+#define E1000_GOTCH	0x04094  /* Good Octets Tx Count High - R/clr */
+#define E1000_RNBC	0x040A0  /* Rx No Buffers Count - R/clr */
+#define E1000_RUC	0x040A4  /* Rx Undersize Count - R/clr */
+#define E1000_RFC	0x040A8  /* Rx Fragment Count - R/clr */
+#define E1000_ROC	0x040AC  /* Rx Oversize Count - R/clr */
+#define E1000_RJC	0x040B0  /* Rx Jabber Count - R/clr */
+#define E1000_MGTPRC	0x040B4  /* Management Packets Rx Count - R/clr */
+#define E1000_MGTPDC	0x040B8  /* Management Packets Dropped Count - R/clr */
+#define E1000_MGTPTC	0x040BC  /* Management Packets Tx Count - R/clr */
+#define E1000_TORL	0x040C0  /* Total Octets Rx Low - R/clr */
+#define E1000_TORH	0x040C4  /* Total Octets Rx High - R/clr */
+#define E1000_TOTL	0x040C8  /* Total Octets Tx Low - R/clr */
+#define E1000_TOTH	0x040CC  /* Total Octets Tx High - R/clr */
+#define E1000_TPR	0x040D0  /* Total Packets Rx - R/clr */
+#define E1000_TPT	0x040D4  /* Total Packets Tx - R/clr */
+#define E1000_PTC64	0x040D8  /* Packets Tx (64 bytes) - R/clr */
+#define E1000_PTC127	0x040DC  /* Packets Tx (65-127 bytes) - R/clr */
+#define E1000_PTC255	0x040E0  /* Packets Tx (128-255 bytes) - R/clr */
+#define E1000_PTC511	0x040E4  /* Packets Tx (256-511 bytes) - R/clr */
+#define E1000_PTC1023	0x040E8  /* Packets Tx (512-1023 bytes) - R/clr */
+#define E1000_PTC1522	0x040EC  /* Packets Tx (1024-1522 Bytes) - R/clr */
+#define E1000_MPTC	0x040F0  /* Multicast Packets Tx Count - R/clr */
+#define E1000_BPTC	0x040F4  /* Broadcast Packets Tx Count - R/clr */
+#define E1000_TSCTC	0x040F8  /* TCP Segmentation Context Tx - R/clr */
+#define E1000_TSCTFC	0x040FC  /* TCP Segmentation Context Tx Fail - R/clr */
+#define E1000_IAC	0x04100  /* Interrupt Assertion Count */
+#define E1000_ICRXPTC	0x04104  /* Interrupt Cause Rx Pkt Timer Expire Count */
+#define E1000_ICRXATC	0x04108  /* Interrupt Cause Rx Abs Timer Expire Count */
+#define E1000_ICTXPTC	0x0410C  /* Interrupt Cause Tx Pkt Timer Expire Count */
+#define E1000_ICTXATC	0x04110  /* Interrupt Cause Tx Abs Timer Expire Count */
+#define E1000_ICTXQEC	0x04118  /* Interrupt Cause Tx Queue Empty Count */
+#define E1000_ICTXQMTC	0x0411C  /* Interrupt Cause Tx Queue Min Thresh Count */
+#define E1000_ICRXDMTC	0x04120  /* Interrupt Cause Rx Desc Min Thresh Count */
+#define E1000_ICRXOC	0x04124  /* Interrupt Cause Receiver Overrun Count */
+#define E1000_CRC_OFFSET	0x05F50  /* CRC Offset register */
 
-#define E1000_VFGPRC   0x00F10
-#define E1000_VFGORC   0x00F18
-#define E1000_VFMPRC   0x00F3C
-#define E1000_VFGPTC   0x00F14
-#define E1000_VFGOTC   0x00F34
-#define E1000_VFGOTLBC 0x00F50
-#define E1000_VFGPTLBC 0x00F44
-#define E1000_VFGORLBC 0x00F48
-#define E1000_VFGPRLBC 0x00F40
+#define E1000_VFGPRC	0x00F10
+#define E1000_VFGORC	0x00F18
+#define E1000_VFMPRC	0x00F3C
+#define E1000_VFGPTC	0x00F14
+#define E1000_VFGOTC	0x00F34
+#define E1000_VFGOTLBC	0x00F50
+#define E1000_VFGPTLBC	0x00F44
+#define E1000_VFGORLBC	0x00F48
+#define E1000_VFGPRLBC	0x00F40
 /* Virtualization statistical counters */
-#define E1000_PFVFGPRC(_n)   (0x010010 + (0x100 * (_n)))
-#define E1000_PFVFGPTC(_n)   (0x010014 + (0x100 * (_n)))
-#define E1000_PFVFGORC(_n)   (0x010018 + (0x100 * (_n)))
-#define E1000_PFVFGOTC(_n)   (0x010034 + (0x100 * (_n)))
-#define E1000_PFVFMPRC(_n)   (0x010038 + (0x100 * (_n)))
-#define E1000_PFVFGPRLBC(_n) (0x010040 + (0x100 * (_n)))
-#define E1000_PFVFGPTLBC(_n) (0x010044 + (0x100 * (_n)))
-#define E1000_PFVFGORLBC(_n) (0x010048 + (0x100 * (_n)))
-#define E1000_PFVFGOTLBC(_n) (0x010050 + (0x100 * (_n)))
+#define E1000_PFVFGPRC(_n)	(0x010010 + (0x100 * (_n)))
+#define E1000_PFVFGPTC(_n)	(0x010014 + (0x100 * (_n)))
+#define E1000_PFVFGORC(_n)	(0x010018 + (0x100 * (_n)))
+#define E1000_PFVFGOTC(_n)	(0x010034 + (0x100 * (_n)))
+#define E1000_PFVFMPRC(_n)	(0x010038 + (0x100 * (_n)))
+#define E1000_PFVFGPRLBC(_n)	(0x010040 + (0x100 * (_n)))
+#define E1000_PFVFGPTLBC(_n)	(0x010044 + (0x100 * (_n)))
+#define E1000_PFVFGORLBC(_n)	(0x010048 + (0x100 * (_n)))
+#define E1000_PFVFGOTLBC(_n)	(0x010050 + (0x100 * (_n)))
 
-#define E1000_LSECTXUT        0x04300  /* LinkSec Tx Untagged Packet Count - OutPktsUntagged */
-#define E1000_LSECTXPKTE      0x04304  /* LinkSec Encrypted Tx Packets Count - OutPktsEncrypted */
-#define E1000_LSECTXPKTP      0x04308  /* LinkSec Protected Tx Packet Count - OutPktsProtected */
-#define E1000_LSECTXOCTE      0x0430C  /* LinkSec Encrypted Tx Octets Count - OutOctetsEncrypted */
-#define E1000_LSECTXOCTP      0x04310  /* LinkSec Protected Tx Octets Count - OutOctetsProtected */
-#define E1000_LSECRXUT        0x04314  /* LinkSec Untagged non-Strict Rx Packet Count - InPktsUntagged/InPktsNoTag */
-#define E1000_LSECRXOCTD      0x0431C  /* LinkSec Rx Octets Decrypted Count - InOctetsDecrypted */
-#define E1000_LSECRXOCTV      0x04320  /* LinkSec Rx Octets Validated - InOctetsValidated */
-#define E1000_LSECRXBAD       0x04324  /* LinkSec Rx Bad Tag - InPktsBadTag */
-#define E1000_LSECRXNOSCI     0x04328  /* LinkSec Rx Packet No SCI Count - InPktsNoSci */
-#define E1000_LSECRXUNSCI     0x0432C  /* LinkSec Rx Packet Unknown SCI Count - InPktsUnknownSci */
-#define E1000_LSECRXUNCH      0x04330  /* LinkSec Rx Unchecked Packets Count - InPktsUnchecked */
-#define E1000_LSECRXDELAY     0x04340  /* LinkSec Rx Delayed Packet Count - InPktsDelayed */
-#define E1000_LSECRXLATE      0x04350  /* LinkSec Rx Late Packets Count - InPktsLate */
-#define E1000_LSECRXOK(_n)    (0x04360 + (0x04 * (_n))) /* LinkSec Rx Packet OK Count - InPktsOk */
-#define E1000_LSECRXINV(_n)   (0x04380 + (0x04 * (_n))) /* LinkSec Rx Invalid Count - InPktsInvalid */
-#define E1000_LSECRXNV(_n)    (0x043A0 + (0x04 * (_n))) /* LinkSec Rx Not Valid Count - InPktsNotValid */
-#define E1000_LSECRXUNSA      0x043C0  /* LinkSec Rx Unused SA Count - InPktsUnusedSa */
-#define E1000_LSECRXNUSA      0x043D0  /* LinkSec Rx Not Using SA Count - InPktsNotUsingSa */
-#define E1000_LSECTXCAP       0x0B000  /* LinkSec Tx Capabilities Register - RO */
-#define E1000_LSECRXCAP       0x0B300  /* LinkSec Rx Capabilities Register - RO */
-#define E1000_LSECTXCTRL      0x0B004  /* LinkSec Tx Control - RW */
-#define E1000_LSECRXCTRL      0x0B304  /* LinkSec Rx Control - RW */
-#define E1000_LSECTXSCL       0x0B008  /* LinkSec Tx SCI Low - RW */
-#define E1000_LSECTXSCH       0x0B00C  /* LinkSec Tx SCI High - RW */
-#define E1000_LSECTXSA        0x0B010  /* LinkSec Tx SA0 - RW */
-#define E1000_LSECTXPN0       0x0B018  /* LinkSec Tx SA PN 0 - RW */
-#define E1000_LSECTXPN1       0x0B01C  /* LinkSec Tx SA PN 1 - RW */
-#define E1000_LSECRXSCL       0x0B3D0  /* LinkSec Rx SCI Low - RW */
-#define E1000_LSECRXSCH       0x0B3E0  /* LinkSec Rx SCI High - RW */
-#define E1000_LSECTXKEY0(_n)  (0x0B020 + (0x04 * (_n))) /* LinkSec Tx 128-bit Key 0 - WO */
-#define E1000_LSECTXKEY1(_n)  (0x0B030 + (0x04 * (_n))) /* LinkSec Tx 128-bit Key 1 - WO */
-#define E1000_LSECRXSA(_n)    (0x0B310 + (0x04 * (_n))) /* LinkSec Rx SAs - RW */
-#define E1000_LSECRXPN(_n)    (0x0B330 + (0x04 * (_n))) /* LinkSec Rx SAs - RW */
+/* LinkSec */
+#define E1000_LSECTXUT		0x04300  /* Tx Untagged Pkt Cnt */
+#define E1000_LSECTXPKTE	0x04304  /* Encrypted Tx Pkts Cnt */
+#define E1000_LSECTXPKTP	0x04308  /* Protected Tx Pkt Cnt */
+#define E1000_LSECTXOCTE	0x0430C  /* Encrypted Tx Octets Cnt */
+#define E1000_LSECTXOCTP	0x04310  /* Protected Tx Octets Cnt */
+#define E1000_LSECRXUT		0x04314  /* Untagged non-Strict Rx Pkt Cnt */
+#define E1000_LSECRXOCTD	0x0431C  /* Rx Octets Decrypted Count */
+#define E1000_LSECRXOCTV	0x04320  /* Rx Octets Validated */
+#define E1000_LSECRXBAD		0x04324  /* Rx Bad Tag */
+#define E1000_LSECRXNOSCI	0x04328  /* Rx Packet No SCI Count */
+#define E1000_LSECRXUNSCI	0x0432C  /* Rx Packet Unknown SCI Count */
+#define E1000_LSECRXUNCH	0x04330  /* Rx Unchecked Packets Count */
+#define E1000_LSECRXDELAY	0x04340  /* Rx Delayed Packet Count */
+#define E1000_LSECRXLATE	0x04350  /* Rx Late Packets Count */
+#define E1000_LSECRXOK(_n)	(0x04360 + (0x04 * (_n))) /* Rx Pkt OK Cnt */
+#define E1000_LSECRXINV(_n)	(0x04380 + (0x04 * (_n))) /* Rx Invalid Cnt */
+#define E1000_LSECRXNV(_n)	(0x043A0 + (0x04 * (_n))) /* Rx Not Valid Cnt */
+#define E1000_LSECRXUNSA	0x043C0  /* Rx Unused SA Count */
+#define E1000_LSECRXNUSA	0x043D0  /* Rx Not Using SA Count */
+#define E1000_LSECTXCAP		0x0B000  /* Tx Capabilities Register - RO */
+#define E1000_LSECRXCAP		0x0B300  /* Rx Capabilities Register - RO */
+#define E1000_LSECTXCTRL	0x0B004  /* Tx Control - RW */
+#define E1000_LSECRXCTRL	0x0B304  /* Rx Control - RW */
+#define E1000_LSECTXSCL		0x0B008  /* Tx SCI Low - RW */
+#define E1000_LSECTXSCH		0x0B00C  /* Tx SCI High - RW */
+#define E1000_LSECTXSA		0x0B010  /* Tx SA0 - RW */
+#define E1000_LSECTXPN0		0x0B018  /* Tx SA PN 0 - RW */
+#define E1000_LSECTXPN1		0x0B01C  /* Tx SA PN 1 - RW */
+#define E1000_LSECRXSCL		0x0B3D0  /* Rx SCI Low - RW */
+#define E1000_LSECRXSCH		0x0B3E0  /* Rx SCI High - RW */
+/* LinkSec Tx 128-bit Key 0 - WO */
+#define E1000_LSECTXKEY0(_n)	(0x0B020 + (0x04 * (_n)))
+/* LinkSec Tx 128-bit Key 1 - WO */
+#define E1000_LSECTXKEY1(_n)	(0x0B030 + (0x04 * (_n)))
+#define E1000_LSECRXSA(_n)	(0x0B310 + (0x04 * (_n))) /* Rx SAs - RW */
+#define E1000_LSECRXPN(_n)	(0x0B330 + (0x04 * (_n))) /* Rx SAs - RW */
 /*
  * LinkSec Rx Keys  - where _n is the SA no. and _m the 4 dwords of the 128 bit
  * key - RW.
  */
-#define E1000_LSECRXKEY(_n, _m) (0x0B350 + (0x10 * (_n)) + (0x04 * (_m)))
+#define E1000_LSECRXKEY(_n, _m)	(0x0B350 + (0x10 * (_n)) + (0x04 * (_m)))
 
-#define E1000_SSVPC             0x041A0  /* Switch Security Violation Packet Count */
-#define E1000_IPSCTRL           0xB430   /* IpSec Control Register */
-#define E1000_IPSRXCMD          0x0B408  /* IPSec Rx Command Register - RW */
-#define E1000_IPSRXIDX          0x0B400  /* IPSec Rx Index - RW */
-#define E1000_IPSRXIPADDR(_n)   (0x0B420+ (0x04 * (_n)))  /* IPSec Rx IPv4/v6 Address - RW */
-#define E1000_IPSRXKEY(_n)      (0x0B410 + (0x04 * (_n))) /* IPSec Rx 128-bit Key - RW */
-#define E1000_IPSRXSALT         0x0B404  /* IPSec Rx Salt - RW */
-#define E1000_IPSRXSPI          0x0B40C  /* IPSec Rx SPI - RW */
-#define E1000_IPSTXKEY(_n)      (0x0B460 + (0x04 * (_n))) /* IPSec Tx 128-bit Key - RW */
-#define E1000_IPSTXSALT         0x0B454  /* IPSec Tx Salt - RW */
-#define E1000_IPSTXIDX          0x0B450  /* IPSec Tx SA IDX - RW */
-#define E1000_PCS_CFG0    0x04200  /* PCS Configuration 0 - RW */
-#define E1000_PCS_LCTL    0x04208  /* PCS Link Control - RW */
-#define E1000_PCS_LSTAT   0x0420C  /* PCS Link Status - RO */
-#define E1000_CBTMPC      0x0402C  /* Circuit Breaker Tx Packet Count */
-#define E1000_HTDPMC      0x0403C  /* Host Transmit Discarded Packets */
-#define E1000_CBRDPC      0x04044  /* Circuit Breaker Rx Dropped Count */
-#define E1000_CBRMPC      0x040FC  /* Circuit Breaker Rx Packet Count */
-#define E1000_RPTHC       0x04104  /* Rx Packets To Host */
-#define E1000_HGPTC       0x04118  /* Host Good Packets Tx Count */
-#define E1000_HTCBDPC     0x04124  /* Host Tx Circuit Breaker Dropped Count */
-#define E1000_HGORCL      0x04128  /* Host Good Octets Received Count Low */
-#define E1000_HGORCH      0x0412C  /* Host Good Octets Received Count High */
-#define E1000_HGOTCL      0x04130  /* Host Good Octets Transmit Count Low */
-#define E1000_HGOTCH      0x04134  /* Host Good Octets Transmit Count High */
-#define E1000_LENERRS     0x04138  /* Length Errors Count */
-#define E1000_SCVPC       0x04228  /* SerDes/SGMII Code Violation Pkt Count */
-#define E1000_HRMPC       0x0A018  /* Header Redirection Missed Packet Count */
-#define E1000_PCS_ANADV   0x04218  /* AN advertisement - RW */
-#define E1000_PCS_LPAB    0x0421C  /* Link Partner Ability - RW */
-#define E1000_PCS_NPTX    0x04220  /* AN Next Page Transmit - RW */
-#define E1000_PCS_LPABNP  0x04224  /* Link Partner Ability Next Page - RW */
-#define E1000_1GSTAT_RCV  0x04228  /* 1GSTAT Code Violation Packet Count - RW */
-#define E1000_RXCSUM   0x05000  /* Rx Checksum Control - RW */
-#define E1000_RLPML    0x05004  /* Rx Long Packet Max Length */
-#define E1000_RFCTL    0x05008  /* Receive Filter Control*/
-#define E1000_MTA      0x05200  /* Multicast Table Array - RW Array */
-#define E1000_RA       0x05400  /* Receive Address - RW Array */
-#define E1000_RA2      0x054E0  /* 2nd half of receive address array - RW Array */
-#define E1000_VFTA     0x05600  /* VLAN Filter Table Array - RW Array */
-#define E1000_VT_CTL   0x0581C  /* VMDq Control - RW */
-#define E1000_VFQA0    0x0B000  /* VLAN Filter Queue Array 0 - RW Array */
-#define E1000_VFQA1    0x0B200  /* VLAN Filter Queue Array 1 - RW Array */
-#define E1000_WUC      0x05800  /* Wakeup Control - RW */
-#define E1000_WUFC     0x05808  /* Wakeup Filter Control - RW */
-#define E1000_WUS      0x05810  /* Wakeup Status - RO */
-#define E1000_MANC     0x05820  /* Management Control - RW */
-#define E1000_IPAV     0x05838  /* IP Address Valid - RW */
-#define E1000_IP4AT    0x05840  /* IPv4 Address Table - RW Array */
-#define E1000_IP6AT    0x05880  /* IPv6 Address Table - RW Array */
-#define E1000_WUPL     0x05900  /* Wakeup Packet Length - RW */
-#define E1000_WUPM     0x05A00  /* Wakeup Packet Memory - RO A */
-#define E1000_PBACL    0x05B68  /* MSIx PBA Clear - Read/Write 1's to clear */
-#define E1000_FFLT     0x05F00  /* Flexible Filter Length Table - RW Array */
-#define E1000_HOST_IF  0x08800  /* Host Interface */
-#define E1000_FFMT     0x09000  /* Flexible Filter Mask Table - RW Array */
-#define E1000_FFVT     0x09800  /* Flexible Filter Value Table - RW Array */
-#define E1000_FHFT(_n)  (0x09000 + (_n * 0x100)) /* Flexible Host Filter Table */
-#define E1000_FHFT_EXT(_n) (0x09A00 + (_n * 0x100)) /* Ext Flexible Host Filter Table */
+#define E1000_SSVPC		0x041A0 /* Switch Security Violation Pkt Cnt */
+#define E1000_IPSCTRL		0xB430  /* IpSec Control Register */
+#define E1000_IPSRXCMD		0x0B408 /* IPSec Rx Command Register - RW */
+#define E1000_IPSRXIDX		0x0B400 /* IPSec Rx Index - RW */
+/* IPSec Rx IPv4/v6 Address - RW */
+#define E1000_IPSRXIPADDR(_n)	(0x0B420 + (0x04 * (_n)))
+/* IPSec Rx 128-bit Key - RW */
+#define E1000_IPSRXKEY(_n)	(0x0B410 + (0x04 * (_n)))
+#define E1000_IPSRXSALT		0x0B404  /* IPSec Rx Salt - RW */
+#define E1000_IPSRXSPI		0x0B40C  /* IPSec Rx SPI - RW */
+/* IPSec Tx 128-bit Key - RW */
+#define E1000_IPSTXKEY(_n)	(0x0B460 + (0x04 * (_n)))
+#define E1000_IPSTXSALT		0x0B454  /* IPSec Tx Salt - RW */
+#define E1000_IPSTXIDX		0x0B450  /* IPSec Tx SA IDX - RW */
+#define E1000_PCS_CFG0	0x04200  /* PCS Configuration 0 - RW */
+#define E1000_PCS_LCTL	0x04208  /* PCS Link Control - RW */
+#define E1000_PCS_LSTAT	0x0420C  /* PCS Link Status - RO */
+#define E1000_CBTMPC	0x0402C  /* Circuit Breaker Tx Packet Count */
+#define E1000_HTDPMC	0x0403C  /* Host Transmit Discarded Packets */
+#define E1000_CBRDPC	0x04044  /* Circuit Breaker Rx Dropped Count */
+#define E1000_CBRMPC	0x040FC  /* Circuit Breaker Rx Packet Count */
+#define E1000_RPTHC	0x04104  /* Rx Packets To Host */
+#define E1000_HGPTC	0x04118  /* Host Good Packets Tx Count */
+#define E1000_HTCBDPC	0x04124  /* Host Tx Circuit Breaker Dropped Count */
+#define E1000_HGORCL	0x04128  /* Host Good Octets Received Count Low */
+#define E1000_HGORCH	0x0412C  /* Host Good Octets Received Count High */
+#define E1000_HGOTCL	0x04130  /* Host Good Octets Transmit Count Low */
+#define E1000_HGOTCH	0x04134  /* Host Good Octets Transmit Count High */
+#define E1000_LENERRS	0x04138  /* Length Errors Count */
+#define E1000_SCVPC	0x04228  /* SerDes/SGMII Code Violation Pkt Count */
+#define E1000_HRMPC	0x0A018  /* Header Redirection Missed Packet Count */
+#define E1000_PCS_ANADV	0x04218  /* AN advertisement - RW */
+#define E1000_PCS_LPAB	0x0421C  /* Link Partner Ability - RW */
+#define E1000_PCS_NPTX	0x04220  /* AN Next Page Transmit - RW */
+#define E1000_PCS_LPABNP	0x04224 /* Link Partner Ability Next Pg - RW */
+#define E1000_1GSTAT_RCV	0x04228 /* 1GSTAT Code Violation Pkt Cnt - RW */
+#define E1000_RXCSUM	0x05000  /* Rx Checksum Control - RW */
+#define E1000_RLPML	0x05004  /* Rx Long Packet Max Length */
+#define E1000_RFCTL	0x05008  /* Receive Filter Control*/
+#define E1000_MTA	0x05200  /* Multicast Table Array - RW Array */
+#define E1000_RA	0x05400  /* Receive Address - RW Array */
+#define E1000_RA2	0x054E0  /* 2nd half of Rx address array - RW Array */
+#define E1000_VFTA	0x05600  /* VLAN Filter Table Array - RW Array */
+#define E1000_VT_CTL	0x0581C  /* VMDq Control - RW */
+#define E1000_CIAA	0x05B88  /* Config Indirect Access Address - RW */
+#define E1000_CIAD	0x05B8C  /* Config Indirect Access Data - RW */
+#define E1000_VFQA0	0x0B000  /* VLAN Filter Queue Array 0 - RW Array */
+#define E1000_VFQA1	0x0B200  /* VLAN Filter Queue Array 1 - RW Array */
+#define E1000_WUC	0x05800  /* Wakeup Control - RW */
+#define E1000_WUFC	0x05808  /* Wakeup Filter Control - RW */
+#define E1000_WUS	0x05810  /* Wakeup Status - RO */
+#define E1000_MANC	0x05820  /* Management Control - RW */
+#define E1000_IPAV	0x05838  /* IP Address Valid - RW */
+#define E1000_IP4AT	0x05840  /* IPv4 Address Table - RW Array */
+#define E1000_IP6AT	0x05880  /* IPv6 Address Table - RW Array */
+#define E1000_WUPL	0x05900  /* Wakeup Packet Length - RW */
+#define E1000_WUPM	0x05A00  /* Wakeup Packet Memory - RO A */
+#define E1000_PBACL	0x05B68  /* MSIx PBA Clear - Read/Write 1's to clear */
+#define E1000_FFLT	0x05F00  /* Flexible Filter Length Table - RW Array */
+#define E1000_HOST_IF	0x08800  /* Host Interface */
+#define E1000_FFMT	0x09000  /* Flexible Filter Mask Table - RW Array */
+#define E1000_FFVT	0x09800  /* Flexible Filter Value Table - RW Array */
+/* Flexible Host Filter Table */
+#define E1000_FHFT(_n)	(0x09000 + (_n * 0x100))
+/* Ext Flexible Host Filter Table */
+#define E1000_FHFT_EXT(_n)	(0x09A00 + (_n * 0x100))
 
 
-#define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */
-#define E1000_MDPHYA      0x0003C /* PHY address - RW */
-#define E1000_MANC2H      0x05860 /* Management Control To Host - RW */
-#define E1000_MDEF(_n)    (0x05890 + (4 * (_n))) /* Mngmt Decision Filters */
-#define E1000_SW_FW_SYNC  0x05B5C /* Software-Firmware Synchronization - RW */
-#define E1000_CCMCTL      0x05B48 /* CCM Control Register */
-#define E1000_GIOCTL      0x05B44 /* GIO Analog Control Register */
-#define E1000_SCCTL       0x05B4C /* PCIc PLL Configuration Register */
-#define E1000_GCR         0x05B00 /* PCI-Ex Control */
-#define E1000_GCR2        0x05B64 /* PCI-Ex Control #2 */
-#define E1000_GSCL_1    0x05B10 /* PCI-Ex Statistic Control #1 */
-#define E1000_GSCL_2    0x05B14 /* PCI-Ex Statistic Control #2 */
-#define E1000_GSCL_3    0x05B18 /* PCI-Ex Statistic Control #3 */
-#define E1000_GSCL_4    0x05B1C /* PCI-Ex Statistic Control #4 */
-#define E1000_FACTPS    0x05B30 /* Function Active and Power State to MNG */
-#define E1000_SWSM      0x05B50 /* SW Semaphore */
-#define E1000_FWSM      0x05B54 /* FW Semaphore */
-#define E1000_SWSM2     0x05B58 /* Driver-only SW semaphore (not used by BOOT agents) */
-#define E1000_DCA_ID    0x05B70 /* DCA Requester ID Information - RO */
-#define E1000_DCA_CTRL  0x05B74 /* DCA Control - RW */
-#define E1000_UFUSE     0x05B78 /* UFUSE - RO */
-#define E1000_FFLT_DBG  0x05F04 /* Debug Register */
-#define E1000_HICR      0x08F00 /* Host Interface Control */
-#define E1000_FWSTS     0x08F0C /* FW Status */
+#define E1000_KMRNCTRLSTA	0x00034 /* MAC-PHY interface - RW */
+#define E1000_MDPHYA		0x0003C /* PHY address - RW */
+#define E1000_MANC2H		0x05860 /* Management Control To Host - RW */
+/* Management Decision Filters */
+#define E1000_MDEF(_n)		(0x05890 + (4 * (_n)))
+#define E1000_SW_FW_SYNC	0x05B5C /* SW-FW Synchronization - RW */
+#define E1000_CCMCTL	0x05B48 /* CCM Control Register */
+#define E1000_GIOCTL	0x05B44 /* GIO Analog Control Register */
+#define E1000_SCCTL	0x05B4C /* PCIc PLL Configuration Register */
+#define E1000_GCR	0x05B00 /* PCI-Ex Control */
+#define E1000_GCR2	0x05B64 /* PCI-Ex Control #2 */
+#define E1000_GSCL_1	0x05B10 /* PCI-Ex Statistic Control #1 */
+#define E1000_GSCL_2	0x05B14 /* PCI-Ex Statistic Control #2 */
+#define E1000_GSCL_3	0x05B18 /* PCI-Ex Statistic Control #3 */
+#define E1000_GSCL_4	0x05B1C /* PCI-Ex Statistic Control #4 */
+#define E1000_FACTPS	0x05B30 /* Function Active and Power State to MNG */
+#define E1000_SWSM	0x05B50 /* SW Semaphore */
+#define E1000_FWSM	0x05B54 /* FW Semaphore */
+/* Driver-only SW semaphore (not used by BOOT agents) */
+#define E1000_SWSM2	0x05B58
+#define E1000_DCA_ID	0x05B70 /* DCA Requester ID Information - RO */
+#define E1000_DCA_CTRL	0x05B74 /* DCA Control - RW */
+#define E1000_UFUSE	0x05B78 /* UFUSE - RO */
+#define E1000_FFLT_DBG	0x05F04 /* Debug Register */
+#define E1000_HICR	0x08F00 /* Host Interface Control */
+#define E1000_FWSTS	0x08F0C /* FW Status */
 
 /* RSS registers */
-#define E1000_CPUVEC    0x02C10 /* CPU Vector Register - RW */
-#define E1000_MRQC      0x05818 /* Multiple Receive Control - RW */
-#define E1000_IMIR(_i)      (0x05A80 + ((_i) * 4))  /* Immediate Interrupt */
-#define E1000_IMIREXT(_i)   (0x05AA0 + ((_i) * 4))  /* Immediate Interrupt Ext*/
-#define E1000_IMIRVP    0x05AC0 /* Immediate Interrupt Rx VLAN Priority - RW */
-#define E1000_MSIXBM(_i)    (0x01600 + ((_i) * 4)) /* MSI-X Allocation Register
-                                                    * (_i) - RW */
-#define E1000_MSIXTADD(_i)  (0x0C000 + ((_i) * 0x10)) /* MSI-X Table entry addr
-                                                       * low reg - RW */
-#define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10)) /* MSI-X Table entry addr
-                                                       * upper reg - RW */
-#define E1000_MSIXTMSG(_i)  (0x0C008 + ((_i) * 0x10)) /* MSI-X Table entry
-                                                       * message reg - RW */
-#define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10)) /* MSI-X Table entry
-                                                       * vector ctrl reg - RW */
-#define E1000_MSIXPBA    0x0E000 /* MSI-X Pending bit array */
-#define E1000_RETA(_i)  (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */
-#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */
-#define E1000_RSSIM     0x05864 /* RSS Interrupt Mask */
-#define E1000_RSSIR     0x05868 /* RSS Interrupt Request */
+#define E1000_CPUVEC	0x02C10 /* CPU Vector Register - RW */
+#define E1000_MRQC	0x05818 /* Multiple Receive Control - RW */
+#define E1000_IMIR(_i)	(0x05A80 + ((_i) * 4))  /* Immediate Interrupt */
+#define E1000_IMIREXT(_i)	(0x05AA0 + ((_i) * 4)) /* Immediate INTR Ext*/
+#define E1000_IMIRVP		0x05AC0 /* Immediate INT Rx VLAN Priority -RW */
+#define E1000_MSIXBM(_i)	(0x01600 + ((_i) * 4)) /* MSI-X Alloc Reg -RW */
+/* MSI-X Table entry addr low reg - RW */
+#define E1000_MSIXTADD(_i)	(0x0C000 + ((_i) * 0x10))
+/* MSI-X Table entry addr upper reg - RW */
+#define E1000_MSIXTUADD(_i)	(0x0C004 + ((_i) * 0x10))
+/* MSI-X Table entry message reg - RW */
+#define E1000_MSIXTMSG(_i)	(0x0C008 + ((_i) * 0x10))
+/* MSI-X Table entry vector ctrl reg - RW */
+#define E1000_MSIXVCTRL(_i)	(0x0C00C + ((_i) * 0x10))
+#define E1000_MSIXPBA	0x0E000 /* MSI-X Pending bit array */
+#define E1000_RETA(_i)	(0x05C00 + ((_i) * 4)) /* Redirection Table - RW */
+#define E1000_RSSRK(_i)	(0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */
+#define E1000_RSSIM	0x05864 /* RSS Interrupt Mask */
+#define E1000_RSSIR	0x05868 /* RSS Interrupt Request */
 /* VT Registers */
-#define E1000_SWPBS     0x03004 /* Switch Packet Buffer Size - RW */
-#define E1000_MBVFICR   0x00C80 /* Mailbox VF Cause - RWC */
-#define E1000_MBVFIMR   0x00C84 /* Mailbox VF int Mask - RW */
-#define E1000_VFLRE     0x00C88 /* VF Register Events - RWC */
-#define E1000_VFRE      0x00C8C /* VF Receive Enables */
-#define E1000_VFTE      0x00C90 /* VF Transmit Enables */
-#define E1000_QDE       0x02408 /* Queue Drop Enable - RW */
-#define E1000_DTXSWC    0x03500 /* DMA Tx Switch Control - RW */
-#define E1000_WVBR      0x03554 /* VM Wrong Behavior - RWS */
-#define E1000_RPLOLR    0x05AF0 /* Replication Offload - RW */
-#define E1000_UTA       0x0A000 /* Unicast Table Array - RW */
-#define E1000_IOVTCL    0x05BBC /* IOV Control Register */
-#define E1000_VMRCTL    0X05D80 /* Virtual Mirror Rule Control */
-#define E1000_VMRVLAN   0x05D90 /* Virtual Mirror Rule VLAN */
-#define E1000_VMRVM     0x05DA0 /* Virtual Mirror Rule VM */
-#define E1000_MDFB      0x03558 /* Malicious Driver free block */
-#define E1000_LVMMC     0x03548 /* Last VM Misbehavior cause */
-#define E1000_TXSWC     0x05ACC /* Tx Switch Control */
-#define E1000_SCCRL     0x05DB0 /* Storm Control Control */
-#define E1000_BSCTRH    0x05DB8 /* Broadcast Storm Control Threshold */
-#define E1000_MSCTRH    0x05DBC /* Multicast Storm Control Threshold */
+#define E1000_SWPBS	0x03004 /* Switch Packet Buffer Size - RW */
+#define E1000_MBVFICR	0x00C80 /* Mailbox VF Cause - RWC */
+#define E1000_MBVFIMR	0x00C84 /* Mailbox VF int Mask - RW */
+#define E1000_VFLRE	0x00C88 /* VF Register Events - RWC */
+#define E1000_VFRE	0x00C8C /* VF Receive Enables */
+#define E1000_VFTE	0x00C90 /* VF Transmit Enables */
+#define E1000_QDE	0x02408 /* Queue Drop Enable - RW */
+#define E1000_DTXSWC	0x03500 /* DMA Tx Switch Control - RW */
+#define E1000_WVBR	0x03554 /* VM Wrong Behavior - RWS */
+#define E1000_RPLOLR	0x05AF0 /* Replication Offload - RW */
+#define E1000_UTA	0x0A000 /* Unicast Table Array - RW */
+#define E1000_IOVTCL	0x05BBC /* IOV Control Register */
+#define E1000_VMRCTL	0X05D80 /* Virtual Mirror Rule Control */
+#define E1000_VMRVLAN	0x05D90 /* Virtual Mirror Rule VLAN */
+#define E1000_VMRVM	0x05DA0 /* Virtual Mirror Rule VM */
+#define E1000_MDFB	0x03558 /* Malicious Driver free block */
+#define E1000_LVMMC	0x03548 /* Last VM Misbehavior cause */
+#define E1000_TXSWC	0x05ACC /* Tx Switch Control */
+#define E1000_SCCRL	0x05DB0 /* Storm Control Control */
+#define E1000_BSCTRH	0x05DB8 /* Broadcast Storm Control Threshold */
+#define E1000_MSCTRH	0x05DBC /* Multicast Storm Control Threshold */
 /* These act per VF so an array friendly macro is used */
-#define E1000_V2PMAILBOX(_n)   (0x00C40 + (4 * (_n)))
-#define E1000_P2VMAILBOX(_n)   (0x00C00 + (4 * (_n)))
-#define E1000_VMBMEM(_n)       (0x00800 + (64 * (_n)))
-#define E1000_VFVMBMEM(_n)     (0x00800 + (_n))
-#define E1000_VMOLR(_n)        (0x05AD0 + (4 * (_n)))
-#define E1000_VLVF(_n)         (0x05D00 + (4 * (_n))) /* VLAN Virtual Machine
-                                                       * Filter - RW */
-#define E1000_VMVIR(_n)        (0x03700 + (4 * (_n)))
-#define E1000_DVMOLR(_n)       (0x0C038 + (0x40 * (_n))) /* DMA VM offload */
-/* Time Sync */
-#define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */
-#define E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */
-#define E1000_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */
-#define E1000_RXSTMPL    0x0B624 /* Rx timestamp Low - RO */
-#define E1000_RXSTMPH    0x0B628 /* Rx timestamp High - RO */
-#define E1000_RXSATRL    0x0B62C /* Rx timestamp attribute low - RO */
-#define E1000_RXSATRH    0x0B630 /* Rx timestamp attribute high - RO */
-#define E1000_TXSTMPL    0x0B618 /* Tx timestamp value Low - RO */
-#define E1000_TXSTMPH    0x0B61C /* Tx timestamp value High - RO */
-#define E1000_SYSTIML    0x0B600 /* System time register Low - RO */
-#define E1000_SYSTIMH    0x0B604 /* System time register High - RO */
-#define E1000_TIMINCA    0x0B608 /* Increment attributes register - RW */
-#define E1000_TSAUXC     0x0B640 /* Timesync Auxiliary Control register */
-#define E1000_SYSTIMR    0x0B6F8 /* System time register Residue */
-#define E1000_RXMTRL     0x0B634 /* Time sync Rx EtherType and Msg Type - RW */
-#define E1000_RXUDP      0x0B638 /* Time Sync Rx UDP Port - RW */
+#define E1000_V2PMAILBOX(_n)	(0x00C40 + (4 * (_n)))
+#define E1000_P2VMAILBOX(_n)	(0x00C00 + (4 * (_n)))
+#define E1000_VMBMEM(_n)	(0x00800 + (64 * (_n)))
+#define E1000_VFVMBMEM(_n)	(0x00800 + (_n))
+#define E1000_VMOLR(_n)		(0x05AD0 + (4 * (_n)))
+/* VLAN Virtual Machine Filter - RW */
+#define E1000_VLVF(_n)		(0x05D00 + (4 * (_n)))
+#define E1000_VMVIR(_n)		(0x03700 + (4 * (_n)))
+#define E1000_DVMOLR(_n)	(0x0C038 + (0x40 * (_n))) /* DMA VM offload */
+#define E1000_VTCTRL(_n)	(0x10000 + (0x100 * (_n))) /* VT Control */
+#define E1000_TSYNCRXCTL	0x0B620 /* Rx Time Sync Control register - RW */
+#define E1000_TSYNCTXCTL	0x0B614 /* Tx Time Sync Control register - RW */
+#define E1000_TSYNCRXCFG	0x05F50 /* Time Sync Rx Configuration - RW */
+#define E1000_RXSTMPL	0x0B624 /* Rx timestamp Low - RO */
+#define E1000_RXSTMPH	0x0B628 /* Rx timestamp High - RO */
+#define E1000_RXSATRL	0x0B62C /* Rx timestamp attribute low - RO */
+#define E1000_RXSATRH	0x0B630 /* Rx timestamp attribute high - RO */
+#define E1000_TXSTMPL	0x0B618 /* Tx timestamp value Low - RO */
+#define E1000_TXSTMPH	0x0B61C /* Tx timestamp value High - RO */
+#define E1000_SYSTIML	0x0B600 /* System time register Low - RO */
+#define E1000_SYSTIMH	0x0B604 /* System time register High - RO */
+#define E1000_TIMINCA	0x0B608 /* Increment attributes register - RW */
+#define E1000_TSAUXC	0x0B640 /* Timesync Auxiliary Control register */
+#define E1000_SYSTIMR	0x0B6F8 /* System time register Residue */
+#define E1000_RXMTRL	0x0B634 /* Time sync Rx EtherType and Msg Type - RW */
+#define E1000_RXUDP	0x0B638 /* Time Sync Rx UDP Port - RW */
 
 /* Filtering Registers */
-#define E1000_SAQF(_n)  (0x05980 + (4 * (_n))) /* Source Address Queue Fltr */
-#define E1000_DAQF(_n)  (0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */
-#define E1000_SPQF(_n)  (0x059C0 + (4 * (_n))) /* Source Port Queue Fltr */
-#define E1000_FTQF(_n)  (0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */
-#define E1000_TTQF(_n)  (0x059E0 + (4 * (_n))) /* 2-tuple Queue Fltr */
-#define E1000_SYNQF(_n) (0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */
-#define E1000_ETQF(_n)  (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */
+#define E1000_SAQF(_n)	(0x05980 + (4 * (_n))) /* Source Address Queue Fltr */
+#define E1000_DAQF(_n)	(0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */
+#define E1000_SPQF(_n)	(0x059C0 + (4 * (_n))) /* Source Port Queue Fltr */
+#define E1000_FTQF(_n)	(0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */
+#define E1000_TTQF(_n)	(0x059E0 + (4 * (_n))) /* 2-tuple Queue Fltr */
+#define E1000_SYNQF(_n)	(0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */
+#define E1000_ETQF(_n)	(0x05CB0 + (4 * (_n))) /* EType Queue Fltr */
 
-#define E1000_RTTDCS            0x3600  /* Reedtown Tx Desc plane control and status */
-#define E1000_RTTPCS            0x3474  /* Reedtown Tx Packet Plane control and status */
-#define E1000_RTRPCS            0x2474  /* Rx packet plane control and status */
-#define E1000_RTRUP2TC          0x05AC4 /* Rx User Priority to Traffic Class */
-#define E1000_RTTUP2TC          0x0418  /* Transmit User Priority to Traffic Class */
-#define E1000_RTTDTCRC(_n)      (0x3610 + ((_n) * 4)) /* Tx Desc plane TC Rate-scheduler config */
-#define E1000_RTTPTCRC(_n)      (0x3480 + ((_n) * 4)) /* Tx Packet plane TC Rate-Scheduler Config */
-#define E1000_RTRPTCRC(_n)      (0x2480 + ((_n) * 4)) /* Rx Packet plane TC Rate-Scheduler Config */
-#define E1000_RTTDTCRS(_n)      (0x3630 + ((_n) * 4)) /* Tx Desc Plane TC Rate-Scheduler Status */
-#define E1000_RTTDTCRM(_n)      (0x3650 + ((_n) * 4)) /* Tx Desc Plane TC Rate-Scheduler MMW */
-#define E1000_RTTPTCRS(_n)      (0x34A0 + ((_n) * 4)) /* Tx Packet plane TC Rate-Scheduler Status */
-#define E1000_RTTPTCRM(_n)      (0x34C0 + ((_n) * 4)) /* Tx Packet plane TC Rate-scheduler MMW */
-#define E1000_RTRPTCRS(_n)      (0x24A0 + ((_n) * 4)) /* Rx Packet plane TC Rate-Scheduler Status */
-#define E1000_RTRPTCRM(_n)      (0x24C0 + ((_n) * 4)) /* Rx Packet plane TC Rate-Scheduler MMW */
-#define E1000_RTTDVMRM(_n)      (0x3670 + ((_n) * 4)) /* Tx Desc plane VM Rate-Scheduler MMW*/
-#define E1000_RTTBCNRM(_n)      (0x3690 + ((_n) * 4)) /* Tx BCN Rate-Scheduler MMW */
-#define E1000_RTTDQSEL          0x3604  /* Tx Desc Plane Queue Select */
-#define E1000_RTTDVMRC          0x3608  /* Tx Desc Plane VM Rate-Scheduler Config */
-#define E1000_RTTDVMRS          0x360C  /* Tx Desc Plane VM Rate-Scheduler Status */
-#define E1000_RTTBCNRC          0x36B0  /* Tx BCN Rate-Scheduler Config */
-#define E1000_RTTBCNRS          0x36B4  /* Tx BCN Rate-Scheduler Status */
-#define E1000_RTTBCNCR          0xB200  /* Tx BCN Control Register */
-#define E1000_RTTBCNTG          0x35A4  /* Tx BCN Tagging */
-#define E1000_RTTBCNCP          0xB208  /* Tx BCN Congestion point */
-#define E1000_RTRBCNCR          0xB20C  /* Rx BCN Control Register */
-#define E1000_RTTBCNRD          0x36B8  /* Tx BCN Rate Drift */
-#define E1000_PFCTOP            0x1080  /* Priority Flow Control Type and Opcode */
-#define E1000_RTTBCNIDX         0xB204  /* Tx BCN Congestion Point */
-#define E1000_RTTBCNACH         0x0B214 /* Tx BCN Control High */
-#define E1000_RTTBCNACL         0x0B210 /* Tx BCN Control Low */
+#define E1000_RTTDCS	0x3600 /* Reedtown Tx Desc plane control and status */
+#define E1000_RTTPCS	0x3474 /* Reedtown Tx Packet Plane control and status */
+#define E1000_RTRPCS	0x2474 /* Rx packet plane control and status */
+#define E1000_RTRUP2TC	0x05AC4 /* Rx User Priority to Traffic Class */
+#define E1000_RTTUP2TC	0x0418 /* Transmit User Priority to Traffic Class */
+/* Tx Desc plane TC Rate-scheduler config */
+#define E1000_RTTDTCRC(_n)	(0x3610 + ((_n) * 4))
+/* Tx Packet plane TC Rate-Scheduler Config */
+#define E1000_RTTPTCRC(_n)	(0x3480 + ((_n) * 4))
+/* Rx Packet plane TC Rate-Scheduler Config */
+#define E1000_RTRPTCRC(_n)	(0x2480 + ((_n) * 4))
+/* Tx Desc Plane TC Rate-Scheduler Status */
+#define E1000_RTTDTCRS(_n)	(0x3630 + ((_n) * 4))
+/* Tx Desc Plane TC Rate-Scheduler MMW */
+#define E1000_RTTDTCRM(_n)	(0x3650 + ((_n) * 4))
+/* Tx Packet plane TC Rate-Scheduler Status */
+#define E1000_RTTPTCRS(_n)	(0x34A0 + ((_n) * 4))
+/* Tx Packet plane TC Rate-scheduler MMW */
+#define E1000_RTTPTCRM(_n)	(0x34C0 + ((_n) * 4))
+/* Rx Packet plane TC Rate-Scheduler Status */
+#define E1000_RTRPTCRS(_n)	(0x24A0 + ((_n) * 4))
+/* Rx Packet plane TC Rate-Scheduler MMW */
+#define E1000_RTRPTCRM(_n)	(0x24C0 + ((_n) * 4))
+/* Tx Desc plane VM Rate-Scheduler MMW*/
+#define E1000_RTTDVMRM(_n)	(0x3670 + ((_n) * 4))
+/* Tx BCN Rate-Scheduler MMW */
+#define E1000_RTTBCNRM(_n)	(0x3690 + ((_n) * 4))
+#define E1000_RTTDQSEL	0x3604  /* Tx Desc Plane Queue Select */
+#define E1000_RTTDVMRC	0x3608  /* Tx Desc Plane VM Rate-Scheduler Config */
+#define E1000_RTTDVMRS	0x360C  /* Tx Desc Plane VM Rate-Scheduler Status */
+#define E1000_RTTBCNRC	0x36B0  /* Tx BCN Rate-Scheduler Config */
+#define E1000_RTTBCNRS	0x36B4  /* Tx BCN Rate-Scheduler Status */
+#define E1000_RTTBCNCR	0xB200  /* Tx BCN Control Register */
+#define E1000_RTTBCNTG	0x35A4  /* Tx BCN Tagging */
+#define E1000_RTTBCNCP	0xB208  /* Tx BCN Congestion point */
+#define E1000_RTRBCNCR	0xB20C  /* Rx BCN Control Register */
+#define E1000_RTTBCNRD	0x36B8  /* Tx BCN Rate Drift */
+#define E1000_PFCTOP	0x1080  /* Priority Flow Control Type and Opcode */
+#define E1000_RTTBCNIDX	0xB204  /* Tx BCN Congestion Point */
+#define E1000_RTTBCNACH	0x0B214 /* Tx BCN Control High */
+#define E1000_RTTBCNACL	0x0B210 /* Tx BCN Control Low */
 
 /* DMA Coalescing registers */
-#define E1000_DMACR             0x02508 /* Control Register */
-#define E1000_DMCTXTH           0x03550 /* Transmit Threshold */
-#define E1000_DMCTLX            0x02514 /* Time to Lx Request */
-#define E1000_DMCRTRH           0x05DD0 /* Receive Packet Rate Threshold */
-#define E1000_DMCCNT            0x05DD4 /* Current Rx Count */
-#define E1000_FCRTC             0x02170 /* Flow Control Rx high watermark */
-#define E1000_PCIEMISC          0x05BB8 /* PCIE misc config register */
+#define E1000_DMACR	0x02508 /* Control Register */
+#define E1000_DMCTXTH	0x03550 /* Transmit Threshold */
+#define E1000_DMCTLX	0x02514 /* Time to Lx Request */
+#define E1000_DMCRTRH	0x05DD0 /* Receive Packet Rate Threshold */
+#define E1000_DMCCNT	0x05DD4 /* Current Rx Count */
+#define E1000_FCRTC	0x02170 /* Flow Control Rx high watermark */
+#define E1000_PCIEMISC	0x05BB8 /* PCIE misc config register */
 
 /* PCIe Parity Status Register */
-#define E1000_PCIEERRSTS        0x05BA8
+#define E1000_PCIEERRSTS	0x05BA8
 
-#define E1000_PROXYS            0x5F64 /* Proxying Status */
-#define E1000_PROXYFC           0x5F60 /* Proxying Filter Control */
+#define E1000_LTRMINV	0x5BB0 /* LTR Minimum Value */
+#define E1000_LTRMAXV	0x5BB4 /* LTR Maximum Value */
+#define E1000_DOBFFCTL	0x3F24 /* DMA OBFF Control Register */
+
+#define E1000_PROXYS	0x5F64 /* Proxying Status */
+#define E1000_PROXYFC	0x5F60 /* Proxying Filter Control */
 /* Thermal sensor configuration and status registers */
-#define E1000_THMJT             0x08100 /* Junction Temperature */
-#define E1000_THLOWTC           0x08104 /* Low Threshold Control */
-#define E1000_THMIDTC           0x08108 /* Mid Threshold Control */
-#define E1000_THHIGHTC          0x0810C /* High Threshold Control */
-#define E1000_THSTAT            0x08110 /* Thermal Sensor Status */
+#define E1000_THMJT	0x08100 /* Junction Temperature */
+#define E1000_THLOWTC	0x08104 /* Low Threshold Control */
+#define E1000_THMIDTC	0x08108 /* Mid Threshold Control */
+#define E1000_THHIGHTC	0x0810C /* High Threshold Control */
+#define E1000_THSTAT	0x08110 /* Thermal Sensor Status */
 
 /*Energy Efficient Ethernet "EEE" registers */
-#define E1000_IPCNFG            0x0E38 /* Internal PHY Configuration */
-#define E1000_LTRC              0x01A0 /* Latency Tolerance Reporting Control */
-#define E1000_EEER              0x0E30 /* Energy Efficient Ethernet "EEE"*/
-#define E1000_EEE_SU            0x0E34 /* EEE Setup */
-#define E1000_TLPIC             0x4148 /* EEE Tx LPI Count - TLPIC */
-#define E1000_RLPIC             0x414C /* EEE Rx LPI Count - RLPIC */
+#define E1000_IPCNFG	0x0E38 /* Internal PHY Configuration */
+#define E1000_LTRC	0x01A0 /* Latency Tolerance Reporting Control */
+#define E1000_EEER	0x0E30 /* Energy Efficient Ethernet "EEE"*/
+#define E1000_EEE_SU	0x0E34 /* EEE Setup */
+#define E1000_TLPIC	0x4148 /* EEE Tx LPI Count - TLPIC */
+#define E1000_RLPIC	0x414C /* EEE Rx LPI Count - RLPIC */
 
 /* OS2BMC Registers */
-#define E1000_B2OSPC            0x08FE0 /* BMC2OS packets sent by BMC */
-#define E1000_B2OGPRC           0x04158 /* BMC2OS packets received by host */
-#define E1000_O2BGPTC           0x08FE4 /* OS2BMC packets received by BMC */
-#define E1000_O2BSPC            0x0415C /* OS2BMC packets transmitted by host */
+#define E1000_B2OSPC	0x08FE0 /* BMC2OS packets sent by BMC */
+#define E1000_B2OGPRC	0x04158 /* BMC2OS packets received by host */
+#define E1000_O2BGPTC	0x08FE4 /* OS2BMC packets received by BMC */
+#define E1000_O2BSPC	0x0415C /* OS2BMC packets transmitted by host */
 
 #endif
diff --git a/sys/dev/e1000/e1000_vf.c b/sys/dev/e1000/e1000_vf.c
index 3eeda24..d1286ad 100644
--- a/sys/dev/e1000/e1000_vf.c
+++ b/sys/dev/e1000/e1000_vf.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -36,21 +36,21 @@
 #include "e1000_api.h"
 
 
-static s32       e1000_init_phy_params_vf(struct e1000_hw *hw);
-static s32       e1000_init_nvm_params_vf(struct e1000_hw *hw);
-static void      e1000_release_vf(struct e1000_hw *hw);
-static s32       e1000_acquire_vf(struct e1000_hw *hw);
-static s32       e1000_setup_link_vf(struct e1000_hw *hw);
-static s32       e1000_get_bus_info_pcie_vf(struct e1000_hw *hw);
-static s32       e1000_init_mac_params_vf(struct e1000_hw *hw);
-static s32       e1000_check_for_link_vf(struct e1000_hw *hw);
-static s32       e1000_get_link_up_info_vf(struct e1000_hw *hw, u16 *speed,
-                                              u16 *duplex);
-static s32       e1000_init_hw_vf(struct e1000_hw *hw);
-static s32       e1000_reset_hw_vf(struct e1000_hw *hw);
-static void      e1000_update_mc_addr_list_vf(struct e1000_hw *hw, u8 *, u32);
-static void      e1000_rar_set_vf(struct e1000_hw *, u8 *, u32);
-static s32       e1000_read_mac_addr_vf(struct e1000_hw *);
+static s32 e1000_init_phy_params_vf(struct e1000_hw *hw);
+static s32 e1000_init_nvm_params_vf(struct e1000_hw *hw);
+static void e1000_release_vf(struct e1000_hw *hw);
+static s32 e1000_acquire_vf(struct e1000_hw *hw);
+static s32 e1000_setup_link_vf(struct e1000_hw *hw);
+static s32 e1000_get_bus_info_pcie_vf(struct e1000_hw *hw);
+static s32 e1000_init_mac_params_vf(struct e1000_hw *hw);
+static s32 e1000_check_for_link_vf(struct e1000_hw *hw);
+static s32 e1000_get_link_up_info_vf(struct e1000_hw *hw, u16 *speed,
+				     u16 *duplex);
+static s32 e1000_init_hw_vf(struct e1000_hw *hw);
+static s32 e1000_reset_hw_vf(struct e1000_hw *hw);
+static void e1000_update_mc_addr_list_vf(struct e1000_hw *hw, u8 *, u32);
+static void e1000_rar_set_vf(struct e1000_hw *, u8 *, u32);
+static s32 e1000_read_mac_addr_vf(struct e1000_hw *);
 
 /**
  *  e1000_init_phy_params_vf - Inits PHY params
@@ -219,7 +219,7 @@ static s32 e1000_get_bus_info_pcie_vf(struct e1000_hw *hw)
  *  the status register's data which is often stale and inaccurate.
  **/
 static s32 e1000_get_link_up_info_vf(struct e1000_hw *hw, u16 *speed,
-                                     u16 *duplex)
+				     u16 *duplex)
 {
 	s32 status;
 
@@ -288,7 +288,7 @@ static s32 e1000_reset_hw_vf(struct e1000_hw *hw)
 		ret_val = mbx->ops.read_posted(hw, msgbuf, 3, 0);
 		if (!ret_val) {
 			if (msgbuf[0] == (E1000_VF_RESET |
-						E1000_VT_MSGTYPE_ACK))
+			    E1000_VT_MSGTYPE_ACK))
 				memcpy(hw->mac.perm_addr, addr, 6);
 			else
 				ret_val = -E1000_ERR_MAC_INIT;
@@ -369,11 +369,22 @@ static u32 e1000_hash_mc_addr_vf(struct e1000_hw *hw, u8 *mc_addr)
 		bit_shift++;
 
 	hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
-	                          (((u16) mc_addr[5]) << bit_shift)));
+				  (((u16) mc_addr[5]) << bit_shift)));
 
 	return hash_value;
 }
 
+static void e1000_write_msg_read_ack(struct e1000_hw *hw,
+				     u32 *msg, u16 size)
+{
+	struct e1000_mbx_info *mbx = &hw->mbx;
+	u32 retmsg[E1000_VFMAILBOX_SIZE];
+	s32 retval = mbx->ops.write_posted(hw, msg, size, 0);
+
+	if (!retval)
+		mbx->ops.read_posted(hw, retmsg, E1000_VFMAILBOX_SIZE, 0);
+}
+
 /**
  *  e1000_update_mc_addr_list_vf - Update Multicast addresses
  *  @hw: pointer to the HW structure
@@ -384,9 +395,8 @@ static u32 e1000_hash_mc_addr_vf(struct e1000_hw *hw, u8 *mc_addr)
  *  The caller must have a packed mc_addr_list of multicast addresses.
  **/
 void e1000_update_mc_addr_list_vf(struct e1000_hw *hw,
-                                  u8 *mc_addr_list, u32 mc_addr_count)
+				  u8 *mc_addr_list, u32 mc_addr_count)
 {
-	struct e1000_mbx_info *mbx = &hw->mbx;
 	u32 msgbuf[E1000_VFMAILBOX_SIZE];
 	u16 *hash_list = (u16 *)&msgbuf[1];
 	u32 hash_value;
@@ -420,7 +430,7 @@ void e1000_update_mc_addr_list_vf(struct e1000_hw *hw,
 		mc_addr_list += ETH_ADDR_LEN;
 	}
 
-	mbx->ops.write_posted(hw, msgbuf, E1000_VFMAILBOX_SIZE, 0);
+	e1000_write_msg_read_ack(hw, msgbuf, E1000_VFMAILBOX_SIZE);
 }
 
 /**
@@ -431,7 +441,6 @@ void e1000_update_mc_addr_list_vf(struct e1000_hw *hw,
  **/
 void e1000_vfta_set_vf(struct e1000_hw *hw, u16 vid, bool set)
 {
-	struct e1000_mbx_info *mbx = &hw->mbx;
 	u32 msgbuf[2];
 
 	msgbuf[0] = E1000_VF_SET_VLAN;
@@ -440,7 +449,7 @@ void e1000_vfta_set_vf(struct e1000_hw *hw, u16 vid, bool set)
 	if (set)
 		msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
 
-	mbx->ops.write_posted(hw, msgbuf, 2, 0);
+	e1000_write_msg_read_ack(hw, msgbuf, 2);
 }
 
 /** e1000_rlpml_set_vf - Set the maximum receive packet length
@@ -449,13 +458,12 @@ void e1000_vfta_set_vf(struct e1000_hw *hw, u16 vid, bool set)
  **/
 void e1000_rlpml_set_vf(struct e1000_hw *hw, u16 max_size)
 {
-	struct e1000_mbx_info *mbx = &hw->mbx;
 	u32 msgbuf[2];
 
 	msgbuf[0] = E1000_VF_SET_LPE;
 	msgbuf[1] = max_size;
 
-	mbx->ops.write_posted(hw, msgbuf, 2, 0);
+	e1000_write_msg_read_ack(hw, msgbuf, 2);
 }
 
 /**
diff --git a/sys/dev/e1000/if_em.c b/sys/dev/e1000/if_em.c
index 10d556e..3d21da3 100644
--- a/sys/dev/e1000/if_em.c
+++ b/sys/dev/e1000/if_em.c
@@ -35,6 +35,7 @@
 #ifdef HAVE_KERNEL_OPTION_HEADERS
 #include "opt_device_polling.h"
 #include "opt_inet.h"
+#include "opt_inet6.h"
 #endif
 
 #include <sys/param.h>
@@ -93,7 +94,7 @@ int	em_display_debug_stats = 0;
 /*********************************************************************
  *  Driver version:
  *********************************************************************/
-char em_driver_version[] = "7.2.3";
+char em_driver_version[] = "7.3.2";
 
 /*********************************************************************
  *  PCI Device ID Table
@@ -286,6 +287,7 @@ static void	em_handle_link(void *context, int pending);
 
 static void	em_set_sysctl_value(struct adapter *, const char *,
 		    const char *, int *, int);
+static int	em_set_flowcntl(SYSCTL_HANDLER_ARGS);
 
 static __inline void em_rx_discard(struct rx_ring *, int);
 
@@ -382,13 +384,8 @@ static int em_rx_process_limit = 100;
 TUNABLE_INT("hw.em.rx_process_limit", &em_rx_process_limit);
 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN,
     &em_rx_process_limit, 0,
-    "Maximum number of received packets to process at a time, -1 means unlimited");
-
-/* Flow control setting - default to FULL */
-static int em_fc_setting = e1000_fc_full;
-TUNABLE_INT("hw.em.fc_setting", &em_fc_setting);
-SYSCTL_INT(_hw_em, OID_AUTO, fc_setting, CTLFLAG_RDTUN, &em_fc_setting, 0,
-    "Flow control");
+    "Maximum number of received packets to process "
+    "at a time, -1 means unlimited");
 
 /* Energy efficient ethernet - default to OFF */
 static int eee_setting = 0;
@@ -399,6 +396,10 @@ SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0,
 /* Global used in WOL setup with multiport cards */
 static int global_quad_port_a = 0;
 
+#ifdef DEV_NETMAP	/* see ixgbe.c for details */
+#include <dev/netmap/if_em_netmap.h>
+#endif /* DEV_NETMAP */
+
 /*********************************************************************
  *  Device identification routine
  *
@@ -469,6 +470,11 @@ em_attach(device_t dev)
 
 	INIT_DEBUGOUT("em_attach: begin");
 
+	if (resource_disabled("em", device_get_unit(dev))) {
+		device_printf(dev, "Disabled by device hint\n");
+		return (ENXIO);
+	}
+
 	adapter = device_get_softc(dev);
 	adapter->dev = adapter->osdep.dev = dev;
 	hw = &adapter->hw;
@@ -485,6 +491,11 @@ em_attach(device_t dev)
 	    OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 	    em_sysctl_debug_info, "I", "Debug Information");
 
+	SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
+	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
+	    OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
+	    em_set_flowcntl, "I", "Flow Control");
+
 	callout_init_mtx(&adapter->timer, &adapter->core_mtx, 0);
 
 	/* Determine hardware and mac info */
@@ -556,11 +567,6 @@ em_attach(device_t dev)
 	    "max number of rx packets to process", &adapter->rx_process_limit,
 	    em_rx_process_limit);
 
-	/* Sysctl for setting the interface flow control */
-	em_set_sysctl_value(adapter, "flow_control",
-	    "configure flow control",
-	    &adapter->fc_setting, em_fc_setting);
-
 	/*
 	 * Validate number of transmit and receive descriptors. It
 	 * must not exceed hardware maximum, and must be multiple
@@ -710,10 +716,14 @@ em_attach(device_t dev)
 		em_get_hw_control(adapter);
 
 	/* Tell the stack that the interface is not active */
-	adapter->ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
+	adapter->ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+	adapter->ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 
 	adapter->led_dev = led_create(em_led_func, adapter,
 	    device_get_nameunit(dev));
+#ifdef DEV_NETMAP
+	em_netmap_attach(adapter);
+#endif /* DEV_NETMAP */
 
 	INIT_DEBUGOUT("em_attach: end");
 
@@ -785,6 +795,10 @@ em_detach(device_t dev)
 	ether_ifdetach(adapter->ifp);
 	callout_drain(&adapter->timer);
 
+#ifdef DEV_NETMAP
+	netmap_detach(ifp);
+#endif /* DEV_NETMAP */
+
 	em_free_pci_resources(adapter);
 	bus_generic_detach(dev);
 	if_free(ifp);
@@ -836,6 +850,8 @@ em_resume(device_t dev)
 	struct ifnet *ifp = adapter->ifp;
 
 	EM_CORE_LOCK(adapter);
+	if (adapter->hw.mac.type == e1000_pch2lan)
+		e1000_resume_workarounds_pchlan(&adapter->hw);
 	em_init_locked(adapter);
 	em_init_manageability(adapter);
 	EM_CORE_UNLOCK(adapter);
@@ -845,17 +861,15 @@ em_resume(device_t dev)
 }
 
 
+#ifdef EM_MULTIQUEUE
 /*********************************************************************
- *  Transmit entry point
+ *  Multiqueue Transmit routines 
  *
- *  em_start is called by the stack to initiate a transmit.
- *  The driver will remain in this routine as long as there are
- *  packets to transmit and transmit resources are available.
- *  In case resources are not available stack is notified and
- *  the packet is requeued.
+ *  em_mq_start is called by the stack to initiate a transmit.
+ *  however, if busy the driver can queue the request rather
+ *  than do an immediate send. It is this that is an advantage
+ *  in this driver, rather than also having multiple tx queues.
  **********************************************************************/
-
-#ifdef EM_MULTIQUEUE
 static int
 em_mq_start_locked(struct ifnet *ifp, struct tx_ring *txr, struct mbuf *m)
 {
@@ -870,10 +884,6 @@ em_mq_start_locked(struct ifnet *ifp, struct tx_ring *txr, struct mbuf *m)
 		return (err);
 	}
 
-        /* Call cleanup if number of TX descriptors low */
-	if (txr->tx_avail <= EM_TX_CLEANUP_THRESHOLD)
-		em_txeof(txr);
-
 	enq = 0;
 	if (m == NULL) {
 		next = drbr_dequeue(ifp, txr->br);
@@ -896,10 +906,6 @@ em_mq_start_locked(struct ifnet *ifp, struct tx_ring *txr, struct mbuf *m)
 		ETHER_BPF_MTAP(ifp, next);
 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
                         break;
-		if (txr->tx_avail < EM_MAX_SCATTER) {
-			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
-			break;
-		}
 		next = drbr_dequeue(ifp, txr->br);
 	}
 
@@ -908,6 +914,11 @@ em_mq_start_locked(struct ifnet *ifp, struct tx_ring *txr, struct mbuf *m)
                 txr->queue_status = EM_QUEUE_WORKING;
 		txr->watchdog_time = ticks;
 	}
+
+	if (txr->tx_avail < EM_MAX_SCATTER)
+		em_txeof(txr);
+	if (txr->tx_avail < EM_MAX_SCATTER)
+		ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 	return (err);
 }
 
@@ -948,7 +959,6 @@ em_qflush(struct ifnet *ifp)
 	}
 	if_qflush(ifp);
 }
-
 #endif /* EM_MULTIQUEUE */
 
 static void
@@ -984,7 +994,6 @@ em_start_locked(struct ifnet *ifp, struct tx_ring *txr)
 		if (em_xmit(txr, &m_head)) {
 			if (m_head == NULL)
 				break;
-			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
 			break;
 		}
@@ -1011,6 +1020,12 @@ em_start(struct ifnet *ifp)
 		em_start_locked(ifp, txr);
 		EM_TX_UNLOCK(txr);
 	}
+	/*
+	** If we went inactive schedule
+	** a task to clean up.
+	*/
+	if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
+		taskqueue_enqueue(txr->tq, &txr->tx_task);
 	return;
 }
 
@@ -1027,11 +1042,12 @@ static int
 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 {
 	struct adapter	*adapter = ifp->if_softc;
-	struct ifreq *ifr = (struct ifreq *)data;
-#ifdef INET
-	struct ifaddr *ifa = (struct ifaddr *)data;
+	struct ifreq	*ifr = (struct ifreq *)data;
+#if defined(INET) || defined(INET6)
+	struct ifaddr	*ifa = (struct ifaddr *)data;
 #endif
-	int error = 0;
+	bool		avoid_reset = FALSE;
+	int		error = 0;
 
 	if (adapter->in_detach)
 		return (error);
@@ -1039,23 +1055,26 @@ em_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 	switch (command) {
 	case SIOCSIFADDR:
 #ifdef INET
-		if (ifa->ifa_addr->sa_family == AF_INET) {
-			/*
-			 * XXX
-			 * Since resetting hardware takes a very long time
-			 * and results in link renegotiation we only
-			 * initialize the hardware only when it is absolutely
-			 * required.
-			 */
+		if (ifa->ifa_addr->sa_family == AF_INET)
+			avoid_reset = TRUE;
+#endif
+#ifdef INET6
+		if (ifa->ifa_addr->sa_family == AF_INET6)
+			avoid_reset = TRUE;
+#endif
+		/*
+		** Calling init results in link renegotiation,
+		** so we avoid doing it when possible.
+		*/
+		if (avoid_reset) {
 			ifp->if_flags |= IFF_UP;
-			if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
-				EM_CORE_LOCK(adapter);
-				em_init_locked(adapter);
-				EM_CORE_UNLOCK(adapter);
-			}
-			arp_ifinit(ifp, ifa);
-		} else
+			if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
+				em_init(adapter);
+#ifdef INET
+			if (!(ifp->if_flags & IFF_NOARP))
+				arp_ifinit(ifp, ifa);
 #endif
+		} else
 			error = ether_ioctl(ifp, command, data);
 		break;
 	case SIOCSIFMTU:
@@ -1072,6 +1091,7 @@ em_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 		case e1000_ich10lan:
 		case e1000_pch2lan:
 		case e1000_82574:
+		case e1000_82583:
 		case e1000_80003es2lan:	/* 9K Jumbo Frame size */
 			max_frame_size = 9234;
 			break;
@@ -1079,7 +1099,6 @@ em_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 			max_frame_size = 4096;
 			break;
 			/* Adapters that do not support jumbo frames */
-		case e1000_82583:
 		case e1000_ich8lan:
 			max_frame_size = ETHER_MAX_LEN;
 			break;
@@ -1134,11 +1153,6 @@ em_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 		}
 		break;
 	case SIOCSIFMEDIA:
-		/*
-		** As the speed/duplex settings are being
-		** changed, we need to reset the PHY.
-		*/
-		adapter->hw.phy.reset_disable = FALSE;
 		/* Check SOL/IDER usage */
 		EM_CORE_LOCK(adapter);
 		if (e1000_check_reset_block(&adapter->hw)) {
@@ -1197,6 +1211,10 @@ em_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 			ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
 			reinit = 1;
 		}
+		if (mask & IFCAP_VLAN_HWTSO) {
+			ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
+			reinit = 1;
+		}
 		if ((mask & IFCAP_WOL) &&
 		    (ifp->if_capabilities & IFCAP_WOL) != 0) {
 			if (mask & IFCAP_WOL_MCAST)
@@ -1235,7 +1253,6 @@ em_init_locked(struct adapter *adapter)
 {
 	struct ifnet	*ifp = adapter->ifp;
 	device_t	dev = adapter->dev;
-	u32		pba;
 
 	INIT_DEBUGOUT("em_init: begin");
 
@@ -1244,46 +1261,6 @@ em_init_locked(struct adapter *adapter)
 	em_disable_intr(adapter);
 	callout_stop(&adapter->timer);
 
-	/*
-	 * Packet Buffer Allocation (PBA)
-	 * Writing PBA sets the receive portion of the buffer
-	 * the remainder is used for the transmit buffer.
-	 */
-	switch (adapter->hw.mac.type) {
-	/* Total Packet Buffer on these is 48K */
-	case e1000_82571:
-	case e1000_82572:
-	case e1000_80003es2lan:
-			pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
-		break;
-	case e1000_82573: /* 82573: Total Packet Buffer is 32K */
-			pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
-		break;
-	case e1000_82574:
-	case e1000_82583:
-			pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
-		break;
-	case e1000_ich8lan:
-		pba = E1000_PBA_8K;
-		break;
-	case e1000_ich9lan:
-	case e1000_ich10lan:
-		pba = E1000_PBA_10K;
-		break;
-	case e1000_pchlan:
-	case e1000_pch2lan:
-		pba = E1000_PBA_26K;
-		break;
-	default:
-		if (adapter->max_frame_size > 8192)
-			pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
-		else
-			pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
-	}
-
-	INIT_DEBUGOUT1("em_init: pba=%dK",pba);
-	E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
-	
 	/* Get the latest mac address, User can use a LAA */
         bcopy(IF_LLADDR(adapter->ifp), adapter->hw.mac.addr,
               ETHER_ADDR_LEN);
@@ -1362,6 +1339,7 @@ em_init_locked(struct adapter *adapter)
 	/* Don't lose promiscuous settings */
 	em_set_promisc(adapter);
 
+	/* Set the interface as ACTIVE */
 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 
@@ -1392,9 +1370,6 @@ em_init_locked(struct adapter *adapter)
 	/* AMT based hardware can now take control from firmware */
 	if (adapter->has_manage && adapter->has_amt)
 		em_get_hw_control(adapter);
-
-	/* Don't reset the phy next time init gets called */
-	adapter->hw.phy.reset_disable = TRUE;
 }
 
 static void
@@ -1984,6 +1959,14 @@ retry:
 		em_transmit_checksum_setup(txr, m_head,
 		    ip_off, ip, &txd_upper, &txd_lower);
 
+	if (m_head->m_flags & M_VLANTAG) {
+		/* Set the vlan id. */
+		txd_upper |=
+		    (htole16(m_head->m_pkthdr.ether_vtag) << 16);
+                /* Tell hardware to add tag */
+                txd_lower |= htole32(E1000_TXD_CMD_VLE);
+        }
+
 	i = txr->next_avail_desc;
 
 	/* Set up our transmit descriptors */
@@ -2041,15 +2024,13 @@ retry:
 	if (tso_desc) /* TSO used an extra for sentinel */
 		txr->tx_avail -= txd_used;
 
-	if (m_head->m_flags & M_VLANTAG) {
-		/* Set the vlan id. */
-		ctxd->upper.fields.special =
-		    htole16(m_head->m_pkthdr.ether_vtag);
-                /* Tell hardware to add tag */
-                ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
-        }
-
         tx_buffer->m_head = m_head;
+	/*
+	** Here we swap the map so the last descriptor,
+	** which gets the completion interrupt has the
+	** real map, and the first descriptor gets the
+	** unused map from this descriptor.
+	*/
 	tx_buffer_mapped->map = tx_buffer->map;
 	tx_buffer->map = map;
         bus_dmamap_sync(txr->txtag, map, BUS_DMASYNC_PREWRITE);
@@ -2219,22 +2200,21 @@ em_local_timer(void *arg)
 	else
 		trigger = E1000_ICS_RXDMT0;
 
-	/* 
-	** Don't do TX watchdog check if we've been paused
-	*/
-	if (adapter->pause_frames) {
-		adapter->pause_frames = 0;
-		goto out;
-	}
 	/*
 	** Check on the state of the TX queue(s), this 
 	** can be done without the lock because its RO
 	** and the HUNG state will be static if set.
 	*/
-	for (int i = 0; i < adapter->num_queues; i++, txr++)
-		if (txr->queue_status == EM_QUEUE_HUNG)
+	for (int i = 0; i < adapter->num_queues; i++, txr++) {
+		if ((txr->queue_status == EM_QUEUE_HUNG) &&
+		    (adapter->pause_frames == 0))
 			goto hung;
-out:
+		/* Schedule a TX tasklet if needed */
+		if (txr->tx_avail <= EM_MAX_SCATTER)
+			taskqueue_enqueue(txr->tq, &txr->tx_task);
+	}
+	
+	adapter->pause_frames = 0;
 	callout_reset(&adapter->timer, hz, em_local_timer, adapter);
 #ifndef DEVICE_POLLING
 	/* Trigger an RX interrupt to guarantee mbuf refresh */
@@ -2253,6 +2233,7 @@ hung:
 	    txr->me, txr->tx_avail, txr->next_to_clean);
 	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 	adapter->watchdog_events++;
+	adapter->pause_frames = 0;
 	em_init_locked(adapter);
 }
 
@@ -2351,7 +2332,8 @@ em_stop(void *arg)
 	callout_stop(&adapter->timer);
 
 	/* Tell the stack that the interface is no longer active */
-	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
+	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+	ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 
         /* Unarm watchdog timer. */
 	for (int i = 0; i < adapter->num_queues; i++, txr++) {
@@ -2447,6 +2429,7 @@ int
 em_allocate_legacy(struct adapter *adapter)
 {
 	device_t dev = adapter->dev;
+	struct tx_ring	*txr = adapter->tx_rings;
 	int error, rid = 0;
 
 	/* Manually turn off all interrupts */
@@ -2468,11 +2451,17 @@ em_allocate_legacy(struct adapter *adapter)
 	 * deferred processing contexts.
 	 */
 	TASK_INIT(&adapter->que_task, 0, em_handle_que, adapter);
-	TASK_INIT(&adapter->link_task, 0, em_handle_link, adapter);
 	adapter->tq = taskqueue_create_fast("em_taskq", M_NOWAIT,
 	    taskqueue_thread_enqueue, &adapter->tq);
-	taskqueue_start_threads(&adapter->tq, 1, PI_NET, "%s taskq",
+	taskqueue_start_threads(&adapter->tq, 1, PI_NET, "%s que",
 	    device_get_nameunit(adapter->dev));
+	/* Use a TX only tasklet for local timer */
+	TASK_INIT(&txr->tx_task, 0, em_handle_tx, txr);
+	txr->tq = taskqueue_create_fast("em_txq", M_NOWAIT,
+	    taskqueue_thread_enqueue, &txr->tq);
+	taskqueue_start_threads(&txr->tq, 1, PI_NET, "%s txq",
+	    device_get_nameunit(adapter->dev));
+	TASK_INIT(&adapter->link_task, 0, em_handle_link, adapter);
 	if ((error = bus_setup_intr(dev, adapter->res, INTR_TYPE_NET,
 	    em_irq_fast, NULL, adapter, &adapter->tag)) != 0) {
 		device_printf(dev, "Failed to register fast interrupt "
@@ -2489,7 +2478,8 @@ em_allocate_legacy(struct adapter *adapter)
  *
  *  Setup the MSIX Interrupt handlers
  *   This is not really Multiqueue, rather
- *   its just multiple interrupt vectors.
+ *   its just seperate interrupt vectors
+ *   for TX, RX, and Link.
  *
  **********************************************************************/
 int
@@ -2681,7 +2671,6 @@ em_setup_msix(struct adapter *adapter)
 	device_t dev = adapter->dev;
 	int val = 0;
 
-
 	/*
 	** Setup MSI/X for Hartwell: tests have shown
 	** use of two queues to be unstable, and to
@@ -2701,16 +2690,18 @@ em_setup_msix(struct adapter *adapter)
 			goto msi;
        		}
 		val = pci_msix_count(dev); 
-		if (val < 3) {
+		/* We only need 3 vectors */
+		if (val > 3)
+			val = 3;
+		if ((val != 3) && (val != 5)) {
 			bus_release_resource(dev, SYS_RES_MEMORY,
 			    PCIR_BAR(EM_MSIX_BAR), adapter->msix_mem);
 			adapter->msix_mem = NULL;
                		device_printf(adapter->dev,
-			    "MSIX: insufficient vectors, using MSI\n");
+			    "MSIX: incorrect vectors, using MSI\n");
 			goto msi;
 		}
-		val = 3;
-		adapter->num_queues = 1;
+
 		if (pci_alloc_msix(dev, &val) == 0) {
 			device_printf(adapter->dev,
 			    "Using MSIX interrupts "
@@ -2745,6 +2736,7 @@ em_reset(struct adapter *adapter)
 	struct ifnet	*ifp = adapter->ifp;
 	struct e1000_hw	*hw = &adapter->hw;
 	u16		rx_buffer_size;
+	u32		pba;
 
 	INIT_DEBUGOUT("em_reset: begin");
 
@@ -2760,6 +2752,48 @@ em_reset(struct adapter *adapter)
 	}
 
 	/*
+	 * Packet Buffer Allocation (PBA)
+	 * Writing PBA sets the receive portion of the buffer
+	 * the remainder is used for the transmit buffer.
+	 */
+	switch (hw->mac.type) {
+	/* Total Packet Buffer on these is 48K */
+	case e1000_82571:
+	case e1000_82572:
+	case e1000_80003es2lan:
+			pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
+		break;
+	case e1000_82573: /* 82573: Total Packet Buffer is 32K */
+			pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
+		break;
+	case e1000_82574:
+	case e1000_82583:
+			pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
+		break;
+	case e1000_ich8lan:
+		pba = E1000_PBA_8K;
+		break;
+	case e1000_ich9lan:
+	case e1000_ich10lan:
+		/* Boost Receive side for jumbo frames */
+		if (adapter->max_frame_size > 4096)
+			pba = E1000_PBA_14K;
+		else
+			pba = E1000_PBA_10K;
+		break;
+	case e1000_pchlan:
+	case e1000_pch2lan:
+		pba = E1000_PBA_26K;
+		break;
+	default:
+		if (adapter->max_frame_size > 8192)
+			pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
+		else
+			pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
+	}
+	E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
+
+	/*
 	 * These parameters control the automatic generation (Tx) and
 	 * response (Rx) to Ethernet PAUSE frames.
 	 * - High water mark should allow for at least two frames to be
@@ -2774,11 +2808,15 @@ em_reset(struct adapter *adapter)
 	 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 	 */
 	rx_buffer_size = ((E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10 );
-
 	hw->fc.high_water = rx_buffer_size -
 	    roundup2(adapter->max_frame_size, 1024);
 	hw->fc.low_water = hw->fc.high_water - 1500;
 
+	if (adapter->fc) /* locally set flow control value? */
+		hw->fc.requested_mode = adapter->fc;
+	else
+		hw->fc.requested_mode = e1000_fc_full;
+
 	if (hw->mac.type == e1000_80003es2lan)
 		hw->fc.pause_time = 0xFFFF;
 	else
@@ -2786,15 +2824,22 @@ em_reset(struct adapter *adapter)
 
 	hw->fc.send_xon = TRUE;
 
-        /* Set Flow control, use the tunable location if sane */
-	hw->fc.requested_mode = adapter->fc_setting;
-
-	/* Workaround: no TX flow ctrl for PCH */
-	if (hw->mac.type == e1000_pchlan)
+	/* Device specific overrides/settings */
+	switch (hw->mac.type) {
+	case e1000_pchlan:
+		/* Workaround: no TX flow ctrl for PCH */
                 hw->fc.requested_mode = e1000_fc_rx_pause;
-
-	/* Override - settings for PCH2LAN, ya its magic :) */
-	if (hw->mac.type == e1000_pch2lan) {
+		hw->fc.pause_time = 0xFFFF; /* override */
+		if (ifp->if_mtu > ETHERMTU) {
+			hw->fc.high_water = 0x3500;
+			hw->fc.low_water = 0x1500;
+		} else {
+			hw->fc.high_water = 0x5000;
+			hw->fc.low_water = 0x3000;
+		}
+		hw->fc.refresh_time = 0x1000;
+		break;
+	case e1000_pch2lan:
 		hw->fc.high_water = 0x5C20;
 		hw->fc.low_water = 0x5048;
 		hw->fc.pause_time = 0x0650;
@@ -2804,13 +2849,26 @@ em_reset(struct adapter *adapter)
 			E1000_WRITE_REG(hw, E1000_PBA, 12);
 		else
 			E1000_WRITE_REG(hw, E1000_PBA, 26);
+		break;
+        case e1000_ich9lan:
+        case e1000_ich10lan:
+		if (ifp->if_mtu > ETHERMTU) {
+			hw->fc.high_water = 0x2800;
+			hw->fc.low_water = hw->fc.high_water - 8;
+			break;
+		} 
+		/* else fall thru */
+	default:
+		if (hw->mac.type == e1000_80003es2lan)
+			hw->fc.pause_time = 0xFFFF;
+		break;
 	}
 
 	/* Issue a global reset */
 	e1000_reset_hw(hw);
 	E1000_WRITE_REG(hw, E1000_WUC, 0);
 	em_disable_aspm(adapter);
-
+	/* and a re-init */
 	if (e1000_init_hw(hw) < 0) {
 		device_printf(dev, "Hardware Initialization Failed\n");
 		return;
@@ -2855,28 +2913,25 @@ em_setup_interface(device_t dev, struct adapter *adapter)
 	ifp->if_capabilities = ifp->if_capenable = 0;
 
 #ifdef EM_MULTIQUEUE
-	/* Multiqueue tx functions */
+	/* Multiqueue stack interface */
 	ifp->if_transmit = em_mq_start;
 	ifp->if_qflush = em_qflush;
 #endif	
 
 	ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM;
-	ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM;
-
-	/* Enable TSO by default, can disable with ifconfig */
 	ifp->if_capabilities |= IFCAP_TSO4;
-	ifp->if_capenable |= IFCAP_TSO4;
-
 	/*
 	 * Tell the upper layer(s) we
 	 * support full VLAN capability
 	 */
 	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
-	ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
-	ifp->if_capenable |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
+	ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING
+			     |  IFCAP_VLAN_HWTSO
+			     |  IFCAP_VLAN_MTU;
+	ifp->if_capenable = ifp->if_capabilities;
 
 	/*
-	** Dont turn this on by default, if vlans are
+	** Don't turn this on by default, if vlans are
 	** created on another pseudo device (eg. lagg)
 	** then vlan events are not passed thru, breaking
 	** operation, but with HW FILTER off it works. If
@@ -3213,9 +3268,17 @@ em_setup_transmit_ring(struct tx_ring *txr)
 	struct adapter *adapter = txr->adapter;
 	struct em_buffer *txbuf;
 	int i;
+#ifdef DEV_NETMAP
+	struct netmap_adapter *na = NA(adapter->ifp);
+	struct netmap_slot *slot;
+#endif /* DEV_NETMAP */
 
 	/* Clear the old descriptor contents */
 	EM_TX_LOCK(txr);
+#ifdef DEV_NETMAP
+	slot = netmap_reset(na, NR_TX, txr->me, 0);
+#endif /* DEV_NETMAP */
+
 	bzero((void *)txr->tx_base,
 	      (sizeof(struct e1000_tx_desc)) * adapter->num_tx_desc);
 	/* Reset indices */
@@ -3232,6 +3295,22 @@ em_setup_transmit_ring(struct tx_ring *txr)
 			m_freem(txbuf->m_head);
 			txbuf->m_head = NULL;
 		}
+#ifdef DEV_NETMAP
+		if (slot) {
+			int si = i + na->tx_rings[txr->me].nkr_hwofs;
+			void *addr;
+
+			if (si >= na->num_tx_desc)
+				si -= na->num_tx_desc;
+			addr = NMB(slot + si);
+			txr->tx_base[i].buffer_addr =
+			    htole64(vtophys(addr));
+			/* reload the map for netmap mode */
+			netmap_load_map(txr->txtag,
+			    txbuf->map, addr, na->buff_size);
+		}
+#endif /* DEV_NETMAP */
+
 		/* clear the watch index */
 		txbuf->next_eop = -1;
         }
@@ -3304,11 +3383,6 @@ em_initialize_transmit_unit(struct adapter *adapter)
 
 	/* Set the default values for the Tx Inter Packet Gap timer */
 	switch (adapter->hw.mac.type) {
-	case e1000_82542:
-		tipg = DEFAULT_82542_TIPG_IPGT;
-		tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
-		tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
-		break;
 	case e1000_80003es2lan:
 		tipg = DEFAULT_82543_TIPG_IPGR1;
 		tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
@@ -3682,6 +3756,19 @@ em_txeof(struct tx_ring *txr)
 	struct ifnet   *ifp = adapter->ifp;
 
 	EM_TX_LOCK_ASSERT(txr);
+#ifdef DEV_NETMAP
+	if (ifp->if_capenable & IFCAP_NETMAP) {
+		struct netmap_adapter *na = NA(ifp);
+
+		selwakeuppri(&na->tx_rings[txr->me].si, PI_NET);
+		EM_TX_UNLOCK(txr);
+		EM_CORE_LOCK(adapter);
+		selwakeuppri(&na->tx_rings[na->num_queues + 1].si, PI_NET);
+		EM_CORE_UNLOCK(adapter);
+		EM_TX_LOCK(txr);
+		return (FALSE);
+	}
+#endif /* DEV_NETMAP */
 
 	/* No work, make sure watchdog is off */
         if (txr->tx_avail == adapter->num_tx_desc) {
@@ -3765,9 +3852,12 @@ em_txeof(struct tx_ring *txr)
         /*
          * If we have a minimum free, clear IFF_DRV_OACTIVE
          * to tell the stack that it is OK to send packets.
+	 * Notice that all writes of OACTIVE happen under the
+	 * TX lock which, with a single queue, guarantees 
+	 * sanity.
          */
-        if (txr->tx_avail > EM_MAX_SCATTER)
-                ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+        if (txr->tx_avail >= EM_MAX_SCATTER)
+		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 
 	/* Disable watchdog if all clean */
 	if (txr->tx_avail == adapter->num_tx_desc) {
@@ -3930,26 +4020,31 @@ em_setup_receive_ring(struct rx_ring *rxr)
 	struct	adapter 	*adapter = rxr->adapter;
 	struct em_buffer	*rxbuf;
 	bus_dma_segment_t	seg[1];
-	int			i, j, nsegs, error = 0;
+	int			rsize, nsegs, error;
 
 
 	/* Clear the ring contents */
 	EM_RX_LOCK(rxr);
+	rsize = roundup2(adapter->num_rx_desc *
+	    sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
+	bzero((void *)rxr->rx_base, rsize);
 
-	/* Invalidate all descriptors */
-	for (i = 0; i < adapter->num_rx_desc; i++) {
-		struct e1000_rx_desc* cur;
-		cur = &rxr->rx_base[i];
-		cur->status = 0;
+	/*
+	** Free current RX buffer structs and their mbufs
+	*/
+	for (int i = 0; i < adapter->num_rx_desc; i++) {
+		rxbuf = &rxr->rx_buffers[i];
+		if (rxbuf->m_head != NULL) {
+			bus_dmamap_sync(rxr->rxtag, rxbuf->map,
+			    BUS_DMASYNC_POSTREAD);
+			bus_dmamap_unload(rxr->rxtag, rxbuf->map);
+			m_freem(rxbuf->m_head);
+		}
 	}
 
 	/* Now replenish the mbufs */
-	i = j = rxr->next_to_refresh;
-	if (++j == adapter->num_rx_desc)
-		j = 0;
-
-	while (j != rxr->next_to_check) {
-		rxbuf = &rxr->rx_buffers[i];
+        for (int j = 0; j != adapter->num_rx_desc; ++j) {
+		rxbuf = &rxr->rx_buffers[j];
 		rxbuf->m_head = m_getjcl(M_DONTWAIT, MT_DATA,
 		    M_PKTHDR, adapter->rx_mbuf_sz);
 		if (rxbuf->m_head == NULL) {
@@ -3973,16 +4068,66 @@ em_setup_receive_ring(struct rx_ring *rxr)
 		    rxbuf->map, BUS_DMASYNC_PREREAD);
 
 		/* Update descriptor */
-		rxr->rx_base[i].buffer_addr = htole64(seg[0].ds_addr);
-		i = j;
-		if (++j == adapter->num_rx_desc)
-			j = 0;
+		rxr->rx_base[j].buffer_addr = htole64(seg[0].ds_addr);
 	}
-
-fail:
-	rxr->next_to_refresh = i;
+	rxr->next_to_check = 0;
+	rxr->next_to_refresh = 0;
 	bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map,
 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+
+#ifdef DEV_NETMAP
+    {
+	/*
+	 * This driver is slightly different from the standard:
+	 * it refills the rings in blocks of 8, so the while()
+	 * above completes any leftover work. Also, after if_init()
+	 * the ring starts at rxr->next_to_check instead of 0.
+	 *
+	 * Currently: we leave the mbufs allocated even in netmap
+	 * mode, and simply make the NIC ring point to the
+	 * correct buffer (netmap_buf or mbuf) depending on
+	 * the mode. To avoid mbuf leaks, when in netmap mode we
+	 * must make sure that next_to_refresh == next_to_check - 1
+	 * so that the above while() loop is never run on init.
+	 *
+	 * A better way would be to free the mbufs when entering
+	 * netmap mode, and set next_to_refresh/check in
+	 * a way that the mbufs are completely reallocated
+	 * when going back to standard mode.
+	 */
+	struct netmap_adapter *na = NA(adapter->ifp);
+	struct netmap_slot *slot = netmap_reset(na,
+		NR_RX, rxr->me, rxr->next_to_check);
+	int sj = slot ? na->rx_rings[rxr->me].nkr_hwofs : 0;
+
+	/* slot sj corresponds to entry j in the NIC ring */
+	if (sj < 0)
+		sj += adapter->num_rx_desc;
+
+	for (int j = 0; j != adapter->num_rx_desc; j++, sj++) {
+		void *addr;
+		int sz;
+
+		rxbuf = &rxr->rx_buffers[j];
+		/* no mbuf and regular mode -> skip this entry */
+		if (rxbuf->m_head == NULL && !slot)
+			continue;
+		/* Handle wrap. Cannot use "na" here, could be NULL */
+		if (sj >= adapter->num_rx_desc)
+			sj -= adapter->num_rx_desc;
+		/* see comment, set slot addr and map */
+		addr = slot ? NMB(slot + sj) : rxbuf->m_head->m_data;
+		sz = slot ? na->buff_size : adapter->rx_mbuf_sz;
+		// XXX load or reload ?
+		netmap_load_map(rxr->rxtag, rxbuf->map, addr, sz);
+		/* Update descriptor */
+		rxr->rx_base[j].buffer_addr = htole64(vtophys(addr));
+		bus_dmamap_sync(rxr->rxtag, rxbuf->map, BUS_DMASYNC_PREREAD);
+	}
+    }
+#endif /* DEV_NETMAP */
+
+fail:
 	EM_RX_UNLOCK(rxr);
 	return (error);
 }
@@ -4009,10 +4154,9 @@ fail:
 	 * the rings that completed, the failing case will have
 	 * cleaned up for itself. 'q' failed, so its the terminus.
 	 */
-	for (int i = 0, n = 0; i < q; ++i) {
+	for (int i = 0; i < q; ++i) {
 		rxr = &adapter->rx_rings[i];
-		n = rxr->next_to_check;
-		while(n != rxr->next_to_refresh) {
+		for (int n = 0; n < adapter->num_rx_desc; n++) {
 			struct em_buffer *rxbuf;
 			rxbuf = &rxr->rx_buffers[n];
 			if (rxbuf->m_head != NULL) {
@@ -4022,8 +4166,6 @@ fail:
 				m_freem(rxbuf->m_head);
 				rxbuf->m_head = NULL;
 			}
-			if (++n == adapter->num_rx_desc)
-				n = 0;
 		}
 		rxr->next_to_check = 0;
 		rxr->next_to_refresh = 0;
@@ -4067,8 +4209,7 @@ em_free_receive_buffers(struct rx_ring *rxr)
 	INIT_DEBUGOUT("free_receive_buffers: begin");
 
 	if (rxr->rx_buffers != NULL) {
-		int i = rxr->next_to_check;
-		while(i != rxr->next_to_refresh) {
+		for (int i = 0; i < adapter->num_rx_desc; i++) {
 			rxbuf = &rxr->rx_buffers[i];
 			if (rxbuf->map != NULL) {
 				bus_dmamap_sync(rxr->rxtag, rxbuf->map,
@@ -4080,8 +4221,6 @@ em_free_receive_buffers(struct rx_ring *rxr)
 				m_freem(rxbuf->m_head);
 				rxbuf->m_head = NULL;
 			}
-			if (++i == adapter->num_rx_desc)
-				i = 0;
 		}
 		free(rxr->rx_buffers, M_DEVBUF);
 		rxr->rx_buffers = NULL;
@@ -4122,7 +4261,9 @@ em_initialize_receive_unit(struct adapter *adapter)
 	 * up the descriptor ring
 	 */
 	rctl = E1000_READ_REG(hw, E1000_RCTL);
-	E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
+	/* Do not disable if ever enabled on this hardware */
+	if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583))
+		E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
 
 	E1000_WRITE_REG(&adapter->hw, E1000_RADV,
 	    adapter->rx_abs_int_delay.value);
@@ -4136,14 +4277,13 @@ em_initialize_receive_unit(struct adapter *adapter)
 	** When using MSIX interrupts we need to throttle
 	** using the EITR register (82574 only)
 	*/
-	if (hw->mac.type == e1000_82574)
+	if (hw->mac.type == e1000_82574) {
 		for (int i = 0; i < 4; i++)
 			E1000_WRITE_REG(hw, E1000_EITR_82574(i),
 			    DEFAULT_ITR);
-
-	/* Disable accelerated ackknowledge */
-	if (adapter->hw.mac.type == e1000_82574)
+		/* Disable accelerated acknowledge */
 		E1000_WRITE_REG(hw, E1000_RFCTL, E1000_RFCTL_ACK_DIS);
+	}
 
 	if (ifp->if_capenable & IFCAP_RXCSUM) {
 		rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
@@ -4169,18 +4309,35 @@ em_initialize_receive_unit(struct adapter *adapter)
 		E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32));
 		E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr);
 		/* Setup the Head and Tail Descriptor Pointers */
-		E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
-		E1000_WRITE_REG(hw, E1000_RDT(i), rxr->next_to_refresh);
+		E1000_WRITE_REG(hw, E1000_RDH(i), 0);
+		E1000_WRITE_REG(hw, E1000_RDT(i), adapter->num_rx_desc - 1);
+#ifdef DEV_NETMAP
+		/*
+		 * an init() while a netmap client is active must
+		 * preserve the rx buffers passed to userspace.
+		 * In this driver it means we adjust RDT to
+		 * something different from next_to_refresh.
+		 */
+		if (ifp->if_capenable & IFCAP_NETMAP) {
+			struct netmap_adapter *na = NA(adapter->ifp);
+			struct netmap_kring *kring = &na->rx_rings[i];
+			int t = rxr->next_to_refresh - kring->nr_hwavail;
+
+			if (t < 0)
+				t += na->num_rx_desc;
+			E1000_WRITE_REG(hw, E1000_RDT(i), t);
+		} else
+#endif /* DEV_NETMAP */
+		E1000_WRITE_REG(hw, E1000_RDT(i), adapter->num_rx_desc - 1);
 	}
 
-	/* Set early receive threshold on appropriate hw */
+	/* Set PTHRESH for improved jumbo performance */
 	if (((adapter->hw.mac.type == e1000_ich9lan) ||
 	    (adapter->hw.mac.type == e1000_pch2lan) ||
 	    (adapter->hw.mac.type == e1000_ich10lan)) &&
 	    (ifp->if_mtu > ETHERMTU)) {
 		u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
 		E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
-		E1000_WRITE_REG(hw, E1000_ERT, 0x100 | (1 << 13));
 	}
 		
 	if (adapter->hw.mac.type == e1000_pch2lan) {
@@ -4247,6 +4404,19 @@ em_rxeof(struct rx_ring *rxr, int count, int *done)
 
 	EM_RX_LOCK(rxr);
 
+#ifdef DEV_NETMAP
+	if (ifp->if_capenable & IFCAP_NETMAP) {
+		struct netmap_adapter *na = NA(ifp);
+
+		selwakeuppri(&na->rx_rings[rxr->me].si, PI_NET);
+		EM_RX_UNLOCK(rxr);
+		EM_CORE_LOCK(adapter);
+		selwakeuppri(&na->rx_rings[na->num_queues + 1].si, PI_NET);
+		EM_CORE_UNLOCK(adapter);
+		return (0);
+	}
+#endif /* DEV_NETMAP */
+
 	for (i = rxr->next_to_check, processed = 0; count != 0;) {
 
 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
@@ -4314,10 +4484,6 @@ em_rxeof(struct rx_ring *rxr, int count, int *done)
 				    E1000_RXD_SPC_VLAN_MASK);
 				sendmp->m_flags |= M_VLANTAG;
 			}
-#ifdef EM_MULTIQUEUE
-			sendmp->m_pkthdr.flowid = rxr->msix;
-			sendmp->m_flags |= M_FLOWID;
-#endif
 #ifndef __NO_STRICT_ALIGNMENT
 skip:
 #endif
@@ -4792,7 +4958,7 @@ em_enable_wakeup(device_t dev)
 	    (adapter->hw.mac.type == e1000_pchlan) ||
 	    (adapter->hw.mac.type == e1000_ich9lan) ||
 	    (adapter->hw.mac.type == e1000_ich10lan))
-		e1000_disable_gig_wol_ich8lan(&adapter->hw);
+		e1000_suspend_workarounds_ich8lan(&adapter->hw);
 
 	/* Keep the laser running on Fiber adapters */
 	if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
@@ -5389,7 +5555,7 @@ em_add_hw_stats(struct adapter *adapter)
 static int
 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
 {
-	struct adapter *adapter;
+	struct adapter *adapter = (struct adapter *)arg1;
 	int error;
 	int result;
 
@@ -5404,10 +5570,8 @@ em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
 	 * first 32 16-bit words of the EEPROM to
 	 * the screen.
 	 */
-	if (result == 1) {
-		adapter = (struct adapter *)arg1;
+	if (result == 1)
 		em_print_nvm_info(adapter);
-        }
 
 	return (error);
 }
@@ -5497,6 +5661,49 @@ em_set_sysctl_value(struct adapter *adapter, const char *name,
 	    OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, limit, value, description);
 }
 
+
+/*
+** Set flow control using sysctl:
+** Flow control values:
+**      0 - off
+**      1 - rx pause
+**      2 - tx pause
+**      3 - full
+*/
+static int
+em_set_flowcntl(SYSCTL_HANDLER_ARGS)
+{       
+        int		error;
+	static int	input = 3; /* default is full */
+        struct adapter	*adapter = (struct adapter *) arg1;
+                    
+        error = sysctl_handle_int(oidp, &input, 0, req);
+    
+        if ((error) || (req->newptr == NULL))
+                return (error);
+                
+	if (input == adapter->fc) /* no change? */
+		return (error);
+
+        switch (input) {
+                case e1000_fc_rx_pause:
+                case e1000_fc_tx_pause:
+                case e1000_fc_full:
+                case e1000_fc_none:
+                        adapter->hw.fc.requested_mode = input;
+			adapter->fc = input;
+                        break;
+                default:
+			/* Do nothing */
+			return (error);
+        }
+
+        adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode;
+        e1000_force_mac_fc(&adapter->hw);
+        return (error);
+}
+
+
 static int
 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
 {
@@ -5533,10 +5740,11 @@ em_print_debug_info(struct adapter *adapter)
 		printf("Interface is RUNNING ");
 	else
 		printf("Interface is NOT RUNNING\n");
+
 	if (adapter->ifp->if_drv_flags & IFF_DRV_OACTIVE)
-		printf("and ACTIVE\n");
-	else
 		printf("and INACTIVE\n");
+	else
+		printf("and ACTIVE\n");
 
 	device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
 	    E1000_READ_REG(&adapter->hw, E1000_TDH(0)),
diff --git a/sys/dev/e1000/if_em.h b/sys/dev/e1000/if_em.h
index e25904e..f1afbad 100644
--- a/sys/dev/e1000/if_em.h
+++ b/sys/dev/e1000/if_em.h
@@ -212,7 +212,8 @@
 #define EM_BAR_MEM_TYPE_64BIT	0x00000004
 #define EM_MSIX_BAR		3	/* On 82575 */
 
-#if !defined(SYSCTL_ADD_UQUAD)
+/* More backward compatibility */
+#if __FreeBSD_version < 900000
 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
 #endif
 
@@ -418,11 +419,11 @@ struct adapter {
 	u32		shadow_vfta[EM_VFTA_SIZE];
 
 	/* Info about the interface */
-	u8		link_active;
+	u16		link_active;
+	u16		fc;
 	u16		link_speed;
 	u16		link_duplex;
 	u32		smartspeed;
-	u32		fc_setting;
 
 	struct em_int_delay_info tx_int_delay;
 	struct em_int_delay_info tx_abs_int_delay;
diff --git a/sys/dev/e1000/if_igb.c b/sys/dev/e1000/if_igb.c
index 4ae4204..1380c3b 100644
--- a/sys/dev/e1000/if_igb.c
+++ b/sys/dev/e1000/if_igb.c
@@ -100,7 +100,7 @@ int	igb_display_debug_stats = 0;
 /*********************************************************************
  *  Driver version:
  *********************************************************************/
-char igb_driver_version[] = "version - 2.2.5";
+char igb_driver_version[] = "version - 2.3.1";
 
 
 /*********************************************************************
@@ -171,15 +171,13 @@ static int	igb_detach(device_t);
 static int	igb_shutdown(device_t);
 static int	igb_suspend(device_t);
 static int	igb_resume(device_t);
+static void	igb_start(struct ifnet *);
+static void	igb_start_locked(struct tx_ring *, struct ifnet *ifp);
 #if __FreeBSD_version >= 800000
 static int	igb_mq_start(struct ifnet *, struct mbuf *);
 static int	igb_mq_start_locked(struct ifnet *,
 		    struct tx_ring *, struct mbuf *);
 static void	igb_qflush(struct ifnet *);
-static void	igb_deferred_mq_start(void *, int);
-#else
-static void	igb_start(struct ifnet *);
-static void	igb_start_locked(struct tx_ring *, struct ifnet *ifp);
 #endif
 static int	igb_ioctl(struct ifnet *, u_long, caddr_t);
 static void	igb_init(void *);
@@ -225,8 +223,9 @@ static __inline void igb_rx_input(struct rx_ring *,
 
 static bool	igb_rxeof(struct igb_queue *, int, int *);
 static void	igb_rx_checksum(u32, struct mbuf *, u32);
-static int	igb_tx_ctx_setup(struct tx_ring *, struct mbuf *);
-static bool	igb_tso_setup(struct tx_ring *, struct mbuf *, u32 *);
+static bool	igb_tx_ctx_setup(struct tx_ring *, struct mbuf *);
+static bool	igb_tso_setup(struct tx_ring *, struct mbuf *, int,
+		    struct ip *, struct tcphdr *);
 static void	igb_set_promisc(struct adapter *);
 static void	igb_disable_promisc(struct adapter *);
 static void	igb_set_multi(struct adapter *);
@@ -348,7 +347,7 @@ SYSCTL_INT(_hw_igb, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
 ** into the header and thus use no cluster. Its
 ** a very workload dependent type feature.
 */
-static bool igb_header_split = FALSE;
+static int igb_header_split = FALSE;
 TUNABLE_INT("hw.igb.hdr_split", &igb_header_split);
 SYSCTL_INT(_hw_igb, OID_AUTO, header_split, CTLFLAG_RDTUN, &igb_header_split, 0,
     "Enable receive mbuf header split");
@@ -369,6 +368,9 @@ SYSCTL_INT(_hw_igb, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN,
     &igb_rx_process_limit, 0,
     "Maximum number of received packets to process at a time, -1 means unlimited");
 
+#ifdef DEV_NETMAP	/* see ixgbe.c for details */
+#include <dev/netmap/if_igb_netmap.h>
+#endif /* DEV_NETMAP */
 /*********************************************************************
  *  Device identification routine
  *
@@ -611,16 +613,6 @@ igb_attach(device_t dev)
 		goto err_late;
 	}
 
-	/* 
-	** Configure Interrupts
-	*/
-	if ((adapter->msix > 1) && (igb_enable_msix))
-		error = igb_allocate_msix(adapter);
-	else /* MSI or Legacy */
-		error = igb_allocate_legacy(adapter);
-	if (error)
-		goto err_late;
-
 	/* Setup OS specific network interface */
 	if (igb_setup_interface(dev, adapter) != 0)
 		goto err_late;
@@ -659,11 +651,25 @@ igb_attach(device_t dev)
 	igb_add_hw_stats(adapter);
 
 	/* Tell the stack that the interface is not active */
-	adapter->ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
+	adapter->ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+	adapter->ifp->if_drv_flags |=  IFF_DRV_OACTIVE;
 
 	adapter->led_dev = led_create(igb_led_func, adapter,
 	    device_get_nameunit(dev));
 
+	/* 
+	** Configure Interrupts
+	*/
+	if ((adapter->msix > 1) && (igb_enable_msix))
+		error = igb_allocate_msix(adapter);
+	else /* MSI or Legacy */
+		error = igb_allocate_legacy(adapter);
+	if (error)
+		goto err_late;
+
+#ifdef DEV_NETMAP
+	igb_netmap_attach(adapter);
+#endif /* DEV_NETMAP */
 	INIT_DEBUGOUT("igb_attach: end");
 
 	return (0);
@@ -673,10 +679,10 @@ err_late:
 	igb_free_transmit_structures(adapter);
 	igb_free_receive_structures(adapter);
 	igb_release_hw_control(adapter);
-	if (adapter->ifp != NULL)
-		if_free(adapter->ifp);
 err_pci:
 	igb_free_pci_resources(adapter);
+	if (adapter->ifp != NULL)
+		if_free(adapter->ifp);
 	free(adapter->mta, M_DEVBUF);
 	IGB_CORE_LOCK_DESTROY(adapter);
 
@@ -707,8 +713,6 @@ igb_detach(device_t dev)
 		return (EBUSY);
 	}
 
-	ether_ifdetach(adapter->ifp);
-
 	if (adapter->led_dev != NULL)
 		led_destroy(adapter->led_dev);
 
@@ -740,8 +744,13 @@ igb_detach(device_t dev)
 	if (adapter->vlan_detach != NULL)
 		EVENTHANDLER_DEREGISTER(vlan_unconfig, adapter->vlan_detach);
 
+	ether_ifdetach(adapter->ifp);
+
 	callout_drain(&adapter->timer);
 
+#ifdef DEV_NETMAP
+	netmap_detach(adapter->ifp);
+#endif /* DEV_NETMAP */
 	igb_free_pci_resources(adapter);
 	bus_generic_detach(dev);
 	if_free(ifp);
@@ -799,27 +808,14 @@ igb_resume(device_t dev)
 {
 	struct adapter *adapter = device_get_softc(dev);
 	struct ifnet *ifp = adapter->ifp;
-#if __FreeBSD_version >= 800000
-	struct tx_ring *txr = adapter->tx_rings;
-#endif
 
 	IGB_CORE_LOCK(adapter);
 	igb_init_locked(adapter);
 	igb_init_manageability(adapter);
 
 	if ((ifp->if_flags & IFF_UP) &&
-	    (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
-#if __FreeBSD_version < 800000
+	    (ifp->if_drv_flags & IFF_DRV_RUNNING))
 		igb_start(ifp);
-#else
-		for (int i = 0; i < adapter->num_queues; i++, txr++) {
-			IGB_TX_LOCK(txr);
-			if (!drbr_empty(ifp, txr->br))
-				igb_mq_start_locked(ifp, txr, NULL);
-			IGB_TX_UNLOCK(txr);
-		}
-#endif
-	}
 
 	IGB_CORE_UNLOCK(adapter);
 
@@ -827,7 +823,6 @@ igb_resume(device_t dev)
 }
 
 
-#if __FreeBSD_version < 800000
 /*********************************************************************
  *  Transmit entry point
  *
@@ -858,7 +853,7 @@ igb_start_locked(struct tx_ring *txr, struct ifnet *ifp)
 
 	while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
 		if (txr->tx_avail <= IGB_MAX_SCATTER) {
-			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
+			txr->queue_status |= IGB_QUEUE_DEPLETED;
 			break;
 		}
 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
@@ -869,10 +864,10 @@ igb_start_locked(struct tx_ring *txr, struct ifnet *ifp)
 		 *  NULL on failure.  In that event, we can't requeue.
 		 */
 		if (igb_xmit(txr, &m_head)) {
-			if (m_head == NULL)
-				break;
-			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
-			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
+			if (m_head != NULL)
+				IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
+			if (txr->tx_avail <= IGB_MAX_SCATTER)
+				txr->queue_status |= IGB_QUEUE_DEPLETED;
 			break;
 		}
 
@@ -881,7 +876,7 @@ igb_start_locked(struct tx_ring *txr, struct ifnet *ifp)
 
 		/* Set watchdog on */
 		txr->watchdog_time = ticks;
-		txr->queue_status = IGB_QUEUE_WORKING;
+		txr->queue_status |= IGB_QUEUE_WORKING;
 	}
 }
  
@@ -904,7 +899,7 @@ igb_start(struct ifnet *ifp)
 	return;
 }
 
-#else /* __FreeBSD_version >= 800000 */
+#if __FreeBSD_version >= 800000
 /*
 ** Multiqueue Transmit driver
 **
@@ -915,21 +910,25 @@ igb_mq_start(struct ifnet *ifp, struct mbuf *m)
 	struct adapter		*adapter = ifp->if_softc;
 	struct igb_queue	*que;
 	struct tx_ring		*txr;
-	int 			i = 0, err = 0;
+	int 			i, err = 0;
+	bool			moveable = TRUE;
 
 	/* Which queue to use */
-	if ((m->m_flags & M_FLOWID) != 0)
+	if ((m->m_flags & M_FLOWID) != 0) {
 		i = m->m_pkthdr.flowid % adapter->num_queues;
+		moveable = FALSE;
+	} else
+		i = curcpu % adapter->num_queues;
 
 	txr = &adapter->tx_rings[i];
 	que = &adapter->queues[i];
-
-	if (IGB_TX_TRYLOCK(txr)) {
+	if (((txr->queue_status & IGB_QUEUE_DEPLETED) == 0) &&
+	    IGB_TX_TRYLOCK(txr)) {
 		err = igb_mq_start_locked(ifp, txr, m);
 		IGB_TX_UNLOCK(txr);
 	} else {
 		err = drbr_enqueue(ifp, txr->br, m);
-		taskqueue_enqueue(que->tq, &txr->txq_task);
+		taskqueue_enqueue(que->tq, &que->que_task);
 	}
 
 	return (err);
@@ -944,8 +943,9 @@ igb_mq_start_locked(struct ifnet *ifp, struct tx_ring *txr, struct mbuf *m)
 
 	IGB_TX_LOCK_ASSERT(txr);
 
-	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
-	    IFF_DRV_RUNNING || adapter->link_active == 0) {
+	if (((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) ||
+	    (txr->queue_status == IGB_QUEUE_DEPLETED) ||
+	    adapter->link_active == 0) {
 		if (m != NULL)
 			err = drbr_enqueue(ifp, txr->br, m);
 		return (err);
@@ -973,39 +973,21 @@ igb_mq_start_locked(struct ifnet *ifp, struct tx_ring *txr, struct mbuf *m)
 		ETHER_BPF_MTAP(ifp, next);
 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
 			break;
-		if (txr->tx_avail <= IGB_TX_CLEANUP_THRESHOLD)
-			igb_txeof(txr);
-		if (txr->tx_avail <= IGB_MAX_SCATTER) {
-			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
-			break;
-		}
 		next = drbr_dequeue(ifp, txr->br);
 	}
 	if (enq > 0) {
 		/* Set the watchdog */
-		txr->queue_status = IGB_QUEUE_WORKING;
+		txr->queue_status |= IGB_QUEUE_WORKING;
 		txr->watchdog_time = ticks;
 	}
+	if (txr->tx_avail <= IGB_TX_CLEANUP_THRESHOLD)
+		igb_txeof(txr);
+	if (txr->tx_avail <= IGB_MAX_SCATTER)
+		txr->queue_status |= IGB_QUEUE_DEPLETED;
 	return (err);
 }
 
 /*
- * Called from a taskqueue to drain queued transmit packets.
- */
-static void
-igb_deferred_mq_start(void *arg, int pending)
-{
-	struct tx_ring *txr = arg;
-	struct adapter *adapter = txr->adapter;
-	struct ifnet *ifp = adapter->ifp;
-
-	IGB_TX_LOCK(txr);
-	if (!drbr_empty(ifp, txr->br))
-		igb_mq_start_locked(ifp, txr, NULL);
-	IGB_TX_UNLOCK(txr);
-}
-
-/*
 ** Flush all ring buffers
 */
 static void
@@ -1023,7 +1005,7 @@ igb_qflush(struct ifnet *ifp)
 	}
 	if_qflush(ifp);
 }
-#endif /* __FreeBSD_version < 800000 */
+#endif /* __FreeBSD_version >= 800000 */
 
 /*********************************************************************
  *  Ioctl entry point
@@ -1129,11 +1111,6 @@ igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 		}
 		break;
 	case SIOCSIFMEDIA:
-		/*
-		** As the speed/duplex settings are being
-		** changed, we need toreset the PHY.
-		*/
-		adapter->hw.phy.reset_disable = FALSE;
 		/* Check SOL/IDER usage */
 		IGB_CORE_LOCK(adapter);
 		if (e1000_check_reset_block(&adapter->hw)) {
@@ -1324,10 +1301,8 @@ igb_init_locked(struct adapter *adapter)
 	}
 
 	/* Set Energy Efficient Ethernet */
-	e1000_set_eee_i350(&adapter->hw);
 
-	/* Don't reset the phy next time init gets called */
-	adapter->hw.phy.reset_disable = TRUE;
+	e1000_set_eee_i350(&adapter->hw);
 }
 
 static void
@@ -1352,18 +1327,21 @@ igb_handle_que(void *context, int pending)
 	if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
 		bool	more;
 
-		more = igb_rxeof(que, -1, NULL);
+		more = igb_rxeof(que, adapter->rx_process_limit, NULL);
 
 		IGB_TX_LOCK(txr);
 		if (igb_txeof(txr))
 			more = TRUE;
 #if __FreeBSD_version >= 800000
-		if (!drbr_empty(ifp, txr->br))
+		/* Process the stack queue only if not depleted */
+		if (((txr->queue_status & IGB_QUEUE_DEPLETED) == 0) &&
+		    !drbr_empty(ifp, txr->br))
 			igb_mq_start_locked(ifp, txr, NULL);
 #else
 		igb_start_locked(txr, ifp);
 #endif
 		IGB_TX_UNLOCK(txr);
+		/* Do we need another? */
 		if (more || (ifp->if_drv_flags & IFF_DRV_OACTIVE)) {
 			taskqueue_enqueue(que->tq, &que->que_task);
 			return;
@@ -1494,7 +1472,7 @@ igb_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
 
 /*********************************************************************
  *
- *  MSIX TX Interrupt Service routine
+ *  MSIX Que Interrupt Service routine
  *
  **********************************************************************/
 static void
@@ -1569,8 +1547,7 @@ igb_msix_que(void *arg)
 
 no_calc:
 	/* Schedule a clean task if needed*/
-	if (more_tx || more_rx ||
-	    (adapter->ifp->if_drv_flags & IFF_DRV_OACTIVE))
+	if (more_tx || more_rx)
 		taskqueue_enqueue(que->tq, &que->que_task);
 	else
 		/* Reenable this interrupt */
@@ -1718,10 +1695,8 @@ igb_media_change(struct ifnet *ifp)
 /*********************************************************************
  *
  *  This routine maps the mbufs to Advanced TX descriptors.
- *  used by the 82575 adapter.
  *  
  **********************************************************************/
-
 static int
 igb_xmit(struct tx_ring *txr, struct mbuf **m_headp)
 {
@@ -1730,22 +1705,123 @@ igb_xmit(struct tx_ring *txr, struct mbuf **m_headp)
 	bus_dmamap_t		map;
 	struct igb_tx_buffer	*tx_buffer, *tx_buffer_mapped;
 	union e1000_adv_tx_desc	*txd = NULL;
-	struct mbuf		*m_head;
-	u32			olinfo_status = 0, cmd_type_len = 0;
-	int			nsegs, i, j, error, first, last = 0;
-	u32			hdrlen = 0;
-
-	m_head = *m_headp;
-
+	struct mbuf		*m_head = *m_headp;
+	struct ether_vlan_header *eh = NULL;
+	struct ip		*ip = NULL;
+	struct tcphdr		*th = NULL;
+	u32			hdrlen, cmd_type_len, olinfo_status = 0;
+	int			ehdrlen, poff;
+	int			nsegs, i, first, last = 0;
+	int			error, do_tso, remap = 1;
 
 	/* Set basic descriptor constants */
-	cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
+	cmd_type_len = E1000_ADVTXD_DTYP_DATA;
 	cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
 	if (m_head->m_flags & M_VLANTAG)
 		cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
 
+retry:
+	m_head = *m_headp;
+	do_tso = ((m_head->m_pkthdr.csum_flags & CSUM_TSO) != 0);
+	hdrlen = ehdrlen = poff = 0;
+
 	/*
-         * Map the packet for DMA.
+	 * Intel recommends entire IP/TCP header length reside in a single
+	 * buffer. If multiple descriptors are used to describe the IP and
+	 * TCP header, each descriptor should describe one or more
+	 * complete headers; descriptors referencing only parts of headers
+	 * are not supported. If all layer headers are not coalesced into
+	 * a single buffer, each buffer should not cross a 4KB boundary,
+	 * or be larger than the maximum read request size.
+	 * Controller also requires modifing IP/TCP header to make TSO work
+	 * so we firstly get a writable mbuf chain then coalesce ethernet/
+	 * IP/TCP header into a single buffer to meet the requirement of
+	 * controller. This also simplifies IP/TCP/UDP checksum offloading
+	 * which also has similiar restrictions.
+	 */
+	if (do_tso || m_head->m_pkthdr.csum_flags & CSUM_OFFLOAD) {
+		if (do_tso || (m_head->m_next != NULL && 
+		    m_head->m_pkthdr.csum_flags & CSUM_OFFLOAD)) {
+			if (M_WRITABLE(*m_headp) == 0) {
+				m_head = m_dup(*m_headp, M_DONTWAIT);
+				m_freem(*m_headp);
+				if (m_head == NULL) {
+					*m_headp = NULL;
+					return (ENOBUFS);
+				}
+				*m_headp = m_head;
+			}
+		}
+		/*
+		 * Assume IPv4, we don't have TSO/checksum offload support
+		 * for IPv6 yet.
+		 */
+		ehdrlen = sizeof(struct ether_header);
+		m_head = m_pullup(m_head, ehdrlen);
+		if (m_head == NULL) {
+			*m_headp = NULL;
+			return (ENOBUFS);
+		}
+		eh = mtod(m_head, struct ether_vlan_header *);
+		if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
+			ehdrlen = sizeof(struct ether_vlan_header);
+			m_head = m_pullup(m_head, ehdrlen);
+			if (m_head == NULL) {
+				*m_headp = NULL;
+				return (ENOBUFS);
+			}
+		}
+		m_head = m_pullup(m_head, ehdrlen + sizeof(struct ip));
+		if (m_head == NULL) {
+			*m_headp = NULL;
+			return (ENOBUFS);
+		}
+		ip = (struct ip *)(mtod(m_head, char *) + ehdrlen);
+		poff = ehdrlen + (ip->ip_hl << 2);
+		if (do_tso) {
+			m_head = m_pullup(m_head, poff + sizeof(struct tcphdr));
+			if (m_head == NULL) {
+				*m_headp = NULL;
+				return (ENOBUFS);
+			}
+			/*
+			 * The pseudo TCP checksum does not include TCP payload
+			 * length so driver should recompute the checksum here
+			 * what hardware expect to see. This is adherence of
+			 * Microsoft's Large Send specification.
+			 */
+			th = (struct tcphdr *)(mtod(m_head, char *) + poff);
+			th->th_sum = in_pseudo(ip->ip_src.s_addr,
+			    ip->ip_dst.s_addr, htons(IPPROTO_TCP));
+			/* Keep track of the full header length */
+			hdrlen = poff + (th->th_off << 2);
+		} else if (m_head->m_pkthdr.csum_flags & CSUM_TCP) {
+			m_head = m_pullup(m_head, poff + sizeof(struct tcphdr));
+			if (m_head == NULL) {
+				*m_headp = NULL;
+				return (ENOBUFS);
+			}
+			th = (struct tcphdr *)(mtod(m_head, char *) + poff);
+			m_head = m_pullup(m_head, poff + (th->th_off << 2));
+			if (m_head == NULL) {
+				*m_headp = NULL;
+				return (ENOBUFS);
+			}
+			ip = (struct ip *)(mtod(m_head, char *) + ehdrlen);
+			th = (struct tcphdr *)(mtod(m_head, char *) + poff);
+		} else if (m_head->m_pkthdr.csum_flags & CSUM_UDP) {
+			m_head = m_pullup(m_head, poff + sizeof(struct udphdr));
+			if (m_head == NULL) {
+				*m_headp = NULL;
+				return (ENOBUFS);
+			}
+			ip = (struct ip *)(mtod(m_head, char *) + ehdrlen);
+		}
+		*m_headp = m_head;
+	}
+
+	/*
+	 * Map the packet for DMA
 	 *
 	 * Capture the first descriptor index,
 	 * this descriptor will have the index
@@ -1760,7 +1836,16 @@ igb_xmit(struct tx_ring *txr, struct mbuf **m_headp)
 	error = bus_dmamap_load_mbuf_sg(txr->txtag, map,
 	    *m_headp, segs, &nsegs, BUS_DMA_NOWAIT);
 
-	if (error == EFBIG) {
+	/*
+	 * There are two types of errors we can (try) to handle:
+	 * - EFBIG means the mbuf chain was too long and bus_dma ran
+	 *   out of segments.  Defragment the mbuf chain and try again.
+	 * - ENOMEM means bus_dma could not obtain enough bounce buffers
+	 *   at this point in time.  Defer sending and try again later.
+	 * All other errors, in particular EINVAL, are fatal and prevent the
+	 * mbuf chain from ever going through.  Drop it and report error.
+	 */
+	if (error == EFBIG && remap) {
 		struct mbuf *m;
 
 		m = m_defrag(*m_headp, M_DONTWAIT);
@@ -1772,19 +1857,9 @@ igb_xmit(struct tx_ring *txr, struct mbuf **m_headp)
 		}
 		*m_headp = m;
 
-		/* Try it again */
-		error = bus_dmamap_load_mbuf_sg(txr->txtag, map,
-		    *m_headp, segs, &nsegs, BUS_DMA_NOWAIT);
-
-		if (error == ENOMEM) {
-			adapter->no_tx_dma_setup++;
-			return (error);
-		} else if (error != 0) {
-			adapter->no_tx_dma_setup++;
-			m_freem(*m_headp);
-			*m_headp = NULL;
-			return (error);
-		}
+		/* Try it again, but only once */
+		remap = 0;
+		goto retry;
 	} else if (error == ENOMEM) {
 		adapter->no_tx_dma_setup++;
 		return (error);
@@ -1795,29 +1870,35 @@ igb_xmit(struct tx_ring *txr, struct mbuf **m_headp)
 		return (error);
 	}
 
-	/* Check again to be sure we have enough descriptors */
-        if (nsegs > (txr->tx_avail - 2)) {
+	/*
+	** Make sure we don't overrun the ring,
+	** we need nsegs descriptors and one for
+	** the context descriptor used for the
+	** offloads.
+	*/
+        if ((nsegs + 1) > (txr->tx_avail - 2)) {
                 txr->no_desc_avail++;
 		bus_dmamap_unload(txr->txtag, map);
 		return (ENOBUFS);
         }
 	m_head = *m_headp;
 
-        /*
-         * Set up the context descriptor:
-         * used when any hardware offload is done.
-	 * This includes CSUM, VLAN, and TSO. It
-	 * will use the first descriptor.
+	/* Do hardware assists:
+         * Set up the context descriptor, used
+         * when any hardware offload is done.
+         * This includes CSUM, VLAN, and TSO.
+         * It will use the first descriptor.
          */
-        if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
-		if (igb_tso_setup(txr, m_head, &hdrlen)) {
+
+	if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
+		if (igb_tso_setup(txr, m_head, ehdrlen, ip, th)) {
 			cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
 			olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
 			olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
 		} else
-			return (ENXIO); 
+			return (ENXIO);
 	} else if (igb_tx_ctx_setup(txr, m_head))
-		olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
+			olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
 
 	/* Calculate payload length */
 	olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
@@ -1829,7 +1910,7 @@ igb_xmit(struct tx_ring *txr, struct mbuf **m_headp)
 
 	/* Set up our transmit descriptors */
 	i = txr->next_avail_desc;
-	for (j = 0; j < nsegs; j++) {
+	for (int j = 0; j < nsegs; j++) {
 		bus_size_t seg_len;
 		bus_addr_t seg_addr;
 
@@ -1850,8 +1931,14 @@ igb_xmit(struct tx_ring *txr, struct mbuf **m_headp)
 
 	txr->next_avail_desc = i;
 	txr->tx_avail -= nsegs;
-
         tx_buffer->m_head = m_head;
+
+	/*
+	** Here we swap the map so the last descriptor,
+	** which gets the completion interrupt has the
+	** real map, and the first descriptor gets the
+	** unused map from this descriptor.
+	*/
 	tx_buffer_mapped->map = tx_buffer->map;
 	tx_buffer->map = map;
         bus_dmamap_sync(txr->txtag, map, BUS_DMASYNC_PREWRITE);
@@ -1869,6 +1956,7 @@ igb_xmit(struct tx_ring *txr, struct mbuf **m_headp)
 	 */
 	tx_buffer = &txr->tx_buffers[first];
 	tx_buffer->next_eop = last;
+	/* Update the watchdog time early and often */
 	txr->watchdog_time = ticks;
 
 	/*
@@ -1881,9 +1969,7 @@ igb_xmit(struct tx_ring *txr, struct mbuf **m_headp)
 	++txr->tx_packets;
 
 	return (0);
-
 }
-
 static void
 igb_set_promisc(struct adapter *adapter)
 {
@@ -1990,7 +2076,10 @@ igb_local_timer(void *arg)
 {
 	struct adapter		*adapter = arg;
 	device_t		dev = adapter->dev;
+	struct ifnet		*ifp = adapter->ifp;
 	struct tx_ring		*txr = adapter->tx_rings;
+	struct igb_queue	*que = adapter->queues;
+	int			hung = 0, busy = 0;
 
 
 	IGB_CORE_LOCK_ASSERT(adapter);
@@ -1998,22 +2087,29 @@ igb_local_timer(void *arg)
 	igb_update_link_status(adapter);
 	igb_update_stats_counters(adapter);
 
-	/* 
-	** If flow control has paused us since last checking
-	** it invalidates the watchdog timing, so dont run it.
-	*/
-	if (adapter->pause_frames) {
-		adapter->pause_frames = 0;
-		goto out;
-	}
-
         /*
-        ** Watchdog: check for time since any descriptor was cleaned
+        ** Check the TX queues status
+	**	- central locked handling of OACTIVE
+	**	- watchdog only if all queues show hung
         */
-	for (int i = 0; i < adapter->num_queues; i++, txr++)
-		if (txr->queue_status == IGB_QUEUE_HUNG) 
-			goto timeout;
-out:
+	for (int i = 0; i < adapter->num_queues; i++, que++, txr++) {
+		if ((txr->queue_status & IGB_QUEUE_HUNG) &&
+		    (adapter->pause_frames == 0))
+			++hung;
+		if (txr->queue_status & IGB_QUEUE_DEPLETED)
+			++busy;
+		if ((txr->queue_status & IGB_QUEUE_IDLE) == 0)
+			taskqueue_enqueue(que->tq, &que->que_task);
+	}
+	if (hung == adapter->num_queues)
+		goto timeout;
+	if (busy == adapter->num_queues)
+		ifp->if_drv_flags |= IFF_DRV_OACTIVE;
+	else if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) &&
+	    (busy < adapter->num_queues))
+		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+
+	adapter->pause_frames = 0;
 	callout_reset(&adapter->timer, hz, igb_local_timer, adapter);
 #ifndef DEVICE_POLLING
 	/* Schedule all queue interrupts - deadlock protection */
@@ -2106,7 +2202,7 @@ igb_update_link_status(struct adapter *adapter)
 		adapter->link_active = 0;
 		/* This can sleep */
 		if_link_state_change(ifp, LINK_STATE_DOWN);
-		/* Turn off watchdogs */
+		/* Reset queue state */
 		for (int i = 0; i < adapter->num_queues; i++, txr++)
 			txr->queue_status = IGB_QUEUE_IDLE;
 	}
@@ -2135,9 +2231,10 @@ igb_stop(void *arg)
 	callout_stop(&adapter->timer);
 
 	/* Tell the stack that the interface is no longer active */
-	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
+	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+	ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 
-	/* Unarm watchdog timer. */
+	/* Disarm watchdog timer. */
 	for (int i = 0; i < adapter->num_queues; i++, txr++) {
 		IGB_TX_LOCK(txr);
 		txr->queue_status = IGB_QUEUE_IDLE;
@@ -2232,7 +2329,6 @@ igb_allocate_legacy(struct adapter *adapter)
 {
 	device_t		dev = adapter->dev;
 	struct igb_queue	*que = adapter->queues;
-	struct tx_ring		*txr = adapter->tx_rings;
 	int			error, rid = 0;
 
 	/* Turn off all interrupts */
@@ -2251,10 +2347,6 @@ igb_allocate_legacy(struct adapter *adapter)
 		return (ENXIO);
 	}
 
-#if __FreeBSD_version >= 800000
-	TASK_INIT(&txr->txq_task, 0, igb_deferred_mq_start, txr);
-#endif
-
 	/*
 	 * Try allocating a fast interrupt and the associated deferred
 	 * processing contexts.
@@ -2292,6 +2384,9 @@ igb_allocate_msix(struct adapter *adapter)
 	struct igb_queue	*que = adapter->queues;
 	int			error, rid, vector = 0;
 
+	/* Be sure to start with all interrupts disabled */
+	E1000_WRITE_REG(&adapter->hw, E1000_IMC, ~0);
+	E1000_WRITE_FLUSH(&adapter->hw);
 
 	for (int i = 0; i < adapter->num_queues; i++, vector++, que++) {
 		rid = vector +1;
@@ -2325,13 +2420,9 @@ igb_allocate_msix(struct adapter *adapter)
 		*/
 		if (adapter->num_queues > 1)
 			bus_bind_intr(dev, que->res, i);
-#if __FreeBSD_version >= 800000
-		TASK_INIT(&que->txr->txq_task, 0, igb_deferred_mq_start,
-		    que->txr);
-#endif
 		/* Make tasklet for deferred handling */
 		TASK_INIT(&que->que_task, 0, igb_handle_que, que);
-		que->tq = taskqueue_create("igb_que", M_NOWAIT,
+		que->tq = taskqueue_create_fast("igb_que", M_NOWAIT,
 		    taskqueue_thread_enqueue, &que->tq);
 		taskqueue_start_threads(&que->tq, 1, PI_NET, "%s que",
 		    device_get_nameunit(adapter->dev));
@@ -2538,24 +2629,13 @@ igb_free_pci_resources(struct adapter *adapter)
 	else
 		(adapter->msix != 0) ? (rid = 1):(rid = 0);
 
-	que = adapter->queues;
 	if (adapter->tag != NULL) {
-		taskqueue_drain(que->tq, &adapter->link_task);
 		bus_teardown_intr(dev, adapter->res, adapter->tag);
 		adapter->tag = NULL;
 	}
 	if (adapter->res != NULL)
 		bus_release_resource(dev, SYS_RES_IRQ, rid, adapter->res);
 
-	for (int i = 0; i < adapter->num_queues; i++, que++) {
-		if (que->tq != NULL) {
-#if __FreeBSD_version >= 800000
-			taskqueue_drain(que->tq, &que->txr->txq_task);
-#endif
-			taskqueue_drain(que->tq, &que->que_task);
-			taskqueue_free(que->tq);
-		}
-	}
 mem:
 	if (adapter->msix)
 		pci_release_msi(dev);
@@ -2686,7 +2766,6 @@ igb_reset(struct adapter *adapter)
 		pba = E1000_READ_REG(hw, E1000_RXPBS);
 		pba = e1000_rxpbs_adjust_82580(pba);
 		break;
-		pba = E1000_PBA_35K;
 	default:
 		break;
 	}
@@ -2741,12 +2820,10 @@ igb_reset(struct adapter *adapter)
 
 	fc->pause_time = IGB_FC_PAUSE_TIME;
 	fc->send_xon = TRUE;
-	if (fc->requested_mode)
-		fc->current_mode = fc->requested_mode;
+	if (adapter->fc)
+		fc->requested_mode = adapter->fc;
 	else
-		fc->current_mode = e1000_fc_full;
-
-	adapter->fc = fc->current_mode;
+		fc->requested_mode = e1000_fc_default;
 
 	/* Issue a global reset */
 	e1000_reset_hw(hw);
@@ -2827,11 +2904,10 @@ igb_setup_interface(device_t dev, struct adapter *adapter)
 	ifp->if_softc = adapter;
 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 	ifp->if_ioctl = igb_ioctl;
+	ifp->if_start = igb_start;
 #if __FreeBSD_version >= 800000
 	ifp->if_transmit = igb_mq_start;
 	ifp->if_qflush = igb_qflush;
-#else
-	ifp->if_start = igb_start;
 #endif
 	IFQ_SET_MAXLEN(&ifp->if_snd, adapter->num_tx_desc - 1);
 	ifp->if_snd.ifq_drv_maxlen = adapter->num_tx_desc - 1;
@@ -3212,9 +3288,16 @@ igb_setup_transmit_ring(struct tx_ring *txr)
 	struct adapter *adapter = txr->adapter;
 	struct igb_tx_buffer *txbuf;
 	int i;
+#ifdef DEV_NETMAP
+	struct netmap_adapter *na = NA(adapter->ifp);
+	struct netmap_slot *slot;
+#endif /* DEV_NETMAP */
 
 	/* Clear the old descriptor contents */
 	IGB_TX_LOCK(txr);
+#ifdef DEV_NETMAP
+	slot = netmap_reset(na, NR_TX, txr->me, 0);
+#endif /* DEV_NETMAP */
 	bzero((void *)txr->tx_base,
 	      (sizeof(union e1000_adv_tx_desc)) * adapter->num_tx_desc);
 	/* Reset indices */
@@ -3231,6 +3314,17 @@ igb_setup_transmit_ring(struct tx_ring *txr)
 			m_freem(txbuf->m_head);
 			txbuf->m_head = NULL;
 		}
+#ifdef DEV_NETMAP
+		if (slot) {
+			/* slot si is mapped to the i-th NIC-ring entry */
+			int si = i + na->tx_rings[txr->me].nkr_hwofs;
+
+			if (si < 0)
+				si += na->num_tx_desc;
+			netmap_load_map(txr->txtag, txbuf->map,
+				NMB(slot + si), na->buff_size);
+		}
+#endif /* DEV_NETMAP */
 		/* clear the watch index */
 		txbuf->next_eop = -1;
         }
@@ -3396,8 +3490,9 @@ igb_free_transmit_buffers(struct tx_ring *txr)
  *  Setup work for hardware segmentation offload (TSO)
  *
  **********************************************************************/
-static boolean_t
-igb_tso_setup(struct tx_ring *txr, struct mbuf *mp, u32 *hdrlen)
+static bool
+igb_tso_setup(struct tx_ring *txr, struct mbuf *mp, int ehdrlen,
+	struct ip *ip, struct tcphdr *th)
 {
 	struct adapter *adapter = txr->adapter;
 	struct e1000_adv_tx_context_desc *TXD;
@@ -3405,45 +3500,15 @@ igb_tso_setup(struct tx_ring *txr, struct mbuf *mp, u32 *hdrlen)
 	u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
 	u32 mss_l4len_idx = 0;
 	u16 vtag = 0;
-	int ctxd, ehdrlen, ip_hlen, tcp_hlen;
-	struct ether_vlan_header *eh;
-	struct ip *ip;
-	struct tcphdr *th;
-
-
-	/*
-	 * Determine where frame payload starts.
-	 * Jump over vlan headers if already present
-	 */
-	eh = mtod(mp, struct ether_vlan_header *);
-	if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN))
-		ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
-	else
-		ehdrlen = ETHER_HDR_LEN;
-
-	/* Ensure we have at least the IP+TCP header in the first mbuf. */
-	if (mp->m_len < ehdrlen + sizeof(struct ip) + sizeof(struct tcphdr))
-		return FALSE;
+	int ctxd, ip_hlen, tcp_hlen;
 
-	/* Only supports IPV4 for now */
 	ctxd = txr->next_avail_desc;
 	tx_buffer = &txr->tx_buffers[ctxd];
 	TXD = (struct e1000_adv_tx_context_desc *) &txr->tx_base[ctxd];
 
-	ip = (struct ip *)(mp->m_data + ehdrlen);
-	if (ip->ip_p != IPPROTO_TCP)
-                return FALSE;   /* 0 */
 	ip->ip_sum = 0;
 	ip_hlen = ip->ip_hl << 2;
-	th = (struct tcphdr *)((caddr_t)ip + ip_hlen);
-	th->th_sum = in_pseudo(ip->ip_src.s_addr,
-	    ip->ip_dst.s_addr, htons(IPPROTO_TCP));
 	tcp_hlen = th->th_off << 2;
-	/*
-	 * Calculate header length, this is used
-	 * in the transmit desc in igb_xmit
-	 */
-	*hdrlen = ehdrlen + ip_hlen + tcp_hlen;
 
 	/* VLAN MACLEN IPLEN */
 	if (mp->m_flags & M_VLANTAG) {
@@ -3626,6 +3691,19 @@ igb_txeof(struct tx_ring *txr)
 
 	IGB_TX_LOCK_ASSERT(txr);
 
+#ifdef DEV_NETMAP
+	if (ifp->if_capenable & IFCAP_NETMAP) {
+		struct netmap_adapter *na = NA(ifp);
+
+		selwakeuppri(&na->tx_rings[txr->me].si, PI_NET);
+		IGB_TX_UNLOCK(txr);
+		IGB_CORE_LOCK(adapter);
+		selwakeuppri(&na->tx_rings[na->num_queues + 1].si, PI_NET);
+		IGB_CORE_UNLOCK(adapter);
+		IGB_TX_LOCK(txr);
+		return FALSE;
+	}
+#endif /* DEV_NETMAP */
         if (txr->tx_avail == adapter->num_tx_desc) {
 		txr->queue_status = IGB_QUEUE_IDLE;
                 return FALSE;
@@ -3705,20 +3783,20 @@ igb_txeof(struct tx_ring *txr)
 	** for too long indicates a hang.
 	*/
 	if ((!processed) && ((ticks - txr->watchdog_time) > IGB_WATCHDOG))
-		txr->queue_status = IGB_QUEUE_HUNG;
-
+		txr->queue_status |= IGB_QUEUE_HUNG;
         /*
-         * If we have a minimum free, clear IFF_DRV_OACTIVE
-         * to tell the stack that it is OK to send packets.
+         * If we have a minimum free,
+         * clear depleted state bit
          */
-        if (txr->tx_avail > IGB_TX_CLEANUP_THRESHOLD) {                
-                ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
-		/* All clean, turn off the watchdog */
-                if (txr->tx_avail == adapter->num_tx_desc) {
-			txr->queue_status = IGB_QUEUE_IDLE;
-			return (FALSE);
-		}
+        if (txr->tx_avail >= IGB_QUEUE_THRESHOLD)          
+                txr->queue_status &= ~IGB_QUEUE_DEPLETED;
+
+	/* All clean, turn off the watchdog */
+	if (txr->tx_avail == adapter->num_tx_desc) {
+		txr->queue_status = IGB_QUEUE_IDLE;
+		return (FALSE);
         }
+
 	return (TRUE);
 }
 
@@ -3949,6 +4027,10 @@ igb_setup_receive_ring(struct rx_ring *rxr)
 	bus_dma_segment_t	pseg[1], hseg[1];
 	struct lro_ctrl		*lro = &rxr->lro;
 	int			rsize, nsegs, error = 0;
+#ifdef DEV_NETMAP
+	struct netmap_adapter *na = NA(rxr->adapter->ifp);
+	struct netmap_slot *slot;
+#endif /* DEV_NETMAP */
 
 	adapter = rxr->adapter;
 	dev = adapter->dev;
@@ -3956,6 +4038,9 @@ igb_setup_receive_ring(struct rx_ring *rxr)
 
 	/* Clear the ring contents */
 	IGB_RX_LOCK(rxr);
+#ifdef DEV_NETMAP
+	slot = netmap_reset(na, NR_RX, rxr->me, 0);
+#endif /* DEV_NETMAP */
 	rsize = roundup2(adapter->num_rx_desc *
 	    sizeof(union e1000_adv_rx_desc), IGB_DBA_ALIGN);
 	bzero((void *)rxr->rx_base, rsize);
@@ -3974,6 +4059,22 @@ igb_setup_receive_ring(struct rx_ring *rxr)
 		struct mbuf	*mh, *mp;
 
 		rxbuf = &rxr->rx_buffers[j];
+#ifdef DEV_NETMAP
+		if (slot) {
+			/* slot sj is mapped to the i-th NIC-ring entry */
+			int sj = j + na->rx_rings[rxr->me].nkr_hwofs;
+			void *addr;
+
+			if (sj < 0)
+				sj += na->num_rx_desc;
+			addr = NMB(slot + sj);
+			netmap_load_map(rxr->ptag,
+			    rxbuf->pmap, addr, na->buff_size);
+			/* Update descriptor */
+			rxr->rx_base[j].read.pkt_addr = htole64(vtophys(addr));
+			continue;
+		}
+#endif /* DEV_NETMAP */
 		if (rxr->hdr_split == FALSE)
 			goto skip_head;
 
@@ -4258,6 +4359,26 @@ igb_initialize_receive_units(struct adapter *adapter)
 	for (int i = 0; i < adapter->num_queues; i++) {
 		rxr = &adapter->rx_rings[i];
 		E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
+#ifdef DEV_NETMAP
+		/*
+		 * an init() while a netmap client is active must
+		 * preserve the rx buffers passed to userspace.
+		 * In this driver it means we adjust RDT to
+		 * somthing different from next_to_refresh
+		 * (which is not used in netmap mode).
+		 */
+		if (ifp->if_capenable & IFCAP_NETMAP) {
+			struct netmap_adapter *na = NA(adapter->ifp);
+			struct netmap_kring *kring = &na->rx_rings[i];
+			int t = rxr->next_to_refresh - kring->nr_hwavail;
+
+			if (t >= adapter->num_rx_desc)
+				t -= adapter->num_rx_desc;
+			else if (t < 0)
+				t += adapter->num_rx_desc;
+			E1000_WRITE_REG(hw, E1000_RDT(i), t);
+		} else
+#endif /* DEV_NETMAP */
 		E1000_WRITE_REG(hw, E1000_RDT(i), rxr->next_to_refresh);
 	}
 	return;
@@ -4436,6 +4557,19 @@ igb_rxeof(struct igb_queue *que, int count, int *done)
 	bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map,
 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 
+#ifdef DEV_NETMAP
+	if (ifp->if_capenable & IFCAP_NETMAP) {
+		struct netmap_adapter *na = NA(ifp);
+
+		selwakeuppri(&na->rx_rings[rxr->me].si, PI_NET);
+		IGB_RX_UNLOCK(rxr);
+		IGB_CORE_LOCK(adapter);
+		selwakeuppri(&na->rx_rings[na->num_queues + 1].si, PI_NET);
+		IGB_CORE_UNLOCK(adapter);
+		return (0);
+	}
+#endif /* DEV_NETMAP */
+
 	/* Main clean loop */
 	for (i = rxr->next_to_check; count != 0;) {
 		struct mbuf		*sendmp, *mh, *mp;
@@ -4762,8 +4896,8 @@ igb_setup_vlan_hw_support(struct adapter *adapter)
 				e1000_vfta_set_vf(hw,
 				    adapter->shadow_vfta[i], TRUE);
 			else
-				E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
-                           	 i, adapter->shadow_vfta[i]);
+				e1000_write_vfta(hw,
+				    i, adapter->shadow_vfta[i]);
 		}
 }
 
@@ -5629,23 +5763,26 @@ igb_set_sysctl_value(struct adapter *adapter, const char *name,
 static int
 igb_set_flowcntl(SYSCTL_HANDLER_ARGS)
 {
-	int error;
-	struct adapter *adapter = (struct adapter *) arg1;
+	int		error;
+	static int	input = 3; /* default is full */
+	struct adapter	*adapter = (struct adapter *) arg1;
 
-	error = sysctl_handle_int(oidp, &adapter->fc, 0, req);
+	error = sysctl_handle_int(oidp, &input, 0, req);
 
 	if ((error) || (req->newptr == NULL))
 		return (error);
 
-	switch (adapter->fc) {
+	switch (input) {
 		case e1000_fc_rx_pause:
 		case e1000_fc_tx_pause:
 		case e1000_fc_full:
-			adapter->hw.fc.requested_mode = adapter->fc;
-			break;
 		case e1000_fc_none:
+			adapter->hw.fc.requested_mode = input;
+			adapter->fc = input;
+			break;
 		default:
-			adapter->hw.fc.requested_mode = e1000_fc_none;
+			/* Do nothing */
+			return (error);
 	}
 
 	adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode;
diff --git a/sys/dev/e1000/if_igb.h b/sys/dev/e1000/if_igb.h
index 80abf6e..9989206 100644
--- a/sys/dev/e1000/if_igb.h
+++ b/sys/dev/e1000/if_igb.h
@@ -188,9 +188,13 @@
 #define IGB_TX_BUFFER_SIZE		((uint32_t) 1514)
 #define IGB_FC_PAUSE_TIME		0x0680
 #define IGB_EEPROM_APME			0x400;
-#define IGB_QUEUE_IDLE			0
-#define IGB_QUEUE_WORKING		1
-#define IGB_QUEUE_HUNG			2
+/* Queue minimum free for use */
+#define IGB_QUEUE_THRESHOLD		(adapter->num_tx_desc / 8)
+/* Queue bit defines */
+#define IGB_QUEUE_IDLE			1
+#define IGB_QUEUE_WORKING		2
+#define IGB_QUEUE_HUNG			4
+#define IGB_QUEUE_DEPLETED		8
 
 /*
  * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
@@ -297,7 +301,6 @@ struct tx_ring {
 	struct buf_ring		*br;
 #endif
 	bus_dma_tag_t		txtag;
-	struct task		txq_task;
 
 	u32			bytes;
 	u32			packets;
diff --git a/sys/dev/e1000/if_lem.c b/sys/dev/e1000/if_lem.c
index a9202f0..5fe24be 100644
--- a/sys/dev/e1000/if_lem.c
+++ b/sys/dev/e1000/if_lem.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -35,6 +35,7 @@
 #ifdef HAVE_KERNEL_OPTION_HEADERS
 #include "opt_device_polling.h"
 #include "opt_inet.h"
+#include "opt_inet6.h"
 #endif
 
 #include <sys/param.h>
@@ -84,7 +85,7 @@
 /*********************************************************************
  *  Legacy Em Driver version:
  *********************************************************************/
-char lem_driver_version[] = "1.0.3";
+char lem_driver_version[] = "1.0.4";
 
 /*********************************************************************
  *  PCI Device ID Table
@@ -316,6 +317,10 @@ TUNABLE_INT("hw.em.fc_setting", &lem_fc_setting);
 /* Global used in WOL setup with multiport cards */
 static int global_quad_port_a = 0;
 
+#ifdef DEV_NETMAP	/* see ixgbe.c for details */
+#include <dev/netmap/if_lem_netmap.h>
+#endif /* DEV_NETMAP */
+
 /*********************************************************************
  *  Device identification routine
  *
@@ -386,6 +391,11 @@ lem_attach(device_t dev)
 
 	INIT_DEBUGOUT("lem_attach: begin");
 
+	if (resource_disabled("lem", device_get_unit(dev))) {
+		device_printf(dev, "Disabled by device hint\n");
+		return (ENXIO);
+	}
+
 	adapter = device_get_softc(dev);
 	adapter->dev = adapter->osdep.dev = dev;
 	EM_CORE_LOCK_INIT(adapter, device_get_nameunit(dev));
@@ -449,7 +459,7 @@ lem_attach(device_t dev)
 
         /* Sysctl for setting the interface flow control */
 	lem_set_flow_cntrl(adapter, "flow_control",
-	    "max number of rx packets to process",
+	    "flow control setting",
 	    &adapter->fc_setting, lem_fc_setting);
 
 	/*
@@ -646,6 +656,9 @@ lem_attach(device_t dev)
 	adapter->led_dev = led_create(lem_led_func, adapter,
 	    device_get_nameunit(dev));
 
+#ifdef DEV_NETMAP
+	lem_netmap_attach(adapter);
+#endif /* DEV_NETMAP */
 	INIT_DEBUGOUT("lem_attach: end");
 
 	return (0);
@@ -724,6 +737,9 @@ lem_detach(device_t dev)
 	callout_drain(&adapter->timer);
 	callout_drain(&adapter->tx_fifo_timer);
 
+#ifdef DEV_NETMAP
+	netmap_detach(ifp);
+#endif /* DEV_NETMAP */
 	lem_free_pci_resources(adapter);
 	bus_generic_detach(dev);
 	if_free(ifp);
@@ -880,11 +896,12 @@ static int
 lem_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 {
 	struct adapter	*adapter = ifp->if_softc;
-	struct ifreq *ifr = (struct ifreq *)data;
-#ifdef INET
-	struct ifaddr *ifa = (struct ifaddr *)data;
+	struct ifreq	*ifr = (struct ifreq *)data;
+#if defined(INET) || defined(INET6)
+	struct ifaddr	*ifa = (struct ifaddr *)data;
 #endif
-	int error = 0;
+	bool		avoid_reset = FALSE;
+	int		error = 0;
 
 	if (adapter->in_detach)
 		return (error);
@@ -892,23 +909,26 @@ lem_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 	switch (command) {
 	case SIOCSIFADDR:
 #ifdef INET
-		if (ifa->ifa_addr->sa_family == AF_INET) {
-			/*
-			 * XXX
-			 * Since resetting hardware takes a very long time
-			 * and results in link renegotiation we only
-			 * initialize the hardware only when it is absolutely
-			 * required.
-			 */
+		if (ifa->ifa_addr->sa_family == AF_INET)
+			avoid_reset = TRUE;
+#endif
+#ifdef INET6
+		if (ifa->ifa_addr->sa_family == AF_INET6)
+			avoid_reset = TRUE;
+#endif
+		/*
+		** Calling init results in link renegotiation,
+		** so we avoid doing it when possible.
+		*/
+		if (avoid_reset) {
 			ifp->if_flags |= IFF_UP;
-			if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
-				EM_CORE_LOCK(adapter);
-				lem_init_locked(adapter);
-				EM_CORE_UNLOCK(adapter);
-			}
-			arp_ifinit(ifp, ifa);
-		} else
+			if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
+				lem_init(adapter);
+#ifdef INET
+			if (!(ifp->if_flags & IFF_NOARP))
+				arp_ifinit(ifp, ifa);
 #endif
+		} else
 			error = ether_ioctl(ifp, command, data);
 		break;
 	case SIOCSIFMTU:
@@ -1207,9 +1227,6 @@ lem_init_locked(struct adapter *adapter)
 	/* AMT based hardware can now take control from firmware */
 	if (adapter->has_manage && adapter->has_amt)
 		lem_get_hw_control(adapter);
-
-	/* Don't reset the phy next time init gets called */
-	adapter->hw.phy.reset_disable = TRUE;
 }
 
 static void
@@ -1508,11 +1525,6 @@ lem_media_change(struct ifnet *ifp)
 		device_printf(adapter->dev, "Unsupported media type\n");
 	}
 
-	/* As the speed/duplex settings my have changed we need to
-	 * reset the PHY.
-	 */
-	adapter->hw.phy.reset_disable = FALSE;
-
 	lem_init_locked(adapter);
 	EM_CORE_UNLOCK(adapter);
 
@@ -2637,6 +2649,11 @@ static void
 lem_setup_transmit_structures(struct adapter *adapter)
 {
 	struct em_buffer *tx_buffer;
+#ifdef DEV_NETMAP
+	/* we are already locked */
+	struct netmap_adapter *na = NA(adapter->ifp);
+	struct netmap_slot *slot = netmap_reset(na, NR_TX, 0, 0);
+#endif /* DEV_NETMAP */
 
 	/* Clear the old ring contents */
 	bzero(adapter->tx_desc_base,
@@ -2650,6 +2667,22 @@ lem_setup_transmit_structures(struct adapter *adapter)
 		bus_dmamap_unload(adapter->txtag, tx_buffer->map);
 		m_freem(tx_buffer->m_head);
 		tx_buffer->m_head = NULL;
+#ifdef DEV_NETMAP
+		if (slot) {
+			/* slot si is mapped to the i-th NIC-ring entry */
+			int si = i + na->tx_rings[0].nkr_hwofs;
+			void *addr;
+
+			if (si > na->num_tx_desc)
+				si -= na->num_tx_desc;
+			addr = NMB(slot + si);
+			adapter->tx_desc_base[si].buffer_addr =
+			    htole64(vtophys(addr));
+			/* reload the map for netmap mode */
+			netmap_load_map(adapter->txtag,
+			    tx_buffer->map, addr, na->buff_size);
+		}
+#endif /* DEV_NETMAP */
 		tx_buffer->next_eop = -1;
 	}
 
@@ -2951,6 +2984,12 @@ lem_txeof(struct adapter *adapter)
 
 	EM_TX_LOCK_ASSERT(adapter);
 
+#ifdef DEV_NETMAP
+	if (ifp->if_capenable & IFCAP_NETMAP) {
+		selwakeuppri(&NA(ifp)->tx_rings[0].si, PI_NET);
+		return;
+	}
+#endif /* DEV_NETMAP */
         if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
                 return;
 
@@ -3181,6 +3220,11 @@ lem_setup_receive_structures(struct adapter *adapter)
 {
 	struct em_buffer *rx_buffer;
 	int i, error;
+#ifdef DEV_NETMAP
+	/* we are already under lock */
+	struct netmap_adapter *na = NA(adapter->ifp);
+	struct netmap_slot *slot = netmap_reset(na, NR_RX, 0, 0);
+#endif
 
 	/* Reset descriptor ring */
 	bzero(adapter->rx_desc_base,
@@ -3200,6 +3244,23 @@ lem_setup_receive_structures(struct adapter *adapter)
 
 	/* Allocate new ones. */
 	for (i = 0; i < adapter->num_rx_desc; i++) {
+#ifdef DEV_NETMAP
+		if (slot) {
+			/* slot si is mapped to the i-th NIC-ring entry */
+			int si = i + na->rx_rings[0].nkr_hwofs;
+			void *addr;
+
+			if (si > na->num_rx_desc)
+				si -= na->num_rx_desc;
+			addr = NMB(slot + si);
+			netmap_load_map(adapter->rxtag,
+			    rx_buffer->map, addr, na->buff_size);
+			/* Update descriptor */
+			adapter->rx_desc_base[i].buffer_addr =
+			    htole64(vtophys(addr));
+			continue;
+		}
+#endif /* DEV_NETMAP */
 		error = lem_get_buf(adapter, i);
 		if (error)
                         return (error);
@@ -3324,6 +3385,18 @@ lem_initialize_receive_unit(struct adapter *adapter)
 	 * Tail Descriptor Pointers
 	 */
 	E1000_WRITE_REG(&adapter->hw, E1000_RDH(0), 0);
+#ifdef DEV_NETMAP
+	/* preserve buffers already made available to clients */
+	if (ifp->if_capenable & IFCAP_NETMAP) {
+		struct netmap_adapter *na = NA(adapter->ifp);
+		struct netmap_kring *kring = &na->rx_rings[0];
+		int t = na->num_rx_desc - 1 - kring->nr_hwavail;
+
+		if (t >= na->num_rx_desc)
+			t -= na->num_rx_desc;
+		E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), t);
+	} else
+#endif /* DEV_NETMAP */
 	E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), adapter->num_rx_desc - 1);
 
 	return;
@@ -3407,6 +3480,14 @@ lem_rxeof(struct adapter *adapter, int count, int *done)
 	bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map,
 	    BUS_DMASYNC_POSTREAD);
 
+#ifdef DEV_NETMAP
+	if (ifp->if_capenable & IFCAP_NETMAP) {
+		selwakeuppri(&NA(ifp)->rx_rings[0].si, PI_NET);
+		EM_RX_UNLOCK(adapter);
+		return (0);
+	}
+#endif /* DEV_NETMAP */
+
 	if (!((current_desc->status) & E1000_RXD_STAT_DD)) {
 		if (done != NULL)
 			*done = rx_sent;
diff --git a/sys/dev/e1000/if_lem.h b/sys/dev/e1000/if_lem.h
index 46ebad1..c1973e5 100644
--- a/sys/dev/e1000/if_lem.h
+++ b/sys/dev/e1000/if_lem.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -217,7 +217,7 @@
 #define EM_BAR_MEM_TYPE_64BIT	0x00000004
 #define EM_MSIX_BAR		3	/* On 82575 */
 
-#if !defined(SYSCTL_ADD_UQUAD)
+#if __FreeBSD_version < 900000
 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
 #endif
 
diff --git a/sys/dev/ed/if_ed.c b/sys/dev/ed/if_ed.c
index b0e1c0c..80446a6 100644
--- a/sys/dev/ed/if_ed.c
+++ b/sys/dev/ed/if_ed.c
@@ -1709,12 +1709,19 @@ ed_shmem_write_mbufs(struct ed_softc *sc, struct mbuf *m, bus_size_t dst)
 			break;
 		}
 	}
-	for (len = 0; m != 0; m = m->m_next) {
-		if (sc->isa16bit)
-			bus_space_write_region_2(sc->mem_bst,
-			    sc->mem_bsh, dst,
-			    mtod(m, uint16_t *), (m->m_len + 1)/ 2);
-		else
+	for (len = 0; m != NULL; m = m->m_next) {
+		if (m->m_len == 0)
+			continue;
+		if (sc->isa16bit) {
+			if (m->m_len > 1)
+				bus_space_write_region_2(sc->mem_bst,
+				    sc->mem_bsh, dst,
+				    mtod(m, uint16_t *), m->m_len / 2);
+			if ((m->m_len & 1) != 0)
+				bus_space_write_1(sc->mem_bst, sc->mem_bsh,
+				    dst + m->m_len - 1,
+				    *(mtod(m, uint8_t *) + m->m_len - 1));
+		} else
 			bus_space_write_region_1(sc->mem_bst,
 			    sc->mem_bsh, dst,
 			    mtod(m, uint8_t *), m->m_len);
diff --git a/sys/dev/eisa/eisaconf.c b/sys/dev/eisa/eisaconf.c
index 689efb6..8ec3419 100644
--- a/sys/dev/eisa/eisaconf.c
+++ b/sys/dev/eisa/eisaconf.c
@@ -557,7 +557,6 @@ static device_method_t eisa_methods[] = {
 	DEVMETHOD(bus_probe_nomatch,	eisa_probe_nomatch),
 	DEVMETHOD(bus_read_ivar,	eisa_read_ivar),
 	DEVMETHOD(bus_write_ivar,	eisa_write_ivar),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
 	DEVMETHOD(bus_alloc_resource,	eisa_alloc_resource),
 	DEVMETHOD(bus_release_resource,	eisa_release_resource),
 	DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
@@ -570,7 +569,7 @@ static device_method_t eisa_methods[] = {
 	DEVMETHOD(eisa_add_iospace,	eisa_add_iospace_m),
 	DEVMETHOD(eisa_add_mspace,	eisa_add_mspace_m),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t eisa_driver = {
diff --git a/sys/dev/esp/esp_pci.c b/sys/dev/esp/esp_pci.c
index 2fa2030..cd88f6b 100644
--- a/sys/dev/esp/esp_pci.c
+++ b/sys/dev/esp/esp_pci.c
@@ -146,7 +146,7 @@ static device_method_t esp_pci_methods[] = {
 	DEVMETHOD(device_suspend,	esp_pci_suspend),
 	DEVMETHOD(device_resume,	esp_pci_resume),
 
-	KOBJMETHOD_END
+	DEVMETHOD_END
 };
 
 static driver_t esp_pci_driver = {
diff --git a/sys/dev/esp/esp_sbus.c b/sys/dev/esp/esp_sbus.c
index c1ff021..01ffb8d 100644
--- a/sys/dev/esp/esp_sbus.c
+++ b/sys/dev/esp/esp_sbus.c
@@ -117,7 +117,7 @@ static device_method_t esp_dma_methods[] = {
 	DEVMETHOD(device_suspend,	esp_suspend),
 	DEVMETHOD(device_resume,	esp_resume),
 
-	KOBJMETHOD_END
+	DEVMETHOD_END
 };
 
 static driver_t esp_dma_driver = {
@@ -136,7 +136,7 @@ static device_method_t esp_sbus_methods[] = {
 	DEVMETHOD(device_suspend,	esp_suspend),
 	DEVMETHOD(device_resume,	esp_resume),
 
-	KOBJMETHOD_END	
+	DEVMETHOD_END
 };
 
 static driver_t esp_sbus_driver = {
diff --git a/sys/dev/esp/ncr53c9x.c b/sys/dev/esp/ncr53c9x.c
index b9d4990..93ad337 100644
--- a/sys/dev/esp/ncr53c9x.c
+++ b/sys/dev/esp/ncr53c9x.c
@@ -316,7 +316,7 @@ ncr53c9x_attach(struct ncr53c9x_softc *sc)
 	 * The recommended timeout is 250ms.  This register is loaded
 	 * with a value calculated as follows, from the docs:
 	 *
-	 *		(timout period) x (CLK frequency)
+	 *		(timeout period) x (CLK frequency)
 	 *	reg = -------------------------------------
 	 *		 8192 x (Clock Conversion Factor)
 	 *
diff --git a/sys/dev/et/if_et.c b/sys/dev/et/if_et.c
index 539224a..426ae88 100644
--- a/sys/dev/et/if_et.c
+++ b/sys/dev/et/if_et.c
@@ -87,6 +87,8 @@ static int	et_probe(device_t);
 static int	et_attach(device_t);
 static int	et_detach(device_t);
 static int	et_shutdown(device_t);
+static int	et_suspend(device_t);
+static int	et_resume(device_t);
 
 static int	et_miibus_readreg(device_t, int, int);
 static int	et_miibus_writereg(device_t, int, int, int);
@@ -97,7 +99,7 @@ static void	et_init(void *);
 static int	et_ioctl(struct ifnet *, u_long, caddr_t);
 static void	et_start_locked(struct ifnet *);
 static void	et_start(struct ifnet *);
-static void	et_watchdog(struct et_softc *);
+static int	et_watchdog(struct et_softc *);
 static int	et_ifmedia_upd_locked(struct ifnet *);
 static int	et_ifmedia_upd(struct ifnet *);
 static void	et_ifmedia_sts(struct ifnet *, struct ifmediareq *);
@@ -107,29 +109,25 @@ static int	et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS);
 static int	et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS);
 
 static void	et_intr(void *);
-static void	et_enable_intrs(struct et_softc *, uint32_t);
-static void	et_disable_intrs(struct et_softc *);
 static void	et_rxeof(struct et_softc *);
 static void	et_txeof(struct et_softc *);
 
-static int	et_dma_alloc(device_t);
-static void	et_dma_free(device_t);
-static int	et_dma_mem_create(device_t, bus_size_t, bus_dma_tag_t *,
-				  void **, bus_addr_t *, bus_dmamap_t *);
-static void	et_dma_mem_destroy(bus_dma_tag_t, void *, bus_dmamap_t);
-static int	et_dma_mbuf_create(device_t);
-static void	et_dma_mbuf_destroy(device_t, int, const int[]);
-static void	et_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
-static void	et_dma_buf_addr(void *, bus_dma_segment_t *, int,
-				bus_size_t, int);
-static int	et_init_tx_ring(struct et_softc *);
+static int	et_dma_alloc(struct et_softc *);
+static void	et_dma_free(struct et_softc *);
+static void	et_dma_map_addr(void *, bus_dma_segment_t *, int, int);
+static int	et_dma_ring_alloc(struct et_softc *, bus_size_t, bus_size_t,
+		    bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *,
+		    const char *);
+static void	et_dma_ring_free(struct et_softc *, bus_dma_tag_t *, uint8_t **,
+		    bus_dmamap_t *);
+static void	et_init_tx_ring(struct et_softc *);
 static int	et_init_rx_ring(struct et_softc *);
 static void	et_free_tx_ring(struct et_softc *);
 static void	et_free_rx_ring(struct et_softc *);
 static int	et_encap(struct et_softc *, struct mbuf **);
-static int	et_newbuf(struct et_rxbuf_data *, int, int, int);
-static int	et_newbuf_cluster(struct et_rxbuf_data *, int, int);
-static int	et_newbuf_hdr(struct et_rxbuf_data *, int, int);
+static int	et_newbuf_cluster(struct et_rxbuf_data *, int);
+static int	et_newbuf_hdr(struct et_rxbuf_data *, int);
+static void	et_rxbuf_discard(struct et_rxbuf_data *, int);
 
 static void	et_stop(struct et_softc *);
 static int	et_chip_init(struct et_softc *);
@@ -143,14 +141,12 @@ static int	et_start_rxdma(struct et_softc *);
 static int	et_start_txdma(struct et_softc *);
 static int	et_stop_rxdma(struct et_softc *);
 static int	et_stop_txdma(struct et_softc *);
-static int	et_enable_txrx(struct et_softc *, int);
 static void	et_reset(struct et_softc *);
 static int	et_bus_config(struct et_softc *);
 static void	et_get_eaddr(device_t, uint8_t[]);
 static void	et_setmulti(struct et_softc *);
 static void	et_tick(void *);
-static void	et_setmedia(struct et_softc *);
-static void	et_setup_rxdesc(struct et_rxbuf_data *, int, bus_addr_t);
+static void	et_stats_update(struct et_softc *);
 
 static const struct et_dev {
 	uint16_t	vid;
@@ -169,15 +165,14 @@ static device_method_t et_methods[] = {
 	DEVMETHOD(device_attach,	et_attach),
 	DEVMETHOD(device_detach,	et_detach),
 	DEVMETHOD(device_shutdown,	et_shutdown),
-
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
+	DEVMETHOD(device_suspend,	et_suspend),
+	DEVMETHOD(device_resume,	et_resume),
 
 	DEVMETHOD(miibus_readreg,	et_miibus_readreg),
 	DEVMETHOD(miibus_writereg,	et_miibus_writereg),
 	DEVMETHOD(miibus_statchg,	et_miibus_statchg),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t et_driver = {
@@ -201,18 +196,6 @@ TUNABLE_INT("hw.et.rx_intr_npkts", &et_rx_intr_npkts);
 TUNABLE_INT("hw.et.rx_intr_delay", &et_rx_intr_delay);
 TUNABLE_INT("hw.et.tx_intr_nsegs", &et_tx_intr_nsegs);
 
-struct et_bsize {
-	int		bufsize;
-	et_newbuf_t	newbuf;
-};
-
-static const struct et_bsize	et_bufsize_std[ET_RX_NRING] = {
-	{ .bufsize = ET_RXDMA_CTRL_RING0_128,
-	  .newbuf = et_newbuf_hdr },
-	{ .bufsize = ET_RXDMA_CTRL_RING1_2048,
-	  .newbuf = et_newbuf_cluster },
-};
-
 static int
 et_probe(device_t dev)
 {
@@ -225,7 +208,7 @@ et_probe(device_t dev)
 	for (d = et_devices; d->desc != NULL; ++d) {
 		if (vid == d->vid && did == d->did) {
 			device_set_desc(dev, d->desc);
-			return (0);
+			return (BUS_PROBE_DEFAULT);
 		}
 	}
 	return (ENXIO);
@@ -237,12 +220,14 @@ et_attach(device_t dev)
 	struct et_softc *sc;
 	struct ifnet *ifp;
 	uint8_t eaddr[ETHER_ADDR_LEN];
+	uint32_t pmcfg;
 	int cap, error, msic;
 
 	sc = device_get_softc(dev);
 	sc->dev = dev;
 	mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
 	    MTX_DEF);
+	callout_init_mtx(&sc->sc_tick, &sc->sc_mtx, 0);
 
 	ifp = sc->ifp = if_alloc(IFT_ETHER);
 	if (ifp == NULL) {
@@ -265,9 +250,9 @@ et_attach(device_t dev)
 	/*
 	 * Allocate IO memory
 	 */
-	sc->sc_mem_rid = ET_PCIR_BAR;
+	sc->sc_mem_rid = PCIR_BAR(0);
 	sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
-						&sc->sc_mem_rid, RF_ACTIVE);
+	    &sc->sc_mem_rid, RF_ACTIVE);
 	if (sc->sc_mem_res == NULL) {
 		device_printf(dev, "can't allocate IO memory\n");
 		return (ENXIO);
@@ -311,20 +296,24 @@ et_attach(device_t dev)
 		goto fail;
 	}
 
+	if (pci_get_device(dev) == PCI_PRODUCT_LUCENT_ET1310_FAST)
+		sc->sc_flags |= ET_FLAG_FASTETHER;
+
 	error = et_bus_config(sc);
 	if (error)
 		goto fail;
 
 	et_get_eaddr(dev, eaddr);
 
-	CSR_WRITE_4(sc, ET_PM,
-		    ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE);
+	/* Take PHY out of COMA and enable clocks. */
+	pmcfg = ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE;
+	if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0)
+		pmcfg |= EM_PM_GIGEPHY_ENB;
+	CSR_WRITE_4(sc, ET_PM, pmcfg);
 
 	et_reset(sc);
 
-	et_disable_intrs(sc);
-
-	error = et_dma_alloc(dev);
+	error = et_dma_alloc(sc);
 	if (error)
 		goto fail;
 
@@ -334,23 +323,26 @@ et_attach(device_t dev)
 	ifp->if_init = et_init;
 	ifp->if_ioctl = et_ioctl;
 	ifp->if_start = et_start;
-	ifp->if_mtu = ETHERMTU;
 	ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_VLAN_MTU;
 	ifp->if_capenable = ifp->if_capabilities;
-	IFQ_SET_MAXLEN(&ifp->if_snd, ET_TX_NDESC);
+	ifp->if_snd.ifq_drv_maxlen = ET_TX_NDESC - 1;
+	IFQ_SET_MAXLEN(&ifp->if_snd, ET_TX_NDESC - 1);
 	IFQ_SET_READY(&ifp->if_snd);
 
 	et_chip_attach(sc);
 
 	error = mii_attach(dev, &sc->sc_miibus, ifp, et_ifmedia_upd,
-	    et_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
+	    et_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
+	    MIIF_DOPAUSE);
 	if (error) {
 		device_printf(dev, "attaching PHYs failed\n");
 		goto fail;
 	}
 
 	ether_ifattach(ifp, eaddr);
-	callout_init_mtx(&sc->sc_tick, &sc->sc_mtx, 0);
+
+	/* Tell the upper layer(s) we support long frames. */
+	ifp->if_hdrlen = sizeof(struct ether_vlan_header);
 
 	error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_NET | INTR_MPSAFE,
 	    NULL, et_intr, sc, &sc->sc_irq_handle);
@@ -374,36 +366,32 @@ et_detach(device_t dev)
 	struct et_softc *sc = device_get_softc(dev);
 
 	if (device_is_attached(dev)) {
-		struct ifnet *ifp = sc->ifp;
-
+		ether_ifdetach(sc->ifp);
 		ET_LOCK(sc);
 		et_stop(sc);
-		bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle);
 		ET_UNLOCK(sc);
-
-		ether_ifdetach(ifp);
+		callout_drain(&sc->sc_tick);
 	}
 
 	if (sc->sc_miibus != NULL)
 		device_delete_child(dev, sc->sc_miibus);
 	bus_generic_detach(dev);
 
-	if (sc->sc_irq_res != NULL) {
-		bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
-				     sc->sc_irq_res);
-	}
+	if (sc->sc_irq_handle != NULL)
+		bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle);
+	if (sc->sc_irq_res != NULL)
+		bus_release_resource(dev, SYS_RES_IRQ,
+		    rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
 	if ((sc->sc_flags & ET_FLAG_MSI) != 0)
 		pci_release_msi(dev);
-
-	if (sc->sc_mem_res != NULL) {
-		bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
-				     sc->sc_mem_res);
-	}
+	if (sc->sc_mem_res != NULL)
+		bus_release_resource(dev, SYS_RES_MEMORY,
+		    rman_get_rid(sc->sc_mem_res), sc->sc_mem_res);
 
 	if (sc->ifp != NULL)
 		if_free(sc->ifp);
 
-	et_dma_free(dev);
+	et_dma_free(sc);
 
 	mtx_destroy(&sc->sc_mtx);
 
@@ -506,7 +494,100 @@ et_miibus_writereg(device_t dev, int phy, int reg, int val0)
 static void
 et_miibus_statchg(device_t dev)
 {
-	et_setmedia(device_get_softc(dev));
+	struct et_softc *sc;
+	struct mii_data *mii;
+	struct ifnet *ifp;
+	uint32_t cfg1, cfg2, ctrl;
+	int i;
+
+	sc = device_get_softc(dev);
+
+	mii = device_get_softc(sc->sc_miibus);
+	ifp = sc->ifp;
+	if (mii == NULL || ifp == NULL ||
+	    (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
+		return;
+
+	sc->sc_flags &= ~ET_FLAG_LINK;
+	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
+	    (IFM_ACTIVE | IFM_AVALID)) {
+		switch (IFM_SUBTYPE(mii->mii_media_active)) {
+		case IFM_10_T:
+		case IFM_100_TX:
+			sc->sc_flags |= ET_FLAG_LINK;
+			break;
+		case IFM_1000_T:
+			if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0)
+				sc->sc_flags |= ET_FLAG_LINK;
+			break;
+		}
+	}
+
+	/* XXX Stop TX/RX MAC? */
+	if ((sc->sc_flags & ET_FLAG_LINK) == 0)
+		return;
+
+	/* Program MACs with resolved speed/duplex/flow-control. */
+	ctrl = CSR_READ_4(sc, ET_MAC_CTRL);
+	ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII);
+	cfg1 = CSR_READ_4(sc, ET_MAC_CFG1);
+	cfg1 &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW |
+	    ET_MAC_CFG1_LOOPBACK);
+	cfg2 = CSR_READ_4(sc, ET_MAC_CFG2);
+	cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII |
+	    ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM);
+	cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC |
+	    ((7 << ET_MAC_CFG2_PREAMBLE_LEN_SHIFT) &
+	    ET_MAC_CFG2_PREAMBLE_LEN_MASK);
+
+	if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
+		cfg2 |= ET_MAC_CFG2_MODE_GMII;
+	else {
+		cfg2 |= ET_MAC_CFG2_MODE_MII;
+		ctrl |= ET_MAC_CTRL_MODE_MII;
+	}
+
+	if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) {
+		cfg2 |= ET_MAC_CFG2_FDX;
+		/*
+		 * Controller lacks automatic TX pause frame
+		 * generation so it should be handled by driver.
+		 * Even though driver can send pause frame with
+		 * arbitrary pause time, controller does not
+		 * provide a way that tells how many free RX
+		 * buffers are available in controller.  This
+		 * limitation makes it hard to generate XON frame
+		 * in time on driver side so don't enable TX flow
+		 * control.
+		 */
+#ifdef notyet
+		if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE)
+			cfg1 |= ET_MAC_CFG1_TXFLOW;
+#endif
+		if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE)
+			cfg1 |= ET_MAC_CFG1_RXFLOW;
+	} else
+		ctrl |= ET_MAC_CTRL_GHDX;
+
+	CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl);
+	CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2);
+	cfg1 |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN;
+	CSR_WRITE_4(sc, ET_MAC_CFG1, cfg1);
+
+#define NRETRY	50
+
+	for (i = 0; i < NRETRY; ++i) {
+		cfg1 = CSR_READ_4(sc, ET_MAC_CFG1);
+		if ((cfg1 & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) ==
+		    (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN))
+			break;
+		DELAY(100);
+	}
+	if (i == NRETRY)
+		if_printf(ifp, "can't enable RX/TX\n");
+	sc->sc_flags |= ET_FLAG_TXRX_ENABLED;
+
+#undef NRETRY
 }
 
 static int
@@ -537,10 +618,17 @@ et_ifmedia_upd(struct ifnet *ifp)
 static void
 et_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 {
-	struct et_softc *sc = ifp->if_softc;
-	struct mii_data *mii = device_get_softc(sc->sc_miibus);
+	struct et_softc *sc;
+	struct mii_data *mii;
 
+	sc = ifp->if_softc;
 	ET_LOCK(sc);
+	if ((ifp->if_flags & IFF_UP) == 0) {
+		ET_UNLOCK(sc);
+		return;
+	}
+
+	mii = device_get_softc(sc->sc_miibus);
 	mii_pollstat(mii);
 	ifmr->ifm_active = mii->mii_media_active;
 	ifmr->ifm_status = mii->mii_media_status;
@@ -555,17 +643,20 @@ et_stop(struct et_softc *sc)
 	ET_LOCK_ASSERT(sc);
 
 	callout_stop(&sc->sc_tick);
+	/* Disable interrupts. */
+	CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff);
+
+	CSR_WRITE_4(sc, ET_MAC_CFG1, CSR_READ_4(sc, ET_MAC_CFG1) & ~(
+	    ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN));
+	DELAY(100);
 
 	et_stop_rxdma(sc);
 	et_stop_txdma(sc);
-
-	et_disable_intrs(sc);
+	et_stats_update(sc);
 
 	et_free_tx_ring(sc);
 	et_free_rx_ring(sc);
 
-	et_reset(sc);
-
 	sc->sc_tx = 0;
 	sc->sc_tx_intr = 0;
 	sc->sc_flags &= ~ET_FLAG_TXRX_ENABLED;
@@ -643,12 +734,7 @@ et_bus_config(struct et_softc *sc)
 	/*
 	 * Set max read request size to 2048 bytes
 	 */
-	val = pci_read_config(sc->dev,
-	    sc->sc_expcap + PCIR_EXPRESS_DEVICE_CTL, 2);
-	val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST;
-	val |= ET_PCIV_DEVICE_CTRL_RRSZ_2K;
-	pci_write_config(sc->dev,
-	    sc->sc_expcap + PCIR_EXPRESS_DEVICE_CTL, val, 2);
+	pci_set_max_read_req(sc->dev, 2048);
 
 	return (0);
 }
@@ -685,249 +771,254 @@ et_reset(struct et_softc *sc)
 		    ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC |
 		    ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC);
 	CSR_WRITE_4(sc, ET_MAC_CFG1, 0);
-}
-
-static void
-et_disable_intrs(struct et_softc *sc)
-{
+	/* Disable interrupts. */
 	CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff);
 }
 
+struct et_dmamap_arg {
+	bus_addr_t	et_busaddr;
+};
+
 static void
-et_enable_intrs(struct et_softc *sc, uint32_t intrs)
+et_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 {
-	CSR_WRITE_4(sc, ET_INTR_MASK, ~intrs);
+	struct et_dmamap_arg *ctx;
+
+	if (error)
+		return;
+
+	KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg));
+
+	ctx = arg;
+	ctx->et_busaddr = segs->ds_addr;
 }
 
 static int
-et_dma_alloc(device_t dev)
+et_dma_ring_alloc(struct et_softc *sc, bus_size_t alignment, bus_size_t maxsize,
+    bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, bus_addr_t *paddr,
+    const char *msg)
 {
-	struct et_softc *sc = device_get_softc(dev);
-	struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
-	struct et_txstatus_data *txsd = &sc->sc_tx_status;
-	struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring;
-	struct et_rxstatus_data *rxsd = &sc->sc_rx_status;
-	int i, error;
+	struct et_dmamap_arg ctx;
+	int error;
 
-	/*
-	 * Create top level DMA tag
-	 */
-	error = bus_dma_tag_create(NULL, 1, 0,
-				   BUS_SPACE_MAXADDR_32BIT,
-				   BUS_SPACE_MAXADDR,
-				   NULL, NULL,
-				   MAXBSIZE,
-				   BUS_SPACE_UNRESTRICTED,
-				   BUS_SPACE_MAXSIZE_32BIT,
-				   0, NULL, NULL, &sc->sc_dtag);
-	if (error) {
-		device_printf(dev, "can't create DMA tag\n");
+	error = bus_dma_tag_create(sc->sc_dtag, alignment, 0, BUS_SPACE_MAXADDR,
+	    BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1, maxsize, 0, NULL, NULL,
+	    tag);
+	if (error != 0) {
+		device_printf(sc->dev, "could not create %s dma tag\n", msg);
 		return (error);
 	}
-
-	/*
-	 * Create TX ring DMA stuffs
-	 */
-	error = et_dma_mem_create(dev, ET_TX_RING_SIZE, &tx_ring->tr_dtag,
-				  (void **)&tx_ring->tr_desc,
-				  &tx_ring->tr_paddr, &tx_ring->tr_dmap);
-	if (error) {
-		device_printf(dev, "can't create TX ring DMA stuffs\n");
+	/* Allocate DMA'able memory for ring. */
+	error = bus_dmamem_alloc(*tag, (void **)ring,
+	    BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
+	if (error != 0) {
+		device_printf(sc->dev,
+		    "could not allocate DMA'able memory for %s\n", msg);
 		return (error);
 	}
-
-	/*
-	 * Create TX status DMA stuffs
-	 */
-	error = et_dma_mem_create(dev, sizeof(uint32_t), &txsd->txsd_dtag,
-				  (void **)&txsd->txsd_status,
-				  &txsd->txsd_paddr, &txsd->txsd_dmap);
-	if (error) {
-		device_printf(dev, "can't create TX status DMA stuffs\n");
+	/* Load the address of the ring. */
+	ctx.et_busaddr = 0;
+	error = bus_dmamap_load(*tag, *map, *ring, maxsize, et_dma_map_addr,
+	    &ctx, BUS_DMA_NOWAIT);
+	if (error != 0) {
+		device_printf(sc->dev,
+		    "could not load DMA'able memory for %s\n", msg);
 		return (error);
 	}
+	*paddr = ctx.et_busaddr;
+	return (0);
+}
 
-	/*
-	 * Create DMA stuffs for RX rings
-	 */
-	for (i = 0; i < ET_RX_NRING; ++i) {
-		static const uint32_t rx_ring_posreg[ET_RX_NRING] =
-		{ ET_RX_RING0_POS, ET_RX_RING1_POS };
-
-		struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i];
+static void
+et_dma_ring_free(struct et_softc *sc, bus_dma_tag_t *tag, uint8_t **ring,
+    bus_dmamap_t *map)
+{
 
-		error = et_dma_mem_create(dev, ET_RX_RING_SIZE,
-					  &rx_ring->rr_dtag,
-					  (void **)&rx_ring->rr_desc,
-					  &rx_ring->rr_paddr,
-					  &rx_ring->rr_dmap);
-		if (error) {
-			device_printf(dev, "can't create DMA stuffs for "
-				      "the %d RX ring\n", i);
-			return (error);
-		}
-		rx_ring->rr_posreg = rx_ring_posreg[i];
+	if (*map != NULL)
+		bus_dmamap_unload(*tag, *map);
+	if (*map != NULL && *ring != NULL) {
+		bus_dmamem_free(*tag, *ring, *map);
+		*ring = NULL;
+		*map = NULL;
 	}
-
-	/*
-	 * Create RX stat ring DMA stuffs
-	 */
-	error = et_dma_mem_create(dev, ET_RXSTAT_RING_SIZE,
-				  &rxst_ring->rsr_dtag,
-				  (void **)&rxst_ring->rsr_stat,
-				  &rxst_ring->rsr_paddr, &rxst_ring->rsr_dmap);
-	if (error) {
-		device_printf(dev, "can't create RX stat ring DMA stuffs\n");
-		return (error);
+	if (*tag) {
+		bus_dma_tag_destroy(*tag);
+		*tag = NULL;
 	}
+}
 
-	/*
-	 * Create RX status DMA stuffs
-	 */
-	error = et_dma_mem_create(dev, sizeof(struct et_rxstatus),
-				  &rxsd->rxsd_dtag,
-				  (void **)&rxsd->rxsd_status,
-				  &rxsd->rxsd_paddr, &rxsd->rxsd_dmap);
-	if (error) {
-		device_printf(dev, "can't create RX status DMA stuffs\n");
+static int
+et_dma_alloc(struct et_softc *sc)
+{
+	struct et_txdesc_ring *tx_ring;
+	struct et_rxdesc_ring *rx_ring;
+	struct et_rxstat_ring *rxst_ring;
+	struct et_rxstatus_data *rxsd;
+	struct et_rxbuf_data *rbd;
+        struct et_txbuf_data *tbd;
+	struct et_txstatus_data *txsd;
+	int i, error;
+
+	error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
+	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
+	    BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
+	    &sc->sc_dtag);
+	if (error != 0) {
+		device_printf(sc->dev, "could not allocate parent dma tag\n");
 		return (error);
 	}
 
-	/*
-	 * Create mbuf DMA stuffs
-	 */
-	error = et_dma_mbuf_create(dev);
+	/* TX ring. */
+	tx_ring = &sc->sc_tx_ring;
+	error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_TX_RING_SIZE,
+	    &tx_ring->tr_dtag, (uint8_t **)&tx_ring->tr_desc, &tx_ring->tr_dmap,
+	    &tx_ring->tr_paddr, "TX ring");
 	if (error)
 		return (error);
 
-	return (0);
-}
+	/* TX status block. */
+	txsd = &sc->sc_tx_status;
+	error = et_dma_ring_alloc(sc, ET_STATUS_ALIGN, sizeof(uint32_t),
+	    &txsd->txsd_dtag, (uint8_t **)&txsd->txsd_status, &txsd->txsd_dmap,
+	    &txsd->txsd_paddr, "TX status block");
+	if (error)
+		return (error);
 
-static void
-et_dma_free(device_t dev)
-{
-	struct et_softc *sc = device_get_softc(dev);
-	struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
-	struct et_txstatus_data *txsd = &sc->sc_tx_status;
-	struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring;
-	struct et_rxstatus_data *rxsd = &sc->sc_rx_status;
-	int i, rx_done[ET_RX_NRING];
+	/* RX ring 0, used as to recive small sized frames. */
+	rx_ring = &sc->sc_rx_ring[0];
+	error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RX_RING_SIZE,
+	    &rx_ring->rr_dtag, (uint8_t **)&rx_ring->rr_desc, &rx_ring->rr_dmap,
+	    &rx_ring->rr_paddr, "RX ring 0");
+	rx_ring->rr_posreg = ET_RX_RING0_POS;
+	if (error)
+		return (error);
 
-	/*
-	 * Destroy TX ring DMA stuffs
-	 */
-	et_dma_mem_destroy(tx_ring->tr_dtag, tx_ring->tr_desc,
-			   tx_ring->tr_dmap);
+	/* RX ring 1, used as to store normal sized frames. */
+	rx_ring = &sc->sc_rx_ring[1];
+	error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RX_RING_SIZE,
+	    &rx_ring->rr_dtag, (uint8_t **)&rx_ring->rr_desc, &rx_ring->rr_dmap,
+	    &rx_ring->rr_paddr, "RX ring 1");
+	rx_ring->rr_posreg = ET_RX_RING1_POS;
+	if (error)
+		return (error);
 
-	/*
-	 * Destroy TX status DMA stuffs
-	 */
-	et_dma_mem_destroy(txsd->txsd_dtag, txsd->txsd_status,
-			   txsd->txsd_dmap);
+	/* RX stat ring. */
+	rxst_ring = &sc->sc_rxstat_ring;
+	error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RXSTAT_RING_SIZE,
+	    &rxst_ring->rsr_dtag, (uint8_t **)&rxst_ring->rsr_stat,
+	    &rxst_ring->rsr_dmap, &rxst_ring->rsr_paddr, "RX stat ring");
+	if (error)
+		return (error);
 
-	/*
-	 * Destroy DMA stuffs for RX rings
-	 */
-	for (i = 0; i < ET_RX_NRING; ++i) {
-		struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i];
+	/* RX status block. */
+	rxsd = &sc->sc_rx_status;
+	error = et_dma_ring_alloc(sc, ET_STATUS_ALIGN,
+	    sizeof(struct et_rxstatus), &rxsd->rxsd_dtag,
+	    (uint8_t **)&rxsd->rxsd_status, &rxsd->rxsd_dmap,
+	    &rxsd->rxsd_paddr, "RX status block");
+	if (error)
+		return (error);
 
-		et_dma_mem_destroy(rx_ring->rr_dtag, rx_ring->rr_desc,
-				   rx_ring->rr_dmap);
+	/* Create parent DMA tag for mbufs. */
+	error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
+	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
+	    BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
+	    &sc->sc_mbuf_dtag);
+	if (error != 0) {
+		device_printf(sc->dev,
+		    "could not allocate parent dma tag for mbuf\n");
+		return (error);
 	}
 
-	/*
-	 * Destroy RX stat ring DMA stuffs
-	 */
-	et_dma_mem_destroy(rxst_ring->rsr_dtag, rxst_ring->rsr_stat,
-			   rxst_ring->rsr_dmap);
-
-	/*
-	 * Destroy RX status DMA stuffs
-	 */
-	et_dma_mem_destroy(rxsd->rxsd_dtag, rxsd->rxsd_status,
-			   rxsd->rxsd_dmap);
-
-	/*
-	 * Destroy mbuf DMA stuffs
-	 */
-	for (i = 0; i < ET_RX_NRING; ++i)
-		rx_done[i] = ET_RX_NDESC;
-	et_dma_mbuf_destroy(dev, ET_TX_NDESC, rx_done);
-
-	/*
-	 * Destroy top level DMA tag
-	 */
-	if (sc->sc_dtag != NULL)
-		bus_dma_tag_destroy(sc->sc_dtag);
-}
+	/* Create DMA tag for mini RX mbufs to use RX ring 0. */
+	error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0,
+	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MHLEN, 1,
+	    MHLEN, 0, NULL, NULL, &sc->sc_rx_mini_tag);
+	if (error) {
+		device_printf(sc->dev, "could not create mini RX dma tag\n");
+		return (error);
+	}
 
-static int
-et_dma_mbuf_create(device_t dev)
-{
-	struct et_softc *sc = device_get_softc(dev);
-	struct et_txbuf_data *tbd = &sc->sc_tx_data;
-	int i, error, rx_done[ET_RX_NRING];
+	/* Create DMA tag for standard RX mbufs to use RX ring 1. */
+	error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0,
+	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
+	    MCLBYTES, 0, NULL, NULL, &sc->sc_rx_tag);
+	if (error) {
+		device_printf(sc->dev, "could not create RX dma tag\n");
+		return (error);
+	}
 
-	/*
-	 * Create mbuf DMA tag
-	 */
-	error = bus_dma_tag_create(sc->sc_dtag, 1, 0,
-				   BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
-				   NULL, NULL,
-				   ET_JUMBO_FRAMELEN, ET_NSEG_MAX,
-				   BUS_SPACE_MAXSIZE_32BIT,
-				   BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_mbuf_dtag);
+	/* Create DMA tag for TX mbufs. */
+	error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0,
+	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
+	    MCLBYTES * ET_NSEG_MAX, ET_NSEG_MAX, MCLBYTES, 0, NULL, NULL,
+	    &sc->sc_tx_tag);
 	if (error) {
-		device_printf(dev, "can't create mbuf DMA tag\n");
+		device_printf(sc->dev, "could not create TX dma tag\n");
 		return (error);
 	}
 
-	/*
-	 * Create spare DMA map for RX mbufs
-	 */
-	error = bus_dmamap_create(sc->sc_mbuf_dtag, 0, &sc->sc_mbuf_tmp_dmap);
+	/* Initialize RX ring 0. */
+	rbd = &sc->sc_rx_data[0];
+	rbd->rbd_bufsize = ET_RXDMA_CTRL_RING0_128;
+	rbd->rbd_newbuf = et_newbuf_hdr;
+	rbd->rbd_discard = et_rxbuf_discard;
+	rbd->rbd_softc = sc;
+	rbd->rbd_ring = &sc->sc_rx_ring[0];
+	/* Create DMA maps for mini RX buffers, ring 0. */
+	for (i = 0; i < ET_RX_NDESC; i++) {
+		error = bus_dmamap_create(sc->sc_rx_mini_tag, 0,
+		    &rbd->rbd_buf[i].rb_dmap);
+		if (error) {
+			device_printf(sc->dev,
+			    "could not create DMA map for mini RX mbufs\n");
+			return (error);
+		}
+	}
+
+	/* Create a spare DMA map for mini RX buffers, ring 0. */
+	error = bus_dmamap_create(sc->sc_rx_mini_tag, 0,
+	    &sc->sc_rx_mini_sparemap);
 	if (error) {
-		device_printf(dev, "can't create spare mbuf DMA map\n");
-		bus_dma_tag_destroy(sc->sc_mbuf_dtag);
-		sc->sc_mbuf_dtag = NULL;
+		device_printf(sc->dev,
+		    "could not create spare DMA map for mini RX mbuf\n");
 		return (error);
 	}
 
-	/*
-	 * Create DMA maps for RX mbufs
-	 */
-	bzero(rx_done, sizeof(rx_done));
-	for (i = 0; i < ET_RX_NRING; ++i) {
-		struct et_rxbuf_data *rbd = &sc->sc_rx_data[i];
-		int j;
-
-		for (j = 0; j < ET_RX_NDESC; ++j) {
-			error = bus_dmamap_create(sc->sc_mbuf_dtag, 0,
-				&rbd->rbd_buf[j].rb_dmap);
-			if (error) {
-				device_printf(dev, "can't create %d RX mbuf "
-					      "for %d RX ring\n", j, i);
-				rx_done[i] = j;
-				et_dma_mbuf_destroy(dev, 0, rx_done);
-				return (error);
-			}
+	/* Initialize RX ring 1. */
+	rbd = &sc->sc_rx_data[1];
+	rbd->rbd_bufsize = ET_RXDMA_CTRL_RING1_2048;
+	rbd->rbd_newbuf = et_newbuf_cluster;
+	rbd->rbd_discard = et_rxbuf_discard;
+	rbd->rbd_softc = sc;
+	rbd->rbd_ring = &sc->sc_rx_ring[1];
+	/* Create DMA maps for standard RX buffers, ring 1. */
+	for (i = 0; i < ET_RX_NDESC; i++) {
+		error = bus_dmamap_create(sc->sc_rx_tag, 0,
+		    &rbd->rbd_buf[i].rb_dmap);
+		if (error) {
+			device_printf(sc->dev,
+			    "could not create DMA map for mini RX mbufs\n");
+			return (error);
 		}
-		rx_done[i] = ET_RX_NDESC;
+	}
 
-		rbd->rbd_softc = sc;
-		rbd->rbd_ring = &sc->sc_rx_ring[i];
+	/* Create a spare DMA map for standard RX buffers, ring 1. */
+	error = bus_dmamap_create(sc->sc_rx_tag, 0, &sc->sc_rx_sparemap);
+	if (error) {
+		device_printf(sc->dev,
+		    "could not create spare DMA map for RX mbuf\n");
+		return (error);
 	}
 
-	/*
-	 * Create DMA maps for TX mbufs
-	 */
-	for (i = 0; i < ET_TX_NDESC; ++i) {
-		error = bus_dmamap_create(sc->sc_mbuf_dtag, 0,
-					  &tbd->tbd_buf[i].tb_dmap);
+	/* Create DMA maps for TX buffers. */
+	tbd = &sc->sc_tx_data;
+	for (i = 0; i < ET_TX_NDESC; i++) {
+		error = bus_dmamap_create(sc->sc_tx_tag, 0,
+		    &tbd->tbd_buf[i].tb_dmap);
 		if (error) {
-			device_printf(dev, "can't create %d TX mbuf "
-				      "DMA map\n", i);
-			et_dma_mbuf_destroy(dev, i, rx_done);
+			device_printf(sc->dev,
+			    "could not create DMA map for TX mbufs\n");
 			return (error);
 		}
 	}
@@ -936,106 +1027,97 @@ et_dma_mbuf_create(device_t dev)
 }
 
 static void
-et_dma_mbuf_destroy(device_t dev, int tx_done, const int rx_done[])
+et_dma_free(struct et_softc *sc)
 {
-	struct et_softc *sc = device_get_softc(dev);
-	struct et_txbuf_data *tbd = &sc->sc_tx_data;
+	struct et_txdesc_ring *tx_ring;
+	struct et_rxdesc_ring *rx_ring;
+	struct et_txstatus_data *txsd;
+	struct et_rxstat_ring *rxst_ring;
+	struct et_rxstatus_data *rxsd;
+	struct et_rxbuf_data *rbd;
+        struct et_txbuf_data *tbd;
 	int i;
 
-	if (sc->sc_mbuf_dtag == NULL)
-		return;
-
-	/*
-	 * Destroy DMA maps for RX mbufs
-	 */
-	for (i = 0; i < ET_RX_NRING; ++i) {
-		struct et_rxbuf_data *rbd = &sc->sc_rx_data[i];
-		int j;
-
-		for (j = 0; j < rx_done[i]; ++j) {
-			struct et_rxbuf *rb = &rbd->rbd_buf[j];
-
-			KASSERT(rb->rb_mbuf == NULL,
-			    ("RX mbuf in %d RX ring is not freed yet\n", i));
-			bus_dmamap_destroy(sc->sc_mbuf_dtag, rb->rb_dmap);
+	/* Destroy DMA maps for mini RX buffers, ring 0. */
+	rbd = &sc->sc_rx_data[0];
+	for (i = 0; i < ET_RX_NDESC; i++) {
+		if (rbd->rbd_buf[i].rb_dmap) {
+			bus_dmamap_destroy(sc->sc_rx_mini_tag,
+			    rbd->rbd_buf[i].rb_dmap);
+			rbd->rbd_buf[i].rb_dmap = NULL;
 		}
 	}
-
-	/*
-	 * Destroy DMA maps for TX mbufs
-	 */
-	for (i = 0; i < tx_done; ++i) {
-		struct et_txbuf *tb = &tbd->tbd_buf[i];
-
-		KASSERT(tb->tb_mbuf == NULL, ("TX mbuf is not freed yet\n"));
-		bus_dmamap_destroy(sc->sc_mbuf_dtag, tb->tb_dmap);
+	if (sc->sc_rx_mini_sparemap) {
+		bus_dmamap_destroy(sc->sc_rx_mini_tag, sc->sc_rx_mini_sparemap);
+		sc->sc_rx_mini_sparemap = NULL;
 	}
-
-	/*
-	 * Destroy spare mbuf DMA map
-	 */
-	bus_dmamap_destroy(sc->sc_mbuf_dtag, sc->sc_mbuf_tmp_dmap);
-
-	/*
-	 * Destroy mbuf DMA tag
-	 */
-	bus_dma_tag_destroy(sc->sc_mbuf_dtag);
-	sc->sc_mbuf_dtag = NULL;
-}
-
-static int
-et_dma_mem_create(device_t dev, bus_size_t size, bus_dma_tag_t *dtag,
-		  void **addr, bus_addr_t *paddr, bus_dmamap_t *dmap)
-{
-	struct et_softc *sc = device_get_softc(dev);
-	int error;
-
-	error = bus_dma_tag_create(sc->sc_dtag, ET_ALIGN, 0,
-				   BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
-				   NULL, NULL,
-				   size, 1, BUS_SPACE_MAXSIZE_32BIT,
-				   0, NULL, NULL, dtag);
-	if (error) {
-		device_printf(dev, "can't create DMA tag\n");
-		return (error);
+	if (sc->sc_rx_mini_tag) {
+		bus_dma_tag_destroy(sc->sc_rx_mini_tag);
+		sc->sc_rx_mini_tag = NULL;
 	}
 
-	error = bus_dmamem_alloc(*dtag, addr, BUS_DMA_WAITOK | BUS_DMA_ZERO,
-				 dmap);
-	if (error) {
-		device_printf(dev, "can't allocate DMA mem\n");
-		bus_dma_tag_destroy(*dtag);
-		*dtag = NULL;
-		return (error);
+	/* Destroy DMA maps for standard RX buffers, ring 1. */
+	rbd = &sc->sc_rx_data[1];
+	for (i = 0; i < ET_RX_NDESC; i++) {
+		if (rbd->rbd_buf[i].rb_dmap) {
+			bus_dmamap_destroy(sc->sc_rx_tag,
+			    rbd->rbd_buf[i].rb_dmap);
+			rbd->rbd_buf[i].rb_dmap = NULL;
+		}
 	}
-
-	error = bus_dmamap_load(*dtag, *dmap, *addr, size,
-				et_dma_ring_addr, paddr, BUS_DMA_WAITOK);
-	if (error) {
-		device_printf(dev, "can't load DMA mem\n");
-		bus_dmamem_free(*dtag, *addr, *dmap);
-		bus_dma_tag_destroy(*dtag);
-		*dtag = NULL;
-		return (error);
+	if (sc->sc_rx_sparemap) {
+		bus_dmamap_destroy(sc->sc_rx_tag, sc->sc_rx_sparemap);
+		sc->sc_rx_sparemap = NULL;
+	}
+	if (sc->sc_rx_tag) {
+		bus_dma_tag_destroy(sc->sc_rx_tag);
+		sc->sc_rx_tag = NULL;
 	}
-	return (0);
-}
 
-static void
-et_dma_mem_destroy(bus_dma_tag_t dtag, void *addr, bus_dmamap_t dmap)
-{
-	if (dtag != NULL) {
-		bus_dmamap_unload(dtag, dmap);
-		bus_dmamem_free(dtag, addr, dmap);
-		bus_dma_tag_destroy(dtag);
+	/* Destroy DMA maps for TX buffers. */
+	tbd = &sc->sc_tx_data;
+	for (i = 0; i < ET_TX_NDESC; i++) {
+		if (tbd->tbd_buf[i].tb_dmap) {
+			bus_dmamap_destroy(sc->sc_tx_tag,
+			    tbd->tbd_buf[i].tb_dmap);
+			tbd->tbd_buf[i].tb_dmap = NULL;
+		}
+	}
+	if (sc->sc_tx_tag) {
+		bus_dma_tag_destroy(sc->sc_tx_tag);
+		sc->sc_tx_tag = NULL;
 	}
-}
 
-static void
-et_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
-{
-	KASSERT(nseg == 1, ("too many segments\n"));
-	*((bus_addr_t *)arg) = seg->ds_addr;
+	/* Destroy mini RX ring, ring 0. */
+	rx_ring = &sc->sc_rx_ring[0];
+	et_dma_ring_free(sc, &rx_ring->rr_dtag, (void *)&rx_ring->rr_desc,
+	    &rx_ring->rr_dmap);
+	/* Destroy standard RX ring, ring 1. */
+	rx_ring = &sc->sc_rx_ring[1];
+	et_dma_ring_free(sc, &rx_ring->rr_dtag, (void *)&rx_ring->rr_desc,
+	    &rx_ring->rr_dmap);
+	/* Destroy RX stat ring. */
+	rxst_ring = &sc->sc_rxstat_ring;
+	et_dma_ring_free(sc, &rxst_ring->rsr_dtag, (void *)&rxst_ring->rsr_stat,
+	    &rxst_ring->rsr_dmap);
+	/* Destroy RX status block. */
+	rxsd = &sc->sc_rx_status;
+	et_dma_ring_free(sc, &rxst_ring->rsr_dtag, (void *)&rxst_ring->rsr_stat,
+	    &rxst_ring->rsr_dmap);
+	/* Destroy TX ring. */
+	tx_ring = &sc->sc_tx_ring;
+	et_dma_ring_free(sc, &tx_ring->tr_dtag, (void *)&tx_ring->tr_desc,
+	    &tx_ring->tr_dmap);
+	/* Destroy TX status block. */
+	txsd = &sc->sc_tx_status;
+	et_dma_ring_free(sc, &txsd->txsd_dtag, (void *)&txsd->txsd_status,
+	    &txsd->txsd_dmap);
+
+	/* Destroy the parent tag. */
+	if (sc->sc_dtag) {
+		bus_dma_tag_destroy(sc->sc_dtag);
+		sc->sc_dtag = NULL;
+	}
 }
 
 static void
@@ -1083,78 +1165,92 @@ et_intr(void *xsc)
 {
 	struct et_softc *sc = xsc;
 	struct ifnet *ifp;
-	uint32_t intrs;
+	uint32_t status;
 
 	ET_LOCK(sc);
 	ifp = sc->ifp;
-	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
-		ET_UNLOCK(sc);
-		return;
-	}
+	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
+		goto done;
 
-	et_disable_intrs(sc);
+	status = CSR_READ_4(sc, ET_INTR_STATUS);
+	if ((status & ET_INTRS) == 0)
+		goto done;
 
-	intrs = CSR_READ_4(sc, ET_INTR_STATUS);
-	intrs &= ET_INTRS;
-	if (intrs == 0)	/* Not interested */
-		goto back;
+	/* Disable further interrupts. */
+	CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff);
 
-	if (intrs & ET_INTR_RXEOF)
+	if (status & (ET_INTR_RXDMA_ERROR | ET_INTR_TXDMA_ERROR)) {
+		device_printf(sc->dev, "DMA error(0x%08x) -- resetting\n",
+		    status);
+		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+		et_init_locked(sc);
+		ET_UNLOCK(sc);
+		return;
+	}
+	if (status & ET_INTR_RXDMA)
 		et_rxeof(sc);
-	if (intrs & (ET_INTR_TXEOF | ET_INTR_TIMER))
+	if (status & (ET_INTR_TXDMA | ET_INTR_TIMER))
 		et_txeof(sc);
-	if (intrs & ET_INTR_TIMER)
+	if (status & ET_INTR_TIMER)
 		CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer);
-back:
-	et_enable_intrs(sc, ET_INTRS);
+	if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
+		CSR_WRITE_4(sc, ET_INTR_MASK, ~ET_INTRS);
+		if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
+			et_start_locked(ifp);
+	}
+done:
 	ET_UNLOCK(sc);
 }
 
 static void
 et_init_locked(struct et_softc *sc)
 {
-	struct ifnet *ifp = sc->ifp;
-	const struct et_bsize *arr;
-	int error, i;
+	struct ifnet *ifp;
+	int error;
 
 	ET_LOCK_ASSERT(sc);
 
+	ifp = sc->ifp;
 	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
 		return;
 
 	et_stop(sc);
+	et_reset(sc);
 
-	arr = et_bufsize_std;
-	for (i = 0; i < ET_RX_NRING; ++i) {
-		sc->sc_rx_data[i].rbd_bufsize = arr[i].bufsize;
-		sc->sc_rx_data[i].rbd_newbuf = arr[i].newbuf;
-	}
-
-	error = et_init_tx_ring(sc);
-	if (error)
-		goto back;
-
+	et_init_tx_ring(sc);
 	error = et_init_rx_ring(sc);
 	if (error)
-		goto back;
+		return;
 
 	error = et_chip_init(sc);
 	if (error)
-		goto back;
+		goto fail;
 
-	error = et_enable_txrx(sc, 1);
+	/*
+	 * Start TX/RX DMA engine
+	 */
+	error = et_start_rxdma(sc);
 	if (error)
-		goto back;
+		return;
 
-	et_enable_intrs(sc, ET_INTRS);
+	error = et_start_txdma(sc);
+	if (error)
+		return;
 
-	callout_reset(&sc->sc_tick, hz, et_tick, sc);
+	/* Enable interrupts. */
+	CSR_WRITE_4(sc, ET_INTR_MASK, ~ET_INTRS);
 
 	CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer);
 
 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
-back:
+
+	sc->sc_flags &= ~ET_FLAG_LINK;
+	et_ifmedia_upd_locked(ifp);
+
+	callout_reset(&sc->sc_tick, hz, et_tick, sc);
+
+fail:
 	if (error)
 		et_stop(sc);
 }
@@ -1208,11 +1304,11 @@ et_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
 			ET_LOCK(sc);
 			et_setmulti(sc);
 			ET_UNLOCK(sc);
-			error = 0;
 		}
 		break;
 
 	case SIOCSIFMTU:
+		ET_LOCK(sc);
 #if 0
 		if (sc->sc_flags & ET_FLAG_JUMBO)
 			max_framelen = ET_JUMBO_FRAMELEN;
@@ -1222,14 +1318,18 @@ et_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
 
 		if (ET_FRAMELEN(ifr->ifr_mtu) > max_framelen) {
 			error = EOPNOTSUPP;
+			ET_UNLOCK(sc);
 			break;
 		}
 
 		if (ifp->if_mtu != ifr->ifr_mtu) {
 			ifp->if_mtu = ifr->ifr_mtu;
-			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
-			et_init(sc);
+			if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
+				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+				et_init_locked(sc);
+			}
 		}
+		ET_UNLOCK(sc);
 		break;
 
 	case SIOCSIFCAP:
@@ -1256,44 +1356,69 @@ et_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
 static void
 et_start_locked(struct ifnet *ifp)
 {
-	struct et_softc *sc = ifp->if_softc;
+	struct et_softc *sc;
+	struct mbuf *m_head = NULL;
+	struct et_txdesc_ring *tx_ring;
 	struct et_txbuf_data *tbd;
-	int trans;
+	uint32_t tx_ready_pos;
+	int enq;
 
+	sc = ifp->if_softc;
 	ET_LOCK_ASSERT(sc);
-	tbd = &sc->sc_tx_data;
 
-	if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0)
+	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
+	    IFF_DRV_RUNNING ||
+	    (sc->sc_flags & (ET_FLAG_LINK | ET_FLAG_TXRX_ENABLED)) !=
+	    (ET_FLAG_LINK | ET_FLAG_TXRX_ENABLED))
 		return;
 
-	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING)
-		return;
-
-	trans = 0;
-	for (;;) {
-		struct mbuf *m;
+	/*
+	 * Driver does not request TX completion interrupt for every
+	 * queued frames to prevent generating excessive interrupts.
+	 * This means driver may wait for TX completion interrupt even
+	 * though some frames were sucessfully transmitted.  Reclaiming
+	 * transmitted frames will ensure driver see all available
+	 * descriptors.
+	 */
+	tbd = &sc->sc_tx_data;
+	if (tbd->tbd_used > (ET_TX_NDESC * 2) / 3)
+		et_txeof(sc);
 
-		if ((tbd->tbd_used + ET_NSEG_SPARE) > ET_TX_NDESC) {
+	for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
+		if (tbd->tbd_used + ET_NSEG_SPARE >= ET_TX_NDESC) {
 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 			break;
 		}
 
-		IFQ_DEQUEUE(&ifp->if_snd, m);
-		if (m == NULL)
+		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
+		if (m_head == NULL)
 			break;
 
-		if (et_encap(sc, &m)) {
-			ifp->if_oerrors++;
-			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
+		if (et_encap(sc, &m_head)) {
+			if (m_head == NULL) {
+				ifp->if_oerrors++;
+				break;
+			}
+			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
+			if (tbd->tbd_used > 0)
+				ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 			break;
 		}
-		trans = 1;
-
-		BPF_MTAP(ifp, m);
+		enq++;
+		ETHER_BPF_MTAP(ifp, m_head);
 	}
 
-	if (trans)
+	if (enq > 0) {
+		tx_ring = &sc->sc_tx_ring;
+		bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap,
+		    BUS_DMASYNC_PREWRITE);
+		tx_ready_pos = tx_ring->tr_ready_index &
+		    ET_TX_READY_POS_INDEX_MASK;
+		if (tx_ring->tr_ready_wrap)
+			tx_ready_pos |= ET_TX_READY_POS_WRAP;
+		CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos);
 		sc->watchdog_timer = 5;
+	}
 }
 
 static void
@@ -1306,20 +1431,26 @@ et_start(struct ifnet *ifp)
 	ET_UNLOCK(sc);
 }
 
-static void
+static int
 et_watchdog(struct et_softc *sc)
 {
+	uint32_t status;
+
 	ET_LOCK_ASSERT(sc);
 
 	if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
-		return;
+		return (0);
 
-	if_printf(sc->ifp, "watchdog timed out\n");
+	bus_dmamap_sync(sc->sc_tx_status.txsd_dtag, sc->sc_tx_status.txsd_dmap,
+	    BUS_DMASYNC_POSTREAD);
+	status = le32toh(*(sc->sc_tx_status.txsd_status));
+	if_printf(sc->ifp, "watchdog timed out (0x%08x) -- resetting\n",
+	    status);
 
 	sc->ifp->if_oerrors++;
 	sc->ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 	et_init_locked(sc);
-	et_start_locked(sc->ifp);
+	return (EJUSTRETURN);
 }
 
 static int
@@ -1347,49 +1478,59 @@ et_stop_txdma(struct et_softc *sc)
 static void
 et_free_tx_ring(struct et_softc *sc)
 {
-	struct et_txbuf_data *tbd = &sc->sc_tx_data;
-	struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
+	struct et_txdesc_ring *tx_ring;
+	struct et_txbuf_data *tbd;
+	struct et_txbuf *tb;
 	int i;
 
+	tbd = &sc->sc_tx_data;
+	tx_ring = &sc->sc_tx_ring;
 	for (i = 0; i < ET_TX_NDESC; ++i) {
-		struct et_txbuf *tb = &tbd->tbd_buf[i];
-
+		tb = &tbd->tbd_buf[i];
 		if (tb->tb_mbuf != NULL) {
+			bus_dmamap_sync(sc->sc_tx_tag, tb->tb_dmap,
+			    BUS_DMASYNC_POSTWRITE);
 			bus_dmamap_unload(sc->sc_mbuf_dtag, tb->tb_dmap);
 			m_freem(tb->tb_mbuf);
 			tb->tb_mbuf = NULL;
 		}
 	}
-
-	bzero(tx_ring->tr_desc, ET_TX_RING_SIZE);
-	bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap,
-			BUS_DMASYNC_PREWRITE);
 }
 
 static void
 et_free_rx_ring(struct et_softc *sc)
 {
-	int n;
-
-	for (n = 0; n < ET_RX_NRING; ++n) {
-		struct et_rxbuf_data *rbd = &sc->sc_rx_data[n];
-		struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[n];
-		int i;
-
-		for (i = 0; i < ET_RX_NDESC; ++i) {
-			struct et_rxbuf *rb = &rbd->rbd_buf[i];
+	struct et_rxbuf_data *rbd;
+	struct et_rxdesc_ring *rx_ring;
+	struct et_rxbuf *rb;
+	int i;
 
-			if (rb->rb_mbuf != NULL) {
-				bus_dmamap_unload(sc->sc_mbuf_dtag,
-			  	    rb->rb_dmap);
-				m_freem(rb->rb_mbuf);
-				rb->rb_mbuf = NULL;
-			}
+	/* Ring 0 */
+	rx_ring = &sc->sc_rx_ring[0];
+	rbd = &sc->sc_rx_data[0];
+	for (i = 0; i < ET_RX_NDESC; ++i) {
+		rb = &rbd->rbd_buf[i];
+		if (rb->rb_mbuf != NULL) {
+			bus_dmamap_sync(sc->sc_rx_mini_tag, rx_ring->rr_dmap,
+			    BUS_DMASYNC_POSTREAD);
+			bus_dmamap_unload(sc->sc_rx_mini_tag, rb->rb_dmap);
+			m_freem(rb->rb_mbuf);
+			rb->rb_mbuf = NULL;
 		}
+	}
 
-		bzero(rx_ring->rr_desc, ET_RX_RING_SIZE);
-		bus_dmamap_sync(rx_ring->rr_dtag, rx_ring->rr_dmap,
-				BUS_DMASYNC_PREWRITE);
+	/* Ring 1 */
+	rx_ring = &sc->sc_rx_ring[1];
+	rbd = &sc->sc_rx_data[1];
+	for (i = 0; i < ET_RX_NDESC; ++i) {
+		rb = &rbd->rbd_buf[i];
+		if (rb->rb_mbuf != NULL) {
+			bus_dmamap_sync(sc->sc_rx_tag, rx_ring->rr_dmap,
+			    BUS_DMASYNC_POSTREAD);
+			bus_dmamap_unload(sc->sc_rx_tag, rb->rb_dmap);
+			m_freem(rb->rb_mbuf);
+			rb->rb_mbuf = NULL;
+		}
 	}
 }
 
@@ -1516,40 +1657,41 @@ et_chip_init(struct et_softc *sc)
 	return (0);
 }
 
-static int
+static void
 et_init_tx_ring(struct et_softc *sc)
 {
-	struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
-	struct et_txstatus_data *txsd = &sc->sc_tx_status;
-	struct et_txbuf_data *tbd = &sc->sc_tx_data;
+	struct et_txdesc_ring *tx_ring;
+	struct et_txbuf_data *tbd;
+	struct et_txstatus_data *txsd;
 
+	tx_ring = &sc->sc_tx_ring;
 	bzero(tx_ring->tr_desc, ET_TX_RING_SIZE);
 	bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap,
-			BUS_DMASYNC_PREWRITE);
+	    BUS_DMASYNC_PREWRITE);
 
+	tbd = &sc->sc_tx_data;
 	tbd->tbd_start_index = 0;
 	tbd->tbd_start_wrap = 0;
 	tbd->tbd_used = 0;
 
+	txsd = &sc->sc_tx_status;
 	bzero(txsd->txsd_status, sizeof(uint32_t));
 	bus_dmamap_sync(txsd->txsd_dtag, txsd->txsd_dmap,
-			BUS_DMASYNC_PREWRITE);
-	return (0);
+	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 }
 
 static int
 et_init_rx_ring(struct et_softc *sc)
 {
-	struct et_rxstatus_data *rxsd = &sc->sc_rx_status;
-	struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring;
-	int n;
+	struct et_rxstatus_data *rxsd;
+	struct et_rxstat_ring *rxst_ring;
+	struct et_rxbuf_data *rbd;
+	int i, error, n;
 
 	for (n = 0; n < ET_RX_NRING; ++n) {
-		struct et_rxbuf_data *rbd = &sc->sc_rx_data[n];
-		int i, error;
-
+		rbd = &sc->sc_rx_data[n];
 		for (i = 0; i < ET_RX_NDESC; ++i) {
-			error = rbd->rbd_newbuf(rbd, i, 1);
+			error = rbd->rbd_newbuf(rbd, i);
 			if (error) {
 				if_printf(sc->ifp, "%d ring %d buf, "
 					  "newbuf failed: %d\n", n, i, error);
@@ -1558,37 +1700,19 @@ et_init_rx_ring(struct et_softc *sc)
 		}
 	}
 
+	rxsd = &sc->sc_rx_status;
 	bzero(rxsd->rxsd_status, sizeof(struct et_rxstatus));
 	bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap,
-			BUS_DMASYNC_PREWRITE);
+	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 
+	rxst_ring = &sc->sc_rxstat_ring;
 	bzero(rxst_ring->rsr_stat, ET_RXSTAT_RING_SIZE);
 	bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap,
-			BUS_DMASYNC_PREWRITE);
+	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 
 	return (0);
 }
 
-static void
-et_dma_buf_addr(void *xctx, bus_dma_segment_t *segs, int nsegs,
-		bus_size_t mapsz __unused, int error)
-{
-	struct et_dmamap_ctx *ctx = xctx;
-	int i;
-
-	if (error)
-		return;
-
-	if (nsegs > ctx->nsegs) {
-		ctx->nsegs = 0;
-		return;
-	}
-
-	ctx->nsegs = nsegs;
-	for (i = 0; i < nsegs; ++i)
-		ctx->segs[i] = segs[i];
-}
-
 static int
 et_init_rxdma(struct et_softc *sc)
 {
@@ -1837,8 +1961,12 @@ et_init_txmac(struct et_softc *sc)
 	/* Disable TX MAC and FC(?) */
 	CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE);
 
-	/* No flow control yet */
-	CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0);
+	/*
+	 * Initialize pause time.
+	 * This register should be set before XON/XOFF frame is
+	 * sent by driver.
+	 */
+	CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0 << ET_TXMAC_FLOWCTRL_CFPT_SHIFT);
 
 	/* Enable TX MAC but leave FC(?) diabled */
 	CSR_WRITE_4(sc, ET_TXMAC_CTRL,
@@ -1873,66 +2001,23 @@ et_start_txdma(struct et_softc *sc)
 	return (0);
 }
 
-static int
-et_enable_txrx(struct et_softc *sc, int media_upd)
-{
-	struct ifnet *ifp = sc->ifp;
-	uint32_t val;
-	int i, error;
-
-	val = CSR_READ_4(sc, ET_MAC_CFG1);
-	val |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN;
-	val &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW |
-		 ET_MAC_CFG1_LOOPBACK);
-	CSR_WRITE_4(sc, ET_MAC_CFG1, val);
-
-	if (media_upd)
-		et_ifmedia_upd_locked(ifp);
-	else
-		et_setmedia(sc);
-
-#define NRETRY	50
-
-	for (i = 0; i < NRETRY; ++i) {
-		val = CSR_READ_4(sc, ET_MAC_CFG1);
-		if ((val & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) ==
-		    (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN))
-			break;
-
-		DELAY(100);
-	}
-	if (i == NRETRY) {
-		if_printf(ifp, "can't enable RX/TX\n");
-		return (0);
-	}
-	sc->sc_flags |= ET_FLAG_TXRX_ENABLED;
-
-#undef NRETRY
-
-	/*
-	 * Start TX/RX DMA engine
-	 */
-	error = et_start_rxdma(sc);
-	if (error)
-		return (error);
-
-	error = et_start_txdma(sc);
-	if (error)
-		return (error);
-
-	return (0);
-}
-
 static void
 et_rxeof(struct et_softc *sc)
 {
-	struct ifnet *ifp;
 	struct et_rxstatus_data *rxsd;
 	struct et_rxstat_ring *rxst_ring;
-	uint32_t rxs_stat_ring, rxst_info2;
-	int rxst_wrap, rxst_index;
+	struct et_rxbuf_data *rbd;
+	struct et_rxdesc_ring *rx_ring;
+	struct et_rxstat *st;
+	struct ifnet *ifp;
+	struct mbuf *m;
+	uint32_t rxstat_pos, rxring_pos;
+	uint32_t rxst_info1, rxst_info2, rxs_stat_ring;
+	int buflen, buf_idx, npost[2], ring_idx;
+	int rxst_index, rxst_wrap;
 
 	ET_LOCK_ASSERT(sc);
+
 	ifp = sc->ifp;
 	rxsd = &sc->sc_rx_status;
 	rxst_ring = &sc->sc_rxstat_ring;
@@ -1941,26 +2026,24 @@ et_rxeof(struct et_softc *sc)
 		return;
 
 	bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap,
-			BUS_DMASYNC_POSTREAD);
+	    BUS_DMASYNC_POSTREAD);
 	bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap,
-			BUS_DMASYNC_POSTREAD);
+	    BUS_DMASYNC_POSTREAD);
 
+	npost[0] = npost[1] = 0;
 	rxs_stat_ring = le32toh(rxsd->rxsd_status->rxs_stat_ring);
 	rxst_wrap = (rxs_stat_ring & ET_RXS_STATRING_WRAP) ? 1 : 0;
 	rxst_index = (rxs_stat_ring & ET_RXS_STATRING_INDEX_MASK) >>
 	    ET_RXS_STATRING_INDEX_SHIFT;
 
 	while (rxst_index != rxst_ring->rsr_index ||
-	       rxst_wrap != rxst_ring->rsr_wrap) {
-		struct et_rxbuf_data *rbd;
-		struct et_rxdesc_ring *rx_ring;
-		struct et_rxstat *st;
-		struct mbuf *m;
-		int buflen, buf_idx, ring_idx;
-		uint32_t rxstat_pos, rxring_pos;
+	    rxst_wrap != rxst_ring->rsr_wrap) {
+		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
+			break;
 
 		MPASS(rxst_ring->rsr_index < ET_RX_NSTAT);
 		st = &rxst_ring->rsr_stat[rxst_ring->rsr_index];
+		rxst_info1 = le32toh(st->rxst_info1);
 		rxst_info2 = le32toh(st->rxst_info2);
 		buflen = (rxst_info2 & ET_RXST_INFO2_LEN_MASK) >>
 		    ET_RXST_INFO2_LEN_SHIFT;
@@ -1991,32 +2074,32 @@ et_rxeof(struct et_softc *sc)
 
 		rbd = &sc->sc_rx_data[ring_idx];
 		m = rbd->rbd_buf[buf_idx].rb_mbuf;
-
-		if (rbd->rbd_newbuf(rbd, buf_idx, 0) == 0) {
-			if (buflen < ETHER_CRC_LEN) {
+		if ((rxst_info1 & ET_RXST_INFO1_OK) == 0){
+			/* Discard errored frame. */
+			rbd->rbd_discard(rbd, buf_idx);
+		} else if (rbd->rbd_newbuf(rbd, buf_idx) != 0) {
+			/* No available mbufs, discard it. */
+			ifp->if_iqdrops++;
+			rbd->rbd_discard(rbd, buf_idx);
+		} else {
+			buflen -= ETHER_CRC_LEN;
+			if (buflen < ETHER_HDR_LEN) {
 				m_freem(m);
-				m = NULL;
 				ifp->if_ierrors++;
 			} else {
-				m->m_pkthdr.len = m->m_len =
-				    buflen - ETHER_CRC_LEN;
+				m->m_pkthdr.len = m->m_len = buflen;
 				m->m_pkthdr.rcvif = ifp;
-				ifp->if_ipackets++;
 				ET_UNLOCK(sc);
 				ifp->if_input(ifp, m);
 				ET_LOCK(sc);
 			}
-		} else {
-			ifp->if_ierrors++;
 		}
-		m = NULL;	/* Catch invalid reference */
 
 		rx_ring = &sc->sc_rx_ring[ring_idx];
-
 		if (buf_idx != rx_ring->rr_index) {
-			if_printf(ifp, "WARNING!! ring %d, "
-				  "buf_idx %d, rr_idx %d\n",
-				  ring_idx, buf_idx, rx_ring->rr_index);
+			if_printf(ifp,
+			    "WARNING!! ring %d, buf_idx %d, rr_idx %d\n",
+			    ring_idx, buf_idx, rx_ring->rr_index);
 		}
 
 		MPASS(rx_ring->rr_index < ET_RX_NDESC);
@@ -2029,81 +2112,66 @@ et_rxeof(struct et_softc *sc)
 			rxring_pos |= ET_RX_RING_POS_WRAP;
 		CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos);
 	}
+
+	bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap,
+	    BUS_DMASYNC_PREREAD);
+	bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap,
+	    BUS_DMASYNC_PREREAD);
 }
 
 static int
 et_encap(struct et_softc *sc, struct mbuf **m0)
 {
-	struct mbuf *m = *m0;
-	bus_dma_segment_t segs[ET_NSEG_MAX];
-	struct et_dmamap_ctx ctx;
-	struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
-	struct et_txbuf_data *tbd = &sc->sc_tx_data;
+	struct et_txdesc_ring *tx_ring;
+	struct et_txbuf_data *tbd;
 	struct et_txdesc *td;
+	struct mbuf *m;
+	bus_dma_segment_t segs[ET_NSEG_MAX];
 	bus_dmamap_t map;
-	int error, maxsegs, first_idx, last_idx, i;
-	uint32_t csum_flags, tx_ready_pos, last_td_ctrl2;
-
-	maxsegs = ET_TX_NDESC - tbd->tbd_used;
-	if (maxsegs > ET_NSEG_MAX)
-		maxsegs = ET_NSEG_MAX;
-	KASSERT(maxsegs >= ET_NSEG_SPARE,
-		("not enough spare TX desc (%d)\n", maxsegs));
+	uint32_t csum_flags, last_td_ctrl2;
+	int error, i, idx, first_idx, last_idx, nsegs;
 
+	tx_ring = &sc->sc_tx_ring;
 	MPASS(tx_ring->tr_ready_index < ET_TX_NDESC);
+	tbd = &sc->sc_tx_data;
 	first_idx = tx_ring->tr_ready_index;
 	map = tbd->tbd_buf[first_idx].tb_dmap;
 
-	ctx.nsegs = maxsegs;
-	ctx.segs = segs;
-	error = bus_dmamap_load_mbuf(sc->sc_mbuf_dtag, map, m,
-				     et_dma_buf_addr, &ctx, BUS_DMA_NOWAIT);
-	if (!error && ctx.nsegs == 0) {
-		bus_dmamap_unload(sc->sc_mbuf_dtag, map);
-		error = EFBIG;
-	}
-	if (error && error != EFBIG) {
-		if_printf(sc->ifp, "can't load TX mbuf, error %d\n",
-			  error);
-		goto back;
-	}
-	if (error) {	/* error == EFBIG */
-		struct mbuf *m_new;
-
-		m_new = m_defrag(m, M_DONTWAIT);
-		if (m_new == NULL) {
-			if_printf(sc->ifp, "can't defrag TX mbuf\n");
-			error = ENOBUFS;
-			goto back;
-		} else {
-			*m0 = m = m_new;
+	error = bus_dmamap_load_mbuf_sg(sc->sc_tx_tag, map, *m0, segs, &nsegs,
+	    0);
+	if (error == EFBIG) {
+		m = m_collapse(*m0, M_DONTWAIT, ET_NSEG_MAX);
+		if (m == NULL) {
+			m_freem(*m0);
+			*m0 = NULL;
+			return (ENOMEM);
 		}
-
-		ctx.nsegs = maxsegs;
-		ctx.segs = segs;
-		error = bus_dmamap_load_mbuf(sc->sc_mbuf_dtag, map, m,
-					     et_dma_buf_addr, &ctx,
-					     BUS_DMA_NOWAIT);
-		if (error || ctx.nsegs == 0) {
-			if (ctx.nsegs == 0) {
-				bus_dmamap_unload(sc->sc_mbuf_dtag, map);
-				error = EFBIG;
-			}
-			if_printf(sc->ifp,
-				  "can't load defraged TX mbuf\n");
-			goto back;
+		*m0 = m;
+		error = bus_dmamap_load_mbuf_sg(sc->sc_tx_tag, map, *m0, segs,
+		    &nsegs, 0);
+		if (error != 0) {
+			m_freem(*m0);
+                        *m0 = NULL;
+			return (error);
 		}
-	}
+	} else if (error != 0)
+		return (error);
 
-	bus_dmamap_sync(sc->sc_mbuf_dtag, map, BUS_DMASYNC_PREWRITE);
+	/* Check for descriptor overruns. */
+	if (tbd->tbd_used + nsegs > ET_TX_NDESC - 1) {
+		bus_dmamap_unload(sc->sc_tx_tag, map);
+		return (ENOBUFS);
+	}
+	bus_dmamap_sync(sc->sc_tx_tag, map, BUS_DMASYNC_PREWRITE);
 
 	last_td_ctrl2 = ET_TDCTRL2_LAST_FRAG;
-	sc->sc_tx += ctx.nsegs;
+	sc->sc_tx += nsegs;
 	if (sc->sc_tx / sc->sc_tx_intr_nsegs != sc->sc_tx_intr) {
 		sc->sc_tx_intr = sc->sc_tx / sc->sc_tx_intr_nsegs;
 		last_td_ctrl2 |= ET_TDCTRL2_INTR;
 	}
 
+	m = *m0;
 	csum_flags = 0;
 	if ((m->m_pkthdr.csum_flags & ET_CSUM_FEATURES) != 0) {
 		if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0)
@@ -2114,15 +2182,14 @@ et_encap(struct et_softc *sc, struct mbuf **m0)
 			csum_flags |= ET_TDCTRL2_CSUM_TCP;
 	}
 	last_idx = -1;
-	for (i = 0; i < ctx.nsegs; ++i) {
-		int idx;
-
+	for (i = 0; i < nsegs; ++i) {
 		idx = (first_idx + i) % ET_TX_NDESC;
 		td = &tx_ring->tr_desc[idx];
 		td->td_addr_hi = htole32(ET_ADDR_HI(segs[i].ds_addr));
 		td->td_addr_lo = htole32(ET_ADDR_LO(segs[i].ds_addr));
 		td->td_ctrl1 =  htole32(segs[i].ds_len & ET_TDCTRL1_LEN_MASK);
-		if (i == ctx.nsegs - 1) {	/* Last frag */
+		if (i == nsegs - 1) {
+			/* Last frag */
 			td->td_ctrl2 = htole32(last_td_ctrl2 | csum_flags);
 			last_idx = idx;
 		} else
@@ -2135,43 +2202,32 @@ et_encap(struct et_softc *sc, struct mbuf **m0)
 		}
 	}
 	td = &tx_ring->tr_desc[first_idx];
-	td->td_ctrl2 |= htole32(ET_TDCTRL2_FIRST_FRAG);	/* First frag */
+	/* First frag */
+	td->td_ctrl2 |= htole32(ET_TDCTRL2_FIRST_FRAG);
 
 	MPASS(last_idx >= 0);
 	tbd->tbd_buf[first_idx].tb_dmap = tbd->tbd_buf[last_idx].tb_dmap;
 	tbd->tbd_buf[last_idx].tb_dmap = map;
 	tbd->tbd_buf[last_idx].tb_mbuf = m;
 
-	tbd->tbd_used += ctx.nsegs;
+	tbd->tbd_used += nsegs;
 	MPASS(tbd->tbd_used <= ET_TX_NDESC);
 
-	bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap,
-			BUS_DMASYNC_PREWRITE);
-
-	tx_ready_pos = tx_ring->tr_ready_index & ET_TX_READY_POS_INDEX_MASK;
-	if (tx_ring->tr_ready_wrap)
-		tx_ready_pos |= ET_TX_READY_POS_WRAP;
-	CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos);
-
-	error = 0;
-back:
-	if (error) {
-		m_freem(m);
-		*m0 = NULL;
-	}
-	return (error);
+	return (0);
 }
 
 static void
 et_txeof(struct et_softc *sc)
 {
-	struct ifnet *ifp;
 	struct et_txdesc_ring *tx_ring;
 	struct et_txbuf_data *tbd;
+	struct et_txbuf *tb;
+	struct ifnet *ifp;
 	uint32_t tx_done;
 	int end, wrap;
 
 	ET_LOCK_ASSERT(sc);
+
 	ifp = sc->ifp;
 	tx_ring = &sc->sc_tx_ring;
 	tbd = &sc->sc_tx_data;
@@ -2182,26 +2238,22 @@ et_txeof(struct et_softc *sc)
 	if (tbd->tbd_used == 0)
 		return;
 
+	bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap,
+	    BUS_DMASYNC_POSTWRITE);
+
 	tx_done = CSR_READ_4(sc, ET_TX_DONE_POS);
 	end = tx_done & ET_TX_DONE_POS_INDEX_MASK;
 	wrap = (tx_done & ET_TX_DONE_POS_WRAP) ? 1 : 0;
 
 	while (tbd->tbd_start_index != end || tbd->tbd_start_wrap != wrap) {
-		struct et_txbuf *tb;
-
 		MPASS(tbd->tbd_start_index < ET_TX_NDESC);
 		tb = &tbd->tbd_buf[tbd->tbd_start_index];
-
-		bzero(&tx_ring->tr_desc[tbd->tbd_start_index],
-		      sizeof(struct et_txdesc));
-		bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap,
-				BUS_DMASYNC_PREWRITE);
-
 		if (tb->tb_mbuf != NULL) {
-			bus_dmamap_unload(sc->sc_mbuf_dtag, tb->tb_dmap);
+			bus_dmamap_sync(sc->sc_tx_tag, tb->tb_dmap,
+			    BUS_DMASYNC_POSTWRITE);
+			bus_dmamap_unload(sc->sc_tx_tag, tb->tb_dmap);
 			m_freem(tb->tb_mbuf);
 			tb->tb_mbuf = NULL;
-			ifp->if_opackets++;
 		}
 
 		if (++tbd->tbd_start_index == ET_TX_NDESC) {
@@ -2215,10 +2267,8 @@ et_txeof(struct et_softc *sc)
 
 	if (tbd->tbd_used == 0)
 		sc->watchdog_timer = 0;
-	if (tbd->tbd_used + ET_NSEG_SPARE <= ET_TX_NDESC)
+	if (tbd->tbd_used + ET_NSEG_SPARE < ET_TX_NDESC)
 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
-
-	et_start_locked(ifp);
 }
 
 static void
@@ -2233,104 +2283,124 @@ et_tick(void *xsc)
 	mii = device_get_softc(sc->sc_miibus);
 
 	mii_tick(mii);
-	if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0 &&
-	    (mii->mii_media_status & IFM_ACTIVE) &&
-	    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
-		if_printf(ifp, "Link up, enable TX/RX\n");
-		if (et_enable_txrx(sc, 0) == 0)
-			et_start_locked(ifp);
-	}
-	et_watchdog(sc);
+	et_stats_update(sc);
+	if (et_watchdog(sc) == EJUSTRETURN)
+		return;
 	callout_reset(&sc->sc_tick, hz, et_tick, sc);
 }
 
 static int
-et_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx, int init)
+et_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx)
 {
-	return (et_newbuf(rbd, buf_idx, init, MCLBYTES));
+	struct et_softc *sc;
+	struct et_rxdesc *desc;
+	struct et_rxbuf *rb;
+	struct mbuf *m;
+	bus_dma_segment_t segs[1];
+	bus_dmamap_t dmap;
+	int nsegs;
+
+	MPASS(buf_idx < ET_RX_NDESC);
+	m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
+	if (m == NULL)
+		return (ENOBUFS);
+	m->m_len = m->m_pkthdr.len = MCLBYTES;
+	m_adj(m, ETHER_ALIGN);
+
+	sc = rbd->rbd_softc;
+	rb = &rbd->rbd_buf[buf_idx];
+
+	if (bus_dmamap_load_mbuf_sg(sc->sc_rx_tag, sc->sc_rx_sparemap, m,
+	    segs, &nsegs, 0) != 0) {
+		m_freem(m);
+		return (ENOBUFS);
+	}
+	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
+
+	if (rb->rb_mbuf != NULL) {
+		bus_dmamap_sync(sc->sc_rx_tag, rb->rb_dmap,
+		    BUS_DMASYNC_POSTREAD);
+		bus_dmamap_unload(sc->sc_rx_tag, rb->rb_dmap);
+	}
+	dmap = rb->rb_dmap;
+	rb->rb_dmap = sc->sc_rx_sparemap;
+	sc->sc_rx_sparemap = dmap;
+	bus_dmamap_sync(sc->sc_rx_tag, rb->rb_dmap, BUS_DMASYNC_PREREAD);
+
+	rb->rb_mbuf = m;
+	desc = &rbd->rbd_ring->rr_desc[buf_idx];
+	desc->rd_addr_hi = htole32(ET_ADDR_HI(segs[0].ds_addr));
+	desc->rd_addr_lo = htole32(ET_ADDR_LO(segs[0].ds_addr));
+	desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK);
+	bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap,
+	    BUS_DMASYNC_PREWRITE);
+	return (0);
 }
 
-static int
-et_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx, int init)
+static void
+et_rxbuf_discard(struct et_rxbuf_data *rbd, int buf_idx)
 {
-	return (et_newbuf(rbd, buf_idx, init, MHLEN));
+	struct et_rxdesc *desc;
+
+	desc = &rbd->rbd_ring->rr_desc[buf_idx];
+	desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK);
+	bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap,
+	    BUS_DMASYNC_PREWRITE);
 }
 
 static int
-et_newbuf(struct et_rxbuf_data *rbd, int buf_idx, int init, int len0)
+et_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx)
 {
-	struct et_softc *sc = rbd->rbd_softc;
+	struct et_softc *sc;
+	struct et_rxdesc *desc;
 	struct et_rxbuf *rb;
 	struct mbuf *m;
-	struct et_dmamap_ctx ctx;
-	bus_dma_segment_t seg;
+	bus_dma_segment_t segs[1];
 	bus_dmamap_t dmap;
-	int error, len;
+	int nsegs;
 
 	MPASS(buf_idx < ET_RX_NDESC);
-	rb = &rbd->rbd_buf[buf_idx];
-
-	m = m_getl(len0, /* init ? M_WAIT :*/ M_DONTWAIT, MT_DATA, M_PKTHDR, &len);
-	if (m == NULL) {
-		error = ENOBUFS;
+	MGETHDR(m, M_DONTWAIT, MT_DATA);
+	if (m == NULL)
+		return (ENOBUFS);
+	m->m_len = m->m_pkthdr.len = MHLEN;
+	m_adj(m, ETHER_ALIGN);
 
-		if (init) {
-			if_printf(sc->ifp,
-				  "m_getl failed, size %d\n", len0);
-			return (error);
-		} else {
-			goto back;
-		}
-	}
-	m->m_len = m->m_pkthdr.len = len;
+	sc = rbd->rbd_softc;
+	rb = &rbd->rbd_buf[buf_idx];
 
-	/*
-	 * Try load RX mbuf into temporary DMA tag
-	 */
-	ctx.nsegs = 1;
-	ctx.segs = &seg;
-	error = bus_dmamap_load_mbuf(sc->sc_mbuf_dtag, sc->sc_mbuf_tmp_dmap, m,
-				     et_dma_buf_addr, &ctx,
-				     init ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
-	if (error || ctx.nsegs == 0) {
-		if (!error) {
-			bus_dmamap_unload(sc->sc_mbuf_dtag,
-					  sc->sc_mbuf_tmp_dmap);
-			error = EFBIG;
-			if_printf(sc->ifp, "too many segments?!\n");
-		}
+	if (bus_dmamap_load_mbuf_sg(sc->sc_rx_mini_tag, sc->sc_rx_mini_sparemap,
+	    m, segs, &nsegs, 0) != 0) {
 		m_freem(m);
-		m = NULL;
-
-		if (init) {
-			if_printf(sc->ifp, "can't load RX mbuf\n");
-			return (error);
-		} else {
-			goto back;
-		}
+		return (ENOBUFS);
 	}
+	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
 
-	if (!init) {
-		bus_dmamap_sync(sc->sc_mbuf_dtag, rb->rb_dmap,
-				BUS_DMASYNC_POSTREAD);
-		bus_dmamap_unload(sc->sc_mbuf_dtag, rb->rb_dmap);
+	if (rb->rb_mbuf != NULL) {
+		bus_dmamap_sync(sc->sc_rx_mini_tag, rb->rb_dmap,
+		    BUS_DMASYNC_POSTREAD);
+		bus_dmamap_unload(sc->sc_rx_mini_tag, rb->rb_dmap);
 	}
-	rb->rb_mbuf = m;
-	rb->rb_paddr = seg.ds_addr;
-
-	/*
-	 * Swap RX buf's DMA map with the loaded temporary one
-	 */
 	dmap = rb->rb_dmap;
-	rb->rb_dmap = sc->sc_mbuf_tmp_dmap;
-	sc->sc_mbuf_tmp_dmap = dmap;
+	rb->rb_dmap = sc->sc_rx_mini_sparemap;
+	sc->sc_rx_mini_sparemap = dmap;
+	bus_dmamap_sync(sc->sc_rx_mini_tag, rb->rb_dmap, BUS_DMASYNC_PREREAD);
 
-	error = 0;
-back:
-	et_setup_rxdesc(rbd, buf_idx, rb->rb_paddr);
-	return (error);
+	rb->rb_mbuf = m;
+	desc = &rbd->rbd_ring->rr_desc[buf_idx];
+	desc->rd_addr_hi = htole32(ET_ADDR_HI(segs[0].ds_addr));
+	desc->rd_addr_lo = htole32(ET_ADDR_LO(segs[0].ds_addr));
+	desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK);
+	bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap,
+	    BUS_DMASYNC_PREWRITE);
+	return (0);
 }
 
+#define	ET_SYSCTL_STAT_ADD32(c, h, n, p, d)	\
+	    SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
+#define	ET_SYSCTL_STAT_ADD64(c, h, n, p, d)	\
+	    SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
+
 /*
  * Create sysctl tree
  */
@@ -2338,7 +2408,9 @@ static void
 et_add_sysctls(struct et_softc * sc)
 {
 	struct sysctl_ctx_list *ctx;
-	struct sysctl_oid_list *children;
+	struct sysctl_oid_list *children, *parent;
+	struct sysctl_oid *tree;
+	struct et_hw_stats *stats;
 
 	ctx = device_get_sysctl_ctx(sc->dev);
 	children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
@@ -2354,8 +2426,116 @@ et_add_sysctls(struct et_softc * sc)
 	    "TX IM, # segments per TX interrupt");
 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "timer",
 	    CTLFLAG_RW, &sc->sc_timer, 0, "TX timer");
+
+	tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
+	    NULL, "ET statistics");
+        parent = SYSCTL_CHILDREN(tree);
+
+	/* TX/RX statistics. */
+	stats = &sc->sc_stats;
+	ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_64", &stats->pkts_64,
+	    "0 to 64 bytes frames");
+	ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_65_127", &stats->pkts_65,
+	    "65 to 127 bytes frames");
+	ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_128_255", &stats->pkts_128,
+	    "128 to 255 bytes frames");
+	ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_256_511", &stats->pkts_256,
+	    "256 to 511 bytes frames");
+	ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_512_1023", &stats->pkts_512,
+	    "512 to 1023 bytes frames");
+	ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_1024_1518", &stats->pkts_1024,
+	    "1024 to 1518 bytes frames");
+	ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_1519_1522", &stats->pkts_1519,
+	    "1519 to 1522 bytes frames");
+
+	/* RX statistics. */
+	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
+	    NULL, "RX MAC statistics");
+	children = SYSCTL_CHILDREN(tree);
+	ET_SYSCTL_STAT_ADD64(ctx, children, "bytes",
+	    &stats->rx_bytes, "Good bytes");
+	ET_SYSCTL_STAT_ADD64(ctx, children, "frames",
+	    &stats->rx_frames, "Good frames");
+	ET_SYSCTL_STAT_ADD32(ctx, children, "crc_errs",
+	    &stats->rx_crcerrs, "CRC errors");
+	ET_SYSCTL_STAT_ADD64(ctx, children, "mcast_frames",
+	    &stats->rx_mcast, "Multicast frames");
+	ET_SYSCTL_STAT_ADD64(ctx, children, "bcast_frames",
+	    &stats->rx_bcast, "Broadcast frames");
+	ET_SYSCTL_STAT_ADD32(ctx, children, "control",
+	    &stats->rx_control, "Control frames");
+	ET_SYSCTL_STAT_ADD32(ctx, children, "pause",
+	    &stats->rx_pause, "Pause frames");
+	ET_SYSCTL_STAT_ADD32(ctx, children, "unknown_control",
+	    &stats->rx_unknown_control, "Unknown control frames");
+	ET_SYSCTL_STAT_ADD32(ctx, children, "align_errs",
+	    &stats->rx_alignerrs, "Alignment errors");
+	ET_SYSCTL_STAT_ADD32(ctx, children, "len_errs",
+	    &stats->rx_lenerrs, "Frames with length mismatched");
+	ET_SYSCTL_STAT_ADD32(ctx, children, "code_errs",
+	    &stats->rx_codeerrs, "Frames with code error");
+	ET_SYSCTL_STAT_ADD32(ctx, children, "cs_errs",
+	    &stats->rx_cserrs, "Frames with carrier sense error");
+	ET_SYSCTL_STAT_ADD32(ctx, children, "runts",
+	    &stats->rx_runts, "Too short frames");
+	ET_SYSCTL_STAT_ADD64(ctx, children, "oversize",
+	    &stats->rx_oversize, "Oversized frames");
+	ET_SYSCTL_STAT_ADD32(ctx, children, "fragments",
+	    &stats->rx_fragments, "Fragmented frames");
+	ET_SYSCTL_STAT_ADD32(ctx, children, "jabbers",
+	    &stats->rx_jabbers, "Frames with jabber error");
+	ET_SYSCTL_STAT_ADD32(ctx, children, "drop",
+	    &stats->rx_drop, "Dropped frames");
+
+	/* TX statistics. */
+	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
+	    NULL, "TX MAC statistics");
+	children = SYSCTL_CHILDREN(tree);
+	ET_SYSCTL_STAT_ADD64(ctx, children, "bytes",
+	    &stats->tx_bytes, "Good bytes");
+	ET_SYSCTL_STAT_ADD64(ctx, children, "frames",
+	    &stats->tx_frames, "Good frames");
+	ET_SYSCTL_STAT_ADD64(ctx, children, "mcast_frames",
+	    &stats->tx_mcast, "Multicast frames");
+	ET_SYSCTL_STAT_ADD64(ctx, children, "bcast_frames",
+	    &stats->tx_bcast, "Broadcast frames");
+	ET_SYSCTL_STAT_ADD32(ctx, children, "pause",
+	    &stats->tx_pause, "Pause frames");
+	ET_SYSCTL_STAT_ADD32(ctx, children, "deferred",
+	    &stats->tx_deferred, "Deferred frames");
+	ET_SYSCTL_STAT_ADD32(ctx, children, "excess_deferred",
+	    &stats->tx_excess_deferred, "Excessively deferred frames");
+	ET_SYSCTL_STAT_ADD32(ctx, children, "single_colls",
+	    &stats->tx_single_colls, "Single collisions");
+	ET_SYSCTL_STAT_ADD32(ctx, children, "multi_colls",
+	    &stats->tx_multi_colls, "Multiple collisions");
+	ET_SYSCTL_STAT_ADD32(ctx, children, "late_colls",
+	    &stats->tx_late_colls, "Late collisions");
+	ET_SYSCTL_STAT_ADD32(ctx, children, "excess_colls",
+	    &stats->tx_excess_colls, "Excess collisions");
+	ET_SYSCTL_STAT_ADD32(ctx, children, "total_colls",
+	    &stats->tx_total_colls, "Total collisions");
+	ET_SYSCTL_STAT_ADD32(ctx, children, "pause_honored",
+	    &stats->tx_pause_honored, "Honored pause frames");
+	ET_SYSCTL_STAT_ADD32(ctx, children, "drop",
+	    &stats->tx_drop, "Dropped frames");
+	ET_SYSCTL_STAT_ADD32(ctx, children, "jabbers",
+	    &stats->tx_jabbers, "Frames with jabber errors");
+	ET_SYSCTL_STAT_ADD32(ctx, children, "crc_errs",
+	    &stats->tx_crcerrs, "Frames with CRC errors");
+	ET_SYSCTL_STAT_ADD32(ctx, children, "control",
+	    &stats->tx_control, "Control frames");
+	ET_SYSCTL_STAT_ADD64(ctx, children, "oversize",
+	    &stats->tx_oversize, "Oversized frames");
+	ET_SYSCTL_STAT_ADD32(ctx, children, "undersize",
+	    &stats->tx_undersize, "Undersized frames");
+	ET_SYSCTL_STAT_ADD32(ctx, children, "fragments",
+	    &stats->tx_fragments, "Fragmented frames");
 }
 
+#undef	ET_SYSCTL_STAT_ADD32
+#undef	ET_SYSCTL_STAT_ADD64
+
 static int
 et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS)
 {
@@ -2407,50 +2587,107 @@ back:
 }
 
 static void
-et_setmedia(struct et_softc *sc)
+et_stats_update(struct et_softc *sc)
 {
-	struct mii_data *mii = device_get_softc(sc->sc_miibus);
-	uint32_t cfg2, ctrl;
-
-	cfg2 = CSR_READ_4(sc, ET_MAC_CFG2);
-	cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII |
-		  ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM);
-	cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC |
-	    ((7 << ET_MAC_CFG2_PREAMBLE_LEN_SHIFT) &
-	    ET_MAC_CFG2_PREAMBLE_LEN_MASK);
-
-	ctrl = CSR_READ_4(sc, ET_MAC_CTRL);
-	ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII);
-
-	if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
-		cfg2 |= ET_MAC_CFG2_MODE_GMII;
-	} else {
-		cfg2 |= ET_MAC_CFG2_MODE_MII;
-		ctrl |= ET_MAC_CTRL_MODE_MII;
-	}
-
-	if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
-		cfg2 |= ET_MAC_CFG2_FDX;
-	else
-		ctrl |= ET_MAC_CTRL_GHDX;
-
-	CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl);
-	CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2);
+	struct ifnet *ifp;
+	struct et_hw_stats *stats;
+
+	stats = &sc->sc_stats;
+	stats->pkts_64 += CSR_READ_4(sc, ET_STAT_PKTS_64);
+	stats->pkts_65 += CSR_READ_4(sc, ET_STAT_PKTS_65_127);
+	stats->pkts_128 += CSR_READ_4(sc, ET_STAT_PKTS_128_255);
+	stats->pkts_256 += CSR_READ_4(sc, ET_STAT_PKTS_256_511);
+	stats->pkts_512 += CSR_READ_4(sc, ET_STAT_PKTS_512_1023);
+	stats->pkts_1024 += CSR_READ_4(sc, ET_STAT_PKTS_1024_1518);
+	stats->pkts_1519 += CSR_READ_4(sc, ET_STAT_PKTS_1519_1522);
+
+	stats->rx_bytes += CSR_READ_4(sc, ET_STAT_RX_BYTES);
+	stats->rx_frames += CSR_READ_4(sc, ET_STAT_RX_FRAMES);
+	stats->rx_crcerrs += CSR_READ_4(sc, ET_STAT_RX_CRC_ERR);
+	stats->rx_mcast += CSR_READ_4(sc, ET_STAT_RX_MCAST);
+	stats->rx_bcast += CSR_READ_4(sc, ET_STAT_RX_BCAST);
+	stats->rx_control += CSR_READ_4(sc, ET_STAT_RX_CTL);
+	stats->rx_pause += CSR_READ_4(sc, ET_STAT_RX_PAUSE);
+	stats->rx_unknown_control += CSR_READ_4(sc, ET_STAT_RX_UNKNOWN_CTL);
+	stats->rx_alignerrs += CSR_READ_4(sc, ET_STAT_RX_ALIGN_ERR);
+	stats->rx_lenerrs += CSR_READ_4(sc, ET_STAT_RX_LEN_ERR);
+	stats->rx_codeerrs += CSR_READ_4(sc, ET_STAT_RX_CODE_ERR);
+	stats->rx_cserrs += CSR_READ_4(sc, ET_STAT_RX_CS_ERR);
+	stats->rx_runts += CSR_READ_4(sc, ET_STAT_RX_RUNT);
+	stats->rx_oversize += CSR_READ_4(sc, ET_STAT_RX_OVERSIZE);
+	stats->rx_fragments += CSR_READ_4(sc, ET_STAT_RX_FRAG);
+	stats->rx_jabbers += CSR_READ_4(sc, ET_STAT_RX_JABBER);
+	stats->rx_drop += CSR_READ_4(sc, ET_STAT_RX_DROP);
+
+	stats->tx_bytes += CSR_READ_4(sc, ET_STAT_TX_BYTES);
+	stats->tx_frames += CSR_READ_4(sc, ET_STAT_TX_FRAMES);
+	stats->tx_mcast += CSR_READ_4(sc, ET_STAT_TX_MCAST);
+	stats->tx_bcast += CSR_READ_4(sc, ET_STAT_TX_BCAST);
+	stats->tx_pause += CSR_READ_4(sc, ET_STAT_TX_PAUSE);
+	stats->tx_deferred += CSR_READ_4(sc, ET_STAT_TX_DEFER);
+	stats->tx_excess_deferred += CSR_READ_4(sc, ET_STAT_TX_EXCESS_DEFER);
+	stats->tx_single_colls += CSR_READ_4(sc, ET_STAT_TX_SINGLE_COL);
+	stats->tx_multi_colls += CSR_READ_4(sc, ET_STAT_TX_MULTI_COL);
+	stats->tx_late_colls += CSR_READ_4(sc, ET_STAT_TX_LATE_COL);
+	stats->tx_excess_colls += CSR_READ_4(sc, ET_STAT_TX_EXCESS_COL);
+	stats->tx_total_colls += CSR_READ_4(sc, ET_STAT_TX_TOTAL_COL);
+	stats->tx_pause_honored += CSR_READ_4(sc, ET_STAT_TX_PAUSE_HONOR);
+	stats->tx_drop += CSR_READ_4(sc, ET_STAT_TX_DROP);
+	stats->tx_jabbers += CSR_READ_4(sc, ET_STAT_TX_JABBER);
+	stats->tx_crcerrs += CSR_READ_4(sc, ET_STAT_TX_CRC_ERR);
+	stats->tx_control += CSR_READ_4(sc, ET_STAT_TX_CTL);
+	stats->tx_oversize += CSR_READ_4(sc, ET_STAT_TX_OVERSIZE);
+	stats->tx_undersize += CSR_READ_4(sc, ET_STAT_TX_UNDERSIZE);
+	stats->tx_fragments += CSR_READ_4(sc, ET_STAT_TX_FRAG);
+
+	/* Update ifnet counters. */
+	ifp = sc->ifp;
+	ifp->if_opackets = (u_long)stats->tx_frames;
+	ifp->if_collisions = stats->tx_total_colls;
+	ifp->if_oerrors = stats->tx_drop + stats->tx_jabbers +
+	    stats->tx_crcerrs + stats->tx_excess_deferred +
+	    stats->tx_late_colls;
+	ifp->if_ipackets = (u_long)stats->rx_frames;
+	ifp->if_ierrors = stats->rx_crcerrs + stats->rx_alignerrs +
+	    stats->rx_lenerrs + stats->rx_codeerrs + stats->rx_cserrs +
+	    stats->rx_runts + stats->rx_jabbers + stats->rx_drop;
 }
 
-static void
-et_setup_rxdesc(struct et_rxbuf_data *rbd, int buf_idx, bus_addr_t paddr)
+static int
+et_suspend(device_t dev)
 {
-	struct et_rxdesc_ring *rx_ring = rbd->rbd_ring;
-	struct et_rxdesc *desc;
+	struct et_softc *sc;
+	uint32_t pmcfg;
 
-	MPASS(buf_idx < ET_RX_NDESC);
-	desc = &rx_ring->rr_desc[buf_idx];
+	sc = device_get_softc(dev);
+	ET_LOCK(sc);
+	if ((sc->ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
+		et_stop(sc);
+	/* Diable all clocks and put PHY into COMA. */
+	pmcfg = CSR_READ_4(sc, ET_PM);
+	pmcfg &= ~(EM_PM_GIGEPHY_ENB | ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE |
+	    ET_PM_RXCLK_GATE);
+	pmcfg |= ET_PM_PHY_SW_COMA;
+	CSR_WRITE_4(sc, ET_PM, pmcfg);
+	ET_UNLOCK(sc);
+	return (0);
+}
 
-	desc->rd_addr_hi = htole32(ET_ADDR_HI(paddr));
-	desc->rd_addr_lo = htole32(ET_ADDR_LO(paddr));
-	desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK);
+static int
+et_resume(device_t dev)
+{
+	struct et_softc *sc;
+	uint32_t pmcfg;
 
-	bus_dmamap_sync(rx_ring->rr_dtag, rx_ring->rr_dmap,
-			BUS_DMASYNC_PREWRITE);
+	sc = device_get_softc(dev);
+	ET_LOCK(sc);
+	/* Take PHY out of COMA and enable clocks. */
+	pmcfg = ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE;
+	if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0)
+		pmcfg |= EM_PM_GIGEPHY_ENB;
+	CSR_WRITE_4(sc, ET_PM, pmcfg);
+	if ((sc->ifp->if_flags & IFF_UP) != 0)
+		et_init_locked(sc);
+	ET_UNLOCK(sc);
+	return (0);
 }
diff --git a/sys/dev/et/if_etreg.h b/sys/dev/et/if_etreg.h
index 3a270c1..a314921 100644
--- a/sys/dev/et/if_etreg.h
+++ b/sys/dev/et/if_etreg.h
@@ -34,50 +34,15 @@
  * $DragonFly: src/sys/dev/netif/et/if_etreg.h,v 1.3 2007/10/23 14:28:42 sephe Exp $
  * $FreeBSD$
  */
-/*-
- * Portions of this code is derived from NetBSD which is covered by
- * the following license:
- *
- * Copyright (c) 2004, 2005 David Young.  All rights reserved.
- *
- * Programmed for NetBSD by David Young.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of David Young may not be used to endorse or promote
- *    products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
- * PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL David
- * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
- * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * $DragonFly: src/sys/sys/bitops.h,v 1.1 2007/10/14 04:15:17 sephe Exp $
- */
 
 #ifndef _IF_ETREG_H
 #define _IF_ETREG_H
 
-#define ET_MEM_TXSIZE_EX		182
-#define ET_MEM_RXSIZE_MIN		608
-#define ET_MEM_RXSIZE_DEFAULT		11216
-#define ET_MEM_SIZE			16384
-#define ET_MEM_UNIT			16
+#define	ET_MEM_TXSIZE_EX		182
+#define	ET_MEM_RXSIZE_MIN		608
+#define	ET_MEM_RXSIZE_DEFAULT		11216
+#define	ET_MEM_SIZE			16384
+#define	ET_MEM_UNIT			16
 
 /*
  * PCI registers
@@ -88,313 +53,366 @@
  * ET_PCIV_REPLAY_TIMER_{128,256} are from
  * PCI EXPRESS BASE SPECIFICATION, REV. 1.0a, Table 3-4
  */
-#define ET_PCIR_BAR			PCIR_BAR(0)
-
-#define ET_PCIR_DEVICE_CAPS		0x4c
-#define ET_PCIM_DEVICE_CAPS_MAX_PLSZ	0x7	/* Max playload size */
-#define ET_PCIV_DEVICE_CAPS_PLSZ_128	0x0
-#define ET_PCIV_DEVICE_CAPS_PLSZ_256	0x1
+#define	ET_PCIR_DEVICE_CAPS		0x4C
+#define	ET_PCIM_DEVICE_CAPS_MAX_PLSZ	0x7	/* Max playload size */
+#define	ET_PCIV_DEVICE_CAPS_PLSZ_128	0x0
+#define	ET_PCIV_DEVICE_CAPS_PLSZ_256	0x1
 
-#define ET_PCIR_DEVICE_CTRL		0x50
-#define ET_PCIM_DEVICE_CTRL_MAX_RRSZ	0x7000	/* Max read request size */
-#define ET_PCIV_DEVICE_CTRL_RRSZ_2K	0x4000
+#define	ET_PCIR_DEVICE_CTRL		0x50
+#define	ET_PCIM_DEVICE_CTRL_MAX_RRSZ	0x7000	/* Max read request size */
+#define	ET_PCIV_DEVICE_CTRL_RRSZ_2K	0x4000
 
-#define ET_PCIR_MAC_ADDR0		0xa4
-#define ET_PCIR_MAC_ADDR1		0xa8
+#define	ET_PCIR_MAC_ADDR0		0xA4
+#define	ET_PCIR_MAC_ADDR1		0xA8
 
-#define ET_PCIR_EEPROM_STATUS		0xb2	/* XXX undocumented */
-#define ET_PCIM_EEPROM_STATUS_ERROR	0x4c
+#define	ET_PCIR_EEPROM_STATUS		0xB2	/* XXX undocumented */
+#define	ET_PCIM_EEPROM_STATUS_ERROR	0x4C
 
-#define ET_PCIR_ACK_LATENCY		0xc0
-#define ET_PCIV_ACK_LATENCY_128		237
-#define ET_PCIV_ACK_LATENCY_256		416
+#define	ET_PCIR_ACK_LATENCY		0xC0
+#define	ET_PCIV_ACK_LATENCY_128		237
+#define	ET_PCIV_ACK_LATENCY_256		416
 
-#define ET_PCIR_REPLAY_TIMER		0xc2
-#define ET_REPLAY_TIMER_RX_L0S_ADJ	250	/* XXX infered from default */
-#define ET_PCIV_REPLAY_TIMER_128	(711 + ET_REPLAY_TIMER_RX_L0S_ADJ)
-#define ET_PCIV_REPLAY_TIMER_256	(1248 + ET_REPLAY_TIMER_RX_L0S_ADJ)
+#define	ET_PCIR_REPLAY_TIMER		0xC2
+#define	ET_REPLAY_TIMER_RX_L0S_ADJ	250	/* XXX infered from default */
+#define	ET_PCIV_REPLAY_TIMER_128	(711 + ET_REPLAY_TIMER_RX_L0S_ADJ)
+#define	ET_PCIV_REPLAY_TIMER_256	(1248 + ET_REPLAY_TIMER_RX_L0S_ADJ)
 
-#define ET_PCIR_L0S_L1_LATENCY		0xcf
+#define	ET_PCIR_L0S_L1_LATENCY		0xCF
 
 /*
  * CSR
  */
-#define ET_TXQUEUE_START		0x0000
-#define ET_TXQUEUE_END			0x0004
-#define ET_RXQUEUE_START		0x0008
-#define ET_RXQUEUE_END			0x000c
-#define ET_QUEUE_ADDR(addr)		(((addr) / ET_MEM_UNIT) - 1)
-#define ET_QUEUE_ADDR_START		0
-#define ET_QUEUE_ADDR_END		ET_QUEUE_ADDR(ET_MEM_SIZE)
-
-#define ET_PM				0x0010
-#define ET_PM_SYSCLK_GATE		0x00000008
-#define ET_PM_TXCLK_GATE		0x00000010
-#define ET_PM_RXCLK_GATE		0x00000020
-
-#define ET_INTR_STATUS			0x0018
-#define ET_INTR_MASK			0x001c
-
-#define ET_SWRST			0x0028
-#define ET_SWRST_TXDMA			0x00000001
-#define ET_SWRST_RXDMA			0x00000002
-#define ET_SWRST_TXMAC			0x00000004
-#define ET_SWRST_RXMAC			0x00000008
-#define ET_SWRST_MAC			0x00000010
-#define ET_SWRST_MAC_STAT		0x00000020
-#define ET_SWRST_MMC			0x00000040
-#define ET_SWRST_SELFCLR_DISABLE	0x80000000
-
-#define ET_MSI_CFG			0x0030
-
-#define ET_LOOPBACK			0x0034
-
-#define ET_TIMER			0x0038
-
-#define ET_TXDMA_CTRL			0x1000
-#define ET_TXDMA_CTRL_HALT		0x00000001
-#define ET_TXDMA_CTRL_CACHE_THR_MASK	0x000000F0
-#define ET_TXDMA_CTRL_SINGLE_EPKT	0x00000100	/* ??? */
-
-#define ET_TX_RING_HI			0x1004
-#define ET_TX_RING_LO			0x1008
-#define ET_TX_RING_CNT			0x100c
-
-#define ET_TX_STATUS_HI			0x101c
-#define ET_TX_STATUS_LO			0x1020
-
-#define ET_TX_READY_POS			0x1024
-#define ET_TX_READY_POS_INDEX_MASK	0x000003FF
-#define ET_TX_READY_POS_WRAP		0x00000400
-
-#define ET_TX_DONE_POS			0x1060
-#define ET_TX_DONE_POS_INDEX_MASK	0x0000003FF
-#define ET_TX_DONE_POS_WRAP		0x000000400
-
-#define ET_RXDMA_CTRL			0x2000
-#define ET_RXDMA_CTRL_HALT		0x00000001
-#define ET_RXDMA_CTRL_RING0_SIZE_MASK	0x00000300
-#define ET_RXDMA_CTRL_RING0_128		0x00000000	/* 127 */
-#define ET_RXDMA_CTRL_RING0_256		0x00000100	/* 255 */
-#define ET_RXDMA_CTRL_RING0_512		0x00000200	/* 511 */
-#define ET_RXDMA_CTRL_RING0_1024	0x00000300	/* 1023 */
-#define ET_RXDMA_CTRL_RING0_ENABLE	0x00000400
-#define ET_RXDMA_CTRL_RING1_SIZE_MASK	0x00001800
-#define ET_RXDMA_CTRL_RING1_2048	0x00000000	/* 2047 */
-#define ET_RXDMA_CTRL_RING1_4096	0x00000800	/* 4095 */
-#define ET_RXDMA_CTRL_RING1_8192	0x00001000	/* 8191 */
-#define ET_RXDMA_CTRL_RING1_16384	0x00001800	/* 16383 (9022?) */
-#define ET_RXDMA_CTRL_RING1_ENABLE	0x00002000
-#define ET_RXDMA_CTRL_HALTED		0x00020000
-
-#define ET_RX_STATUS_LO			0x2004
-#define ET_RX_STATUS_HI			0x2008
-
-#define ET_RX_INTR_NPKTS		0x200c
-#define ET_RX_INTR_DELAY		0x2010
-
-#define ET_RXSTAT_LO			0x2020
-#define ET_RXSTAT_HI			0x2024
-#define ET_RXSTAT_CNT			0x2028
-
-#define ET_RXSTAT_POS			0x2030
-#define ET_RXSTAT_POS_INDEX_MASK	0x00000FFF
-#define ET_RXSTAT_POS_WRAP		0x00001000
-
-#define ET_RXSTAT_MINCNT		0x2038
-
-#define ET_RX_RING0_LO			0x203c
-#define ET_RX_RING0_HI			0x2040
-#define ET_RX_RING0_CNT			0x2044
-
-#define ET_RX_RING0_POS			0x204c
-#define ET_RX_RING0_POS_INDEX_MASK	0x000003FF
-#define ET_RX_RING0_POS_WRAP		0x00000400
-
-#define ET_RX_RING0_MINCNT		0x2054
-
-#define ET_RX_RING1_LO			0x2058
-#define ET_RX_RING1_HI			0x205c
-#define ET_RX_RING1_CNT			0x2060
-
-#define ET_RX_RING1_POS			0x2068
-#define ET_RX_RING1_POS_INDEX		0x000003FF
-#define ET_RX_RING1_POS_WRAP		0x00000400
-
-#define ET_RX_RING1_MINCNT		0x2070
-
-#define ET_TXMAC_CTRL			0x3000
-#define ET_TXMAC_CTRL_ENABLE		0x00000001
-#define ET_TXMAC_CTRL_FC_DISABLE	0x00000008
-
-#define ET_TXMAC_FLOWCTRL		0x3010
-
-#define ET_RXMAC_CTRL			0x4000
-#define ET_RXMAC_CTRL_ENABLE		0x00000001
-#define ET_RXMAC_CTRL_NO_PKTFILT	0x00000004
-#define ET_RXMAC_CTRL_WOL_DISABLE	0x00000008
-
-#define ET_WOL_CRC			0x4004
-#define ET_WOL_SA_LO			0x4010
-#define ET_WOL_SA_HI			0x4014
-#define ET_WOL_MASK			0x4018
-
-#define ET_UCAST_FILTADDR1		0x4068
-#define ET_UCAST_FILTADDR2		0x406c
-#define ET_UCAST_FILTADDR3		0x4070
-
-#define ET_MULTI_HASH			0x4074
-
-#define ET_PKTFILT			0x4084
-#define ET_PKTFILT_BCAST		0x00000001
-#define ET_PKTFILT_MCAST		0x00000002
-#define ET_PKTFILT_UCAST		0x00000004
-#define ET_PKTFILT_FRAG			0x00000008
-#define ET_PKTFILT_MINLEN_MASK		0x007F0000
-#define ET_PKTFILT_MINLEN_SHIFT		16
-
-#define ET_RXMAC_MC_SEGSZ		0x4088
-#define ET_RXMAC_MC_SEGSZ_ENABLE	0x00000001
-#define ET_RXMAC_MC_SEGSZ_FC		0x00000002
-#define ET_RXMAC_MC_SEGSZ_MAX_MASK	0x000003FC
-#define ET_RXMAC_SEGSZ(segsz)		((segsz) / ET_MEM_UNIT)
-#define ET_RXMAC_CUT_THRU_FRMLEN	8074
-
-#define ET_RXMAC_MC_WATERMARK		0x408c
-#define ET_RXMAC_SPACE_AVL		0x4094
-
-#define ET_RXMAC_MGT			0x4098
-#define ET_RXMAC_MGT_PASS_ECRC		0x00000010
-#define ET_RXMAC_MGT_PASS_ELEN		0x00000020
-#define ET_RXMAC_MGT_PASS_ETRUNC	0x00010000
-#define ET_RXMAC_MGT_CHECK_PKT		0x00020000
-
-#define ET_MAC_CFG1			0x5000
-#define ET_MAC_CFG1_TXEN		0x00000001
-#define ET_MAC_CFG1_SYNC_TXEN		0x00000002
-#define ET_MAC_CFG1_RXEN		0x00000004
-#define ET_MAC_CFG1_SYNC_RXEN		0x00000008
-#define ET_MAC_CFG1_TXFLOW		0x00000010
-#define ET_MAC_CFG1_RXFLOW		0x00000020
-#define ET_MAC_CFG1_LOOPBACK		0x00000100
-#define ET_MAC_CFG1_RST_TXFUNC		0x00010000
-#define ET_MAC_CFG1_RST_RXFUNC		0x00020000
-#define ET_MAC_CFG1_RST_TXMC		0x00040000
-#define ET_MAC_CFG1_RST_RXMC		0x00080000
-#define ET_MAC_CFG1_SIM_RST		0x40000000
-#define ET_MAC_CFG1_SOFT_RST		0x80000000
-
-#define ET_MAC_CFG2			0x5004
-#define ET_MAC_CFG2_FDX			0x00000001
-#define ET_MAC_CFG2_CRC			0x00000002
-#define ET_MAC_CFG2_PADCRC		0x00000004
-#define ET_MAC_CFG2_LENCHK		0x00000010
-#define ET_MAC_CFG2_BIGFRM		0x00000020
-#define ET_MAC_CFG2_MODE_MII		0x00000100
-#define ET_MAC_CFG2_MODE_GMII		0x00000200
-#define ET_MAC_CFG2_PREAMBLE_LEN_MASK	0x0000F000
-#define ET_MAC_CFG2_PREAMBLE_LEN_SHIFT	12
-
-#define ET_IPG				0x5008
-#define ET_IPG_B2B_MASK			0x0000007F
-#define ET_IPG_MINIFG_MASK		0x0000FF00
-#define ET_IPG_NONB2B_2_MASK		0x007F0000
-#define ET_IPG_NONB2B_1_MASK		0x7F000000
-#define ET_IPG_B2B_SHIFT		0
-#define ET_IPG_MINIFG_SHIFT		8
-#define ET_IPG_NONB2B_2_SHIFT		16
-#define ET_IPG_NONB2B_1_SHIFT		24
-
-#define ET_MAC_HDX			0x500c
-#define ET_MAC_HDX_COLLWIN_MASK		0x000003FF
-#define ET_MAC_HDX_REXMIT_MAX_MASK	0x0000F000
-#define ET_MAC_HDX_EXC_DEFER		0x00010000
-#define ET_MAC_HDX_NOBACKOFF		0x00020000
-#define ET_MAC_HDX_BP_NOBACKOFF		0x00040000
-#define ET_MAC_HDX_ALT_BEB		0x00080000
-#define ET_MAC_HDX_ALT_BEB_TRUNC_MASK	0x00F00000
-#define ET_MAC_HDX_COLLWIN_SHIFT	0
-#define ET_MAC_HDX_REXMIT_MAX_SHIFT	12
-#define ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT	20
-
-#define ET_MAX_FRMLEN			0x5010
-
-#define ET_MII_CFG			0x5020
-#define ET_MII_CFG_CLKRST		0x00000007
-#define ET_MII_CFG_PREAMBLE_SUP		0x00000010
-#define ET_MII_CFG_SCAN_AUTOINC		0x00000020
-#define ET_MII_CFG_RST			0x80000000
-
-#define ET_MII_CMD			0x5024
-#define ET_MII_CMD_READ			0x00000001
-
-#define ET_MII_ADDR			0x5028
-#define ET_MII_ADDR_REG_MASK		0x0000001F
-#define ET_MII_ADDR_PHY_MASK		0x00001F00
-#define ET_MII_ADDR_REG_SHIFT		0
-#define ET_MII_ADDR_PHY_SHIFT		8
-
-#define ET_MII_CTRL			0x502c
-#define ET_MII_CTRL_VALUE_MASK		0x0000FFFF
-#define ET_MII_CTRL_VALUE_SHIFT		0
-
-#define ET_MII_STAT			0x5030
-#define ET_MII_STAT_VALUE_MASK		0x0000FFFF
-
-#define ET_MII_IND			0x5034
-#define ET_MII_IND_BUSY			0x00000001
-#define ET_MII_IND_INVALID		0x00000004
-
-#define ET_MAC_CTRL			0x5038
-#define ET_MAC_CTRL_MODE_MII		0x01000000
-#define ET_MAC_CTRL_LHDX		0x02000000
-#define ET_MAC_CTRL_GHDX		0x04000000
-
-#define ET_MAC_ADDR1			0x5040
-#define ET_MAC_ADDR2			0x5044
-
-#define ET_MMC_CTRL			0x7000
-#define ET_MMC_CTRL_ENABLE		0x00000001
-#define ET_MMC_CTRL_ARB_DISABLE		0x00000002
-#define ET_MMC_CTRL_RXMAC_DISABLE	0x00000004
-#define ET_MMC_CTRL_TXMAC_DISABLE	0x00000008
-#define ET_MMC_CTRL_TXDMA_DISABLE	0x00000010
-#define ET_MMC_CTRL_RXDMA_DISABLE	0x00000020
-#define ET_MMC_CTRL_FORCE_CE		0x00000040
+#define	ET_TXQUEUE_START		0x0000
+#define	ET_TXQUEUE_END			0x0004
+#define	ET_RXQUEUE_START		0x0008
+#define	ET_RXQUEUE_END			0x000C
+#define	ET_QUEUE_ADDR(addr)		(((addr) / ET_MEM_UNIT) - 1)
+#define	ET_QUEUE_ADDR_START		0
+#define	ET_QUEUE_ADDR_END		ET_QUEUE_ADDR(ET_MEM_SIZE)
+
+#define	ET_PM				0x0010
+#define	EM_PM_GIGEPHY_ENB		0x00000001
+#define	ET_PM_SYSCLK_GATE		0x00000008
+#define	ET_PM_TXCLK_GATE		0x00000010
+#define	ET_PM_RXCLK_GATE		0x00000020
+#define	ET_PM_PHY_SW_COMA		0x00000040
+
+#define	ET_INTR_STATUS			0x0018
+#define	ET_INTR_MASK			0x001C
+
+#define	ET_SWRST			0x0028
+#define	ET_SWRST_TXDMA			0x00000001
+#define	ET_SWRST_RXDMA			0x00000002
+#define	ET_SWRST_TXMAC			0x00000004
+#define	ET_SWRST_RXMAC			0x00000008
+#define	ET_SWRST_MAC			0x00000010
+#define	ET_SWRST_MAC_STAT		0x00000020
+#define	ET_SWRST_MMC			0x00000040
+#define	ET_SWRST_SELFCLR_DISABLE	0x80000000
+
+#define	ET_MSI_CFG			0x0030
+
+#define	ET_LOOPBACK			0x0034
+
+#define	ET_TIMER			0x0038
+
+#define	ET_TXDMA_CTRL			0x1000
+#define	ET_TXDMA_CTRL_HALT		0x00000001
+#define	ET_TXDMA_CTRL_CACHE_THR_MASK	0x000000F0
+#define	ET_TXDMA_CTRL_SINGLE_EPKT	0x00000100	/* ??? */
+
+#define	ET_TX_RING_HI			0x1004
+#define	ET_TX_RING_LO			0x1008
+#define	ET_TX_RING_CNT			0x100C
+
+#define	ET_TX_STATUS_HI			0x101C
+#define	ET_TX_STATUS_LO			0x1020
+
+#define	ET_TX_READY_POS			0x1024
+#define	ET_TX_READY_POS_INDEX_MASK	0x000003FF
+#define	ET_TX_READY_POS_WRAP		0x00000400
+
+#define	ET_TX_DONE_POS			0x1060
+#define	ET_TX_DONE_POS_INDEX_MASK	0x0000003FF
+#define	ET_TX_DONE_POS_WRAP		0x000000400
+
+#define	ET_RXDMA_CTRL			0x2000
+#define	ET_RXDMA_CTRL_HALT		0x00000001
+#define	ET_RXDMA_CTRL_RING0_SIZE_MASK	0x00000300
+#define	ET_RXDMA_CTRL_RING0_128		0x00000000	/* 127 */
+#define	ET_RXDMA_CTRL_RING0_256		0x00000100	/* 255 */
+#define	ET_RXDMA_CTRL_RING0_512		0x00000200	/* 511 */
+#define	ET_RXDMA_CTRL_RING0_1024	0x00000300	/* 1023 */
+#define	ET_RXDMA_CTRL_RING0_ENABLE	0x00000400
+#define	ET_RXDMA_CTRL_RING1_SIZE_MASK	0x00001800
+#define	ET_RXDMA_CTRL_RING1_2048	0x00000000	/* 2047 */
+#define	ET_RXDMA_CTRL_RING1_4096	0x00000800	/* 4095 */
+#define	ET_RXDMA_CTRL_RING1_8192	0x00001000	/* 8191 */
+#define	ET_RXDMA_CTRL_RING1_16384	0x00001800	/* 16383 (9022?) */
+#define	ET_RXDMA_CTRL_RING1_ENABLE	0x00002000
+#define	ET_RXDMA_CTRL_HALTED		0x00020000
+
+#define	ET_RX_STATUS_LO			0x2004
+#define	ET_RX_STATUS_HI			0x2008
+
+#define	ET_RX_INTR_NPKTS		0x200C
+#define	ET_RX_INTR_DELAY		0x2010
+
+#define	ET_RXSTAT_LO			0x2020
+#define	ET_RXSTAT_HI			0x2024
+#define	ET_RXSTAT_CNT			0x2028
+
+#define	ET_RXSTAT_POS			0x2030
+#define	ET_RXSTAT_POS_INDEX_MASK	0x00000FFF
+#define	ET_RXSTAT_POS_WRAP		0x00001000
+
+#define	ET_RXSTAT_MINCNT		0x2038
+
+#define	ET_RX_RING0_LO			0x203C
+#define	ET_RX_RING0_HI			0x2040
+#define	ET_RX_RING0_CNT			0x2044
+
+#define	ET_RX_RING0_POS			0x204C
+#define	ET_RX_RING0_POS_INDEX_MASK	0x000003FF
+#define	ET_RX_RING0_POS_WRAP		0x00000400
+
+#define	ET_RX_RING0_MINCNT		0x2054
+
+#define	ET_RX_RING1_LO			0x2058
+#define	ET_RX_RING1_HI			0x205C
+#define	ET_RX_RING1_CNT			0x2060
+
+#define	ET_RX_RING1_POS			0x2068
+#define	ET_RX_RING1_POS_INDEX		0x000003FF
+#define	ET_RX_RING1_POS_WRAP		0x00000400
+
+#define	ET_RX_RING1_MINCNT		0x2070
+
+#define	ET_TXMAC_CTRL			0x3000
+#define	ET_TXMAC_CTRL_ENABLE		0x00000001
+#define	ET_TXMAC_CTRL_FC_DISABLE	0x00000008
+
+#define	ET_TXMAC_FLOWCTRL		0x3010
+#define	ET_TXMAC_FLOWCTRL_CFPT_MASK	0x0000FFFF
+#define	ET_TXMAC_FLOWCTRL_CFEP_MASK	0xFFFF0000
+#define	ET_TXMAC_FLOWCTRL_CFPT_SHIFT	0
+
+#define	ET_TXMAC_BP_CTRL		0x3020
+#define	ET_TXMAC_BP_CTRL_XONXOFF	0x00000001
+#define	ET_TXMAC_BP_CTRL_REQ		0x00000002
+
+#define	ET_RXMAC_CTRL			0x4000
+#define	ET_RXMAC_CTRL_ENABLE		0x00000001
+#define	ET_RXMAC_CTRL_NO_PKTFILT	0x00000004
+#define	ET_RXMAC_CTRL_WOL_DISABLE	0x00000008
+
+#define	ET_WOL_CRC			0x4004
+#define	ET_WOL_SA_LO			0x4010
+#define	ET_WOL_SA_HI			0x4014
+#define	ET_WOL_MASK			0x4018
+
+#define	ET_UCAST_FILTADDR1		0x4068
+#define	ET_UCAST_FILTADDR2		0x406C
+#define	ET_UCAST_FILTADDR3		0x4070
+
+#define	ET_MULTI_HASH			0x4074
+
+#define	ET_PKTFILT			0x4084
+#define	ET_PKTFILT_BCAST		0x00000001
+#define	ET_PKTFILT_MCAST		0x00000002
+#define	ET_PKTFILT_UCAST		0x00000004
+#define	ET_PKTFILT_FRAG			0x00000008
+#define	ET_PKTFILT_MINLEN_MASK		0x007F0000
+#define	ET_PKTFILT_MINLEN_SHIFT		16
+
+#define	ET_RXMAC_MC_SEGSZ		0x4088
+#define	ET_RXMAC_MC_SEGSZ_ENABLE	0x00000001
+#define	ET_RXMAC_MC_SEGSZ_FC		0x00000002
+#define	ET_RXMAC_MC_SEGSZ_MAX_MASK	0x000003FC
+#define	ET_RXMAC_SEGSZ(segsz)		((segsz) / ET_MEM_UNIT)
+#define	ET_RXMAC_CUT_THRU_FRMLEN	8074
+
+#define	ET_RXMAC_MC_WATERMARK		0x408C
+#define	ET_RXMAC_SPACE_AVL		0x4094
+
+#define	ET_RXMAC_MGT			0x4098
+#define	ET_RXMAC_MGT_PASS_ECRC		0x00000010
+#define	ET_RXMAC_MGT_PASS_ELEN		0x00000020
+#define	ET_RXMAC_MGT_PASS_ETRUNC	0x00010000
+#define	ET_RXMAC_MGT_CHECK_PKT		0x00020000
+
+#define	ET_MAC_CFG1			0x5000
+#define	ET_MAC_CFG1_TXEN		0x00000001
+#define	ET_MAC_CFG1_SYNC_TXEN		0x00000002
+#define	ET_MAC_CFG1_RXEN		0x00000004
+#define	ET_MAC_CFG1_SYNC_RXEN		0x00000008
+#define	ET_MAC_CFG1_TXFLOW		0x00000010
+#define	ET_MAC_CFG1_RXFLOW		0x00000020
+#define	ET_MAC_CFG1_LOOPBACK		0x00000100
+#define	ET_MAC_CFG1_RST_TXFUNC		0x00010000
+#define	ET_MAC_CFG1_RST_RXFUNC		0x00020000
+#define	ET_MAC_CFG1_RST_TXMC		0x00040000
+#define	ET_MAC_CFG1_RST_RXMC		0x00080000
+#define	ET_MAC_CFG1_SIM_RST		0x40000000
+#define	ET_MAC_CFG1_SOFT_RST		0x80000000
+
+#define	ET_MAC_CFG2			0x5004
+#define	ET_MAC_CFG2_FDX			0x00000001
+#define	ET_MAC_CFG2_CRC			0x00000002
+#define	ET_MAC_CFG2_PADCRC		0x00000004
+#define	ET_MAC_CFG2_LENCHK		0x00000010
+#define	ET_MAC_CFG2_BIGFRM		0x00000020
+#define	ET_MAC_CFG2_MODE_MII		0x00000100
+#define	ET_MAC_CFG2_MODE_GMII		0x00000200
+#define	ET_MAC_CFG2_PREAMBLE_LEN_MASK	0x0000F000
+#define	ET_MAC_CFG2_PREAMBLE_LEN_SHIFT	12
+
+#define	ET_IPG				0x5008
+#define	ET_IPG_B2B_MASK			0x0000007F
+#define	ET_IPG_MINIFG_MASK		0x0000FF00
+#define	ET_IPG_NONB2B_2_MASK		0x007F0000
+#define	ET_IPG_NONB2B_1_MASK		0x7F000000
+#define	ET_IPG_B2B_SHIFT		0
+#define	ET_IPG_MINIFG_SHIFT		8
+#define	ET_IPG_NONB2B_2_SHIFT		16
+#define	ET_IPG_NONB2B_1_SHIFT		24
+
+#define	ET_MAC_HDX			0x500C
+#define	ET_MAC_HDX_COLLWIN_MASK		0x000003FF
+#define	ET_MAC_HDX_REXMIT_MAX_MASK	0x0000F000
+#define	ET_MAC_HDX_EXC_DEFER		0x00010000
+#define	ET_MAC_HDX_NOBACKOFF		0x00020000
+#define	ET_MAC_HDX_BP_NOBACKOFF		0x00040000
+#define	ET_MAC_HDX_ALT_BEB		0x00080000
+#define	ET_MAC_HDX_ALT_BEB_TRUNC_MASK	0x00F00000
+#define	ET_MAC_HDX_COLLWIN_SHIFT	0
+#define	ET_MAC_HDX_REXMIT_MAX_SHIFT	12
+#define	ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT	20
+
+#define	ET_MAX_FRMLEN			0x5010
+
+#define	ET_MII_CFG			0x5020
+#define	ET_MII_CFG_CLKRST		0x00000007
+#define	ET_MII_CFG_PREAMBLE_SUP		0x00000010
+#define	ET_MII_CFG_SCAN_AUTOINC		0x00000020
+#define	ET_MII_CFG_RST			0x80000000
+
+#define	ET_MII_CMD			0x5024
+#define	ET_MII_CMD_READ			0x00000001
+
+#define	ET_MII_ADDR			0x5028
+#define	ET_MII_ADDR_REG_MASK		0x0000001F
+#define	ET_MII_ADDR_PHY_MASK		0x00001F00
+#define	ET_MII_ADDR_REG_SHIFT		0
+#define	ET_MII_ADDR_PHY_SHIFT		8
+
+#define	ET_MII_CTRL			0x502C
+#define	ET_MII_CTRL_VALUE_MASK		0x0000FFFF
+#define	ET_MII_CTRL_VALUE_SHIFT		0
+
+#define	ET_MII_STAT			0x5030
+#define	ET_MII_STAT_VALUE_MASK		0x0000FFFF
+
+#define	ET_MII_IND			0x5034
+#define	ET_MII_IND_BUSY			0x00000001
+#define	ET_MII_IND_INVALID		0x00000004
+
+#define	ET_MAC_CTRL			0x5038
+#define	ET_MAC_CTRL_MODE_MII		0x01000000
+#define	ET_MAC_CTRL_LHDX		0x02000000
+#define	ET_MAC_CTRL_GHDX		0x04000000
+
+#define	ET_MAC_ADDR1			0x5040
+#define	ET_MAC_ADDR2			0x5044
+
+/* MAC statistics counters. */
+#define	ET_STAT_PKTS_64			0x6080
+#define	ET_STAT_PKTS_65_127		0x6084
+#define	ET_STAT_PKTS_128_255		0x6088
+#define	ET_STAT_PKTS_256_511		0x608C
+#define	ET_STAT_PKTS_512_1023		0x6090
+#define	ET_STAT_PKTS_1024_1518		0x6094
+#define	ET_STAT_PKTS_1519_1522		0x6098
+#define	ET_STAT_RX_BYTES		0x609C
+#define	ET_STAT_RX_FRAMES		0x60A0
+#define	ET_STAT_RX_CRC_ERR		0x60A4
+#define	ET_STAT_RX_MCAST		0x60A8
+#define	ET_STAT_RX_BCAST		0x60AC
+#define	ET_STAT_RX_CTL			0x60B0
+#define	ET_STAT_RX_PAUSE		0x60B4
+#define	ET_STAT_RX_UNKNOWN_CTL		0x60B8
+#define	ET_STAT_RX_ALIGN_ERR		0x60BC
+#define	ET_STAT_RX_LEN_ERR		0x60C0
+#define	ET_STAT_RX_CODE_ERR		0x60C4
+#define	ET_STAT_RX_CS_ERR		0x60C8
+#define	ET_STAT_RX_RUNT			0x60CC
+#define	ET_STAT_RX_OVERSIZE		0x60D0
+#define	ET_STAT_RX_FRAG			0x60D4
+#define	ET_STAT_RX_JABBER		0x60D8
+#define	ET_STAT_RX_DROP			0x60DC
+#define	ET_STAT_TX_BYTES		0x60E0
+#define	ET_STAT_TX_FRAMES		0x60E4
+#define	ET_STAT_TX_MCAST		0x60E8
+#define	ET_STAT_TX_BCAST		0x60EC
+#define	ET_STAT_TX_PAUSE		0x60F0
+#define	ET_STAT_TX_DEFER		0x60F4
+#define	ET_STAT_TX_EXCESS_DEFER		0x60F8
+#define	ET_STAT_TX_SINGLE_COL		0x60FC
+#define	ET_STAT_TX_MULTI_COL		0x6100
+#define	ET_STAT_TX_LATE_COL		0x6104
+#define	ET_STAT_TX_EXCESS_COL		0x6108
+#define	ET_STAT_TX_TOTAL_COL		0x610C
+#define	ET_STAT_TX_PAUSE_HONOR		0x6110
+#define	ET_STAT_TX_DROP			0x6114
+#define	ET_STAT_TX_JABBER		0x6118
+#define	ET_STAT_TX_CRC_ERR		0x611C
+#define	ET_STAT_TX_CTL			0x6120
+#define	ET_STAT_TX_OVERSIZE		0x6124
+#define	ET_STAT_TX_UNDERSIZE		0x6128
+#define	ET_STAT_TX_FRAG			0x612C
+
+#define	ET_MMC_CTRL			0x7000
+#define	ET_MMC_CTRL_ENABLE		0x00000001
+#define	ET_MMC_CTRL_ARB_DISABLE		0x00000002
+#define	ET_MMC_CTRL_RXMAC_DISABLE	0x00000004
+#define	ET_MMC_CTRL_TXMAC_DISABLE	0x00000008
+#define	ET_MMC_CTRL_TXDMA_DISABLE	0x00000010
+#define	ET_MMC_CTRL_RXDMA_DISABLE	0x00000020
+#define	ET_MMC_CTRL_FORCE_CE		0x00000040
 
 /*
  * Interrupts
  */
-#define ET_INTR_TXEOF			0x00000008
-#define ET_INTR_TXDMA_ERROR		0x00000010
-#define ET_INTR_RXEOF			0x00000020
-#define ET_INTR_RXRING0_LOW		0x00000040
-#define ET_INTR_RXRING1_LOW		0x00000080
-#define ET_INTR_RXSTAT_LOW		0x00000100
-#define ET_INTR_RXDMA_ERROR		0x00000200
-#define ET_INTR_TIMER			0x00004000
-#define ET_INTR_WOL			0x00008000
-#define ET_INTR_PHY			0x00010000
-#define ET_INTR_TXMAC			0x00020000
-#define ET_INTR_RXMAC			0x00040000
-#define ET_INTR_MAC_STATS		0x00080000
-#define ET_INTR_SLAVE_TO		0x00100000
-
-#define ET_INTRS			(ET_INTR_TXEOF | \
-					 ET_INTR_RXEOF | \
-					 ET_INTR_TIMER)
+#define	ET_INTR_TXDMA			0x00000008
+#define	ET_INTR_TXDMA_ERROR		0x00000010
+#define	ET_INTR_RXDMA			0x00000020
+#define	ET_INTR_RXRING0_LOW		0x00000040
+#define	ET_INTR_RXRING1_LOW		0x00000080
+#define	ET_INTR_RXSTAT_LOW		0x00000100
+#define	ET_INTR_RXDMA_ERROR		0x00000200
+#define	ET_INTR_TIMER			0x00004000
+#define	ET_INTR_WOL			0x00008000
+#define	ET_INTR_PHY			0x00010000
+#define	ET_INTR_TXMAC			0x00020000
+#define	ET_INTR_RXMAC			0x00040000
+#define	ET_INTR_MAC_STATS		0x00080000
+#define	ET_INTR_SLAVE_TO		0x00100000
+
+#define	ET_INTRS						\
+	(ET_INTR_TXDMA | ET_INTR_RXDMA | ET_INTR_TIMER |	\
+	 ET_INTR_TXDMA_ERROR | ET_INTR_RXDMA_ERROR)
 
 /*
  * RX ring position uses same layout
  */
-#define ET_RX_RING_POS_INDEX_MASK	0x000003FF
-#define ET_RX_RING_POS_WRAP		0x00000400
+#define	ET_RX_RING_POS_INDEX_MASK	0x000003FF
+#define	ET_RX_RING_POS_WRAP		0x00000400
 
 /*
  * PCI IDs
  */
-#define PCI_VENDOR_LUCENT		0x11c1
-#define PCI_PRODUCT_LUCENT_ET1310	0xed00		/* ET1310 10/100/1000M Ethernet */
-#define PCI_PRODUCT_LUCENT_ET1310_FAST	0xed01		/* ET1310 10/100M Ethernet */
+#define	PCI_VENDOR_LUCENT		0x11C1
+#define	PCI_PRODUCT_LUCENT_ET1310	0xED00		/* ET1310 10/100/1000M Ethernet */
+#define	PCI_PRODUCT_LUCENT_ET1310_FAST	0xED01		/* ET1310 10/100M Ethernet */
 
 #endif	/* !_IF_ETREG_H */
diff --git a/sys/dev/et/if_etvar.h b/sys/dev/et/if_etvar.h
index cc2ebcf..e2e30ea 100644
--- a/sys/dev/et/if_etvar.h
+++ b/sys/dev/et/if_etvar.h
@@ -38,66 +38,39 @@
 #ifndef _IF_ETVAR_H
 #define _IF_ETVAR_H
 
-/* DragonFly compatibility */
-#define EVL_ENCAPLEN		ETHER_VLAN_ENCAP_LEN
+#define	ET_RING_ALIGN		4096
+#define	ET_STATUS_ALIGN		8
+#define	ET_NSEG_MAX		32	/* XXX no limit actually */
+#define	ET_NSEG_SPARE		4
 
-/*
- * Allocate the right type of mbuf for the desired total length.
- */
-static __inline struct mbuf *
-m_getl(int len, int how, int type, int flags, int *psize)
-{
-	struct mbuf *m;
-	int size;
-
-	if (len >= MINCLSIZE) {
-		m = m_getcl(how, type, flags);
-		size = MCLBYTES;
-	} else if (flags & M_PKTHDR) {
-		m = m_gethdr(how, type);
-		size = MHLEN;
-	} else {
-		m = m_get(how, type);
-		size = MLEN;
-	}
-	if (psize != NULL)
-		*psize = size;
-	return (m);
-}
-
-
-#define ET_ALIGN		0x1000
-#define ET_NSEG_MAX		32	/* XXX no limit actually */
-#define ET_NSEG_SPARE		8
-
-#define ET_TX_NDESC		512
-#define ET_RX_NDESC		512
-#define ET_RX_NRING		2
-#define ET_RX_NSTAT		(ET_RX_NRING * ET_RX_NDESC)
-
-#define ET_TX_RING_SIZE		(ET_TX_NDESC * sizeof(struct et_txdesc))
-#define ET_RX_RING_SIZE		(ET_RX_NDESC * sizeof(struct et_rxdesc))
-#define ET_RXSTAT_RING_SIZE	(ET_RX_NSTAT * sizeof(struct et_rxstat))
-
-#define ET_JUMBO_FRAMELEN	(ET_MEM_SIZE - ET_MEM_RXSIZE_MIN -	\
+#define	ET_TX_NDESC		512
+#define	ET_RX_NDESC		512
+#define	ET_RX_NRING		2
+#define	ET_RX_NSTAT		(ET_RX_NRING * ET_RX_NDESC)
+
+#define	ET_TX_RING_SIZE		(ET_TX_NDESC * sizeof(struct et_txdesc))
+#define	ET_RX_RING_SIZE		(ET_RX_NDESC * sizeof(struct et_rxdesc))
+#define	ET_RXSTAT_RING_SIZE	(ET_RX_NSTAT * sizeof(struct et_rxstat))
+
+#define	ET_JUMBO_FRAMELEN	(ET_MEM_SIZE - ET_MEM_RXSIZE_MIN -	\
 				 ET_MEM_TXSIZE_EX)
-#define ET_JUMBO_MTU		(ET_JUMBO_FRAMELEN - ETHER_HDR_LEN -	\
+#define	ET_JUMBO_MTU		(ET_JUMBO_FRAMELEN - ETHER_HDR_LEN -	\
 				 EVL_ENCAPLEN - ETHER_CRC_LEN)
 
-#define ET_FRAMELEN(mtu)	(ETHER_HDR_LEN + EVL_ENCAPLEN + (mtu) +	\
-				 ETHER_CRC_LEN)
+#define	ET_FRAMELEN(mtu)	(ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +	\
+				 (mtu) + ETHER_CRC_LEN)
 
-#define ET_JSLOTS		(ET_RX_NDESC + 128)
-#define ET_JLEN			(ET_JUMBO_FRAMELEN + ETHER_ALIGN)
-#define ET_JUMBO_MEM_SIZE	(ET_JSLOTS * ET_JLEN)
+#define	ET_JSLOTS		(ET_RX_NDESC + 128)
+#define	ET_JLEN			(ET_JUMBO_FRAMELEN + ETHER_ALIGN)
+#define	ET_JUMBO_MEM_SIZE	(ET_JSLOTS * ET_JLEN)
 
-#define CSR_WRITE_4(sc, reg, val)	\
+#define	CSR_WRITE_4(sc, reg, val)	\
 	bus_write_4((sc)->sc_mem_res, (reg), (val))
-#define CSR_READ_4(sc, reg)		\
+#define	CSR_READ_4(sc, reg)		\
 	bus_read_4((sc)->sc_mem_res, (reg))
 
-#define ET_ADDR_HI(addr)	((uint64_t) (addr) >> 32)
-#define ET_ADDR_LO(addr)	((uint64_t) (addr) & 0xffffffff)
+#define	ET_ADDR_HI(addr)	((uint64_t) (addr) >> 32)
+#define	ET_ADDR_LO(addr)	((uint64_t) (addr) & 0xffffffff)
 
 struct et_txdesc {
 	uint32_t	td_addr_hi;
@@ -106,23 +79,23 @@ struct et_txdesc {
 	uint32_t	td_ctrl2;	/* ET_TDCTRL2_ */
 };
 
-#define ET_TDCTRL1_LEN_MASK	0x0000FFFF
-
-#define ET_TDCTRL2_LAST_FRAG	0x00000001
-#define ET_TDCTRL2_FIRST_FRAG	0x00000002
-#define ET_TDCTRL2_INTR		0x00000004
-#define ET_TDCTRL2_CTRL_WORD	0x00000008
-#define ET_TDCTRL2_HDX_BACKP	0x00000010
-#define ET_TDCTRL2_XMIT_PAUSE	0x00000020
-#define ET_TDCTRL2_FRAME_ERR	0x00000040
-#define ET_TDCTRL2_NO_CRC	0x00000080
-#define ET_TDCTRL2_MAC_OVRRD	0x00000100
-#define ET_TDCTRL2_PAD_PACKET	0x00000200
-#define ET_TDCTRL2_JUMBO_PACKET	0x00000400
-#define ET_TDCTRL2_INS_VLAN	0x00000800
-#define ET_TDCTRL2_CSUM_IP	0x00001000
-#define ET_TDCTRL2_CSUM_TCP	0x00002000
-#define ET_TDCTRL2_CSUM_UDP	0x00004000
+#define	ET_TDCTRL1_LEN_MASK	0x0000FFFF
+
+#define	ET_TDCTRL2_LAST_FRAG	0x00000001
+#define	ET_TDCTRL2_FIRST_FRAG	0x00000002
+#define	ET_TDCTRL2_INTR		0x00000004
+#define	ET_TDCTRL2_CTRL_WORD	0x00000008
+#define	ET_TDCTRL2_HDX_BACKP	0x00000010
+#define	ET_TDCTRL2_XMIT_PAUSE	0x00000020
+#define	ET_TDCTRL2_FRAME_ERR	0x00000040
+#define	ET_TDCTRL2_NO_CRC	0x00000080
+#define	ET_TDCTRL2_MAC_OVRRD	0x00000100
+#define	ET_TDCTRL2_PAD_PACKET	0x00000200
+#define	ET_TDCTRL2_JUMBO_PACKET	0x00000400
+#define	ET_TDCTRL2_INS_VLAN	0x00000800
+#define	ET_TDCTRL2_CSUM_IP	0x00001000
+#define	ET_TDCTRL2_CSUM_TCP	0x00002000
+#define	ET_TDCTRL2_CSUM_UDP	0x00004000
 
 struct et_rxdesc {
 	uint32_t	rd_addr_lo;
@@ -130,33 +103,56 @@ struct et_rxdesc {
 	uint32_t	rd_ctrl;	/* ET_RDCTRL_ */
 };
 
-#define ET_RDCTRL_BUFIDX_MASK	0x000003FF
+#define	ET_RDCTRL_BUFIDX_MASK	0x000003FF
 
 struct et_rxstat {
 	uint32_t	rxst_info1;
 	uint32_t	rxst_info2;	/* ET_RXST_INFO2_ */
 };
 
-#define ET_RXST_INFO2_LEN_MASK	0x0000FFFF
-#define ET_RXST_INFO2_LEN_SHIFT	0
-#define ET_RXST_INFO2_BUFIDX_MASK	0x03FF0000
-#define ET_RXST_INFO2_BUFIDX_SHIFT	16
-#define ET_RXST_INFO2_RINGIDX_MASK	0x0C000000
-#define ET_RXST_INFO2_RINGIDX_SHIFT	26
+#define	ET_RXST_INFO1_HASH_PASS		0x00000001
+#define	ET_RXST_INFO1_IPCSUM		0x00000002
+#define	ET_RXST_INFO1_IPCSUM_OK		0x00000004
+#define	ET_RXST_INFO1_TCPCSUM		0x00000008
+#define	ET_RXST_INFO1_TCPCSUM_OK	0x00000010
+#define	ET_RXST_INFO1_WOL		0x00000020
+#define	ET_RXST_INFO1_RXMAC_ERR		0x00000040
+#define	ET_RXST_INFO1_DROP		0x00000080
+#define	ET_RXST_INFO1_FRAME_TRUNC	0x00000100
+#define	ET_RXST_INFO1_JUMBO		0x00000200
+#define	ET_RXST_INFO1_VLAN		0x00000400
+#define	ET_RXST_INFO1_PREV_FRMAE_DROP	0x00010000
+#define	ET_RXST_INFO1_SHORT		0x00020000
+#define	ET_RXST_INFO1_BAD_CARRIER	0x00040000
+#define	ET_RXST_INFO1_CODE_ERR		0x00080000
+#define	ET_RXST_INFO1_CRC_ERR		0x00100000
+#define	ET_RXST_INFO1_LEN_MISMATCH	0x00200000
+#define	ET_RXST_INFO1_TOO_LONG		0x00400000
+#define	ET_RXST_INFO1_OK		0x00800000
+#define	ET_RXST_INFO1_MULTICAST		0x01000000
+#define	ET_RXST_INFO1_BROADCAST		0x02000000
+#define	ET_RXST_INFO1_DRIBBLE		0x04000000
+#define	ET_RXST_INFO1_CTL_FRAME		0x08000000
+#define	ET_RXST_INFO1_PAUSE_FRAME	0x10000000
+#define	ET_RXST_INFO1_UNKWN_CTL_FRAME	0x20000000
+#define	ET_RXST_INFO1_VLAN_TAG		0x40000000
+#define	ET_RXST_INFO1_LONG_EVENT	0x80000000
+
+#define	ET_RXST_INFO2_LEN_MASK		0x0000FFFF
+#define	ET_RXST_INFO2_LEN_SHIFT		0
+#define	ET_RXST_INFO2_BUFIDX_MASK	0x03FF0000
+#define	ET_RXST_INFO2_BUFIDX_SHIFT	16
+#define	ET_RXST_INFO2_RINGIDX_MASK	0x0C000000
+#define	ET_RXST_INFO2_RINGIDX_SHIFT	26
 
 struct et_rxstatus {
 	uint32_t	rxs_ring;
 	uint32_t	rxs_stat_ring;	/* ET_RXS_STATRING_ */
 };
 
-#define ET_RXS_STATRING_INDEX_MASK	0x0FFF0000
-#define ET_RXS_STATRING_INDEX_SHIFT	16
-#define ET_RXS_STATRING_WRAP	0x10000000
-
-struct et_dmamap_ctx {
-	int		nsegs;
-	bus_dma_segment_t *segs;
-};
+#define	ET_RXS_STATRING_INDEX_MASK	0x0FFF0000
+#define	ET_RXS_STATRING_INDEX_SHIFT	16
+#define	ET_RXS_STATRING_WRAP		0x10000000
 
 struct et_txbuf {
 	struct mbuf		*tb_mbuf;
@@ -166,7 +162,6 @@ struct et_txbuf {
 struct et_rxbuf {
 	struct mbuf		*rb_mbuf;
 	bus_dmamap_t		rb_dmap;
-	bus_addr_t		rb_paddr;
 };
 
 struct et_txstatus_data {
@@ -224,7 +219,6 @@ struct et_txbuf_data {
 
 struct et_softc;
 struct et_rxbuf_data;
-typedef int	(*et_newbuf_t)(struct et_rxbuf_data *, int, int);
 
 struct et_rxbuf_data {
 	struct et_rxbuf		rbd_buf[ET_RX_NDESC];
@@ -233,7 +227,58 @@ struct et_rxbuf_data {
 	struct et_rxdesc_ring	*rbd_ring;
 
 	int			rbd_bufsize;
-	et_newbuf_t		rbd_newbuf;
+	int			(*rbd_newbuf)(struct et_rxbuf_data *, int);
+	void			(*rbd_discard)(struct et_rxbuf_data *, int);
+};
+
+struct et_hw_stats {
+	/* RX/TX stats. */
+	uint64_t		pkts_64;
+	uint64_t		pkts_65;
+	uint64_t		pkts_128;
+	uint64_t		pkts_256;
+	uint64_t		pkts_512;
+	uint64_t		pkts_1024;
+	uint64_t		pkts_1519;
+	/* RX stats. */
+	uint64_t		rx_bytes;
+	uint64_t		rx_frames;
+	uint32_t		rx_crcerrs;
+	uint64_t		rx_mcast;
+	uint64_t		rx_bcast;
+	uint32_t		rx_control;
+	uint32_t		rx_pause;
+	uint32_t		rx_unknown_control;
+	uint32_t		rx_alignerrs;
+	uint32_t		rx_lenerrs;
+	uint32_t		rx_codeerrs;
+	uint32_t		rx_cserrs;
+	uint32_t		rx_runts;
+	uint64_t		rx_oversize;
+	uint32_t		rx_fragments;
+	uint32_t		rx_jabbers;
+	uint32_t		rx_drop;
+	/* TX stats. */
+	uint64_t		tx_bytes;
+	uint64_t		tx_frames;
+	uint64_t		tx_mcast;
+	uint64_t		tx_bcast;
+	uint32_t		tx_pause;
+	uint32_t		tx_deferred;
+	uint32_t		tx_excess_deferred;
+	uint32_t		tx_single_colls;
+	uint32_t		tx_multi_colls;
+	uint32_t		tx_late_colls;
+	uint32_t		tx_excess_colls;
+	uint32_t		tx_total_colls;
+	uint32_t		tx_pause_honored;
+	uint32_t		tx_drop;
+	uint32_t		tx_jabbers;
+	uint32_t		tx_crcerrs;
+	uint32_t		tx_control;
+	uint64_t		tx_oversize;
+	uint32_t		tx_undersize;
+	uint32_t		tx_fragments;
 };
 
 struct et_softc {
@@ -245,7 +290,6 @@ struct et_softc {
 	struct resource		*sc_irq_res;
 	struct resource		*sc_mem_res;
 
-	struct arpcom		arpcom;
 	int			sc_if_flags;
 	uint32_t		sc_flags;	/* ET_FLAG_ */
 	int			sc_expcap;
@@ -268,10 +312,15 @@ struct et_softc {
 	struct et_txstatus_data	sc_tx_status;
 
 	bus_dma_tag_t		sc_mbuf_dtag;
-	bus_dmamap_t		sc_mbuf_tmp_dmap;
+	bus_dma_tag_t		sc_rx_mini_tag;
+	bus_dmamap_t		sc_rx_mini_sparemap;
+	bus_dma_tag_t		sc_rx_tag;
+	bus_dmamap_t		sc_rx_sparemap;
+	bus_dma_tag_t		sc_tx_tag;
 	struct et_rxbuf_data	sc_rx_data[ET_RX_NRING];
 	struct et_txbuf_data	sc_tx_data;
 
+	struct et_hw_stats	sc_stats;
 	uint32_t		sc_tx;
 	uint32_t		sc_tx_intr;
 
@@ -284,13 +333,15 @@ struct et_softc {
 	uint32_t		sc_timer;
 };
 
-#define ET_LOCK(_sc)		mtx_lock(&(_sc)->sc_mtx)
-#define ET_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_mtx)
-#define ET_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
+#define	ET_LOCK(_sc)		mtx_lock(&(_sc)->sc_mtx)
+#define	ET_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_mtx)
+#define	ET_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
 
-#define ET_FLAG_PCIE		0x0001
-#define ET_FLAG_MSI		0x0002
-#define ET_FLAG_TXRX_ENABLED	0x0100
-#define ET_FLAG_JUMBO		0x0200
+#define	ET_FLAG_PCIE		0x0001
+#define	ET_FLAG_MSI		0x0002
+#define	ET_FLAG_FASTETHER	0x0004
+#define	ET_FLAG_TXRX_ENABLED	0x0100
+#define	ET_FLAG_JUMBO		0x0200
+#define	ET_FLAG_LINK		0x8000
 
 #endif	/* !_IF_ETVAR_H */
diff --git a/sys/dev/fb/fb.c b/sys/dev/fb/fb.c
index b201d29..183e20c 100644
--- a/sys/dev/fb/fb.c
+++ b/sys/dev/fb/fb.c
@@ -315,8 +315,7 @@ static device_method_t fb_methods[] = {
 	DEVMETHOD(device_probe,		fbprobe),
 	DEVMETHOD(device_attach,	fbattach),
 
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t fb_driver = {
diff --git a/sys/dev/fb/splash_txt.c b/sys/dev/fb/splash_txt.c
new file mode 100644
index 0000000..7bd9ff9
--- /dev/null
+++ b/sys/dev/fb/splash_txt.c
@@ -0,0 +1,135 @@
+/*-
+ * Copyright (c) 1999 Michael Smith <msmith@freebsd.org>
+ * Copyright (c) 1999 Kazutaka YOKOTA <yokota@freebsd.org>
+ * Copyright (c) 2005 Antony Mawer <antony@mawer.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/module.h>
+#include <sys/kernel.h>
+#include <sys/consio.h>
+#include <sys/fbio.h>
+
+#include <machine/pc/display.h>
+
+#include <dev/fb/fbreg.h>
+#include <dev/fb/splashreg.h>
+#include <dev/syscons/syscons.h>
+
+static int splash_on = FALSE;
+
+static int txt_init(video_adapter_t *adp);
+static int txt_end(video_adapter_t *adp);
+static int txt_splash(video_adapter_t * adp, const int on);
+
+/* These are rows by columns of the text-mode display device. */
+#define BIN_IMAGE_WIDTH		80
+#define BIN_IMAGE_HEIGHT	25
+
+static splash_decoder_t txt_decoder = {
+       .name = "splash_txt",
+       .init = txt_init,
+       .term = txt_end,
+       .splash = txt_splash,
+       .data_type = SPLASH_IMAGE,
+};
+
+SPLASH_DECODER(splash_txt, txt_decoder);
+
+static void
+draw_text_splash(sc_softc_t *sc)
+{
+	u_int x, y;
+	u_char ch, attr;
+	u_char *pdata = txt_decoder.data;
+
+	/* Init failed. */
+	if (txt_decoder.data == NULL)
+		return;
+	for (y = 0; y < BIN_IMAGE_HEIGHT; y++) {
+		for (x = 0; x < BIN_IMAGE_WIDTH; x++) {
+			ch = *pdata++;
+			attr = *pdata++;
+			sc_vtb_putc(&sc->cur_scp->scr,
+			    (y * sc->cur_scp->xsize) + x,
+			    sc->scr_map[ch], (int)attr << 8);
+		}
+	}
+}
+
+static int
+txt_init(video_adapter_t *adp)
+{
+
+	/* Ensure that the image data exists. */
+	if (txt_decoder.data == NULL || txt_decoder.data_size <= 0) {
+		printf("splash_txt: No ASCII bitmap file found\n");
+		return (ENODEV);
+	}
+	return (0);
+}
+
+static int
+txt_end(video_adapter_t *adp)
+{
+
+	return (0);
+}
+
+static int
+txt_splash(video_adapter_t *adp, const int on)
+{
+	sc_softc_t *sc;
+	scr_stat *scp;
+
+	sc = sc_find_softc(adp, NULL);
+	if (sc == NULL)
+		return (EAGAIN);
+	scp = sc->cur_scp;
+	if (on) {
+		if (!splash_on) {
+			if (adp->va_info.vi_flags & V_INFO_GRAPHICS)
+				return EAGAIN;
+			/* Clear screen and set border colour. */
+			sc_vtb_clear(&scp->scr, sc->scr_map[0x20],
+			    (FG_LIGHTGREY | BG_BLACK) << 8);
+			(*vidsw[adp->va_index]->set_hw_cursor)(adp, -1, -1);
+			sc_set_border(scp, 0);
+			splash_on = TRUE;
+			/* Display the splash screen. */
+			draw_text_splash(sc);
+		}
+		return (0);
+	} else {
+		/* The video mode will be restored by the caller. */
+		splash_on = FALSE;
+		return (0);
+	}
+}
+
+
diff --git a/sys/dev/fdc/fdc.c b/sys/dev/fdc/fdc.c
index 00cdcd6..52260c1 100644
--- a/sys/dev/fdc/fdc.c
+++ b/sys/dev/fdc/fdc.c
@@ -314,14 +314,14 @@ fdsettype(struct fd_data *fd, struct fd_type *ft)
 /*
  * Bus space handling (access to low-level IO).
  */
-__inline static void
+static inline void
 fdregwr(struct fdc_data *fdc, int reg, uint8_t v)
 {
 
 	bus_space_write_1(fdc->iot, fdc->ioh[reg], fdc->ioff[reg], v);
 }
 
-__inline static uint8_t
+static inline uint8_t
 fdregrd(struct fdc_data *fdc, int reg)
 {
 
diff --git a/sys/dev/fdt/fdt_common.c b/sys/dev/fdt/fdt_common.c
index d25715b..8702df2 100644
--- a/sys/dev/fdt/fdt_common.c
+++ b/sys/dev/fdt/fdt_common.c
@@ -74,13 +74,13 @@ fdt_immr_addr(vm_offset_t immr_va)
 	/*
 	 * Try to access the SOC node directly i.e. through /aliases/.
 	 */
-	if ((node = OF_finddevice("soc")) != 0)
+	if ((node = OF_finddevice("soc")) != -1)
 		if (fdt_is_compatible_strict(node, "simple-bus"))
 			goto moveon;
 	/*
 	 * Find the node the long way.
 	 */
-	if ((node = OF_finddevice("/")) == 0)
+	if ((node = OF_finddevice("/")) == -1)
 		return (ENXIO);
 
 	if ((node = fdt_find_compatible(node, "simple-bus", 1)) == 0)
@@ -576,7 +576,7 @@ fdt_get_mem_regions(struct mem_region *mr, int *mrcnt, uint32_t *memsize)
 
 	max_size = sizeof(reg);
 	memory = OF_finddevice("/memory");
-	if (memory <= 0) {
+	if (memory == -1) {
 		rv = ENXIO;
 		goto out;
 	}
diff --git a/sys/dev/fdt/fdt_pci.c b/sys/dev/fdt/fdt_pci.c
index 14aa270..7f0ddd3 100644
--- a/sys/dev/fdt/fdt_pci.c
+++ b/sys/dev/fdt/fdt_pci.c
@@ -46,9 +46,6 @@ __FBSDID("$FreeBSD$");
 #include "ofw_bus_if.h"
 #include "pcib_if.h"
 
-#define DEBUG
-#undef DEBUG
-
 #ifdef DEBUG
 #define debugf(fmt, args...) do { printf("%s(): ", __func__);	\
     printf(fmt,##args); } while (0)
diff --git a/sys/dev/fdt/fdt_powerpc.c b/sys/dev/fdt/fdt_powerpc.c
index ea614db..ac81c08 100644
--- a/sys/dev/fdt/fdt_powerpc.c
+++ b/sys/dev/fdt/fdt_powerpc.c
@@ -62,7 +62,7 @@ fdt_fixup_busfreq(phandle_t root)
 	 * This fixup uses /cpus/ bus-frequency prop value to set simple-bus
 	 * bus-frequency property.
 	 */
-	if ((cpus = OF_finddevice("/cpus")) == 0)
+	if ((cpus = OF_finddevice("/cpus")) == -1)
 		return;
 
 	if ((child = OF_child(cpus)) == 0)
diff --git a/sys/dev/fdt/fdtbus.c b/sys/dev/fdt/fdtbus.c
index a2530cd..577b159 100644
--- a/sys/dev/fdt/fdtbus.c
+++ b/sys/dev/fdt/fdtbus.c
@@ -46,9 +46,6 @@ __FBSDID("$FreeBSD$");
 #include "fdt_common.h"
 #include "ofw_bus_if.h"
 
-#define DEBUG
-#undef DEBUG
-
 #ifdef DEBUG
 #define debugf(fmt, args...) do { printf("%s(): ", __func__);	\
     printf(fmt,##args); } while (0)
@@ -177,7 +174,7 @@ fdtbus_attach(device_t dev)
 	u_long start, end;
 	int error;
 
-	if ((root = OF_peer(0)) == 0)
+	if ((root = OF_finddevice("/")) == -1)
 		panic("fdtbus_attach: no root node.");
 
 	sc = device_get_softc(dev);
diff --git a/sys/dev/fdt/simplebus.c b/sys/dev/fdt/simplebus.c
index 3fa1dd8..e6887b4 100644
--- a/sys/dev/fdt/simplebus.c
+++ b/sys/dev/fdt/simplebus.c
@@ -49,9 +49,6 @@ __FBSDID("$FreeBSD$");
 #include "fdt_common.h"
 #include "ofw_bus_if.h"
 
-#define DEBUG
-#undef DEBUG
-
 #ifdef DEBUG
 #define debugf(fmt, args...) do { printf("%s(): ", __func__);	\
     printf(fmt,##args); } while (0)
diff --git a/sys/dev/firewire/firewire.c b/sys/dev/firewire/firewire.c
index 490f39b..aa0f1aa 100644
--- a/sys/dev/firewire/firewire.c
+++ b/sys/dev/firewire/firewire.c
@@ -30,11 +30,11 @@
  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
- * 
- * $FreeBSD$
- *
  */
 
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/types.h>
@@ -128,9 +128,8 @@ static device_method_t firewire_methods[] = {
 
 	/* Bus interface */
 	DEVMETHOD(bus_add_child,	firewire_add_child),
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 char *linkspeed[] = {
 	"S100", "S200", "S400", "S800",
diff --git a/sys/dev/firewire/fwohci_pci.c b/sys/dev/firewire/fwohci_pci.c
index 0bb66a9..979f587 100644
--- a/sys/dev/firewire/fwohci_pci.c
+++ b/sys/dev/firewire/fwohci_pci.c
@@ -30,10 +30,11 @@
  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
- * 
- * $FreeBSD$
  */
 
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #define BOUNCE_BUFFER_TEST	0
 
 #include <sys/param.h>
@@ -536,9 +537,8 @@ static device_method_t fwohci_methods[] = {
 
 	/* Bus interface */
 	DEVMETHOD(bus_add_child,	fwohci_pci_add_child),
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t fwohci_driver = {
diff --git a/sys/dev/fxp/if_fxp.c b/sys/dev/fxp/if_fxp.c
index 62c8dc2..0255b91 100644
--- a/sys/dev/fxp/if_fxp.c
+++ b/sys/dev/fxp/if_fxp.c
@@ -1454,7 +1454,7 @@ fxp_encap(struct fxp_softc *sc, struct mbuf **m_head)
 			return (ENOBUFS);
 		}
 		tcp = (struct tcphdr *)(mtod(m, char *) + poff);
-		m = m_pullup(m, poff + sizeof(struct tcphdr) + tcp->th_off);
+		m = m_pullup(m, poff + (tcp->th_off << 2));
 		if (m == NULL) {
 			*m_head = NULL;
 			return (ENOBUFS);
diff --git a/sys/dev/gem/if_gem_pci.c b/sys/dev/gem/if_gem_pci.c
index c5e1acd..a3376fd 100644
--- a/sys/dev/gem/if_gem_pci.c
+++ b/sys/dev/gem/if_gem_pci.c
@@ -82,16 +82,12 @@ static device_method_t gem_pci_methods[] = {
 	/* Use the suspend handler here, it is all that is required. */
 	DEVMETHOD(device_shutdown,	gem_pci_suspend),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	gem_mii_readreg),
 	DEVMETHOD(miibus_writereg,	gem_mii_writereg),
 	DEVMETHOD(miibus_statchg,	gem_mii_statchg),
 
-	KOBJMETHOD_END
+	DEVMETHOD_END
 };
 
 static driver_t gem_pci_driver = {
diff --git a/sys/dev/gem/if_gem_sbus.c b/sys/dev/gem/if_gem_sbus.c
index 205285d..4265b8c 100644
--- a/sys/dev/gem/if_gem_sbus.c
+++ b/sys/dev/gem/if_gem_sbus.c
@@ -78,16 +78,12 @@ static device_method_t gem_sbus_methods[] = {
 	/* Use the suspend handler here, it is all that is required. */
 	DEVMETHOD(device_shutdown,	gem_sbus_suspend),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	gem_mii_readreg),
 	DEVMETHOD(miibus_writereg,	gem_mii_writereg),
 	DEVMETHOD(miibus_statchg,	gem_mii_statchg),
 
-	KOBJMETHOD_END
+	DEVMETHOD_END
 };
 
 static driver_t gem_sbus_driver = {
diff --git a/sys/dev/gpio/gpiobus.c b/sys/dev/gpio/gpiobus.c
index 54644a2..09ebe4e 100644
--- a/sys/dev/gpio/gpiobus.c
+++ b/sys/dev/gpio/gpiobus.c
@@ -229,7 +229,7 @@ gpiobus_detach(device_t dev)
 		return (err);
 
 	/* detach and delete all children */
-	device_delete_all_children(dev);
+	device_delete_children(dev);
 
 	if (sc->sc_pins_mapped) {
 		free(sc->sc_pins_mapped, M_DEVBUF);
@@ -458,7 +458,6 @@ static device_method_t gpiobus_methods[] = {
 	/* Bus interface */
 	DEVMETHOD(bus_add_child,	gpiobus_add_child),
 	DEVMETHOD(bus_print_child,	gpiobus_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
 	DEVMETHOD(bus_child_pnpinfo_str, gpiobus_child_pnpinfo_str),
 	DEVMETHOD(bus_child_location_str, gpiobus_child_location_str),
 	DEVMETHOD(bus_hinted_child,	gpiobus_hinted_child),
@@ -475,7 +474,7 @@ static device_method_t gpiobus_methods[] = {
 	DEVMETHOD(gpiobus_pin_set,	gpiobus_pin_set),
 	DEVMETHOD(gpiobus_pin_toggle,	gpiobus_pin_toggle),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 driver_t gpiobus_driver = {
diff --git a/sys/dev/gpio/gpioiic.c b/sys/dev/gpio/gpioiic.c
index e9611dd..2a6d093 100644
--- a/sys/dev/gpio/gpioiic.c
+++ b/sys/dev/gpio/gpioiic.c
@@ -48,15 +48,16 @@ __FBSDID("$FreeBSD$");
 
 #include "iicbb_if.h"
 
-#define	SCL_PIN		0	/* gpiobus mapped pin 6 */
-#define	SDA_PIN		1	/* gpiobus mapped pin 7 */
+#define	SCL_PIN_DEFAULT	0	/* default index of SCL pin on gpiobus */
+#define	SDA_PIN_DEFAULT	1
 
 struct gpioiic_softc 
 {
 	device_t	sc_dev;
 	device_t	sc_busdev;
-	struct mtx	sc_mtx;
 	struct cdev	*sc_leddev;
+	int		scl_pin;
+	int		sda_pin;
 };
 
 static int gpioiic_probe(device_t);
@@ -88,6 +89,12 @@ gpioiic_attach(device_t dev)
 
 	sc->sc_dev = dev;
 	sc->sc_busdev = device_get_parent(dev);
+	if (resource_int_value(device_get_name(dev),
+		device_get_unit(dev), "scl", &sc->scl_pin))
+		sc->scl_pin = SCL_PIN_DEFAULT;
+	if (resource_int_value(device_get_name(dev),
+		device_get_unit(dev), "sda", &sc->sda_pin))
+		sc->sda_pin = SDA_PIN_DEFAULT;
 
 	/* add generic bit-banging code */
 	bitbang = device_add_child(dev, "iicbb", -1);
@@ -105,9 +112,9 @@ gpioiic_reset_bus(device_t dev)
 {
 	struct gpioiic_softc		*sc = device_get_softc(dev);
 
-	GPIOBUS_PIN_SETFLAGS(sc->sc_busdev, sc->sc_dev, SDA_PIN,
+	GPIOBUS_PIN_SETFLAGS(sc->sc_busdev, sc->sc_dev, sc->sda_pin,
 	    GPIO_PIN_INPUT);
-	GPIOBUS_PIN_SETFLAGS(sc->sc_busdev, sc->sc_dev, SCL_PIN,
+	GPIOBUS_PIN_SETFLAGS(sc->sc_busdev, sc->sc_dev, sc->scl_pin,
 	    GPIO_PIN_INPUT);
 }
 
@@ -140,16 +147,14 @@ gpioiic_setsda(device_t dev, int val)
 {
 	struct gpioiic_softc		*sc = device_get_softc(dev);
 
-	GPIOBUS_LOCK_BUS(sc->sc_busdev);
 	if (val == 0) {
-		GPIOBUS_PIN_SET(sc->sc_busdev, sc->sc_dev, SDA_PIN, 0);
-		GPIOBUS_PIN_SETFLAGS(sc->sc_busdev, sc->sc_dev, SDA_PIN,
+		GPIOBUS_PIN_SET(sc->sc_busdev, sc->sc_dev, sc->sda_pin, 0);
+		GPIOBUS_PIN_SETFLAGS(sc->sc_busdev, sc->sc_dev, sc->sda_pin,
 		    GPIO_PIN_OUTPUT);
 	} else {
-		GPIOBUS_PIN_SETFLAGS(sc->sc_busdev, sc->sc_dev, SDA_PIN,
+		GPIOBUS_PIN_SETFLAGS(sc->sc_busdev, sc->sc_dev, sc->sda_pin,
 		    GPIO_PIN_INPUT);
 	}
-	GPIOBUS_UNLOCK_BUS(sc->sc_busdev);
 }
 
 static void
@@ -157,16 +162,14 @@ gpioiic_setscl(device_t dev, int val)
 {
 	struct gpioiic_softc		*sc = device_get_softc(dev);
 
-	GPIOBUS_LOCK_BUS(sc->sc_busdev);
 	if (val == 0) {
-		GPIOBUS_PIN_SET(sc->sc_busdev, sc->sc_dev, SCL_PIN, 0);
-		GPIOBUS_PIN_SETFLAGS(sc->sc_busdev, sc->sc_dev, SCL_PIN,
+		GPIOBUS_PIN_SET(sc->sc_busdev, sc->sc_dev, sc->scl_pin, 0);
+		GPIOBUS_PIN_SETFLAGS(sc->sc_busdev, sc->sc_dev, sc->scl_pin,
 		    GPIO_PIN_OUTPUT);
 	} else {
-		GPIOBUS_PIN_SETFLAGS(sc->sc_busdev, sc->sc_dev, SCL_PIN,
+		GPIOBUS_PIN_SETFLAGS(sc->sc_busdev, sc->sc_dev, sc->scl_pin,
 		    GPIO_PIN_INPUT);
 	}
-	GPIOBUS_UNLOCK_BUS(sc->sc_busdev);
 }
 
 static int
@@ -175,11 +178,9 @@ gpioiic_getscl(device_t dev)
 	struct gpioiic_softc		*sc = device_get_softc(dev);
 	unsigned int			val;
 
-	GPIOBUS_LOCK_BUS(sc->sc_busdev);
-	GPIOBUS_PIN_SETFLAGS(sc->sc_busdev, sc->sc_dev, SCL_PIN,
+	GPIOBUS_PIN_SETFLAGS(sc->sc_busdev, sc->sc_dev, sc->scl_pin,
 	    GPIO_PIN_INPUT);
-	GPIOBUS_PIN_GET(sc->sc_busdev, sc->sc_dev, SCL_PIN, &val);
-	GPIOBUS_UNLOCK_BUS(sc->sc_busdev);
+	GPIOBUS_PIN_GET(sc->sc_busdev, sc->sc_dev, sc->scl_pin, &val);
 
 	return ((int)val);
 }
@@ -190,11 +191,9 @@ gpioiic_getsda(device_t dev)
 	struct gpioiic_softc		*sc = device_get_softc(dev);
 	unsigned int			val;
 
-	GPIOBUS_LOCK_BUS(sc->sc_busdev);
-	GPIOBUS_PIN_SETFLAGS(sc->sc_busdev, sc->sc_dev, SDA_PIN,
+	GPIOBUS_PIN_SETFLAGS(sc->sc_busdev, sc->sc_dev, sc->sda_pin,
 	    GPIO_PIN_INPUT);
-	GPIOBUS_PIN_GET(sc->sc_busdev, sc->sc_dev, SDA_PIN, &val);
-	GPIOBUS_UNLOCK_BUS(sc->sc_busdev);
+	GPIOBUS_PIN_GET(sc->sc_busdev, sc->sc_dev, sc->sda_pin, &val);
 
 	return ((int)val);
 }
diff --git a/sys/dev/hifn/hifn7751.c b/sys/dev/hifn/hifn7751.c
index 2da5a9e..7e3a65f 100644
--- a/sys/dev/hifn/hifn7751.c
+++ b/sys/dev/hifn/hifn7751.c
@@ -113,16 +113,12 @@ static device_method_t hifn_methods[] = {
 	DEVMETHOD(device_resume,	hifn_resume),
 	DEVMETHOD(device_shutdown,	hifn_shutdown),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* crypto device methods */
 	DEVMETHOD(cryptodev_newsession,	hifn_newsession),
 	DEVMETHOD(cryptodev_freesession,hifn_freesession),
 	DEVMETHOD(cryptodev_process,	hifn_process),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 static driver_t hifn_driver = {
 	"hifn",
diff --git a/sys/dev/hme/if_hme_pci.c b/sys/dev/hme/if_hme_pci.c
index 9f68df2..d114fd8 100644
--- a/sys/dev/hme/if_hme_pci.c
+++ b/sys/dev/hme/if_hme_pci.c
@@ -93,16 +93,12 @@ static device_method_t hme_pci_methods[] = {
 	/* Can just use the suspend method here. */
 	DEVMETHOD(device_shutdown,	hme_pci_suspend),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	hme_mii_readreg),
 	DEVMETHOD(miibus_writereg,	hme_mii_writereg),
 	DEVMETHOD(miibus_statchg,	hme_mii_statchg),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t hme_pci_driver = {
diff --git a/sys/dev/hme/if_hme_sbus.c b/sys/dev/hme/if_hme_sbus.c
index 846ee11..946597e 100644
--- a/sys/dev/hme/if_hme_sbus.c
+++ b/sys/dev/hme/if_hme_sbus.c
@@ -95,16 +95,12 @@ static device_method_t hme_sbus_methods[] = {
 	/* Can just use the suspend method here. */
 	DEVMETHOD(device_shutdown,	hme_sbus_suspend),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	hme_mii_readreg),
 	DEVMETHOD(miibus_writereg,	hme_mii_writereg),
 	DEVMETHOD(miibus_statchg,	hme_mii_statchg),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t hme_sbus_driver = {
diff --git a/sys/dev/hpt27xx/README b/sys/dev/hpt27xx/README
new file mode 100644
index 0000000..57085f7
--- /dev/null
+++ b/sys/dev/hpt27xx/README
@@ -0,0 +1,196 @@
+RocketRAID Controller Driver for FreeBSD
+Copyright (C) 2011 HighPoint Technologies, Inc. All rights reserved.
+
+#############################################################################
+Revision History:
+   v1.0 2011-12-27
+        First source code release
+
+#############################################################################
+
+1. Overview
+---------------------
+  This package contains FreeBSD driver source code for HighPoint RocketRAID 
+  controller, include:
+  SAS Controller: RR271x, RR272x, RR274x, RR276x, RR278x.
+
+  NO WARRANTY
+
+  THE DRIVER SOURCE CODE HIGHPOINT PROVIDED IS FREE OF CHARGE, AND THERE IS
+  NO WARRANTY FOR THE PROGRAM. THERE ARE NO RESTRICTIONS ON THE USE OF THIS
+  FREE SOURCE CODE. HIGHPOINT DOES NOT PROVIDE ANY TECHNICAL SUPPORT IF THE
+  CODE HAS BEEN CHANGED FROM ORIGINAL SOURCE CODE.
+
+  LIMITATION OF LIABILITY
+
+  IN NO EVENT WILL HIGHPOINT BE LIABLE FOR DIRECT, INDIRECT, SPECIAL,
+  INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OF OR
+  INABILITY TO USE THIS PRODUCT OR DOCUMENTATION, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGES. IN PARTICULAR, HIGHPOINT SHALL NOT HAVE
+  LIABILITY FOR ANY HARDWARE, SOFTWARE, OR DATA STORED USED WITH THE
+  PRODUCT, INCLUDING THE COSTS OF REPAIRING, REPLACING, OR RECOVERING
+  SUCH HARDWARE, OR DATA.
+
+
+2. Rebuild the kernel with HighPoint RocketRAID support
+-----------------------------------------------
+
+  1) Install kernel source package and building tools. 
+  
+  2) Extract the driver files under the kernel source tree:
+
+     # cd /usr/src/sys/
+     # tar xvzf /your/path/to/hpt27xx-freebsd-src-v1.0-111227.tgz
+
+  3) Update the kernel configuration file to include the HighPoint source.
+     Assume the configure file is GENERIC, and new kernel configure file is 
+     MYKERNEL:
+
+     # cd i386/conf          (or amd64/conf for AMD64)
+     # cp GENERIC MYKERNEL
+
+  4) Edit MYKERNEL, and add the following line under "RAID controllers 
+     interfaced to the SCSI subsystem":
+
+          device  "hpt27xx"   #HighPoint RocketRAID
+
+  5) For i386 system, edit /usr/src/sys/conf/files.i386 and append the lines
+     shown below:
+
+          hpt27xx_lib.o optional    hpt27xx  \
+              dependency  "$S/dev/hpt27xx/i386-elf.hpt27xx_lib.o.uu" \
+              compile-with    "uudecode < $S/dev/hpt27xx/i386-elf.hpt27xx_lib.o.uu" \
+              no-implicit-rule
+
+          dev/hpt27xx/os_bsd.c      optional        hpt27xx
+          dev/hpt27xx/osm_bsd.c     optional        hpt27xx
+          dev/hpt27xx/hpt27xx_config.c      optional        hpt27xx
+
+     For amd64 system, edit /usr/src/sys/conf/files.amd64 and append the lines
+     shown below:
+
+          hpt27xx_lib.o optional    hpt27xx  \
+              dependency  "$S/dev/hpt27xx/amd64-elf.hpt27xx_lib.o.uu" \
+              compile-with    "uudecode < $S/dev/hpt27xx/amd64-elf.hpt27xx_lib.o.uu" \
+              no-implicit-rule
+
+          dev/hpt27xx/os_bsd.c      optional        hpt27xx
+          dev/hpt27xx/osm_bsd.c     optional        hpt27xx
+          dev/hpt27xx/hpt27xx_config.c      optional        hpt27xx
+
+  6) Rebuild and install the kernel:
+
+     a) for FreeBSD 5.x-i386/6.x-i386/7.x-i386/8.x-i386/9.x-i386:
+     
+        # cd /usr/src/sys/i386/conf/
+        # /usr/sbin/config MYKERNEL
+        # cd ../compile/MYKERNEL/
+        # make depend
+        # make 
+        # make install
+
+     b) for FreeBSD 5.x-amd64/6.x-amd64/7.x-amd64/8.x-amd64/9.x-amd64:
+
+        # cd /usr/src/sys/amd64/conf/
+        # /usr/sbin/config MYKERNEL
+        # cd ../compile/MYKERNEL/
+        # make depend
+        # make 
+        # make install
+
+     c) for FreeBSD 4.x:
+     
+        # cd /usr/src/sys/i386/conf/
+        # /usr/sbin/config MYKERNEL
+        # cd ../../compile/MYKERNEL/
+        # make depend
+        # make 
+        # make install
+
+    If the driver was previously configured as an auto-loaded module by
+    /boot/defaults/loader.conf, please remove the entry hpt27xx_load="YES"
+    from loader.conf to prevent the driver from being loaded twice.
+    
+  7) Reboot from the new kernel.
+
+
+3. Build/Load the driver as a kernel module
+------------------------------------------------
+
+  1) Install kernel source package and building tools. 
+  
+  2) Extract the driver files under the kernel source tree:
+    
+     # cd /usr/src/sys/
+     # tar xvzf /your/path/to/hpt27xx-freebsd-src-v1.0-111227.tgz
+
+
+  4) Build the driver module:
+    
+     # cd modules/hpt27xx
+     # make
+
+  5) Copy the driver module to the kernel module directory
+
+     For FreeBSD 4.x:
+     
+     # cp hpt27xx.ko /modules/
+
+     For FreeBSD 5.x/6.x/7.x/8.x/9.x:
+    
+     # cp hpt27xx.ko /boot/kernel/
+
+  6) Reboot and load the driver under loader prompt. e.g:
+
+        BTX loader 1.00  BTX version is 1.01
+        Console: internal video/keyboard
+        BIOS driver A: is disk0
+        BIOS driver C: is disk2
+        BIOS 636kB/74512kB available memory
+        
+        FreeBSD/i386 bootstrap loader, Revision 0.8
+        (mailto:jkh@narf.osd.bsdi.com, Sat Apr 21 08:46:19 GMT 2001)
+        Loading /boot/defaults/loader.conf
+        /kernel text=0x24f1db data=0x3007ec+0x2062c -
+        
+        Hit [Enter] to boot immediagely, or any other key for command prompt.
+        Booting [kernel] in 9 seconds¡­
+        
+         <-- press SPACE key here 
+        Type '?' for a list of commands, 'help' for more detailed help.
+        ok load hpt27xx
+        /modules/hpt27xx.ko text=0xf571 data=0x2c8+0x254
+        ok boot
+        
+     For FreeBSD 5.x/6.x/7.x/8.x/9.x, you can select 6 on the boot menu to get a loader
+     prompt.
+  
+  7) You can add a below line into /boot/defaults/loader.conf to load the
+     driver automatically:
+    
+           hpt27xx_load="YES"
+    
+     Please refer to the installation guide in HighPoint FreeBSD driver release 
+     package for more information.
+     
+
+#############################################################################
+Technical support and service
+
+  If you have questions about installing or using your HighPoint product,
+  check the user's guide or readme file first, and you will find answers to
+  most of your questions here. If you need further assistance, please
+  contact us. We offer the following support and information services:
+
+  1)  The HighPoint Web Site provides information on software upgrades,
+      answers to common questions, and other topics. The Web Site is
+      available from Internet 24 hours a day, 7 days a week, at
+      http://www.highpoint-tech.com.
+
+  2)  For technical support, send e-mail to support@highpoint-tech.com
+
+  NOTE: Before you send an e-mail, please visit our Web Site
+        (http://www.highpoint-tech.com) to check if there is a new or 
+        updated device driver for your system.
+
+$FreeBSD$
diff --git a/sys/dev/hpt27xx/amd64-elf.hpt27xx_lib.o.uu b/sys/dev/hpt27xx/amd64-elf.hpt27xx_lib.o.uu
new file mode 100644
index 0000000..8bb1b3a
--- /dev/null
+++ b/sys/dev/hpt27xx/amd64-elf.hpt27xx_lib.o.uu
@@ -0,0 +1,22893 @@
+begin 644 hpt27xx_lib.o
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+M``!`(0@``````,CW`````````0````$```!`(@@``````/#W`````````0``
+M``$```#0(P@``````"#X`````````0````$```#`)`@``````$CX````````
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+M``#0>`@``````#`'`0```````0````$````@?0@``````%`'`0```````0``
+M``$```!P?0@``````(@'`0```````0````$```!0?@@``````,@'`0``````
+M`0````$```#`?P@``````/@'`0```````0````$```!`@`@``````!@(`0``
+M`````0````$```#@@`@``````#`(`0```````0````$`````@@@``````%@(
+M`0```````0````$```"@@P@``````'@(`0```````0````$```#@@P@`````
+M`*`(`0```````0````$````PA0@``````,@(`0```````0````$```#`A@@`
+M``````@)`0```````0````$```!0B0@``````$@)`0```````0````$```"@
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+M``#@C`@``````-`)`0```````0````$````PC0@``````.@)`0```````0``
+M``$```"0C0@``````"@*`0```````0````$````@D@@``````&@*`0``````
+M`0````$```#`P0@``````*`*`0```````0````$```"@Q`@``````.`*`0``
+M`````0````$```!`R@@```````@+`0```````0````$```"PRP@``````"@+
+M`0```````0````$```!`S`@``````&@+`0```````0````$```!@SP@`````
+M`)`+`0```````0````$```!PT`@``````-`+`0```````0````$```#@TP@`
+M`````!`,`0```````0````$```#0VP@``````%`,`0```````0````$```#0
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+M``#@WP@``````-`,`0```````0````$```"0X0@``````/@,`0```````0``
+M``$```"PXP@``````"`-`0```````0````$```!@Y@@``````$`-`0``````
+M`0````$```"@Y@@``````&`-`0```````0````$`````YP@``````)`-`0``
+M`````0````$```!0Z`@``````+`-`0```````0````$```"PZ`@``````-@-
+M`0```````0````$````PZ0@````````.`0```````0````$````PZ@@`````
+M`"@.`0```````0````$```#PZ@@``````$@.`0```````0````$````PZP@`
+M`````&@.`0```````0````$````P[`@``````*`.`0```````0````$```!@
+M[`@``````,`.`0```````0````$```"0[`@``````.`.`0```````0````$`
+M``"P[`@````````/`0```````0````$```#@[`@``````"@/`0```````0``
+M``$```!@[@@``````%`/`0```````0````$```#@[@@``````&@/`0``````
+M`0````$````@[P@``````(@/`0```````0````$```#0[P@``````+`/`0``
+3`````0````$`````\@@`````````
+`
+end
diff --git a/sys/dev/hpt27xx/array.h b/sys/dev/hpt27xx/array.h
new file mode 100644
index 0000000..e22464c
--- /dev/null
+++ b/sys/dev/hpt27xx/array.h
@@ -0,0 +1,187 @@
+/*-
+ * Copyright (c) 2011 HighPoint Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <dev/hpt27xx/hpt27xx_config.h>
+
+#ifndef _HPT_ARRAY_H_
+#define _HPT_ARRAY_H_
+
+#define VERMAGIC_ARRAY 46
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define MAX_ARRAY_NAME 16
+
+#ifndef MAX_MEMBERS
+#define MAX_MEMBERS    16
+#endif
+
+#if MAX_MEMBERS<=16
+typedef HPT_U16 HPT_MMASK;
+#elif MAX_MEMBERS<=32
+typedef HPT_U32 HPT_MMASK;
+#elif MAX_MEMBERS<=64
+typedef HPT_U64 HPT_MMASK;
+#else 
+#error "MAX_MEMBERS too large"
+#endif
+
+#define HPT_MMASK_VALUE(x) (HPT_MMASK)((HPT_MMASK)1<<(x))
+
+#if MAX_MEMBERS<32
+#define HPT_MMASK_VALUE_SAFE(x) HPT_MMASK_VALUE(x)
+#else 
+#define HPT_MMASK_VALUE_SAFE(x) ((x)>=MAX_MEMBERS? (HPT_MMASK)0 : HPT_MMASK_VALUE(x))
+#endif
+
+#define MAX_REBUILD_SECTORS 128
+
+typedef struct _RAID_FLAGS {
+	HPT_UINT rf_need_initialize : 1;    
+	HPT_UINT rf_need_rebuild: 1;        
+	HPT_UINT rf_need_sync: 1;           
+	/* ioctl flags */
+	HPT_UINT rf_auto_rebuild: 1;
+	HPT_UINT rf_rebuilding: 1;          
+	HPT_UINT rf_verifying: 1;
+	HPT_UINT rf_initializing: 1;        
+	HPT_UINT rf_abort_verifying: 1;
+	HPT_UINT rf_raid15: 1;
+	HPT_UINT rf_v3_format : 1;
+	HPT_UINT rf_need_transform : 1;
+	HPT_UINT rf_transforming : 1;
+	HPT_UINT rf_abort_transform : 1;
+	HPT_UINT rf_log_write: 1;           
+} RAID_FLAGS;
+
+typedef struct transform_cmd_ext
+{
+	HPT_LBA lba;
+	HPT_U16 total_sectors;
+	HPT_U16 finished_sectors;
+} TRANSFORM_CMD_EXT , *PTRANSFORM_CMD_EXT;
+
+
+#define TO_MOVE_DATA        0
+#define TO_INITIALIZE       1
+#define TO_INITIALIZE_ONLY  2
+#define TO_MOVE_DATA_ONLY   3
+typedef struct hpt_transform
+{
+	HPT_U32 stamp;
+	PVDEV source;
+	PVDEV target;
+	struct list_head link;
+	HPT_U8 transform_from_tail;
+	struct tq_item task;
+	
+	struct lock_request lock;
+	TRANSFORM_CMD_EXT cmdext;
+
+	HPT_U64 transform_point;
+	HPT_U16 transform_sectors_per_step;
+	HPT_U8  operation;
+	HPT_U8  disabled; 
+} HPT_TRANSFORM, *PHPT_TRANSFORM;
+
+typedef struct hpt_array
+{
+	HPT_U32 array_stamp;
+	HPT_U32 data_stamp;  
+	HPT_U32 array_sn; 
+
+	HPT_U8  ndisk;
+	HPT_U8  block_size_shift;
+	HPT_U16 strip_width;
+	HPT_U8  sector_size_shift; /*sector size = 512B<<sector_size_shift*/
+	HPT_U8  jid; 
+	HPT_U8  reserved[2];
+
+	
+	HPT_MMASK outdated_members;
+	HPT_MMASK offline_members;
+
+	PVDEV member[MAX_MEMBERS];
+
+	RAID_FLAGS flags;
+
+	HPT_U64 rebuilt_sectors;
+
+	
+	HPT_U8 name[MAX_ARRAY_NAME];
+	PHPT_TRANSFORM transform;
+
+	TIME_RECORD create_time;        
+	HPT_U8  description[64];        
+	HPT_U8  create_manager[16];     
+
+#ifdef OS_SUPPORT_TASK
+	int floating_priority;
+	OSM_TASK ioctl_task;
+	IOCTL_ARG ioctl_arg;
+	
+	char ioctl_inbuf[sizeof(PVDEV)+sizeof(HPT_U64)+sizeof(HPT_U16)];
+	char ioctl_outbuf[sizeof(HPT_UINT)];
+#endif
+
+} HPT_ARRAY, *PHPT_ARRAY;
+
+#ifdef OS_SUPPORT_TASK
+void ldm_start_rebuild(struct _VDEV *pArray);
+#else 
+#define ldm_start_rebuild(pArray)
+#endif
+
+typedef struct _raw_partition{
+	struct _raw_partition * next;
+	__HPT_RAW_LBA start;
+	__HPT_RAW_LBA capacity;
+	PVDEV   vd_part;
+} RAW_PARTITION, *PRAW_PARTITION;
+
+typedef struct hpt_partiton
+{
+	PVDEV raw_disk;
+	__HPT_RAW_LBA des_location;
+	PRAW_PARTITION raw_part;
+	HPT_U8  del_mbr;
+	HPT_U8  reserved[3];
+} HPT_PARTITION, *PHPT_PARTITION;
+
+void ldm_check_array_online(PVDEV pArray);
+void ldm_generic_member_failed(PVDEV member);
+void ldm_sync_array_info(PVDEV pArray);
+void ldm_sync_array_stamp(PVDEV pArray);
+void ldm_add_spare_to_array(PVDEV pArray, PVDEV spare_partition);
+
+#if defined(__cplusplus)
+}
+#endif
+#endif
diff --git a/sys/dev/hpt27xx/him.h b/sys/dev/hpt27xx/him.h
new file mode 100644
index 0000000..58d4217
--- /dev/null
+++ b/sys/dev/hpt27xx/him.h
@@ -0,0 +1,496 @@
+/*-
+ * Copyright (c) 2011 HighPoint Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <dev/hpt27xx/hpt27xx_config.h>
+
+#ifndef _HPT_HIM_H_
+#define _HPT_HIM_H_
+
+#define VERMAGIC_HIM 55
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#include <dev/hpt27xx/list.h>
+
+#define SECTOR_TO_BYTE_SHIFT 9
+#define SECTOR_TO_BYTE(x)       ((HPT_U32)(x) << SECTOR_TO_BYTE_SHIFT)
+#define BYTE_TO_SECTOR(x)       ((x)>>SECTOR_TO_BYTE_SHIFT)
+
+typedef struct _PCI_ID
+{
+	HPT_U16 vid;
+	HPT_U16 did;
+	HPT_U32 subsys;
+	HPT_U8  rev;
+	HPT_U8  nbase;
+	HPT_U16 reserve;
+}
+PCI_ID;
+
+typedef struct _PCI_ADDRESS
+{
+	HPT_U8 tree;
+	HPT_U8 bus;
+	HPT_U8 device;
+	HPT_U8 function;
+}
+PCI_ADDRESS;
+
+typedef struct _HIM_ADAPTER_CONFIG
+{
+	PCI_ADDRESS pci_addr;
+	PCI_ID  pci_id;
+
+	HPT_U8  max_devices;
+	
+	HPT_U8  bProbeInInitializing:1;
+	
+	HPT_U8  bSpinupOneDevEachTime:1;	
+	
+	HPT_U8  bGlobalNcq:1;
+	HPT_U8  bSGPIOPartSupport:1;
+	 
+	HPT_U8  bNeedSASIdleTimer:1;
+	HPT_U8  reserved:3;
+
+	HPT_U8  bDevsPerBus;
+	HPT_U8  first_on_slot;
+
+	HPT_U8  bChipType;
+	HPT_U8  bChipIntrNum;
+	HPT_U8  bChipFlags;
+	HPT_U8  bNumBuses;
+
+	HPT_U8  szVendorID[36];
+	HPT_U8  szProductID[36];
+	HPT_U32 nvramSize;
+	HPT_U64 nvramAddress;
+	HPT_U8  slot_index;
+	HPT_U8  reserved2[11];
+}
+HIM_ADAPTER_CONFIG, *PHIM_ADAPTER_CONFIG;
+
+typedef struct _HIM_CHANNEL_CONFIG
+{
+	HPT_U32 io_port;
+	HPT_U32 ctl_port;
+} HIM_CHANNEL_CONFIG, *PHIM_CHANNEL_CONFIG;
+
+typedef struct _HIM_DEVICE_FLAGS
+{
+	HPT_UINT df_atapi               :1;   
+	HPT_UINT df_removable_drive     :1;
+	HPT_UINT df_on_line             :1;   
+	HPT_UINT df_reduce_mode         :1;   
+	HPT_UINT df_sata                :1;   
+	HPT_UINT df_on_pm_port          :1;   
+	HPT_UINT df_support_read_ahead  :1;
+	HPT_UINT df_read_ahead_enabled  :1;
+	HPT_UINT df_support_write_cache :1;
+	HPT_UINT df_write_cache_enabled :1;
+	HPT_UINT df_cdrom_device        :1;
+	HPT_UINT df_tape_device         :1;
+	HPT_UINT df_support_tcq         :1;
+	HPT_UINT df_tcq_enabled         :1;
+	HPT_UINT df_support_ncq         :1;
+	HPT_UINT df_ncq_enabled         :1;
+	HPT_UINT df_sas                 :1;
+	HPT_UINT df_in_enclosure        :1;
+	HPT_UINT df_ssd                 :1;
+} DEVICE_FLAGS, *PDEVICE_FLAGS;
+
+#pragma pack(1)
+typedef struct _IDENTIFY_DATA {
+	HPT_U16 GeneralConfiguration;
+	HPT_U16 NumberOfCylinders;
+	HPT_U16 Reserved1;
+	HPT_U16 NumberOfHeads;
+	HPT_U16 UnformattedBytesPerTrack;
+	HPT_U16 UnformattedBytesPerSector;
+	HPT_U8  SasAddress[8];
+	HPT_U16 SerialNumber[10];
+	HPT_U16 BufferType;
+	HPT_U16 BufferSectorSize;
+	HPT_U16 NumberOfEccBytes;
+	HPT_U16 FirmwareRevision[4];
+	HPT_U16 ModelNumber[20];
+	HPT_U8  MaximumBlockTransfer;
+	HPT_U8  VendorUnique2;
+	HPT_U16 DoubleWordIo;
+	HPT_U16 Capabilities;
+	HPT_U16 Reserved2;
+	HPT_U8  VendorUnique3;
+	HPT_U8  PioCycleTimingMode;
+	HPT_U8  VendorUnique4;
+	HPT_U8  DmaCycleTimingMode;
+	HPT_U16 TranslationFieldsValid;
+	HPT_U16 NumberOfCurrentCylinders;
+	HPT_U16 NumberOfCurrentHeads;
+	HPT_U16 CurrentSectorsPerTrack;
+	HPT_U32 CurrentSectorCapacity;
+	HPT_U16 CurrentMultiSectorSetting;
+	HPT_U32 UserAddressableSectors;
+	HPT_U8  SingleWordDMASupport;
+	HPT_U8  SingleWordDMAActive;
+	HPT_U8  MultiWordDMASupport;
+	HPT_U8  MultiWordDMAActive;
+	HPT_U8  AdvancedPIOModes;
+	HPT_U8  Reserved4;
+	HPT_U16 MinimumMWXferCycleTime;
+	HPT_U16 RecommendedMWXferCycleTime;
+	HPT_U16 MinimumPIOCycleTime;
+	HPT_U16 MinimumPIOCycleTimeIORDY;
+	HPT_U16 Reserved5[2];
+	HPT_U16 ReleaseTimeOverlapped;
+	HPT_U16 ReleaseTimeServiceCommand;
+	HPT_U16 MajorRevision;
+	HPT_U16 MinorRevision;
+	HPT_U16 MaxQueueDepth;
+	HPT_U16 SataCapability;
+	HPT_U16 Reserved6[9];
+	HPT_U16 CommandSupport;
+	HPT_U16 CommandEnable;
+	HPT_U16 UtralDmaMode;
+	HPT_U16 Reserved7[11];
+	HPT_U32 Lba48BitLow;
+	HPT_U32 Lba48BitHigh;
+	HPT_U16 Reserved8[23];
+	HPT_U16 SpecialFunctionsEnabled;
+	HPT_U16 Reserved9[128];
+}
+#ifdef __GNUC__
+__attribute__((packed))
+#endif
+IDENTIFY_DATA, *PIDENTIFY_DATA;
+#pragma pack()
+
+typedef struct _HIM_DEVICE_CONFIG
+{
+	HPT_U64 capacity;
+
+	DEVICE_FLAGS flags;
+
+	HPT_U8  path_id;
+	HPT_U8  target_id;
+	HPT_U8  max_queue_depth;
+	HPT_U8  spin_up_mode;
+
+	HPT_U8  reserved;
+	HPT_U8  transfer_mode;        
+	HPT_U8  bMaxShowMode;         
+	HPT_U8  bDeUsable_Mode;       
+
+	HPT_U16 max_sectors_per_cmd;
+
+	PIDENTIFY_DATA pIdentifyData;
+
+
+	HPT_U8  fixed_path_id; /*equals to phy id */
+}
+HIM_DEVICE_CONFIG, *PHIM_DEVICE_CONFIG;
+
+
+#define _DIT_MODE               0
+#define _DIT_601                1
+#define _DIT_READ_AHEAD         2
+#define _DIT_WRITE_CACHE        3
+#define _DIT_TCQ                4
+#define _DIT_NCQ                5
+#define _DIT_BEEP_OFF           6
+#define _DIT_SPIN_UP_MODE       7
+#define _DIT_IDLE_STANDBY       8
+#define _DIT_IDENTIFY           9
+
+#define SPIN_UP_MODE_NOSUPPORT 0
+#define SPIN_UP_MODE_FULL      1
+#define SPIN_UP_MODE_STANDBY   2
+
+struct tcq_control {
+	HPT_U8 enable;
+	HPT_U8 depth;
+};
+
+struct ncq_control {
+	HPT_U8 enable;
+	HPT_U8 depth;
+};
+
+typedef struct _HIM_ALTERABLE_DEV_INFO{
+	HPT_U8 type;
+	union {
+		HPT_U8 mode;
+		HPT_U8 enable_read_ahead;
+		HPT_U8 enable_read_cache;
+		HPT_U8 enable_write_cache;
+		struct tcq_control tcq;
+		struct ncq_control ncq;
+		void * adapter;
+		HPT_U8 spin_up_mode;
+		HPT_U8 idle_standby_timeout;
+		HPT_U8 identify_indicator;
+	}u;
+} HIM_ALTERABLE_DEV_INFO, *PHIM_ALTERABLE_DEV_INFO;
+
+struct _COMMAND;
+struct _IOCTL_ARG;
+
+typedef void (*PROBE_CALLBACK)(void *arg, void *dev, int index);
+
+typedef struct _HIM {
+	char *name;
+	struct _HIM *next;
+	HPT_UINT max_sg_descriptors;
+	#define _HIM_INTERFACE(_type, _fn, _args) _type (* _fn) _args;
+	#include <dev/hpt27xx/himfuncs.h>
+}
+HIM, *PHIM;
+
+
+#pragma pack(1)
+#ifdef SG_FLAG_EOT
+#error "don't use SG_FLAG_EOT with _SG.eot. clean the code!"
+#endif
+
+typedef struct _SG {
+	HPT_U32 size;
+	HPT_UINT eot; 
+	union {
+		HPT_U8 FAR * _logical; 
+		BUS_ADDRESS bus;
+	}
+	addr;
+}
+SG, *PSG;
+#pragma pack()
+
+typedef struct _AtaCommand
+{
+    HPT_U64     Lba;          
+    HPT_U16     nSectors;     
+    HPT_U16     pad;
+} AtaComm, *PAtaComm;
+
+#define ATA_CMD_NOP          0x0
+
+#define ATA_CMD_SET_FEATURES    0xef
+#define ATA_CMD_FLUSH           0xE7
+#define ATA_CMD_VERIFY          0x40
+#define ATA_CMD_STANDBY         0xe2
+#define ATA_CMD_READ_MULTI      0xC4
+#define ATA_CMD_READ_MULTI_EXT  0x29
+#define ATA_CMD_WRITE_MULTI     0xC5
+#define ATA_CMD_WRITE_MULTI_EXT 0x39
+#define ATA_CMD_WRITE_MULTI_FUA_EXT     0xCE
+
+#define ATA_CMD_READ_DMA        0xc8  /* IDE DMA read command           */
+#define ATA_CMD_WRITE_DMA       0xca  /* IDE DMA write command          */
+#define ATA_CMD_READ_DMA_EXT        0x25
+#define ATA_CMD_READ_QUEUE_EXT      0x26
+#define ATA_CMD_READ_MAX_ADDR       0x27
+#define ATA_CMD_READ_EXT            0x24
+#define ATA_CMD_VERIFY_EXT          0x42
+#define ATA_CMD_WRITE_DMA_EXT       0x35
+#define ATA_CMD_WRITE_QUEUE_EXT     0x36
+#define ATA_CMD_WRITE_EXT           0x34
+
+#define ATA_SET_FEATURES_XFER 0x3
+#define ATA_SECTOR_SIZE 512
+
+typedef struct _PassthroughCmd {
+	HPT_U16    bFeaturesReg;     
+	HPT_U16    bSectorCountReg;  
+	HPT_U16    bLbaLowReg;       
+	HPT_U16    bLbaMidReg;       
+	HPT_U16    bLbaHighReg;      
+	HPT_U8     bDriveHeadReg;    
+	HPT_U8     bCommandReg;      
+	HPT_U16    nSectors;         
+	HPT_U8    *pDataBuffer;      
+}
+PassthroughCmd;
+
+typedef struct _ScsiComm {
+	HPT_U8  cdbLength;
+	HPT_U8  senseLength; 
+	HPT_U8  scsiStatus; 
+	HPT_U8  reserve1;
+	HPT_U32 dataLength; 
+	HPT_U8 *cdb;
+	HPT_U8 *senseBuffer;
+}
+ScsiComm;
+
+
+#define CTRL_CMD_REBUILD 1
+#define CTRL_CMD_VERIFY  2
+#define CTRL_CMD_INIT    3
+
+
+typedef struct _R5ControlCmd {
+	HPT_U64  StripeLine;  
+	HPT_U16 Offset;       
+	HPT_U8  Command;      
+	HPT_U8  reserve1;
+}
+R5ControlCmd, *PR5ControlCmd;
+
+typedef struct _HPT_ADDRESS
+{
+	HPT_U8 * logical;
+	BUS_ADDRESS bus;
+}
+HPT_ADDRESS;
+
+
+typedef struct ctl_pages {
+	HPT_ADDRESS *pages;
+	HPT_UINT        page_size; 
+	HPT_UINT        npages;
+	HPT_UINT min_sg_descriptors; 
+} CONTROL_PAGES, *PCONTROL_PAGES;
+
+typedef struct _R1ControlCmd {
+	HPT_U64  Lba;
+	HPT_U16 nSectors;
+	HPT_U8  Command;      /* CTRL_CMD_XXX */
+	HPT_U8  reserve1;
+	PCONTROL_PAGES ctl_pages;  
+}
+R1ControlCmd, *PR1ControlCmd;
+
+typedef void (*TQ_PROC)(void *arg);
+
+struct tq_item {
+	TQ_PROC proc;
+	void *arg;
+	struct tq_item *next;
+};
+
+#define INIT_TQ_ITEM(t, p, a) \
+	do { (t)->proc = p; (t)->arg = a; (t)->next = 0; } while (0)
+
+typedef struct _COMMAND
+{
+	
+	struct _VBUS * vbus;
+
+	struct freelist *grplist; 
+	HPT_UINT grpcnt; 
+
+	
+	struct list_head q_link;
+	struct tq_item done_dpc;
+
+	HPT_UINT extsize;   
+	void *ext;
+
+	
+
+	void *target;      
+	void *priv;        
+	HPT_UPTR priv2;    
+
+	int priority;
+	struct lock_request *owned_lock; 
+	struct lock_request *lock_req;   
+	void (*dtor)(struct _COMMAND *, void *);
+	void *dtor_arg;
+
+	union{
+		AtaComm Ide;
+		PassthroughCmd Passthrough;
+		ScsiComm Scsi;
+		R5ControlCmd R5Control;
+		R1ControlCmd R1Control;
+	} uCmd;
+
+	HPT_U8 type; /* CMD_TYPE_* */
+
+	struct {
+		HPT_U8  physical_sg: 1;
+		HPT_U8  data_in: 1;
+		HPT_U8  data_out: 1;
+		HPT_U8  transform : 1;
+		HPT_U8  hard_flush: 2; 
+		HPT_U8  from_cc: 1;
+		HPT_U8  force_cc: 1;
+	} flags;
+
+	/* return status */
+	HPT_U8  Result;
+	/* retry count */
+	HPT_U8  RetryCount;
+
+	
+	PSG psg;
+
+	
+	int  (*buildsgl)(struct _COMMAND *cmd, PSG psg, int logical);
+	void (*done)(struct _COMMAND *cmd);
+}
+COMMAND, *PCOMMAND;
+
+/* command types */
+#define   CMD_TYPE_IO           0
+#define   CMD_TYPE_CONTROL      1
+#define   CMD_TYPE_ATAPI        2
+#define   CMD_TYPE_SCSI         CMD_TYPE_ATAPI
+#define   CMD_TYPE_PASSTHROUGH  3
+#define   CMD_TYPE_FLUSH        4
+#define   CMD_TYPE_IO_INDIRECT  0x80 
+
+/* flush command flags */
+#define   CF_HARD_FLUSH_CACHE   1
+#define   CF_HARD_FLUSH_STANDBY 2
+
+/* command return values */
+#define   RETURN_PENDING             0
+#define   RETURN_SUCCESS             1
+#define   RETURN_BAD_DEVICE          2
+#define   RETURN_BAD_PARAMETER       3
+#define   RETURN_WRITE_NO_DRQ        4
+#define   RETURN_DEVICE_BUSY         5
+#define   RETURN_INVALID_REQUEST     6
+#define   RETURN_SELECTION_TIMEOUT   7
+#define   RETURN_IDE_ERROR           8
+#define   RETURN_NEED_LOGICAL_SG     9
+#define   RETURN_NEED_PHYSICAL_SG    10
+#define   RETURN_RETRY               11
+#define   RETURN_DATA_ERROR          12
+#define   RETURN_BUS_RESET           13
+#define   RETURN_BAD_TRANSFER_LENGTH 14
+#define   RETURN_INSUFFICIENT_MEMORY 15 
+#define   RETURN_SECTOR_ERROR        16
+#define   RETURN_NEED_SPINUP         17
+
+#if defined(__cplusplus)
+}
+#endif
+#endif
diff --git a/sys/dev/hpt27xx/himfuncs.h b/sys/dev/hpt27xx/himfuncs.h
new file mode 100644
index 0000000..a14ff77
--- /dev/null
+++ b/sys/dev/hpt27xx/himfuncs.h
@@ -0,0 +1,107 @@
+/*-
+ * Copyright (c) 2011 HighPoint Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <dev/hpt27xx/hpt27xx_config.h>
+/* 
+ * define _HIM_INTERFACE before include this file, and
+ * undef it after include this file.
+ */
+
+
+#ifndef _HIM_INTERFACE
+#error "you must define _HIM_INTERFACE before this file"
+#endif
+
+_HIM_INTERFACE(HPT_BOOL, get_supported_device_id, (int index, PCI_ID *id))
+
+_HIM_INTERFACE(HPT_U8, get_controller_count, (PCI_ID *id, HPT_U8 *reached, PCI_ADDRESS *addr))
+
+
+_HIM_INTERFACE(HPT_UINT, get_adapter_size, (const PCI_ID *id))
+
+
+_HIM_INTERFACE(HPT_BOOL, create_adapter, (const PCI_ID *id, PCI_ADDRESS pciAddress, void *adapter, void *osext))
+
+_HIM_INTERFACE(void, get_adapter_config, (void *adapter, HIM_ADAPTER_CONFIG *config))
+
+_HIM_INTERFACE(HPT_BOOL, get_meminfo, (void *adapter))
+
+
+_HIM_INTERFACE(HPT_BOOL, adapter_on_same_vbus, (void *adapter1, void *adapter2))
+_HIM_INTERFACE(void, route_irq, (void *adapter, HPT_BOOL enable))
+
+
+_HIM_INTERFACE(HPT_BOOL, initialize, (void *adapter))
+
+
+_HIM_INTERFACE(HPT_UINT, get_device_size, (void *adapter))
+
+
+_HIM_INTERFACE(HPT_BOOL, probe_device, (void *adapter, int index, void *devhandle, PROBE_CALLBACK done, void *arg))
+_HIM_INTERFACE(void *, get_device, (void *adapter, int index))
+_HIM_INTERFACE(void, get_device_config, (void *dev, HIM_DEVICE_CONFIG *config))
+_HIM_INTERFACE(void, remove_device, (void *dev))
+
+_HIM_INTERFACE(void, reset_device, (void * dev, void (*done)(void *arg), void *arg))
+
+
+_HIM_INTERFACE(HPT_U32, get_cmdext_size, (void))
+
+_HIM_INTERFACE(void, queue_cmd, (void *dev, struct _COMMAND *cmd))
+
+
+_HIM_INTERFACE(int, read_write, (void *dev,HPT_LBA lba, HPT_U16 nsector, HPT_U8 *buffer, HPT_BOOL read))
+
+_HIM_INTERFACE(HPT_BOOL, intr_handler, (void *adapter))
+_HIM_INTERFACE(HPT_BOOL, intr_control, (void * adapter, HPT_BOOL enable))
+
+
+_HIM_INTERFACE(int, get_channel_config, (void * adapter, int index, PHIM_CHANNEL_CONFIG pInfo))
+_HIM_INTERFACE(int, set_device_info, (void * dev, PHIM_ALTERABLE_DEV_INFO pInfo))
+_HIM_INTERFACE(void, unplug_device, (void * dev))
+
+
+_HIM_INTERFACE(void, shutdown, (void *adapter))
+_HIM_INTERFACE(void, suspend, (void *adapter))
+_HIM_INTERFACE(void, resume, (void *adapter))
+_HIM_INTERFACE(void, release_adapter, (void *adapter))
+
+/*called after ldm_register_adapter*/
+_HIM_INTERFACE(HPT_BOOL, verify_adapter, (void *adapter))
+
+/* (optional) */
+_HIM_INTERFACE(void, ioctl, (void * adapter, struct _IOCTL_ARG *arg))
+_HIM_INTERFACE(int, compare_slot_seq, (void *adapter1, void *adapter2))
+_HIM_INTERFACE(int, get_enclosure_count, (void *adapter))
+_HIM_INTERFACE(int, get_enclosure_info, (void *adapter, int id, void *pinfo))
+_HIM_INTERFACE(int, get_enclosure_info_v2, (void *adapter, int id, void *pinfo))
+_HIM_INTERFACE(int, get_enclosure_info_v3, (void *adapter, int id, void *pinfo))
+
+_HIM_INTERFACE(HPT_BOOL, flash_access, (void *adapter, HPT_U32 offset, void *value, int size, HPT_BOOL reading))
+
+#undef _HIM_INTERFACE
diff --git a/sys/dev/hpt27xx/hpt27xx_config.c b/sys/dev/hpt27xx/hpt27xx_config.c
new file mode 100644
index 0000000..f87c7ee
--- /dev/null
+++ b/sys/dev/hpt27xx/hpt27xx_config.c
@@ -0,0 +1,67 @@
+/*-
+ * Copyright (c) 2011 HighPoint Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <dev/hpt27xx/hpt27xx_config.h>
+/****************************************************************************
+ * config.c - auto-generated file
+ ****************************************************************************/
+#include <dev/hpt27xx/os_bsd.h>
+
+extern int init_module_him_rr2720(void);
+extern int init_module_him_rr273x(void);
+extern int init_module_him_rr276x(void);
+extern int init_module_him_rr278x(void);
+extern int init_module_vdev_raw(void);
+extern int init_module_partition(void);
+extern int init_module_raid0(void);
+extern int init_module_raid1(void);
+extern int init_module_raid5(void);
+extern int init_module_jbod(void);
+
+int init_config(void)
+{
+	init_module_him_rr2720();
+	init_module_him_rr273x();
+	init_module_him_rr276x();
+	init_module_him_rr278x();
+	init_module_vdev_raw();
+	init_module_partition();
+	init_module_raid0();
+	init_module_raid1();
+	init_module_raid5();
+	init_module_jbod();
+	return 0;
+}
+
+char driver_name[] = "hpt27xx";
+char driver_name_long[] = "RocketRAID 27xx controller driver";
+char driver_ver[] = "v1.0 (" __DATE__ " " __TIME__ ")";
+int  osm_max_targets = 0xff;
+
+
+int os_max_cache_size = 0x1000000;
diff --git a/sys/dev/hpt27xx/hpt27xx_config.h b/sys/dev/hpt27xx/hpt27xx_config.h
new file mode 100644
index 0000000..dad8760
--- /dev/null
+++ b/sys/dev/hpt27xx/hpt27xx_config.h
@@ -0,0 +1,155 @@
+/*-
+ * Copyright (c) 2011 HighPoint Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef hpt27xx_CONFIG_H
+#define hpt27xx_CONFIG_H
+#define SUPPORT_ARRAY
+#define __KERNEL__ 1
+#define DRIVER_MINOR 16
+#define TARGETNAME hpt27xx
+#define __dummy_reg hpt27xx___dummy_reg
+#define __ldm_alloc_cmd hpt27xx___ldm_alloc_cmd
+#define delay_between_spinup hpt27xx_delay_between_spinup
+#define dmapool_active hpt27xx_dmapool_active
+#define dmapool_get_page hpt27xx_dmapool_get_page
+#define dmapool_get_page_at hpt27xx_dmapool_get_page_at
+#define dmapool_init hpt27xx_dmapool_init
+#define dmapool_make_order hpt27xx_dmapool_make_order
+#define dmapool_max_class_pages hpt27xx_dmapool_max_class_pages
+#define dmapool_put_page hpt27xx_dmapool_put_page
+#define dmapool_register_client hpt27xx_dmapool_register_client
+#define driver_name hpt27xx_driver_name
+#define driver_name_long hpt27xx_driver_name_long
+#define driver_ver hpt27xx_driver_ver
+#define freelist_get hpt27xx_freelist_get
+#define freelist_get_dma hpt27xx_freelist_get_dma
+#define freelist_put hpt27xx_freelist_put
+#define freelist_put_dma hpt27xx_freelist_put_dma
+#define freelist_reserve hpt27xx_freelist_reserve
+#define freelist_reserve_dma hpt27xx_freelist_reserve_dma
+#define gGlobalNcqFlag hpt27xx_gGlobalNcqFlag
+#define gProbeInInitializing hpt27xx_gProbeInInitializing
+#define gSGPIOPartSupport hpt27xx_gSGPIOPartSupport
+#define gSpinupOneDevEachTime hpt27xx_gSpinupOneDevEachTime
+#define g_legacy_mode hpt27xx_g_legacy_mode
+#define gautorebuild hpt27xx_gautorebuild
+#define grebuildpriority hpt27xx_grebuildpriority
+#define him_handle_to_vbus hpt27xx_him_handle_to_vbus
+#define him_list hpt27xx_him_list
+#define init_config hpt27xx_init_config
+#define init_module_him_rr2720 hpt27xx_init_module_him_rr2720
+#define init_module_him_rr273x hpt27xx_init_module_him_rr273x
+#define init_module_him_rr276x hpt27xx_init_module_him_rr276x
+#define init_module_him_rr278x hpt27xx_init_module_him_rr278x
+#define init_module_jbod hpt27xx_init_module_jbod
+#define init_module_partition hpt27xx_init_module_partition
+#define init_module_raid0 hpt27xx_init_module_raid0
+#define init_module_raid1 hpt27xx_init_module_raid1
+#define init_module_raid5 hpt27xx_init_module_raid5
+#define init_module_vdev_raw hpt27xx_init_module_vdev_raw
+#define ldm_acquire_lock hpt27xx_ldm_acquire_lock
+#define ldm_add_spare_to_array hpt27xx_ldm_add_spare_to_array
+#define ldm_alloc_cmds_R_6_55_75_46_64 hpt27xx_ldm_alloc_cmds_R_6_55_75_46_64
+#define ldm_alloc_cmds_from_list hpt27xx_ldm_alloc_cmds_from_list
+#define ldm_check_array_online hpt27xx_ldm_check_array_online
+#define ldm_create_vbus hpt27xx_ldm_create_vbus
+#define ldm_create_vdev hpt27xx_ldm_create_vdev
+#define ldm_event_notify hpt27xx_ldm_event_notify
+#define ldm_find_stamp hpt27xx_ldm_find_stamp
+#define ldm_find_target hpt27xx_ldm_find_target
+#define ldm_finish_cmd hpt27xx_ldm_finish_cmd
+#define ldm_free_cmds hpt27xx_ldm_free_cmds
+#define ldm_free_cmds_to_list hpt27xx_ldm_free_cmds_to_list
+#define ldm_generic_member_failed hpt27xx_ldm_generic_member_failed
+#define ldm_get_cmd_size hpt27xx_ldm_get_cmd_size
+#define ldm_get_device_id hpt27xx_ldm_get_device_id
+#define ldm_get_mem_info hpt27xx_ldm_get_mem_info
+#define ldm_get_next_vbus hpt27xx_ldm_get_next_vbus
+#define ldm_get_vbus_ext hpt27xx_ldm_get_vbus_ext
+#define ldm_get_vbus_size hpt27xx_ldm_get_vbus_size
+#define ldm_ide_fixstring hpt27xx_ldm_ide_fixstring
+#define ldm_idle hpt27xx_ldm_idle
+#define ldm_initialize_vbus_async hpt27xx_ldm_initialize_vbus_async
+#define ldm_intr hpt27xx_ldm_intr
+#define ldm_ioctl hpt27xx_ldm_ioctl
+#define ldm_on_timer hpt27xx_ldm_on_timer
+#define ldm_queue_cmd hpt27xx_ldm_queue_cmd
+#define ldm_queue_task hpt27xx_ldm_queue_task
+#define ldm_queue_vbus_dpc hpt27xx_ldm_queue_vbus_dpc
+#define ldm_register_adapter hpt27xx_ldm_register_adapter
+#define ldm_register_device hpt27xx_ldm_register_device
+#define ldm_register_him_R_6_55_75_46_64 hpt27xx_ldm_register_him_R_6_55_75_46_64
+#define ldm_register_vdev_class_R_6_55_75_46_64 hpt27xx_ldm_register_vdev_class_R_6_55_75_46_64
+#define ldm_release_lock hpt27xx_ldm_release_lock
+#define ldm_release_vbus hpt27xx_ldm_release_vbus
+#define ldm_release_vdev hpt27xx_ldm_release_vdev
+#define ldm_remove_timer hpt27xx_ldm_remove_timer
+#define ldm_request_timer hpt27xx_ldm_request_timer
+#define ldm_reset_vbus hpt27xx_ldm_reset_vbus
+#define ldm_resume hpt27xx_ldm_resume
+#define ldm_run hpt27xx_ldm_run
+#define ldm_set_autorebuild hpt27xx_ldm_set_autorebuild
+#define ldm_shutdown hpt27xx_ldm_shutdown
+#define ldm_suspend hpt27xx_ldm_suspend
+#define ldm_sync_array_info hpt27xx_ldm_sync_array_info
+#define ldm_sync_array_stamp hpt27xx_ldm_sync_array_stamp
+#define ldm_timer_probe_device hpt27xx_ldm_timer_probe_device
+#define ldm_unregister_device hpt27xx_ldm_unregister_device
+#define log_sector_repair hpt27xx_log_sector_repair
+#define num_drives_per_spinup hpt27xx_num_drives_per_spinup
+#define os_get_stamp hpt27xx_os_get_stamp
+#define os_get_vbus_seq hpt27xx_os_get_vbus_seq
+#define os_inb hpt27xx_os_inb
+#define os_inl hpt27xx_os_inl
+#define os_insw hpt27xx_os_insw
+#define os_inw hpt27xx_os_inw
+#define os_map_pci_bar hpt27xx_os_map_pci_bar
+#define os_max_cache_size hpt27xx_os_max_cache_size
+#define os_outb hpt27xx_os_outb
+#define os_outl hpt27xx_os_outl
+#define os_outsw hpt27xx_os_outsw
+#define os_outw hpt27xx_os_outw
+#define os_pci_readb hpt27xx_os_pci_readb
+#define os_pci_readl hpt27xx_os_pci_readl
+#define os_pci_readw hpt27xx_os_pci_readw
+#define os_pci_writeb hpt27xx_os_pci_writeb
+#define os_pci_writel hpt27xx_os_pci_writel
+#define os_pci_writew hpt27xx_os_pci_writew
+#define os_printk hpt27xx_os_printk
+#define os_query_remove_device hpt27xx_os_query_remove_device
+#define os_query_time hpt27xx_os_query_time
+#define os_request_timer hpt27xx_os_request_timer
+#define os_revalidate_device hpt27xx_os_revalidate_device
+#define os_schedule_task hpt27xx_os_schedule_task
+#define os_stallexec hpt27xx_os_stallexec
+#define os_unmap_pci_bar hpt27xx_os_unmap_pci_bar
+#define osm_max_targets hpt27xx_osm_max_targets
+#define pcicfg_read_dword hpt27xx_pcicfg_read_dword
+#define vbus_list hpt27xx_vbus_list
+#define vdev_queue_cmd hpt27xx_vdev_queue_cmd
+#endif
diff --git a/sys/dev/hpt27xx/hptintf.h b/sys/dev/hpt27xx/hptintf.h
new file mode 100644
index 0000000..c2a7b7f
--- /dev/null
+++ b/sys/dev/hpt27xx/hptintf.h
@@ -0,0 +1,2112 @@
+/*-
+ * Copyright (c) 2011 HighPoint Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <dev/hpt27xx/hpt27xx_config.h>
+
+#ifndef HPT_INTF_H
+#define HPT_INTF_H
+
+#if defined(__BIG_ENDIAN__)&&!defined(__BIG_ENDIAN_BITFIELD)
+#define __BIG_ENDIAN_BITFIELD
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef __GNUC__
+#define __attribute__(x)
+#endif
+
+#pragma pack(1)
+
+/*
+ * Version of this interface.
+ * The user mode application must first issue a hpt_get_version() call to
+ * check HPT_INTERFACE_VERSION. When an utility using newer version interface
+ * is used with old version drivers, it must call only the functions that
+ * driver supported.
+ * A new version interface should only add ioctl functions; it should implement
+ * all old version functions without change their definition.
+ */
+#define __this_HPT_INTERFACE_VERSION 0x02010000
+
+#ifndef HPT_INTERFACE_VERSION
+#error "You must define HPT_INTERFACE_VERSION you implemented"
+#endif
+
+#if HPT_INTERFACE_VERSION > __this_HPT_INTERFACE_VERSION
+#error "HPT_INTERFACE_VERSION is invalid"
+#endif
+
+/*
+ * DEFINITION
+ *   Logical device  --- a device that can be accessed by OS.
+ *   Physical device --- device attached to the controller.
+ *  A logical device can be simply a physical device.
+ *
+ * Each logical and physical device has a 32bit ID. GUI will use this ID
+ * to identify devices.
+ *   1. The ID must be unique.
+ *   2. The ID must be immutable. Once an ID is assigned to a device, it
+ * must not change when system is running and the device exists.
+ *   3. The ID of logical device must be NOT reusable. If a device is
+ * removed, other newly created logical device must not use the same ID.
+ *   4. The ID must not be zero or 0xFFFFFFFF.
+ */
+typedef HPT_U32 DEVICEID;
+
+/*
+ * logical device type.
+ * Identify array (logical device) and physical device.
+ */
+#define LDT_ARRAY   1
+#define LDT_DEVICE  2
+
+/*
+ * Array types
+ * GUI will treat all array as 1-level RAID. No RAID0/1 or RAID1/0.
+ * A RAID0/1 device is type AT_RAID1. A RAID1/0 device is type AT_RAID0.
+ * Their members may be another array of type RAID0 or RAID1.
+ */
+#define AT_UNKNOWN  0
+#define AT_RAID0    1
+#define AT_RAID1    2
+#define AT_RAID5    3
+#define AT_RAID6    4
+#define AT_RAID3    5
+#define AT_RAID4    6
+#define AT_JBOD     7
+#define AT_RAID1E   8
+
+/*
+ * physical device type
+ */
+#define PDT_UNKNOWN     0
+#define PDT_HARDDISK    1
+#define PDT_CDROM       2
+#define PDT_TAPE        3
+
+/*
+ * Some constants.
+ */
+#define MAX_NAME_LENGTH     36
+#define MAX_ARRAYNAME_LEN   16
+
+#define MAX_ARRAY_MEMBERS_V1 8
+
+#ifndef MAX_ARRAY_MEMBERS_V2
+#define MAX_ARRAY_MEMBERS_V2 16
+#endif
+
+#ifndef MAX_ARRAY_MEMBERS_V3
+#define MAX_ARRAY_MEMBERS_V3 64
+#endif
+
+/* keep definition for source code compatiblity */
+#define MAX_ARRAY_MEMBERS MAX_ARRAY_MEMBERS_V1
+
+/*
+ * io commands
+ * GUI use these commands to do IO on logical/physical devices.
+ */
+#define IO_COMMAND_READ     1
+#define IO_COMMAND_WRITE    2
+
+
+
+/*
+ * array flags
+ */
+#define ARRAY_FLAG_DISABLED         0x00000001 /* The array is disabled */
+#define ARRAY_FLAG_NEEDBUILDING     0x00000002 /* array data need to be rebuilt */
+#define ARRAY_FLAG_REBUILDING       0x00000004 /* array is in rebuilding process */
+#define ARRAY_FLAG_BROKEN           0x00000008 /* broken but may still working */
+#define ARRAY_FLAG_BOOTDISK         0x00000010 /* array has a active partition */
+
+#define ARRAY_FLAG_BOOTMARK         0x00000040 /* array has boot mark set */
+#define ARRAY_FLAG_NEED_AUTOREBUILD 0x00000080 /* auto-rebuild should start */
+#define ARRAY_FLAG_VERIFYING        0x00000100 /* is being verified */
+#define ARRAY_FLAG_INITIALIZING     0x00000200 /* is being initialized */
+#define ARRAY_FLAG_TRANSFORMING     0x00000400 /* tranform in progress */
+#define ARRAY_FLAG_NEEDTRANSFORM    0x00000800 /* array need tranform */
+#define ARRAY_FLAG_NEEDINITIALIZING 0x00001000 /* the array's initialization hasn't finished*/
+#define ARRAY_FLAG_BROKEN_REDUNDANT 0x00002000 /* broken but redundant (raid6) */
+#define ARRAY_FLAG_RAID15PLUS       0x80000000 /* display this RAID 1 as RAID 1.5 */
+/*
+ * device flags
+ */
+#define DEVICE_FLAG_DISABLED        0x00000001 /* device is disabled */
+#define DEVICE_FLAG_BOOTDISK        0x00000002 /* disk has a active partition */
+#define DEVICE_FLAG_BOOTMARK        0x00000004 /* disk has boot mark set */
+#define DEVICE_FLAG_WITH_601        0x00000008 /* has HPT601 connected */
+#define DEVICE_FLAG_SATA            0x00000010 /* SATA or SAS device */
+#define DEVICE_FLAG_ON_PM_PORT      0x00000020 /* PM port */
+#define DEVICE_FLAG_SAS             0x00000040 /* SAS device */
+#define DEVICE_FLAG_IN_ENCLOSURE    0x00000080 /* PathId is enclosure# */
+#define DEVICE_FLAG_UNINITIALIZED   0x00010000 /* device is not initialized, can't be used to create array */
+#define DEVICE_FLAG_LEGACY          0x00020000 /* single disk & mbr contains at least one partition */
+
+#define DEVICE_FLAG_IS_SPARE        0x80000000 /* is a spare disk */
+
+/*
+ * array states used by hpt_set_array_state()
+ */
+/* old defines */
+#define MIRROR_REBUILD_START    1
+#define MIRROR_REBUILD_ABORT    2
+#define MIRROR_REBUILD_COMPLETE 3
+/* new defines */
+#define AS_REBUILD_START 1
+#define AS_REBUILD_ABORT 2
+#define AS_REBUILD_PAUSE AS_REBUILD_ABORT
+#define AS_REBUILD_COMPLETE 3
+#define AS_VERIFY_START 4
+#define AS_VERIFY_ABORT 5
+#define AS_VERIFY_COMPLETE 6
+#define AS_INITIALIZE_START 7
+#define AS_INITIALIZE_ABORT 8
+#define AS_INITIALIZE_COMPLETE 9
+#define AS_VERIFY_FAILED 10
+#define AS_REBUILD_STOP 11
+#define AS_SAVE_STATE   12
+#define AS_TRANSFORM_START 13
+#define AS_TRANSFORM_ABORT 14
+
+/************************************************************************
+ * ioctl code
+ * It would be better if ioctl code are the same on different platforms,
+ * but we must not conflict with system defined ioctl code.
+ ************************************************************************/
+#if defined(LINUX) || defined(__FreeBSD_version) || defined(linux)
+#define HPT_CTL_CODE(x) (x+0xFF00)
+#define HPT_CTL_CODE_LINUX_TO_IOP(x) ((x)-0xff00)
+#elif defined(_MS_WIN32_) || defined(WIN32)
+
+#ifndef CTL_CODE
+#define CTL_CODE( DeviceType, Function, Method, Access ) \
+			(((DeviceType) << 16) | ((Access) << 14) | ((Function) << 2) | (Method))
+#endif
+#define HPT_CTL_CODE(x) CTL_CODE(0x370, 0x900+(x), 0, 0)
+#define HPT_CTL_CODE_WIN32_TO_IOP(x) ((((x) & 0xffff)>>2)-0x900)
+
+#else 
+#define HPT_CTL_CODE(x) (x)
+#endif
+
+#define HPT_IOCTL_GET_VERSION               HPT_CTL_CODE(0)
+#define HPT_IOCTL_GET_CONTROLLER_COUNT      HPT_CTL_CODE(1)
+#define HPT_IOCTL_GET_CONTROLLER_INFO       HPT_CTL_CODE(2)
+#define HPT_IOCTL_GET_CHANNEL_INFO          HPT_CTL_CODE(3)
+#define HPT_IOCTL_GET_LOGICAL_DEVICES       HPT_CTL_CODE(4)
+#define HPT_IOCTL_GET_DEVICE_INFO           HPT_CTL_CODE(5)
+#define HPT_IOCTL_CREATE_ARRAY              HPT_CTL_CODE(6)
+#define HPT_IOCTL_DELETE_ARRAY              HPT_CTL_CODE(7)
+#define HPT_IOCTL_ARRAY_IO                  HPT_CTL_CODE(8)
+#define HPT_IOCTL_DEVICE_IO                 HPT_CTL_CODE(9)
+#define HPT_IOCTL_GET_EVENT                 HPT_CTL_CODE(10)
+#define HPT_IOCTL_REBUILD_MIRROR            HPT_CTL_CODE(11)
+/* use HPT_IOCTL_REBUILD_DATA_BLOCK from now on */
+#define HPT_IOCTL_REBUILD_DATA_BLOCK HPT_IOCTL_REBUILD_MIRROR
+#define HPT_IOCTL_ADD_SPARE_DISK            HPT_CTL_CODE(12)
+#define HPT_IOCTL_REMOVE_SPARE_DISK         HPT_CTL_CODE(13)
+#define HPT_IOCTL_ADD_DISK_TO_ARRAY         HPT_CTL_CODE(14)
+#define HPT_IOCTL_SET_ARRAY_STATE           HPT_CTL_CODE(15)
+#define HPT_IOCTL_SET_ARRAY_INFO            HPT_CTL_CODE(16)
+#define HPT_IOCTL_SET_DEVICE_INFO           HPT_CTL_CODE(17)
+#define HPT_IOCTL_RESCAN_DEVICES            HPT_CTL_CODE(18)
+#define HPT_IOCTL_GET_DRIVER_CAPABILITIES   HPT_CTL_CODE(19)
+#define HPT_IOCTL_GET_601_INFO              HPT_CTL_CODE(20)
+#define HPT_IOCTL_SET_601_INFO              HPT_CTL_CODE(21)
+#define HPT_IOCTL_LOCK_DEVICE               HPT_CTL_CODE(22)
+#define HPT_IOCTL_UNLOCK_DEVICE             HPT_CTL_CODE(23)
+#define HPT_IOCTL_IDE_PASS_THROUGH          HPT_CTL_CODE(24)
+#define HPT_IOCTL_VERIFY_DATA_BLOCK         HPT_CTL_CODE(25)
+#define HPT_IOCTL_INITIALIZE_DATA_BLOCK     HPT_CTL_CODE(26)
+#define HPT_IOCTL_ADD_DEDICATED_SPARE       HPT_CTL_CODE(27)
+#define HPT_IOCTL_DEVICE_IO_EX              HPT_CTL_CODE(28)
+#define HPT_IOCTL_SET_BOOT_MARK             HPT_CTL_CODE(29)
+#define HPT_IOCTL_QUERY_REMOVE              HPT_CTL_CODE(30)
+#define HPT_IOCTL_REMOVE_DEVICES            HPT_CTL_CODE(31)
+#define HPT_IOCTL_CREATE_ARRAY_V2           HPT_CTL_CODE(32)
+#define HPT_IOCTL_GET_DEVICE_INFO_V2        HPT_CTL_CODE(33)
+#define HPT_IOCTL_SET_DEVICE_INFO_V2        HPT_CTL_CODE(34)
+#define HPT_IOCTL_REBUILD_DATA_BLOCK_V2     HPT_CTL_CODE(35)
+#define HPT_IOCTL_VERIFY_DATA_BLOCK_V2      HPT_CTL_CODE(36)
+#define HPT_IOCTL_INITIALIZE_DATA_BLOCK_V2  HPT_CTL_CODE(37)
+#define HPT_IOCTL_LOCK_DEVICE_V2            HPT_CTL_CODE(38)
+#define HPT_IOCTL_DEVICE_IO_V2              HPT_CTL_CODE(39)
+#define HPT_IOCTL_DEVICE_IO_EX_V2           HPT_CTL_CODE(40)
+#define HPT_IOCTL_CREATE_TRANSFORM          HPT_CTL_CODE(41)
+#define HPT_IOCTL_STEP_TRANSFORM            HPT_CTL_CODE(42)
+#define HPT_IOCTL_SET_VDEV_INFO             HPT_CTL_CODE(43)
+#define HPT_IOCTL_CALC_MAX_CAPACITY         HPT_CTL_CODE(44)
+#define HPT_IOCTL_INIT_DISKS                HPT_CTL_CODE(45)
+#define HPT_IOCTL_GET_DEVICE_INFO_V3        HPT_CTL_CODE(46)
+#define HPT_IOCTL_GET_CONTROLLER_INFO_V2    HPT_CTL_CODE(47)
+#define HPT_IOCTL_I2C_TRANSACTION           HPT_CTL_CODE(48)
+#define HPT_IOCTL_GET_PARAMETER_LIST        HPT_CTL_CODE(49)
+#define HPT_IOCTL_GET_PARAMETER             HPT_CTL_CODE(50)
+#define HPT_IOCTL_SET_PARAMETER             HPT_CTL_CODE(51)
+#define HPT_IOCTL_GET_DRIVER_CAPABILITIES_V2 HPT_CTL_CODE(52)
+#define HPT_IOCTL_GET_CHANNEL_INFO_V2       HPT_CTL_CODE(53)
+#define HPT_IOCTL_GET_CONTROLLER_INFO_V3    HPT_CTL_CODE(54)
+#define HPT_IOCTL_GET_DEVICE_INFO_V4        HPT_CTL_CODE(55)
+#define HPT_IOCTL_CREATE_ARRAY_V3           HPT_CTL_CODE(56)
+#define HPT_IOCTL_CREATE_TRANSFORM_V2       HPT_CTL_CODE(57)
+#define HPT_IOCTL_CALC_MAX_CAPACITY_V2      HPT_CTL_CODE(58)
+#define HPT_IOCTL_SCSI_PASSTHROUGH          HPT_CTL_CODE(59)
+#define HPT_IOCTL_GET_PHYSICAL_DEVICES      HPT_CTL_CODE(60)
+#define HPT_IOCTL_GET_ENCLOSURE_COUNT       HPT_CTL_CODE(61)
+#define HPT_IOCTL_GET_ENCLOSURE_INFO        HPT_CTL_CODE(62)
+#define HPT_IOCTL_GET_PERFMON_STATUS        HPT_CTL_CODE(63)
+#define HPT_IOCTL_SET_PERFMON_STATUS        HPT_CTL_CODE(64)
+#define HPT_IOCTL_GET_PERFMON_DATA          HPT_CTL_CODE(65)
+#define HPT_IOCTL_IDE_PASS_THROUGH_V2       HPT_CTL_CODE(66)
+#define HPT_IOCTL_GET_ENCLOSURE_INFO_V2    HPT_CTL_CODE(67)
+#define HPT_IOCTL_GET_ENCLOSURE_INFO_V3    HPT_CTL_CODE(68)
+
+#define HPT_IOCTL_GET_CONTROLLER_IDS        HPT_CTL_CODE(100)
+#define HPT_IOCTL_GET_DCB                   HPT_CTL_CODE(101)
+
+#define HPT_IOCTL_EPROM_IO                  HPT_CTL_CODE(102)
+#define HPT_IOCTL_GET_CONTROLLER_VENID      HPT_CTL_CODE(103)
+
+/************************************************************************
+ * shared data structures
+ ************************************************************************/
+
+/*
+ * Chip Type
+ */
+#define CHIP_TYPE_HPT366      1
+#define CHIP_TYPE_HPT368      2
+#define CHIP_TYPE_HPT370      3
+#define CHIP_TYPE_HPT370A     4
+#define CHIP_TYPE_HPT370B     5
+#define CHIP_TYPE_HPT374      6
+#define CHIP_TYPE_HPT372      7
+#define CHIP_TYPE_HPT372A     8
+#define CHIP_TYPE_HPT302      9
+#define CHIP_TYPE_HPT371      10
+#define CHIP_TYPE_HPT372N     11
+#define CHIP_TYPE_HPT302N     12
+#define CHIP_TYPE_HPT371N     13
+#define CHIP_TYPE_SI3112A     14
+#define CHIP_TYPE_ICH5        15
+#define CHIP_TYPE_ICH5R       16
+#define CHIP_TYPE_MV50XX      20
+#define CHIP_TYPE_MV60X1      21
+#define CHIP_TYPE_MV60X2      22
+#define CHIP_TYPE_MV70X2      23
+#define CHIP_TYPE_MV5182      24
+#define CHIP_TYPE_IOP331      31
+#define CHIP_TYPE_IOP333      32
+#define CHIP_TYPE_IOP341      33
+#define CHIP_TYPE_IOP348      34
+
+/*
+ * Chip Flags
+ */
+#define CHIP_SUPPORT_ULTRA_66   0x20
+#define CHIP_SUPPORT_ULTRA_100  0x40
+#define CHIP_HPT3XX_DPLL_MODE   0x80
+#define CHIP_SUPPORT_ULTRA_133  0x01
+#define CHIP_SUPPORT_ULTRA_150  0x02
+#define CHIP_MASTER             0x04
+#define CHIP_SUPPORT_SATA_300   0x08
+
+#define HPT_SPIN_UP_MODE_NOSUPPORT 0
+#define HPT_SPIN_UP_MODE_FULL      1
+#define HPT_SPIN_UP_MODE_STANDBY   2
+
+typedef struct _DRIVER_CAPABILITIES {
+	HPT_U32 dwSize;
+
+	HPT_U8 MaximumControllers;           /* maximum controllers the driver can support */
+	HPT_U8 SupportCrossControllerRAID;   /* 1-support, 0-not support */
+	HPT_U8 MinimumBlockSizeShift;        /* minimum block size shift */
+	HPT_U8 MaximumBlockSizeShift;        /* maximum block size shift */
+
+	HPT_U8 SupportDiskModeSetting;
+	HPT_U8 SupportSparePool;
+	HPT_U8 MaximumArrayNameLength;
+	/* only one HPT_U8 left here! */
+#ifdef __BIG_ENDIAN_BITFIELD
+	HPT_U8 reserved: 2;
+	HPT_U8 SupportPerformanceMonitor: 1;
+	HPT_U8 SupportVariableSectorSize: 1;
+	HPT_U8 SupportHotSwap: 1;
+	HPT_U8 HighPerformanceRAID1: 1;
+	HPT_U8 RebuildProcessInDriver: 1;
+	HPT_U8 SupportDedicatedSpare: 1;
+#else 
+	HPT_U8 SupportDedicatedSpare: 1;     /* call hpt_add_dedicated_spare() for dedicated spare. */
+	HPT_U8 RebuildProcessInDriver: 1;    /* Windows only. used by mid layer for rebuild control. */
+	HPT_U8 HighPerformanceRAID1: 1;      
+	HPT_U8 SupportHotSwap: 1;
+	HPT_U8 SupportVariableSectorSize: 1;
+	HPT_U8 SupportPerformanceMonitor: 1;
+	HPT_U8 reserved: 2;
+#endif
+
+	
+	HPT_U8 SupportedRAIDTypes[16];
+	/* maximum members in an array corresponding to SupportedRAIDTypes */
+	HPT_U8 MaximumArrayMembers[16];
+}
+DRIVER_CAPABILITIES, *PDRIVER_CAPABILITIES;
+
+typedef struct _DRIVER_CAPABILITIES_V2 {
+	DRIVER_CAPABILITIES v1;
+	HPT_U8 SupportedCachePolicies[16];
+	HPT_U32 reserved[17];
+}
+DRIVER_CAPABILITIES_V2, *PDRIVER_CAPABILITIES_V2;
+
+/*
+ * Controller information.
+ */
+typedef struct _CONTROLLER_INFO {
+	HPT_U8 ChipType;                    /* chip type */
+	HPT_U8 InterruptLevel;              /* IRQ level */
+	HPT_U8 NumBuses;                    /* bus count */
+	HPT_U8 ChipFlags;
+
+	HPT_U8 szProductID[MAX_NAME_LENGTH];/* product name */
+	HPT_U8 szVendorID[MAX_NAME_LENGTH]; /* vender name */
+
+} CONTROLLER_INFO, *PCONTROLLER_INFO;
+
+#if HPT_INTERFACE_VERSION>=0x01020000
+typedef struct _CONTROLLER_INFO_V2 {
+	HPT_U8 ChipType;                    /* chip type */
+	HPT_U8 InterruptLevel;              /* IRQ level */
+	HPT_U8 NumBuses;                    /* bus count */
+	HPT_U8 ChipFlags;
+
+	HPT_U8 szProductID[MAX_NAME_LENGTH];/* product name */
+	HPT_U8 szVendorID[MAX_NAME_LENGTH]; /* vender name */
+
+	HPT_U32 GroupId;                    /* low 32bit of vbus pointer the controller belongs
+										 * the master controller has CHIP_MASTER flag set*/
+	HPT_U8  pci_tree;
+	HPT_U8  pci_bus;
+	HPT_U8  pci_device;
+	HPT_U8  pci_function;
+
+	HPT_U32 ExFlags;
+} CONTROLLER_INFO_V2, *PCONTROLLER_INFO_V2;
+
+
+#define CEXF_IOPModel            1
+#define CEXF_SDRAMSize           2
+#define CEXF_BatteryInstalled    4
+#define CEXF_BatteryStatus       8
+#define CEXF_BatteryVoltage      0x10
+#define CEXF_BatteryBackupTime   0x20
+#define CEXF_FirmwareVersion     0x40
+#define CEXF_SerialNumber        0x80
+#define CEXF_BatteryTemperature  0x100
+#define CEXF_Power12v            0x200
+#define CEXF_Power5v             0x400
+#define CEXF_Power3p3v           0x800
+#define CEXF_Power2p5v           0x1000
+#define CEXF_Power1p8v           0x2000
+#define CEXF_Core1p8v            0x4000
+#define CEXF_Core1p2v            0x8000
+#define CEXF_DDR1p8v             0x10000
+#define CEXF_DDR1p8vRef          0x20000
+#define CEXF_CPUTemperature      0x40000
+#define CEXF_BoardTemperature    0x80000
+#define CEXF_FanSpeed            0x100000
+#define CEXF_Core1p0v            0x200000
+#define CEXF_Fan2Speed           0x400000
+
+typedef struct _CONTROLLER_INFO_V3 {
+	HPT_U8 ChipType;
+	HPT_U8 InterruptLevel;
+	HPT_U8 NumBuses;
+	HPT_U8 ChipFlags;
+	HPT_U8 szProductID[MAX_NAME_LENGTH];
+	HPT_U8 szVendorID[MAX_NAME_LENGTH];
+	HPT_U32 GroupId;
+	HPT_U8  pci_tree;
+	HPT_U8  pci_bus;
+	HPT_U8  pci_device;
+	HPT_U8  pci_function;
+	HPT_U32 ExFlags;
+	HPT_U8  IOPModel[32];
+	HPT_U32 SDRAMSize;
+	HPT_U8  BatteryInstalled; 
+	HPT_U8  BatteryStatus; 
+	HPT_U16 BatteryVoltage; 
+	HPT_U32 BatteryBackupTime; 
+	HPT_U32 FirmwareVersion;
+	HPT_U8  SerialNumber[32];
+	HPT_U8  BatteryMBInstalled; 
+	HPT_U8  BatteryTemperature; 
+	signed char CPUTemperature;
+	signed char BoardTemperature;
+	HPT_U16 FanSpeed;
+	HPT_U16 Power12v;
+	HPT_U16 Power5v;
+	HPT_U16 Power3p3v;
+	HPT_U16 Power2p5v;
+	HPT_U16 Power1p8v;
+	HPT_U16 Core1p8v;
+	HPT_U16 Core1p2v;
+	HPT_U16 DDR1p8v;
+	HPT_U16 DDR1p8vRef;
+	HPT_U16 Core1p0v;
+	HPT_U16 Fan2Speed;
+	HPT_U8  reserve[60];
+}
+CONTROLLER_INFO_V3, *PCONTROLLER_INFO_V3;
+typedef char check_CONTROLLER_INFO_V3[sizeof(CONTROLLER_INFO_V3)==256? 1:-1];
+#endif
+/*
+ * Channel information.
+ */
+typedef struct _CHANNEL_INFO {
+	HPT_U32         IoPort;         /* IDE Base Port Address */
+	HPT_U32         ControlPort;    /* IDE Control Port Address */
+
+	DEVICEID    Devices[2];         /* device connected to this channel */
+
+} CHANNEL_INFO, *PCHANNEL_INFO;
+
+typedef struct _CHANNEL_INFO_V2 {
+	HPT_U32         IoPort;         /* IDE Base Port Address */
+	HPT_U32         ControlPort;    /* IDE Control Port Address */
+
+	DEVICEID        Devices[2+13];    /* device connected to this channel, PMPort max=15 */
+} CHANNEL_INFO_V2, *PCHANNEL_INFO_V2;
+
+typedef struct _ENCLOSURE_INFO {
+	HPT_U8  EnclosureType;
+	HPT_U8  NumberOfPhys;
+	HPT_U8  AttachedTo; 
+	HPT_U8  Status;
+	HPT_U8  VendorId[8];
+	HPT_U8  ProductId[16];
+	HPT_U8  ProductRevisionLevel[4];
+	HPT_U32 PortPhyMap;
+	HPT_U32 reserve[55];
+} ENCLOSURE_INFO, *PENCLOSURE_INFO;
+
+
+typedef struct _SES_ELEMENT_STATUS {
+	HPT_U8   ElementType;
+	HPT_U8   ElementOverallIndex;
+	HPT_U8   ElementStatus;
+	HPT_U8   Reserved;
+	HPT_U32 ElementValue;
+	HPT_U8   ElementDescriptor[32];
+}SES_ELEMENT_STATUS,*PSES_ELEMENT_STATUS;
+
+#define MAX_ELEMENT_COUNT  80
+/* Element Type */
+#define SES_TYPE_UNSPECIFIED         0x00
+#define SES_TYPE_DEVICE              0x01
+#define SES_TYPE_POWER_SUPPLY        0x02
+#define SES_TYPE_FAN                 0x03
+#define SES_TYPE_TEMPERATURE_SENSOR  0x04
+#define SES_TYPE_DOOR_LOCK           0x05
+#define SES_TYPE_SPEAKER             0x06
+#define SES_TYPE_ES_CONTROLLER       0x07
+#define SES_TYPE_SCC_CONTROLLER      0x08
+#define SES_TYPE_NONVOLATILE_CACHE   0x09
+#define SES_TYPE_UPS                 0x0B
+#define SES_TYPE_DISPLAY             0x0C
+#define SES_TYPE_KEYPAD              0x0D
+#define SES_TYPE_ENCLOSURE           0x0E
+#define SES_TYPE_SCSI_TRANSCEIVER    0x0F
+#define SES_TYPE_LANGUAGE            0x10
+#define SES_TYPE_COMM_PORT           0x11
+#define SES_TYPE_VOLTAGE_SENSOR      0x12
+#define SES_TYPE_CURRENT_SENSOR      0x13
+#define SES_TYPE_SCSI_TARGET_PORT    0x14
+#define SES_TYPE_SCSI_INITIATOR_PORT 0x15
+#define SES_TYPE_SIMPLE_SUBENCLOSURE 0x16
+#define SES_TYPE_ARRAY_DEVICE        0x17
+#define SES_TYPE_VENDOR_SPECIFIC     0x80
+
+/* Element Status */
+
+#define	SES_STATUS_UNSUPPORTED   		0x00
+#define	SES_STATUS_OK					0x01
+#define	SES_STATUS_CRITICAL			0x02
+#define	SES_STATUS_NONCRITICAL 		0x03
+#define	SES_STATUS_UNRECOVERABLE	0x04
+#define	SES_STATUS_NOTINSTALLED		0x05
+#define	SES_STATUS_UNKNOWN			0x06
+#define	SES_STATUS_NOTAVAILABLE		0x06
+#define	SES_STATUS_RESERVED			0x07
+
+
+typedef struct _ENCLOSURE_INFO_V2 {
+	HPT_U8  EnclosureType;
+	HPT_U8  NumberOfPhys;
+	HPT_U8  AttachedTo; 
+	HPT_U8  Status;
+	HPT_U8  VendorId[8];
+	HPT_U8  ProductId[16];
+	HPT_U8  ProductRevisionLevel[4];
+	HPT_U32 PortPhyMap;
+	SES_ELEMENT_STATUS ElementStatus[MAX_ELEMENT_COUNT];
+} ENCLOSURE_INFO_V2, *PENCLOSURE_INFO_V2;
+
+typedef struct _ENCLOSURE_INFO_V3 {
+	HPT_U8  EnclosureType;
+	HPT_U8  NumberOfPhys;
+	HPT_U8  AttachedTo; 
+	HPT_U8  Status;
+	HPT_U8  VendorId[8];
+	HPT_U8  ProductId[16];
+	HPT_U8  ProductRevisionLevel[4];
+	HPT_U32 PortPhyMap;
+	HPT_U32	UnitId;	/*272x card has two Cores, unitId is used to distinguish them */
+	HPT_U32 reserved[32];
+	SES_ELEMENT_STATUS ElementStatus[MAX_ELEMENT_COUNT];
+} ENCLOSURE_INFO_V3, *PENCLOSURE_INFO_V3;
+
+#define ENCLOSURE_STATUS_OFFLINE 1
+
+#define ENCLOSURE_TYPE_INTERNAL 0
+#define ENCLOSURE_TYPE_SMP      1
+#define ENCLOSURE_TYPE_PM       2
+
+#ifndef __KERNEL__
+/*
+ * time represented in HPT_U32 format
+ */
+typedef struct _TIME_RECORD {
+   HPT_U32        seconds:6;      /* 0 - 59 */
+   HPT_U32        minutes:6;      /* 0 - 59 */
+   HPT_U32        month:4;        /* 1 - 12 */
+   HPT_U32        hours:6;        /* 0 - 59 */
+   HPT_U32        day:5;          /* 1 - 31 */
+   HPT_U32        year:5;         /* 0=2000, 31=2031 */
+} TIME_RECORD;
+#endif
+
+/*
+ * Array information.
+ */
+typedef struct _HPT_ARRAY_INFO {
+	HPT_U8      Name[MAX_ARRAYNAME_LEN];/* array name */
+	HPT_U8      Description[64];        /* array description */
+	HPT_U8      CreateManager[16];      /* who created it */
+	TIME_RECORD CreateTime;             /* when created it */
+
+	HPT_U8      ArrayType;              /* array type */
+	HPT_U8      BlockSizeShift;         /* stripe size */
+	HPT_U8      nDisk;                  /* member count: Number of ID in Members[] */
+	HPT_U8      SubArrayType;
+
+	HPT_U32     Flags;                  /* working flags, see ARRAY_FLAG_XXX */
+	HPT_U32     Members[MAX_ARRAY_MEMBERS_V1];  /* member array/disks */
+
+	/*
+	 * rebuilding progress, xx.xx% = sprintf(s, "%.2f%%", RebuildingProgress/100.0);
+	 * only valid if rebuilding is done by driver code.
+	 * Member Flags will have ARRAY_FLAG_REBUILDING set at this case.
+	 * Verify operation use same fields below, the only difference is
+	 * ARRAY_FLAG_VERIFYING is set.
+	 */
+	HPT_U32     RebuildingProgress;
+	HPT_U32     RebuiltSectors; /* rebuilding point (LBA) for single member */
+
+} HPT_ARRAY_INFO, *PHPT_ARRAY_INFO;
+
+#if HPT_INTERFACE_VERSION>=0x01010000
+typedef struct _HPT_ARRAY_INFO_V2 {
+	HPT_U8      Name[MAX_ARRAYNAME_LEN];/* array name */
+	HPT_U8      Description[64];        /* array description */
+	HPT_U8      CreateManager[16];      /* who created it */
+	TIME_RECORD CreateTime;             /* when created it */
+
+	HPT_U8      ArrayType;              /* array type */
+	HPT_U8      BlockSizeShift;         /* stripe size */
+	HPT_U8      nDisk;                  /* member count: Number of ID in Members[] */
+	HPT_U8      SubArrayType;
+
+	HPT_U32     Flags;                  /* working flags, see ARRAY_FLAG_XXX */
+	HPT_U32     Members[MAX_ARRAY_MEMBERS_V2];  /* member array/disks */
+
+	HPT_U32     RebuildingProgress;
+	HPT_U64     RebuiltSectors; /* rebuilding point (LBA) for single member */
+
+	HPT_U32     reserve4[4];
+} HPT_ARRAY_INFO_V2, *PHPT_ARRAY_INFO_V2;
+#endif
+
+#if HPT_INTERFACE_VERSION>=0x01020000
+typedef struct _HPT_ARRAY_INFO_V3 {
+	HPT_U8      Name[MAX_ARRAYNAME_LEN];/* array name */
+	HPT_U8      Description[64];        /* array description */
+	HPT_U8      CreateManager[16];      /* who created it */
+	TIME_RECORD CreateTime;             /* when created it */
+
+	HPT_U8      ArrayType;              /* array type */
+	HPT_U8      BlockSizeShift;         /* stripe size */
+	HPT_U8      nDisk;                  /* member count: Number of ID in Members[] */
+	HPT_U8      SubArrayType;
+
+	HPT_U32     Flags;                  /* working flags, see ARRAY_FLAG_XXX */
+	HPT_U32     Members[MAX_ARRAY_MEMBERS_V2];  /* member array/disks */
+
+	HPT_U32     RebuildingProgress;
+	HPT_U64     RebuiltSectors;         /* rebuilding point (LBA) for single member */
+
+	DEVICEID    TransformSource;
+	DEVICEID    TransformTarget;        /* destination device ID */
+	HPT_U32     TransformingProgress;
+	HPT_U32     Signature;              /* persistent identification*/
+#if MAX_ARRAY_MEMBERS_V2==16
+	HPT_U16     Critical_Members;       /* bit mask of critical members */
+	HPT_U16     reserve2;
+	HPT_U32     reserve;
+#else 
+	HPT_U32     Critical_Members;
+	HPT_U32     reserve;
+#endif
+} HPT_ARRAY_INFO_V3, *PHPT_ARRAY_INFO_V3;
+#endif
+
+#if HPT_INTERFACE_VERSION>=0x02000001
+typedef struct _HPT_ARRAY_INFO_V4 {
+	HPT_U8      Name[MAX_ARRAYNAME_LEN];/* array name */
+	HPT_U8      Description[64];        /* array description */
+	HPT_U8      CreateManager[16];      /* who created it */
+	TIME_RECORD CreateTime;             /* when created it */
+
+	HPT_U8      ArrayType;              /* array type */
+	HPT_U8      BlockSizeShift;         /* stripe size */
+	HPT_U8      nDisk;                  /* member count: Number of ID in Members[] */
+	HPT_U8      SubArrayType;
+
+	HPT_U32     Flags;                  /* working flags, see ARRAY_FLAG_XXX */
+
+	HPT_U32     RebuildingProgress;
+	HPT_U64     RebuiltSectors; /* rebuilding point (LBA) for single member */
+
+	DEVICEID    TransformSource;
+	DEVICEID    TransformTarget;   /* destination device ID */
+	HPT_U32     TransformingProgress;
+	HPT_U32     Signature;          /* persistent identification*/
+	HPT_U8       SectorSizeShift; /*sector size = 512B<<SectorSizeShift*/
+	HPT_U8       reserved2[7];
+	HPT_U64     Critical_Members;
+	HPT_U32     Members[MAX_ARRAY_MEMBERS_V3];  /* member array/disks */
+} HPT_ARRAY_INFO_V4, *PHPT_ARRAY_INFO_V4;
+#endif
+
+
+/*
+ * ATA/ATAPI Device identify data without the Reserved4.
+ */
+typedef struct _IDENTIFY_DATA2 {
+	HPT_U16 GeneralConfiguration;
+	HPT_U16 NumberOfCylinders;
+	HPT_U16 Reserved1;
+	HPT_U16 NumberOfHeads;
+	HPT_U16 UnformattedBytesPerTrack;
+	HPT_U16 UnformattedBytesPerSector;
+	HPT_U8  SasAddress[8];
+	HPT_U16 SerialNumber[10];
+	HPT_U16 BufferType;
+	HPT_U16 BufferSectorSize;
+	HPT_U16 NumberOfEccBytes;
+	HPT_U16 FirmwareRevision[4];
+	HPT_U16 ModelNumber[20];
+	HPT_U8  MaximumBlockTransfer;
+	HPT_U8  VendorUnique2;
+	HPT_U16 DoubleWordIo;
+	HPT_U16 Capabilities;
+	HPT_U16 Reserved2;
+	HPT_U8  VendorUnique3;
+	HPT_U8  PioCycleTimingMode;
+	HPT_U8  VendorUnique4;
+	HPT_U8  DmaCycleTimingMode;
+	HPT_U16 TranslationFieldsValid;
+	HPT_U16 NumberOfCurrentCylinders;
+	HPT_U16 NumberOfCurrentHeads;
+	HPT_U16 CurrentSectorsPerTrack;
+	HPT_U32 CurrentSectorCapacity;
+	HPT_U16 CurrentMultiSectorSetting;
+	HPT_U32 UserAddressableSectors;
+	HPT_U8  SingleWordDMASupport;
+	HPT_U8  SingleWordDMAActive;
+	HPT_U8  MultiWordDMASupport;
+	HPT_U8  MultiWordDMAActive;
+	HPT_U8  AdvancedPIOModes;
+	HPT_U8  Reserved4;
+	HPT_U16 MinimumMWXferCycleTime;
+	HPT_U16 RecommendedMWXferCycleTime;
+	HPT_U16 MinimumPIOCycleTime;
+	HPT_U16 MinimumPIOCycleTimeIORDY;
+	HPT_U16 Reserved5[2];
+	HPT_U16 ReleaseTimeOverlapped;
+	HPT_U16 ReleaseTimeServiceCommand;
+	HPT_U16 MajorRevision;
+	HPT_U16 MinorRevision;
+} __attribute__((packed)) IDENTIFY_DATA2, *PIDENTIFY_DATA2;
+
+/*
+ * physical device information.
+ * IdentifyData.ModelNumber[] is HPT_U8-swapped from the original identify data.
+ */
+typedef struct _DEVICE_INFO {
+	HPT_U8   ControllerId;          /* controller id */
+	HPT_U8   PathId;                /* bus */
+	HPT_U8   TargetId;              /* id */
+	HPT_U8   DeviceModeSetting;     /* Current Data Transfer mode: 0-4 PIO 0-4 */
+									/* 5-7 MW DMA0-2, 8-13 UDMA0-5             */
+	HPT_U8   DeviceType;            /* device type */
+	HPT_U8   UsableMode;            /* highest usable mode */
+
+#ifdef __BIG_ENDIAN_BITFIELD
+	HPT_U8   NCQEnabled: 1;
+	HPT_U8   NCQSupported: 1;
+	HPT_U8   TCQEnabled: 1;
+	HPT_U8   TCQSupported: 1;
+	HPT_U8   WriteCacheEnabled: 1;
+	HPT_U8   WriteCacheSupported: 1;
+	HPT_U8   ReadAheadEnabled: 1;
+	HPT_U8   ReadAheadSupported: 1;
+	HPT_U8   reserved6: 6;
+	HPT_U8   SpinUpMode: 2;
+#else 
+	HPT_U8   ReadAheadSupported: 1;
+	HPT_U8   ReadAheadEnabled: 1;
+	HPT_U8   WriteCacheSupported: 1;
+	HPT_U8   WriteCacheEnabled: 1;
+	HPT_U8   TCQSupported: 1;
+	HPT_U8   TCQEnabled: 1;
+	HPT_U8   NCQSupported: 1;
+	HPT_U8   NCQEnabled: 1;
+	HPT_U8   SpinUpMode: 2;
+	HPT_U8   reserved6: 6;
+#endif
+
+	HPT_U32     Flags;              /* working flags, see DEVICE_FLAG_XXX */
+
+	IDENTIFY_DATA2 IdentifyData;    /* Identify Data of this device */
+
+}
+__attribute__((packed)) DEVICE_INFO, *PDEVICE_INFO;
+
+#if HPT_INTERFACE_VERSION>=0x01020000
+#define MAX_PARENTS_PER_DISK    8
+/*
+ * physical device information.
+ * IdentifyData.ModelNumber[] is HPT_U8-swapped from the original identify data.
+ */
+typedef struct _DEVICE_INFO_V2 {
+	HPT_U8   ControllerId;          /* controller id */
+	HPT_U8   PathId;                /* bus */
+	HPT_U8   TargetId;              /* id */
+	HPT_U8   DeviceModeSetting;     /* Current Data Transfer mode: 0-4 PIO 0-4 */
+									/* 5-7 MW DMA0-2, 8-13 UDMA0-5             */
+	HPT_U8   DeviceType;            /* device type */
+	HPT_U8   UsableMode;            /* highest usable mode */
+
+#ifdef __BIG_ENDIAN_BITFIELD
+	HPT_U8   NCQEnabled: 1;
+	HPT_U8   NCQSupported: 1;
+	HPT_U8   TCQEnabled: 1;
+	HPT_U8   TCQSupported: 1;
+	HPT_U8   WriteCacheEnabled: 1;
+	HPT_U8   WriteCacheSupported: 1;
+	HPT_U8   ReadAheadEnabled: 1;
+	HPT_U8   ReadAheadSupported: 1;
+	HPT_U8   reserved6: 6;
+	HPT_U8   SpinUpMode: 2;
+#else 
+	HPT_U8   ReadAheadSupported: 1;
+	HPT_U8   ReadAheadEnabled: 1;
+	HPT_U8   WriteCacheSupported: 1;
+	HPT_U8   WriteCacheEnabled: 1;
+	HPT_U8   TCQSupported: 1;
+	HPT_U8   TCQEnabled: 1;
+	HPT_U8   NCQSupported: 1;
+	HPT_U8   NCQEnabled: 1;
+	HPT_U8   SpinUpMode: 2;
+	HPT_U8   reserved6: 6;
+#endif
+
+	HPT_U32     Flags;              /* working flags, see DEVICE_FLAG_XXX */
+
+	IDENTIFY_DATA2 IdentifyData;    /* Identify Data of this device */
+
+	HPT_U64 TotalFree;
+	HPT_U64 MaxFree;
+	HPT_U64 BadSectors;
+	DEVICEID ParentArrays[MAX_PARENTS_PER_DISK];
+
+}
+__attribute__((packed)) DEVICE_INFO_V2, *PDEVICE_INFO_V2, DEVICE_INFO_V3, *PDEVICE_INFO_V3;
+
+/*
+ * HPT601 information
+ */
+#endif
+/*
+ * HPT601 information
+ */
+#define HPT601_INFO_DEVICEID      1
+#define HPT601_INFO_TEMPERATURE   2
+#define HPT601_INFO_FANSTATUS     4
+#define HPT601_INFO_BEEPERCONTROL 8
+#define HPT601_INFO_LED1CONTROL   0x10
+#define HPT601_INFO_LED2CONTROL   0x20
+#define HPT601_INFO_POWERSTATUS   0x40
+
+typedef struct _HPT601_INFO_ {
+	HPT_U16 ValidFields;        /* mark valid fields below */
+	HPT_U16 DeviceId;           /* 0x5A3E */
+	HPT_U16 Temperature;        /* Read: temperature sensor value. Write: temperature limit */
+	HPT_U16 FanStatus;          /* Fan status */
+	HPT_U16 BeeperControl;      /* bit4: beeper control bit. bit0-3: frequency bits */
+	HPT_U16 LED1Control;        /* bit4: twinkling control bit. bit0-3: frequency bits */
+	HPT_U16 LED2Control;        /* bit4: twinkling control bit. bit0-3: frequency bits */
+	HPT_U16 PowerStatus;        /* 1: has power 2: no power */
+} HPT601_INFO, *PHPT601_INFO;
+
+#if HPT_INTERFACE_VERSION>=0x01010000
+#ifndef __KERNEL__
+/* cache policy for each vdev, copied from ldm.h */
+#define CACHE_POLICY_NONE 0
+#define CACHE_POLICY_WRITE_THROUGH 1
+#define CACHE_POLICY_WRITE_BACK 2
+
+#endif
+#endif
+/*
+ * Logical device information.
+ * Union of ArrayInfo and DeviceInfo.
+ * Common properties will be put in logical device information.
+ */
+typedef struct _LOGICAL_DEVICE_INFO {
+	HPT_U8      Type;                   /* LDT_ARRAY or LDT_DEVICE */
+	HPT_U8      reserved[3];
+
+	HPT_U32     Capacity;               /* array capacity */
+	DEVICEID    ParentArray;
+
+	union {
+		HPT_ARRAY_INFO array;
+		DEVICE_INFO device;
+	} __attribute__((packed)) u;
+
+} __attribute__((packed)) LOGICAL_DEVICE_INFO, *PLOGICAL_DEVICE_INFO;
+
+#if HPT_INTERFACE_VERSION>=0x01010000
+typedef struct _LOGICAL_DEVICE_INFO_V2 {
+	HPT_U8      Type;                   /* LDT_ARRAY or LDT_DEVICE */
+	HPT_U8      reserved[3];
+
+	HPT_U64     Capacity;               /* array capacity */
+	DEVICEID    ParentArray;            /* for physical device, Please don't use this field.
+										 * use ParentArrays field in DEVICE_INFO_V2
+										 */
+
+	union {
+		HPT_ARRAY_INFO_V2 array;
+		DEVICE_INFO device;
+	} __attribute__((packed)) u;
+
+} __attribute__((packed)) LOGICAL_DEVICE_INFO_V2, *PLOGICAL_DEVICE_INFO_V2;
+#endif
+
+#if HPT_INTERFACE_VERSION>=0x01020000
+#define INVALID_TARGET_ID   0xFF
+#define INVALID_BUS_ID      0xFF
+typedef struct _LOGICAL_DEVICE_INFO_V3 {
+	HPT_U8      Type;                   /* LDT_ARRAY or LDT_DEVICE */
+	HPT_U8      CachePolicy;            /* refer to CACHE_POLICY_xxx */
+	HPT_U8      VBusId;                 /* vbus sequence in vbus_list */
+	HPT_U8      TargetId;               /* OS target id. Value 0xFF is invalid */
+										/* OS disk name: HPT DISK $VBusId_$TargetId */
+	HPT_U64     Capacity;               /* array capacity */
+	DEVICEID    ParentArray;            /* for physical device, don't use this field.
+										 * use ParentArrays field in DEVICE_INFO_V2 instead.
+										 */
+	HPT_U32     TotalIOs;
+	HPT_U32     TobalMBs;
+	HPT_U32     IOPerSec;
+	HPT_U32     MBPerSec;
+
+	union {
+		HPT_ARRAY_INFO_V3 array;
+		DEVICE_INFO_V2 device;
+	} __attribute__((packed)) u;
+
+}
+__attribute__((packed)) LOGICAL_DEVICE_INFO_V3, *PLOGICAL_DEVICE_INFO_V3;
+#endif
+
+#if HPT_INTERFACE_VERSION>=0x02000001
+typedef struct _LOGICAL_DEVICE_INFO_V4 {
+	HPT_U32    dwSize;
+	HPT_U8      revision;
+	HPT_U8      reserved[7];
+
+	HPT_U8      Type;                   /* LDT_ARRAY or LDT_DEVICE */
+	HPT_U8      CachePolicy;            /* refer to CACHE_POLICY_xxx */
+	HPT_U8      VBusId;                 /* vbus sequence in vbus_list */
+	HPT_U8      TargetId;               /* OS target id. Value 0xFF is invalid */
+										/* OS disk name: HPT DISK $VBusId_$TargetId */
+	HPT_U64     Capacity;               /* array capacity */
+	DEVICEID    ParentArray;            /* for physical device, don't use this field.
+										 * use ParentArrays field in DEVICE_INFO_V2 instead.
+										 */
+	HPT_U32     TotalIOs;
+	HPT_U32     TobalMBs;
+	HPT_U32     IOPerSec;
+	HPT_U32     MBPerSec;
+
+	union {
+		HPT_ARRAY_INFO_V4 array;
+		DEVICE_INFO_V3 device;
+	} __attribute__((packed)) u;
+}
+__attribute__((packed)) LOGICAL_DEVICE_INFO_V4, *PLOGICAL_DEVICE_INFO_V4;
+
+/*LOGICAL_DEVICE_INFO_V4 max revision number*/
+#define LOGICAL_DEVICE_INFO_V4_REVISION 0
+/*If new revision was defined please check evey revision size*/
+#define LOGICAL_DEVICE_INFO_V4_R0_SIZE (sizeof(LOGICAL_DEVICE_INFO_V4))
+#endif
+
+/*
+ * ALTERABLE_ARRAY_INFO and ALTERABLE_DEVICE_INFO, used in set_array_info()
+ * and set_device_info().
+ * When set_xxx_info() is called, the ValidFields member indicates which
+ * fields in the structure are valid.
+ */
+/* field masks */
+#define AAIF_NAME           1
+#define AAIF_DESCRIPTION    2
+
+#define ADIF_MODE           1
+#define ADIF_TCQ            2
+#define ADIF_NCQ            4
+#define ADIF_WRITE_CACHE    8
+#define ADIF_READ_AHEAD     0x10
+#define ADIF_SPIN_UP_MODE   0x20
+
+typedef struct _ALTERABLE_ARRAY_INFO {
+	HPT_U32   ValidFields;              /* mark valid fields below */
+	HPT_U8  Name[MAX_ARRAYNAME_LEN];    /* array name */
+	HPT_U8  Description[64];            /* array description */
+}__attribute__((packed))ALTERABLE_ARRAY_INFO, *PALTERABLE_ARRAY_INFO;
+
+typedef struct _ALTERABLE_DEVICE_INFO {
+	HPT_U32   ValidFields;              /* mark valid fields below */
+	HPT_U8   DeviceModeSetting;         /* 0-4 PIO 0-4, 5-7 MW DMA0-2, 8-13 UDMA0-5 */
+}__attribute__((packed))ALTERABLE_DEVICE_INFO, *PALTERABLE_DEVICE_INFO;
+
+typedef struct _ALTERABLE_DEVICE_INFO_V2 {
+	HPT_U32   ValidFields;              /* mark valid fields below */
+	HPT_U8   DeviceModeSetting;         /* 0-4 PIO 0-4, 5-7 MW DMA0-2, 8-13 UDMA0-5 */
+	HPT_U8   TCQEnabled;
+	HPT_U8   NCQEnabled;
+	HPT_U8   WriteCacheEnabled;
+	HPT_U8   ReadAheadEnabled;
+	HPT_U8   SpinUpMode;
+	HPT_U8   reserve[2];
+	HPT_U32  reserve2[13]; /* pad to 64 bytes */
+}__attribute__((packed))ALTERABLE_DEVICE_INFO_V2, *PALTERABLE_DEVICE_INFO_V2;
+
+#if HPT_INTERFACE_VERSION>=0x01020000
+
+#define TARGET_TYPE_DEVICE  0
+#define TARGET_TYPE_ARRAY   1
+
+
+#define AIT_NAME            0
+#define AIT_DESCRIPTION     1
+#define AIT_CACHE_POLICY    2
+
+
+#define DIT_MODE        0
+#define DIT_READ_AHEAD  1
+#define DIT_WRITE_CACHE 2
+#define DIT_TCQ         3
+#define DIT_NCQ         4
+#define DIT_IDENTIFY    5
+
+/* param type is determined by target_type and info_type*/
+typedef struct _SET_DEV_INFO
+{
+	HPT_U8 target_type;
+	HPT_U8 infor_type;
+	HPT_U16 param_length;
+	#define SET_VDEV_INFO_param(p) ((HPT_U8 *)(p)+sizeof(SET_VDEV_INFO))
+	/* HPT_U8 param[0]; */
+} SET_VDEV_INFO, * PSET_VDEV_INFO;
+
+typedef HPT_U8 PARAM_ARRAY_NAME[MAX_ARRAYNAME_LEN] ;
+typedef HPT_U8 PARAM_ARRAY_DES[64];
+typedef HPT_U8 PARAM_DEVICE_MODE, PARAM_TCQ, PARAM_NCQ, PARAM_READ_AHEAD, PARAM_WRITE_CACHE, PARAM_CACHE_POLICY;
+
+#endif
+
+/*
+ * CREATE_ARRAY_PARAMS
+ *  Param structure used to create an array.
+ */
+typedef struct _CREATE_ARRAY_PARAMS {
+	HPT_U8 ArrayType;                   /* 1-level array type */
+	HPT_U8 nDisk;                       /* number of elements in Members[] array */
+	HPT_U8 BlockSizeShift;              /* Stripe size if ArrayType==AT_RAID0 / AT_RAID5 */
+	HPT_U8 CreateFlags;                 /* See CAF_xxx */
+
+	HPT_U8 ArrayName[MAX_ARRAYNAME_LEN];/* Array name */
+	HPT_U8      Description[64];        /* array description */
+	HPT_U8      CreateManager[16];      /* who created it */
+	TIME_RECORD CreateTime;             /* when created it */
+
+	HPT_U32 Members[MAX_ARRAY_MEMBERS_V1];/* ID of array members, a member can be an array */
+
+} CREATE_ARRAY_PARAMS, *PCREATE_ARRAY_PARAMS;
+
+#if HPT_INTERFACE_VERSION>=0x01010000
+typedef struct _CREATE_ARRAY_PARAMS_V2 {
+	HPT_U8 ArrayType;                   /* 1-level array type */
+	HPT_U8 nDisk;                       /* number of elements in Members[] array */
+	HPT_U8 BlockSizeShift;              /* Stripe size if ArrayType==AT_RAID0 / AT_RAID5 */
+	HPT_U8 CreateFlags;                 /* See CAF_xxx */
+
+	HPT_U8 ArrayName[MAX_ARRAYNAME_LEN];/* Array name */
+	HPT_U8 Description[64];             /* array description */
+	HPT_U8 CreateManager[16];           /* who created it */
+	TIME_RECORD CreateTime;             /* when created it */
+	HPT_U64 Capacity;
+
+	HPT_U32 Members[MAX_ARRAY_MEMBERS_V2];/* ID of array members, a member can be an array */
+
+} CREATE_ARRAY_PARAMS_V2, *PCREATE_ARRAY_PARAMS_V2;
+#endif
+
+#if HPT_INTERFACE_VERSION>=0x02000001
+typedef struct _CREATE_ARRAY_PARAMS_V3 {
+	HPT_U32  dwSize;
+	HPT_U8 revision;			/*CREATE_ARRAY_PARAMS_V3_REVISION*/
+	HPT_U8 reserved[5];
+	HPT_U8 subDisks;            /* RAIDn0 sub array */
+	HPT_U8 SectorSizeShift;     /*sector size = 512B<<SectorSizeShift*/
+	HPT_U8 ArrayType;                   /* 1-level array type */
+	HPT_U8 nDisk;                       /* number of elements in Members[] array */
+	HPT_U8 BlockSizeShift;              /* Stripe size if ArrayType==AT_RAID0 / AT_RAID5 */
+	HPT_U8 CreateFlags;                 /* See CAF_xxx */
+
+	HPT_U8 ArrayName[MAX_ARRAYNAME_LEN];/* Array name */
+	HPT_U8 Description[64];     /* array description */
+	HPT_U8 CreateManager[16];       /* who created it */
+	TIME_RECORD CreateTime;             /* when created it */
+	HPT_U64 Capacity;
+
+	HPT_U32 Members[MAX_ARRAY_MEMBERS_V3];/* ID of array members, a member can be an array */
+} CREATE_ARRAY_PARAMS_V3, *PCREATE_ARRAY_PARAMS_V3;
+
+/*CREATE_ARRAY_PARAMS_V3 current max revision*/
+#define CREATE_ARRAY_PARAMS_V3_REVISION 0
+/*If new revision defined please check evey revision size*/
+#define CREATE_ARRAY_PARAMS_V3_R0_SIZE (sizeof(CREATE_ARRAY_PARAMS_V3))
+#endif
+
+#if HPT_INTERFACE_VERSION < 0x01020000
+/*
+ * Flags used for creating an RAID 1 array
+ *
+ * CAF_CREATE_AND_DUPLICATE
+ *    Copy source disk contents to target for RAID 1. If user choose "create and duplicate"
+ *    to create an array, GUI will call CreateArray() with this flag set. Then GUI should
+ *    call hpt_get_device_info() with the returned array ID and check returned flags to
+ *    see if ARRAY_FLAG_REBUILDING is set. If not set, driver does not support rebuilding
+ *    and GUI must do duplication itself.
+ * CAF_DUPLICATE_MUST_DONE
+ *    If the duplication is aborted or fails, do not create the array.
+ */
+#define CAF_CREATE_AND_DUPLICATE 1
+#define CAF_DUPLICATE_MUST_DONE  2
+#define CAF_CREATE_AS_RAID15     4
+/*
+ * Flags used for creating an RAID 5 array
+ */
+#define CAF_CREATE_R5_NO_BUILD     1
+#define CAF_CREATE_R5_ZERO_INIT    2
+#define CAF_CREATE_R5_BUILD_PARITY 4
+
+#else 
+/*
+ * Flags used for creating
+ */
+#define CAF_FOREGROUND_INITIALIZE   1
+#define CAF_BACKGROUND_INITIALIZE   2
+#define CAF_CREATE_R5_WRITE_BACK    (CACHE_POLICY_WRITE_BACK<<CAF_CACHE_POLICY_SHIFT)
+
+
+#define CAF_CACHE_POLICY_MASK       0x1C
+#define CAF_CACHE_POLICY_SHIFT      2
+
+#endif
+
+#define CAF_KEEP_DATA_ALWAYS     0x80
+
+/* Flags used for deleting an array
+ *
+ * DAF_KEEP_DATA_IF_POSSIBLE
+ *    If this flag is set, deleting a RAID 1 array will not destroy the data on both disks.
+ *    Deleting a JBOD should keep partitions on first disk ( not implement now ).
+ *    Deleting a RAID 0/1 should result as two RAID 0 array ( not implement now ).
+ */
+#define DAF_KEEP_DATA_IF_POSSIBLE 1
+#define DAF_KEEP_DATA_ALWAYS      2
+
+/*
+ * event types
+ */
+#define ET_DEVICE_REMOVED   1   /* device removed */
+#define ET_DEVICE_PLUGGED   2   /* device plugged */
+#define ET_DEVICE_ERROR     3   /* device I/O error */
+#define ET_REBUILD_STARTED  4
+#define ET_REBUILD_ABORTED  5
+#define ET_REBUILD_FINISHED 6
+#define ET_SPARE_TOOK_OVER  7
+#define ET_REBUILD_FAILED   8
+#define ET_VERIFY_STARTED   9
+#define ET_VERIFY_ABORTED   10
+#define ET_VERIFY_FAILED    11
+#define ET_VERIFY_FINISHED  12
+#define ET_INITIALIZE_STARTED   13
+#define ET_INITIALIZE_ABORTED   14
+#define ET_INITIALIZE_FAILED    15
+#define ET_INITIALIZE_FINISHED  16
+#define ET_VERIFY_DATA_ERROR    17
+#define ET_TRANSFORM_STARTED    18
+#define ET_TRANSFORM_ABORTED    19
+#define ET_TRANSFORM_FAILED     20
+#define ET_TRANSFORM_FINISHED   21
+#define ET_SMART_FAILED         22
+#define ET_SMART_PASSED         23
+#define ET_SECTOR_REPAIR_FAIL     24
+#define ET_SECTOR_REPAIR_SUCCESS  25
+#define ET_ERASE_FAIL		26
+#define ET_ERASE_SUCCESS	27
+#define ET_CONTINUE_REBUILD_ON_ERROR 28
+
+
+/*
+ * event structure
+ */
+typedef struct _HPT_EVENT {
+	TIME_RECORD Time;
+	DEVICEID    DeviceID;
+	HPT_U8       EventType;
+	HPT_U8      reserved[3];
+
+	HPT_U8      Data[32]; /* various data depend on EventType */
+} HPT_EVENT, *PHPT_EVENT;
+
+/*
+ * IDE pass-through command. Use it at your own risk!
+ */
+typedef struct _IDE_PASS_THROUGH_HEADER {
+	DEVICEID idDisk;             /* disk ID */
+	HPT_U8     bFeaturesReg;     /* feature register */
+	HPT_U8     bSectorCountReg;  /* IDE sector count register. */
+	HPT_U8     bLbaLowReg;       /* IDE LBA low value. */
+	HPT_U8     bLbaMidReg;       /* IDE LBA mid register. */
+	HPT_U8     bLbaHighReg;      /* IDE LBA high value. */
+	HPT_U8     bDriveHeadReg;    /* IDE drive/head register. */
+	HPT_U8     bCommandReg;      /* Actual IDE command. Checked for validity by driver. */
+	HPT_U8     nSectors;         /* data size in sectors, if the command has data transfer */
+	HPT_U8     protocol;         /* IO_COMMAND_(READ,WRITE) or zero for non-DATA */
+	HPT_U8     reserve[3];
+	#define IDE_PASS_THROUGH_buffer(p) ((HPT_U8 *)(p) + sizeof(IDE_PASS_THROUGH_HEADER))
+	/* HPT_U8     DataBuffer[0]; */
+}
+IDE_PASS_THROUGH_HEADER, *PIDE_PASS_THROUGH_HEADER;
+
+typedef struct _IDE_PASS_THROUGH_HEADER_V2 {
+	DEVICEID idDisk;             /* disk ID */
+	HPT_U16    bFeaturesReg;     /* feature register */
+	HPT_U16    bSectorCountReg;  /* IDE sector count register. */
+	HPT_U16    bLbaLowReg;       /* IDE LBA low value. */
+	HPT_U16    bLbaMidReg;       /* IDE LBA mid register. */
+	HPT_U16    bLbaHighReg;      /* IDE LBA high value. */
+	HPT_U8     bDriveHeadReg;    /* IDE drive/head register. */
+	HPT_U8     bCommandReg;      /* Actual IDE command. Checked for validity by driver. */
+	HPT_U16    nSectors;         /* data size in sectors, if the command has data transfer */
+	HPT_U8     protocol;         /* IO_COMMAND_(READ,WRITE) or zero for non-DATA */
+	HPT_U8     reserve;
+	#define IDE_PASS_THROUGH_V2_buffer(p) ((HPT_U8 *)(p) + sizeof(IDE_PASS_THROUGH_HEADER_V2))
+	/* HPT_U8     DataBuffer[0]; */
+}
+IDE_PASS_THROUGH_HEADER_V2, *PIDE_PASS_THROUGH_HEADER_V2;
+
+typedef struct _HPT_SCSI_PASSTHROUGH_IN {
+	DEVICEID idDisk;
+	HPT_U8   protocol;
+	HPT_U8   reserve1;
+	HPT_U8   reserve2;
+	HPT_U8   cdbLength;
+	HPT_U8   cdb[16];
+	HPT_U32  dataLength;
+	/* data follows, if any */
+}
+HPT_SCSI_PASSTHROUGH_IN, *PHPT_SCSI_PASSTHROUGH_IN;
+
+typedef struct _HPT_SCSI_PASSTHROUGH_OUT {
+	HPT_U8   scsiStatus;
+	HPT_U8   reserve1;
+	HPT_U8   reserve2;
+	HPT_U8   reserve3;
+	HPT_U32  dataLength;
+	/* data/sense follows if any */
+}
+HPT_SCSI_PASSTHROUGH_OUT, *PHPT_SCSI_PASSTHROUGH_OUT;
+
+/*
+ * device io packet format
+ */
+typedef struct _DEVICE_IO_EX_PARAMS {
+	DEVICEID idDisk;
+	HPT_U32    Lba;
+	HPT_U16   nSectors;
+	HPT_U8    Command;    /* IO_COMMAD_xxx */
+	HPT_U8    BufferType; /* BUFFER_TYPE_xxx, see below */
+	HPT_U32    BufferPtr;
+}
+DEVICE_IO_EX_PARAMS, *PDEVICE_IO_EX_PARAMS;
+
+#define BUFFER_TYPE_LOGICAL              1 /* logical pointer to buffer */
+#define BUFFER_TYPE_PHYSICAL             2 /* physical address of buffer */
+#define BUFFER_TYPE_LOGICAL_LOGICAL_SG   3 /* logical pointer to logical S/G table */
+#define BUFFER_TYPE_LOGICAL_PHYSICAL_SG  4 /* logical pointer to physical S/G table */
+#define BUFFER_TYPE_PHYSICAL_LOGICAL_SG  5 /* physical address to logical S/G table */
+#define BUFFER_TYPE_PHYSICAL_PHYSICAL_SG 6 /* physical address of physical S/G table */
+#define BUFFER_TYPE_PHYSICAL_PHYSICAL_SG_PIO 7 /* non DMA capable physical address of physical S/G table */
+
+typedef struct _HPT_DRIVER_PARAMETER {
+	char    name[32];
+	HPT_U8  value[32];
+	HPT_U8  type;        /* HPT_DRIVER_PARAMETER_TYPE_* */
+	HPT_U8  persistent;
+	HPT_U8  reserve2[2];
+	HPT_U8  location;    /* 0 - system */
+	HPT_U8  controller;
+	HPT_U8  bus;
+	HPT_U8  reserve1;
+	char    desc[128];
+}
+HPT_DRIVER_PARAMETER, *PHPT_DRIVER_PARAMETER;
+
+#define HPT_DRIVER_PARAMETER_TYPE_INT 1
+#define HPT_DRIVER_PARAMETER_TYPE_BOOL 2
+
+typedef struct _HPT_PM_CMDSTAT {
+	HPT_U64 timeStamp;
+	HPT_U64 lba;
+	HPT_U16 sectors;
+	HPT_U16 reserved;
+	HPT_U32 rspTime;
+}
+HPT_PM_CMDSTAT, *PHPT_PM_CMDSTAT;
+
+#define HIGHEST_RSPTIME_CMD_SAVE 10
+#define RSPTIME_HISTOGRAM_SEGMENT_COUNT 38
+
+typedef struct _HPT_PM_IOSTAT {
+	HPT_PM_CMDSTAT highestRspCmdStatData[HIGHEST_RSPTIME_CMD_SAVE];
+	HPT_U32 rspTimeHistogram[RSPTIME_HISTOGRAM_SEGMENT_COUNT];
+	HPT_U16 pendingIo;
+	HPT_U16 activeIo;
+	HPT_U32 instantKBPs;
+	HPT_U32 averageKBPs;
+	HPT_U32 instantIOPs;
+	HPT_U32 averageIOPs;
+}
+HPT_PM_IOSTAT, *PHPT_PM_IOSTAT;
+
+
+
+/*
+ * ioctl structure
+ */
+#define HPT_IOCTL_MAGIC32 0x1A2B3C4D
+#define HPT_IOCTL_MAGIC   0xA1B2C3D4
+
+typedef struct _HPT_IOCTL_PARAM {
+	HPT_U32   Magic;                 /* used to check if it's a valid ioctl packet */
+	HPT_U32   dwIoControlCode;       /* operation control code */
+	HPT_PTR   lpInBuffer;            /* input data buffer */
+	HPT_U32   nInBufferSize;         /* size of input data buffer */
+	HPT_PTR   lpOutBuffer;           /* output data buffer */
+	HPT_U32   nOutBufferSize;        /* size of output data buffer */
+	HPT_PTR   lpBytesReturned;       /* count of HPT_U8s returned */
+}
+HPT_IOCTL_PARAM, *PHPT_IOCTL_PARAM;
+
+/* for 32-bit app running on 64-bit system */
+typedef struct _HPT_IOCTL_PARAM32 {
+	HPT_U32   Magic;
+	HPT_U32   dwIoControlCode;
+	HPT_U32   lpInBuffer;
+	HPT_U32   nInBufferSize;
+	HPT_U32   lpOutBuffer;
+	HPT_U32   nOutBufferSize;
+	HPT_U32   lpBytesReturned;
+}
+HPT_IOCTL_PARAM32, *PHPT_IOCTL_PARAM32;
+
+#if !defined(__KERNEL__) || defined(SIMULATE)
+/*
+ * User-mode ioctl parameter passing conventions:
+ *   The ioctl function implementation is platform specific, so we don't
+ * have forced rules for it. However, it's suggested to use a parameter
+ * passing method as below
+ *   1) Put all input data continuously in an input buffer.
+ *   2) Prepare an output buffer with enough size if needed.
+ *   3) Fill a HPT_IOCTL_PARAM structure.
+ *   4) Pass the structure to driver through a platform-specific method.
+ * This is implemented in the mid-layer user-mode library. The UI
+ * programmer needn't care about it.
+ */
+
+/************************************************************************
+ * User mode functions
+ ************************************************************************/
+/*
+ * hpt_get_version
+ * Version compatibility: all versions
+ * Parameters:
+ *  None
+ * Returns:
+ *  interface version. 0 when fail.
+ */
+HPT_U32 hpt_get_version(void);
+
+/*
+ * hpt_get_driver_capabilities
+ * Version compatibility: v1.0.0.2 or later
+ * Parameters:
+ *  Pointer to receive a DRIVE_CAPABILITIES structure. The caller must set
+ *  dwSize member to sizeof(DRIVER_CAPABILITIES). The callee must check this
+ *  member to see if it's correct.
+ * Returns:
+ *  0 - Success
+ */
+int hpt_get_driver_capabilities(PDRIVER_CAPABILITIES cap);
+int hpt_get_driver_capabilities_v2(PDRIVER_CAPABILITIES_V2 cap);
+
+/*
+ * hpt_get_controller_count
+ * Version compatibility: v1.0.0.1 or later
+ * Parameters:
+ *  None
+ * Returns:
+ *  number of controllers
+ */
+int hpt_get_controller_count(void);
+
+/* hpt_get_controller_info
+ * Version compatibility: v1.0.0.1 or later
+ * Parameters:
+ *  id      Controller id
+ *  pInfo   pointer to CONTROLLER_INFO buffer
+ * Returns:
+ *  0       Success, controller info is put into (*pInfo ).
+ */
+int hpt_get_controller_info(int id, PCONTROLLER_INFO pInfo);
+
+#if HPT_INTERFACE_VERSION>=0x01020000
+/* hpt_get_controller_info_v2
+ * Version compatibility: v2.0.0.0 or later
+ * Parameters:
+ *  id      Controller id
+ *  pInfo   pointer to CONTROLLER_INFO_V2 buffer
+ * Returns:
+ *  0       Success, controller info is put into (*pInfo ).
+ */
+int hpt_get_controller_info_v2(int id, PCONTROLLER_INFO_V2 pInfo);
+
+/* hpt_get_controller_info_v3
+ * Version compatibility: v2.0.0.0 or later
+ * Parameters:
+ *  id      Controller id
+ *  pInfo   pointer to CONTROLLER_INFO_V3 buffer
+ * Returns:
+ *  0       Success, controller info is put into (*pInfo ).
+ */
+int hpt_get_controller_info_v3(int id, PCONTROLLER_INFO_V3 pInfo);
+#endif
+
+/* hpt_get_channel_info
+ * Version compatibility: v1.0.0.1 or later
+ * Parameters:
+ *  id      Controller id
+ *  bus     bus number
+ *  pInfo   pointer to CHANNEL_INFO buffer
+ * Returns:
+ *  0       Success, channel info is put into (*pInfo ).
+ */
+int hpt_get_channel_info(int id, int bus, PCHANNEL_INFO pInfo);
+
+/* hpt_get_channel_info_v2
+ * Version compatibility: v1.0.0.1 or later
+ * Parameters:
+ *  id      Controller id
+ *  bus     bus number
+ *  pInfo   pointer to CHANNEL_INFO buffer
+ * Returns:
+ *  0       Success, channel info is put into (*pInfo ).
+ */
+int hpt_get_channel_info_v2(int id, int bus, PCHANNEL_INFO_V2 pInfo);
+
+/* hpt_get_logical_devices
+ * Version compatibility: v1.0.0.1 or later
+ * Parameters:
+ *  pIds        pointer to a DEVICEID array
+ *  nMaxCount   array size
+ * Returns:
+ *  Number of ID returned. All logical device IDs are put into pIds array.
+ *  Note: A spare disk is not a logical device.
+ */
+int hpt_get_logical_devices(DEVICEID * pIds, int nMaxCount);
+
+/* hpt_get_physical_devices
+ * Version compatibility: v2.1.0.0 or later
+ * Parameters:
+ *  pIds        pointer to a DEVICEID array
+ *  nMaxCount   array size
+ * Returns:
+ *  Number of ID returned. All physical device IDs are put into pIds array.
+ */
+int hpt_get_physical_devices(DEVICEID * pIds, int nMaxCount);
+
+/* hpt_get_device_info
+ * Version compatibility: v1.0.0.1 or later
+ * Parameters:
+ *  id      logical device id
+ *  pInfo   pointer to LOGICAL_DEVICE_INFO structure
+ * Returns:
+ *  0 - Success
+ */
+int hpt_get_device_info(DEVICEID id, PLOGICAL_DEVICE_INFO pInfo);
+
+/* hpt_create_array
+ * Version compatibility: v1.0.0.1 or later
+ * Parameters:
+ *  pParam      pointer to CREATE_ARRAY_PARAMS structure
+ * Returns:
+ *  0   failed
+ *  else return array id
+ */
+DEVICEID hpt_create_array(PCREATE_ARRAY_PARAMS pParam);
+
+/* hpt_delete_array
+ * Version compatibility: v1.0.0.1 or later
+ * Parameters:
+ *  id      array id
+ * Returns:
+ *  0   Success
+ */
+int hpt_delete_array(DEVICEID id, HPT_U32 options);
+
+/* hpt_device_io
+ *  Read/write data on array and physcal device.
+ * Version compatibility: v1.0.0.1 or later
+ * Parameters:
+ *  id      device id. If it's an array ID, IO will be performed on the array.
+ *          If it's a physical device ID, IO will be performed on the device.
+ *  cmd     IO_COMMAND_READ or IO_COMMAND_WRITE
+ *  buffer  data buffer
+ *  length  data size
+ * Returns:
+ *  0   Success
+ */
+int hpt_device_io(DEVICEID id, int cmd, HPT_U32 lba, HPT_U32 nSector, void * buffer);
+
+/* hpt_add_disk_to_array
+ *   Used to dynamicly add a disk to an RAID1, RAID0/1, RAID1/0 or RAID5 array.
+ *   Auto-rebuild will start.
+ * Version compatibility: v1.0.0.1 or later
+ * Parameters:
+ *  idArray     array id
+ *  idDisk      disk id
+ * Returns:
+ *  0   Success
+ */
+int hpt_add_disk_to_array(DEVICEID idArray, DEVICEID idDisk);
+
+/* hpt_add_spare_disk
+ * Version compatibility: v1.0.0.1 or later
+ *   Add a disk to spare pool.
+ * Parameters:
+ *  idDisk      disk id
+ * Returns:
+ *  0   Success
+ */
+int hpt_add_spare_disk(DEVICEID idDisk);
+
+/* hpt_add_dedicated_spare
+ * Version compatibility: v1.0.0.3 or later
+ *   Add a spare disk to an array
+ * Parameters:
+ *  idDisk      disk id
+ *  idArray     array id
+ * Returns:
+ *  0   Success
+ */
+int hpt_add_dedicated_spare(DEVICEID idDisk, DEVICEID idArray);
+
+/* hpt_remove_spare_disk
+ *   remove a disk from spare pool.
+ * Version compatibility: v1.0.0.1 or later
+ * Parameters:
+ *  idDisk      disk id
+ * Returns:
+ *  0   Success
+ */
+int hpt_remove_spare_disk(DEVICEID idDisk);
+
+/* hpt_get_event
+ *   Used to poll events from driver.
+ * Version compatibility: v1.0.0.1 or later
+ * Parameters:
+ *   pEvent    pointer to HPT_EVENT structure
+ * Returns:
+ *  0   Success, event info is filled in *pEvent
+ */
+int hpt_get_event(PHPT_EVENT pEvent);
+
+/* hpt_rebuild_data_block
+ *   Used to copy data from source disk and mirror disk.
+ * Version compatibility: v1.0.0.1 or later
+ * Parameters:
+ *   idArray        Array ID (RAID1, 0/1 or RAID5)
+ *   Lba            Start LBA for each array member
+ *   nSector        Number of sectors for each array member (RAID 5 will ignore this parameter)
+ *
+ * Returns:
+ *  0   Success, event info is filled in *pEvent
+ */
+int hpt_rebuild_data_block(DEVICEID idMirror, HPT_U32 Lba, HPT_U8 nSector);
+#define hpt_rebuild_mirror(p1, p2, p3) hpt_rebuild_data_block(p1, p2, p3)
+
+/* hpt_set_array_state
+ *   set array state.
+ * Version compatibility: v1.0.0.1 or later
+ * Parameters:
+ *   idArray        Array ID
+ *   state          See above 'array states' constants, possible values are:
+ *     MIRROR_REBUILD_START
+ *        Indicate that GUI wants to rebuild a mirror array
+ *     MIRROR_REBUILD_ABORT
+ *        GUI wants to abort rebuilding an array
+ *     MIRROR_REBUILD_COMPLETE
+ *        GUI finished to rebuild an array. If rebuild is done by driver this
+ *        state has no use
+ *
+ * Returns:
+ *  0   Success
+ */
+int hpt_set_array_state(DEVICEID idArray, HPT_U32 state);
+
+/* hpt_set_array_info
+ *   set array info.
+ * Version compatibility: v1.0.0.1 or later
+ * Parameters:
+ *   idArray        Array ID
+ *   pInfo          pointer to new info
+ *
+ * Returns:
+ *  0   Success
+ */
+int hpt_set_array_info(DEVICEID idArray, PALTERABLE_ARRAY_INFO pInfo);
+
+/* hpt_set_device_info
+ *   set device info.
+ * Version compatibility: v1.0.0.1 or later
+ * Parameters:
+ *   idDisk         device ID
+ *   pInfo          pointer to new info
+ *
+ * Returns:
+ *  0   Success
+ * Additional notes:
+ *  If idDisk==0, call to this function will stop buzzer on the adapter
+ *  (if supported by driver).
+ */
+int hpt_set_device_info(DEVICEID idDisk, PALTERABLE_DEVICE_INFO pInfo);
+
+#if HPT_INTERFACE_VERSION >= 0x01000004
+int hpt_set_device_info_v2(DEVICEID idDisk, PALTERABLE_DEVICE_INFO_V2 pInfo);
+#endif
+
+/* hpt_rescan_devices
+ *   rescan devices
+ * Version compatibility: v1.0.0.1 or later
+ * Parameters:
+ *   None
+ * Returns:
+ *   0  Success
+ */
+int hpt_rescan_devices(void);
+
+/* hpt_get_601_info
+ *   Get HPT601 status
+ * Version compatibiilty: v1.0.0.3 or later
+ * Parameters:
+ *   idDisk - Disk handle
+ *   PHPT601_INFO - pointer to HPT601 info buffer
+ * Returns:
+ *   0  Success
+ */
+int hpt_get_601_info(DEVICEID idDisk, PHPT601_INFO pInfo);
+
+/* hpt_set_601_info
+ *   HPT601 function control
+ * Version compatibiilty: v1.0.0.3 or later
+ * Parameters:
+ *   idDisk - Disk handle
+ *   PHPT601_INFO - pointer to HPT601 info buffer
+ * Returns:
+ *   0  Success
+ */
+int hpt_set_601_info(DEVICEID idDisk, PHPT601_INFO pInfo);
+
+/* hpt_lock_device
+ *   Lock a block on a device (prevent OS accessing it)
+ * Version compatibiilty: v1.0.0.3 or later
+ * Parameters:
+ *   idDisk - Disk handle
+ *   Lba - Start LBA
+ *   nSectors - number of sectors
+ * Returns:
+ *   0  Success
+ */
+int hpt_lock_device(DEVICEID idDisk, HPT_U32 Lba, HPT_U8 nSectors);
+
+/* hpt_lock_device
+ *   Unlock a device
+ * Version compatibiilty: v1.0.0.3 or later
+ * Parameters:
+ *   idDisk - Disk handle
+ * Returns:
+ *   0  Success
+ */
+int hpt_unlock_device(DEVICEID idDisk);
+
+/* hpt_ide_pass_through
+ *  send a ATA passthrough command to a device.
+ * Version compatibility: v1.0.0.3 or later
+ * Parameters:
+ *   p - IDE_PASS_THROUGH header pointer
+ * Returns:
+ *   0  Success
+ */
+int hpt_ide_pass_through(PIDE_PASS_THROUGH_HEADER p);
+int hpt_ide_pass_through_v2(PIDE_PASS_THROUGH_HEADER_V2 p);
+
+/* hpt_scsi_passthrough
+ *  send a SCSI passthrough command to a device.
+ * Version compatibility: v2.0.0.0 or later
+ * Parameters:
+ *   in  - HPT_SCSI_PASSTHROUGH_IN header pointer
+ *   out - PHPT_SCSI_PASSTHROUGH_OUT header pointer
+ *   insize, outsize - in/out buffer size
+ * Returns:
+ *   0  Success
+ */
+int hpt_scsi_passthrough(PHPT_SCSI_PASSTHROUGH_IN in, HPT_U32 insize,
+				PHPT_SCSI_PASSTHROUGH_OUT out, HPT_U32 outsize);
+
+/* hpt_verify_data_block
+ *   verify data block on RAID1 or RAID5.
+ * Version compatibility: v1.0.0.3 or later
+ * Parameters:
+ *   idArray - Array ID
+ *   Lba - block number (on each array member, not logical block!)
+ *   nSectors - Sectors for each member (RAID 5 will ignore this parameter)
+ * Returns:
+ *   0  Success
+ *   1  Data compare error
+ *   2  I/O error
+ */
+int hpt_verify_data_block(DEVICEID idArray, HPT_U32 Lba, HPT_U8 nSectors);
+
+/* hpt_initialize_data_block
+ *   initialize data block (fill with zero) on RAID5
+ * Version compatibility: v1.0.0.3 or later
+ * Parameters:
+ *   idArray - Array ID
+ *   Lba - block number (on each array member, not logical block!)
+ *   nSectors - Sectors for each member (RAID 5 will ignore this parameter)
+ * Returns:
+ *   0  Success
+ */
+int hpt_initialize_data_block(DEVICEID idArray, HPT_U32 Lba, HPT_U8 nSectors);
+
+/* hpt_device_io_ex
+ *   extended device I/O function
+ * Version compatibility: v1.0.0.3 or later
+ * Parameters:
+ *   idArray - Array ID
+ *   Lba - block number (on each array member, not logical block!)
+ *   nSectors - Sectors for each member
+ *   buffer - I/O buffer or s/g address
+ * Returns:
+ *   0  Success
+ */
+int hpt_device_io_ex(PDEVICE_IO_EX_PARAMS param);
+
+/* hpt_set_boot_mark
+ *   select boot device
+ * Version compatibility: v1.0.0.3 or later
+ * Parameters:
+ *   id - logical device ID. If id is 0 the boot mark will be removed.
+ * Returns:
+ *   0  Success
+ */
+int hpt_set_boot_mark(DEVICEID id);
+
+/* hpt_query_remove
+ *  check if device can be removed safely
+ * Version compatibility: v1.0.0.4 or later
+ * Parameters:
+ *  ndev - number of devices
+ *  pIds - device ID list
+ * Returns:
+ *  0  - Success
+ *  -1 - unknown error
+ *  n  - the n-th device that can't be removed
+ */
+int hpt_query_remove(HPT_U32 ndev, DEVICEID *pIds);
+
+/* hpt_remove_devices
+ *  remove a list of devices
+ * Version compatibility: v1.0.0.4 or later
+ * Parameters:
+ *  ndev - number of devices
+ *  pIds - device ID list
+ * Returns:
+ *  0  - Success
+ *  -1 - unknown error
+ *  n  - the n-th device that can't be removed
+ */
+int hpt_remove_devices(HPT_U32 ndev, DEVICEID *pIds);
+
+/* hpt_create_array_v2
+ * Version compatibility: v1.1.0.0 or later
+ * Parameters:
+ *  pParam      pointer to CREATE_ARRAY_PARAMS_V2 structure
+ * Returns:
+ *  0   failed
+ *  else return array id
+ */
+#if HPT_INTERFACE_VERSION>=0x01010000
+DEVICEID hpt_create_array_v2(PCREATE_ARRAY_PARAMS_V2 pParam);
+#endif
+
+/* hpt_create_array_v3
+ * Version compatibility: v2.0.0.1 or later
+ * Parameters:
+ *  pParam      pointer to CREATE_ARRAY_PARAMS_V3 structure
+ * Returns:
+ *  0   failed
+ *  else return array id
+ */
+#if HPT_INTERFACE_VERSION>=0x02000001
+DEVICEID hpt_create_array_v3(PCREATE_ARRAY_PARAMS_V3 pParam);
+#endif
+
+/* hpt_get_device_info_v2
+ * Version compatibility: v1.1.0.0 or later
+ * Parameters:
+ *  id      logical device id
+ *  pInfo   pointer to LOGICAL_DEVICE_INFO_V2 structure
+ * Returns:
+ *  0 - Success
+ */
+#if HPT_INTERFACE_VERSION>=0x01010000
+int hpt_get_device_info_v2(DEVICEID id, PLOGICAL_DEVICE_INFO_V2 pInfo);
+#endif
+
+/* hpt_get_device_info_v3
+ * Version compatibility: v1.2.0.0 or later
+ * Parameters:
+ *  id      logical device id
+ *  pInfo   pointer to LOGICAL_DEVICE_INFO_V3 structure
+ * Returns:
+ *  0 - Success
+ */
+#if HPT_INTERFACE_VERSION>=0x01020000
+int hpt_get_device_info_v3(DEVICEID id, PLOGICAL_DEVICE_INFO_V3 pInfo);
+#endif
+
+/* hpt_get_device_info_v4
+ * Version compatibility: v2.0.0.1 or later
+ * Parameters:
+ *  id      logical device id
+ *  pInfo   pointer to LOGICAL_DEVICE_INFO_V4 structure
+ * Returns:
+ *  0 - Success
+ */
+#if HPT_INTERFACE_VERSION>=0x02000001
+int hpt_get_device_info_v4(DEVICEID id, PLOGICAL_DEVICE_INFO_V4 pInfo);
+#endif
+
+/* hpt_create_transform
+ *  create a transform instance.
+ * Version compatibility: v2.0.0.0 or later
+ * Parameters:
+ *  idArray - source array
+ *  destInfo - destination array info
+ * Returns:
+ *  destination array id
+ */
+#if HPT_INTERFACE_VERSION>=0x02000000
+DEVICEID hpt_create_transform(DEVICEID idArray, PCREATE_ARRAY_PARAMS_V2 destInfo);
+#endif
+
+/* hpt_create_transform_v2
+ *  create a transform instance.
+ * Version compatibility: v2.0.0.1 or later
+ * Parameters:
+ *  idArray - source array
+ *  destInfo - destination array info
+ * Returns:
+ *  destination array id
+ */
+#if HPT_INTERFACE_VERSION>=0x02000001
+DEVICEID hpt_create_transform_v2(DEVICEID idArray, PCREATE_ARRAY_PARAMS_V3 destInfo);
+#endif
+
+/* hpt_step_transform
+ *  move a block in a tranform progress.
+ *  This function is called by mid-layer, not GUI (which uses set_array_state instead).
+ * Version compatibility: v2.0.0.0 or later
+ * Parameters:
+ *  idArray - destination array ID
+ *            the source ID will be invalid when transform complete.
+ * Returns:
+ *  0 - Success
+ */
+#if HPT_INTERFACE_VERSION>=0x02000000
+int hpt_step_transform(DEVICEID idArray);
+#endif
+
+/* hpt_set_vdev_info
+ *  set information for disk or array
+ * Version compatibility: v1.2.0.0 or later
+ * Parameters:
+ *  dev - destination device
+ *
+ * Returns:
+ *  0 - Success
+ */
+#if HPT_INTERFACE_VERSION>=0x01020000
+int hpt_set_vdev_info(DEVICEID dev, PSET_VDEV_INFO pInfo);
+#endif
+
+/* hpt_init_disks
+ *  initialize disks for use
+ * Version compatibility: v2.0.0.0 or later
+ * Parameters:
+ *  ndev - number of disks to initialize
+ *  pIds - array of DEVICEID
+ *
+ * Returns:
+ *  0 - Success
+ */
+#if HPT_INTERFACE_VERSION>=0x02000000
+int hpt_init_disks(HPT_U32 ndev, DEVICEID * pIds);
+#endif
+
+/* hpt_calc_max_array_capacity
+ *  cap max capacity of the array user want to create or transform
+ * Version compatibility: v1.2.0.0 or later
+ * Parameters:
+ *  source - if transform, this is the source array, otherwise, it should be zero
+ *  destInfo - target array params
+ * Returns:
+ *  0 - Success
+ *  cap - max capacity of the target array
+ */
+#if HPT_INTERFACE_VERSION>=0x01020000
+int hpt_calc_max_array_capacity(DEVICEID source, PCREATE_ARRAY_PARAMS_V2 destInfo, HPT_U64 * cap);
+#endif
+
+/* hpt_calc_max_array_capacity_v2
+ *  cap max capacity of the array user want to create or transform
+ * Version compatibility: v2.0.0.1 or later
+ * Parameters:
+ *  source - if transform, this is the source array, otherwise, it should be zero
+ *  destInfo - target array params
+ * Returns:
+ *  0 - Success
+ *  cap - max capacity of the target array
+ */
+#if HPT_INTERFACE_VERSION>=0x02000001
+int hpt_calc_max_array_capacity_v2(DEVICEID source, PCREATE_ARRAY_PARAMS_V3 destInfo, HPT_U64 * cap);
+#endif
+
+/* hpt_rebuild_data_block2
+ *   Used to copy data from source disk and mirror disk.
+ * Version compatibility: v1.1.0.0 or later
+ * Parameters:
+ *   idArray        Array ID (RAID1, 0/1 or RAID5)
+ *   Lba            Start LBA for each array member
+ *   nSector        Number of sectors for each array member (RAID 5 will ignore this parameter)
+ *
+ * Returns:
+ *  0   Success, event info is filled in *pEvent
+ */
+#if HPT_INTERFACE_VERSION>=0x01010000
+int hpt_rebuild_data_block_v2(DEVICEID idMirror, HPT_U64 Lba, HPT_U16 nSector);
+#endif
+
+/* hpt_verify_data_block2
+ *   verify data block on RAID1 or RAID5.
+ * Version compatibility: v1.1.0.0 or later
+ * Parameters:
+ *   idArray - Array ID
+ *   Lba - block number (on each array member, not logical block!)
+ *   nSectors - Sectors for each member (RAID 5 will ignore this parameter)
+ * Returns:
+ *   0  Success
+ *   1  Data compare error
+ *   2  I/O error
+ */
+#if HPT_INTERFACE_VERSION>=0x01010000
+int hpt_verify_data_block_v2(DEVICEID idArray, HPT_U64 Lba, HPT_U16 nSectors);
+#endif
+
+/* hpt_initialize_data_block2
+ *   initialize data block (fill with zero) on RAID5
+ * Version compatibility: v1.1.0.0 or later
+ * Parameters:
+ *   idArray - Array ID
+ *   Lba - block number (on each array member, not logical block!)
+ *   nSectors - Sectors for each member (RAID 5 will ignore this parameter)
+ * Returns:
+ *   0  Success
+ */
+#if HPT_INTERFACE_VERSION>=0x01010000
+int hpt_initialize_data_block_v2(DEVICEID idArray, HPT_U64 Lba, HPT_U16 nSectors);
+#endif
+
+/* hpt_i2c_transaction
+ *   perform an transaction on i2c bus
+ * Version compatibility: v2.0.0.0 or later
+ * Parameters:
+ *   indata[0] - controller ID
+ * Returns:
+ *   0  Success
+ */
+#if HPT_INTERFACE_VERSION>=0x01020000
+int hpt_i2c_transaction(HPT_U8 *indata, HPT_U32 inlen, HPT_U8 *outdata, HPT_U32 outlen, HPT_U32 *poutlen);
+#endif
+
+/* hpt_get_parameter_list
+ *   get a list of driver parameters.
+ * Version compatibility: v1.0.0.0 or later
+ * Parameters:
+ *   location - parameter location
+ *   outBuffer - a buffer to hold the output
+ *   outBufferSize - size of outBuffer
+ * Returns:
+ *   0  Success
+ *      put in outBuffer a list of zero terminated parameter names. the whole list
+ *      is terminated with an additional zero byte.
+ */
+int hpt_get_parameter_list(HPT_U32 location, char *outBuffer, HPT_U32 outBufferSize);
+
+/* hpt_{get,set}_parameter
+ *   get/set a parameter value.
+ * Version compatibility: v1.0.0.0 or later
+ * Parameters:
+ *   pParam - a pointer to HPT_DRIVER_PARAMETER.
+ * Returns:
+ *   0  Success
+ */
+int hpt_get_parameter(PHPT_DRIVER_PARAMETER pParam);
+int hpt_set_parameter(PHPT_DRIVER_PARAMETER pParam);
+int hpt_reenumerate_device(DEVICEID id);
+
+/*
+ * hpt_get_enclosure_count
+ * Version compatibility: v2.1.0.0 or later
+ * Parameters:
+ *  controller_id
+ * Returns:
+ *  number of enclosurers
+ */
+int hpt_get_enclosure_count(int ctlr_id);
+
+/* hpt_get_enclosure_info
+ * Version compatibility: v2.1.0.0 or later
+ * Parameters:
+ *  id      enclosure id
+ *  pInfo   pointer to ENCLOSURE_INFO buffer
+ * Returns:
+ *  0       Success, enclosure info is put into (*pInfo ).
+ */
+int hpt_get_enclosure_info(int ctlr_id, int enc_id, PENCLOSURE_INFO pInfo);
+
+int hpt_get_enclosure_info_v2(int ctlr_id, int enc_id, PENCLOSURE_INFO_V2 pInfo);
+
+int hpt_get_enclosure_info_v3(int ctlr_id, int enc_id, PENCLOSURE_INFO_V3 pInfo);
+
+/* performance monitor interface
+ * Version compatibility: v2.1.0.0 or later
+ */
+int hpt_get_perfmon_status(int ctlr_id, int *p_status);
+int hpt_set_perfmon_status(int ctlr_id, int enable);
+int hpt_get_perfmon_data(DEVICEID id, PHPT_PM_IOSTAT iostat);
+
+/* hpt_get_controller_venid
+ * Version compatibility: v1.0.0.0 or later
+ */
+int hpt_get_controller_venid(int ctlr_id, HPT_U32 *venid);
+
+#endif
+
+#pragma pack()
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/sys/dev/hpt27xx/i386-elf.hpt27xx_lib.o.uu b/sys/dev/hpt27xx/i386-elf.hpt27xx_lib.o.uu
new file mode 100644
index 0000000..ce5aafe
--- /dev/null
+++ b/sys/dev/hpt27xx/i386-elf.hpt27xx_lib.o.uu
@@ -0,0 +1,15583 @@
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+M``$!``#8!0```0$``-P%```!`0``X`4```$!``#D!0```0$``.@%```!`0``
+M[`4```$!``#P!0```0$``/0%```!`0``^`4```$!``#\!0```0$````&```!
+MM@``!`8```$!```(!@```0$```P&```!`0``$`8```$!```4!@```0$``!@&
+M```!`0``'`8```$!```@!@```0$``"0&```!`0``*`8```$!```L!@```0$`
+M`#`&```!`0``-`8```$!```X!@```0$``#P&```!!P$`1`8```$!``!(!@``
+M`0$``$P&```!`0``4`8```$!``!4!@```>@``*`+```!!@``K`L```$!``"P
+M"P```0$``+0+```!`0``N`L```$!``"\"P```0$``,`+```!`0``Q`L```$!
+M``#("P```0$``,P+```!`0``T`L```$!``#4"P```0$``-@+```!`0``W`L`
+M``$!``#@"P```=D!`.0+```!`0``Z`L```$!``#L"P```0$``/`+```!`0``
+M]`L```$!``#X"P```0$``/P+```!`0````P```$!```$#````0$```@,```!
+M`0``#`P```$!```0#````0$``!0,```!`0``&`P```$!```<#````4T!`"`,
+M```!`0``)`P```$!```H#````0$``"P,```!`0``,`P```$!```T#````7@!
+M`(`1```!!@``C!$```$!``"0$0```0$``)01```!`0``F!$```$!``"<$0``
+M`0$``*`1```!`0``I!$```$!``"H$0```0$``*P1```!`0``L!$```$!``"T
+M$0```0$``+@1```!`0``O!$```$!``#`$0```9\"`,01```!`0``R!$```$!
+M``#,$0```0$``-`1```!`0``U!$```$!``#8$0```0$``-P1```!`0``X!$`
+M``$!``#D$0```0$``.@1```!`0``[!$```$!``#P$0```0$``/01```!`0``
+M^!$```$!``#\$0```<X"```2```!`0``!!(```$!```($@```0$```P2```!
+M`0``$!(```$!```4$@```=("`(`7```!!@``C!<```$!``"0%P```0$``)07
+M```!`0``F!<```$!``"<%P```0$``*`7```!`0``I!<```$!``"H%P```0$`
+M`*P7```!`0``L!<```$!``"T%P```0$``+@7```!`0``O!<```$!``#`%P``
+M`;<#`,07```!`0``R!<```$!``#,%P```0$``-`7```!`0``U!<```$!``#8
+M%P```0$``-P7```!`0``X!<```$!``#D%P```0$``.@7```!`0``[!<```$!
+M``#P%P```0$``/07```!`0``^!<```$!``#\%P```78#```8```!`0``!!@`
+M``$!```(&````0$```P8```!`0``$!@```$!```4&````50#`%P8```!`0``
+M8!@```$!``!D&````0$``'`8```!`0``=!@```$!``!X&````0$``*08```!
+M`0``K!@```$!``"X&````0$``,`8```!`0``S!@```$!``#4&````0$``.`8
+M```!`0``Z!@```$!``#T&````0$``/P8```!`0``"!D```$!```0&0```0$`
+M`!P9```!`0``)!D```$!```P&0```0$``#09```!`0``.!D```$!``!$&0``
+M`0$``$@9```!`0``3!D```$!``!8&0```0$``&`9```!`0``;!D```$!``!T
+M&0```0$``(`9```!`0``A!D```$!``"(&0```0$``)09```!`0``F!D```$!
+M``"<&0```0$``*@9```!`0``K!D```$!``"P&0```0$``+P9```!`0``P!D`
+M``$!``#$&0```0$``-`9```!`0``U!D```$!``#8&0```0$``.09```!`0``
+M[!D```$!``#X&0```0$````:```!`0``#!H```$!```4&@```0$``"`:```!
+M`0``*!H```$!```T&@```0$``#P:```!`0``2!H```$!``!0&@```0$``%P:
+M```!`0``9!H```$!``!P&@```0$``'@:```!`0``A!H```$!``",&@```0$`
+M`)@:```!`0``H!H```$!``"L&@```0$``+`:```!`0``M!H```$!``#`&@``
+M`0$``,0:```!`0``R!H```$!``#4&@```0$``-P:```!`0``Z!H```$!``#P
+M&@```0$``/P:```!`0``!!L```$!```0&P```0$``!@;```!`0``)!L```$!
+M```L&P```0$``#@;```!`0``/!L```$!``!`&P```0$``$P;```!`0``5!L`
+M``$!``!@&P```0$``&0;```!`0``:!L```$!``!T&P```0$``'P;```!`0``
+MB!L```$!``",&P```0$``)`;```!`0``G!L```$!``"D&P```0$``+`;```!
+M`0``N!L```$!``#$&P```0$``,P;```!`0``V!L```$!``#<&P```0$``.`;
+M```!`0``[!L```$!``#P&P```0$``/0;```!`0```!P```$!```('````0$`
+M`!0<```!`0``'!P```$!```H'````0$``#`<```!`0``/!P```$!``!$'```
+M`0$``%`<```!`0``6!P```$!``!D'````0$``&P<```!`0``>!P```$!``"`
+M'````0$``(P<```!`0``E!P```$!``"@'````0$``*0<```!`0``J!P```$!
+M``"T'````0$``+P<```!`0``R!P```$!``#0'````0$``-P<```!`0``Y!P`
+M``$!``#P'````0$``/@<```!`0``0!T```$!``!$'0```0$``)P=```!`0``
+MH!T```$!``"D'0```94$`*@=```!`0``K!T```$!````'@```0$```0>```!
+ME00`7!X```$!``!@'@```0$``&0>```!`0``:!X```$!``!L'@```0$``'`>
+M```!`0``=!X```$!``!X'@```0$``'P>```!`0``O!X```$!``#`'@```0$`
+9`,0>```!E00`R!X```$!``#,'@```0$`````
+`
+end
diff --git a/sys/dev/hpt27xx/ldm.h b/sys/dev/hpt27xx/ldm.h
new file mode 100644
index 0000000..d3b5e61
--- /dev/null
+++ b/sys/dev/hpt27xx/ldm.h
@@ -0,0 +1,533 @@
+/*-
+ * Copyright (c) 2011 HighPoint Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <dev/hpt27xx/hpt27xx_config.h>
+
+#ifndef _HPT_LDM_H_
+#define _HPT_LDM_H_
+
+#define VERMAGIC_LDM 75
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+#define __hpt_set_ver(x, v1, v2, v3, v4, v5) x ## _R_ ## v1 ## _ ## v2 ## _ ## v3 ## _ ## v4 ## _ ## v5
+#define _hpt_set_ver(x, v1, v2, v3, v4, v5)  __hpt_set_ver(x, v1, v2, v3, v4, v5)
+#define hpt_set_ver(x)               _hpt_set_ver(x, VERMAGIC_OSM, VERMAGIC_HIM, VERMAGIC_LDM, VERMAGIC_ARRAY, MAX_MEMBERS)
+
+#define ldm_register_him        hpt_set_ver(ldm_register_him)
+#define ldm_register_vdev_class hpt_set_ver(ldm_register_vdev_class)
+#define ldm_alloc_cmds          hpt_set_ver(ldm_alloc_cmds)
+
+
+#ifndef HPT_INTERFACE_VERSION
+#define HPT_INTERFACE_VERSION 0x02010000
+#endif
+
+#ifndef MAX_PARTITIONS_PER_DISK
+#define MAX_PARTITIONS_PER_DISK	4
+#endif
+
+#if defined(__MAX_PARTITIONS_PER_DISK) && MAX_PARTITIONS_PER_DISK > __MAX_PARTITIONS_PER_DISK
+#error "Please redefine MAX_PARTITIONS_PER_DISK!!!"
+#endif
+
+#define MAX(a,b) (((a)>(b))?(a):(b))
+#define MIN(a,b) (((a)<(b))?(a):(b))
+
+
+typedef char check_HPT_TIME_is_unsigned[ (HPT_TIME)(-1) > 0 ? 1 : -1 ];
+
+#define hpt_time_after_eq(a, b) ((int)(a) - (int)(b) >= 0)
+#define hpt_time_after(a, b) ((int)(a) - (int)(b) > 0)
+
+
+
+struct freelist {
+	int dma;
+	HPT_UINT alignment;
+	HPT_UINT count;
+	HPT_UINT size;
+	void * head;
+	struct freelist *next;
+#if DBG
+	char *tag;
+	HPT_UINT reserved_count; 
+	#define freelist_debug_tag(list, _tag) (list)->tag = _tag
+#else 
+	#define freelist_debug_tag(list, _tag)
+#endif
+};
+
+
+void freelist_reserve(struct freelist *list, void *osext, HPT_UINT size, HPT_UINT count);
+
+void *freelist_get(struct freelist *);
+void freelist_put(struct freelist *, void *p);
+
+void freelist_reserve_dma(struct freelist *list, void *osext, HPT_UINT size, HPT_UINT alignment, HPT_UINT count);
+void *freelist_get_dma(struct freelist *, BUS_ADDRESS *busaddr);
+void freelist_put_dma(struct freelist *, void *p, BUS_ADDRESS busaddr);
+
+
+#define freelist_reserve_with_tag(list, osext, size, count) \
+	do {\
+		freelist_debug_tag(list, #list  " at " __FILE__);\
+		freelist_reserve(list, osext, (HPT_UINT)(size), (HPT_UINT)(count));\
+	}while(0)
+
+#define freelist_reserve_dma_with_tag(list, osext, size, alignment, count) \
+	do {\
+		freelist_debug_tag(list, #list " at " __FILE__);\
+		freelist_reserve_dma(list, osext, (HPT_UINT)(size), (HPT_UINT)(alignment), (HPT_UINT)(count));\
+	}while(0)
+
+struct lock_request {
+	HPT_U64 start, end;
+	struct lock_request *next;
+	struct list_head waiters; /* blocked commands */
+	struct tq_item callback;
+	int lock_cc;
+};
+
+#define INIT_LOCK_REQUEST(req, _start, _end, _cb, _arg, _cc) \
+	do {\
+		(req)->next = 0;\
+		(req)->start = _start;\
+		(req)->end = _end;\
+		INIT_TQ_ITEM(&(req)->callback, _cb, _arg);\
+		INIT_LIST_HEAD(&(req)->waiters);\
+		(req)->lock_cc = _cc;\
+	} while (0)
+
+struct task_queue {
+	struct tq_item *head, *tail;
+};
+
+#define TQ_EMPTY(tq) ((tq)->head==0)
+
+struct dmapool_order {
+	HPT_UINT npages;
+	struct tq_item wakeup_fn;
+	struct dmapool_order *next;
+};
+
+struct dmapool_client {
+	void * handle;
+	HPT_UINT (*shrink)(void *handle, HPT_UINT npages);
+	int (*resume)(void *handle);
+	struct dmapool_client *next;
+};
+
+typedef struct _VBUS * PVBUS;
+typedef struct _VDEV * PVDEV;
+
+
+void dmapool_register_client(PVBUS vbus, struct dmapool_client *client);
+
+
+void dmapool_active(PVBUS vbus);
+
+/* return 0 if the request is immediately satisfied, non-zero otherwise. */
+int dmapool_make_order(PVBUS vbus, struct dmapool_order *order);
+
+
+void *dmapool_get_page(PVBUS vbus, BUS_ADDRESS *busaddr);
+void *dmapool_get_page_at(PVBUS vbus, void *p, BUS_ADDRESS *busaddr);
+void dmapool_put_page(PVBUS vbus, void *p, BUS_ADDRESS busaddr);
+void dmapool_init(PVBUS vbus);
+HPT_UINT dmapool_max_class_pages(PVBUS vbus);
+
+
+struct timer_call {
+	HPT_U32 interval; /*microseconds*/
+	HPT_TIME expire_time; /*microseconds*/
+	void (*proc)(void * arg);
+	void * arg;
+	struct timer_call ** pprev;
+	struct timer_call * next;
+};
+
+#define ldm_init_timer(timer) do { (timer)->next=0; (timer)->pprev=0; } while (0)
+
+#define INIT_TIMER_CALL(timer, _interval, _proc, _arg) \
+	do { \
+		HPT_ASSERT((timer)->next==0 && (timer)->pprev==0);\
+		(timer)->interval = _interval;\
+		(timer)->proc = _proc;\
+		(timer)->arg = _arg;\
+	} while(0)
+
+void ldm_request_timer(PVBUS vbus, struct timer_call * tc);
+void ldm_remove_timer(PVBUS vbus, struct timer_call * tc);
+void ldm_on_timer(PVBUS vbus);
+
+
+typedef struct _LDM_ADAPTER
+{
+	struct _LDM_ADAPTER *next;
+	HIM  *him;
+	void *him_handle;
+	PVBUS vbus;
+	struct freelist freelist_dev;
+	int devid_start;
+	struct freelist freelist_plugged_dpc;
+	HPT_BOOL master;
+}
+LDM_ADAPTER, *PLDM_ADAPTER;
+
+typedef struct _IOCTL_ARG
+{
+	struct list_head link;
+	PVBUS vbus;
+	HPT_U32 dwIoControlCode;
+	HPT_U32 nInBufferSize;
+	HPT_U32 nOutBufferSize;
+	void *  lpInBuffer;
+	void *  lpOutBuffer;
+	HPT_U32 *lpBytesReturned;
+	void *  ioctl_cmnd;
+	void (* done)(struct _IOCTL_ARG *);
+	int     result; /* HPT_IOCTL_RESULT_ */
+	struct tq_item dpc;
+} IOCTL_ARG;
+
+#define HPT_IOCTL_RESULT_OK          0
+#define HPT_IOCTL_RESULT_FAILED     (-1)
+#define HPT_IOCTL_RESULT_INVALID    (-2)
+#define HPT_IOCTL_RESULT_RETRY      (-3)
+#define HPT_IOCTL_RESULT_WRONG_VBUS (-4)
+
+void ldm_ioctl(	PVBUS vbus,	IOCTL_ARG *IAPnt);
+void ldm_set_autorebuild(PVBUS vbus, int enable);
+HPT_U32 ldm_get_device_id(PVDEV vd); /* for ioctl */
+
+#ifndef __HPT_RAW_LBA
+#define __HPT_RAW_LBA HPT_RAW_LBA
+#endif
+
+#include <dev/hpt27xx/array.h>
+
+typedef struct hpt_raw_disk
+{
+#ifdef SUPPORT_ARRAY
+	PRAW_PARTITION raw_part_list;
+	__HPT_RAW_LBA max_available_capacity; 
+	__HPT_RAW_LBA total_available_capacity;
+#endif
+	__HPT_RAW_LBA real_capacity;
+	__HPT_RAW_LBA head_position;
+
+	HPT_U16 max_sectors_per_cmd;
+	HPT_U8  max_queue_depth;
+	HPT_U8  user_select_mode;
+
+	HPT_UINT  uninitialized : 1;
+	HPT_UINT  legacy_disk : 1;
+	HPT_UINT  is_spare : 1;
+	HPT_UINT  v3_format : 1;
+	HPT_UINT  need_sync : 1;
+	HPT_UINT  temp_spare : 1;
+	HPT_UINT  need_check_array : 1;
+	HPT_UINT  df_user_mode_set: 1;
+
+	HPT_UINT  df_read_ahead_set: 1;
+	HPT_UINT  enable_read_ahead : 1;
+	HPT_UINT  df_write_cache_set: 1;
+	HPT_UINT  enable_write_cache : 1;
+	HPT_UINT  df_tcq_set: 1;
+	HPT_UINT  enable_tcq : 1;
+	HPT_UINT  df_ncq_set: 1;
+	HPT_UINT  enable_ncq : 1;
+
+	HIM  *				him;
+	int 				index;
+	PLDM_ADAPTER		adapter;
+	void *				phy_dev;
+
+	char    model[40];
+
+	struct tq_item reset_dpc;
+	int reset_pending;
+
+	struct tq_item fail_dpc;
+	int fail_pending;
+}
+HPT_RAW_DISK, *PHPT_RAW_DISK;
+
+struct vdev_class
+{
+	struct vdev_class *next;
+
+	HPT_U8   __type;
+	HPT_U8   stripped;        /* RAID0,3,5,6 */
+	HPT_U8   redundancy;      /* RAID1-1, RAID3/5-1, RAID6-2 */
+	HPT_U8   must_init;       /* RAID3,5,6 */
+	HPT_U8   docache;
+
+	HPT_UINT vbus_ext_size;
+	HPT_UINT vbus_ext_offset; /* used by LDM */
+	HPT_UINT dev_ext_size;
+	HPT_UINT cmd_ext_size;
+
+	
+	void (*get_mem_info)(PVBUS vbus, void *osext, int phydev_count);
+	void (*queue_cmd)(PCOMMAND cmd);
+	void (*member_failed)(struct _VDEV * vd); 
+
+	
+	void (*initialize)(PVBUS vbus);
+	void (*release)(PVBUS vbus); 
+	int  (*add)(PVDEV vd); 
+	void (*remove)(PVDEV vd); 
+	void (*reset)(PVDEV vd); 
+	void (*sync_stamp)(PVDEV vd);
+	int  (*support_type)(int type);
+};
+
+
+#define VDEV_CLASS_CONSTRUCTOR(type, prefix) { \
+	0, \
+	type, \
+	prefix ## _stripped, \
+	prefix ## _redundancy, \
+	prefix ## _must_init, \
+	0, \
+	(HPT_UINT)(prefix ## _vbus_ext_size), \
+	0, \
+	(HPT_UINT)(prefix ## _dev_ext_size), \
+	(HPT_UINT)(prefix ## _cmd_ext_size), \
+	prefix ## _get_mem_info, \
+	prefix ## _queue_cmd, \
+	prefix ## _member_failed, \
+	prefix ## _initialize, \
+	prefix ## _release, \
+	prefix ## _add, \
+	prefix ## _remove, \
+	prefix ## _reset, \
+	prefix ## _sync_stamp, \
+	0 \
+}
+
+#define VD_RAW       1
+#define VD_PARTITION 4
+
+#define mIsArray(vdev_type) ((vdev_type)>VD_PARTITION)
+
+#define VD_RAID0     5
+#define VD_RAID1     6
+#define VD_JBOD      7
+#define VD_RAID5     8
+#define VD_RAID6     9
+#define VD_RAID3     10
+#define VD_RAID4     11
+#define VD_RAID1E    12
+
+#define MAX_VD_TYPE_ID  12
+
+struct vdev_class *ldm_find_vdev_class(HPT_U8 type);
+
+typedef struct _VDEV {
+	PVBUS vbus;
+	struct vdev_class *Class;
+	HPT_U8 type;
+	PVDEV parent;
+	void * ext;
+	HPT_U64 capacity;
+	int     target_id;
+	HPT_UINT cmds_per_request;
+
+	union {
+#ifdef SUPPORT_ARRAY
+		HPT_ARRAY array;
+		HPT_PARTITION partition;
+#endif
+		HPT_RAW_DISK raw;
+	} u;
+
+	HPT_U8 vf_online : 1;
+	HPT_U8 vf_bootmark : 1;
+	HPT_U8 vf_bootable : 1;
+	HPT_U8 vf_resetting: 1;
+	HPT_U8 vf_quiesced: 1;
+	HPT_U8 vf_clslock: 1;
+
+	HPT_U8 cache_policy; /* see CACHE_POLICY_* */
+
+	HPT_UINT cq_len;
+	HPT_UINT cmds_sent;
+
+	struct list_head link;
+	struct list_head cq_wait_send;
+	struct list_head cq_sent;
+
+	HPT_U32  last_active;
+	int cq_priority;
+	struct list_head cq_wait_lock;
+	struct lock_request *locks_granted;
+	struct lock_request *locks_wait;
+	HPT_U32 ioctl_id; 
+	void * cc_ext;
+}
+VDEV;
+
+#define CACHE_POLICY_NONE 0
+#define CACHE_POLICY_WRITE_THROUGH 1
+#define CACHE_POLICY_WRITE_BACK 2
+
+
+extern HIM *him_list;
+
+
+void ldm_register_him(PHIM him);
+
+
+void ldm_register_vdev_class(struct vdev_class *Class);
+
+
+HPT_BOOL ldm_register_adapter(PLDM_ADAPTER adapter);
+
+
+int init_config(void);
+
+HPT_UINT ldm_get_vbus_size(void);
+
+
+void ldm_create_vbus(PVBUS vbus, void *osext);
+
+
+void ldm_get_mem_info(PVBUS vbus, void *osext);
+
+
+void *ldm_get_vbus_ext(PVBUS vbus, struct vdev_class *Class);
+
+
+PVBUS ldm_get_next_vbus(PVBUS vbus, void **posext);
+
+#define ldm_for_each_vbus(vbus, vbus_ext) \
+	for (vbus = ldm_get_next_vbus(0, (void **)(void *)&vbus_ext); vbus; \
+		vbus = ldm_get_next_vbus(vbus, (void **)(void *)&vbus_ext))
+
+
+void ldm_initialize_vbus_async(PVBUS vbus, PLDM_ADAPTER master_adapter, void (*done)(void *osext));
+
+/* ldm_initialize_vbus is deprecated since it will hold the CPU too long. */
+#define ldm_initialize_vbus(vbus, adapter) ldm_initialize_vbus_async(vbus, adapter, 0)
+
+
+void ldm_release_vbus(PVBUS vbus);
+
+PVDEV ldm_create_vdev(PVBUS vbus, HPT_U8 type);
+void ldm_release_vdev(PVDEV vd);
+
+PVDEV ldm_find_target(PVBUS vbus, int id);
+PVDEV ldm_find_stamp(PVBUS vbus, HPT_U32 stamp, int seq);
+
+
+PCOMMAND ldm_alloc_cmds(PVBUS vbus, HPT_UINT cnt);
+void ldm_free_cmds(PCOMMAND cmd);
+
+HPT_UINT ldm_get_cmd_size(void);
+PCOMMAND ldm_alloc_cmds_from_list(PVBUS vbus, struct freelist *list, HPT_UINT cnt);
+void ldm_free_cmds_to_list(struct freelist *list, PCOMMAND cmd);
+
+
+PCOMMAND __ldm_alloc_cmd(struct freelist *list);
+
+#ifdef OS_SUPPORT_TASK
+#define CMD_SET_PRIORITY(cmd, pri) cmd->priority = (pri)
+#else 
+#define CMD_SET_PRIORITY(cmd, pri)
+#endif
+
+
+#define CMD_GROUP_GET(grp, cmd) \
+	do {\
+		grp->grplist->count++;\
+		cmd = __ldm_alloc_cmd(grp->grplist);\
+		cmd->vbus = grp->vbus;\
+		cmd->grplist = grp->grplist;\
+		CMD_SET_PRIORITY(cmd, grp->priority);\
+	} while(0)
+
+#define CMD_GROUP_PUT(grp, cmd) \
+	do {\
+		freelist_put(grp->grplist, cmd);\
+		grp->grplist->count--;\
+	} while (0)
+
+
+
+
+void ldm_queue_cmd(PCOMMAND cmd);
+void vdev_queue_cmd(PCOMMAND cmd);
+void ldm_finish_cmd(PCOMMAND cmd);
+
+
+int  ldm_acquire_lock(PVDEV vd, struct lock_request *req);
+void ldm_release_lock(PVDEV vd, struct lock_request *req);
+
+void ldm_queue_task(struct task_queue *tq, struct tq_item *t);
+void ldm_queue_vbus_dpc(PVBUS vbus, struct tq_item *t);
+
+HPT_BOOL ldm_intr(PVBUS vbus);
+void ldm_run(PVBUS vbus);
+int ldm_idle(PVBUS vbus);
+
+
+int ldm_reset_vbus(PVBUS vbus);
+
+
+void ldm_suspend(PVBUS vbus);
+void ldm_resume(PVBUS vbus);
+void ldm_shutdown(PVBUS vbus);/*shutdown all the controllers*/
+
+
+#define HIM_EVENT_DEVICE_REMOVED 1
+#define HIM_EVENT_DEVICE_PLUGGED 2
+#define HIM_EVENT_DEVICE_ERROR   3
+#define HIM_EVENT_RESET_REQUIRED 4
+#define HIM_EVENT_QUIESCE_DEVICE 5
+#define HIM_EVENT_UNQUIESCE_DEVICE 6
+#define HIM_EVENT_CONFIG_CHANGED 7
+
+void ldm_event_notify(HPT_U32 event, void *arg1, void *arg2);
+
+void log_sector_repair(PVDEV vd, int success, HPT_LBA lba, HPT_U16 nsectors);
+
+void ldm_register_device(PVDEV vd);
+void ldm_unregister_device(PVDEV vd);
+
+PVBUS him_handle_to_vbus(void * him_handle);
+void ldm_ide_fixstring (HPT_U8 *s, const int bytecount);
+#if defined(__cplusplus)
+}
+#endif
+#endif
diff --git a/sys/dev/hpt27xx/list.h b/sys/dev/hpt27xx/list.h
new file mode 100644
index 0000000..cae0767
--- /dev/null
+++ b/sys/dev/hpt27xx/list.h
@@ -0,0 +1,130 @@
+/*-
+ * Copyright (c) 2011 HighPoint Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <dev/hpt27xx/hpt27xx_config.h>
+
+#ifndef _HPT_LIST_H_
+#define _HPT_LIST_H_
+
+#ifndef _LINUX_LIST_H
+
+#ifndef HPT_INLINE
+#define HPT_INLINE __inline
+#endif
+
+struct list_head {
+	struct list_head *next, *prev;
+};
+
+#define INIT_LIST_HEAD(ptr) do { (ptr)->next = (ptr); (ptr)->prev = (ptr); } while (0)
+
+static HPT_INLINE void __list_add(struct list_head * _new, struct list_head * prev, struct list_head * next)
+{
+	next->prev = _new;
+	_new->next = next;
+	_new->prev = prev;
+	prev->next = _new;
+}
+
+static HPT_INLINE void list_add(struct list_head *_new, struct list_head *head)
+{
+	__list_add(_new, head, head->next);
+}
+
+static HPT_INLINE void list_add_tail(struct list_head *_new, struct list_head *head)
+{
+	__list_add(_new, head->prev, head);
+}
+
+static HPT_INLINE void __list_del(struct list_head * prev, struct list_head * next)
+{
+	next->prev = prev;
+	prev->next = next;
+}
+
+static HPT_INLINE void list_del(struct list_head *entry)
+{
+	__list_del(entry->prev, entry->next);
+}
+
+static HPT_INLINE void list_del_init(struct list_head *entry)
+{
+	__list_del(entry->prev, entry->next);
+	INIT_LIST_HEAD(entry); 
+}
+
+static HPT_INLINE int list_empty(struct list_head *head)
+{
+	HPT_ASSERT(!(head->next==head && head->prev!=head));
+	return head->next == head;
+}
+
+static HPT_INLINE void __list_splice(struct list_head *list,
+				 struct list_head *head)
+{
+	struct list_head *first = list->next;
+	struct list_head *last = list->prev;
+	struct list_head *at = head->next;
+
+	first->prev = head;
+	head->next = first;
+
+	last->next = at;
+	at->prev = last;
+}
+
+static HPT_INLINE void list_splice(struct list_head *list, struct list_head *head)
+{
+	if (!list_empty(list))
+		__list_splice(list, head);
+}
+
+static HPT_INLINE void list_splice_init(struct list_head *list, struct list_head *head)
+{
+	if (!list_empty(list)) {
+		__list_splice(list, head);
+		INIT_LIST_HEAD(list);
+	}
+}
+
+#define list_entry(ptr, type, member) \
+	((type *)((char *)(ptr)-(HPT_UPTR)(&((type *)0)->member)))
+
+#define list_for_each(pos, head) \
+	for (pos = (head)->next; pos != (head); pos = pos->next)
+
+#define list_for_each_safe(pos, n, head) \
+	for (pos = (head)->next, n = pos->next; pos != (head); \
+		pos = n, n = pos->next)
+
+#define get_first_item(attached, type, member) \
+	((type *)((char *)((attached)->next)-(HPT_UPTR)(&((type *)0)->member)))
+
+#endif
+
+#endif
diff --git a/sys/dev/hpt27xx/os_bsd.c b/sys/dev/hpt27xx/os_bsd.c
new file mode 100644
index 0000000..43f8116
--- /dev/null
+++ b/sys/dev/hpt27xx/os_bsd.c
@@ -0,0 +1,370 @@
+/*-
+ * Copyright (c) 2011 HighPoint Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <dev/hpt27xx/hpt27xx_config.h>
+
+#include <dev/hpt27xx/os_bsd.h>
+
+/* hardware access */
+HPT_U8   os_inb  (void *port) { return inb((unsigned)(HPT_UPTR)port); }
+HPT_U16  os_inw  (void *port) { return inw((unsigned)(HPT_UPTR)port); }
+HPT_U32  os_inl  (void *port) { return inl((unsigned)(HPT_UPTR)port); }
+
+void os_outb (void *port, HPT_U8 value) { outb((unsigned)(HPT_UPTR)port, (value)); }
+void os_outw (void *port, HPT_U16 value) { outw((unsigned)(HPT_UPTR)port, (value)); }
+void os_outl (void *port, HPT_U32 value) { outl((unsigned)(HPT_UPTR)port, (value)); }
+
+void os_insw (void *port, HPT_U16 *buffer, HPT_U32 count)
+{ insw((unsigned)(HPT_UPTR)port, (void *)buffer, count); }
+
+void os_outsw(void *port, HPT_U16 *buffer, HPT_U32 count)
+{ outsw((unsigned)(HPT_UPTR)port, (void *)buffer, count); }
+
+HPT_U32 __dummy_reg = 0;
+
+/* PCI configuration space */
+HPT_U8  os_pci_readb (void *osext, HPT_U8 offset)
+{
+    return  pci_read_config(((PHBA)osext)->pcidev, offset, 1);
+}
+
+HPT_U16 os_pci_readw (void *osext, HPT_U8 offset)
+{
+    return  pci_read_config(((PHBA)osext)->pcidev, offset, 2);
+}
+
+HPT_U32 os_pci_readl (void *osext, HPT_U8 offset)
+{
+    return  pci_read_config(((PHBA)osext)->pcidev, offset, 4);
+}
+
+void os_pci_writeb (void *osext, HPT_U8 offset, HPT_U8 value)
+{
+    pci_write_config(((PHBA)osext)->pcidev, offset, value, 1);
+}
+
+void os_pci_writew (void *osext, HPT_U8 offset, HPT_U16 value)
+{
+    pci_write_config(((PHBA)osext)->pcidev, offset, value, 2);
+}
+
+void os_pci_writel (void *osext, HPT_U8 offset, HPT_U32 value)
+{
+    pci_write_config(((PHBA)osext)->pcidev, offset, value, 4);
+}
+
+#if __FreeBSD_version < 500043
+/* PCI space access */
+HPT_U8 pcicfg_read_byte (HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg)
+{
+	HPT_U8 v;
+	pcicfgregs pciref;
+
+	pciref.bus  = bus;
+	pciref.slot = dev;
+	pciref.func = func;
+
+	v = pci_cfgread(&pciref, reg, 1);
+	return v;
+}
+HPT_U32 pcicfg_read_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg)
+{
+	HPT_U32 v;
+	pcicfgregs pciref;
+
+	pciref.bus  = bus;
+	pciref.slot = dev;
+	pciref.func = func;
+
+	v = pci_cfgread(&pciref, reg, 4);
+	return v;
+}
+void pcicfg_write_byte (HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U8 v)
+{
+	pcicfgregs pciref;
+
+	pciref.hose = -1;
+	pciref.bus  = bus;
+	pciref.slot = dev;
+	pciref.func = func;
+
+	pci_cfgwrite(&pciref, reg, v, 1);
+}
+void pcicfg_write_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U32 v)
+{
+	pcicfgregs pciref;
+
+	pciref.hose = -1;
+	pciref.bus  = bus;
+	pciref.slot = dev;
+	pciref.func = func;
+
+	pci_cfgwrite(&pciref, reg, v, 4);
+}/* PCI space access */
+#else 
+HPT_U8 pcicfg_read_byte (HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg)
+{
+	return (HPT_U8)pci_cfgregread(bus, dev, func, reg, 1);
+}
+HPT_U32 pcicfg_read_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg)
+{
+	return (HPT_U32)pci_cfgregread(bus, dev, func, reg, 4);;
+}
+void pcicfg_write_byte (HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U8 v)
+{
+	pci_cfgregwrite(bus, dev, func, reg, v, 1);
+}
+void pcicfg_write_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U32 v)
+{
+	pci_cfgregwrite(bus, dev, func, reg, v, 4);
+}/* PCI space access */
+#endif
+
+void *os_map_pci_bar(
+    void *osext, 
+    int index,   
+    HPT_U32 offset,
+    HPT_U32 length
+)
+{
+	PHBA hba = (PHBA)osext;
+	HPT_U32 base;
+
+	hba->pcibar[index].rid = 0x10 + index * 4;
+	base = pci_read_config(hba->pcidev, hba->pcibar[index].rid, 4);
+
+	if (base & 1) {
+		hba->pcibar[index].type = SYS_RES_IOPORT;
+		hba->pcibar[index].res = bus_alloc_resource(hba->pcidev,
+			hba->pcibar[index].type, &hba->pcibar[index].rid, 0, ~0, length, RF_ACTIVE);
+		hba->pcibar[index].base = (void *)(unsigned long)(base & ~0x1);
+	} else {
+		hba->pcibar[index].type = SYS_RES_MEMORY;
+		hba->pcibar[index].res = bus_alloc_resource(hba->pcidev,
+			hba->pcibar[index].type, &hba->pcibar[index].rid, 0, ~0, length, RF_ACTIVE);
+		hba->pcibar[index].base = (char *)rman_get_virtual(hba->pcibar[index].res) + offset;
+	}
+
+	return hba->pcibar[index].base;
+}
+
+void os_unmap_pci_bar(void *osext, void *base)
+{
+	PHBA hba = (PHBA)osext;
+	int index;
+	
+	for (index=0; index<6; index++) {
+		if (hba->pcibar[index].base==base) {
+			bus_release_resource(hba->pcidev, hba->pcibar[index].type,
+				hba->pcibar[index].rid, hba->pcibar[index].res);
+			hba->pcibar[index].base = 0;
+			return;
+		}
+	}
+}
+
+void freelist_reserve(struct freelist *list, void *osext, HPT_UINT size, HPT_UINT count)
+{
+    PVBUS_EXT vbus_ext = osext;
+
+    if (vbus_ext->ext_type!=EXT_TYPE_VBUS)
+        vbus_ext = ((PHBA)osext)->vbus_ext;
+
+    list->next = vbus_ext->freelist_head;
+    vbus_ext->freelist_head = list;
+    list->dma = 0;
+    list->size = size;
+    list->head = 0;
+#if DBG
+    list->reserved_count =
+#endif
+    list->count = count;
+}
+
+void *freelist_get(struct freelist *list)
+{
+    void * result;
+    if (list->count) {
+        HPT_ASSERT(list->head);
+        result = list->head;
+        list->head = *(void **)result;
+        list->count--;
+        return result;
+    }
+    return 0;
+}
+
+void freelist_put(struct freelist * list, void *p)
+{
+    HPT_ASSERT(list->dma==0);
+    list->count++;
+    *(void **)p = list->head;
+    list->head = p;
+}
+
+void freelist_reserve_dma(struct freelist *list, void *osext, HPT_UINT size, HPT_UINT alignment, HPT_UINT count)
+{
+    PVBUS_EXT vbus_ext = osext;
+
+    if (vbus_ext->ext_type!=EXT_TYPE_VBUS)
+        vbus_ext = ((PHBA)osext)->vbus_ext;
+
+    list->next = vbus_ext->freelist_dma_head;
+    vbus_ext->freelist_dma_head = list;
+    list->dma = 1;
+    list->alignment = alignment;
+    list->size = size;
+    list->head = 0;
+#if DBG
+    list->reserved_count =
+#endif
+    list->count = count;
+}
+
+void *freelist_get_dma(struct freelist *list, BUS_ADDRESS *busaddr)
+{
+    void *result;
+    HPT_ASSERT(list->dma);
+    result = freelist_get(list);
+    if (result)
+        *busaddr = *(BUS_ADDRESS *)((void **)result+1);
+    return result;
+}
+
+void freelist_put_dma(struct freelist *list, void *p, BUS_ADDRESS busaddr)
+{
+    HPT_ASSERT(list->dma);
+    list->count++;
+    *(void **)p = list->head;
+    *(BUS_ADDRESS *)((void **)p+1) = busaddr;
+    list->head = p;
+}
+
+HPT_U32 os_get_stamp(void)
+{
+    HPT_U32 stamp;
+    do { stamp = random(); } while (stamp==0);
+    return stamp;
+}
+
+void os_stallexec(HPT_U32 microseconds)
+{
+    DELAY(microseconds);
+}
+
+static void os_timer_for_ldm(void *arg)
+{
+	PVBUS_EXT vbus_ext = (PVBUS_EXT)arg;
+	ldm_on_timer((PVBUS)vbus_ext->vbus);
+}
+
+void  os_request_timer(void * osext, HPT_U32 interval)
+{
+	PVBUS_EXT vbus_ext = osext;
+
+	HPT_ASSERT(vbus_ext->ext_type==EXT_TYPE_VBUS);
+	
+	untimeout(os_timer_for_ldm, vbus_ext, vbus_ext->timer);
+	vbus_ext->timer = timeout(os_timer_for_ldm, vbus_ext, interval * hz / 1000000);
+}
+
+HPT_TIME os_query_time(void)
+{
+	return ticks * (1000000 / hz);
+}
+
+void os_schedule_task(void *osext, OSM_TASK *task)
+{
+	PVBUS_EXT vbus_ext = osext;
+	
+	HPT_ASSERT(task->next==0);
+	
+	if (vbus_ext->tasks==0)
+		vbus_ext->tasks = task;
+	else {
+		OSM_TASK *t = vbus_ext->tasks;
+		while (t->next) t = t->next;
+		t->next = task;
+	}
+
+	if (vbus_ext->worker.ta_context)
+		TASK_ENQUEUE(&vbus_ext->worker);
+}
+
+int os_revalidate_device(void *osext, int id)
+{
+
+    return 0;
+}
+
+int os_query_remove_device(void *osext, int id)
+{
+	PVBUS_EXT				vbus_ext = (PVBUS_EXT)osext;
+	struct cam_periph		*periph = NULL;
+    struct cam_path			*path;
+    int						status,retval = 0;
+
+    status = xpt_create_path(&path, NULL, vbus_ext->sim->path_id, id, 0);
+    if (status == CAM_REQ_CMP) {
+		if((periph = cam_periph_find(path, "da")) != NULL){
+			if(periph->refcount >= 1)	
+				retval = -1;
+		}
+		xpt_free_path(path);
+    }
+
+    return retval;
+}
+
+HPT_U8 os_get_vbus_seq(void *osext)
+{
+    return ((PVBUS_EXT)osext)->sim->path_id;
+}
+
+int  os_printk(char *fmt, ...)
+{
+    va_list args;
+    static char buf[512];
+
+    va_start(args, fmt);
+    vsnprintf(buf, sizeof(buf), fmt, args);
+    va_end(args);
+    return printf("%s: %s\n", driver_name, buf);
+}
+
+#if DBG
+void os_check_stack(const char *location, int size){}
+
+void __os_dbgbreak(const char *file, int line)
+{
+    printf("*** break at %s:%d ***", file, line);
+    while (1);
+}
+
+int hpt_dbg_level = 1;
+#endif
diff --git a/sys/dev/hpt27xx/os_bsd.h b/sys/dev/hpt27xx/os_bsd.h
new file mode 100644
index 0000000..3895f40
--- /dev/null
+++ b/sys/dev/hpt27xx/os_bsd.h
@@ -0,0 +1,263 @@
+/*-
+ * Copyright (c) 2011 HighPoint Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <dev/hpt27xx/hpt27xx_config.h>
+
+#ifndef _OS_BSD_H
+#define _OS_BSD_H
+
+#ifndef DBG
+#define  DBG	0
+#endif
+
+#include <sys/param.h>
+#include <sys/types.h>
+#include <sys/cons.h>
+#if (__FreeBSD_version >= 500000) 
+#include <sys/time.h>
+#include <sys/systm.h> 
+#else 
+#include <machine/clock.h>	/*to support DELAY function under 4.x BSD versions*/
+#endif
+
+#include <sys/stat.h>
+#include <sys/malloc.h>
+#include <sys/conf.h>
+#include <sys/libkern.h>
+#include <sys/kernel.h>
+
+#if (__FreeBSD_version >= 500000)
+#include <sys/kthread.h>
+#include <sys/mutex.h>
+#include <sys/module.h>
+#endif
+
+#include <sys/eventhandler.h>
+#include <sys/bus.h>
+#include <sys/taskqueue.h>
+#include <sys/ioccom.h>
+
+#include <machine/resource.h>
+#if __FreeBSD_version >= 500043
+#include <machine/pci_cfgreg.h>
+#endif
+#include <machine/bus.h>
+#include <machine/stdarg.h>
+#include <sys/rman.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+
+#if (__FreeBSD_version >= 500000)
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#else 
+#include <pci/pcivar.h>
+#include <pci/pcireg.h>
+#endif
+
+#if (__FreeBSD_version <= 500043)
+#include <sys/devicestat.h>
+#endif
+
+#include <cam/cam.h>
+#include <cam/cam_ccb.h>
+#include <cam/cam_sim.h>
+#include <cam/cam_xpt_sim.h>
+#include <cam/cam_debug.h>
+#include <cam/cam_xpt_periph.h>
+#include <cam/cam_periph.h>
+#include <cam/scsi/scsi_all.h>
+#include <cam/scsi/scsi_message.h>
+
+#if (__FreeBSD_version < 500043)
+#include <sys/bus_private.h>
+#endif
+
+
+typedef struct _INQUIRYDATA {
+	u_char DeviceType : 5;
+	u_char DeviceTypeQualifier : 3;
+	u_char DeviceTypeModifier : 7;
+	u_char RemovableMedia : 1;
+	u_char Versions;
+	u_char ResponseDataFormat;
+	u_char AdditionalLength;
+	u_char Reserved[2];
+	u_char SoftReset : 1;
+	u_char CommandQueue : 1;
+	u_char Reserved2 : 1;
+	u_char LinkedCommands : 1;
+	u_char Synchronous : 1;
+	u_char Wide16Bit : 1;
+	u_char Wide32Bit : 1;
+	u_char RelativeAddressing : 1;
+	u_char VendorId[8];
+	u_char ProductId[16];
+	u_char ProductRevisionLevel[4];
+	u_char VendorSpecific[20];
+	u_char Reserved3[40];
+} 
+__attribute__((packed))
+INQUIRYDATA, *PINQUIRYDATA;
+
+#endif
+
+/* private headers */
+
+#include <dev/hpt27xx/osm.h>
+#include <dev/hpt27xx/him.h>
+#include <dev/hpt27xx/ldm.h>
+
+/* driver parameters */
+extern char driver_name[];
+extern char driver_name_long[];
+extern char driver_ver[];
+extern int  osm_max_targets;
+
+/*
+ * adapter/vbus extensions:
+ * each physical controller has an adapter_ext, passed to him.create_adapter()
+ * each vbus has a vbus_ext passed to ldm_create_vbus().
+ */
+#define EXT_TYPE_HBA  1
+#define EXT_TYPE_VBUS 2
+
+typedef struct _hba {
+	int               ext_type;
+	LDM_ADAPTER       ldm_adapter;
+	device_t          pcidev;
+	PCI_ADDRESS       pciaddr;
+	struct _vbus_ext *vbus_ext;
+	struct _hba      *next;
+	
+	struct {
+		struct resource *res;
+		int type;
+		int rid;
+		void *base;
+	}
+	pcibar[6];
+
+	struct resource  *irq_res;
+	void             *irq_handle;
+}
+HBA, *PHBA;
+
+typedef struct _os_cmdext {
+	struct _vbus_ext  *vbus_ext;
+	struct _os_cmdext *next;
+	union ccb         *ccb;
+	bus_dmamap_t       dma_map;
+	SG                 psg[os_max_sg_descriptors];
+}
+OS_CMDEXT, *POS_CMDEXT;
+
+typedef struct _vbus_ext {
+	int               ext_type;
+	struct _vbus_ext *next;
+	PHBA              hba_list;
+	struct freelist  *freelist_head;
+	struct freelist  *freelist_dma_head;
+	
+	struct cam_sim   *sim;    /* sim for this vbus */
+	struct cam_path  *path;   /* peripheral, path, tgt, lun with this vbus */
+#if (__FreeBSD_version >= 500000)
+	struct mtx        lock; /* general purpose lock */
+#else 
+	int  			hpt_splx;
+#endif
+	bus_dma_tag_t     io_dmat; /* I/O buffer DMA tag */
+	
+	POS_CMDEXT        cmdext_list;
+
+	OSM_TASK         *tasks;
+	struct task       worker;
+	
+	struct callout_handle timer;
+
+	eventhandler_tag  shutdown_eh;
+	
+	/* the LDM vbus instance continues */
+	unsigned long vbus[0] __attribute__((aligned(sizeof(unsigned long))));
+}
+VBUS_EXT, *PVBUS_EXT;
+
+#if __FreeBSD_version >= 500000
+#define hpt_lock_vbus(vbus_ext)   mtx_lock(&(vbus_ext)->lock)
+#define hpt_unlock_vbus(vbus_ext) mtx_unlock(&(vbus_ext)->lock)
+#else 
+static __inline	void	hpt_lock_vbus(PVBUS_EXT	vbus_ext)
+{
+	vbus_ext->hpt_splx = splcam();
+}
+static __inline	void	hpt_unlock_vbus(PVBUS_EXT vbus_ext)
+{
+	splx(vbus_ext->hpt_splx);
+}
+#endif
+
+
+#define HPT_OSM_TIMEOUT (20*hz)  /* timeout value for OS commands */
+
+#define HPT_DO_IOCONTROL	_IOW('H', 0, HPT_IOCTL_PARAM)
+
+#define HPT_SCAN_BUS		_IO('H', 1)
+
+#if __FreeBSD_version >= 501000
+#define TASK_ENQUEUE(task)	taskqueue_enqueue(taskqueue_swi_giant,(task));
+#else 
+#define TASK_ENQUEUE(task)	taskqueue_enqueue(taskqueue_swi,(task));
+#endif
+
+#if __FreeBSD_version >= 500000
+static	__inline	int hpt_sleep(PVBUS_EXT vbus_ext, void *ident, int priority, const char *wmesg, int timo)
+{
+	return	msleep(ident, &vbus_ext->lock, priority, wmesg, timo);
+}
+#else 
+static	__inline	int hpt_sleep(PVBUS_EXT vbus_ext, void *ident, int priority, const char *wmesg, int timo)
+{
+	int retval = 0;
+	
+	asleep(ident, priority, wmesg, timo);
+	hpt_unlock_vbus(vbus_ext);
+	retval = await(priority, timo);
+	hpt_lock_vbus(vbus_ext);
+	
+	return retval;
+}
+#endif
+
+#if __FreeBSD_version < 501000
+#define	READ_16				0x88
+#define WRITE_16			0x8a
+#define SERVICE_ACTION_IN	0x9e
+#endif
+
+#define	HPT_DEV_MAJOR	200
diff --git a/sys/dev/hpt27xx/osm.h b/sys/dev/hpt27xx/osm.h
new file mode 100644
index 0000000..3d8a471
--- /dev/null
+++ b/sys/dev/hpt27xx/osm.h
@@ -0,0 +1,240 @@
+/*-
+ * Copyright (c) 2011 HighPoint Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <dev/hpt27xx/hpt27xx_config.h>
+
+#ifndef _HPT_OSM_H_
+#define _HPT_OSM_H_
+
+#define VERMAGIC_OSM 6
+
+
+#define MAX_MEMBERS 64
+
+#define os_max_queue_comm 32
+#define os_max_sg_descriptors 18
+
+
+extern int os_max_cache_size;
+
+
+#define DMAPOOL_PAGE_SIZE 0x1000 /* PAGE_SIZE (i386/x86_64) */
+#define os_max_cache_pages (os_max_cache_size/DMAPOOL_PAGE_SIZE)
+
+/* data types */
+typedef unsigned int HPT_UINT, HPT_U32;
+typedef unsigned long HPT_UPTR;
+typedef unsigned short HPT_U16;
+typedef unsigned char HPT_U8;
+typedef unsigned long HPT_TIME;
+typedef unsigned long long HPT_U64;
+
+#define CPU_TO_LE64(x) (x)
+#define CPU_TO_LE32(x) (x)
+#define CPU_TO_LE16(x) (x)
+#define LE32_TO_CPU(x) (x)
+#define LE16_TO_CPU(x) (x)
+#define LE64_TO_CPU(x) (x)
+
+static __inline HPT_U64 CPU_TO_BE64(HPT_U64 x)
+{
+	HPT_U8 *p = (HPT_U8 *)&x;
+	return ((HPT_U64)p[0] << 56) |
+		((HPT_U64)p[1] << 48) |
+		((HPT_U64)p[2] << 40) |
+		((HPT_U64)p[3] << 32) |
+		((HPT_U64)p[4] << 24) |
+		((HPT_U64)p[5] << 16) |
+		((HPT_U64)p[6] << 8) |
+		p[7];
+}
+
+static __inline HPT_U32 CPU_TO_BE32(HPT_U32 x)
+{
+	HPT_U8 *p = (HPT_U8 *)&x;
+	return ((HPT_U32)p[0] << 24) |
+		((HPT_U32)p[1] << 16) |
+		((HPT_U32)p[2] << 8) | p[3];
+}
+
+static __inline HPT_U16 CPU_TO_BE16(HPT_U16 x)
+{
+	return ((HPT_U8)x << 8) | (x>>8);
+}
+
+#define BE16_TO_CPU(x) CPU_TO_BE16(x)
+#define BE32_TO_CPU(x) CPU_TO_BE32(x)
+#define BE64_TO_CPU(x) CPU_TO_BE64(x)
+
+#define FAR
+#define EXTERN_C
+
+typedef void * HPT_PTR;
+
+typedef HPT_U64 HPT_LBA;
+typedef HPT_U64 HPT_RAW_LBA;
+#define MAX_LBA_VALUE 0xffffffffffffffffull
+#define MAX_RAW_LBA_VALUE MAX_LBA_VALUE
+#define RAW_LBA(x) (x)
+#define LO_LBA(x) ((HPT_U32)(x))
+#define HI_LBA(x) (sizeof(HPT_LBA)>4? (HPT_U32)((x)>>32) : 0)
+#define LBA_FORMAT_STR "0x%llX"
+
+typedef HPT_U64 BUS_ADDRESS;
+#define LO_BUSADDR(x) ((HPT_U32)(x))
+#define HI_BUSADDR(x) (sizeof(BUS_ADDRESS)>4? (x)>>32 : 0)
+
+typedef unsigned char HPT_BOOL;
+#define HPT_TRUE  1
+#define HPT_FALSE 0
+
+typedef struct _TIME_RECORD {
+   HPT_U32        seconds:6;      /* 0 - 59 */
+   HPT_U32        minutes:6;      /* 0 - 59 */
+   HPT_U32        month:4;        /* 1 - 12 */
+   HPT_U32        hours:6;        /* 0 - 59 */
+   HPT_U32        day:5;          /* 1 - 31 */
+   HPT_U32        year:5;         /* 0=2000, 31=2031 */
+} TIME_RECORD;
+
+/* hardware access */
+HPT_U8   os_inb  (void *port);
+HPT_U16  os_inw  (void *port);
+HPT_U32  os_inl  (void *port);
+void     os_outb (void *port, HPT_U8 value);
+void     os_outw (void *port, HPT_U16 value);
+void     os_outl (void *port, HPT_U32 value);
+void     os_insw (void *port, HPT_U16 *buffer, HPT_U32 count);
+void     os_outsw(void *port, HPT_U16 *buffer, HPT_U32 count);
+
+extern HPT_U32 __dummy_reg; /* to avoid the compiler warning */
+
+#define os_readb(addr) (*(HPT_U8 *)&__dummy_reg = *(volatile HPT_U8 *)(addr))
+#define os_readw(addr) (*(HPT_U16 *)&__dummy_reg = *(volatile HPT_U16 *)(addr))
+#define os_readl(addr) (*(HPT_U32 *)&__dummy_reg = *(volatile HPT_U32 *)(addr))
+
+#define os_writeb(addr, val) *(volatile HPT_U8 *)(addr) = (HPT_U8)(val)
+#define os_writew(addr, val) *(volatile HPT_U16 *)(addr) = (HPT_U16)(val)
+#define os_writel(addr, val) *(volatile HPT_U32 *)(addr) = (HPT_U32)(val)
+
+/* PCI configuration space for specified device*/
+HPT_U8   os_pci_readb (void *osext, HPT_U8 offset);
+HPT_U16  os_pci_readw (void *osext, HPT_U8 offset);
+HPT_U32  os_pci_readl (void *osext, HPT_U8 offset);
+void     os_pci_writeb(void *osext, HPT_U8 offset, HPT_U8 value);
+void     os_pci_writew(void *osext, HPT_U8 offset, HPT_U16 value);
+void     os_pci_writel(void *osext, HPT_U8 offset, HPT_U32 value);
+
+/* obsolute interface */
+#define MAX_PCI_BUS_NUMBER 0xff
+#define MAX_PCI_DEVICE_NUMBER 32
+#define MAX_PCI_FUNC_NUMBER 1
+HPT_U8 pcicfg_read_byte (HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg);
+HPT_U32 pcicfg_read_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg);
+void pcicfg_write_byte (HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U8 v);
+void pcicfg_write_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U32 v);
+
+
+void *os_map_pci_bar(
+	void *osext, 
+	int index,   
+	HPT_U32 offset,
+	HPT_U32 length
+);
+
+
+void os_unmap_pci_bar(void *osext, void *base);
+
+#define os_kmap_sgptr(psg) (psg->addr._logical)
+#define os_kunmap_sgptr(ptr)
+#define os_set_sgptr(psg, ptr) (psg)->addr._logical = (ptr)
+
+/* timer */
+void *os_add_timer(void *osext, HPT_U32 microseconds, void (*proc)(void *), void *arg);
+void  os_del_timer(void *handle);
+void  os_request_timer(void * osext, HPT_U32 interval);
+HPT_TIME os_query_time(void);
+
+/* task */
+#define OS_SUPPORT_TASK
+
+typedef struct _OSM_TASK {
+	struct _OSM_TASK *next;
+	void (*func)(void *vbus, void *data);
+	void *data;
+}
+OSM_TASK;
+
+void os_schedule_task(void *osext, OSM_TASK *task);
+
+/* misc */
+HPT_U32 os_get_stamp(void);
+void os_stallexec(HPT_U32 microseconds);
+
+#ifndef _SYS_LIBKERN_H_
+#define memcpy(dst, src, size) __builtin_memcpy((dst), (src), (size))
+#define memcmp(dst, src, size) __builtin_memcmp((dst), (src), (size))
+#define strcpy(dst, src) __builtin_strcpy((dst), (src))
+static __inline void * memset(void *dst, int c, unsigned long size)
+{
+	char *p;
+	for (p=(char*)dst; size; size--,p++) *p = c;
+	return dst;
+}
+#endif
+
+#define farMemoryCopy(a,b,c) memcpy((char *)(a), (char *)(b), (HPT_U32)c)
+
+
+#define os_register_device(osext, target_id)
+#define os_unregister_device(osext, target_id)
+int os_query_remove_device(void *osext, int target_id);
+int os_revalidate_device(void *osext, int target_id);
+
+HPT_U8 os_get_vbus_seq(void *osext);
+
+/* debug support */
+int  os_printk(char *fmt, ...);
+
+#if DBG
+extern int hpt_dbg_level;
+#define KdPrint(x)  do { if (hpt_dbg_level) os_printk x; } while (0)
+void __os_dbgbreak(const char *file, int line);
+#define os_dbgbreak() __os_dbgbreak(__FILE__, __LINE__)
+#define HPT_ASSERT(x) do { if (!(x)) os_dbgbreak(); } while (0)
+void os_check_stack(const char *location, int size);
+#define HPT_CHECK_STACK(size) os_check_stack(__FUNCTION__, (size))
+#else 
+#define KdPrint(x)
+#define HPT_ASSERT(x)
+#define HPT_CHECK_STACK(size)
+#endif
+
+#define OsPrint(x) do { os_printk x; } while (0)
+
+#endif
diff --git a/sys/dev/hpt27xx/osm_bsd.c b/sys/dev/hpt27xx/osm_bsd.c
new file mode 100644
index 0000000..ac7e9d8
--- /dev/null
+++ b/sys/dev/hpt27xx/osm_bsd.c
@@ -0,0 +1,1421 @@
+/*-
+ * Copyright (c) 2011 HighPoint Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <dev/hpt27xx/hpt27xx_config.h>
+
+#include <dev/hpt27xx/os_bsd.h>
+#include <dev/hpt27xx/hptintf.h>
+
+static int hpt_probe(device_t dev)
+{
+	PCI_ID pci_id;
+	HIM *him;
+	int i;
+	PHBA hba;
+
+	for (him = him_list; him; him = him->next) {
+		for (i=0; him->get_supported_device_id(i, &pci_id); i++) {
+			if (him->get_controller_count)
+				him->get_controller_count(&pci_id,0,0);
+			if ((pci_get_vendor(dev) == pci_id.vid) &&
+				(pci_get_device(dev) == pci_id.did)){
+				KdPrint(("hpt_probe: adapter at PCI %d:%d:%d, IRQ %d",
+					pci_get_bus(dev), pci_get_slot(dev), pci_get_function(dev), pci_get_irq(dev)
+				));
+				device_set_desc(dev, him->name);
+				hba = (PHBA)device_get_softc(dev);
+				memset(hba, 0, sizeof(HBA));
+				hba->ext_type = EXT_TYPE_HBA;
+				hba->ldm_adapter.him = him;
+				return 0;
+			}
+		}
+	}
+
+	return (ENXIO);
+}
+
+static int hpt_attach(device_t dev)
+{
+	PHBA hba = (PHBA)device_get_softc(dev);
+	HIM *him = hba->ldm_adapter.him;
+	PCI_ID pci_id;
+	HPT_UINT size;
+	PVBUS vbus;
+	PVBUS_EXT vbus_ext;
+	
+	KdPrint(("hpt_attach(%d/%d/%d)", pci_get_bus(dev), pci_get_slot(dev), pci_get_function(dev)));
+	
+#if __FreeBSD_version >=440000
+	pci_enable_busmaster(dev);
+#endif
+
+	pci_id.vid = pci_get_vendor(dev);
+	pci_id.did = pci_get_device(dev);
+	pci_id.rev = pci_get_revid(dev);
+	pci_id.subsys = (HPT_U32)(pci_get_subdevice(dev)) << 16 | pci_get_subvendor(dev);
+
+	size = him->get_adapter_size(&pci_id);
+	hba->ldm_adapter.him_handle = malloc(size, M_DEVBUF, M_WAITOK);
+	if (!hba->ldm_adapter.him_handle)
+		return ENXIO;
+
+	hba->pcidev = dev;
+	hba->pciaddr.tree = 0;
+	hba->pciaddr.bus = pci_get_bus(dev);
+	hba->pciaddr.device = pci_get_slot(dev);
+	hba->pciaddr.function = pci_get_function(dev);
+
+	if (!him->create_adapter(&pci_id, hba->pciaddr, hba->ldm_adapter.him_handle, hba)) {
+		free(hba->ldm_adapter.him_handle, M_DEVBUF);
+		return -1;
+	}
+
+	os_printk("adapter at PCI %d:%d:%d, IRQ %d",
+		hba->pciaddr.bus, hba->pciaddr.device, hba->pciaddr.function, pci_get_irq(dev));
+
+	if (!ldm_register_adapter(&hba->ldm_adapter)) {
+		size = ldm_get_vbus_size();
+		vbus_ext = malloc(sizeof(VBUS_EXT) + size, M_DEVBUF, M_WAITOK);
+		if (!vbus_ext) {
+			free(hba->ldm_adapter.him_handle, M_DEVBUF);
+			return -1;
+		}
+		memset(vbus_ext, 0, sizeof(VBUS_EXT));
+		vbus_ext->ext_type = EXT_TYPE_VBUS;
+		ldm_create_vbus((PVBUS)vbus_ext->vbus, vbus_ext);
+		ldm_register_adapter(&hba->ldm_adapter);
+	}
+
+	ldm_for_each_vbus(vbus, vbus_ext) {
+		if (hba->ldm_adapter.vbus==vbus) {
+			hba->vbus_ext = vbus_ext;
+			hba->next = vbus_ext->hba_list;
+			vbus_ext->hba_list = hba;
+			break;
+		}
+	}	
+	return 0;
+}
+
+/*
+ * Maybe we'd better to use the bus_dmamem_alloc to alloc DMA memory,
+ * but there are some problems currently (alignment, etc).
+ */
+static __inline void *__get_free_pages(int order)
+{
+	/* don't use low memory - other devices may get starved */
+	return contigmalloc(PAGE_SIZE<<order, 
+			M_DEVBUF, M_WAITOK, BUS_SPACE_MAXADDR_24BIT, BUS_SPACE_MAXADDR, PAGE_SIZE, 0);
+}
+
+static __inline void free_pages(void *p, int order)
+{
+	contigfree(p, PAGE_SIZE<<order, M_DEVBUF);
+}
+
+static int hpt_alloc_mem(PVBUS_EXT vbus_ext)
+{
+	PHBA hba;
+	struct freelist *f;
+	HPT_UINT i;
+	void **p;
+
+	for (hba = vbus_ext->hba_list; hba; hba = hba->next)
+		hba->ldm_adapter.him->get_meminfo(hba->ldm_adapter.him_handle);
+
+	ldm_get_mem_info((PVBUS)vbus_ext->vbus, 0);
+
+	for (f=vbus_ext->freelist_head; f; f=f->next) {
+		KdPrint(("%s: %d*%d=%d bytes",
+			f->tag, f->count, f->size, f->count*f->size));
+		for (i=0; i<f->count; i++) {
+			p = (void **)malloc(f->size, M_DEVBUF, M_WAITOK);
+			if (!p)	return (ENXIO);
+			*p = f->head;
+			f->head = p;
+		}
+	}
+
+	for (f=vbus_ext->freelist_dma_head; f; f=f->next) {
+		int order, size, j;
+
+		HPT_ASSERT((f->size & (f->alignment-1))==0);
+
+		for (order=0, size=PAGE_SIZE; size<f->size; order++, size<<=1) ;
+
+		KdPrint(("%s: %d*%d=%d bytes, order %d",
+			f->tag, f->count, f->size, f->count*f->size, order));
+		HPT_ASSERT(f->alignment<=PAGE_SIZE);
+
+		for (i=0; i<f->count;) {
+			p = (void **)__get_free_pages(order);
+			if (!p) return -1;
+			for (j = size/f->size; j && i<f->count; i++,j--) {
+				*p = f->head;
+				*(BUS_ADDRESS *)(p+1) = (BUS_ADDRESS)vtophys(p);
+				f->head = p;
+				p = (void **)((unsigned long)p + f->size);
+			}
+		}
+	}
+	
+	HPT_ASSERT(PAGE_SIZE==DMAPOOL_PAGE_SIZE);
+
+	for (i=0; i<os_max_cache_pages; i++) {
+		p = (void **)__get_free_pages(0);
+		if (!p) return -1;
+		HPT_ASSERT(((HPT_UPTR)p & (DMAPOOL_PAGE_SIZE-1))==0);
+		dmapool_put_page((PVBUS)vbus_ext->vbus, p, (BUS_ADDRESS)vtophys(p));
+	}
+
+	return 0;
+}
+
+static void hpt_free_mem(PVBUS_EXT vbus_ext)
+{
+	struct freelist *f;
+	void *p;
+	int i;
+	BUS_ADDRESS bus;
+
+	for (f=vbus_ext->freelist_head; f; f=f->next) {
+#if DBG
+		if (f->count!=f->reserved_count) {
+			KdPrint(("memory leak for freelist %s (%d/%d)", f->tag, f->count, f->reserved_count));
+		}
+#endif
+		while ((p=freelist_get(f)))
+			free(p, M_DEVBUF);
+	}
+
+	for (i=0; i<os_max_cache_pages; i++) {
+		p = dmapool_get_page((PVBUS)vbus_ext->vbus, &bus);
+		HPT_ASSERT(p);
+		free_pages(p, 0);
+	}
+
+	for (f=vbus_ext->freelist_dma_head; f; f=f->next) {
+		int order, size;
+#if DBG
+		if (f->count!=f->reserved_count) {
+			KdPrint(("memory leak for dma freelist %s (%d/%d)", f->tag, f->count, f->reserved_count));
+		}
+#endif
+		for (order=0, size=PAGE_SIZE; size<f->size; order++, size<<=1) ;
+
+		while ((p=freelist_get_dma(f, &bus))) {
+			if (order)
+				free_pages(p, order);
+			else {
+			/* can't free immediately since other blocks in this page may still be in the list */
+				if (((HPT_UPTR)p & (PAGE_SIZE-1))==0)
+					dmapool_put_page((PVBUS)vbus_ext->vbus, p, bus);
+			}
+		}
+	}
+	
+	while ((p = dmapool_get_page((PVBUS)vbus_ext->vbus, &bus)))
+		free_pages(p, 0);
+}
+
+static int hpt_init_vbus(PVBUS_EXT vbus_ext)
+{
+	PHBA hba;
+
+	for (hba = vbus_ext->hba_list; hba; hba = hba->next)
+		if (!hba->ldm_adapter.him->initialize(hba->ldm_adapter.him_handle)) {
+			KdPrint(("fail to initialize %p", hba));
+			return -1;
+		}
+
+	ldm_initialize_vbus((PVBUS)vbus_ext->vbus, &vbus_ext->hba_list->ldm_adapter);
+	return 0;
+}
+
+static void hpt_flush_done(PCOMMAND pCmd)
+{
+	PVDEV vd = pCmd->target;
+
+	if (mIsArray(vd->type) && vd->u.array.transform && vd!=vd->u.array.transform->target) {
+		vd = vd->u.array.transform->target;
+		HPT_ASSERT(vd);
+		pCmd->target = vd;
+		pCmd->Result = RETURN_PENDING;
+		vdev_queue_cmd(pCmd);
+		return;
+	}
+
+	*(int *)pCmd->priv = 1;
+	wakeup(pCmd);
+}
+
+/*
+ * flush a vdev (without retry).
+ */
+static int hpt_flush_vdev(PVBUS_EXT vbus_ext, PVDEV vd)
+{
+	PCOMMAND pCmd;
+	int result = 0, done;
+	HPT_UINT count;
+
+	KdPrint(("flusing dev %p", vd));
+
+	hpt_lock_vbus(vbus_ext);
+
+	if (mIsArray(vd->type) && vd->u.array.transform)
+		count = MAX(vd->u.array.transform->source->cmds_per_request,
+					vd->u.array.transform->target->cmds_per_request);
+	else
+		count = vd->cmds_per_request;
+
+	pCmd = ldm_alloc_cmds(vd->vbus, count);
+
+	if (!pCmd) {
+		hpt_unlock_vbus(vbus_ext);
+		return -1;
+	}
+
+	pCmd->type = CMD_TYPE_FLUSH;
+	pCmd->flags.hard_flush = 1;
+	pCmd->target = vd;
+	pCmd->done = hpt_flush_done;
+	done = 0;
+	pCmd->priv = &done;
+
+	ldm_queue_cmd(pCmd);
+	
+	if (!done) {
+		while (hpt_sleep(vbus_ext, pCmd, PPAUSE, "hptfls", HPT_OSM_TIMEOUT)) {
+			ldm_reset_vbus(vd->vbus);
+		}
+	}
+
+	KdPrint(("flush result %d", pCmd->Result));
+
+	if (pCmd->Result!=RETURN_SUCCESS)
+		result = -1;
+
+	ldm_free_cmds(pCmd);
+
+	hpt_unlock_vbus(vbus_ext);
+
+	return result;
+}
+
+static void hpt_stop_tasks(PVBUS_EXT vbus_ext);
+static void hpt_shutdown_vbus(PVBUS_EXT vbus_ext, int howto)
+{
+	PVBUS     vbus = (PVBUS)vbus_ext->vbus;
+	PHBA hba;
+	int i;
+	
+	KdPrint(("hpt_shutdown_vbus"));
+
+	/* stop all ctl tasks and disable the worker taskqueue */
+	hpt_stop_tasks(vbus_ext);
+	vbus_ext->worker.ta_context = 0;
+
+	/* flush devices */
+	for (i=0; i<osm_max_targets; i++) {
+		PVDEV vd = ldm_find_target(vbus, i);
+		if (vd) {
+			/* retry once */
+			if (hpt_flush_vdev(vbus_ext, vd))
+				hpt_flush_vdev(vbus_ext, vd);
+		}
+	}
+
+	hpt_lock_vbus(vbus_ext);
+	ldm_shutdown(vbus);
+	hpt_unlock_vbus(vbus_ext);
+
+	ldm_release_vbus(vbus);
+
+	for (hba=vbus_ext->hba_list; hba; hba=hba->next)
+		bus_teardown_intr(hba->pcidev, hba->irq_res, hba->irq_handle);
+
+	hpt_free_mem(vbus_ext);
+
+	while ((hba=vbus_ext->hba_list)) {
+		vbus_ext->hba_list = hba->next;
+		free(hba->ldm_adapter.him_handle, M_DEVBUF);
+	}
+
+	free(vbus_ext, M_DEVBUF);
+	KdPrint(("hpt_shutdown_vbus done"));
+}
+
+static void __hpt_do_tasks(PVBUS_EXT vbus_ext)
+{
+	OSM_TASK *tasks;
+
+	tasks = vbus_ext->tasks;
+	vbus_ext->tasks = 0;
+
+	while (tasks) {
+		OSM_TASK *t = tasks;
+		tasks = t->next;
+		t->next = 0;
+		t->func(vbus_ext->vbus, t->data);
+	}
+}
+
+static void hpt_do_tasks(PVBUS_EXT vbus_ext, int pending)
+{
+	if(vbus_ext){
+		hpt_lock_vbus(vbus_ext);
+		__hpt_do_tasks(vbus_ext);
+		hpt_unlock_vbus(vbus_ext);
+	}
+}
+
+static void hpt_action(struct cam_sim *sim, union ccb *ccb);
+static void hpt_poll(struct cam_sim *sim);
+static void hpt_async(void * callback_arg, u_int32_t code, struct cam_path * path, void * arg);
+static void hpt_pci_intr(void *arg);
+
+static __inline POS_CMDEXT cmdext_get(PVBUS_EXT vbus_ext)
+{
+	POS_CMDEXT p = vbus_ext->cmdext_list;
+	if (p)
+		vbus_ext->cmdext_list = p->next;
+	return p;
+}
+
+static __inline void cmdext_put(POS_CMDEXT p)
+{
+	p->next = p->vbus_ext->cmdext_list;
+	p->vbus_ext->cmdext_list = p;
+}
+
+static void hpt_timeout(void *arg)
+{
+	PCOMMAND pCmd = (PCOMMAND)arg;
+	POS_CMDEXT ext = (POS_CMDEXT)pCmd->priv;
+	
+	KdPrint(("pCmd %p timeout", pCmd));
+	
+	ldm_reset_vbus((PVBUS)ext->vbus_ext->vbus);
+}
+
+static void os_cmddone(PCOMMAND pCmd)
+{
+	POS_CMDEXT ext = (POS_CMDEXT)pCmd->priv;
+	union ccb *ccb = ext->ccb;
+
+	KdPrint(("os_cmddone(%p, %d)", pCmd, pCmd->Result));
+	
+	untimeout(hpt_timeout, pCmd, ccb->ccb_h.timeout_ch);
+
+	switch(pCmd->Result) {
+	case RETURN_SUCCESS:
+		ccb->ccb_h.status = CAM_REQ_CMP;
+		break;
+	case RETURN_BAD_DEVICE:
+		ccb->ccb_h.status = CAM_DEV_NOT_THERE;
+		break;
+	case RETURN_DEVICE_BUSY:
+		ccb->ccb_h.status = CAM_BUSY;
+		break;
+	case RETURN_INVALID_REQUEST:
+		ccb->ccb_h.status = CAM_REQ_INVALID;
+		break;
+	case RETURN_SELECTION_TIMEOUT:
+		ccb->ccb_h.status = CAM_SEL_TIMEOUT;
+		break;
+	case RETURN_RETRY:
+		ccb->ccb_h.status = CAM_BUSY;
+		break;
+	default:
+		ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
+		break;
+	}
+
+	if (pCmd->flags.data_in) {
+		bus_dmamap_sync(ext->vbus_ext->io_dmat, ext->dma_map, BUS_DMASYNC_POSTREAD);
+	}
+	else if (pCmd->flags.data_out) {
+		bus_dmamap_sync(ext->vbus_ext->io_dmat, ext->dma_map, BUS_DMASYNC_POSTWRITE);
+	}
+	
+	bus_dmamap_unload(ext->vbus_ext->io_dmat, ext->dma_map);
+
+	cmdext_put(ext);
+	ldm_free_cmds(pCmd);
+	xpt_done(ccb);
+}
+
+static int os_buildsgl(PCOMMAND pCmd, PSG pSg, int logical)
+{
+	POS_CMDEXT ext = (POS_CMDEXT)pCmd->priv;
+	union ccb *ccb = ext->ccb;
+	bus_dma_segment_t *sgList = (bus_dma_segment_t *)ccb->csio.data_ptr;
+	int idx;
+
+	if(logical)	{
+		if (ccb->ccb_h.flags & CAM_DATA_PHYS)
+			panic("physical address unsupported");
+
+		if (ccb->ccb_h.flags & CAM_SCATTER_VALID) {
+			if (ccb->ccb_h.flags & CAM_SG_LIST_PHYS)
+				panic("physical address unsupported");
+	
+			for (idx = 0; idx < ccb->csio.sglist_cnt; idx++) {
+				os_set_sgptr(&pSg[idx], (HPT_U8 *)(HPT_UPTR)sgList[idx].ds_addr);
+				pSg[idx].size = sgList[idx].ds_len;
+				pSg[idx].eot = (idx==ccb->csio.sglist_cnt-1)? 1 : 0;
+			}
+		}
+		else {
+			os_set_sgptr(pSg, (HPT_U8 *)ccb->csio.data_ptr);
+			pSg->size = ccb->csio.dxfer_len;
+			pSg->eot = 1;
+		}
+		return TRUE;
+	}
+
+	/* since we have provided physical sg, nobody will ask us to build physical sg */
+	HPT_ASSERT(0);
+	return FALSE;
+}
+
+static void hpt_io_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
+{
+	PCOMMAND pCmd = (PCOMMAND)arg;
+	POS_CMDEXT ext = (POS_CMDEXT)pCmd->priv;
+	PSG psg = pCmd->psg;
+	int idx;
+	
+	HPT_ASSERT(pCmd->flags.physical_sg);
+	
+	if (error || nsegs == 0)
+		panic("busdma error");
+		
+	HPT_ASSERT(nsegs<=os_max_sg_descriptors);
+
+	for (idx = 0; idx < nsegs; idx++, psg++) {
+		psg->addr.bus = segs[idx].ds_addr;
+		psg->size = segs[idx].ds_len;
+		psg->eot = 0;
+	}
+	psg[-1].eot = 1;
+	
+	if (pCmd->flags.data_in) {
+		bus_dmamap_sync(ext->vbus_ext->io_dmat, ext->dma_map, BUS_DMASYNC_PREREAD);
+	}
+	else if (pCmd->flags.data_out) {
+		bus_dmamap_sync(ext->vbus_ext->io_dmat, ext->dma_map, BUS_DMASYNC_PREWRITE);
+	}
+
+	ext->ccb->ccb_h.timeout_ch = timeout(hpt_timeout, pCmd, HPT_OSM_TIMEOUT);
+	ldm_queue_cmd(pCmd);
+}
+
+static void hpt_scsi_io(PVBUS_EXT vbus_ext, union ccb *ccb)
+{
+	PVBUS vbus = (PVBUS)vbus_ext->vbus;
+	PVDEV vd;
+	PCOMMAND pCmd;
+	POS_CMDEXT ext;
+	HPT_U8 *cdb;
+
+	if (ccb->ccb_h.flags & CAM_CDB_POINTER)
+		cdb = ccb->csio.cdb_io.cdb_ptr;
+	else
+		cdb = ccb->csio.cdb_io.cdb_bytes;
+	
+	KdPrint(("hpt_scsi_io: ccb %x id %d lun %d cdb %x-%x-%x",
+		ccb,
+		ccb->ccb_h.target_id, ccb->ccb_h.target_lun,
+		*(HPT_U32 *)&cdb[0], *(HPT_U32 *)&cdb[4], *(HPT_U32 *)&cdb[8]
+	));
+
+	/* ccb->ccb_h.path_id is not our bus id - don't check it */
+	if (ccb->ccb_h.target_lun != 0 ||
+		ccb->ccb_h.target_id >= osm_max_targets ||
+		(ccb->ccb_h.flags & CAM_CDB_PHYS))
+	{
+		ccb->ccb_h.status = CAM_TID_INVALID;
+		xpt_done(ccb);
+		return;
+	}
+
+	vd = ldm_find_target(vbus, ccb->ccb_h.target_id);
+
+	if (!vd) {
+		ccb->ccb_h.status = CAM_TID_INVALID;
+		xpt_done(ccb);
+		return;
+	}
+   
+	switch (cdb[0]) {
+	case TEST_UNIT_READY:
+	case START_STOP_UNIT:
+	case SYNCHRONIZE_CACHE:
+		ccb->ccb_h.status = CAM_REQ_CMP;
+		break;
+
+	case INQUIRY:
+		{
+			PINQUIRYDATA inquiryData;
+			memset(ccb->csio.data_ptr, 0, ccb->csio.dxfer_len);
+			inquiryData = (PINQUIRYDATA)ccb->csio.data_ptr;
+		
+			inquiryData->AdditionalLength = 31;
+			inquiryData->CommandQueue = 1;
+			memcpy(&inquiryData->VendorId, "HPT     ", 8);
+			memcpy(&inquiryData->ProductId, "DISK 0_0        ", 16);
+	
+			if (vd->target_id / 10) {
+				inquiryData->ProductId[7] = (vd->target_id % 100) / 10 + '0';
+				inquiryData->ProductId[8] = (vd->target_id % 100) % 10 + '0';
+			}
+			else
+				inquiryData->ProductId[7] = (vd->target_id % 100) % 10 + '0';
+	
+			memcpy(&inquiryData->ProductRevisionLevel, "4.00", 4);
+	
+			ccb->ccb_h.status = CAM_REQ_CMP;
+		}
+		break;
+
+	case READ_CAPACITY:
+	{
+		HPT_U8 *rbuf = ccb->csio.data_ptr;
+		HPT_U32 cap;
+		
+		if (vd->capacity>0xfffffffful)
+			cap = 0xfffffffful;
+		else
+			cap = vd->capacity - 1;
+	
+		rbuf[0] = (HPT_U8)(cap>>24);
+		rbuf[1] = (HPT_U8)(cap>>16);
+		rbuf[2] = (HPT_U8)(cap>>8);
+		rbuf[3] = (HPT_U8)cap;
+		rbuf[4] = 0;
+		rbuf[5] = 0;
+		rbuf[6] = 2;
+		rbuf[7] = 0;
+
+		ccb->ccb_h.status = CAM_REQ_CMP;
+		break;
+	}
+	
+	case SERVICE_ACTION_IN: 
+	{
+		HPT_U8 *rbuf = ccb->csio.data_ptr;
+		HPT_U64	cap = vd->capacity - 1;
+		
+		rbuf[0] = (HPT_U8)(cap>>56);
+		rbuf[1] = (HPT_U8)(cap>>48);
+		rbuf[2] = (HPT_U8)(cap>>40);
+		rbuf[3] = (HPT_U8)(cap>>32);
+		rbuf[4] = (HPT_U8)(cap>>24);
+		rbuf[5] = (HPT_U8)(cap>>16);
+		rbuf[6] = (HPT_U8)(cap>>8);
+		rbuf[7] = (HPT_U8)cap;
+		rbuf[8] = 0;
+		rbuf[9] = 0;
+		rbuf[10] = 2;
+		rbuf[11] = 0;
+		
+		ccb->ccb_h.status = CAM_REQ_CMP;
+		break;	
+	}
+	
+	case READ_6:
+	case READ_10:
+	case READ_16:
+	case WRITE_6:
+	case WRITE_10:
+	case WRITE_16:
+	case 0x13:
+	case 0x2f:
+	case 0x8f: /* VERIFY_16 */
+	{
+		pCmd = ldm_alloc_cmds(vbus, vd->cmds_per_request);
+		if(!pCmd){
+			KdPrint(("Failed to allocate command!"));
+			ccb->ccb_h.status = CAM_BUSY;
+			break;
+		}
+
+		switch (cdb[0])	{
+		case READ_6:
+		case WRITE_6:
+		case 0x13:
+			pCmd->uCmd.Ide.Lba =  ((HPT_U32)cdb[1] << 16) | ((HPT_U32)cdb[2] << 8) | (HPT_U32)cdb[3];
+			pCmd->uCmd.Ide.nSectors = (HPT_U16) cdb[4];
+			break;
+		case READ_16:
+		case WRITE_16:
+		case 0x8f: /* VERIFY_16 */
+		{
+			HPT_U64 block =
+				((HPT_U64)cdb[2]<<56) |
+				((HPT_U64)cdb[3]<<48) |
+				((HPT_U64)cdb[4]<<40) |
+				((HPT_U64)cdb[5]<<32) |
+				((HPT_U64)cdb[6]<<24) |
+				((HPT_U64)cdb[7]<<16) |
+				((HPT_U64)cdb[8]<<8) |
+				((HPT_U64)cdb[9]);
+			pCmd->uCmd.Ide.Lba = block;
+			pCmd->uCmd.Ide.nSectors = (HPT_U16)cdb[13] | ((HPT_U16)cdb[12]<<8);
+			break;
+		}
+		
+		default:
+			pCmd->uCmd.Ide.Lba = (HPT_U32)cdb[5] | ((HPT_U32)cdb[4] << 8) | ((HPT_U32)cdb[3] << 16) | ((HPT_U32)cdb[2] << 24);
+			pCmd->uCmd.Ide.nSectors = (HPT_U16) cdb[8] | ((HPT_U16)cdb[7]<<8);
+			break;
+		}
+		
+		switch (cdb[0]) {
+		case READ_6:
+		case READ_10:
+		case READ_16:
+			pCmd->flags.data_in = 1;
+			break;
+		case WRITE_6:
+		case WRITE_10:
+		case WRITE_16:
+			pCmd->flags.data_out = 1;
+			break;
+		}
+		pCmd->priv = ext = cmdext_get(vbus_ext);
+		HPT_ASSERT(ext);
+		ext->ccb = ccb;
+		pCmd->target = vd;
+		pCmd->done = os_cmddone;
+		pCmd->buildsgl = os_buildsgl;
+
+		pCmd->psg = ext->psg;
+		
+		if (ccb->ccb_h.flags & CAM_SCATTER_VALID) {
+			int idx;
+			bus_dma_segment_t *sgList = (bus_dma_segment_t *)ccb->csio.data_ptr;
+			
+			if (ccb->ccb_h.flags & CAM_SG_LIST_PHYS)
+				pCmd->flags.physical_sg = 1;
+				
+			for (idx = 0; idx < ccb->csio.sglist_cnt; idx++) {
+				pCmd->psg[idx].addr.bus = sgList[idx].ds_addr;
+				pCmd->psg[idx].size = sgList[idx].ds_len;
+				pCmd->psg[idx].eot = (idx==ccb->csio.sglist_cnt-1)? 1 : 0;
+			}
+
+			ccb->ccb_h.timeout_ch = timeout(hpt_timeout, pCmd, HPT_OSM_TIMEOUT);
+			ldm_queue_cmd(pCmd);
+		}
+		else {
+			int error;
+			pCmd->flags.physical_sg = 1;
+			error = bus_dmamap_load(vbus_ext->io_dmat, 
+						ext->dma_map, 
+						ccb->csio.data_ptr, ccb->csio.dxfer_len, 
+						hpt_io_dmamap_callback, pCmd,
+				    	BUS_DMA_WAITOK
+					);
+			KdPrint(("bus_dmamap_load return %d", error));
+			if (error && error!=EINPROGRESS) {
+				os_printk("bus_dmamap_load error %d", error);
+				cmdext_put(ext);
+				ldm_free_cmds(pCmd);
+				ccb->ccb_h.status = CAM_REQ_CMP_ERR;
+				xpt_done(ccb);
+			}
+		}
+		return;
+	}
+
+	default:
+		ccb->ccb_h.status = CAM_REQ_INVALID;
+		break;
+	}
+
+	xpt_done(ccb);
+	return;
+}
+
+static void hpt_action(struct cam_sim *sim, union ccb *ccb)
+{
+	PVBUS_EXT vbus_ext = (PVBUS_EXT)cam_sim_softc(sim);
+
+	KdPrint(("hpt_action(fn=%d, id=%d)", ccb->ccb_h.func_code, ccb->ccb_h.target_id));
+
+	switch (ccb->ccb_h.func_code) {
+	
+	case XPT_SCSI_IO:
+		hpt_lock_vbus(vbus_ext);
+		hpt_scsi_io(vbus_ext, ccb);
+		hpt_unlock_vbus(vbus_ext);
+		return;
+
+	case XPT_RESET_BUS:
+		hpt_lock_vbus(vbus_ext);
+		ldm_reset_vbus((PVBUS)vbus_ext->vbus);
+		hpt_unlock_vbus(vbus_ext);
+		break;
+
+	case XPT_GET_TRAN_SETTINGS:
+	case XPT_SET_TRAN_SETTINGS:
+		ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
+		break;
+
+	case XPT_CALC_GEOMETRY:
+		ccb->ccg.heads = 255;
+		ccb->ccg.secs_per_track = 63;
+		ccb->ccg.cylinders = ccb->ccg.volume_size / (ccb->ccg.heads * ccb->ccg.secs_per_track);
+		ccb->ccb_h.status = CAM_REQ_CMP;
+		break;
+
+	case XPT_PATH_INQ:
+	{
+		struct ccb_pathinq *cpi = &ccb->cpi;
+
+		cpi->version_num = 1;
+		cpi->hba_inquiry = PI_SDTR_ABLE;
+		cpi->target_sprt = 0;
+		cpi->hba_misc = PIM_NOBUSRESET;
+		cpi->hba_eng_cnt = 0;
+		cpi->max_target = osm_max_targets;
+		cpi->max_lun = 0;
+		cpi->unit_number = cam_sim_unit(sim);
+		cpi->bus_id = cam_sim_bus(sim);
+		cpi->initiator_id = osm_max_targets;
+		cpi->base_transfer_speed = 3300;
+
+		strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
+		strncpy(cpi->hba_vid, "HPT   ", HBA_IDLEN);
+		strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
+#if (__FreeBSD_version >= 800000)
+		cpi->transport = XPORT_SPI;
+		cpi->transport_version = 2;
+		cpi->protocol = PROTO_SCSI;
+		cpi->protocol_version = SCSI_REV_2;
+#endif
+		cpi->ccb_h.status = CAM_REQ_CMP;
+		break;
+	}
+
+	default:
+		ccb->ccb_h.status = CAM_REQ_INVALID;
+		break;
+	}
+
+	xpt_done(ccb);
+	return;
+}
+
+static void hpt_pci_intr(void *arg)
+{	
+	PVBUS_EXT vbus_ext = (PVBUS_EXT)arg;
+	hpt_lock_vbus(vbus_ext);
+	ldm_intr((PVBUS)vbus_ext->vbus);
+	hpt_unlock_vbus(vbus_ext);
+}
+
+static void hpt_poll(struct cam_sim *sim)
+{
+	hpt_pci_intr(cam_sim_softc(sim));
+}
+
+static void hpt_async(void * callback_arg, u_int32_t code, struct cam_path * path, void * arg)
+{
+	KdPrint(("hpt_async"));
+}
+
+static int hpt_shutdown(device_t dev)
+{
+	KdPrint(("hpt_shutdown(dev=%p)", dev));
+	return 0;
+}
+
+static int hpt_detach(device_t dev)
+{
+	/* we don't allow the driver to be unloaded. */
+	return EBUSY;
+}
+
+static void hpt_ioctl_done(struct _IOCTL_ARG *arg)
+{
+	arg->ioctl_cmnd = 0;
+	wakeup(arg);
+}
+
+static void __hpt_do_ioctl(PVBUS_EXT vbus_ext, IOCTL_ARG *ioctl_args)
+{
+	ioctl_args->result = -1;
+	ioctl_args->done = hpt_ioctl_done;
+	ioctl_args->ioctl_cmnd = (void *)1;
+
+	hpt_lock_vbus(vbus_ext);
+	ldm_ioctl((PVBUS)vbus_ext->vbus, ioctl_args);
+
+	while (ioctl_args->ioctl_cmnd) {
+		if (hpt_sleep(vbus_ext, ioctl_args, PPAUSE, "hptctl", HPT_OSM_TIMEOUT)==0)
+			break;
+		ldm_reset_vbus((PVBUS)vbus_ext->vbus);
+		__hpt_do_tasks(vbus_ext);
+	}
+
+	/* KdPrint(("ioctl %x result %d", ioctl_args->dwIoControlCode, ioctl_args->result)); */
+
+	hpt_unlock_vbus(vbus_ext);
+}
+
+static void hpt_do_ioctl(IOCTL_ARG *ioctl_args)
+{
+	PVBUS vbus;
+	PVBUS_EXT vbus_ext;
+	
+	ldm_for_each_vbus(vbus, vbus_ext) {
+		__hpt_do_ioctl(vbus_ext, ioctl_args);
+		if (ioctl_args->result!=HPT_IOCTL_RESULT_WRONG_VBUS)
+			return;
+	}
+}
+
+#define HPT_DO_IOCTL(code, inbuf, insize, outbuf, outsize) ({\
+	IOCTL_ARG arg;\
+	arg.dwIoControlCode = code;\
+	arg.lpInBuffer = inbuf;\
+	arg.lpOutBuffer = outbuf;\
+	arg.nInBufferSize = insize;\
+	arg.nOutBufferSize = outsize;\
+	arg.lpBytesReturned = 0;\
+	hpt_do_ioctl(&arg);\
+	arg.result;\
+})
+
+#define DEVICEID_VALID(id) ((id) && ((HPT_U32)(id)!=0xffffffff))
+
+static int hpt_get_logical_devices(DEVICEID * pIds, int nMaxCount)
+{
+	int i;
+	HPT_U32 count = nMaxCount-1;
+	
+	if (HPT_DO_IOCTL(HPT_IOCTL_GET_LOGICAL_DEVICES,
+			&count, sizeof(HPT_U32), pIds, sizeof(DEVICEID)*nMaxCount))
+		return -1;
+
+	nMaxCount = (int)pIds[0];
+	for (i=0; i<nMaxCount; i++) pIds[i] = pIds[i+1];
+	return nMaxCount;
+}
+
+static int hpt_get_device_info_v3(DEVICEID id, PLOGICAL_DEVICE_INFO_V3 pInfo)
+{
+	return HPT_DO_IOCTL(HPT_IOCTL_GET_DEVICE_INFO_V3,
+				&id, sizeof(DEVICEID), pInfo, sizeof(LOGICAL_DEVICE_INFO_V3));
+}
+
+/* not belong to this file logically, but we want to use ioctl interface */
+static int __hpt_stop_tasks(PVBUS_EXT vbus_ext, DEVICEID id)
+{
+	LOGICAL_DEVICE_INFO_V3 devinfo;
+	int i, result;
+	DEVICEID param[2] = { id, 0 };
+	
+	if (hpt_get_device_info_v3(id, &devinfo))
+		return -1;
+		
+	if (devinfo.Type!=LDT_ARRAY)
+		return -1;
+		
+	if (devinfo.u.array.Flags & ARRAY_FLAG_REBUILDING)
+		param[1] = AS_REBUILD_ABORT;
+	else if (devinfo.u.array.Flags & ARRAY_FLAG_VERIFYING)
+		param[1] = AS_VERIFY_ABORT;
+	else if (devinfo.u.array.Flags & ARRAY_FLAG_INITIALIZING)
+		param[1] = AS_INITIALIZE_ABORT;
+	else if (devinfo.u.array.Flags & ARRAY_FLAG_TRANSFORMING)
+		param[1] = AS_TRANSFORM_ABORT;
+	else
+		return -1;
+
+	KdPrint(("SET_ARRAY_STATE(%x, %d)", param[0], param[1]));
+	result = HPT_DO_IOCTL(HPT_IOCTL_SET_ARRAY_STATE,
+				param, sizeof(param), 0, 0);
+				
+	for (i=0; i<devinfo.u.array.nDisk; i++)
+		if (DEVICEID_VALID(devinfo.u.array.Members[i]))
+			__hpt_stop_tasks(vbus_ext, devinfo.u.array.Members[i]);
+			
+	return result;
+}
+
+static void hpt_stop_tasks(PVBUS_EXT vbus_ext)
+{
+	DEVICEID ids[32];
+	int i, count;
+
+	count = hpt_get_logical_devices((DEVICEID *)&ids, sizeof(ids)/sizeof(ids[0]));
+	
+	for (i=0; i<count; i++)
+		__hpt_stop_tasks(vbus_ext, ids[i]);
+}
+
+static	d_open_t	hpt_open;
+static	d_close_t	hpt_close;
+static	d_ioctl_t	hpt_ioctl;
+static	void		hpt_bus_scan_cb(struct cam_periph *periph, union ccb *ccb);
+static  int 		hpt_rescan_bus(void);
+
+static struct cdevsw hpt_cdevsw = {
+	.d_open =	hpt_open,
+	.d_close =	hpt_close,
+	.d_ioctl =	hpt_ioctl,
+	.d_name =	driver_name,
+#if __FreeBSD_version>=503000
+	.d_version =	D_VERSION,
+#endif
+#if (__FreeBSD_version>=503000 && __FreeBSD_version<600034)
+	.d_flags =	D_NEEDGIANT,
+#endif
+#if __FreeBSD_version<600034
+#if __FreeBSD_version>501000
+	.d_maj = 	MAJOR_AUTO,
+#else 
+	.d_maj = HPT_DEV_MAJOR,
+#endif
+#endif
+};
+
+static struct intr_config_hook hpt_ich;
+
+/*
+ * hpt_final_init will be called after all hpt_attach.
+ */
+static void hpt_final_init(void *dummy)
+{
+	int       i;
+	PVBUS_EXT vbus_ext;
+	PVBUS vbus;
+	PHBA hba;
+
+	/* Clear the config hook */
+	config_intrhook_disestablish(&hpt_ich);
+
+	/* allocate memory */
+	i = 0;
+	ldm_for_each_vbus(vbus, vbus_ext) {
+		if (hpt_alloc_mem(vbus_ext)) {
+			os_printk("out of memory");
+			return;
+		}
+		i++;
+	}
+
+	if (!i) {
+			os_printk("no controller detected.");
+		return;
+	}
+
+	/* initializing hardware */
+	ldm_for_each_vbus(vbus, vbus_ext) {
+		/* make timer available here */
+		callout_handle_init(&vbus_ext->timer);
+		if (hpt_init_vbus(vbus_ext)) {
+			os_printk("fail to initialize hardware");
+			break; /* FIXME */
+		}
+	}
+
+	/* register CAM interface */
+	ldm_for_each_vbus(vbus, vbus_ext) {
+		struct cam_devq *devq;
+		struct ccb_setasync	ccb;
+		
+#if (__FreeBSD_version >= 500000)
+		mtx_init(&vbus_ext->lock, "hptsleeplock", NULL, MTX_DEF);
+#endif
+		if (bus_dma_tag_create(NULL,/* parent */
+				4,	/* alignment */
+				BUS_SPACE_MAXADDR_32BIT+1, /* boundary */
+				BUS_SPACE_MAXADDR,	/* lowaddr */
+				BUS_SPACE_MAXADDR, 	/* highaddr */
+				NULL, NULL, 		/* filter, filterarg */
+				PAGE_SIZE * (os_max_sg_descriptors-1),	/* maxsize */
+				os_max_sg_descriptors,	/* nsegments */
+				0x10000,	/* maxsegsize */
+				BUS_DMA_WAITOK,		/* flags */
+#if __FreeBSD_version>502000
+				busdma_lock_mutex,	/* lockfunc */
+				&vbus_ext->lock,		/* lockfuncarg */
+#endif
+				&vbus_ext->io_dmat	/* tag */))
+		{
+			return ;
+		}
+
+		for (i=0; i<os_max_queue_comm; i++) {
+			POS_CMDEXT ext = (POS_CMDEXT)malloc(sizeof(OS_CMDEXT), M_DEVBUF, M_WAITOK);
+			if (!ext) {
+				os_printk("Can't alloc cmdext(%d)", i);
+				return ;
+			}
+			ext->vbus_ext = vbus_ext;
+			ext->next = vbus_ext->cmdext_list;
+			vbus_ext->cmdext_list = ext;
+	
+			if (bus_dmamap_create(vbus_ext->io_dmat, 0, &ext->dma_map)) {
+				os_printk("Can't create dma map(%d)", i);
+				return ;
+			}
+		}
+
+		if ((devq = cam_simq_alloc(os_max_queue_comm)) == NULL) {
+			os_printk("cam_simq_alloc failed");
+			return ;
+		}
+
+#if __FreeBSD_version > 700025
+		vbus_ext->sim = cam_sim_alloc(hpt_action, hpt_poll, driver_name,
+				vbus_ext, 0, &Giant, os_max_queue_comm, /*tagged*/8,  devq);
+#else 
+		vbus_ext->sim = cam_sim_alloc(hpt_action, hpt_poll, driver_name,
+				vbus_ext, 0, os_max_queue_comm, /*tagged*/8,  devq);
+#endif
+				
+		if (!vbus_ext->sim) {
+			os_printk("cam_sim_alloc failed");
+			cam_simq_free(devq);
+			return ;
+		}
+
+#if __FreeBSD_version > 700044
+		if (xpt_bus_register(vbus_ext->sim, NULL, 0) != CAM_SUCCESS) {
+#else 
+		if (xpt_bus_register(vbus_ext->sim, 0) != CAM_SUCCESS) {
+#endif
+			os_printk("xpt_bus_register failed");
+			cam_sim_free(vbus_ext->sim, /*free devq*/ TRUE);
+			vbus_ext->sim = NULL;
+			return ;
+		}
+	
+		if (xpt_create_path(&vbus_ext->path, /*periph */ NULL,
+				cam_sim_path(vbus_ext->sim), CAM_TARGET_WILDCARD,
+				CAM_LUN_WILDCARD) != CAM_REQ_CMP)
+		{
+			os_printk("xpt_create_path failed");
+			xpt_bus_deregister(cam_sim_path(vbus_ext->sim));
+			cam_sim_free(vbus_ext->sim, /*free_devq*/TRUE);
+			vbus_ext->sim = NULL;
+			return ;
+		}
+
+		xpt_setup_ccb(&ccb.ccb_h, vbus_ext->path, /*priority*/5);
+		ccb.ccb_h.func_code = XPT_SASYNC_CB;
+		ccb.event_enable = AC_LOST_DEVICE;
+		ccb.callback = hpt_async;
+		ccb.callback_arg = vbus_ext;
+		xpt_action((union ccb *)&ccb);
+
+		for (hba = vbus_ext->hba_list; hba; hba = hba->next) {
+			int rid = 0;
+			if ((hba->irq_res = bus_alloc_resource(hba->pcidev,
+				SYS_RES_IRQ, &rid, 0, ~0ul, 1, RF_SHAREABLE | RF_ACTIVE)) == NULL)
+			{
+				os_printk("can't allocate interrupt");
+				return ;
+			}
+			
+			if (bus_setup_intr(hba->pcidev, hba->irq_res, INTR_TYPE_CAM,
+#if __FreeBSD_version > 700025
+				NULL, hpt_pci_intr, vbus_ext, &hba->irq_handle)) 
+#else 
+				hpt_pci_intr, vbus_ext, &hba->irq_handle)) 
+#endif
+			{
+				os_printk("can't set up interrupt");
+				return ;
+			}
+			hba->ldm_adapter.him->intr_control(hba->ldm_adapter.him_handle, HPT_TRUE);
+
+		}
+
+		vbus_ext->shutdown_eh = EVENTHANDLER_REGISTER(shutdown_final, 
+									hpt_shutdown_vbus, vbus_ext, SHUTDOWN_PRI_DEFAULT);
+		if (!vbus_ext->shutdown_eh)
+			os_printk("Shutdown event registration failed");
+	}
+	
+	ldm_for_each_vbus(vbus, vbus_ext) {
+		TASK_INIT(&vbus_ext->worker, 0, (task_fn_t *)hpt_do_tasks, vbus_ext);
+		if (vbus_ext->tasks)
+			TASK_ENQUEUE(&vbus_ext->worker);
+	}	
+
+	make_dev(&hpt_cdevsw, DRIVER_MINOR, UID_ROOT, GID_OPERATOR,
+	    S_IRUSR | S_IWUSR, driver_name);
+}
+
+#if defined(KLD_MODULE) && (__FreeBSD_version >= 503000)
+
+typedef struct driverlink *driverlink_t;
+struct driverlink {
+	kobj_class_t	driver;
+	TAILQ_ENTRY(driverlink) link;	/* list of drivers in devclass */
+};
+
+typedef TAILQ_HEAD(driver_list, driverlink) driver_list_t;
+
+struct devclass {
+	TAILQ_ENTRY(devclass) link;
+	devclass_t	parent;		/* parent in devclass hierarchy */
+	driver_list_t	drivers;     /* bus devclasses store drivers for bus */
+	char		*name;
+	device_t	*devices;	/* array of devices indexed by unit */
+	int		maxunit;	/* size of devices array */
+};
+
+static void override_kernel_driver(void)
+{
+	driverlink_t dl, dlfirst;
+	driver_t *tmpdriver;
+	devclass_t dc = devclass_find("pci");
+	
+	if (dc){
+		dlfirst = TAILQ_FIRST(&dc->drivers);
+		for (dl = dlfirst; dl; dl = TAILQ_NEXT(dl, link)) {
+			if(strcmp(dl->driver->name, driver_name) == 0) {
+				tmpdriver=dl->driver;
+				dl->driver=dlfirst->driver;
+				dlfirst->driver=tmpdriver;
+				break;
+			}
+		}
+	}
+}
+
+#else 
+#define override_kernel_driver()
+#endif
+
+static void hpt_init(void *dummy)
+{
+		os_printk("%s %s", driver_name_long, driver_ver);
+
+	override_kernel_driver();
+	init_config();
+
+	hpt_ich.ich_func = hpt_final_init;
+	hpt_ich.ich_arg = NULL;
+	if (config_intrhook_establish(&hpt_ich) != 0) {
+		printf("%s: cannot establish configuration hook\n",
+		    driver_name_long);
+	}
+
+}
+SYSINIT(hptinit, SI_SUB_CONFIGURE, SI_ORDER_FIRST, hpt_init, NULL);
+
+/*
+ * CAM driver interface
+ */
+static device_method_t driver_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		hpt_probe),
+	DEVMETHOD(device_attach,	hpt_attach),
+	DEVMETHOD(device_detach,	hpt_detach),
+	DEVMETHOD(device_shutdown,	hpt_shutdown),
+	{ 0, 0 }
+};
+
+static driver_t hpt_pci_driver = {
+	driver_name,
+	driver_methods,
+	sizeof(HBA)
+};
+
+static devclass_t	hpt_devclass;
+
+#ifndef TARGETNAME
+#error "no TARGETNAME found"
+#endif
+
+/* use this to make TARGETNAME be expanded */
+#define __DRIVER_MODULE(p1, p2, p3, p4, p5, p6) DRIVER_MODULE(p1, p2, p3, p4, p5, p6)
+#define __MODULE_VERSION(p1, p2) MODULE_VERSION(p1, p2)
+#define __MODULE_DEPEND(p1, p2, p3, p4, p5) MODULE_DEPEND(p1, p2, p3, p4, p5)
+__DRIVER_MODULE(TARGETNAME, pci, hpt_pci_driver, hpt_devclass, 0, 0);
+__MODULE_VERSION(TARGETNAME, 1);
+__MODULE_DEPEND(TARGETNAME, cam, 1, 1, 1);
+
+#if __FreeBSD_version>503000
+typedef struct cdev * ioctl_dev_t;
+#else 
+typedef dev_t ioctl_dev_t;
+#endif
+
+#if __FreeBSD_version >= 500000
+typedef	struct thread *	ioctl_thread_t;
+#else 
+typedef struct proc *	ioctl_thread_t;
+#endif
+
+static int hpt_open(ioctl_dev_t dev, int flags, int devtype, ioctl_thread_t td)
+{
+	return 0;
+}
+
+static int hpt_close(ioctl_dev_t dev, int flags, int devtype, ioctl_thread_t td)
+{
+	return 0;
+}
+
+static int hpt_ioctl(ioctl_dev_t dev, u_long cmd, caddr_t data, int fflag, ioctl_thread_t td)
+{
+	PHPT_IOCTL_PARAM piop=(PHPT_IOCTL_PARAM)data;
+	IOCTL_ARG ioctl_args;
+	HPT_U32 bytesReturned;
+
+	switch (cmd){
+	case HPT_DO_IOCONTROL:
+	{	
+		if (piop->Magic == HPT_IOCTL_MAGIC || piop->Magic == HPT_IOCTL_MAGIC32) {
+			KdPrint(("ioctl=%x in=%p len=%d out=%p len=%d\n",
+				piop->dwIoControlCode,
+				piop->lpInBuffer,
+				piop->nInBufferSize,
+				piop->lpOutBuffer,
+				piop->nOutBufferSize));
+			
+		memset(&ioctl_args, 0, sizeof(ioctl_args));
+		
+		ioctl_args.dwIoControlCode = piop->dwIoControlCode;
+		ioctl_args.nInBufferSize = piop->nInBufferSize;
+		ioctl_args.nOutBufferSize = piop->nOutBufferSize;
+		ioctl_args.lpBytesReturned = &bytesReturned;
+
+		if (ioctl_args.nInBufferSize) {
+			ioctl_args.lpInBuffer = malloc(ioctl_args.nInBufferSize, M_DEVBUF, M_WAITOK);
+			if (!ioctl_args.lpInBuffer)
+				goto invalid;
+			if (copyin((void*)piop->lpInBuffer,
+					ioctl_args.lpInBuffer, piop->nInBufferSize))
+				goto invalid;
+		}
+	
+		if (ioctl_args.nOutBufferSize) {
+			ioctl_args.lpOutBuffer = malloc(ioctl_args.nOutBufferSize, M_DEVBUF, M_WAITOK);
+			if (!ioctl_args.lpOutBuffer)
+				goto invalid;
+		}
+		
+#if (__FreeBSD_version >= 500000)
+		mtx_lock(&Giant);
+#endif
+
+		hpt_do_ioctl(&ioctl_args);
+	
+#if (__FreeBSD_version >= 500000)
+		mtx_unlock(&Giant);
+#endif
+
+		if (ioctl_args.result==HPT_IOCTL_RESULT_OK) {
+			if (piop->nOutBufferSize) {
+				if (copyout(ioctl_args.lpOutBuffer,
+					(void*)piop->lpOutBuffer, piop->nOutBufferSize))
+					goto invalid;
+			}
+			if (piop->lpBytesReturned) {
+				if (copyout(&bytesReturned,
+					(void*)piop->lpBytesReturned, sizeof(HPT_U32)))
+					goto invalid;
+			}
+			if (ioctl_args.lpInBuffer) free(ioctl_args.lpInBuffer, M_DEVBUF);
+			if (ioctl_args.lpOutBuffer) free(ioctl_args.lpOutBuffer, M_DEVBUF);
+			return 0;
+		}
+invalid:
+		if (ioctl_args.lpInBuffer) free(ioctl_args.lpInBuffer, M_DEVBUF);
+		if (ioctl_args.lpOutBuffer) free(ioctl_args.lpOutBuffer, M_DEVBUF);
+		return EFAULT;
+	}
+	return EFAULT;
+	}
+
+	case HPT_SCAN_BUS:
+	{
+		return hpt_rescan_bus();
+	}
+	default:
+		KdPrint(("invalid command!"));
+		return EFAULT;
+	}	
+
+}
+
+static int	hpt_rescan_bus(void)
+{
+	struct cam_path		*path;
+	union ccb			*ccb;
+	PVBUS 				vbus;
+	PVBUS_EXT			vbus_ext;	
+		
+#if (__FreeBSD_version >= 500000)
+	mtx_lock(&Giant);
+#endif
+
+	ldm_for_each_vbus(vbus, vbus_ext) {
+		if (xpt_create_path(&path, xpt_periph, cam_sim_path(vbus_ext->sim),
+			CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP)	
+			return(EIO);
+		if ((ccb = malloc(sizeof(union ccb), M_TEMP, M_WAITOK)) == NULL)
+			return(ENOMEM);
+		bzero(ccb, sizeof(union ccb));
+		xpt_setup_ccb(&ccb->ccb_h, path, 5);
+		ccb->ccb_h.func_code = XPT_SCAN_BUS;
+		ccb->ccb_h.cbfcnp = hpt_bus_scan_cb;
+		ccb->crcn.flags = CAM_FLAG_NONE;
+		xpt_action(ccb);
+	}
+	
+#if (__FreeBSD_version >= 500000)
+	mtx_unlock(&Giant);
+#endif
+
+	return(0);	
+}
+
+static	void	hpt_bus_scan_cb(struct cam_periph *periph, union ccb *ccb)
+{
+	if (ccb->ccb_h.status != CAM_REQ_CMP)
+		KdPrint(("cam_scan_callback: failure status = %x",ccb->ccb_h.status));
+	else
+		KdPrint(("Scan bus successfully!"));
+
+	xpt_free_path(ccb->ccb_h.path);
+	free(ccb, M_TEMP);
+	return;
+}
diff --git a/sys/dev/hpt27xx/wj.h b/sys/dev/hpt27xx/wj.h
new file mode 100644
index 0000000..7f2a9c9c
--- /dev/null
+++ b/sys/dev/hpt27xx/wj.h
@@ -0,0 +1,56 @@
+/*-
+ * Copyright (c) 2011 HighPoint Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <dev/hpt27xx/hpt27xx_config.h>
+/*
+ * NVRAM write journaling interface.
+ */
+
+#ifndef _WJ_H_
+#define _WJ_H_
+
+#if defined(SUPPORT_BBU) || defined(SUPPORT_NVRAM)
+
+void wj_init(PVBUS vbus, void *nvram_addr, HPT_U32 nvram_size);
+void *wj_add_entry(PVBUS vbus, PVDEV vd, HPT_LBA lba, HPT_U16 sectors);
+void *wj_get_entry(PVBUS vbus, PVDEV *vd_p, HPT_LBA *lba_p, HPT_U16 *sectors_p);
+void wj_del_entry(PVBUS vbus, void *handle);
+void wj_del_vd(PVBUS vbus, PVDEV vd);
+void wj_sync_stamp(PVBUS vbus, PVDEV vd);
+
+#else 
+
+#define wj_add_entry(vbus, vd, lba, sectors) 0
+#define wj_get_entry(vbus, vd_p, lba_p, sectors_p) 0
+#define wj_del_entry(vbus, handle) 0
+#define wj_del_vd(vbus, vd) 0
+#define wj_sync_stamp(vbus, vd) 0
+
+#endif
+
+#endif
diff --git a/sys/dev/hptiop/hptiop.c b/sys/dev/hptiop/hptiop.c
index c4e2427..035cf07 100644
--- a/sys/dev/hptiop/hptiop.c
+++ b/sys/dev/hptiop/hptiop.c
@@ -1813,11 +1813,15 @@ scsi_done:
 		break;
 
 	case XPT_CALC_GEOMETRY:
+#if __FreeBSD_version >= 500000
+		cam_calc_geometry(&ccb->ccg, 1);
+#else
 		ccb->ccg.heads = 255;
 		ccb->ccg.secs_per_track = 63;
 		ccb->ccg.cylinders = ccb->ccg.volume_size /
 				(ccb->ccg.heads * ccb->ccg.secs_per_track);
 		ccb->ccb_h.status = CAM_REQ_CMP;
+#endif
 		break;
 
 	case XPT_PATH_INQ:
diff --git a/sys/dev/hptmv/entry.c b/sys/dev/hptmv/entry.c
index b1b4f24..4c61e65 100644
--- a/sys/dev/hptmv/entry.c
+++ b/sys/dev/hptmv/entry.c
@@ -22,9 +22,10 @@
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
- *
- * $FreeBSD$
  */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
  
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -94,7 +95,7 @@ static device_method_t driver_methods[] = {
 	DEVMETHOD(device_detach,	hpt_detach),
 
 	DEVMETHOD(device_shutdown,	hpt_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t hpt_pci_driver = {
@@ -2371,7 +2372,10 @@ hpt_action(struct cam_sim *sim, union ccb *ccb)
 			break;
 
 		case XPT_CALC_GEOMETRY:
-		{
+#if __FreeBSD_version >= 500000
+			cam_calc_geometry(&ccb->ccg, 1);
+#else
+			{
 			struct	  ccb_calc_geometry *ccg;
 			u_int32_t size_mb;
 			u_int32_t secs_per_cylinder;
@@ -2389,9 +2393,10 @@ hpt_action(struct cam_sim *sim, union ccb *ccb)
 			secs_per_cylinder = ccg->heads * ccg->secs_per_track;
 			ccg->cylinders = ccg->volume_size / secs_per_cylinder;
 			ccb->ccb_h.status = CAM_REQ_CMP;
+			}
+#endif
 			xpt_done(ccb);
 			break;
-		}
 
 		case XPT_PATH_INQ:		/* Path routing inquiry */
 		{
diff --git a/sys/dev/hptrr/hptrr_osm_bsd.c b/sys/dev/hptrr/hptrr_osm_bsd.c
index 0469791..1f6b19a 100644
--- a/sys/dev/hptrr/hptrr_osm_bsd.c
+++ b/sys/dev/hptrr/hptrr_osm_bsd.c
@@ -22,9 +22,11 @@
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
- *
- * $FreeBSD$
  */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #include <dev/hptrr/hptrr_config.h>
 /* $Id: osm_bsd.c,v 1.27 2007/11/22 07:35:49 gmm Exp $
  *
@@ -795,10 +797,14 @@ static void hpt_action(struct cam_sim *sim, union ccb *ccb)
 		break;
 
 	case XPT_CALC_GEOMETRY:
+#if __FreeBSD_version >= 500000
+		cam_calc_geometry(&ccb->ccg, 1);
+#else
 		ccb->ccg.heads = 255;
 		ccb->ccg.secs_per_track = 63;
 		ccb->ccg.cylinders = ccb->ccg.volume_size / (ccb->ccg.heads * ccb->ccg.secs_per_track);
 		ccb->ccb_h.status = CAM_REQ_CMP;
+#endif
 		break;
 
 	case XPT_PATH_INQ:
@@ -1250,7 +1256,7 @@ static device_method_t driver_methods[] = {
 	DEVMETHOD(device_attach,	hpt_attach),
 	DEVMETHOD(device_detach,	hpt_detach),
 	DEVMETHOD(device_shutdown,	hpt_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t hpt_pci_driver = {
diff --git a/sys/dev/hwpmc/hwpmc_amd.c b/sys/dev/hwpmc/hwpmc_amd.c
index 268904b..9ffa62f 100644
--- a/sys/dev/hwpmc/hwpmc_amd.c
+++ b/sys/dev/hwpmc/hwpmc_amd.c
@@ -889,7 +889,6 @@ pmc_amd_initialize(void)
 	 * field returned by CPUID for instruction family >= 6.
 	 */
 
-	class = cputype = -1;
 	name = NULL;
 	switch (cpu_id & 0xF00) {
 #if	defined(__i386__)
@@ -906,9 +905,8 @@ pmc_amd_initialize(void)
 		class = PMC_CLASS_K8;
 		name = "K8";
 		break;
-	}
 
-	if ((int) cputype == -1) {
+	default:
 		(void) printf("pmc: Unknown AMD CPU.\n");
 		return NULL;
 	}
diff --git a/sys/dev/hwpmc/hwpmc_core.c b/sys/dev/hwpmc/hwpmc_core.c
index 01bd482..207d68b 100644
--- a/sys/dev/hwpmc/hwpmc_core.c
+++ b/sys/dev/hwpmc/hwpmc_core.c
@@ -41,6 +41,7 @@ __FBSDID("$FreeBSD$");
 #include <machine/apicvar.h>
 #include <machine/cpu.h>
 #include <machine/cpufunc.h>
+#include <machine/md_var.h>
 #include <machine/specialreg.h>
 
 #define	CORE_CPUID_REQUEST		0xA
@@ -1479,6 +1480,10 @@ iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri)
 		/*
 		 * Events valid only on counter 0.
 		 */
+	case PMC_EV_IAP_EVENT_60H_01H:
+	case PMC_EV_IAP_EVENT_60H_02H:
+	case PMC_EV_IAP_EVENT_60H_04H:
+	case PMC_EV_IAP_EVENT_60H_08H:	
 	case PMC_EV_IAP_EVENT_B3H_01H:
 	case PMC_EV_IAP_EVENT_B3H_02H:
 	case PMC_EV_IAP_EVENT_B3H_04H:
@@ -1488,6 +1493,10 @@ iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri)
 		/*
 		 * Events valid only on counter 0, 1.
 		 */
+	case PMC_EV_IAP_EVENT_4CH_01H:
+	case PMC_EV_IAP_EVENT_4EH_01H:
+	case PMC_EV_IAP_EVENT_4EH_02H:
+	case PMC_EV_IAP_EVENT_4EH_04H:
 	case PMC_EV_IAP_EVENT_51H_01H:
 	case PMC_EV_IAP_EVENT_51H_02H:
 	case PMC_EV_IAP_EVENT_51H_04H:
@@ -1545,7 +1554,7 @@ static int
 iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
     const struct pmc_op_pmcallocate *a)
 {
-	int n;
+	int n, model;
 	enum pmc_event ev;
 	struct iap_event_descr *ie;
 	uint32_t c, caps, config, cpuflag, evsel, mask;
@@ -1565,6 +1574,16 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
 	if (iap_architectural_event_is_unsupported(ev))
 		return (EOPNOTSUPP);
 
+	/*
+	 * A small number of events are not supported in all the
+	 * processors based on a given microarchitecture.
+	 */
+	if (ev == PMC_EV_IAP_EVENT_0FH_01H || ev == PMC_EV_IAP_EVENT_0FH_80H) { 
+		model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4);
+		if (core_cputype == PMC_CPU_INTEL_COREI7 && model != 0x2E)  
+			return (EINVAL); 	
+	}
+	
 	switch (core_cputype) {
 	case PMC_CPU_INTEL_COREI7:
 		if (iap_event_corei7_ok_on_counter(ev, ri) == 0)
@@ -1702,7 +1721,7 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
 		if (core_cputype == PMC_CPU_INTEL_COREI7 &&
 		    ev == PMC_EV_IAP_EVENT_BBH_01H)
 			return (EINVAL);
-		if ( a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK)
+		if (a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK)
 			return (EINVAL);
 		pm->pm_md.pm_iap.pm_iap_rsp =
 		    a->pm_md.pm_iap.pm_iap_rsp & IA_OFFCORE_RSP_MASK;
diff --git a/sys/dev/hwpmc/hwpmc_powerpc.c b/sys/dev/hwpmc/hwpmc_powerpc.c
index ce1caf6..8e97b97 100644
--- a/sys/dev/hwpmc/hwpmc_powerpc.c
+++ b/sys/dev/hwpmc/hwpmc_powerpc.c
@@ -1,4 +1,5 @@
 /*-
+ * Copyright (c) 2011 Justin Hibbits
  * Copyright (c) 2005, Joseph Koshy
  * All rights reserved.
  *
@@ -30,20 +31,297 @@ __FBSDID("$FreeBSD$");
 
 #include <sys/param.h>
 #include <sys/pmc.h>
+#include <sys/pmckern.h>
+#include <sys/systm.h>
 
 #include <machine/pmc_mdep.h>
+#include <machine/spr.h>
+#include <machine/cpu.h>
 
-struct pmc_mdep *
-pmc_md_initialize()
-{
-	return NULL;
-}
+#define	POWERPC_PMC_CAPS	(PMC_CAP_INTERRUPT | PMC_CAP_USER |     \
+				 PMC_CAP_SYSTEM | PMC_CAP_EDGE |	\
+				 PMC_CAP_THRESHOLD | PMC_CAP_READ |	\
+				 PMC_CAP_WRITE | PMC_CAP_INVERT |	\
+				 PMC_CAP_QUALIFIER)
 
-void
-pmc_md_finalize(struct pmc_mdep *md)
-{
-	(void) md;
-}
+#define PPC_SET_PMC1SEL(r, x)	((r & ~(SPR_MMCR0_PMC1SEL(0x3f))) | SPR_MMCR0_PMC1SEL(x))
+#define PPC_SET_PMC2SEL(r, x)	((r & ~(SPR_MMCR0_PMC2SEL(0x3f))) | SPR_MMCR0_PMC2SEL(x))
+#define PPC_SET_PMC3SEL(r, x)	((r & ~(SPR_MMCR1_PMC3SEL(0x1f))) | SPR_MMCR1_PMC3SEL(x))
+#define PPC_SET_PMC4SEL(r, x)	((r & ~(SPR_MMCR1_PMC4SEL(0x1f))) | SPR_MMCR1_PMC4SEL(x))
+#define PPC_SET_PMC5SEL(r, x)	((r & ~(SPR_MMCR1_PMC5SEL(0x1f))) | SPR_MMCR1_PMC5SEL(x))
+#define PPC_SET_PMC6SEL(r, x)	((r & ~(SPR_MMCR1_PMC6SEL(0x3f))) | SPR_MMCR1_PMC6SEL(x))
+
+/* Change this when we support more than just the 7450. */
+#define PPC_MAX_PMCS	6
+
+#define POWERPC_PMC_KERNEL_ENABLE	(0x1 << 30)
+#define POWERPC_PMC_USER_ENABLE		(0x1 << 31)
+
+#define POWERPC_PMC_ENABLE		(POWERPC_PMC_KERNEL_ENABLE | POWERPC_PMC_USER_ENABLE)
+#define	POWERPC_RELOAD_COUNT_TO_PERFCTR_VALUE(V)	(0x80000000-(V))
+#define	POWERPC_PERFCTR_VALUE_TO_RELOAD_COUNT(P)	((P)-0x80000000)
+#define POWERPC_PMC_HAS_OVERFLOWED(x) (powerpc_pmcn_read(x) & (0x1 << 31))
+
+
+/*
+ * This should work for every 32-bit PowerPC implementation I know of (G3 and G4
+ * specifically).  PoewrPC 970 will take more work.
+ */
+
+/*
+ * Per-processor information.
+ */
+struct powerpc_cpu {
+	struct pmc_hw   *pc_ppcpmcs;
+};
+
+static struct powerpc_cpu **powerpc_pcpu;
+
+struct powerpc_event_code_map {
+	enum pmc_event	pe_ev;       /* enum value */
+	uint8_t         pe_counter_mask;  /* Which counter this can be counted in. */
+	uint8_t			pe_code;     /* numeric code */
+};
+
+#define PPC_PMC_MASK1	0
+#define PPC_PMC_MASK2	1
+#define PPC_PMC_MASK3	2
+#define PPC_PMC_MASK4	3
+#define PPC_PMC_MASK5	4
+#define PPC_PMC_MASK6	5
+#define PPC_PMC_MASK_ALL	0x3f
+
+#define PMC_POWERPC_EVENT(id, mask, number) \
+	{ .pe_ev = PMC_EV_PPC7450_##id, .pe_counter_mask = mask, .pe_code = number }
+
+static struct powerpc_event_code_map powerpc_event_codes[] = {
+	PMC_POWERPC_EVENT(CYCLE,PPC_PMC_MASK_ALL, 1),
+	PMC_POWERPC_EVENT(INSTR_COMPLETED, 0x0f, 2),
+	PMC_POWERPC_EVENT(TLB_BIT_TRANSITIONS, 0x0f, 3),
+	PMC_POWERPC_EVENT(INSTR_DISPATCHED, 0x0f, 4),
+	PMC_POWERPC_EVENT(PMON_EXCEPT, 0x0f, 5),
+	PMC_POWERPC_EVENT(PMON_SIG, 0x0f, 7),
+	PMC_POWERPC_EVENT(VPU_INSTR_COMPLETED, 0x03, 8),
+	PMC_POWERPC_EVENT(VFPU_INSTR_COMPLETED, 0x03, 9),
+	PMC_POWERPC_EVENT(VIU1_INSTR_COMPLETED, 0x03, 10),
+	PMC_POWERPC_EVENT(VIU2_INSTR_COMPLETED, 0x03, 11),
+	PMC_POWERPC_EVENT(MTVSCR_INSTR_COMPLETED, 0x03, 12),
+	PMC_POWERPC_EVENT(MTVRSAVE_INSTR_COMPLETED, 0x03, 13),
+	PMC_POWERPC_EVENT(VPU_INSTR_WAIT_CYCLES, 0x03, 14),
+	PMC_POWERPC_EVENT(VFPU_INSTR_WAIT_CYCLES, 0x03, 15),
+	PMC_POWERPC_EVENT(VIU1_INSTR_WAIT_CYCLES, 0x03, 16),
+	PMC_POWERPC_EVENT(VIU2_INSTR_WAIT_CYCLES, 0x03, 17),
+	PMC_POWERPC_EVENT(MFVSCR_SYNC_CYCLES, 0x03, 18),
+	PMC_POWERPC_EVENT(VSCR_SAT_SET, 0x03, 19),
+	PMC_POWERPC_EVENT(STORE_INSTR_COMPLETED, 0x03, 20),
+	PMC_POWERPC_EVENT(L1_INSTR_CACHE_MISSES, 0x03, 21),
+	PMC_POWERPC_EVENT(L1_DATA_SNOOPS, 0x03, 22),
+	PMC_POWERPC_EVENT(UNRESOLVED_BRANCHES, 0x01, 23),
+	PMC_POWERPC_EVENT(SPEC_BUFFER_CYCLES, 0x01, 24),
+	PMC_POWERPC_EVENT(BRANCH_UNIT_STALL_CYCLES, 0x01, 25),
+	PMC_POWERPC_EVENT(TRUE_BRANCH_TARGET_HITS, 0x01, 26),
+	PMC_POWERPC_EVENT(BRANCH_LINK_STAC_PREDICTED, 0x01, 27),
+	PMC_POWERPC_EVENT(GPR_ISSUE_QUEUE_DISPATCHES, 0x01, 28),
+	PMC_POWERPC_EVENT(CYCLES_THREE_INSTR_DISPATCHED, 0x01, 29),
+	PMC_POWERPC_EVENT(THRESHOLD_INSTR_QUEUE_ENTRIES_CYCLES, 0x01, 30),
+	PMC_POWERPC_EVENT(THRESHOLD_VEC_INSTR_QUEUE_ENTRIES_CYCLES, 0x01, 31),
+	PMC_POWERPC_EVENT(CYCLES_NO_COMPLETED_INSTRS, 0x01, 32),
+	PMC_POWERPC_EVENT(IU2_INSTR_COMPLETED, 0x01, 33),
+	PMC_POWERPC_EVENT(BRANCHES_COMPLETED, 0x01, 34),
+	PMC_POWERPC_EVENT(EIEIO_INSTR_COMPLETED, 0x01, 35),
+	PMC_POWERPC_EVENT(MTSPR_INSTR_COMPLETED, 0x01, 36),
+	PMC_POWERPC_EVENT(SC_INSTR_COMPLETED, 0x01, 37),
+	PMC_POWERPC_EVENT(LS_LM_COMPLETED, 0x01, 38),
+	PMC_POWERPC_EVENT(ITLB_HW_TABLE_SEARCH_CYCLES, 0x01, 39),
+	PMC_POWERPC_EVENT(DTLB_HW_SEARCH_CYCLES_OVER_THRESHOLD, 0x01, 40),
+	PMC_POWERPC_EVENT(L1_INSTR_CACHE_ACCESSES, 0x01, 41),
+	PMC_POWERPC_EVENT(INSTR_BKPT_MATCHES, 0x01, 42),
+	PMC_POWERPC_EVENT(L1_DATA_CACHE_LOAD_MISS_CYCLES_OVER_THRESHOLD, 0x01, 43),
+	PMC_POWERPC_EVENT(L1_DATA_SNOOP_HIT_ON_MODIFIED, 0x01, 44),
+	PMC_POWERPC_EVENT(LOAD_MISS_ALIAS, 0x01, 45),
+	PMC_POWERPC_EVENT(LOAD_MISS_ALIAS_ON_TOUCH, 0x01, 46),
+	PMC_POWERPC_EVENT(TOUCH_ALIAS, 0x01, 47),
+	PMC_POWERPC_EVENT(L1_DATA_SNOOP_HIT_CASTOUT_QUEUE, 0x01, 48),
+	PMC_POWERPC_EVENT(L1_DATA_SNOOP_HIT_CASTOUT, 0x01, 49),
+	PMC_POWERPC_EVENT(L1_DATA_SNOOP_HITS, 0x01, 50),
+	PMC_POWERPC_EVENT(WRITE_THROUGH_STORES, 0x01, 51),
+	PMC_POWERPC_EVENT(CACHE_INHIBITED_STORES, 0x01, 52),
+	PMC_POWERPC_EVENT(L1_DATA_LOAD_HIT, 0x01, 53),
+	PMC_POWERPC_EVENT(L1_DATA_TOUCH_HIT, 0x01, 54),
+	PMC_POWERPC_EVENT(L1_DATA_STORE_HIT, 0x01, 55),
+	PMC_POWERPC_EVENT(L1_DATA_TOTAL_HITS, 0x01, 56),
+	PMC_POWERPC_EVENT(DST_INSTR_DISPATCHED, 0x01, 57),
+	PMC_POWERPC_EVENT(REFRESHED_DSTS, 0x01, 58),
+	PMC_POWERPC_EVENT(SUCCESSFUL_DST_TABLE_SEARCHES, 0x01, 59),
+	PMC_POWERPC_EVENT(DSS_INSTR_COMPLETED, 0x01, 60),
+	PMC_POWERPC_EVENT(DST_STREAM_0_CACHE_LINE_FETCHES, 0x01, 61),
+	PMC_POWERPC_EVENT(VTQ_SUSPENDS_DUE_TO_CTX_CHANGE, 0x01, 62),
+	PMC_POWERPC_EVENT(VTQ_LINE_FETCH_HIT, 0x01, 63),
+	PMC_POWERPC_EVENT(VEC_LOAD_INSTR_COMPLETED, 0x01, 64),
+	PMC_POWERPC_EVENT(FP_STORE_INSTR_COMPLETED_IN_LSU, 0x01, 65),
+	PMC_POWERPC_EVENT(FPU_RENORMALIZATION, 0x01, 66),
+	PMC_POWERPC_EVENT(FPU_DENORMALIZATION, 0x01, 67),
+	PMC_POWERPC_EVENT(FP_STORE_CAUSES_STALL_IN_LSU, 0x01, 68),
+	PMC_POWERPC_EVENT(LD_ST_TRUE_ALIAS_STALL, 0x01, 70),
+	PMC_POWERPC_EVENT(LSU_INDEXED_ALIAS_STALL, 0x01, 71),
+	PMC_POWERPC_EVENT(LSU_ALIAS_VS_FSQ_WB0_WB1, 0x01, 72),
+	PMC_POWERPC_EVENT(LSU_ALIAS_VS_CSQ, 0x01, 73),
+	PMC_POWERPC_EVENT(LSU_LOAD_HIT_LINE_ALIAS_VS_CSQ0, 0x01, 74),
+	PMC_POWERPC_EVENT(LSU_LOAD_MISS_LINE_ALIAS_VS_CSQ0, 0x01, 75),
+	PMC_POWERPC_EVENT(LSU_TOUCH_LINE_ALIAS_VS_FSQ_WB0_WB1, 0x01, 76),
+	PMC_POWERPC_EVENT(LSU_TOUCH_ALIAS_VS_CSQ, 0x01, 77),
+	PMC_POWERPC_EVENT(LSU_LMQ_FULL_STALL, 0x01, 78),
+	PMC_POWERPC_EVENT(FP_LOAD_INSTR_COMPLETED_IN_LSU, 0x01, 79),
+	PMC_POWERPC_EVENT(FP_LOAD_SINGLE_INSTR_COMPLETED_IN_LSU, 0x01, 80),
+	PMC_POWERPC_EVENT(FP_LOAD_DOUBLE_COMPLETED_IN_LSU, 0x01, 81),
+	PMC_POWERPC_EVENT(LSU_RA_LATCH_STALL, 0x01, 82),
+	PMC_POWERPC_EVENT(LSU_LOAD_VS_STORE_QUEUE_ALIAS_STALL, 0x01, 83),
+	PMC_POWERPC_EVENT(LSU_LMQ_INDEX_ALIAS, 0x01, 84),
+	PMC_POWERPC_EVENT(LSU_STORE_QUEUE_INDEX_ALIAS, 0x01, 85),
+	PMC_POWERPC_EVENT(LSU_CSQ_FORWARDING, 0x01, 86),
+	PMC_POWERPC_EVENT(LSU_MISALIGNED_LOAD_FINISH, 0x01, 87),
+	PMC_POWERPC_EVENT(LSU_MISALIGN_STORE_COMPLETED, 0x01, 88),
+	PMC_POWERPC_EVENT(LSU_MISALIGN_STALL, 0x01, 89),
+	PMC_POWERPC_EVENT(FP_ONE_QUARTER_FPSCR_RENAMES_BUSY, 0x01, 90),
+	PMC_POWERPC_EVENT(FP_ONE_HALF_FPSCR_RENAMES_BUSY, 0x01, 91),
+	PMC_POWERPC_EVENT(FP_THREE_QUARTERS_FPSCR_RENAMES_BUSY, 0x01, 92),
+	PMC_POWERPC_EVENT(FP_ALL_FPSCR_RENAMES_BUSY, 0x01, 93),
+	PMC_POWERPC_EVENT(FP_DENORMALIZED_RESULT, 0x01, 94),
+	PMC_POWERPC_EVENT(L1_DATA_TOTAL_MISSES, 0x02, 23),
+	PMC_POWERPC_EVENT(DISPATCHES_TO_FPR_ISSUE_QUEUE, 0x02, 24),
+	PMC_POWERPC_EVENT(LSU_INSTR_COMPLETED, 0x02, 25),
+	PMC_POWERPC_EVENT(LOAD_INSTR_COMPLETED, 0x02, 26),
+	PMC_POWERPC_EVENT(SS_SM_INSTR_COMPLETED, 0x02, 27),
+	PMC_POWERPC_EVENT(TLBIE_INSTR_COMPLETED, 0x02, 28),
+	PMC_POWERPC_EVENT(LWARX_INSTR_COMPLETED, 0x02, 29),
+	PMC_POWERPC_EVENT(MFSPR_INSTR_COMPLETED, 0x02, 30),
+	PMC_POWERPC_EVENT(REFETCH_SERIALIZATION, 0x02, 31),
+	PMC_POWERPC_EVENT(COMPLETION_QUEUE_ENTRIES_OVER_THRESHOLD, 0x02, 32),
+	PMC_POWERPC_EVENT(CYCLES_ONE_INSTR_DISPATCHED, 0x02, 33),
+	PMC_POWERPC_EVENT(CYCLES_TWO_INSTR_COMPLETED, 0x02, 34),
+	PMC_POWERPC_EVENT(ITLB_NON_SPECULATIVE_MISSES, 0x02, 35),
+	PMC_POWERPC_EVENT(CYCLES_WAITING_FROM_L1_INSTR_CACHE_MISS, 0x02, 36),
+	PMC_POWERPC_EVENT(L1_DATA_LOAD_ACCESS_MISS, 0x02, 37),
+	PMC_POWERPC_EVENT(L1_DATA_TOUCH_MISS, 0x02, 38),
+	PMC_POWERPC_EVENT(L1_DATA_STORE_MISS, 0x02, 39),
+	PMC_POWERPC_EVENT(L1_DATA_TOUCH_MISS_CYCLES, 0x02, 40),
+	PMC_POWERPC_EVENT(L1_DATA_CYCLES_USED, 0x02, 41),
+	PMC_POWERPC_EVENT(DST_STREAM_1_CACHE_LINE_FETCHES, 0x02, 42),
+	PMC_POWERPC_EVENT(VTQ_STREAM_CANCELED_PREMATURELY, 0x02, 43),
+	PMC_POWERPC_EVENT(VTQ_RESUMES_DUE_TO_CTX_CHANGE, 0x02, 44),
+	PMC_POWERPC_EVENT(VTQ_LINE_FETCH_MISS, 0x02, 45),
+	PMC_POWERPC_EVENT(VTQ_LINE_FETCH, 0x02, 46),
+	PMC_POWERPC_EVENT(TLBIE_SNOOPS, 0x02, 47),
+	PMC_POWERPC_EVENT(L1_INSTR_CACHE_RELOADS, 0x02, 48),
+	PMC_POWERPC_EVENT(L1_DATA_CACHE_RELOADS, 0x02, 49),
+	PMC_POWERPC_EVENT(L1_DATA_CACHE_CASTOUTS_TO_L2, 0x02, 50),
+	PMC_POWERPC_EVENT(STORE_MERGE_GATHER, 0x02, 51),
+	PMC_POWERPC_EVENT(CACHEABLE_STORE_MERGE_TO_32_BYTES, 0x02, 52),
+	PMC_POWERPC_EVENT(DATA_BKPT_MATCHES, 0x02, 53),
+	PMC_POWERPC_EVENT(FALL_THROUGH_BRANCHES_PROCESSED, 0x02, 54),
+	PMC_POWERPC_EVENT(FIRST_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY, 0x02, 55),
+	PMC_POWERPC_EVENT(SECOND_SPECULATION_BUFFER_ACTIVE, 0x02, 56),
+	PMC_POWERPC_EVENT(BPU_STALL_ON_LR_DEPENDENCY, 0x02, 57),
+	PMC_POWERPC_EVENT(BTIC_MISS, 0x02, 58),
+	PMC_POWERPC_EVENT(BRANCH_LINK_STACK_CORRECTLY_RESOLVED, 0x02, 59),
+	PMC_POWERPC_EVENT(FPR_ISSUE_STALLED, 0x02, 60),
+	PMC_POWERPC_EVENT(SWITCHES_BETWEEN_PRIV_USER, 0x02, 61),
+	PMC_POWERPC_EVENT(LSU_COMPLETES_FP_STORE_SINGLE, 0x02, 62),
+	PMC_POWERPC_EVENT(CYCLES_TWO_INSTR_COMPLETED, 0x04, 8),
+	PMC_POWERPC_EVENT(CYCLES_ONE_INSTR_DISPATCHED, 0x04, 9),
+	PMC_POWERPC_EVENT(VR_ISSUE_QUEUE_DISPATCHES, 0x04, 10),
+	PMC_POWERPC_EVENT(VR_STALLS, 0x04, 11),
+	PMC_POWERPC_EVENT(GPR_RENAME_BUFFER_ENTRIES_OVER_THRESHOLD, 0x04, 12),
+	PMC_POWERPC_EVENT(FPR_ISSUE_QUEUE_ENTRIES, 0x04, 13),
+	PMC_POWERPC_EVENT(FPU_INSTR_COMPLETED, 0x04, 14),
+	PMC_POWERPC_EVENT(STWCX_INSTR_COMPLETED, 0x04, 15),
+	PMC_POWERPC_EVENT(LS_LM_INSTR_PIECES, 0x04, 16),
+	PMC_POWERPC_EVENT(ITLB_HW_SEARCH_CYCLES_OVER_THRESHOLD, 0x04, 17),
+	PMC_POWERPC_EVENT(DTLB_MISSES, 0x04, 18),
+	PMC_POWERPC_EVENT(CANCELLED_L1_INSTR_CACHE_MISSES, 0x04, 19),
+	PMC_POWERPC_EVENT(L1_DATA_CACHE_OP_HIT, 0x04, 20),
+	PMC_POWERPC_EVENT(L1_DATA_LOAD_MISS_CYCLES, 0x04, 21),
+	PMC_POWERPC_EVENT(L1_DATA_PUSHES, 0x04, 22),
+	PMC_POWERPC_EVENT(L1_DATA_TOTAL_MISS, 0x04, 23),
+	PMC_POWERPC_EVENT(VT2_FETCHES, 0x04, 24),
+	PMC_POWERPC_EVENT(TAKEN_BRANCHES_PROCESSED, 0x04, 25),
+	PMC_POWERPC_EVENT(BRANCH_FLUSHES, 0x04, 26),
+	PMC_POWERPC_EVENT(SECOND_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY, 0x04, 27),
+	PMC_POWERPC_EVENT(THIRD_SPECULATION_BUFFER_ACTIVE, 0x04, 28),
+	PMC_POWERPC_EVENT(BRANCH_UNIT_STALL_ON_CTR_DEPENDENCY, 0x04, 29),
+	PMC_POWERPC_EVENT(FAST_BTIC_HIT, 0x04, 30),
+	PMC_POWERPC_EVENT(BRANCH_LINK_STACK_MISPREDICTED, 0x04, 31),
+	PMC_POWERPC_EVENT(CYCLES_THREE_INSTR_COMPLETED, 0x08, 14),
+	PMC_POWERPC_EVENT(CYCLES_NO_INSTR_DISPATCHED, 0x08, 15),
+	PMC_POWERPC_EVENT(GPR_ISSUE_QUEUE_ENTRIES_OVER_THRESHOLD, 0x08, 16),
+	PMC_POWERPC_EVENT(GPR_ISSUE_QUEUE_STALLED, 0x08, 17),
+	PMC_POWERPC_EVENT(IU1_INSTR_COMPLETED, 0x08, 18),
+	PMC_POWERPC_EVENT(DSSALL_INSTR_COMPLETED, 0x08, 19),
+	PMC_POWERPC_EVENT(TLBSYNC_INSTR_COMPLETED, 0x08, 20),
+	PMC_POWERPC_EVENT(SYNC_INSTR_COMPLETED, 0x08, 21),
+	PMC_POWERPC_EVENT(SS_SM_INSTR_PIECES, 0x08, 22),
+	PMC_POWERPC_EVENT(DTLB_HW_SEARCH_CYCLES, 0x08, 23),
+	PMC_POWERPC_EVENT(SNOOP_RETRIES, 0x08, 24),
+	PMC_POWERPC_EVENT(SUCCESSFUL_STWCX, 0x08, 25),
+	PMC_POWERPC_EVENT(DST_STREAM_3_CACHE_LINE_FETCHES, 0x08, 26),
+	PMC_POWERPC_EVENT(THIRD_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY, 0x08, 27),
+	PMC_POWERPC_EVENT(MISPREDICTED_BRANCHES, 0x08, 28),
+	PMC_POWERPC_EVENT(FOLDED_BRANCHES, 0x08, 29),
+	PMC_POWERPC_EVENT(FP_STORE_DOUBLE_COMPLETES_IN_LSU, 0x08, 30),
+	PMC_POWERPC_EVENT(L2_CACHE_HITS, 0x30, 2),
+	PMC_POWERPC_EVENT(L3_CACHE_HITS, 0x30, 3),
+	PMC_POWERPC_EVENT(L2_INSTR_CACHE_MISSES, 0x30, 4),
+	PMC_POWERPC_EVENT(L3_INSTR_CACHE_MISSES, 0x30, 5),
+	PMC_POWERPC_EVENT(L2_DATA_CACHE_MISSES, 0x30, 6),
+	PMC_POWERPC_EVENT(L3_DATA_CACHE_MISSES, 0x30, 7),
+	PMC_POWERPC_EVENT(L2_LOAD_HITS, 0x10, 8),
+	PMC_POWERPC_EVENT(L2_STORE_HITS, 0x10, 9),
+	PMC_POWERPC_EVENT(L3_LOAD_HITS, 0x10, 10),
+	PMC_POWERPC_EVENT(L3_STORE_HITS, 0x10, 11),
+	PMC_POWERPC_EVENT(L2_TOUCH_HITS, 0x30, 13),
+	PMC_POWERPC_EVENT(L3_TOUCH_HITS, 0x30, 14),
+	PMC_POWERPC_EVENT(SNOOP_RETRIES, 0x30, 15),
+	PMC_POWERPC_EVENT(SNOOP_MODIFIED, 0x10, 16),
+	PMC_POWERPC_EVENT(SNOOP_VALID, 0x10, 17),
+	PMC_POWERPC_EVENT(INTERVENTION, 0x30, 18),
+	PMC_POWERPC_EVENT(L2_CACHE_MISSES, 0x10, 19),
+	PMC_POWERPC_EVENT(L3_CACHE_MISSES, 0x10, 20),
+	PMC_POWERPC_EVENT(L2_CACHE_CASTOUTS, 0x20, 8),
+	PMC_POWERPC_EVENT(L3_CACHE_CASTOUTS, 0x20, 9),
+	PMC_POWERPC_EVENT(L2SQ_FULL_CYCLES, 0x20, 10),
+	PMC_POWERPC_EVENT(L3SQ_FULL_CYCLES, 0x20, 11),
+	PMC_POWERPC_EVENT(RAQ_FULL_CYCLES, 0x20, 16),
+	PMC_POWERPC_EVENT(WAQ_FULL_CYCLES, 0x20, 17),
+	PMC_POWERPC_EVENT(L1_EXTERNAL_INTERVENTIONS, 0x20, 19),
+	PMC_POWERPC_EVENT(L2_EXTERNAL_INTERVENTIONS, 0x20, 20),
+	PMC_POWERPC_EVENT(L3_EXTERNAL_INTERVENTIONS, 0x20, 21),
+	PMC_POWERPC_EVENT(EXTERNAL_INTERVENTIONS, 0x20, 22),
+	PMC_POWERPC_EVENT(EXTERNAL_PUSHES, 0x20, 23),
+	PMC_POWERPC_EVENT(EXTERNAL_SNOOP_RETRY, 0x20, 24),
+	PMC_POWERPC_EVENT(DTQ_FULL_CYCLES, 0x20, 25),
+	PMC_POWERPC_EVENT(BUS_RETRY, 0x20, 26),
+	PMC_POWERPC_EVENT(L2_VALID_REQUEST, 0x20, 27),
+	PMC_POWERPC_EVENT(BORDQ_FULL, 0x20, 28),
+	PMC_POWERPC_EVENT(BUS_TAS_FOR_READS, 0x20, 42),
+	PMC_POWERPC_EVENT(BUS_TAS_FOR_WRITES, 0x20, 43),
+	PMC_POWERPC_EVENT(BUS_READS_NOT_RETRIED, 0x20, 44),
+	PMC_POWERPC_EVENT(BUS_WRITES_NOT_RETRIED, 0x20, 45),
+	PMC_POWERPC_EVENT(BUS_READS_WRITES_NOT_RETRIED, 0x20, 46),
+	PMC_POWERPC_EVENT(BUS_RETRY_DUE_TO_L1_RETRY, 0x20, 47),
+	PMC_POWERPC_EVENT(BUS_RETRY_DUE_TO_PREVIOUS_ADJACENT, 0x20, 48),
+	PMC_POWERPC_EVENT(BUS_RETRY_DUE_TO_COLLISION, 0x20, 49),
+	PMC_POWERPC_EVENT(BUS_RETRY_DUE_TO_INTERVENTION_ORDERING, 0x20, 50),
+	PMC_POWERPC_EVENT(SNOOP_REQUESTS, 0x20, 51),
+	PMC_POWERPC_EVENT(PREFETCH_ENGINE_REQUEST, 0x20, 52),
+	PMC_POWERPC_EVENT(PREFETCH_ENGINE_COLLISION_VS_LOAD, 0x20, 53),
+	PMC_POWERPC_EVENT(PREFETCH_ENGINE_COLLISION_VS_STORE, 0x20, 54),
+	PMC_POWERPC_EVENT(PREFETCH_ENGINE_COLLISION_VS_INSTR_FETCH, 0x20, 55),
+	PMC_POWERPC_EVENT(PREFETCH_ENGINE_COLLISION_VS_LOAD_STORE_INSTR_FETCH, 0x20, 56),
+	PMC_POWERPC_EVENT(PREFETCH_ENGINE_FULL, 0x20, 57)
+};
+
+const size_t powerpc_event_codes_size = 
+	sizeof(powerpc_event_codes) / sizeof(powerpc_event_codes[0]);
 
 int
 pmc_save_kernel_callchain(uintptr_t *cc, int maxsamples,
@@ -55,6 +333,515 @@ pmc_save_kernel_callchain(uintptr_t *cc, int maxsamples,
 	return (0);
 }
 
+static pmc_value_t
+powerpc_pmcn_read(unsigned int pmc)
+{
+	switch (pmc) {
+		case 0:
+			return mfspr(SPR_PMC1);
+			break;
+		case 1:
+			return mfspr(SPR_PMC2);
+			break;
+		case 2:
+			return mfspr(SPR_PMC3);
+			break;
+		case 3:
+			return mfspr(SPR_PMC4);
+			break;
+		case 4:
+			return mfspr(SPR_PMC5);
+			break;
+		case 5:
+			return mfspr(SPR_PMC6);
+		default:
+			panic("Invalid PMC number: %d\n", pmc);
+	}
+}
+
+static void
+powerpc_pmcn_write(unsigned int pmc, uint32_t val)
+{
+	switch (pmc) {
+		case 0:
+			mtspr(SPR_PMC1, val);
+			break;
+		case 1:
+			mtspr(SPR_PMC2, val);
+			break;
+		case 2:
+			mtspr(SPR_PMC3, val);
+			break;
+		case 3:
+			mtspr(SPR_PMC4, val);
+			break;
+		case 4:
+			mtspr(SPR_PMC5, val);
+			break;
+		case 5:
+			mtspr(SPR_PMC6, val);
+			break;
+		default:
+			panic("Invalid PMC number: %d\n", pmc);
+	}
+}
+
+static int
+powerpc_allocate_pmc(int cpu, int ri, struct pmc *pm,
+  const struct pmc_op_pmcallocate *a)
+{
+	enum pmc_event pe;
+	uint32_t caps, config, counter;
+	int i;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[powerpc,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < PPC_MAX_PMCS,
+	    ("[powerpc,%d] illegal row index %d", __LINE__, ri));
+
+	caps = a->pm_caps;
+
+	/*
+	 * TODO: Check actual class for different generations.
+	 */
+	if (a->pm_class != PMC_CLASS_PPC7450)
+		return (EINVAL);
+	pe = a->pm_ev;
+	for (i = 0; i < powerpc_event_codes_size; i++) {
+		if (powerpc_event_codes[i].pe_ev == pe) {
+			config = powerpc_event_codes[i].pe_code;
+			counter =  powerpc_event_codes[i].pe_counter_mask;
+			break;
+		}
+	}
+	if (i == powerpc_event_codes_size)
+		return (EINVAL);
+
+	if ((counter & (1 << ri)) == 0)
+		return (EINVAL);
+
+	if (caps & PMC_CAP_SYSTEM)
+		config |= POWERPC_PMC_KERNEL_ENABLE;
+	if (caps & PMC_CAP_USER)
+		config |= POWERPC_PMC_USER_ENABLE;
+	if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
+		config |= POWERPC_PMC_ENABLE;
+
+	pm->pm_md.pm_powerpc.pm_powerpc_evsel = config;
+
+	PMCDBG(MDP,ALL,2,"powerpc-allocate ri=%d -> config=0x%x", ri, config);
+
+	return 0;
+}
+
+static int
+powerpc_read_pmc(int cpu, int ri, pmc_value_t *v)
+{
+	struct pmc *pm;
+	pmc_value_t tmp;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[powerpc,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < PPC_MAX_PMCS,
+	    ("[powerpc,%d] illegal row index %d", __LINE__, ri));
+
+	pm  = powerpc_pcpu[cpu]->pc_ppcpmcs[ri].phw_pmc;
+	tmp = powerpc_pmcn_read(ri);
+	PMCDBG(MDP,REA,2,"ppc-read id=%d -> %jd", ri, tmp);
+	if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
+		*v = POWERPC_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
+	else
+		*v = tmp;
+
+	return 0;
+}
+
+static int
+powerpc_write_pmc(int cpu, int ri, pmc_value_t v)
+{
+	struct pmc *pm;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[powerpc,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < PPC_MAX_PMCS,
+	    ("[powerpc,%d] illegal row-index %d", __LINE__, ri));
+
+	pm  = powerpc_pcpu[cpu]->pc_ppcpmcs[ri].phw_pmc;
+
+	if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
+		v = POWERPC_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
+	
+	PMCDBG(MDP,WRI,1,"powerpc-write cpu=%d ri=%d v=%jx", cpu, ri, v);
+
+	powerpc_pmcn_write(ri, v);
+
+	return 0;
+}
+
+static int
+powerpc_config_pmc(int cpu, int ri, struct pmc *pm)
+{
+	struct pmc_hw *phw;
+
+	PMCDBG(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[powerpc,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < PPC_MAX_PMCS,
+	    ("[powerpc,%d] illegal row-index %d", __LINE__, ri));
+
+	phw = &powerpc_pcpu[cpu]->pc_ppcpmcs[ri];
+
+	KASSERT(pm == NULL || phw->phw_pmc == NULL,
+	    ("[powerpc,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
+	    __LINE__, pm, phw->phw_pmc));
+
+	phw->phw_pmc = pm;
+
+	return 0;
+}
+
+static int
+powerpc_start_pmc(int cpu, int ri)
+{
+	uint32_t config;
+        struct pmc *pm;
+        struct pmc_hw *phw;
+	register_t pmc_mmcr;
+
+	phw    = &powerpc_pcpu[cpu]->pc_ppcpmcs[ri];
+	pm     = phw->phw_pmc;
+	config = pm->pm_md.pm_powerpc.pm_powerpc_evsel & ~POWERPC_PMC_ENABLE;
+
+	/* Enable the PMC. */
+	switch (ri) {
+	case 0:
+		pmc_mmcr = mfspr(SPR_MMCR0);
+		pmc_mmcr = PPC_SET_PMC1SEL(pmc_mmcr, config);
+		mtspr(SPR_MMCR0, pmc_mmcr);
+		break;
+	case 1:
+		pmc_mmcr = mfspr(SPR_MMCR0);
+		pmc_mmcr = PPC_SET_PMC2SEL(pmc_mmcr, config);
+		mtspr(SPR_MMCR0, pmc_mmcr);
+		break;
+	case 2:
+		pmc_mmcr = mfspr(SPR_MMCR1);
+		pmc_mmcr = PPC_SET_PMC3SEL(pmc_mmcr, config);
+		mtspr(SPR_MMCR1, pmc_mmcr);
+		break;
+	case 3:
+		pmc_mmcr = mfspr(SPR_MMCR0);
+		pmc_mmcr = PPC_SET_PMC4SEL(pmc_mmcr, config);
+		mtspr(SPR_MMCR0, pmc_mmcr);
+		break;
+	case 4:
+		pmc_mmcr = mfspr(SPR_MMCR1);
+		pmc_mmcr = PPC_SET_PMC5SEL(pmc_mmcr, config);
+		mtspr(SPR_MMCR1, pmc_mmcr);
+		break;
+	case 5:
+		pmc_mmcr = mfspr(SPR_MMCR1);
+		pmc_mmcr = PPC_SET_PMC6SEL(pmc_mmcr, config);
+		mtspr(SPR_MMCR1, pmc_mmcr);
+		break;
+	default:
+		break;
+	}
+	
+	/* The mask is inverted (enable is 1) compared to the flags in MMCR0, which
+	 * are Freeze flags.
+	 */
+	config = ~pm->pm_md.pm_powerpc.pm_powerpc_evsel & POWERPC_PMC_ENABLE;
+
+	pmc_mmcr = mfspr(SPR_MMCR0);
+	pmc_mmcr &= ~SPR_MMCR0_FC;
+	pmc_mmcr |= config;
+	mtspr(SPR_MMCR0, pmc_mmcr);
+
+	return 0;
+}
+
+static int
+powerpc_stop_pmc(int cpu, int ri)
+{
+        struct pmc *pm;
+        struct pmc_hw *phw;
+        register_t pmc_mmcr;
+
+	phw    = &powerpc_pcpu[cpu]->pc_ppcpmcs[ri];
+	pm     = phw->phw_pmc;
+
+	/*
+	 * Disable the PMCs.
+	 */
+	switch (ri) {
+	case 0:
+		pmc_mmcr = mfspr(SPR_MMCR0);
+		pmc_mmcr = PPC_SET_PMC1SEL(pmc_mmcr, 0);
+		mtspr(SPR_MMCR0, pmc_mmcr);
+		break;
+	case 1:
+		pmc_mmcr = mfspr(SPR_MMCR0);
+		pmc_mmcr = PPC_SET_PMC2SEL(pmc_mmcr, 0);
+		mtspr(SPR_MMCR0, pmc_mmcr);
+		break;
+	case 2:
+		pmc_mmcr = mfspr(SPR_MMCR1);
+		pmc_mmcr = PPC_SET_PMC3SEL(pmc_mmcr, 0);
+		mtspr(SPR_MMCR1, pmc_mmcr);
+		break;
+	case 3:
+		pmc_mmcr = mfspr(SPR_MMCR0);
+		pmc_mmcr = PPC_SET_PMC4SEL(pmc_mmcr, 0);
+		mtspr(SPR_MMCR0, pmc_mmcr);
+		break;
+	case 4:
+		pmc_mmcr = mfspr(SPR_MMCR1);
+		pmc_mmcr = PPC_SET_PMC5SEL(pmc_mmcr, 0);
+		mtspr(SPR_MMCR1, pmc_mmcr);
+		break;
+	case 5:
+		pmc_mmcr = mfspr(SPR_MMCR1);
+		pmc_mmcr = PPC_SET_PMC6SEL(pmc_mmcr, 0);
+		mtspr(SPR_MMCR1, pmc_mmcr);
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
+static int
+powerpc_release_pmc(int cpu, int ri, struct pmc *pmc)
+{
+	struct pmc_hw *phw;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[powerpc,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < PPC_MAX_PMCS,
+	    ("[powerpc,%d] illegal row-index %d", __LINE__, ri));
+
+	phw = &powerpc_pcpu[cpu]->pc_ppcpmcs[ri];
+	KASSERT(phw->phw_pmc == NULL,
+	    ("[powerpc,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
+
+	return 0;
+}
+
+static int
+powerpc_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
+{
+	return 0;
+}
+
+static int
+powerpc_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
+{
+	return 0;
+}
+
+static int
+powerpc_intr(int cpu, struct trapframe *tf)
+{
+	int i, error, retval;
+	uint32_t config;
+	struct pmc *pm;
+	struct powerpc_cpu *pac;
+	pmc_value_t v;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[powerpc,%d] out of range CPU %d", __LINE__, cpu));
+
+	PMCDBG(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *) tf,
+	    TRAPF_USERMODE(tf));
+
+	retval = 0;
+
+	pac = powerpc_pcpu[cpu];
+
+	/*
+	 * look for all PMCs that have interrupted:
+	 * - look for a running, sampling PMC which has overflowed
+	 *   and which has a valid 'struct pmc' association
+	 *
+	 * If found, we call a helper to process the interrupt.
+	 */
+
+	for (i = 0; i < PPC_MAX_PMCS; i++) {
+		if ((pm = pac->pc_ppcpmcs[i].phw_pmc) == NULL ||
+		    !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) {
+			continue;
+		}
+
+		if (!POWERPC_PMC_HAS_OVERFLOWED(i))
+			continue;
+
+		retval = 1;	/* Found an interrupting PMC. */
+
+		if (pm->pm_state != PMC_STATE_RUNNING)
+			continue;
+
+		/* Stop the PMC, reload count. */
+		v       = pm->pm_sc.pm_reloadcount;
+		config  = mfspr(SPR_MMCR0);
+
+		mtspr(SPR_MMCR0, config | SPR_MMCR0_FC);
+		powerpc_pmcn_write(i, v);
+
+		/* Restart the counter if logging succeeded. */
+		error = pmc_process_interrupt(cpu, pm, tf, TRAPF_USERMODE(tf));
+		mtspr(SPR_MMCR0, config);
+		if (error != 0)
+			powerpc_stop_pmc(cpu, i);
+		atomic_add_int(retval ? &pmc_stats.pm_intr_processed :
+				&pmc_stats.pm_intr_ignored, 1);
+
+	}
+
+	/* Re-enable PERF exceptions. */
+	mtspr(SPR_MMCR0, mfspr(SPR_MMCR0) | SPR_MMCR0_PMXE);
+
+	return (retval);
+}
+
+static int
+powerpc_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
+{
+	int error;
+	struct pmc_hw *phw;
+	char powerpc_name[PMC_NAME_MAX];
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[powerpc,%d], illegal CPU %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < PPC_MAX_PMCS,
+	    ("[powerpc,%d] row-index %d out of range", __LINE__, ri));
+
+	phw = &powerpc_pcpu[cpu]->pc_ppcpmcs[ri];
+	snprintf(powerpc_name, sizeof(powerpc_name), "POWERPC-%d", ri);
+	if ((error = copystr(powerpc_name, pi->pm_name, PMC_NAME_MAX,
+	    NULL)) != 0)
+		return error;
+	pi->pm_class = PMC_CLASS_PPC7450;
+	if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
+		pi->pm_enabled = TRUE;
+		*ppmc          = phw->phw_pmc;
+	} else {
+		pi->pm_enabled = FALSE;
+		*ppmc	       = NULL;
+	}
+
+	return (0);
+}
+
+static int
+powerpc_get_config(int cpu, int ri, struct pmc **ppm)
+{
+	*ppm = powerpc_pcpu[cpu]->pc_ppcpmcs[ri].phw_pmc;
+
+	return 0;
+}
+
+static int
+powerpc_pcpu_init(struct pmc_mdep *md, int cpu)
+{
+	int first_ri, i;
+	struct pmc_cpu *pc;
+	struct powerpc_cpu *pac;
+	struct pmc_hw  *phw;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[powerpc,%d] wrong cpu number %d", __LINE__, cpu));
+	PMCDBG(MDP,INI,1,"powerpc-init cpu=%d", cpu);
+
+	powerpc_pcpu[cpu] = pac = malloc(sizeof(struct powerpc_cpu), M_PMC,
+	    M_WAITOK|M_ZERO);
+	pac->pc_ppcpmcs = malloc(sizeof(struct pmc_hw) * PPC_MAX_PMCS,
+	    M_PMC, M_WAITOK|M_ZERO);
+	pc = pmc_pcpu[cpu];
+	first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_PPC7450].pcd_ri;
+	KASSERT(pc != NULL, ("[powerpc,%d] NULL per-cpu pointer", __LINE__));
+
+	for (i = 0, phw = pac->pc_ppcpmcs; i < PPC_MAX_PMCS; i++, phw++) {
+		phw->phw_state    = PMC_PHW_FLAG_IS_ENABLED |
+		    PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i);
+		phw->phw_pmc      = NULL;
+		pc->pc_hwpmcs[i + first_ri] = phw;
+	}
+
+	/* Clear the MMCRs, and set FC, to disable all PMCs. */
+	mtspr(SPR_MMCR0, SPR_MMCR0_FC | SPR_MMCR0_PMXE | SPR_MMCR0_PMC1CE | SPR_MMCR0_PMCNCE);
+	mtspr(SPR_MMCR1, 0);
+
+	return 0;
+}
+
+static int
+powerpc_pcpu_fini(struct pmc_mdep *md, int cpu)
+{
+	uint32_t mmcr0 = mfspr(SPR_MMCR0);
+
+	mmcr0 |= SPR_MMCR0_FC;
+	mtspr(SPR_MMCR0, mmcr0);
+	free(powerpc_pcpu[cpu]->pc_ppcpmcs, M_PMC);
+	free(powerpc_pcpu[cpu], M_PMC);
+	return 0;
+}
+
+struct pmc_mdep *
+pmc_md_initialize()
+{
+	struct pmc_mdep *pmc_mdep;
+	struct pmc_classdep *pcd;
+	
+	/*
+	 * Allocate space for pointers to PMC HW descriptors and for
+	 * the MDEP structure used by MI code.
+	 */
+	powerpc_pcpu = malloc(sizeof(struct powerpc_cpu *) * pmc_cpu_max(), M_PMC,
+			   M_WAITOK|M_ZERO);
+
+	/* Just one class */
+	pmc_mdep = malloc(sizeof(struct pmc_mdep) + sizeof(struct pmc_classdep),
+			  M_PMC, M_WAITOK|M_ZERO);
+
+	pmc_mdep->pmd_cputype = PMC_CPU_PPC_7450;
+	pmc_mdep->pmd_nclass  = 1;
+
+	pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_PPC7450];
+	pcd->pcd_caps  = POWERPC_PMC_CAPS;
+	pcd->pcd_class = PMC_CLASS_PPC7450;
+	pcd->pcd_num   = PPC_MAX_PMCS;
+	pcd->pcd_ri    = pmc_mdep->pmd_npmc;
+	pcd->pcd_width = 32;	/* All PMCs, even in ppc970, are 32-bit */
+
+	pcd->pcd_allocate_pmc   = powerpc_allocate_pmc;
+	pcd->pcd_config_pmc     = powerpc_config_pmc;
+	pcd->pcd_pcpu_fini      = powerpc_pcpu_fini;
+	pcd->pcd_pcpu_init      = powerpc_pcpu_init;
+	pcd->pcd_describe       = powerpc_describe;
+	pcd->pcd_get_config	= powerpc_get_config;
+	pcd->pcd_read_pmc       = powerpc_read_pmc;
+	pcd->pcd_release_pmc    = powerpc_release_pmc;
+	pcd->pcd_start_pmc      = powerpc_start_pmc;
+	pcd->pcd_stop_pmc       = powerpc_stop_pmc;
+ 	pcd->pcd_write_pmc      = powerpc_write_pmc;
+
+	pmc_mdep->pmd_intr       = powerpc_intr;
+	pmc_mdep->pmd_switch_in  = powerpc_switch_in;
+	pmc_mdep->pmd_switch_out = powerpc_switch_out;
+	
+	pmc_mdep->pmd_npmc   += PPC_MAX_PMCS;
+
+	return (pmc_mdep);
+}
+
+void
+pmc_md_finalize(struct pmc_mdep *md)
+{
+	free(md, M_PMC);
+}
+
 int
 pmc_save_user_callchain(uintptr_t *cc, int maxsamples,
     struct trapframe *tf)
diff --git a/sys/dev/hwpmc/pmc_events.h b/sys/dev/hwpmc/pmc_events.h
index 9fcf926..347e833 100644
--- a/sys/dev/hwpmc/pmc_events.h
+++ b/sys/dev/hwpmc/pmc_events.h
@@ -3093,6 +3093,231 @@ __PMC_EV_ALIAS("CYCLES_UNHALTED_L3_FLL_DISABLE", UCP_EVENT_86H_01H)
 #define	PMC_EV_MIPS24K_FIRST	PMC_EV_MIPS24K_CYCLE
 #define	PMC_EV_MIPS24K_LAST	PMC_EV_MIPS24K_WBB_FULL_PIPELINE_STALLS
 
+#define __PMC_EV_PPC7450() \
+	__PMC_EV(PPC7450, CYCLE)	\
+	__PMC_EV(PPC7450, INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, TLB_BIT_TRANSITIONS)	\
+	__PMC_EV(PPC7450, INSTR_DISPATCHED)	\
+	__PMC_EV(PPC7450, PMON_EXCEPT) \
+	__PMC_EV(PPC7450, PMON_SIG) \
+	__PMC_EV(PPC7450, VPU_INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, VFPU_INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, VIU1_INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, VIU2_INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, MTVSCR_INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, MTVRSAVE_INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, VPU_INSTR_WAIT_CYCLES)	\
+	__PMC_EV(PPC7450, VFPU_INSTR_WAIT_CYCLES)	\
+	__PMC_EV(PPC7450, VIU1_INSTR_WAIT_CYCLES)	\
+	__PMC_EV(PPC7450, VIU2_INSTR_WAIT_CYCLES)	\
+	__PMC_EV(PPC7450, MFVSCR_SYNC_CYCLES)	\
+	__PMC_EV(PPC7450, VSCR_SAT_SET)	\
+	__PMC_EV(PPC7450, STORE_INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, L1_INSTR_CACHE_MISSES)	\
+	__PMC_EV(PPC7450, L1_DATA_SNOOPS)	\
+	__PMC_EV(PPC7450, UNRESOLVED_BRANCHES)	\
+	__PMC_EV(PPC7450, SPEC_BUFFER_CYCLES)	\
+	__PMC_EV(PPC7450, BRANCH_UNIT_STALL_CYCLES)	\
+	__PMC_EV(PPC7450, TRUE_BRANCH_TARGET_HITS)	\
+	__PMC_EV(PPC7450, BRANCH_LINK_STAC_PREDICTED)	\
+	__PMC_EV(PPC7450, GPR_ISSUE_QUEUE_DISPATCHES)	\
+	__PMC_EV(PPC7450, CYCLES_THREE_INSTR_DISPATCHED)	\
+	__PMC_EV(PPC7450, THRESHOLD_INSTR_QUEUE_ENTRIES_CYCLES)	\
+	__PMC_EV(PPC7450, THRESHOLD_VEC_INSTR_QUEUE_ENTRIES_CYCLES)	\
+	__PMC_EV(PPC7450, CYCLES_NO_COMPLETED_INSTRS)	\
+	__PMC_EV(PPC7450, IU2_INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, BRANCHES_COMPLETED)	\
+	__PMC_EV(PPC7450, EIEIO_INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, MTSPR_INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, SC_INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, LS_LM_COMPLETED)	\
+	__PMC_EV(PPC7450, ITLB_HW_TABLE_SEARCH_CYCLES)	\
+	__PMC_EV(PPC7450, DTLB_HW_SEARCH_CYCLES_OVER_THRESHOLD)	\
+	__PMC_EV(PPC7450, L1_INSTR_CACHE_ACCESSES)	\
+	__PMC_EV(PPC7450, INSTR_BKPT_MATCHES)	\
+	__PMC_EV(PPC7450, L1_DATA_CACHE_LOAD_MISS_CYCLES_OVER_THRESHOLD)	\
+	__PMC_EV(PPC7450, L1_DATA_SNOOP_HIT_ON_MODIFIED) \
+	__PMC_EV(PPC7450, LOAD_MISS_ALIAS)	\
+	__PMC_EV(PPC7450, LOAD_MISS_ALIAS_ON_TOUCH)	\
+	__PMC_EV(PPC7450, TOUCH_ALIAS)	\
+	__PMC_EV(PPC7450, L1_DATA_SNOOP_HIT_CASTOUT_QUEUE)	\
+	__PMC_EV(PPC7450, L1_DATA_SNOOP_HIT_CASTOUT)	\
+	__PMC_EV(PPC7450, L1_DATA_SNOOP_HITS)	\
+	__PMC_EV(PPC7450, WRITE_THROUGH_STORES)	\
+	__PMC_EV(PPC7450, CACHE_INHIBITED_STORES)	\
+	__PMC_EV(PPC7450, L1_DATA_LOAD_HIT)	\
+	__PMC_EV(PPC7450, L1_DATA_TOUCH_HIT)	\
+	__PMC_EV(PPC7450, L1_DATA_STORE_HIT)	\
+	__PMC_EV(PPC7450, L1_DATA_TOTAL_HITS)	\
+	__PMC_EV(PPC7450, DST_INSTR_DISPATCHED)	\
+	__PMC_EV(PPC7450, REFRESHED_DSTS)	\
+	__PMC_EV(PPC7450, SUCCESSFUL_DST_TABLE_SEARCHES)	\
+	__PMC_EV(PPC7450, DSS_INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, DST_STREAM_0_CACHE_LINE_FETCHES)	\
+	__PMC_EV(PPC7450, VTQ_SUSPENDS_DUE_TO_CTX_CHANGE)	\
+	__PMC_EV(PPC7450, VTQ_LINE_FETCH_HIT)	\
+	__PMC_EV(PPC7450, VEC_LOAD_INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, FP_STORE_INSTR_COMPLETED_IN_LSU)	\
+	__PMC_EV(PPC7450, FPU_RENORMALIZATION)	\
+	__PMC_EV(PPC7450, FPU_DENORMALIZATION)	\
+	__PMC_EV(PPC7450, FP_STORE_CAUSES_STALL_IN_LSU)	\
+	__PMC_EV(PPC7450, LD_ST_TRUE_ALIAS_STALL)	\
+	__PMC_EV(PPC7450, LSU_INDEXED_ALIAS_STALL)	\
+	__PMC_EV(PPC7450, LSU_ALIAS_VS_FSQ_WB0_WB1)	\
+	__PMC_EV(PPC7450, LSU_ALIAS_VS_CSQ)	\
+	__PMC_EV(PPC7450, LSU_LOAD_HIT_LINE_ALIAS_VS_CSQ0)	\
+	__PMC_EV(PPC7450, LSU_LOAD_MISS_LINE_ALIAS_VS_CSQ0)	\
+	__PMC_EV(PPC7450, LSU_TOUCH_LINE_ALIAS_VS_FSQ_WB0_WB1)	\
+	__PMC_EV(PPC7450, LSU_TOUCH_ALIAS_VS_CSQ)	\
+	__PMC_EV(PPC7450, LSU_LMQ_FULL_STALL)	\
+	__PMC_EV(PPC7450, FP_LOAD_INSTR_COMPLETED_IN_LSU)	\
+	__PMC_EV(PPC7450, FP_LOAD_SINGLE_INSTR_COMPLETED_IN_LSU)	\
+	__PMC_EV(PPC7450, FP_LOAD_DOUBLE_COMPLETED_IN_LSU)	\
+	__PMC_EV(PPC7450, LSU_RA_LATCH_STALL)	\
+	__PMC_EV(PPC7450, LSU_LOAD_VS_STORE_QUEUE_ALIAS_STALL)	\
+	__PMC_EV(PPC7450, LSU_LMQ_INDEX_ALIAS)	\
+	__PMC_EV(PPC7450, LSU_STORE_QUEUE_INDEX_ALIAS)	\
+	__PMC_EV(PPC7450, LSU_CSQ_FORWARDING)	\
+	__PMC_EV(PPC7450, LSU_MISALIGNED_LOAD_FINISH)	\
+	__PMC_EV(PPC7450, LSU_MISALIGN_STORE_COMPLETED)	\
+	__PMC_EV(PPC7450, LSU_MISALIGN_STALL)	\
+	__PMC_EV(PPC7450, FP_ONE_QUARTER_FPSCR_RENAMES_BUSY)	\
+	__PMC_EV(PPC7450, FP_ONE_HALF_FPSCR_RENAMES_BUSY)	\
+	__PMC_EV(PPC7450, FP_THREE_QUARTERS_FPSCR_RENAMES_BUSY)	\
+	__PMC_EV(PPC7450, FP_ALL_FPSCR_RENAMES_BUSY)	\
+	__PMC_EV(PPC7450, FP_DENORMALIZED_RESULT)	\
+	__PMC_EV(PPC7450, L1_DATA_TOTAL_MISSES)	\
+	__PMC_EV(PPC7450, DISPATCHES_TO_FPR_ISSUE_QUEUE)	\
+	__PMC_EV(PPC7450, LSU_INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, LOAD_INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, SS_SM_INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, TLBIE_INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, LWARX_INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, MFSPR_INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, REFETCH_SERIALIZATION)	\
+	__PMC_EV(PPC7450, COMPLETION_QUEUE_ENTRIES_OVER_THRESHOLD)	\
+	__PMC_EV(PPC7450, CYCLES_ONE_INSTR_DISPATCHED)	\
+	__PMC_EV(PPC7450, CYCLES_TWO_INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, ITLB_NON_SPECULATIVE_MISSES)	\
+	__PMC_EV(PPC7450, CYCLES_WAITING_FROM_L1_INSTR_CACHE_MISS)	\
+	__PMC_EV(PPC7450, L1_DATA_LOAD_ACCESS_MISS)	\
+	__PMC_EV(PPC7450, L1_DATA_TOUCH_MISS)	\
+	__PMC_EV(PPC7450, L1_DATA_STORE_MISS)	\
+	__PMC_EV(PPC7450, L1_DATA_TOUCH_MISS_CYCLES)	\
+	__PMC_EV(PPC7450, L1_DATA_CYCLES_USED)	\
+	__PMC_EV(PPC7450, DST_STREAM_1_CACHE_LINE_FETCHES)	\
+	__PMC_EV(PPC7450, VTQ_STREAM_CANCELED_PREMATURELY)	\
+	__PMC_EV(PPC7450, VTQ_RESUMES_DUE_TO_CTX_CHANGE)	\
+	__PMC_EV(PPC7450, VTQ_LINE_FETCH_MISS)	\
+	__PMC_EV(PPC7450, VTQ_LINE_FETCH)	\
+	__PMC_EV(PPC7450, TLBIE_SNOOPS)	\
+	__PMC_EV(PPC7450, L1_INSTR_CACHE_RELOADS)	\
+	__PMC_EV(PPC7450, L1_DATA_CACHE_RELOADS)	\
+	__PMC_EV(PPC7450, L1_DATA_CACHE_CASTOUTS_TO_L2)	\
+	__PMC_EV(PPC7450, STORE_MERGE_GATHER)	\
+	__PMC_EV(PPC7450, CACHEABLE_STORE_MERGE_TO_32_BYTES)	\
+	__PMC_EV(PPC7450, DATA_BKPT_MATCHES)	\
+	__PMC_EV(PPC7450, FALL_THROUGH_BRANCHES_PROCESSED)	\
+	__PMC_EV(PPC7450, FIRST_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY)	\
+	__PMC_EV(PPC7450, SECOND_SPECULATION_BUFFER_ACTIVE)	\
+	__PMC_EV(PPC7450, BPU_STALL_ON_LR_DEPENDENCY)	\
+	__PMC_EV(PPC7450, BTIC_MISS)	\
+	__PMC_EV(PPC7450, BRANCH_LINK_STACK_CORRECTLY_RESOLVED)	\
+	__PMC_EV(PPC7450, FPR_ISSUE_STALLED)	\
+	__PMC_EV(PPC7450, SWITCHES_BETWEEN_PRIV_USER)	\
+	__PMC_EV(PPC7450, LSU_COMPLETES_FP_STORE_SINGLE)	\
+	__PMC_EV(PPC7450, VR_ISSUE_QUEUE_DISPATCHES)	\
+	__PMC_EV(PPC7450, VR_STALLS)	\
+	__PMC_EV(PPC7450, GPR_RENAME_BUFFER_ENTRIES_OVER_THRESHOLD)	\
+	__PMC_EV(PPC7450, FPR_ISSUE_QUEUE_ENTRIES)	\
+	__PMC_EV(PPC7450, FPU_INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, STWCX_INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, LS_LM_INSTR_PIECES)	\
+	__PMC_EV(PPC7450, ITLB_HW_SEARCH_CYCLES_OVER_THRESHOLD)	\
+	__PMC_EV(PPC7450, DTLB_MISSES)	\
+	__PMC_EV(PPC7450, CANCELLED_L1_INSTR_CACHE_MISSES)	\
+	__PMC_EV(PPC7450, L1_DATA_CACHE_OP_HIT)	\
+	__PMC_EV(PPC7450, L1_DATA_LOAD_MISS_CYCLES)	\
+	__PMC_EV(PPC7450, L1_DATA_PUSHES)	\
+	__PMC_EV(PPC7450, L1_DATA_TOTAL_MISS)	\
+	__PMC_EV(PPC7450, VT2_FETCHES)	\
+	__PMC_EV(PPC7450, TAKEN_BRANCHES_PROCESSED)	\
+	__PMC_EV(PPC7450, BRANCH_FLUSHES)	\
+	__PMC_EV(PPC7450, SECOND_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY)	\
+	__PMC_EV(PPC7450, THIRD_SPECULATION_BUFFER_ACTIVE)	\
+	__PMC_EV(PPC7450, BRANCH_UNIT_STALL_ON_CTR_DEPENDENCY)	\
+	__PMC_EV(PPC7450, FAST_BTIC_HIT)	\
+	__PMC_EV(PPC7450, BRANCH_LINK_STACK_MISPREDICTED)	\
+	__PMC_EV(PPC7450, CYCLES_THREE_INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, CYCLES_NO_INSTR_DISPATCHED)	\
+	__PMC_EV(PPC7450, GPR_ISSUE_QUEUE_ENTRIES_OVER_THRESHOLD)	\
+	__PMC_EV(PPC7450, GPR_ISSUE_QUEUE_STALLED)	\
+	__PMC_EV(PPC7450, IU1_INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, DSSALL_INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, TLBSYNC_INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, SYNC_INSTR_COMPLETED)	\
+	__PMC_EV(PPC7450, SS_SM_INSTR_PIECES)	\
+	__PMC_EV(PPC7450, DTLB_HW_SEARCH_CYCLES)	\
+	__PMC_EV(PPC7450, SNOOP_RETRIES)	\
+	__PMC_EV(PPC7450, SUCCESSFUL_STWCX)	\
+	__PMC_EV(PPC7450, DST_STREAM_3_CACHE_LINE_FETCHES)	\
+	__PMC_EV(PPC7450, THIRD_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY)	\
+	__PMC_EV(PPC7450, MISPREDICTED_BRANCHES)	\
+	__PMC_EV(PPC7450, FOLDED_BRANCHES)	\
+	__PMC_EV(PPC7450, FP_STORE_DOUBLE_COMPLETES_IN_LSU)	\
+	__PMC_EV(PPC7450, L2_CACHE_HITS)	\
+	__PMC_EV(PPC7450, L3_CACHE_HITS)	\
+	__PMC_EV(PPC7450, L2_INSTR_CACHE_MISSES)	\
+	__PMC_EV(PPC7450, L3_INSTR_CACHE_MISSES)	\
+	__PMC_EV(PPC7450, L2_DATA_CACHE_MISSES)	\
+	__PMC_EV(PPC7450, L3_DATA_CACHE_MISSES)	\
+	__PMC_EV(PPC7450, L2_LOAD_HITS)	\
+	__PMC_EV(PPC7450, L2_STORE_HITS)	\
+	__PMC_EV(PPC7450, L3_LOAD_HITS)	\
+	__PMC_EV(PPC7450, L3_STORE_HITS)	\
+	__PMC_EV(PPC7450, L2_TOUCH_HITS)	\
+	__PMC_EV(PPC7450, L3_TOUCH_HITS)	\
+	__PMC_EV(PPC7450, SNOOP_MODIFIED)	\
+	__PMC_EV(PPC7450, SNOOP_VALID)	\
+	__PMC_EV(PPC7450, INTERVENTION)	\
+	__PMC_EV(PPC7450, L2_CACHE_MISSES)	\
+	__PMC_EV(PPC7450, L3_CACHE_MISSES)	\
+	__PMC_EV(PPC7450, L2_CACHE_CASTOUTS)	\
+	__PMC_EV(PPC7450, L3_CACHE_CASTOUTS)	\
+	__PMC_EV(PPC7450, L2SQ_FULL_CYCLES)	\
+	__PMC_EV(PPC7450, L3SQ_FULL_CYCLES)	\
+	__PMC_EV(PPC7450, RAQ_FULL_CYCLES)	\
+	__PMC_EV(PPC7450, WAQ_FULL_CYCLES)	\
+	__PMC_EV(PPC7450, L1_EXTERNAL_INTERVENTIONS)	\
+	__PMC_EV(PPC7450, L2_EXTERNAL_INTERVENTIONS)	\
+	__PMC_EV(PPC7450, L3_EXTERNAL_INTERVENTIONS)	\
+	__PMC_EV(PPC7450, EXTERNAL_INTERVENTIONS)	\
+	__PMC_EV(PPC7450, EXTERNAL_PUSHES)	\
+	__PMC_EV(PPC7450, EXTERNAL_SNOOP_RETRY)	\
+	__PMC_EV(PPC7450, DTQ_FULL_CYCLES)	\
+	__PMC_EV(PPC7450, BUS_RETRY)	\
+	__PMC_EV(PPC7450, L2_VALID_REQUEST)	\
+	__PMC_EV(PPC7450, BORDQ_FULL)	\
+	__PMC_EV(PPC7450, BUS_TAS_FOR_READS)	\
+	__PMC_EV(PPC7450, BUS_TAS_FOR_WRITES)	\
+	__PMC_EV(PPC7450, BUS_READS_NOT_RETRIED)	\
+	__PMC_EV(PPC7450, BUS_WRITES_NOT_RETRIED)	\
+	__PMC_EV(PPC7450, BUS_READS_WRITES_NOT_RETRIED)	\
+	__PMC_EV(PPC7450, BUS_RETRY_DUE_TO_L1_RETRY)	\
+	__PMC_EV(PPC7450, BUS_RETRY_DUE_TO_PREVIOUS_ADJACENT)	\
+	__PMC_EV(PPC7450, BUS_RETRY_DUE_TO_COLLISION)	\
+	__PMC_EV(PPC7450, BUS_RETRY_DUE_TO_INTERVENTION_ORDERING)	\
+	__PMC_EV(PPC7450, SNOOP_REQUESTS)	\
+	__PMC_EV(PPC7450, PREFETCH_ENGINE_REQUEST)	\
+	__PMC_EV(PPC7450, PREFETCH_ENGINE_COLLISION_VS_LOAD)	\
+	__PMC_EV(PPC7450, PREFETCH_ENGINE_COLLISION_VS_STORE)	\
+	__PMC_EV(PPC7450, PREFETCH_ENGINE_COLLISION_VS_INSTR_FETCH)	\
+	__PMC_EV(PPC7450, PREFETCH_ENGINE_COLLISION_VS_LOAD_STORE_INSTR_FETCH)	\
+	__PMC_EV(PPC7450, PREFETCH_ENGINE_FULL)
+
+#define PMC_EV_PPC7450_FIRST	PMC_EV_PPC7450_CYCLE
+#define PMC_EV_PPC7450_LAST	PMC_EV_PPC7450_PREFETCH_ENGINE_FULL
+
 /*
  * All known PMC events.
  *
@@ -3138,6 +3363,8 @@ __PMC_EV_ALIAS("CYCLES_UNHALTED_L3_FLL_DISABLE", UCP_EVENT_86H_01H)
 	__PMC_EV_UCF()				\
 	__PMC_EV_BLOCK(UCP,	0x12080)	\
 	__PMC_EV_UCP()				\
+	__PMC_EV_BLOCK(PPC7450,	0x13000)	\
+	__PMC_EV_PPC7450()			\
 
 #define	PMC_EVENT_FIRST	PMC_EV_TSC_TSC
 #define	PMC_EVENT_LAST	PMC_EV_UCP_LAST
diff --git a/sys/dev/ichsmb/ichsmb_pci.c b/sys/dev/ichsmb/ichsmb_pci.c
index 48d6eb6..d4fb777 100644
--- a/sys/dev/ichsmb/ichsmb_pci.c
+++ b/sys/dev/ichsmb/ichsmb_pci.c
@@ -103,9 +103,6 @@ static device_method_t ichsmb_pci_methods[] = {
         DEVMETHOD(device_attach, ichsmb_pci_attach),
         DEVMETHOD(device_detach, ichsmb_detach),
 
-	/* Bus methods */
-        DEVMETHOD(bus_print_child, bus_generic_print_child),
-
 	/* SMBus methods */
         DEVMETHOD(smbus_callback, ichsmb_callback),
         DEVMETHOD(smbus_quick, ichsmb_quick),
@@ -118,7 +115,8 @@ static device_method_t ichsmb_pci_methods[] = {
         DEVMETHOD(smbus_pcall, ichsmb_pcall),
         DEVMETHOD(smbus_bwrite, ichsmb_bwrite),
         DEVMETHOD(smbus_bread, ichsmb_bread),
-	{ 0, 0 }
+
+	DEVMETHOD_END
 };
 
 static driver_t ichsmb_pci_driver = {
diff --git a/sys/dev/ida/ida_pci.c b/sys/dev/ida/ida_pci.c
index c33e235..e71c6d4 100644
--- a/sys/dev/ida/ida_pci.c
+++ b/sys/dev/ida/ida_pci.c
@@ -188,9 +188,7 @@ static device_method_t ida_pci_methods[] = {
 	DEVMETHOD(device_attach,	ida_pci_attach),
 	DEVMETHOD(device_detach,	ida_detach),
 
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t ida_pci_driver = {
diff --git a/sys/dev/if_ndis/if_ndis.c b/sys/dev/if_ndis/if_ndis.c
index d350e09..68b7d98 100644
--- a/sys/dev/if_ndis/if_ndis.c
+++ b/sys/dev/if_ndis/if_ndis.c
@@ -150,9 +150,9 @@ static funcptr ndis_resettask_wrap;
 static funcptr ndis_inputtask_wrap;
 
 static struct	ieee80211vap *ndis_vap_create(struct ieee80211com *,
-		    const char name[IFNAMSIZ], int unit, int opmode,
-		    int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
-		    const uint8_t mac[IEEE80211_ADDR_LEN]);
+		    const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
+		    const uint8_t [IEEE80211_ADDR_LEN],
+		    const uint8_t [IEEE80211_ADDR_LEN]);
 static void ndis_vap_delete	(struct ieee80211vap *);
 static void ndis_tick		(void *);
 static void ndis_ticktask	(device_object *, void *);
@@ -973,10 +973,10 @@ fail:
 }
 
 static struct ieee80211vap *
-ndis_vap_create(struct ieee80211com *ic,
-	const char name[IFNAMSIZ], int unit, int opmode, int flags,
-	const uint8_t bssid[IEEE80211_ADDR_LEN],
-	const uint8_t mac[IEEE80211_ADDR_LEN])
+ndis_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
+    enum ieee80211_opmode opmode, int flags,
+    const uint8_t bssid[IEEE80211_ADDR_LEN],
+    const uint8_t mac[IEEE80211_ADDR_LEN])
 {
 	struct ndis_vap *nvp;
 	struct ieee80211vap *vap;
diff --git a/sys/dev/if_ndis/if_ndis_pccard.c b/sys/dev/if_ndis/if_ndis_pccard.c
index e7ecf2e..a5a7b5e 100644
--- a/sys/dev/if_ndis/if_ndis_pccard.c
+++ b/sys/dev/if_ndis/if_ndis_pccard.c
@@ -207,7 +207,7 @@ ndis_attach_pccard(dev)
 		goto fail;
 	}
 	sc->ndis_rescnt++;
-	resource_list_add(&sc->ndis_rl, SYS_RES_IOPORT, rid,
+	resource_list_add(&sc->ndis_rl, SYS_RES_IOPORT, sc->ndis_io_rid,
 	    rman_get_start(sc->ndis_res_io), rman_get_end(sc->ndis_res_io),
 	    rman_get_size(sc->ndis_res_io));
 
diff --git a/sys/dev/if_ndis/if_ndis_usb.c b/sys/dev/if_ndis/if_ndis_usb.c
index b872f9a..21fac0d 100644
--- a/sys/dev/if_ndis/if_ndis_usb.c
+++ b/sys/dev/if_ndis/if_ndis_usb.c
@@ -91,11 +91,9 @@ static device_method_t ndis_methods[] = {
 	DEVMETHOD(device_shutdown,	ndis_shutdown),
 
         /* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
 	DEVMETHOD(bus_get_resource_list, ndis_get_resource_list),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t ndis_driver = {
diff --git a/sys/dev/iicbus/iicbb.c b/sys/dev/iicbus/iicbb.c
index 2bc6321..a7eb2a0 100644
--- a/sys/dev/iicbus/iicbb.c
+++ b/sys/dev/iicbus/iicbb.c
@@ -61,6 +61,7 @@ __FBSDID("$FreeBSD$");
 
 struct iicbb_softc {
 	device_t iicbus;
+	int udelay;		/* signal toggle delay in usec */
 };
 
 static int iicbb_attach(device_t);
@@ -123,6 +124,7 @@ iicbb_attach(device_t dev)
 	sc->iicbus = device_add_child(dev, "iicbus", -1);
 	if (!sc->iicbus)
 		return (ENXIO);
+	sc->udelay = 10;		/* 10 uS default */
 	bus_generic_attach(dev);
 
 	return (0);
@@ -184,20 +186,18 @@ iicbb_print_child(device_t bus, device_t dev)
 	return (retval);
 }
 
-#define IIC_DELAY	10
-
-#define I2C_SETSDA(dev,val) do {			\
+#define I2C_SETSDA(sc,dev,val) do {			\
 	IICBB_SETSDA(device_get_parent(dev), val);	\
-	DELAY(IIC_DELAY);				\
+	DELAY(sc->udelay);				\
 	} while (0)
 
 #define I2C_SETSCL(dev,val) do {			\
 	iicbb_setscl(dev, val, 100);			\
 	} while (0)
 
-#define I2C_SET(dev,ctrl,data) do {			\
+#define I2C_SET(sc,dev,ctrl,data) do {			\
 	I2C_SETSCL(dev, ctrl);				\
-	I2C_SETSDA(dev, data);				\
+	I2C_SETSDA(sc, dev, data);			\
 	} while (0)
 
 #define I2C_GETSDA(dev) (IICBB_GETSDA(device_get_parent(dev)))
@@ -216,34 +216,39 @@ static int i2c_debug = 0;
 static void
 iicbb_setscl(device_t dev, int val, int timeout)
 {
+	struct iicbb_softc *sc = device_get_softc(dev);
 	int k = 0;
 
 	IICBB_SETSCL(device_get_parent(dev), val);
-	DELAY(IIC_DELAY);
+	DELAY(sc->udelay);
 
 	while (val && !I2C_GETSCL(dev) && k++ < timeout) {
 		IICBB_SETSCL(device_get_parent(dev), val);
-		DELAY(IIC_DELAY);
+		DELAY(sc->udelay);
 	}
-		
+
 	return;
 }
 
 static void
 iicbb_one(device_t dev, int timeout)
 {
-	I2C_SET(dev,0,1);
-	I2C_SET(dev,1,1);
-	I2C_SET(dev,0,1);
+	struct iicbb_softc *sc = device_get_softc(dev);
+
+	I2C_SET(sc,dev,0,1);
+	I2C_SET(sc,dev,1,1);
+	I2C_SET(sc,dev,0,1);
 	return;
 }
 
 static void
 iicbb_zero(device_t dev, int timeout)
 {
-	I2C_SET(dev,0,0);
-	I2C_SET(dev,1,0);
-	I2C_SET(dev,0,0);
+	struct iicbb_softc *sc = device_get_softc(dev);
+
+	I2C_SET(sc,dev,0,0);
+	I2C_SET(sc,dev,1,0);
+	I2C_SET(sc,dev,0,0);
 	return;
 }
 
@@ -264,20 +269,21 @@ iicbb_zero(device_t dev, int timeout)
 static int
 iicbb_ack(device_t dev, int timeout)
 {
+	struct iicbb_softc *sc = device_get_softc(dev);
 	int noack;
 	int k = 0;
-    
-	I2C_SET(dev,0,1);
-	I2C_SET(dev,1,1);
+
+	I2C_SET(sc,dev,0,1);
+	I2C_SET(sc,dev,1,1);
 	do {
 		noack = I2C_GETSDA(dev);
 		if (!noack)
 			break;
-		DELAY(10);
-		k += 10;
+		DELAY(1);
+		k++;
 	} while (k < timeout);
 
-	I2C_SET(dev,0,1);
+	I2C_SET(sc,dev,0,1);
 	I2C_DEBUG(printf("%c ",noack?'-':'+'));
 
 	return (noack);
@@ -302,16 +308,17 @@ iicbb_sendbyte(device_t dev, u_char data, int timeout)
 static u_char
 iicbb_readbyte(device_t dev, int last, int timeout)
 {
+	struct iicbb_softc *sc = device_get_softc(dev);
 	int i;
 	unsigned char data=0;
-    
-	I2C_SET(dev,0,1);
+
+	I2C_SET(sc,dev,0,1);
 	for (i=7; i>=0; i--) 
 	{
-		I2C_SET(dev,1,1);
+		I2C_SET(sc,dev,1,1);
 		if (I2C_GETSDA(dev))
 			data |= (1<<i);
-		I2C_SET(dev,0,1);
+		I2C_SET(sc,dev,0,1);
 	}
 	if (last) {
 		iicbb_one(dev, timeout);
@@ -337,13 +344,14 @@ iicbb_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
 static int
 iicbb_start(device_t dev, u_char slave, int timeout)
 {
+	struct iicbb_softc *sc = device_get_softc(dev);
 	int error;
 
 	I2C_DEBUG(printf("<"));
 
-	I2C_SET(dev,1,1);
-	I2C_SET(dev,1,0);
-	I2C_SET(dev,0,0);
+	I2C_SET(sc,dev,1,1);
+	I2C_SET(sc,dev,1,0);
+	I2C_SET(sc,dev,0,0);
 
 	/* send address */
 	iicbb_sendbyte(dev, slave, timeout);
@@ -364,10 +372,13 @@ error:
 static int
 iicbb_stop(device_t dev)
 {
-	I2C_SET(dev,0,0);
-	I2C_SET(dev,1,0);
-	I2C_SET(dev,1,1);
+	struct iicbb_softc *sc = device_get_softc(dev);
+
+	I2C_SET(sc,dev,0,0);
+	I2C_SET(sc,dev,1,0);
+	I2C_SET(sc,dev,1,1);
 	I2C_DEBUG(printf(">"));
+	I2C_DEBUG(printf("\n"));
 	return (0);
 }
 
diff --git a/sys/dev/iicbus/iicbus.c b/sys/dev/iicbus/iicbus.c
index ca110c8..d919277 100644
--- a/sys/dev/iicbus/iicbus.c
+++ b/sys/dev/iicbus/iicbus.c
@@ -92,10 +92,16 @@ iicbus_attach(device_t dev)
 	unsigned char addr;
 #endif
 	struct iicbus_softc *sc = IICBUS_SOFTC(dev);
+	int strict;
 
 	sc->dev = dev;
 	mtx_init(&sc->lock, "iicbus", NULL, MTX_DEF);
 	iicbus_reset(dev, IIC_FASTEST, 0, NULL);
+	if (resource_int_value(device_get_name(dev),
+		device_get_unit(dev), "strict", &strict) == 0)
+		sc->strict = strict;
+	else
+		sc->strict = 1;
 
 	/* device probing is meaningless since the bus is supposed to be
 	 * hot-plug. Moreover, some I2C chips do not appreciate random
@@ -245,7 +251,6 @@ static device_method_t iicbus_methods[] = {
 
         /* bus interface */
         DEVMETHOD(bus_add_child,	iicbus_add_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
         DEVMETHOD(bus_print_child,      iicbus_print_child),
 	DEVMETHOD(bus_probe_nomatch,	iicbus_probe_nomatch),
 	DEVMETHOD(bus_read_ivar,	iicbus_read_ivar),
@@ -256,7 +261,7 @@ static device_method_t iicbus_methods[] = {
 	/* iicbus interface */
 	DEVMETHOD(iicbus_transfer,	iicbus_transfer),
 
-        { 0, 0 }
+	DEVMETHOD_END
 };
 
 driver_t iicbus_driver = {
diff --git a/sys/dev/iicbus/iicbus.h b/sys/dev/iicbus/iicbus.h
index 0698d5c..92c250e 100644
--- a/sys/dev/iicbus/iicbus.h
+++ b/sys/dev/iicbus/iicbus.h
@@ -41,6 +41,8 @@ struct iicbus_softc
 	device_t owner;		/* iicbus owner device structure */
 	u_char started;		/* address of the 'started' slave
 				 * 0 if no start condition succeeded */
+	u_char strict;		/* deny operations that violate the
+				 * I2C protocol */
 	struct mtx lock;
 };
 
diff --git a/sys/dev/iicbus/iiconf.c b/sys/dev/iicbus/iiconf.c
index e59dc35..7c22b51 100644
--- a/sys/dev/iicbus/iiconf.c
+++ b/sys/dev/iicbus/iiconf.c
@@ -243,8 +243,8 @@ iicbus_write(device_t bus, const char *buf, int len, int *sent, int timeout)
 {
 	struct iicbus_softc *sc = (struct iicbus_softc *)device_get_softc(bus);
 	
-	/* a slave must have been started with the appropriate address */
-	if (!sc->started || (sc->started & LSB))
+	/* a slave must have been started for writing */
+	if (sc->started == 0 || (sc->strict != 0 && (sc->started & LSB) != 0))
 		return (EINVAL);
 
 	return (IICBUS_WRITE(device_get_parent(bus), buf, len, sent, timeout));
@@ -261,8 +261,8 @@ iicbus_read(device_t bus, char *buf, int len, int *read, int last, int delay)
 {
 	struct iicbus_softc *sc = (struct iicbus_softc *)device_get_softc(bus);
 	
-	/* a slave must have been started with the appropriate address */
-	if (!sc->started || !(sc->started & LSB))
+	/* a slave must have been started for reading */
+	if (sc->started == 0 || (sc->strict != 0 && (sc->started & LSB) == 0))
 		return (EINVAL);
 
 	return (IICBUS_READ(device_get_parent(bus), buf, len, read, last, delay));
diff --git a/sys/dev/iicbus/iicsmb.c b/sys/dev/iicbus/iicsmb.c
index 10229ac..27f1d2b 100644
--- a/sys/dev/iicbus/iicsmb.c
+++ b/sys/dev/iicbus/iicsmb.c
@@ -22,11 +22,11 @@
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
- *
- * $FreeBSD$
- *
  */
 
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 /*
  * I2C to SMB bridge
  *
@@ -106,10 +106,6 @@ static device_method_t iicsmb_methods[] = {
 	DEVMETHOD(device_attach,	iicsmb_attach),
 	DEVMETHOD(device_detach,	iicsmb_detach),
 
-	/* bus interface */
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-
 	/* iicbus interface */
 	DEVMETHOD(iicbus_intr,		iicsmb_intr),
 
@@ -125,8 +121,8 @@ static device_method_t iicsmb_methods[] = {
 	DEVMETHOD(smbus_pcall,		iicsmb_pcall),
 	DEVMETHOD(smbus_bwrite,		iicsmb_bwrite),
 	DEVMETHOD(smbus_bread,		iicsmb_bread),
-	
-	{ 0, 0 }
+
+	DEVMETHOD_END
 };
 
 static driver_t iicsmb_driver = {
diff --git a/sys/dev/ipw/if_ipw.c b/sys/dev/ipw/if_ipw.c
index 7560430..e632451 100644
--- a/sys/dev/ipw/if_ipw.c
+++ b/sys/dev/ipw/if_ipw.c
@@ -108,9 +108,9 @@ static const struct ipw_ident ipw_ident_table[] = {
 };
 
 static struct ieee80211vap *ipw_vap_create(struct ieee80211com *,
-		    const char name[IFNAMSIZ], int unit, int opmode, int flags,
-		    const uint8_t bssid[IEEE80211_ADDR_LEN],
-		    const uint8_t mac[IEEE80211_ADDR_LEN]);
+		    const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
+		    const uint8_t [IEEE80211_ADDR_LEN],
+		    const uint8_t [IEEE80211_ADDR_LEN]);
 static void	ipw_vap_delete(struct ieee80211vap *);
 static int	ipw_dma_alloc(struct ipw_softc *);
 static void	ipw_release(struct ipw_softc *);
@@ -428,10 +428,10 @@ ipw_detach(device_t dev)
 }
 
 static struct ieee80211vap *
-ipw_vap_create(struct ieee80211com *ic,
-	const char name[IFNAMSIZ], int unit, int opmode, int flags,
-	const uint8_t bssid[IEEE80211_ADDR_LEN],
-	const uint8_t mac[IEEE80211_ADDR_LEN])
+ipw_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
+    enum ieee80211_opmode opmode, int flags,
+    const uint8_t bssid[IEEE80211_ADDR_LEN],
+    const uint8_t mac[IEEE80211_ADDR_LEN])
 {
 	struct ifnet *ifp = ic->ic_ifp;
 	struct ipw_softc *sc = ifp->if_softc;
diff --git a/sys/dev/isp/isp_freebsd.c b/sys/dev/isp/isp_freebsd.c
index 3d676ab..56fedff 100644
--- a/sys/dev/isp/isp_freebsd.c
+++ b/sys/dev/isp/isp_freebsd.c
@@ -1087,8 +1087,9 @@ static ISP_INLINE void
 destroy_lun_state(ispsoftc_t *isp, tstate_t *tptr)
 {
 	struct tslist *lhp;
-	KASSERT((tptr->hold == 0), ("tptr still held"));
-	ISP_GET_PC_ADDR(isp, xpt_path_path_id(tptr->owner), lun_hash[LUN_HASH_FUNC(xpt_path_lun_id(tptr->owner))], lhp);
+	KASSERT((tptr->hold != 0), ("tptr is not held"));
+	KASSERT((tptr->hold == 1), ("tptr still held (%d)", tptr->hold));
+	ISP_GET_PC_ADDR(isp, cam_sim_bus(xpt_path_sim(tptr->owner)), lun_hash[LUN_HASH_FUNC(xpt_path_lun_id(tptr->owner))], lhp);
 	SLIST_REMOVE(lhp, tptr, tstate, next);
 	xpt_free_path(tptr->owner);
 	free(tptr, M_DEVBUF);
@@ -1316,12 +1317,13 @@ isp_disable_lun(ispsoftc_t *isp, union ccb *ccb)
 		mtx_sleep(isp, &isp->isp_lock, PRIBIO, "want_isp_disable_lun", 0);
 	}
 	isp->isp_osinfo.tmbusy = 1;
+	status = CAM_REQ_INPROG;
 
 	/*
 	 * Find the state pointer.
 	 */
 	if ((tptr = get_lun_statep(isp, bus, lun)) == NULL) {
-		ccb->ccb_h.status = CAM_PATH_INVALID;
+		status = CAM_PATH_INVALID;
 		goto done;
 	}
 
@@ -1341,13 +1343,13 @@ isp_disable_lun(ispsoftc_t *isp, union ccb *ccb)
 	}
 
 	isp->isp_osinfo.rptr = &status;
-	status = CAM_REQ_INPROG;
 	if (isp_lun_cmd(isp, RQSTYPE_ENABLE_LUN, bus, lun, 0, 0)) {
 		status = CAM_RESRC_UNAVAIL;
 	} else {
 		mtx_sleep(ccb, &isp->isp_lock, PRIBIO, "isp_disable_lun", 0);
 	}
 done:
+	ccb->ccb_h.status = status;
 	if (status == CAM_REQ_CMP) {
 		xpt_print(ccb->ccb_h.path, "now disabled for target mode\n");
 	}
@@ -2949,23 +2951,25 @@ isp_target_mark_aborted(ispsoftc_t *isp, union ccb *ccb)
 {
 	tstate_t *tptr;
 	atio_private_data_t *atp;
+	union ccb *accb = ccb->cab.abort_ccb;
 
-	tptr = get_lun_statep(isp, XS_CHANNEL(ccb), XS_LUN(ccb));
+	tptr = get_lun_statep(isp, XS_CHANNEL(accb), XS_LUN(accb));
 	if (tptr == NULL) {
-		tptr = get_lun_statep(isp, XS_CHANNEL(ccb), CAM_LUN_WILDCARD);
+		tptr = get_lun_statep(isp, XS_CHANNEL(accb), CAM_LUN_WILDCARD);
 		if (tptr == NULL) {
 			ccb->ccb_h.status = CAM_REQ_INVALID;
 			return;
 		}
 	}
 
-	atp = isp_get_atpd(isp, tptr, ccb->atio.tag_id);
+	atp = isp_get_atpd(isp, tptr, accb->atio.tag_id);
 	if (atp == NULL) {
 		ccb->ccb_h.status = CAM_REQ_INVALID;
-		return;
+	} else {
+		atp->dead = 1;
+		ccb->ccb_h.status = CAM_REQ_CMP;
 	}
-	atp->dead = 1;
-	ccb->ccb_h.status = CAM_REQ_CMP;
+	rls_lun_statep(isp, tptr);
 }
 
 static void
@@ -3166,10 +3170,10 @@ isptargstart(struct cam_periph *periph, union ccb *iccb)
 		xpt_print(atio->ccb_h.path, "[0x%x] Non-Zero Lun %d: cdb0=0x%x\n", atio->tag_id, return_lun, cdb[0]);
 		if (cdb[0] != INQUIRY && cdb[0] != REPORT_LUNS && cdb[0] != REQUEST_SENSE) {
 			status = SCSI_STATUS_CHECK_COND;
-			atio->sense_data.error_code = SSD_ERRCODE_VALID|SSD_CURRENT_ERROR|SSD_KEY_ILLEGAL_REQUEST;
-			atio->sense_data.add_sense_code = 0x25;
-			atio->sense_data.add_sense_code_qual = 0x0;
-			atio->sense_len = sizeof (atio->sense_data);
+			SDFIXED(atio->sense_data)->error_code = SSD_ERRCODE_VALID|SSD_CURRENT_ERROR|SSD_KEY_ILLEGAL_REQUEST;
+			SDFIXED(atio->sense_data)->add_sense_code = 0x25;
+			SDFIXED(atio->sense_data)->add_sense_code_qual = 0x0;
+			atio->sense_len = SSD_MIN_SIZE;
 		}
 		return_lun = CAM_LUN_WILDCARD;
 	}
@@ -3193,10 +3197,10 @@ isptargstart(struct cam_periph *periph, union ccb *iccb)
 	case READ_16:
 		if (isptarg_rwparm(cdb, disk_data, disk_size, atio->ccb_h.ccb_data_offset, &data_ptr, &data_len, &last)) {
 			status = SCSI_STATUS_CHECK_COND;
-			atio->sense_data.error_code = SSD_ERRCODE_VALID|SSD_CURRENT_ERROR|SSD_KEY_UNIT_ATTENTION;
-			atio->sense_data.add_sense_code = 0x5;
-			atio->sense_data.add_sense_code_qual = 0x24;
-			atio->sense_len = sizeof (atio->sense_data);
+			SDFIXED(atio->sense_data)->error_code = SSD_ERRCODE_VALID|SSD_CURRENT_ERROR|SSD_KEY_UNIT_ATTENTION;
+			SDFIXED(atio->sense_data)->add_sense_code = 0x5;
+			SDFIXED(atio->sense_data)->add_sense_code_qual = 0x24;
+			atio->sense_len = SSD_MIN_SIZE;
 		} else {
 #ifdef	ISP_FORCE_TIMEOUT
 			{
@@ -3232,10 +3236,10 @@ isptargstart(struct cam_periph *periph, union ccb *iccb)
 	case WRITE_16:
 		if (isptarg_rwparm(cdb, disk_data, disk_size, atio->ccb_h.ccb_data_offset, &data_ptr, &data_len, &last)) {
 			status = SCSI_STATUS_CHECK_COND;
-			atio->sense_data.error_code = SSD_ERRCODE_VALID|SSD_CURRENT_ERROR|SSD_KEY_UNIT_ATTENTION;
-			atio->sense_data.add_sense_code = 0x5;
-			atio->sense_data.add_sense_code_qual = 0x24;
-			atio->sense_len = sizeof (atio->sense_data);
+			SDFIXED(atio->sense_data)->error_code = SSD_ERRCODE_VALID|SSD_CURRENT_ERROR|SSD_KEY_UNIT_ATTENTION;
+			SDFIXED(atio->sense_data)->add_sense_code = 0x5;
+			SDFIXED(atio->sense_data)->add_sense_code_qual = 0x24;
+			atio->sense_len = SSD_MIN_SIZE;
 		} else {
 #ifdef	ISP_FORCE_TIMEOUT
 			{
@@ -3269,10 +3273,10 @@ isptargstart(struct cam_periph *periph, union ccb *iccb)
 		flags |= CAM_DIR_IN;
 		if (cdb[1] || cdb[2] || cdb[3]) {
 			status = SCSI_STATUS_CHECK_COND;
-			atio->sense_data.error_code = SSD_ERRCODE_VALID|SSD_CURRENT_ERROR|SSD_KEY_UNIT_ATTENTION;
-			atio->sense_data.add_sense_code = 0x5;
-			atio->sense_data.add_sense_code_qual = 0x20;
-			atio->sense_len = sizeof (atio->sense_data);
+			SDFIXED(atio->sense_data)->error_code = SSD_ERRCODE_VALID|SSD_CURRENT_ERROR|SSD_KEY_UNIT_ATTENTION;
+			SDFIXED(atio->sense_data)->add_sense_code = 0x5;
+			SDFIXED(atio->sense_data)->add_sense_code_qual = 0x20;
+			atio->sense_len = SSD_MIN_SIZE;
 			break;
 		}
 		data_len = sizeof (iqd);
@@ -3293,10 +3297,10 @@ isptargstart(struct cam_periph *periph, union ccb *iccb)
 		if (ca) {
 			ca = 0;
 			status = SCSI_STATUS_CHECK_COND;
-			atio->sense_data.error_code = SSD_ERRCODE_VALID|SSD_CURRENT_ERROR|SSD_KEY_UNIT_ATTENTION;
-			atio->sense_data.add_sense_code = 0x28;
-			atio->sense_data.add_sense_code_qual = 0x0;
-			atio->sense_len = sizeof (atio->sense_data);
+			SDFIXED(atio->sense_data)->error_code = SSD_ERRCODE_VALID|SSD_CURRENT_ERROR|SSD_KEY_UNIT_ATTENTION;
+			SDFIXED(atio->sense_data)->add_sense_code = 0x28;
+			SDFIXED(atio->sense_data)->add_sense_code_qual = 0x0;
+			atio->sense_len = SSD_MIN_SIZE;
 		}
 		break;
 	case SYNCHRONIZE_CACHE:
@@ -3311,10 +3315,10 @@ isptargstart(struct cam_periph *periph, union ccb *iccb)
 		flags |= CAM_DIR_IN;
 		if (cdb[2] || cdb[3] || cdb[4] || cdb[5]) {
 			status = SCSI_STATUS_CHECK_COND;
-			atio->sense_data.error_code = SSD_ERRCODE_VALID|SSD_CURRENT_ERROR|SSD_KEY_UNIT_ATTENTION;
-			atio->sense_data.add_sense_code = 0x5;
-			atio->sense_data.add_sense_code_qual = 0x24;
-			atio->sense_len = sizeof (atio->sense_data);
+			SDFIXED(atio->sense_data)->error_code = SSD_ERRCODE_VALID|SSD_CURRENT_ERROR|SSD_KEY_UNIT_ATTENTION;
+			SDFIXED(atio->sense_data)->add_sense_code = 0x5;
+			SDFIXED(atio->sense_data)->add_sense_code_qual = 0x24;
+			atio->sense_len = SSD_MIN_SIZE;
 			break;
 		}
 		if (cdb[8] & 0x1) { /* PMI */
@@ -3365,10 +3369,10 @@ isptargstart(struct cam_periph *periph, union ccb *iccb)
 	default:
 		flags |= CAM_DIR_NONE;
 		status = SCSI_STATUS_CHECK_COND;
-		atio->sense_data.error_code = SSD_ERRCODE_VALID|SSD_CURRENT_ERROR|SSD_KEY_UNIT_ATTENTION;
-		atio->sense_data.add_sense_code = 0x5;
-		atio->sense_data.add_sense_code_qual = 0x20;
-		atio->sense_len = sizeof (atio->sense_data);
+		SDFIXED(atio->sense_data)->error_code = SSD_ERRCODE_VALID|SSD_CURRENT_ERROR|SSD_KEY_UNIT_ATTENTION;
+		SDFIXED(atio->sense_data)->add_sense_code = 0x5;
+		SDFIXED(atio->sense_data)->add_sense_code_qual = 0x20;
+		atio->sense_len = SSD_MIN_SIZE;
 		break;
 	}
 
@@ -4519,7 +4523,7 @@ isp_action(struct cam_sim *sim, union ccb *ccb)
 		switch (accb->ccb_h.func_code) {
 #ifdef	ISP_TARGET_MODE
 		case XPT_ACCEPT_TARGET_IO:
-			isp_target_mark_aborted(isp, accb);
+			isp_target_mark_aborted(isp, ccb);
 			break;
 #endif
 		case XPT_SCSI_IO:
diff --git a/sys/dev/isp/isp_freebsd.h b/sys/dev/isp/isp_freebsd.h
index 0875e64..d54defa 100644
--- a/sys/dev/isp/isp_freebsd.h
+++ b/sys/dev/isp/isp_freebsd.h
@@ -76,6 +76,13 @@
 #define	ISP_IFLAGS	INTR_TYPE_CAM | INTR_ENTROPY | INTR_MPSAFE
 
 #ifdef	ISP_TARGET_MODE
+/* Not quite right, but there was no bump for this change */
+#if __FreeBSD_version < 225469
+#define	SDFIXED(x)	(&x)
+#else
+#define	SDFIXED(x)	((struct scsi_sense_data_fixed *)(&x))
+#endif
+
 #define	ISP_TARGET_FUNCTIONS	1
 #define	ATPDPSIZE	4096
 
diff --git a/sys/dev/iwi/if_iwi.c b/sys/dev/iwi/if_iwi.c
index 73b861c..a7fd9d1 100644
--- a/sys/dev/iwi/if_iwi.c
+++ b/sys/dev/iwi/if_iwi.c
@@ -129,9 +129,9 @@ static const struct iwi_ident iwi_ident_table[] = {
 };
 
 static struct ieee80211vap *iwi_vap_create(struct ieee80211com *,
-		    const char name[IFNAMSIZ], int unit, int opmode, int flags,
-		    const uint8_t bssid[IEEE80211_ADDR_LEN],
-		    const uint8_t mac[IEEE80211_ADDR_LEN]);
+		    const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
+		    const uint8_t [IEEE80211_ADDR_LEN],
+		    const uint8_t [IEEE80211_ADDR_LEN]);
 static void	iwi_vap_delete(struct ieee80211vap *);
 static void	iwi_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 static int	iwi_alloc_cmd_ring(struct iwi_softc *, struct iwi_cmd_ring *,
@@ -495,10 +495,10 @@ iwi_detach(device_t dev)
 }
 
 static struct ieee80211vap *
-iwi_vap_create(struct ieee80211com *ic,
-	const char name[IFNAMSIZ], int unit, int opmode, int flags,
-	const uint8_t bssid[IEEE80211_ADDR_LEN],
-	const uint8_t mac[IEEE80211_ADDR_LEN])
+iwi_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
+    enum ieee80211_opmode opmode, int flags,
+    const uint8_t bssid[IEEE80211_ADDR_LEN],
+    const uint8_t mac[IEEE80211_ADDR_LEN])
 {
 	struct ifnet *ifp = ic->ic_ifp;
 	struct iwi_softc *sc = ifp->if_softc;
diff --git a/sys/dev/iwn/if_iwn.c b/sys/dev/iwn/if_iwn.c
index 8a02752..3786456 100644
--- a/sys/dev/iwn/if_iwn.c
+++ b/sys/dev/iwn/if_iwn.c
@@ -116,9 +116,9 @@ static int	iwn5000_attach(struct iwn_softc *, uint16_t);
 static void	iwn_radiotap_attach(struct iwn_softc *);
 static void	iwn_sysctlattach(struct iwn_softc *);
 static struct ieee80211vap *iwn_vap_create(struct ieee80211com *,
-		    const char name[IFNAMSIZ], int unit, int opmode,
-		    int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
-		    const uint8_t mac[IEEE80211_ADDR_LEN]);
+		    const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
+		    const uint8_t [IEEE80211_ADDR_LEN],
+		    const uint8_t [IEEE80211_ADDR_LEN]);
 static void	iwn_vap_delete(struct ieee80211vap *);
 static int	iwn_detach(device_t);
 static int	iwn_shutdown(device_t);
@@ -246,6 +246,7 @@ static int	iwn_send_sensitivity(struct iwn_softc *);
 static int	iwn_set_pslevel(struct iwn_softc *, int, int, int);
 static int	iwn_send_btcoex(struct iwn_softc *);
 static int	iwn_send_advanced_btcoex(struct iwn_softc *);
+static int	iwn5000_runtime_calib(struct iwn_softc *);
 static int	iwn_config(struct iwn_softc *);
 static uint8_t	*ieee80211_add_ssid(uint8_t *, const uint8_t *, u_int);
 static int	iwn_scan(struct iwn_softc *);
@@ -844,8 +845,8 @@ iwn_sysctlattach(struct iwn_softc *sc)
 }
 
 static struct ieee80211vap *
-iwn_vap_create(struct ieee80211com *ic,
-    const char name[IFNAMSIZ], int unit, int opmode, int flags,
+iwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
+    enum ieee80211_opmode opmode, int flags,
     const uint8_t bssid[IEEE80211_ADDR_LEN],
     const uint8_t mac[IEEE80211_ADDR_LEN])
 {
@@ -2127,7 +2128,7 @@ iwn_newassoc(struct ieee80211_node *ni, int isnew)
 					plcp |= IWN_RFLAG_SGI;
 			} else if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI20)
 				plcp |= IWN_RFLAG_SGI;
-			if (i > 7)
+			if (RV(ni->ni_htrates.rs_rates[i]) > 7)
 				plcp |= IWN_RFLAG_ANT(txant1 | txant2);
 			else
 				plcp |= IWN_RFLAG_ANT(txant1);
@@ -2505,7 +2506,8 @@ iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc,
 	case IWN5000_PHY_CALIB_DC:
 		if ((sc->sc_flags & IWN_FLAG_INTERNAL_PA) == 0 &&
 		    (sc->hw_type == IWN_HW_REV_TYPE_5150 ||
-		     sc->hw_type >= IWN_HW_REV_TYPE_6000))
+		     sc->hw_type >= IWN_HW_REV_TYPE_6000) &&
+		     sc->hw_type != IWN_HW_REV_TYPE_6050)
 			idx = 0;
 		break;
 	case IWN5000_PHY_CALIB_LO:
@@ -4996,6 +4998,19 @@ iwn_send_advanced_btcoex(struct iwn_softc *sc)
 }
 
 static int
+iwn5000_runtime_calib(struct iwn_softc *sc)
+{
+	struct iwn5000_calib_config cmd;
+
+	memset(&cmd, 0, sizeof cmd);
+	cmd.ucode.once.enable = 0xffffffff;
+	cmd.ucode.once.start = IWN5000_CALIB_DC;
+	DPRINTF(sc, IWN_DEBUG_CALIBRATE,
+	    "%s: configuring runtime calibration\n", __func__);
+	return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0);
+}
+
+static int
 iwn_config(struct iwn_softc *sc)
 {
 	struct iwn_ops *ops = &sc->ops;
@@ -5015,6 +5030,17 @@ iwn_config(struct iwn_softc *sc)
 		}
 	}
 
+	if (sc->hw_type == IWN_HW_REV_TYPE_6050) {
+		/* Configure runtime DC calibration. */
+		error = iwn5000_runtime_calib(sc);
+		if (error != 0) {
+			device_printf(sc->sc_dev,
+			    "%s: could not configure runtime calibration\n",
+			    __func__);
+			return error;
+		}
+	}
+
 	/* Configure valid TX chains for >=5000 Series. */
 	if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
 		txmask = htole32(sc->txchainmask);
diff --git a/sys/dev/iwn/if_iwnreg.h b/sys/dev/iwn/if_iwnreg.h
index c3079e6..062125f 100644
--- a/sys/dev/iwn/if_iwnreg.h
+++ b/sys/dev/iwn/if_iwnreg.h
@@ -739,6 +739,8 @@ struct iwn5000_wimax_coex {
 struct iwn5000_calib_elem {
 	uint32_t	enable;
 	uint32_t	start;
+#define	IWN5000_CALIB_DC	(1 << 1)
+
 	uint32_t	send;
 	uint32_t	apply;
 	uint32_t	reserved;
diff --git a/sys/dev/ixgbe/ixgbe.c b/sys/dev/ixgbe/ixgbe.c
index 9a709af..6277848 100644
--- a/sys/dev/ixgbe/ixgbe.c
+++ b/sys/dev/ixgbe/ixgbe.c
@@ -265,7 +265,7 @@ TUNABLE_INT("hw.ixgbe.enable_msix", &ixgbe_enable_msix);
  * it can be a performance win in some workloads, but
  * in others it actually hurts, its off by default. 
  */
-static bool ixgbe_header_split = FALSE;
+static int ixgbe_header_split = FALSE;
 TUNABLE_INT("hw.ixgbe.hdr_split", &ixgbe_header_split);
 
 /*
@@ -313,6 +313,18 @@ static int atr_sample_rate = 20;
 static int fdir_pballoc = 1;
 #endif
 
+#ifdef DEV_NETMAP
+/*
+ * The #ifdef DEV_NETMAP / #endif blocks in this file are meant to
+ * be a reference on how to implement netmap support in a driver.
+ * Additional comments are in ixgbe_netmap.h .
+ *
+ * <dev/netma/ixgbe_netmap.h> contains functions for netmap support
+ * that extend the standard driver.
+ */
+#include <dev/netmap/ixgbe_netmap.h>
+#endif /* DEV_NETMAP */
+
 /*********************************************************************
  *  Device identification routine
  *
@@ -578,6 +590,9 @@ ixgbe_attach(device_t dev)
 
 	ixgbe_add_hw_stats(adapter);
 
+#ifdef DEV_NETMAP
+	ixgbe_netmap_attach(adapter);
+#endif /* DEV_NETMAP */
 	INIT_DEBUGOUT("ixgbe_attach: end");
 	return (0);
 err_late:
@@ -652,6 +667,9 @@ ixgbe_detach(device_t dev)
 
 	ether_ifdetach(adapter->ifp);
 	callout_drain(&adapter->timer);
+#ifdef DEV_NETMAP
+	netmap_detach(adapter->ifp);
+#endif /* DEV_NETMAP */
 	ixgbe_free_pci_resources(adapter);
 	bus_generic_detach(dev);
 	if_free(adapter->ifp);
@@ -2813,9 +2831,20 @@ ixgbe_setup_transmit_ring(struct tx_ring *txr)
 	struct adapter *adapter = txr->adapter;
 	struct ixgbe_tx_buf *txbuf;
 	int i;
+#ifdef DEV_NETMAP
+	struct netmap_adapter *na = NA(adapter->ifp);
+	struct netmap_slot *slot;
+#endif /* DEV_NETMAP */
 
 	/* Clear the old ring contents */
 	IXGBE_TX_LOCK(txr);
+#ifdef DEV_NETMAP
+	/*
+	 * (under lock): if in netmap mode, do some consistency
+	 * checks and set slot to entry 0 of the netmap ring.
+	 */
+	slot = netmap_reset(na, NR_TX, txr->me, 0);
+#endif /* DEV_NETMAP */
 	bzero((void *)txr->tx_base,
 	      (sizeof(union ixgbe_adv_tx_desc)) * adapter->num_tx_desc);
 	/* Reset indices */
@@ -2832,6 +2861,26 @@ ixgbe_setup_transmit_ring(struct tx_ring *txr)
 			m_freem(txbuf->m_head);
 			txbuf->m_head = NULL;
 		}
+#ifdef DEV_NETMAP
+		/*
+		 * In netmap mode, set the map for the packet buffer.
+		 * NOTE: Some drivers (not this one) also need to set
+		 * the physical buffer address in the NIC ring.
+		 * Slots in the netmap ring (indexed by "si") are
+		 * kring->nkr_hwofs positions "ahead" wrt the
+		 * corresponding slot in the NIC ring. In some drivers
+		 * (not here) nkr_hwofs can be negative. When computing
+		 * si = i + kring->nkr_hwofs make sure to handle wraparounds.
+		 */
+		if (slot) {
+			int si = i + na->tx_rings[txr->me].nkr_hwofs;
+
+			if (si >= na->num_tx_desc)
+				si -= na->num_tx_desc;
+			netmap_load_map(txr->txtag, txbuf->map,
+			    NMB(slot + si), na->buff_size);
+		}
+#endif /* DEV_NETMAP */
 		/* Clear the EOP index */
 		txbuf->eop_index = -1;
         }
@@ -3017,7 +3066,7 @@ ixgbe_free_transmit_buffers(struct tx_ring *txr)
  *
  **********************************************************************/
 
-static boolean_t
+static bool
 ixgbe_tx_ctx_setup(struct tx_ring *txr, struct mbuf *mp)
 {
 	struct adapter *adapter = txr->adapter;
@@ -3135,7 +3184,7 @@ ixgbe_tx_ctx_setup(struct tx_ring *txr, struct mbuf *mp)
  *  adapters using advanced tx descriptors
  *
  **********************************************************************/
-static boolean_t
+static bool
 ixgbe_tso_setup(struct tx_ring *txr, struct mbuf *mp, u32 *paylen)
 {
 	struct adapter *adapter = txr->adapter;
@@ -3299,7 +3348,7 @@ ixgbe_atr(struct tx_ring *txr, struct mbuf *mp)
  *  tx_buffer is put back on the free queue.
  *
  **********************************************************************/
-static boolean_t
+static bool
 ixgbe_txeof(struct tx_ring *txr)
 {
 	struct adapter	*adapter = txr->adapter;
@@ -3310,6 +3359,29 @@ ixgbe_txeof(struct tx_ring *txr)
 
 	mtx_assert(&txr->tx_mtx, MA_OWNED);
 
+#ifdef DEV_NETMAP
+	if (ifp->if_capenable & IFCAP_NETMAP) {
+		struct netmap_adapter *na = NA(ifp);
+
+		/*
+		 * In netmap mode, all the work is done in the context
+		 * of the client thread. Interrupt handlers only wake up
+		 * clients, which may be sleeping on individual rings
+		 * or on a global resource for all rings.
+		 * When the driver has separate locks, we need to
+		 * release and re-acquire txlock to avoid deadlocks.
+		 * XXX see if we can find a better way.
+		 */
+		selwakeuppri(&na->tx_rings[txr->me].si, PI_NET);
+		IXGBE_TX_UNLOCK(txr);
+		IXGBE_CORE_LOCK(adapter);
+		selwakeuppri(&na->tx_rings[na->num_queues + 1].si, PI_NET);
+		IXGBE_CORE_UNLOCK(adapter);
+		IXGBE_TX_LOCK(txr);
+		return FALSE;
+	}
+#endif /* DEV_NETMAP */
+
 	if (txr->tx_avail == adapter->num_tx_desc) {
 		txr->queue_status = IXGBE_QUEUE_IDLE;
 		return FALSE;
@@ -3698,6 +3770,10 @@ ixgbe_setup_receive_ring(struct rx_ring *rxr)
 	bus_dma_segment_t	pseg[1], hseg[1];
 	struct lro_ctrl		*lro = &rxr->lro;
 	int			rsize, nsegs, error = 0;
+#ifdef DEV_NETMAP
+	struct netmap_adapter *na = NA(rxr->adapter->ifp);
+	struct netmap_slot *slot;
+#endif /* DEV_NETMAP */
 
 	adapter = rxr->adapter;
 	ifp = adapter->ifp;
@@ -3705,6 +3781,10 @@ ixgbe_setup_receive_ring(struct rx_ring *rxr)
 
 	/* Clear the ring contents */
 	IXGBE_RX_LOCK(rxr);
+#ifdef DEV_NETMAP
+	/* same as in ixgbe_setup_transmit_ring() */
+	slot = netmap_reset(na, NR_RX, rxr->me, 0);
+#endif /* DEV_NETMAP */
 	rsize = roundup2(adapter->num_rx_desc *
 	    sizeof(union ixgbe_adv_rx_desc), DBA_ALIGN);
 	bzero((void *)rxr->rx_base, rsize);
@@ -3721,6 +3801,29 @@ ixgbe_setup_receive_ring(struct rx_ring *rxr)
 		struct mbuf	*mh, *mp;
 
 		rxbuf = &rxr->rx_buffers[j];
+#ifdef DEV_NETMAP
+		/*
+		 * In netmap mode, fill the map and set the buffer
+		 * address in the NIC ring, considering the offset
+		 * between the netmap and NIC rings (see comment in
+		 * ixgbe_setup_transmit_ring() ). No need to allocate
+		 * an mbuf, so end the block with a continue;
+		 */
+		if (slot) {
+			int sj = j + na->rx_rings[rxr->me].nkr_hwofs;
+			void *addr;
+
+			if (sj >= na->num_rx_desc)
+				sj -= na->num_rx_desc;
+			addr = NMB(slot + sj);
+			netmap_load_map(rxr->ptag,
+			    rxbuf->pmap, addr, na->buff_size);
+			/* Update descriptor */
+			rxr->rx_base[j].read.pkt_addr =
+			    htole64(vtophys(addr));
+			continue;
+		}
+#endif /* DEV_NETMAP */
 		/*
 		** Don't allocate mbufs if not
 		** doing header split, its wasteful
@@ -3913,6 +4016,35 @@ ixgbe_initialize_receive_units(struct adapter *adapter)
 
 		/* Setup the HW Rx Head and Tail Descriptor Pointers */
 		IXGBE_WRITE_REG(hw, IXGBE_RDH(i), 0);
+#ifdef DEV_NETMAP
+		/*
+		 * In netmap mode, we must preserve the buffers made
+		 * available to userspace before the if_init()
+		 * (this is true by default on the TX side, because
+		 * init makes all buffers available to userspace).
+		 *
+		 * netmap_reset() and the device specific routines
+		 * (e.g. ixgbe_setup_receive_rings()) map these
+		 * buffers at the end of the NIC ring, so here we
+		 * must set the RDT (tail) register to make sure
+		 * they are not overwritten.
+		 *
+		 * In this driver the NIC ring starts at RDH = 0,
+		 * RDT points to the first 'busy' slot, so RDT = 0
+		 * means the whole ring is available, and
+		 * RDT = (num_rx_desc - X) means X slots are available.
+		 * Computations are done modulo the ring size.
+		 */
+		if (ifp->if_capenable & IFCAP_NETMAP) {
+			struct netmap_adapter *na = NA(adapter->ifp);
+			struct netmap_kring *kring = &na->rx_rings[i];
+			int t = na->num_rx_desc - kring->nr_hwavail;
+
+			if (t >= na->num_rx_desc)
+				t -= adapter->num_rx_desc;
+			IXGBE_WRITE_REG(hw, IXGBE_RDT(i), t);
+		} else
+#endif /* DEV_NETMAP */
 		IXGBE_WRITE_REG(hw, IXGBE_RDT(i), 0);
 	}
 
@@ -4148,6 +4280,22 @@ ixgbe_rxeof(struct ix_queue *que, int count)
 
 	IXGBE_RX_LOCK(rxr);
 
+#ifdef DEV_NETMAP
+	if (ifp->if_capenable & IFCAP_NETMAP) {
+		/*
+		 * Same as the txeof routine, only wakeup clients
+		 * and make sure there are no deadlocks.
+		 */
+		struct netmap_adapter *na = NA(ifp);
+
+		selwakeuppri(&na->rx_rings[rxr->me].si, PI_NET);
+		IXGBE_RX_UNLOCK(rxr);
+		IXGBE_CORE_LOCK(adapter);
+		selwakeuppri(&na->rx_rings[na->num_queues + 1].si, PI_NET);
+		IXGBE_CORE_UNLOCK(adapter);
+		return (FALSE);
+	}
+#endif /* DEV_NETMAP */
 	for (i = rxr->next_to_check; count != 0;) {
 		struct mbuf	*sendmp, *mh, *mp;
 		u32		rsc, ptype;
diff --git a/sys/dev/ixgbe/ixgbe_osdep.h b/sys/dev/ixgbe/ixgbe_osdep.h
index 03ea5b5..19dbf6b 100644
--- a/sys/dev/ixgbe/ixgbe_osdep.h
+++ b/sys/dev/ixgbe/ixgbe_osdep.h
@@ -95,7 +95,9 @@ typedef uint16_t	u16;
 typedef uint32_t	u32;
 typedef int32_t		s32;
 typedef uint64_t	u64;
+#ifndef __bool_true_false_are_defined
 typedef boolean_t	bool;
+#endif
 
 #define le16_to_cpu 
 
diff --git a/sys/dev/ixgbe/ixv.c b/sys/dev/ixgbe/ixv.c
index e52a527..eaf05d2 100644
--- a/sys/dev/ixgbe/ixv.c
+++ b/sys/dev/ixgbe/ixv.c
@@ -207,7 +207,7 @@ TUNABLE_INT("hw.ixv.flow_control", &ixv_flow_control);
  * it can be a performance win in some workloads, but
  * in others it actually hurts, its off by default.
  */
-static bool ixv_header_split = FALSE;
+static int ixv_header_split = FALSE;
 TUNABLE_INT("hw.ixv.hdr_split", &ixv_header_split);
 
 /*
@@ -2374,7 +2374,7 @@ ixv_free_transmit_buffers(struct tx_ring *txr)
  *
  **********************************************************************/
 
-static boolean_t
+static bool
 ixv_tx_ctx_setup(struct tx_ring *txr, struct mbuf *mp)
 {
 	struct adapter *adapter = txr->adapter;
@@ -2497,7 +2497,7 @@ ixv_tx_ctx_setup(struct tx_ring *txr, struct mbuf *mp)
  *  adapters using advanced tx descriptors
  *
  **********************************************************************/
-static boolean_t
+static bool
 ixv_tso_setup(struct tx_ring *txr, struct mbuf *mp, u32 *paylen)
 {
 	struct adapter *adapter = txr->adapter;
@@ -2586,7 +2586,7 @@ ixv_tso_setup(struct tx_ring *txr, struct mbuf *mp, u32 *paylen)
  *  tx_buffer is put back on the free queue.
  *
  **********************************************************************/
-static boolean_t
+static bool
 ixv_txeof(struct tx_ring *txr)
 {
 	struct adapter	*adapter = txr->adapter;
diff --git a/sys/dev/lge/if_lge.c b/sys/dev/lge/if_lge.c
index c4ddef8..6f69a0a 100644
--- a/sys/dev/lge/if_lge.c
+++ b/sys/dev/lge/if_lge.c
@@ -170,16 +170,12 @@ static device_method_t lge_methods[] = {
 	DEVMETHOD(device_detach,	lge_detach),
 	DEVMETHOD(device_shutdown,	lge_shutdown),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	lge_miibus_readreg),
 	DEVMETHOD(miibus_writereg,	lge_miibus_writereg),
 	DEVMETHOD(miibus_statchg,	lge_miibus_statchg),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t lge_driver = {
diff --git a/sys/dev/malo/if_malo.c b/sys/dev/malo/if_malo.c
index 6a7a786..7305d12 100644
--- a/sys/dev/malo/if_malo.c
+++ b/sys/dev/malo/if_malo.c
@@ -125,10 +125,10 @@ enum {
 
 static MALLOC_DEFINE(M_MALODEV, "malodev", "malo driver dma buffers");
 
-static struct ieee80211vap *malo_vap_create(struct ieee80211com *ic,
-	const char name[IFNAMSIZ], int unit, int opmode, int flags,
-	const uint8_t bssid[IEEE80211_ADDR_LEN],
-	const uint8_t mac[IEEE80211_ADDR_LEN]);
+static struct ieee80211vap *malo_vap_create(struct ieee80211com *,
+		    const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
+		    const uint8_t [IEEE80211_ADDR_LEN],
+		    const uint8_t [IEEE80211_ADDR_LEN]);
 static  void	malo_vap_delete(struct ieee80211vap *);
 static	int	malo_dma_setup(struct malo_softc *);
 static	int	malo_setup_hwdma(struct malo_softc *);
@@ -344,10 +344,10 @@ bad:
 }
 
 static struct ieee80211vap *
-malo_vap_create(struct ieee80211com *ic,
-	const char name[IFNAMSIZ], int unit, int opmode, int flags,
-	const uint8_t bssid[IEEE80211_ADDR_LEN],
-	const uint8_t mac[IEEE80211_ADDR_LEN])
+malo_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
+    enum ieee80211_opmode opmode, int flags,
+    const uint8_t bssid[IEEE80211_ADDR_LEN],
+    const uint8_t mac[IEEE80211_ADDR_LEN])
 {
 	struct ifnet *ifp = ic->ic_ifp;
 	struct malo_vap *mvp;
diff --git a/sys/dev/mca/mca_bus.c b/sys/dev/mca/mca_bus.c
index d3f9313..2b4a0b5 100644
--- a/sys/dev/mca/mca_bus.c
+++ b/sys/dev/mca/mca_bus.c
@@ -507,7 +507,6 @@ static device_method_t mca_methods[] = {
 	DEVMETHOD(bus_probe_nomatch,	mca_probe_nomatch),
 	DEVMETHOD(bus_read_ivar,	mca_read_ivar),
 	DEVMETHOD(bus_write_ivar,	bus_generic_write_ivar),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
 	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
 	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),     
 
@@ -520,7 +519,7 @@ static device_method_t mca_methods[] = {
 	DEVMETHOD(bus_activate_resource,bus_generic_activate_resource),
 	DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t mca_driver = {       
diff --git a/sys/dev/md/md.c b/sys/dev/md/md.c
index 35d5832..8ff52a9 100644
--- a/sys/dev/md/md.c
+++ b/sys/dev/md/md.c
@@ -105,9 +105,11 @@ static MALLOC_DEFINE(M_MD, "md_disk", "Memory Disk");
 static MALLOC_DEFINE(M_MDSECT, "md_sectors", "Memory Disk Sectors");
 
 static int md_debug;
-SYSCTL_INT(_debug, OID_AUTO, mddebug, CTLFLAG_RW, &md_debug, 0, "");
+SYSCTL_INT(_debug, OID_AUTO, mddebug, CTLFLAG_RW, &md_debug, 0,
+    "Enable md(4) debug messages");
 static int md_malloc_wait;
-SYSCTL_INT(_vm, OID_AUTO, md_malloc_wait, CTLFLAG_RW, &md_malloc_wait, 0, "");
+SYSCTL_INT(_vm, OID_AUTO, md_malloc_wait, CTLFLAG_RW, &md_malloc_wait, 0,
+    "Allow malloc to wait for memory allocations");
 
 #if defined(MD_ROOT) && defined(MD_ROOT_SIZE)
 /*
diff --git a/sys/dev/mfi/mfi_pci.c b/sys/dev/mfi/mfi_pci.c
index 8de2e12..952ab1a 100644
--- a/sys/dev/mfi/mfi_pci.c
+++ b/sys/dev/mfi/mfi_pci.c
@@ -93,9 +93,8 @@ static device_method_t mfi_methods[] = {
 	DEVMETHOD(device_detach,	mfi_pci_detach),
 	DEVMETHOD(device_suspend,	mfi_pci_suspend),
 	DEVMETHOD(device_resume,	mfi_pci_resume),
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-	{ 0, 0 }
+
+	DEVMETHOD_END
 };
 
 static driver_t mfi_pci_driver = {
diff --git a/sys/dev/mii/acphy.c b/sys/dev/mii/acphy.c
index 58e546e..c61c05b 100644
--- a/sys/dev/mii/acphy.c
+++ b/sys/dev/mii/acphy.c
@@ -87,7 +87,7 @@ static device_method_t acphy_methods[] = {
 	DEVMETHOD(device_attach,	acphy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t acphy_devclass;
diff --git a/sys/dev/mii/amphy.c b/sys/dev/mii/amphy.c
index c5f5f5c..bd90ccf 100644
--- a/sys/dev/mii/amphy.c
+++ b/sys/dev/mii/amphy.c
@@ -66,7 +66,7 @@ static device_method_t amphy_methods[] = {
 	DEVMETHOD(device_attach,	amphy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t amphy_devclass;
diff --git a/sys/dev/mii/atphy.c b/sys/dev/mii/atphy.c
index b5cf14f..cca8813 100644
--- a/sys/dev/mii/atphy.c
+++ b/sys/dev/mii/atphy.c
@@ -59,7 +59,7 @@ static device_method_t atphy_methods[] = {
 	DEVMETHOD(device_attach,	atphy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ NULL, NULL }
+	DEVMETHOD_END
 };
 
 static devclass_t atphy_devclass;
diff --git a/sys/dev/mii/axphy.c b/sys/dev/mii/axphy.c
index 7e83f4b..78f3901 100644
--- a/sys/dev/mii/axphy.c
+++ b/sys/dev/mii/axphy.c
@@ -56,7 +56,7 @@ static device_method_t axphy_methods[] = {
 	DEVMETHOD(device_attach,	axphy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t axphy_devclass;
diff --git a/sys/dev/mii/bmtphy.c b/sys/dev/mii/bmtphy.c
index 84933b7..81c2bd2 100644
--- a/sys/dev/mii/bmtphy.c
+++ b/sys/dev/mii/bmtphy.c
@@ -91,8 +91,7 @@ static device_method_t bmtphy_methods[] = {
 	DEVMETHOD(device_attach,	bmtphy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t	bmtphy_devclass;
diff --git a/sys/dev/mii/brgphy.c b/sys/dev/mii/brgphy.c
index 2c14ea5..cf924cf 100644
--- a/sys/dev/mii/brgphy.c
+++ b/sys/dev/mii/brgphy.c
@@ -82,7 +82,7 @@ static device_method_t brgphy_methods[] = {
 	DEVMETHOD(device_attach,	brgphy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t brgphy_devclass;
@@ -139,6 +139,9 @@ static const struct mii_phydesc brgphys[] = {
 	MII_PHY_DESC(BROADCOM2, BCM5754),
 	MII_PHY_DESC(BROADCOM2, BCM5761),
 	MII_PHY_DESC(BROADCOM2, BCM5784),
+#ifdef notyet	/* better handled by ukphy(4) until WARs are implemented */
+	MII_PHY_DESC(BROADCOM2, BCM5785),
+#endif
 	MII_PHY_DESC(BROADCOM3, BCM5717C),
 	MII_PHY_DESC(BROADCOM3, BCM5719C),
 	MII_PHY_DESC(BROADCOM3, BCM5720C),
diff --git a/sys/dev/mii/ciphy.c b/sys/dev/mii/ciphy.c
index 2133c76..87d0d81 100644
--- a/sys/dev/mii/ciphy.c
+++ b/sys/dev/mii/ciphy.c
@@ -67,7 +67,7 @@ static device_method_t ciphy_methods[] = {
 	DEVMETHOD(device_attach,	ciphy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t ciphy_devclass;
diff --git a/sys/dev/mii/e1000phy.c b/sys/dev/mii/e1000phy.c
index e657592..91ae44d 100644
--- a/sys/dev/mii/e1000phy.c
+++ b/sys/dev/mii/e1000phy.c
@@ -71,7 +71,7 @@ static device_method_t e1000phy_methods[] = {
 	DEVMETHOD(device_attach,	e1000phy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t e1000phy_devclass;
diff --git a/sys/dev/mii/gentbi.c b/sys/dev/mii/gentbi.c
index bf5319b..05209cf 100644
--- a/sys/dev/mii/gentbi.c
+++ b/sys/dev/mii/gentbi.c
@@ -95,7 +95,7 @@ static device_method_t gentbi_methods[] = {
 	DEVMETHOD(device_attach,	gentbi_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{0, 0}
+	DEVMETHOD_END
 };
 
 static devclass_t gentbi_devclass;
diff --git a/sys/dev/mii/icsphy.c b/sys/dev/mii/icsphy.c
index 90ec374..6330d9e 100644
--- a/sys/dev/mii/icsphy.c
+++ b/sys/dev/mii/icsphy.c
@@ -89,7 +89,7 @@ static device_method_t icsphy_methods[] = {
 	DEVMETHOD(device_attach,	icsphy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t icsphy_devclass;
diff --git a/sys/dev/mii/ip1000phy.c b/sys/dev/mii/ip1000phy.c
index 566b5b0..b7fb515 100644
--- a/sys/dev/mii/ip1000phy.c
+++ b/sys/dev/mii/ip1000phy.c
@@ -63,7 +63,7 @@ static device_method_t ip1000phy_methods[] = {
 	DEVMETHOD(device_attach,	ip1000phy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t ip1000phy_devclass;
@@ -324,7 +324,8 @@ ip1000phy_mii_phy_auto(struct mii_softc *sc, int media)
 	PHY_WRITE(sc, IP1000PHY_MII_ANAR, reg | IP1000PHY_ANAR_CSMA);
 
 	reg = IP1000PHY_1000CR_1000T | IP1000PHY_1000CR_1000T_FDX;
-	reg |= IP1000PHY_1000CR_MASTER;
+	if (sc->mii_mpd_model != MII_MODEL_xxICPLUS_IP1001)
+		reg |= IP1000PHY_1000CR_MASTER;
 	PHY_WRITE(sc, IP1000PHY_MII_1000CR, reg);
 	PHY_WRITE(sc, IP1000PHY_MII_BMCR, (IP1000PHY_BMCR_FDX |
 	    IP1000PHY_BMCR_AUTOEN | IP1000PHY_BMCR_STARTNEG));
diff --git a/sys/dev/mii/jmphy.c b/sys/dev/mii/jmphy.c
index 1e3eb55..14fdf7e 100644
--- a/sys/dev/mii/jmphy.c
+++ b/sys/dev/mii/jmphy.c
@@ -62,7 +62,7 @@ static device_method_t jmphy_methods[] = {
 	DEVMETHOD(device_attach,	jmphy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ NULL, NULL }
+	DEVMETHOD_END
 };
 
 static devclass_t jmphy_devclass;
diff --git a/sys/dev/mii/lxtphy.c b/sys/dev/mii/lxtphy.c
index f223ec6..d7059fb 100644
--- a/sys/dev/mii/lxtphy.c
+++ b/sys/dev/mii/lxtphy.c
@@ -91,7 +91,7 @@ static device_method_t lxtphy_methods[] = {
 	DEVMETHOD(device_attach,	lxtphy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t lxtphy_devclass;
diff --git a/sys/dev/mii/mii.c b/sys/dev/mii/mii.c
index 2c99bc0..f85c579 100644
--- a/sys/dev/mii/mii.c
+++ b/sys/dev/mii/mii.c
@@ -82,7 +82,6 @@ static device_method_t miibus_methods[] = {
 	/* bus interface */
 	DEVMETHOD(bus_print_child,	miibus_print_child),
 	DEVMETHOD(bus_read_ivar,	miibus_read_ivar),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
 	DEVMETHOD(bus_child_pnpinfo_str, miibus_child_pnpinfo_str),
 	DEVMETHOD(bus_child_location_str, miibus_child_location_str),
 	DEVMETHOD(bus_hinted_child,	miibus_hinted_child),
@@ -94,7 +93,7 @@ static device_method_t miibus_methods[] = {
 	DEVMETHOD(miibus_linkchg,	miibus_linkchg),
 	DEVMETHOD(miibus_mediainit,	miibus_mediainit),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 devclass_t miibus_devclass;
@@ -500,7 +499,7 @@ mii_attach(device_t dev, device_t *miibus, struct ifnet *ifp,
 	free(children, M_TEMP);
 
 	if (first != 0) {
-		rv = device_probe(*miibus);
+		rv = device_set_driver(*miibus, &miibus_driver);
 		if (rv != 0)
 			goto fail;
 		bus_enumerate_hinted_children(*miibus);
@@ -512,7 +511,7 @@ mii_attach(device_t dev, device_t *miibus, struct ifnet *ifp,
 			rv = ENXIO;
 			goto fail;
 		}
-		rv = device_attach(*miibus);
+		rv = bus_generic_attach(dev);
 		if (rv != 0)
 			goto fail;
 
@@ -627,7 +626,7 @@ mii_down(struct mii_data *mii)
 static unsigned char
 mii_bitreverse(unsigned char x)
 {
-	unsigned const char const nibbletab[16] = {
+	static unsigned const char const nibbletab[16] = {
 		0, 8, 4, 12, 2, 10, 6, 14, 1, 9, 5, 13, 3, 11, 7, 15
 	};
 
diff --git a/sys/dev/mii/miidevs b/sys/dev/mii/miidevs
index d069c68..3e85261 100644
--- a/sys/dev/mii/miidevs
+++ b/sys/dev/mii/miidevs
@@ -1,5 +1,5 @@
 $FreeBSD$
-/*$NetBSD: miidevs,v 1.99 2011/01/26 18:39:04 bouyer Exp $*/
+/*$NetBSD: miidevs,v 1.104 2011/11/12 11:10:49 sekiya Exp $*/
 
 /*-
  * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
@@ -146,6 +146,7 @@ model xxBROADCOM BCM5214	0x0028 BCM5214 Quad 10/100 media interface
 model xxBROADCOM BCM5221	0x001e BCM5221 10/100 media interface
 model xxBROADCOM BCM5222	0x0032 BCM5222 Dual 10/100 media interface
 model xxBROADCOM BCM4401	0x0036 BCM4401 10/100 media interface
+model xxBROADCOM BCM5365	0x0037 BCM5365 10/100 5-port PHY switch
 model BROADCOM BCM5400		0x0004 BCM5400 1000BASE-T media interface
 model BROADCOM BCM5401		0x0005 BCM5401 1000BASE-T media interface
 model BROADCOM BCM5411		0x0007 BCM5411 1000BASE-T media interface
@@ -164,12 +165,14 @@ model BROADCOM BCM54K2		0x002e BCM54K2 1000BASE-T media interface
 model BROADCOM BCM5714		0x0034 BCM5714 1000BASE-T media interface
 model BROADCOM BCM5780		0x0035 BCM5780 1000BASE-T media interface
 model BROADCOM BCM5708C		0x0036 BCM5708C 1000BASE-T media interface
+model BROADCOM2 BCM5325		0x0003 BCM5325 10/100 5-port PHY switch
 model BROADCOM2 BCM5906		0x0004 BCM5906 10/100baseTX media interface
 model BROADCOM2 BCM5481		0x000a BCM5481 1000BASE-T media interface
 model BROADCOM2 BCM5482		0x000b BCM5482 1000BASE-T media interface
 model BROADCOM2 BCM5755		0x000c BCM5755 1000BASE-T media interface
 model BROADCOM2 BCM5754		0x000e BCM5754/5787 1000BASE-T media interface
 model BROADCOM2 BCM5708S	0x0015 BCM5708S 1000/2500baseSX PHY
+model BROADCOM2 BCM5785		0x0016 BCM5785 1000BASE-T media interface
 model BROADCOM2 BCM5709CAX	0x002c BCM5709CAX 10/100/1000baseT PHY
 model BROADCOM2 BCM5722		0x002d BCM5722 1000BASE-T media interface
 model BROADCOM2 BCM5784		0x003a BCM5784 10/100/1000baseT PHY
@@ -218,6 +221,10 @@ model yyINTEL I82562ET		0x0033 i82562ET 10/100 media interface
 model yyINTEL I82553		0x0035 i82553 10/100 media interface
 model yyINTEL I82566		0x0039 i82566 10/100/1000 media interface
 model INTEL I82577		0x0005 i82577 10/100/1000 media interface
+model INTEL I82579		0x0009 i82579 10/100/1000 media interface
+model xxMARVELL I82563		0x000a i82563 10/100/1000 media interface
+
+model yyINTEL IGP01E1000	0x0038 Intel IGP01E1000 Gigabit PHY
 
 /* Jato Technologies PHYs */
 model xxJATO BASEX		0x0000 Jato 1000baseX media interface
@@ -246,18 +253,24 @@ model xxMARVELL E3082		0x0008 Marvell 88E3082 10/100 Fast Ethernet PHY
 model xxMARVELL E1112		0x0009 Marvell 88E1112 Gigabit PHY
 model xxMARVELL E1149		0x000b Marvell 88E1149 Gigabit PHY
 model xxMARVELL E1111		0x000c Marvell 88E1111 Gigabit PHY
+model xxMARVELL E1145		0x000d Marvell 88E1145 Quad Gigabit PHY
 model xxMARVELL E1116		0x0021 Marvell 88E1116 Gigabit PHY
 model xxMARVELL E1116R		0x0024 Marvell 88E1116R Gigabit PHY
 model xxMARVELL E1118		0x0022 Marvell 88E1118 Gigabit PHY
 model xxMARVELL E1149R		0x0025 Marvell 88E1149R Quad Gigabit PHY
 model xxMARVELL E3016		0x0026 Marvell 88E3016 10/100 Fast Ethernet PHY
 model xxMARVELL PHYG65G		0x0027 Marvell PHYG65G Gigabit PHY
+model xxMARVELL E1116R_29	0x0029 Marvell 88E1116R Gigabit PHY
 model MARVELL E1000		0x0005 Marvell 88E1000 Gigabit PHY
 model MARVELL E1011		0x0002 Marvell 88E1011 Gigabit PHY
 model MARVELL E1000_3		0x0003 Marvell 88E1000 Gigabit PHY
 model MARVELL E1000_5		0x0005 Marvell 88E1000 Gigabit PHY
 model MARVELL E1111		0x000c Marvell 88E1111 Gigabit PHY
 
+/* Myson Technology PHYs */
+model xxMYSON MTD972		0x0000 MTD972 10/100 media interface
+model MYSON MTD803		0x0000 MTD803 3-in-1 media interface
+
 /* National Semiconductor PHYs */
 model xxNATSEMI DP83840		0x0000 DP83840 10/100 media interface
 model xxNATSEMI DP83843		0x0001 DP83843 10/100 media interface
diff --git a/sys/dev/mii/mlphy.c b/sys/dev/mii/mlphy.c
index 3708b4a..f9b1962 100644
--- a/sys/dev/mii/mlphy.c
+++ b/sys/dev/mii/mlphy.c
@@ -84,7 +84,7 @@ static device_method_t mlphy_methods[] = {
 	DEVMETHOD(device_attach,	mlphy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t mlphy_devclass;
diff --git a/sys/dev/mii/nsgphy.c b/sys/dev/mii/nsgphy.c
index cd18acf..988e5c2 100644
--- a/sys/dev/mii/nsgphy.c
+++ b/sys/dev/mii/nsgphy.c
@@ -83,7 +83,7 @@ static device_method_t nsgphy_methods[] = {
 	DEVMETHOD(device_attach,	nsgphy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t nsgphy_devclass;
diff --git a/sys/dev/mii/nsphy.c b/sys/dev/mii/nsphy.c
index 86a69b6..01cd31d 100644
--- a/sys/dev/mii/nsphy.c
+++ b/sys/dev/mii/nsphy.c
@@ -90,7 +90,7 @@ static device_method_t nsphy_methods[] = {
 	DEVMETHOD(device_attach,	nsphy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t nsphy_devclass;
diff --git a/sys/dev/mii/nsphyter.c b/sys/dev/mii/nsphyter.c
index facdebb..316117d 100644
--- a/sys/dev/mii/nsphyter.c
+++ b/sys/dev/mii/nsphyter.c
@@ -93,7 +93,7 @@ static device_method_t nsphyter_methods[] = {
 	DEVMETHOD(device_attach,	nsphyter_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t nsphyter_devclass;
diff --git a/sys/dev/mii/pnaphy.c b/sys/dev/mii/pnaphy.c
index 0e77c4f..29f2c78 100644
--- a/sys/dev/mii/pnaphy.c
+++ b/sys/dev/mii/pnaphy.c
@@ -69,7 +69,7 @@ static device_method_t pnaphy_methods[] = {
 	DEVMETHOD(device_attach,	pnaphy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t pnaphy_devclass;
diff --git a/sys/dev/mii/qsphy.c b/sys/dev/mii/qsphy.c
index a504504..a649e5c 100644
--- a/sys/dev/mii/qsphy.c
+++ b/sys/dev/mii/qsphy.c
@@ -91,7 +91,7 @@ static device_method_t qsphy_methods[] = {
 	DEVMETHOD(device_attach,	qsphy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t qsphy_devclass;
diff --git a/sys/dev/mii/rdcphy.c b/sys/dev/mii/rdcphy.c
index cf5db88..6f7f98d 100644
--- a/sys/dev/mii/rdcphy.c
+++ b/sys/dev/mii/rdcphy.c
@@ -65,7 +65,7 @@ static device_method_t rdcphy_methods[] = {
 	DEVMETHOD(device_attach,	rdcphy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	KOBJMETHOD_END
+	DEVMETHOD_END
 };
 
 static devclass_t rdcphy_devclass;
diff --git a/sys/dev/mii/rgephy.c b/sys/dev/mii/rgephy.c
index 6d54542..d5dbbc8 100644
--- a/sys/dev/mii/rgephy.c
+++ b/sys/dev/mii/rgephy.c
@@ -68,7 +68,7 @@ static device_method_t rgephy_methods[] = {
 	DEVMETHOD(device_attach,	rgephy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t rgephy_devclass;
diff --git a/sys/dev/mii/rlphy.c b/sys/dev/mii/rlphy.c
index b285f7f..ddf8d73 100644
--- a/sys/dev/mii/rlphy.c
+++ b/sys/dev/mii/rlphy.c
@@ -66,7 +66,7 @@ static device_method_t rlphy_methods[] = {
 	DEVMETHOD(device_attach,	rlphy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t rlphy_devclass;
diff --git a/sys/dev/mii/rlswitch.c b/sys/dev/mii/rlswitch.c
index 67c4ec3..b158fd4 100644
--- a/sys/dev/mii/rlswitch.c
+++ b/sys/dev/mii/rlswitch.c
@@ -70,7 +70,7 @@ static device_method_t rlswitch_methods[] = {
 	DEVMETHOD(device_attach,	rlswitch_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t rlswitch_devclass;
diff --git a/sys/dev/mii/smcphy.c b/sys/dev/mii/smcphy.c
index b04a919..fbeaddf 100644
--- a/sys/dev/mii/smcphy.c
+++ b/sys/dev/mii/smcphy.c
@@ -62,8 +62,7 @@ static device_method_t smcphy_methods[] = {
 	DEVMETHOD(device_attach,	smcphy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t smcphy_devclass;
@@ -207,8 +206,7 @@ smcphy_auto(struct mii_softc *sc, int media)
 {
 	uint16_t	anar;
 
-	anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) |
-	    ANAR_CSMA;
+	anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
 	if ((media & IFM_FLOW) != 0 || (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
 		anar |= ANAR_FC;
 	PHY_WRITE(sc, MII_ANAR, anar);
diff --git a/sys/dev/mii/tdkphy.c b/sys/dev/mii/tdkphy.c
index 83868ad..d07327c 100644
--- a/sys/dev/mii/tdkphy.c
+++ b/sys/dev/mii/tdkphy.c
@@ -71,7 +71,7 @@ static device_method_t tdkphy_methods[] = {
 	DEVMETHOD(device_attach,	tdkphy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t tdkphy_devclass;
diff --git a/sys/dev/mii/tlphy.c b/sys/dev/mii/tlphy.c
index c99c754..ac5cff3 100644
--- a/sys/dev/mii/tlphy.c
+++ b/sys/dev/mii/tlphy.c
@@ -97,7 +97,7 @@ static device_method_t tlphy_methods[] = {
 	DEVMETHOD(device_attach,	tlphy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t tlphy_devclass;
diff --git a/sys/dev/mii/truephy.c b/sys/dev/mii/truephy.c
index 86480f1..df17b24 100644
--- a/sys/dev/mii/truephy.c
+++ b/sys/dev/mii/truephy.c
@@ -72,7 +72,7 @@ static device_method_t truephy_methods[] = {
 	DEVMETHOD(device_attach,	truephy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static const struct mii_phydesc truephys[] = {
diff --git a/sys/dev/mii/ukphy.c b/sys/dev/mii/ukphy.c
index 9697176..9d52eb5 100644
--- a/sys/dev/mii/ukphy.c
+++ b/sys/dev/mii/ukphy.c
@@ -86,7 +86,7 @@ static device_method_t ukphy_methods[] = {
 	DEVMETHOD(device_attach,	ukphy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t ukphy_devclass;
diff --git a/sys/dev/mii/xmphy.c b/sys/dev/mii/xmphy.c
index 75d3e27..328d34a 100644
--- a/sys/dev/mii/xmphy.c
+++ b/sys/dev/mii/xmphy.c
@@ -66,7 +66,7 @@ static device_method_t xmphy_methods[] = {
 	DEVMETHOD(device_attach,	xmphy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t xmphy_devclass;
diff --git a/sys/dev/mlx/mlx_pci.c b/sys/dev/mlx/mlx_pci.c
index b39a6b8..00d0fe2 100644
--- a/sys/dev/mlx/mlx_pci.c
+++ b/sys/dev/mlx/mlx_pci.c
@@ -61,9 +61,7 @@ static device_method_t mlx_methods[] = {
     DEVMETHOD(device_suspend,	mlx_suspend),
     DEVMETHOD(device_resume,	mlx_resume),
 
-    DEVMETHOD(bus_print_child,	bus_generic_print_child),
-    DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-    { 0, 0 }
+    DEVMETHOD_END
 };
 
 static driver_t mlx_pci_driver = {
diff --git a/sys/dev/mps/mps_pci.c b/sys/dev/mps/mps_pci.c
index 2c57286..9b27488 100644
--- a/sys/dev/mps/mps_pci.c
+++ b/sys/dev/mps/mps_pci.c
@@ -78,9 +78,8 @@ static device_method_t mps_methods[] = {
 	DEVMETHOD(device_detach,	mps_pci_detach),
 	DEVMETHOD(device_suspend,	mps_pci_suspend),
 	DEVMETHOD(device_resume,	mps_pci_resume),
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-	{ 0, 0 }
+
+	DEVMETHOD_END
 };
 
 static driver_t mps_pci_driver = {
diff --git a/sys/dev/mps/mps_sas.c b/sys/dev/mps/mps_sas.c
index cf4757a..c253ee0 100644
--- a/sys/dev/mps/mps_sas.c
+++ b/sys/dev/mps/mps_sas.c
@@ -937,6 +937,7 @@ mpssas_action(struct cam_sim *sim, union ccb *ccb)
 		cpi->transport_version = 0;
 		cpi->protocol = PROTO_SCSI;
 		cpi->protocol_version = SCSI_REV_SPC;
+		cpi->maxio = MAXPHYS;
 		cpi->ccb_h.status = CAM_REQ_CMP;
 		break;
 	}
diff --git a/sys/dev/msk/if_msk.c b/sys/dev/msk/if_msk.c
index 36407a2..aa08f51 100644
--- a/sys/dev/msk/if_msk.c
+++ b/sys/dev/msk/if_msk.c
@@ -334,11 +334,7 @@ static device_method_t mskc_methods[] = {
 	DEVMETHOD(device_resume,	mskc_resume),
 	DEVMETHOD(device_shutdown,	mskc_shutdown),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
-	{ NULL, NULL }
+	DEVMETHOD_END
 };
 
 static driver_t mskc_driver = {
@@ -356,16 +352,12 @@ static device_method_t msk_methods[] = {
 	DEVMETHOD(device_detach,	msk_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	msk_miibus_readreg),
 	DEVMETHOD(miibus_writereg,	msk_miibus_writereg),
 	DEVMETHOD(miibus_statchg,	msk_miibus_statchg),
 
-	{ NULL, NULL }
+	DEVMETHOD_END
 };
 
 static driver_t msk_driver = {
@@ -656,8 +648,8 @@ msk_rx_fill(struct msk_if_softc *sc_if, int jumbo)
 	if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
 	    (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) {
 		/* Wait until controller executes OP_TCPSTART command. */
-		for (i = 10; i > 0; i--) {
-			DELAY(10);
+		for (i = 100; i > 0; i--) {
+			DELAY(100);
 			idx = CSR_READ_2(sc_if->msk_softc,
 			    Y2_PREF_Q_ADDR(sc_if->msk_rxq,
 			    PREF_UNIT_GET_IDX_REG));
diff --git a/sys/dev/mvs/mvs_pci.c b/sys/dev/mvs/mvs_pci.c
index 36dd93d..7379522 100644
--- a/sys/dev/mvs/mvs_pci.c
+++ b/sys/dev/mvs/mvs_pci.c
@@ -179,7 +179,7 @@ mvs_detach(device_t dev)
 	struct mvs_controller *ctlr = device_get_softc(dev);
 
 	/* Detach & delete all children */
-	device_delete_all_children(dev);
+	device_delete_children(dev);
 
 	/* Free interrupt. */
 	if (ctlr->irq.r_irq) {
diff --git a/sys/dev/mvs/mvs_soc.c b/sys/dev/mvs/mvs_soc.c
index 670bfec..9c5c479 100644
--- a/sys/dev/mvs/mvs_soc.c
+++ b/sys/dev/mvs/mvs_soc.c
@@ -175,7 +175,7 @@ mvs_detach(device_t dev)
 	struct mvs_controller *ctlr = device_get_softc(dev);
 
 	/* Detach & delete all children */
-	device_delete_all_children(dev);
+	device_delete_children(dev);
 
 	/* Free interrupt. */
 	if (ctlr->irq.r_irq) {
diff --git a/sys/dev/mwl/if_mwl.c b/sys/dev/mwl/if_mwl.c
index 5af96ba..bc1a15e 100644
--- a/sys/dev/mwl/if_mwl.c
+++ b/sys/dev/mwl/if_mwl.c
@@ -83,9 +83,9 @@ __FBSDID("$FreeBSD$");
 #define	SM(v,x)	(((v) << x##_S) & x)
 
 static struct ieee80211vap *mwl_vap_create(struct ieee80211com *,
-		    const char name[IFNAMSIZ], int unit, int opmode,
-		    int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
-		    const uint8_t mac[IEEE80211_ADDR_LEN]);
+		    const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
+		    const uint8_t [IEEE80211_ADDR_LEN],
+		    const uint8_t [IEEE80211_ADDR_LEN]);
 static void	mwl_vap_delete(struct ieee80211vap *);
 static int	mwl_setupdma(struct mwl_softc *);
 static int	mwl_hal_reset(struct mwl_softc *sc);
@@ -601,10 +601,10 @@ reclaim_address(struct mwl_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN])
 }
 
 static struct ieee80211vap *
-mwl_vap_create(struct ieee80211com *ic,
-	const char name[IFNAMSIZ], int unit, int opmode, int flags,
-	const uint8_t bssid[IEEE80211_ADDR_LEN],
-	const uint8_t mac0[IEEE80211_ADDR_LEN])
+mwl_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
+    enum ieee80211_opmode opmode, int flags,
+    const uint8_t bssid[IEEE80211_ADDR_LEN],
+    const uint8_t mac0[IEEE80211_ADDR_LEN])
 {
 	struct ifnet *ifp = ic->ic_ifp;
 	struct mwl_softc *sc = ifp->if_softc;
diff --git a/sys/dev/mxge/if_mxge.c b/sys/dev/mxge/if_mxge.c
index 23af286..a33d03f 100644
--- a/sys/dev/mxge/if_mxge.c
+++ b/sys/dev/mxge/if_mxge.c
@@ -2827,7 +2827,7 @@ mxge_media_init(mxge_softc_t *sc)
 	}
 
 	for (i = 0; i < 3; i++, ptr++) {
-		ptr = index(ptr, '-');
+		ptr = strchr(ptr, '-');
 		if (ptr == NULL) {
 			device_printf(sc->dev,
 				      "only %d dashes in PC?!?\n", i);
diff --git a/sys/dev/netmap/if_em_netmap.h b/sys/dev/netmap/if_em_netmap.h
index 0e220e7..d75e924 100644
--- a/sys/dev/netmap/if_em_netmap.h
+++ b/sys/dev/netmap/if_em_netmap.h
@@ -9,7 +9,7 @@
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
- * 
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -25,9 +25,12 @@
 
 /*
  * $FreeBSD$
- * $Id: if_em_netmap.h 9662 2011-11-16 13:18:06Z luigi $
+ * $Id: if_em_netmap.h 9802 2011-12-02 18:42:37Z luigi $
  *
  * netmap changes for if_em.
+ *
+ * For structure and details on the individual functions please see
+ * ixgbe_netmap.h
  */
 
 #include <net/netmap.h>
@@ -58,12 +61,7 @@ em_netmap_attach(struct adapter *adapter)
 	na.nm_rxsync = em_netmap_rxsync;
 	na.nm_lock = em_netmap_lock_wrapper;
 	na.nm_register = em_netmap_reg;
-	/*
-	 * adapter->rx_mbuf_sz is set by SIOCSETMTU, but in netmap mode
-	 * we allocate the buffers on the first register. So we must
-	 * disallow a SIOCSETMTU when if_capenable & IFCAP_NETMAP is set.
-	 */
-	na.buff_size = MCLBYTES;
+	na.buff_size = NETMAP_BUF_SIZE;
 	netmap_attach(&na, adapter->num_queues);
 }
 
@@ -78,7 +76,7 @@ em_netmap_lock_wrapper(void *_a, int what, u_int queueid)
 
 	ASSERT(queueid < adapter->num_queues);
 	switch (what) {
-		case NETMAP_CORE_LOCK:
+	case NETMAP_CORE_LOCK:
 		EM_CORE_LOCK(adapter);
 		break;
 	case NETMAP_CORE_UNLOCK:
@@ -100,6 +98,7 @@ em_netmap_lock_wrapper(void *_a, int what, u_int queueid)
 }
 
 
+// XXX do we need to block/unblock the tasks ?
 static void
 em_netmap_block_tasks(struct adapter *adapter)
 {
@@ -162,9 +161,6 @@ em_netmap_reg(struct ifnet *ifp, int onoff)
 	if (onoff) {
 		ifp->if_capenable |= IFCAP_NETMAP;
 
-		/* save if_transmit for later restore.
-		 * XXX also if_start and if_qflush ?
-		 */
 		na->if_transmit = ifp->if_transmit;
 		ifp->if_transmit = netmap_start;
 
@@ -179,15 +175,13 @@ fail:
 		ifp->if_transmit = na->if_transmit;
 		ifp->if_capenable &= ~IFCAP_NETMAP;
 		em_init_locked(adapter);	/* also enable intr */
-
 	}
 	em_netmap_unblock_tasks(adapter);
 	return (error);
 }
 
 /*
- * Reconcile hardware and user view of the transmit ring, see
- * ixgbe.c for details.
+ * Reconcile hardware and user view of the transmit ring.
  */
 static int
 em_netmap_txsync(void *a, u_int ring_nr, int do_lock)
@@ -197,13 +191,13 @@ em_netmap_txsync(void *a, u_int ring_nr, int do_lock)
 	struct netmap_adapter *na = NA(adapter->ifp);
 	struct netmap_kring *kring = &na->tx_rings[ring_nr];
 	struct netmap_ring *ring = kring->ring;
-	int j, k, n, lim = kring->nkr_num_slots - 1;
+	int j, k, l, n = 0, lim = kring->nkr_num_slots - 1;
 
 	/* generate an interrupt approximately every half ring */
 	int report_frequency = kring->nkr_num_slots >> 1;
 
 	k = ring->cur;
-	if ( (kring->nr_kflags & NR_REINIT) || k > lim)
+	if (k > lim)
 		return netmap_ring_reinit(kring);
 
 	if (do_lock)
@@ -211,35 +205,20 @@ em_netmap_txsync(void *a, u_int ring_nr, int do_lock)
 	bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map,
 			BUS_DMASYNC_POSTREAD);
 
-	/* record completed transmissions TODO
-	 *
-	 * instead of using TDH, we could read the transmitted status bit.
+	/* check for new packets to send.
+	 * j indexes the netmap ring, l indexes the nic ring, and
+	 *	j = kring->nr_hwcur, l = E1000_TDT (not tracked),
+	 *	j == (l + kring->nkr_hwofs) % ring_size
 	 */
-	j = E1000_READ_REG(&adapter->hw, E1000_TDH(ring_nr));
-	if (j >= kring->nkr_num_slots) { /* XXX can happen */
-		D("TDH wrap %d", j);
-		j -= kring->nkr_num_slots;
-	}
-	int delta = j - txr->next_to_clean;
-	if (delta) {
-		/* new transmissions were completed, increment
-		   ring->nr_hwavail. */
-		if (delta < 0)
-			delta += kring->nkr_num_slots;
-		txr->next_to_clean = j;
-		kring->nr_hwavail += delta;
-	}
-
-	/* update avail to what the hardware knows */
-	ring->avail = kring->nr_hwavail;
-
 	j = kring->nr_hwcur;
 	if (j != k) {	/* we have packets to send */
-		n = 0;
+		l = j - kring->nkr_hwofs;
+		if (l < 0)
+			l += lim + 1;
 		while (j != k) {
 			struct netmap_slot *slot = &ring->slot[j];
-			struct e1000_tx_desc *curr = &txr->tx_base[j];
-			struct em_buffer *txbuf = &txr->tx_buffers[j];
+			struct e1000_tx_desc *curr = &txr->tx_base[l];
+			struct em_buffer *txbuf = &txr->tx_buffers[l];
 			int flags = ((slot->flags & NS_REPORT) ||
 				j == 0 || j == report_frequency) ?
 					E1000_TXD_CMD_RS : 0;
@@ -254,42 +233,61 @@ em_netmap_txsync(void *a, u_int ring_nr, int do_lock)
 			slot->flags &= ~NS_REPORT;
 			curr->upper.data = 0;
 			curr->lower.data = 
-			    htole32(
-				adapter->txd_cmd |
-				(E1000_TXD_CMD_EOP | flags) |
-				slot->len);
+			    htole32(adapter->txd_cmd | len |
+				(E1000_TXD_CMD_EOP | flags) );
 			if (slot->flags & NS_BUF_CHANGED) {
 				curr->buffer_addr = htole64(vtophys(addr));
-				/* buffer has changed, unload and reload map */
+				/* buffer has changed, reload map */
 				netmap_reload_map(txr->txtag, txbuf->map,
-					addr, na->buff_size);
+				    addr, na->buff_size);
 				slot->flags &= ~NS_BUF_CHANGED;
 			}
 
 			bus_dmamap_sync(txr->txtag, txbuf->map,
 				BUS_DMASYNC_PREWRITE);
 			j = (j == lim) ? 0 : j + 1;
+			l = (l == lim) ? 0 : l + 1;
 			n++;
 		}
-		kring->nr_hwcur = ring->cur;
+		kring->nr_hwcur = k;
 
 		/* decrease avail by number of sent packets */
-		ring->avail -= n;
-		kring->nr_hwavail = ring->avail;
+		kring->nr_hwavail -= n;
 
 		bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map,
-			BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 
-		E1000_WRITE_REG(&adapter->hw, E1000_TDT(txr->me),
-			ring->cur);
+		E1000_WRITE_REG(&adapter->hw, E1000_TDT(txr->me), l);
 	}
+
+	if (n == 0 || kring->nr_hwavail < 1) {
+		int delta;
+
+		/* record completed transmissions using THD. */
+		l = E1000_READ_REG(&adapter->hw, E1000_TDH(ring_nr));
+		if (l >= kring->nkr_num_slots) { /* XXX can happen */
+			D("TDH wrap %d", l);
+			l -= kring->nkr_num_slots;
+		}
+		delta = l - txr->next_to_clean;
+		if (delta) {
+			/* some completed, increment hwavail. */
+			if (delta < 0)
+				delta += kring->nkr_num_slots;
+			txr->next_to_clean = l;
+			kring->nr_hwavail += delta;
+		}
+	}
+	/* update avail to what the hardware knows */
+	ring->avail = kring->nr_hwavail;
+
 	if (do_lock)
 		EM_TX_UNLOCK(txr);
 	return 0;
 }
 
 /*
- * Reconcile kernel and user view of the receive ring, see ixgbe.c
+ * Reconcile kernel and user view of the receive ring.
  */
 static int
 em_netmap_rxsync(void *a, u_int ring_nr, int do_lock)
@@ -299,10 +297,10 @@ em_netmap_rxsync(void *a, u_int ring_nr, int do_lock)
 	struct netmap_adapter *na = NA(adapter->ifp);
 	struct netmap_kring *kring = &na->rx_rings[ring_nr];
 	struct netmap_ring *ring = kring->ring;
-	int j, k, n, lim = kring->nkr_num_slots - 1;
+	int j, k, l, n, lim = kring->nkr_num_slots - 1;
 
 	k = ring->cur;
-	if ( (kring->nr_kflags & NR_REINIT) || k > lim)
+	if (k > lim)
 		return netmap_ring_reinit(kring);
  
 	if (do_lock)
@@ -311,36 +309,52 @@ em_netmap_rxsync(void *a, u_int ring_nr, int do_lock)
 	bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map,
 			BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 
-	/* acknowledge all the received packets. */
-	j = rxr->next_to_check;
+	/* import newly received packets into the netmap ring.
+	 * j is an index in the netmap ring, l in the NIC ring, and
+	 *	j = (kring->nr_hwcur + kring->nr_hwavail) % ring_size
+	 *	l = rxr->next_to_check;
+	 * and
+	 *	j == (l + kring->nkr_hwofs) % ring_size
+	 */
+	l = rxr->next_to_check;
+	j = l + kring->nkr_hwofs;
+	/* here nkr_hwofs can be negative so must check for j < 0 */
+	if (j < 0)
+		j += lim + 1;
+	else if (j > lim)
+		j -= lim + 1;
 	for (n = 0; ; n++) {
-		struct e1000_rx_desc *curr = &rxr->rx_base[j];
+		struct e1000_rx_desc *curr = &rxr->rx_base[l];
 
 		if ((curr->status & E1000_RXD_STAT_DD) == 0)
 			break;
 		ring->slot[j].len = le16toh(curr->length);
-		bus_dmamap_sync(rxr->tag, rxr->rx_buffers[j].map,
+		bus_dmamap_sync(rxr->rxtag, rxr->rx_buffers[l].map,
 			BUS_DMASYNC_POSTREAD);
 		j = (j == lim) ? 0 : j + 1;
+		/* make sure next_to_refresh follows next_to_check */
+		rxr->next_to_refresh = l;	// XXX
+		l = (l == lim) ? 0 : l + 1;
 	}
 	if (n) {
-		rxr->next_to_check = j;
+		rxr->next_to_check = l;
 		kring->nr_hwavail += n;
 	}
 
-	/* skip past packets that userspace has already processed:
-	 * making them available for reception.
-	 * advance nr_hwcur and issue a bus_dmamap_sync on the
-	 * buffers so it is safe to write to them.
-	 * Also increase nr_hwavail
-         */
+	/* skip past packets that userspace has already processed */
 	j = kring->nr_hwcur;
 	if (j != k) { /* userspace has read some packets. */
 		n = 0;
+		l = j - kring->nkr_hwofs; /* NIC ring index */
+		/* here nkr_hwofs can be negative so check for l > lim */
+		if (l < 0)
+			l += lim + 1;
+		else if (l > lim)
+			l -= lim + 1;
 		while (j != k) {
 			struct netmap_slot *slot = &ring->slot[j];
-			struct e1000_rx_desc *curr = &rxr->rx_base[j];
-			struct em_buffer *rxbuf = &rxr->rx_buffers[j];
+			struct e1000_rx_desc *curr = &rxr->rx_base[l];
+			struct em_buffer *rxbuf = &rxr->rx_buffers[l];
 			void *addr = NMB(slot);
 
 			if (addr == netmap_buffer_base) { /* bad buf */
@@ -352,28 +366,29 @@ em_netmap_rxsync(void *a, u_int ring_nr, int do_lock)
 			curr->status = 0;
 			if (slot->flags & NS_BUF_CHANGED) {
 				curr->buffer_addr = htole64(vtophys(addr));
-				/* buffer has changed, unload and reload map */
+				/* buffer has changed, reload map */
 				netmap_reload_map(rxr->rxtag, rxbuf->map,
-					addr, na->buff_size);
+				    addr, na->buff_size);
 				slot->flags &= ~NS_BUF_CHANGED;
 			}
 
 			bus_dmamap_sync(rxr->rxtag, rxbuf->map,
-				BUS_DMASYNC_PREREAD);
+			    BUS_DMASYNC_PREREAD);
 
 			j = (j == lim) ? 0 : j + 1;
+			l = (l == lim) ? 0 : l + 1;
 			n++;
 		}
 		kring->nr_hwavail -= n;
-		kring->nr_hwcur = ring->cur;
+		kring->nr_hwcur = k;
 		bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map,
-			BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 		/*
 		 * IMPORTANT: we must leave one free slot in the ring,
-		 * so move j back by one unit
+		 * so move l back by one unit
 		 */
-		j = (j == 0) ? lim : j - 1;
-		E1000_WRITE_REG(&adapter->hw, E1000_RDT(rxr->me), j);
+		l = (l == 0) ? lim : l - 1;
+		E1000_WRITE_REG(&adapter->hw, E1000_RDT(rxr->me), l);
 	}
 	/* tell userspace that there are new packets */
 	ring->avail = kring->nr_hwavail ;
diff --git a/sys/dev/netmap/if_igb_netmap.h b/sys/dev/netmap/if_igb_netmap.h
index 0c14706..5e41742 100644
--- a/sys/dev/netmap/if_igb_netmap.h
+++ b/sys/dev/netmap/if_igb_netmap.h
@@ -25,7 +25,7 @@
 
 /*
  * $FreeBSD$
- * $Id: if_igb_netmap.h 9662 2011-11-16 13:18:06Z luigi $
+ * $Id: if_igb_netmap.h 9802 2011-12-02 18:42:37Z luigi $
  *
  * netmap modifications for igb
  * contribured by Ahmed Kooli
@@ -58,12 +58,7 @@ igb_netmap_attach(struct adapter *adapter)
 	na.nm_rxsync = igb_netmap_rxsync;
 	na.nm_lock = igb_netmap_lock_wrapper;
 	na.nm_register = igb_netmap_reg;
-	/*
-	 * adapter->rx_mbuf_sz is set by SIOCSETMTU, but in netmap mode
-	 * we allocate the buffers on the first register. So we must
-	 * disallow a SIOCSETMTU when if_capenable & IFCAP_NETMAP is set.
-	 */
-	na.buff_size = MCLBYTES;
+	na.buff_size = NETMAP_BUF_SIZE;
 	netmap_attach(&na, adapter->num_queues);
 }	
 
@@ -111,7 +106,7 @@ igb_netmap_reg(struct ifnet *ifp, int onoff)
 	struct netmap_adapter *na = NA(ifp);
 	int error = 0;
 
-	if (!na)
+	if (na == NULL)
 		return EINVAL;
 
 	igb_disable_intr(adapter);
@@ -144,21 +139,6 @@ fail:
 
 /*
  * Reconcile kernel and user view of the transmit ring.
- *
- * Userspace has filled tx slots up to cur (excluded).
- * The last unused slot previously known to the kernel was nr_hwcur,
- * and the last interrupt reported nr_hwavail slots available
- * (using the special value -1 to indicate idle transmit ring).
- * The function must first update avail to what the kernel
- * knows, subtract the newly used slots (cur - nr_hwcur)
- * from both avail and nr_hwavail, and set nr_hwcur = cur
- * issuing a dmamap_sync on all slots.
- *
- * Check parameters in the struct netmap_ring.
- * We don't use avail, only check for bogus values.
- * Make sure cur is valid, and same goes for buffer indexes and lengths.
- * To avoid races, read the values once, and never use those from
- * the ring afterwards.
  */
 static int
 igb_netmap_txsync(void *a, u_int ring_nr, int do_lock)
@@ -168,54 +148,39 @@ igb_netmap_txsync(void *a, u_int ring_nr, int do_lock)
 	struct netmap_adapter *na = NA(adapter->ifp);
 	struct netmap_kring *kring = &na->tx_rings[ring_nr];
 	struct netmap_ring *ring = kring->ring;
-	int j, k, n, lim = kring->nkr_num_slots - 1;
+	int j, k, l, n = 0, lim = kring->nkr_num_slots - 1;
 
 	/* generate an interrupt approximately every half ring */
 	int report_frequency = kring->nkr_num_slots >> 1;
 
-	k = ring->cur;	/* ring is not protected by any lock */
-	if ( (kring->nr_kflags & NR_REINIT) || k > lim)
+	k = ring->cur;
+	if (k > lim)
 		return netmap_ring_reinit(kring);
 
 	if (do_lock)
 		IGB_TX_LOCK(txr);
 	bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map,
-			BUS_DMASYNC_POSTREAD);
-
-	/* record completed transmissions. TODO
-	 *
-	 * Instead of reading from the TDH register, we could and try to check
-	 * the status bit of descriptor packets.
-	 */
-	j = E1000_READ_REG(&adapter->hw, E1000_TDH(ring_nr));
-	if (j >= kring->nkr_num_slots) /* XXX can it happen ? */
-		j -= kring->nkr_num_slots;
-	int delta = j - txr->next_to_clean;
-	if (delta) {
-		/* new tx were completed */
-		if (delta < 0)
-			delta += kring->nkr_num_slots;
-		txr->next_to_clean = j;
-		kring->nr_hwavail += delta;
-	}
+	    BUS_DMASYNC_POSTREAD);
 
 	/* update avail to what the hardware knows */
 	ring->avail = kring->nr_hwavail;
 
-	j = kring->nr_hwcur;
+	j = kring->nr_hwcur; /* netmap ring index */
 	if (j != k) {	/* we have new packets to send */
 		u32 olinfo_status = 0;
-		n = 0;
 
+		l = j - kring->nkr_hwofs; /* NIC ring index */
+		if (l < 0)
+			l += lim + 1;
 		/* 82575 needs the queue index added */
 		if (adapter->hw.mac.type == e1000_82575)
 			olinfo_status |= txr->me << 4;
 
 		while (j != k) {
 			struct netmap_slot *slot = &ring->slot[j];
-			struct igb_tx_buffer *txbuf = &txr->tx_buffers[j];
+			struct igb_tx_buffer *txbuf = &txr->tx_buffers[l];
 			union e1000_adv_tx_desc *curr =
-				(union e1000_adv_tx_desc *)&txr->tx_base[j];
+			    (union e1000_adv_tx_desc *)&txr->tx_base[l];
 			void *addr = NMB(slot);
 			int flags = ((slot->flags & NS_REPORT) ||
 				j == 0 || j == report_frequency) ?
@@ -229,6 +194,7 @@ igb_netmap_txsync(void *a, u_int ring_nr, int do_lock)
 			}
 
 			slot->flags &= ~NS_REPORT;
+			// XXX do we need to set the address ?
 			curr->read.buffer_addr = htole64(vtophys(addr));
 			curr->read.olinfo_status =
 			    htole32(olinfo_status |
@@ -239,7 +205,7 @@ igb_netmap_txsync(void *a, u_int ring_nr, int do_lock)
 				    E1000_ADVTXD_DCMD_DEXT |
 				    E1000_ADVTXD_DCMD_EOP | flags);
 			if (slot->flags & NS_BUF_CHANGED) {
-				/* buffer has changed, unload and reload map */
+				/* buffer has changed, reload map */
 				netmap_reload_map(txr->txtag, txbuf->map,
 					addr, na->buff_size);
 				slot->flags &= ~NS_BUF_CHANGED;
@@ -248,22 +214,40 @@ igb_netmap_txsync(void *a, u_int ring_nr, int do_lock)
 			bus_dmamap_sync(txr->txtag, txbuf->map,
 				BUS_DMASYNC_PREWRITE);
 			j = (j == lim) ? 0 : j + 1;
+			l = (l == lim) ? 0 : l + 1;
 			n++;
 		}
 		kring->nr_hwcur = k;
 
 		/* decrease avail by number of sent packets */
-		ring->avail -= n;
-		kring->nr_hwavail = ring->avail;
+		kring->nr_hwavail -= n;
+		ring->avail = kring->nr_hwavail;
 
-		/* Set the watchdog */
+		/* Set the watchdog XXX ? */
 		txr->queue_status = IGB_QUEUE_WORKING;
 		txr->watchdog_time = ticks;
 
 		bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map,
-			BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 
-		E1000_WRITE_REG(&adapter->hw, E1000_TDT(txr->me), k);
+		E1000_WRITE_REG(&adapter->hw, E1000_TDT(txr->me), l);
+	}
+	if (n == 0 || kring->nr_hwavail < 1) {
+		int delta;
+
+		/* record completed transmission using TDH */
+		l = E1000_READ_REG(&adapter->hw, E1000_TDH(ring_nr));
+		if (l >= kring->nkr_num_slots) /* XXX can it happen ? */
+			l -= kring->nkr_num_slots;
+		delta = l - txr->next_to_clean;
+		if (delta) {
+			/* new tx were completed */
+			if (delta < 0)
+				delta += kring->nkr_num_slots;
+			txr->next_to_clean = l;
+			kring->nr_hwavail += delta;
+			ring->avail = kring->nr_hwavail;
+		}
 	}
 	if (do_lock)
 		IGB_TX_UNLOCK(txr);
@@ -273,15 +257,6 @@ igb_netmap_txsync(void *a, u_int ring_nr, int do_lock)
 
 /*
  * Reconcile kernel and user view of the receive ring.
- *
- * Userspace has read rx slots up to cur (excluded).
- * The last unread slot previously known to the kernel was nr_hwcur,
- * and the last interrupt reported nr_hwavail slots available.
- * We must subtract the newly consumed slots (cur - nr_hwcur)
- * from nr_hwavail, clearing the descriptors for the next
- * read, tell the hardware that they are available,
- * and set nr_hwcur = cur and avail = nr_hwavail.
- * issuing a dmamap_sync on all slots.
  */
 static int
 igb_netmap_rxsync(void *a, u_int ring_nr, int do_lock)
@@ -291,10 +266,10 @@ igb_netmap_rxsync(void *a, u_int ring_nr, int do_lock)
 	struct netmap_adapter *na = NA(adapter->ifp);
 	struct netmap_kring *kring = &na->rx_rings[ring_nr];
 	struct netmap_ring *ring = kring->ring;
-	int j, k, n, lim = kring->nkr_num_slots - 1;
+	int j, k, l, n, lim = kring->nkr_num_slots - 1;
 
-	k = ring->cur;	/* ring is not protected by any lock */
-	if ( (kring->nr_kflags & NR_REINIT) || k > lim)
+	k = ring->cur;
+	if (k > lim)
 		return netmap_ring_reinit(kring);
 
 	if (do_lock)
@@ -304,9 +279,12 @@ igb_netmap_rxsync(void *a, u_int ring_nr, int do_lock)
 	bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map,
 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 
-	j = rxr->next_to_check;
+	l = rxr->next_to_check;
+	j = l + kring->nkr_hwofs;
+	if (j > lim)
+		j -= lim + 1;
 	for (n = 0; ; n++) {
-		union e1000_adv_rx_desc *curr = &rxr->rx_base[j];
+		union e1000_adv_rx_desc *curr = &rxr->rx_base[l];
 		uint32_t staterr = le32toh(curr->wb.upper.status_error);
 
 		if ((staterr & E1000_RXD_STAT_DD) == 0)
@@ -314,15 +292,13 @@ igb_netmap_rxsync(void *a, u_int ring_nr, int do_lock)
 		ring->slot[j].len = le16toh(curr->wb.upper.length);
 		
 		bus_dmamap_sync(rxr->ptag,
-			rxr->rx_buffers[j].pmap, BUS_DMASYNC_POSTREAD);
+			rxr->rx_buffers[l].pmap, BUS_DMASYNC_POSTREAD);
 		j = (j == lim) ? 0 : j + 1;
+		l = (l == lim) ? 0 : l + 1;
 	}
 	if (n) {
-		rxr->next_to_check = j;
+		rxr->next_to_check = l;
 		kring->nr_hwavail += n;
-		if (kring->nr_hwavail >= lim - 10) {
-			ND("rx ring %d almost full %d", ring_nr, kring->nr_hwavail);
-		}
 	}
 
 	/* skip past packets that userspace has already processed,
@@ -332,12 +308,15 @@ igb_netmap_rxsync(void *a, u_int ring_nr, int do_lock)
 	 * Also increase nr_hwavail
 	 */
 	j = kring->nr_hwcur;
+	l = kring->nr_hwcur - kring->nkr_hwofs;
+	if (l < 0)
+		l += lim + 1;
 	if (j != k) {	/* userspace has read some packets. */
 		n = 0;
 		while (j != k) {
 			struct netmap_slot *slot = ring->slot + j;
-			union e1000_adv_rx_desc *curr = &rxr->rx_base[j];
-			struct igb_rx_buf *rxbuf = rxr->rx_buffers + j;
+			union e1000_adv_rx_desc *curr = &rxr->rx_base[l];
+			struct igb_rx_buf *rxbuf = rxr->rx_buffers + l;
 			void *addr = NMB(slot);
 
 			if (addr == netmap_buffer_base) { /* bad buf */
@@ -358,6 +337,7 @@ igb_netmap_rxsync(void *a, u_int ring_nr, int do_lock)
 				BUS_DMASYNC_PREREAD);
 
 			j = (j == lim) ? 0 : j + 1;
+			l = (l == lim) ? 0 : l + 1;
 			n++;
 		}
 		kring->nr_hwavail -= n;
@@ -365,10 +345,10 @@ igb_netmap_rxsync(void *a, u_int ring_nr, int do_lock)
 		bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map,
 			BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 		/* IMPORTANT: we must leave one free slot in the ring,
-		 * so move j back by one unit
+		 * so move l back by one unit
 		 */
-		j = (j == 0) ? lim : j - 1;
-		E1000_WRITE_REG(&adapter->hw, E1000_RDT(rxr->me), j);
+		l = (l == 0) ? lim : l - 1;
+		E1000_WRITE_REG(&adapter->hw, E1000_RDT(rxr->me), l);
 	}
 	/* tell userspace that there are new packets */
 	ring->avail = kring->nr_hwavail ;
diff --git a/sys/dev/netmap/if_lem_netmap.h b/sys/dev/netmap/if_lem_netmap.h
index a8f3498..ae64cd6 100644
--- a/sys/dev/netmap/if_lem_netmap.h
+++ b/sys/dev/netmap/if_lem_netmap.h
@@ -25,9 +25,12 @@
 
 /*
  * $FreeBSD$
- * $Id: if_lem_netmap.h 9662 2011-11-16 13:18:06Z luigi $
+ * $Id: if_lem_netmap.h 9802 2011-12-02 18:42:37Z luigi $
  *
  * netmap support for if_lem.c
+ *
+ * For structure and details on the individual functions please see
+ * ixgbe_netmap.h
  */
 
 #include <net/netmap.h>
@@ -59,7 +62,7 @@ lem_netmap_attach(struct adapter *adapter)
 	na.nm_rxsync = lem_netmap_rxsync;
 	na.nm_lock = lem_netmap_lock_wrapper;
 	na.nm_register = lem_netmap_reg;
-	na.buff_size = MCLBYTES;
+	na.buff_size = NETMAP_BUF_SIZE;
 	netmap_attach(&na, 1);
 }
 
@@ -94,7 +97,61 @@ lem_netmap_lock_wrapper(void *_a, int what, u_int ringid)
 
 
 /*
- * Reconcile kernel and user view of the transmit ring. see ixgbe.c
+ * Register/unregister routine
+ */
+static int
+lem_netmap_reg(struct ifnet *ifp, int onoff)
+{
+	struct adapter *adapter = ifp->if_softc;
+	struct netmap_adapter *na = NA(ifp);
+	int error = 0;
+
+	if (na == NULL)
+		return EINVAL;
+
+	lem_disable_intr(adapter);
+
+	/* Tell the stack that the interface is no longer active */
+	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
+
+	/* lem_netmap_block_tasks(adapter); */
+#ifndef EM_LEGACY_IRQ // XXX do we need this ?
+	taskqueue_block(adapter->tq);
+	taskqueue_drain(adapter->tq, &adapter->rxtx_task);
+	taskqueue_drain(adapter->tq, &adapter->link_task);
+#endif /* !EM_LEGCY_IRQ */
+	if (onoff) {
+		ifp->if_capenable |= IFCAP_NETMAP;
+
+		/* save if_transmit to restore it when exiting.
+		 * XXX what about if_start and if_qflush ?
+		 */
+		na->if_transmit = ifp->if_transmit;
+		ifp->if_transmit = netmap_start;
+
+		lem_init_locked(adapter);
+		if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) == 0) {
+			error = ENOMEM;
+			goto fail;
+		}
+	} else {
+fail:
+		/* restore non-netmap mode */
+		ifp->if_transmit = na->if_transmit;
+		ifp->if_capenable &= ~IFCAP_NETMAP;
+		lem_init_locked(adapter);	/* also enables intr */
+	}
+
+#ifndef EM_LEGACY_IRQ
+	taskqueue_unblock(adapter->tq); // XXX do we need this ?
+#endif /* !EM_LEGCY_IRQ */
+
+	return (error);
+}
+
+
+/*
+ * Reconcile kernel and user view of the transmit ring.
  */
 static int
 lem_netmap_txsync(void *a, u_int ring_nr, int do_lock)
@@ -103,13 +160,13 @@ lem_netmap_txsync(void *a, u_int ring_nr, int do_lock)
 	struct netmap_adapter *na = NA(adapter->ifp);
 	struct netmap_kring *kring = &na->tx_rings[0];
 	struct netmap_ring *ring = kring->ring;
-	int j, k, n, lim = kring->nkr_num_slots - 1;
+	int j, k, l, n = 0, lim = kring->nkr_num_slots - 1;
 
 	/* generate an interrupt approximately every half ring */
 	int report_frequency = kring->nkr_num_slots >> 1;
 
 	k = ring->cur;
-	if ( (kring->nr_kflags & NR_REINIT) || k > lim)
+	if (k > lim)
 		return netmap_ring_reinit(kring);
 
 	if (do_lock)
@@ -117,33 +174,18 @@ lem_netmap_txsync(void *a, u_int ring_nr, int do_lock)
 	bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map,
 			BUS_DMASYNC_POSTREAD);
 
-	/* record completed transmissions TODO
-	 *
-	 * instead of using TDH, we could read the transmitted status bit.
-	 */
-	j = E1000_READ_REG(&adapter->hw, E1000_TDH(0));
-	if (j >= kring->nkr_num_slots) { /* can it happen ? */
-		D("bad TDH %d", j);
-		j -= kring->nkr_num_slots;
-	}
-	int delta = j - adapter->next_tx_to_clean;
-	if (delta) {
-		if (delta < 0)
-			delta += kring->nkr_num_slots;
-		adapter->next_tx_to_clean = j;
-		kring->nr_hwavail += delta;
-	}
-
 	/* update avail to what the hardware knows */
 	ring->avail = kring->nr_hwavail;
 
-	j = kring->nr_hwcur;
+	j = kring->nr_hwcur; /* points into the netmap ring */
 	if (j != k) {	/* we have new packets to send */
-		n = 0;
+		l = j - kring->nkr_hwofs; /* points into the NIC ring */
+		if (l < 0)
+			l += lim + 1;
 		while (j != k) {
 			struct netmap_slot *slot = &ring->slot[j];
-			struct e1000_tx_desc *curr = &adapter->tx_desc_base[j];
-			struct em_buffer *txbuf = &adapter->tx_buffer_area[j];
+			struct e1000_tx_desc *curr = &adapter->tx_desc_base[l];
+			struct em_buffer *txbuf = &adapter->tx_buffer_area[l];
 			void *addr = NMB(slot);
 			int flags = ((slot->flags & NS_REPORT) ||
 				j == 0 || j == report_frequency) ?
@@ -156,34 +198,54 @@ lem_netmap_txsync(void *a, u_int ring_nr, int do_lock)
 				return netmap_ring_reinit(kring);
 			}
 
+			slot->flags &= ~NS_REPORT;
 			curr->upper.data = 0;
-			/* always interrupt. XXX make it conditional */
 			curr->lower.data =
 			    htole32( adapter->txd_cmd | len |
 				(E1000_TXD_CMD_EOP | flags) );
 			if (slot->flags & NS_BUF_CHANGED) {
 				curr->buffer_addr = htole64(vtophys(addr));
-				/* buffer has changed, unload and reload map */
+				/* buffer has changed, reload map */
 				netmap_reload_map(adapter->txtag, txbuf->map,
-					addr, na->buff_size);
+				    addr, na->buff_size);
 				slot->flags &= ~NS_BUF_CHANGED;
 			}
 
 			bus_dmamap_sync(adapter->txtag, txbuf->map,
-				BUS_DMASYNC_PREWRITE);
+			    BUS_DMASYNC_PREWRITE);
 			j = (j == lim) ? 0 : j + 1;
+			l = (l == lim) ? 0 : l + 1;
 			n++;
 		}
-		kring->nr_hwcur = ring->cur;
+		kring->nr_hwcur = k;
 
 		/* decrease avail by number of sent packets */
-		ring->avail -= n;
-		kring->nr_hwavail = ring->avail;
+		kring->nr_hwavail -= n;
+		ring->avail = kring->nr_hwavail;
 
 		bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map,
-				BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 
-		E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), ring->cur);
+		E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), l);
+	}
+
+	if (n == 0 || kring->nr_hwavail < 1) {
+		int delta;
+
+		/* record completed transmissions using TDH */
+		l = E1000_READ_REG(&adapter->hw, E1000_TDH(0));
+		if (l >= kring->nkr_num_slots) { /* can it happen ? */
+			D("bad TDH %d", l);
+			l -= kring->nkr_num_slots;
+		}
+		delta = l - adapter->next_tx_to_clean;
+		if (delta) {
+			if (delta < 0)
+				delta += kring->nkr_num_slots;
+			adapter->next_tx_to_clean = l;
+			kring->nr_hwavail += delta;
+			ring->avail = kring->nr_hwavail;
+		}
 	}
 	if (do_lock)
 		EM_TX_UNLOCK(adapter);
@@ -192,7 +254,7 @@ lem_netmap_txsync(void *a, u_int ring_nr, int do_lock)
 
 
 /*
- * Reconcile kernel and user view of the receive ring. see ixgbe.c
+ * Reconcile kernel and user view of the receive ring.
  */
 static int
 lem_netmap_rxsync(void *a, u_int ring_nr, int do_lock)
@@ -201,10 +263,10 @@ lem_netmap_rxsync(void *a, u_int ring_nr, int do_lock)
 	struct netmap_adapter *na = NA(adapter->ifp);
 	struct netmap_kring *kring = &na->rx_rings[0];
 	struct netmap_ring *ring = kring->ring;
-	int j, k, n, lim = kring->nkr_num_slots - 1;
+	int j, k, l, n, lim = kring->nkr_num_slots - 1;
 
 	k = ring->cur;
-	if ( (kring->nr_kflags & NR_REINIT) || k > lim)
+	if (k > lim)
 		return netmap_ring_reinit(kring);
 
 	if (do_lock)
@@ -213,40 +275,45 @@ lem_netmap_rxsync(void *a, u_int ring_nr, int do_lock)
 	bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map,
 			BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 
-	/* acknowldge all the received packets. */
-	j = adapter->next_rx_desc_to_check;
+	/* import newly received packets into the netmap ring */
+	l = adapter->next_rx_desc_to_check; /* points into the NIC ring */
+	j = l + kring->nkr_hwofs; /* points into the netmap ring */
+	if (j > lim)
+		j -= lim + 1;
 	for (n = 0; ; n++) {
-		struct e1000_rx_desc *curr = &adapter->rx_desc_base[j];
-		int len = le16toh(adapter->rx_desc_base[j].length) - 4; // CRC
+		struct e1000_rx_desc *curr = &adapter->rx_desc_base[l];
+		int len;
 
 		if ((curr->status & E1000_RXD_STAT_DD) == 0)
 			break;
+		len = le16toh(curr->length) - 4; // CRC
 
 		if (len < 0) {
 			D("bogus pkt size at %d", j);
 			len = 0;
 		}
 		ring->slot[j].len = len;
-		bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[j].map,
-			BUS_DMASYNC_POSTREAD);
+		bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[l].map,
+		    BUS_DMASYNC_POSTREAD);
 		j = (j == lim) ? 0 : j + 1;
+		l = (l == lim) ? 0 : l + 1;
 	}
 	if (n) {
-		adapter->next_rx_desc_to_check = j;
+		adapter->next_rx_desc_to_check = l;
 		kring->nr_hwavail += n;
 	}
 
-	/* skip past packets that userspace has already processed,
-	 * making them available for reception. We don't need to set
-	 * the length as it is the same for all slots.
-	 */
-	j = kring->nr_hwcur;
+	/* skip past packets that userspace has already processed */
+	j = kring->nr_hwcur; /* netmap ring index */
 	if (j != k) {	/* userspace has read some packets. */
 		n = 0;
+		l = j - kring->nkr_hwofs; /* NIC ring index */
+		if (l < 0)
+			l += lim + 1;
 		while (j != k) {
 			struct netmap_slot *slot = &ring->slot[j];
-			struct e1000_rx_desc *curr = &adapter->rx_desc_base[j];
-			struct em_buffer *rxbuf = &adapter->rx_buffer_area[j];
+			struct e1000_rx_desc *curr = &adapter->rx_desc_base[l];
+			struct em_buffer *rxbuf = &adapter->rx_buffer_area[l];
 			void *addr = NMB(slot);
 
 			if (addr == netmap_buffer_base) { /* bad buf */
@@ -254,32 +321,32 @@ lem_netmap_rxsync(void *a, u_int ring_nr, int do_lock)
 					EM_RX_UNLOCK(adapter);
 				return netmap_ring_reinit(kring);
 			}
-			curr = &adapter->rx_desc_base[j];
 			curr->status = 0;
 			if (slot->flags & NS_BUF_CHANGED) {
 				curr->buffer_addr = htole64(vtophys(addr));
-				/* buffer has changed, unload and reload map */
+				/* buffer has changed, and reload map */
 				netmap_reload_map(adapter->rxtag, rxbuf->map,
-					addr, na->buff_size);
+				    addr, na->buff_size);
 				slot->flags &= ~NS_BUF_CHANGED;
 			}
 
 			bus_dmamap_sync(adapter->rxtag, rxbuf->map,
-				BUS_DMASYNC_PREREAD);
+			    BUS_DMASYNC_PREREAD);
 
 			j = (j == lim) ? 0 : j + 1;
+			l = (l == lim) ? 0 : l + 1;
 			n++;
 		}
 		kring->nr_hwavail -= n;
-		kring->nr_hwcur = ring->cur;
+		kring->nr_hwcur = k;
 		bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map,
-			BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 		/*
 		 * IMPORTANT: we must leave one free slot in the ring,
-		 * so move j back by one unit
+		 * so move l back by one unit
 		 */
-		j = (j == 0) ? lim : j - 1;
-		E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), j);
+		l = (l == 0) ? lim : l - 1;
+		E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), l);
 	}
 
 	/* tell userspace that there are new packets */
@@ -290,55 +357,3 @@ lem_netmap_rxsync(void *a, u_int ring_nr, int do_lock)
 }
 
 
-/*
- * Register/unregister routine
- */
-static int
-lem_netmap_reg(struct ifnet *ifp, int onoff)
-{
-	struct adapter *adapter = ifp->if_softc;
-	struct netmap_adapter *na = NA(ifp);
-	int error = 0;
-
-	if (!na)
-		return EINVAL;
-
-	lem_disable_intr(adapter);
-
-	/* Tell the stack that the interface is no longer active */
-	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
-
-	/* lem_netmap_block_tasks(adapter); */
-#ifndef EM_LEGACY_IRQ
-	taskqueue_block(adapter->tq);
-	taskqueue_drain(adapter->tq, &adapter->rxtx_task);
-	taskqueue_drain(adapter->tq, &adapter->link_task);
-#endif /* !EM_LEGCY_IRQ */
-	if (onoff) {
-		ifp->if_capenable |= IFCAP_NETMAP;
-
-		/* save if_transmit to restore it when exiting.
-		 * XXX what about if_start and if_qflush ?
-		 */
-		na->if_transmit = ifp->if_transmit;
-		ifp->if_transmit = netmap_start;
-
-		lem_init_locked(adapter);
-		if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) == 0) {
-			error = ENOMEM;
-			goto fail;
-		}
-	} else {
-fail:
-		/* restore non-netmap mode */
-		ifp->if_transmit = na->if_transmit;
-		ifp->if_capenable &= ~IFCAP_NETMAP;
-		lem_init_locked(adapter);	/* also enables intr */
-	}
-
-#ifndef EM_LEGACY_IRQ
-	taskqueue_unblock(adapter->tq);
-#endif /* !EM_LEGCY_IRQ */
-
-	return (error);
-}
diff --git a/sys/dev/netmap/if_re_netmap.h b/sys/dev/netmap/if_re_netmap.h
index efccf3a..105660c 100644
--- a/sys/dev/netmap/if_re_netmap.h
+++ b/sys/dev/netmap/if_re_netmap.h
@@ -25,7 +25,7 @@
 
 /*
  * $FreeBSD$
- * $Id: if_re_netmap.h 9662 2011-11-16 13:18:06Z luigi $
+ * $Id: if_re_netmap.h 9802 2011-12-02 18:42:37Z luigi $
  *
  * netmap support for if_re
  */
@@ -56,7 +56,7 @@ re_netmap_attach(struct rl_softc *sc)
 	na.nm_rxsync = re_netmap_rxsync;
 	na.nm_lock = re_netmap_lock_wrapper;
 	na.nm_register = re_netmap_reg;
-	na.buff_size = MCLBYTES;
+	na.buff_size = NETMAP_BUF_SIZE;
 	netmap_attach(&na, 1);
 }
 
@@ -99,7 +99,7 @@ re_netmap_reg(struct ifnet *ifp, int onoff)
 	struct netmap_adapter *na = NA(ifp);
 	int error = 0;
 
-	if (!na)
+	if (na == NULL)
 		return EINVAL;
 	/* Tell the stack that the interface is no longer active */
 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
@@ -109,9 +109,8 @@ re_netmap_reg(struct ifnet *ifp, int onoff)
 	if (onoff) {
 		ifp->if_capenable |= IFCAP_NETMAP;
 
-		/* save if_transmit and restore it */
+		/* save if_transmit to restore it later */
 		na->if_transmit = ifp->if_transmit;
-		/* XXX if_start and if_qflush ??? */
 		ifp->if_transmit = netmap_start;
 
 		re_init_locked(adapter);
@@ -127,23 +126,12 @@ fail:
 		ifp->if_capenable &= ~IFCAP_NETMAP;
 		re_init_locked(adapter);	/* also enables intr */
 	}
-    return (error);
-
+	return (error);
 }
 
 
 /*
  * Reconcile kernel and user view of the transmit ring.
- *
- * Userspace has filled tx slots up to cur (excluded).
- * The last unused slot previously known to the kernel was nr_hwcur,
- * and the last interrupt reported nr_hwavail slots available
- * (using the special value -1 to indicate idle transmit ring).
- * The function must first update avail to what the kernel
- * knows (translating the -1 to nkr_num_slots - 1),
- * subtract the newly used slots (cur - nr_hwcur)
- * from both avail and nr_hwavail, and set nr_hwcur = cur
- * issuing a dmamap_sync on all slots.
  */
 static int
 re_netmap_txsync(void *a, u_int ring_nr, int do_lock)
@@ -153,10 +141,10 @@ re_netmap_txsync(void *a, u_int ring_nr, int do_lock)
 	struct netmap_adapter *na = NA(sc->rl_ifp);
 	struct netmap_kring *kring = &na->tx_rings[ring_nr];
 	struct netmap_ring *ring = kring->ring;
-	int j, k, n, lim = kring->nkr_num_slots - 1;
+	int j, k, l, n, lim = kring->nkr_num_slots - 1;
 
 	k = ring->cur;
-	if ( (kring->nr_kflags & NR_REINIT) || k > lim)
+	if (k > lim)
 		return netmap_ring_reinit(kring);
 
 	if (do_lock)
@@ -167,17 +155,18 @@ re_netmap_txsync(void *a, u_int ring_nr, int do_lock)
             sc->rl_ldata.rl_tx_list_map,
             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 
+	/* XXX move after the transmissions */
 	/* record completed transmissions */
-        for (n = 0, j = sc->rl_ldata.rl_tx_considx;
-	    j != sc->rl_ldata.rl_tx_prodidx;
-	    n++, j = RL_TX_DESC_NXT(sc, j)) {
+        for (n = 0, l = sc->rl_ldata.rl_tx_considx;
+	    l != sc->rl_ldata.rl_tx_prodidx;
+	    n++, l = RL_TX_DESC_NXT(sc, l)) {
 		uint32_t cmdstat =
-			le32toh(sc->rl_ldata.rl_tx_list[j].rl_cmdstat);
+			le32toh(sc->rl_ldata.rl_tx_list[l].rl_cmdstat);
 		if (cmdstat & RL_TDESC_STAT_OWN)
 			break;
 	}
 	if (n > 0) {
-		sc->rl_ldata.rl_tx_considx = j;
+		sc->rl_ldata.rl_tx_considx = l;
 		sc->rl_ldata.rl_tx_free += n;
 		kring->nr_hwavail += n;
 	}
@@ -185,13 +174,13 @@ re_netmap_txsync(void *a, u_int ring_nr, int do_lock)
 	/* update avail to what the hardware knows */
 	ring->avail = kring->nr_hwavail;
 	
-	/* we trust prodidx, not hwcur */
-	j = kring->nr_hwcur = sc->rl_ldata.rl_tx_prodidx;
+	j = kring->nr_hwcur;
 	if (j != k) {	/* we have new packets to send */
 		n = 0;
+		l = sc->rl_ldata.rl_tx_prodidx;
 		while (j != k) {
 			struct netmap_slot *slot = &ring->slot[j];
-			struct rl_desc *desc = &sc->rl_ldata.rl_tx_list[j];
+			struct rl_desc *desc = &sc->rl_ldata.rl_tx_list[l];
 			int cmd = slot->len | RL_TDESC_CMD_EOF |
 				RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF ;
 			void *addr = NMB(slot);
@@ -200,10 +189,11 @@ re_netmap_txsync(void *a, u_int ring_nr, int do_lock)
 			if (addr == netmap_buffer_base || len > NETMAP_BUF_SIZE) {
 				if (do_lock)
 					RL_UNLOCK(sc);
+				// XXX what about prodidx ?
 				return netmap_ring_reinit(kring);
 			}
 			
-			if (j == lim)	/* mark end of ring */
+			if (l == lim)	/* mark end of ring */
 				cmd |= RL_TDESC_CMD_EOR;
 
 			if (slot->flags & NS_BUF_CHANGED) {
@@ -212,17 +202,19 @@ re_netmap_txsync(void *a, u_int ring_nr, int do_lock)
 				desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(paddr));
 				/* buffer has changed, unload and reload map */
 				netmap_reload_map(sc->rl_ldata.rl_tx_mtag,
-					txd[j].tx_dmamap, addr, na->buff_size);
+					txd[l].tx_dmamap, addr, na->buff_size);
 				slot->flags &= ~NS_BUF_CHANGED;
 			}
 			slot->flags &= ~NS_REPORT;
 			desc->rl_cmdstat = htole32(cmd);
 			bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
-				txd[j].tx_dmamap, BUS_DMASYNC_PREWRITE);
+				txd[l].tx_dmamap, BUS_DMASYNC_PREWRITE);
 			j = (j == lim) ? 0 : j + 1;
+			l = (l == lim) ? 0 : l + 1;
 			n++;
 		}
-		sc->rl_ldata.rl_tx_prodidx = kring->nr_hwcur = ring->cur;
+		sc->rl_ldata.rl_tx_prodidx = l;
+		kring->nr_hwcur = k;
 
 		/* decrease avail by number of sent packets */
 		ring->avail -= n;
@@ -243,15 +235,6 @@ re_netmap_txsync(void *a, u_int ring_nr, int do_lock)
 
 /*
  * Reconcile kernel and user view of the receive ring.
- *
- * Userspace has read rx slots up to cur (excluded).
- * The last unread slot previously known to the kernel was nr_hwcur,
- * and the last interrupt reported nr_hwavail slots available.
- * We must subtract the newly consumed slots (cur - nr_hwcur)
- * from nr_hwavail, clearing the descriptors for the next
- * read, tell the hardware that they are available,
- * and set nr_hwcur = cur and avail = nr_hwavail.
- * issuing a dmamap_sync on all slots.
  */
 static int
 re_netmap_rxsync(void *a, u_int ring_nr, int do_lock)
@@ -261,10 +244,10 @@ re_netmap_rxsync(void *a, u_int ring_nr, int do_lock)
 	struct netmap_adapter *na = NA(sc->rl_ifp);
 	struct netmap_kring *kring = &na->rx_rings[ring_nr];
 	struct netmap_ring *ring = kring->ring;
-	int j, k, n, lim = kring->nkr_num_slots - 1;
+	int j, k, l, n, lim = kring->nkr_num_slots - 1;
 
 	k = ring->cur;
-	if ( (kring->nr_kflags & NR_REINIT) || k > lim)
+	if (k > lim)
 		return netmap_ring_reinit(kring);
 
 	if (do_lock)
@@ -280,9 +263,10 @@ re_netmap_rxsync(void *a, u_int ring_nr, int do_lock)
 	 * cleared (all buffers could have it cleared. The easiest one
 	 * is to limit the amount of data reported up to 'lim'
 	 */
-	j = sc->rl_ldata.rl_rx_prodidx;
+	l = sc->rl_ldata.rl_rx_prodidx; /* next pkt to check */
+	j = l + kring->nkr_hwofs;
 	for (n = kring->nr_hwavail; n < lim ; n++) {
-		struct rl_desc *cur_rx = &sc->rl_ldata.rl_rx_list[j];
+		struct rl_desc *cur_rx = &sc->rl_ldata.rl_rx_list[l];
 		uint32_t rxstat = le32toh(cur_rx->rl_cmdstat);
 		uint32_t total_len;
 
@@ -294,11 +278,12 @@ re_netmap_rxsync(void *a, u_int ring_nr, int do_lock)
 		kring->ring->slot[j].len = total_len;
 		/*  sync was in re_newbuf() */
 		bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
-		    rxd[j].rx_dmamap, BUS_DMASYNC_POSTREAD);
-		j = RL_RX_DESC_NXT(sc, j);
+		    rxd[l].rx_dmamap, BUS_DMASYNC_POSTREAD);
+		j = (j == lim) ? 0 : j + 1;
+		l = (l == lim) ? 0 : l + 1;
 	}
 	if (n != kring->nr_hwavail) {
-		sc->rl_ldata.rl_rx_prodidx = j;
+		sc->rl_ldata.rl_rx_prodidx = l;
 		sc->rl_ifp->if_ipackets += n - kring->nr_hwavail;
 		kring->nr_hwavail = n;
 	}
@@ -312,9 +297,12 @@ re_netmap_rxsync(void *a, u_int ring_nr, int do_lock)
 	j = kring->nr_hwcur;
 	if (j != k) {	/* userspace has read some packets. */
 		n = 0;
+		l = kring->nr_hwcur - kring->nkr_hwofs;
+		if (l < 0)
+			l += lim + 1;
 		while (j != k) {
 			struct netmap_slot *slot = ring->slot + j;
-			struct rl_desc *desc = &sc->rl_ldata.rl_rx_list[j];
+			struct rl_desc *desc = &sc->rl_ldata.rl_rx_list[l];
 			int cmd = na->buff_size | RL_RDESC_CMD_OWN;
 			void *addr = NMB(slot);
 
@@ -324,7 +312,7 @@ re_netmap_rxsync(void *a, u_int ring_nr, int do_lock)
 				return netmap_ring_reinit(kring);
 			}
 
-			if (j == lim)	/* mark end of ring */
+			if (l == lim)	/* mark end of ring */
 				cmd |= RL_RDESC_CMD_EOR;
 
 			desc->rl_cmdstat = htole32(cmd);
@@ -334,12 +322,13 @@ re_netmap_rxsync(void *a, u_int ring_nr, int do_lock)
 				desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(paddr));
 				desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(paddr));
 				netmap_reload_map(sc->rl_ldata.rl_rx_mtag,
-					rxd[j].rx_dmamap, addr, na->buff_size);
+					rxd[l].rx_dmamap, addr, na->buff_size);
 				slot->flags &= ~NS_BUF_CHANGED;
 			}
 			bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
-				rxd[j].rx_dmamap, BUS_DMASYNC_PREREAD);
+				rxd[l].rx_dmamap, BUS_DMASYNC_PREREAD);
 			j = (j == lim) ? 0 : j + 1;
+			l = (l == lim) ? 0 : l + 1;
 			n++;
 		}
 		kring->nr_hwavail -= n;
@@ -351,18 +340,22 @@ re_netmap_rxsync(void *a, u_int ring_nr, int do_lock)
 		    BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
 	}
 	/* tell userspace that there are new packets */
-	ring->avail = kring->nr_hwavail ;
+	ring->avail = kring->nr_hwavail;
 	if (do_lock)
 		RL_UNLOCK(sc);
 	return 0;
 }
 
+/*
+ * Additional routines to init the tx and rx rings.
+ * In other drivers we do that inline in the main code.
+ */
 static void
 re_netmap_tx_init(struct rl_softc *sc)
 {   
 	struct rl_txdesc *txd;
 	struct rl_desc *desc;
-	int i;
+	int i, n;
 	struct netmap_adapter *na = NA(sc->rl_ifp);
 	struct netmap_slot *slot = netmap_reset(na, NR_TX, 0, 0);
 
@@ -372,11 +365,20 @@ re_netmap_tx_init(struct rl_softc *sc)
 	/* in netmap mode, overwrite addresses and maps */
 	txd = sc->rl_ldata.rl_tx_desc;
 	desc = sc->rl_ldata.rl_tx_list;
+	n = sc->rl_ldata.rl_tx_desc_cnt;
+
+	/* l points in the netmap ring, i points in the NIC ring */
+	for (i = 0; i < n; i++) {
+		void *addr;
+		uint64_t paddr;
+		struct netmap_kring *kring = &na->tx_rings[0];
+		int l = i + kring->nkr_hwofs;
 
-	for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
-		void *addr = NMB(slot+i);
-		uint64_t paddr = vtophys(addr);
+		if (l >= n)
+			l -= n;
 
+		addr = NMB(slot + l);
+		paddr = vtophys(addr);
 		desc[i].rl_bufaddr_lo = htole32(RL_ADDR_LO(paddr));
 		desc[i].rl_bufaddr_hi = htole32(RL_ADDR_HI(paddr));
 		netmap_load_map(sc->rl_ldata.rl_tx_mtag,
@@ -387,26 +389,39 @@ re_netmap_tx_init(struct rl_softc *sc)
 static void
 re_netmap_rx_init(struct rl_softc *sc)
 {
-	/* slot is NULL if we are not in netmap mode */  
 	struct netmap_adapter *na = NA(sc->rl_ifp);
 	struct netmap_slot *slot = netmap_reset(na, NR_RX, 0, 0);
 	struct rl_desc *desc = sc->rl_ldata.rl_rx_list;
 	uint32_t cmdstat;
-	int i;
+	int i, n;
 
 	if (!slot)
 		return;
-
-	for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
-		void *addr = NMB(slot+i);
-		uint64_t paddr = vtophys(addr);
-
+	n = sc->rl_ldata.rl_rx_desc_cnt;
+	for (i = 0; i < n; i++) {
+		void *addr;
+		uint64_t paddr;
+		struct netmap_kring *kring = &na->rx_rings[0];
+		int l = i + kring->nkr_hwofs;
+
+		if (l >= n)
+			l -= n;
+
+		addr = NMB(slot + l);
+		paddr = vtophys(addr);
 		desc[i].rl_bufaddr_lo = htole32(RL_ADDR_LO(paddr));
 		desc[i].rl_bufaddr_hi = htole32(RL_ADDR_HI(paddr));
-		cmdstat = slot[i].len = na->buff_size; // XXX
-		if (i == sc->rl_ldata.rl_rx_desc_cnt - 1)
+		cmdstat = na->buff_size;
+		if (i == n - 1)
 			cmdstat |= RL_RDESC_CMD_EOR;
-		desc[i].rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
+		/*
+		 * userspace knows that hwavail packets were ready before the
+		 * reset, so we need to tell the NIC that last hwavail
+		 * descriptors of the ring are still owned by the driver.
+		 */
+		if (i < n - 1 - kring->nr_hwavail) // XXX + 1 ?
+			cmdstat |= RL_RDESC_CMD_OWN;
+		desc[i].rl_cmdstat = htole32(cmdstat);
 
 		netmap_reload_map(sc->rl_ldata.rl_rx_mtag,
 			sc->rl_ldata.rl_rx_desc[i].rx_dmamap,
diff --git a/sys/dev/netmap/ixgbe_netmap.h b/sys/dev/netmap/ixgbe_netmap.h
index a4d5491..fdf15d8 100644
--- a/sys/dev/netmap/ixgbe_netmap.h
+++ b/sys/dev/netmap/ixgbe_netmap.h
@@ -25,25 +25,48 @@
 
 /*
  * $FreeBSD$
- * $Id: ixgbe_netmap.h 9662 2011-11-16 13:18:06Z luigi $
+ * $Id: ixgbe_netmap.h 9802 2011-12-02 18:42:37Z luigi $
  *
  * netmap modifications for ixgbe
+ *
+ * This file is meant to be a reference on how to implement
+ * netmap support for a network driver.
+ * This file contains code but only static or inline functions
+ * that are used by a single driver. To avoid replication of
+ * code we just #include it near the beginning of the
+ * standard driver.
  */
 
 #include <net/netmap.h>
 #include <sys/selinfo.h>
-// #include <vm/vm.h>
-// #include <vm/pmap.h>    /* vtophys ? */
+/*
+ * Some drivers may need the following headers. Others
+ * already include them by default
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+
+ */
+
 #include <dev/netmap/netmap_kern.h>
 
+/*
+ * prototypes for the new API calls that are used by the
+ * *_netmap_attach() routine.
+ */
 static int	ixgbe_netmap_reg(struct ifnet *, int onoff);
 static int	ixgbe_netmap_txsync(void *, u_int, int);
 static int	ixgbe_netmap_rxsync(void *, u_int, int);
 static void	ixgbe_netmap_lock_wrapper(void *, int, u_int);
 
 
-SYSCTL_NODE(_dev, OID_AUTO, ixgbe, CTLFLAG_RW, 0, "ixgbe card");
-
+/*
+ * The attach routine, called near the end of ixgbe_attach(),
+ * fills the parameters for netmap_attach() and calls it.
+ * It cannot fail, in the worst case (such as no memory)
+ * netmap mode will be disabled and the driver will only
+ * operate in standard mode.
+ */
 static void
 ixgbe_netmap_attach(struct adapter *adapter)
 {
@@ -52,7 +75,7 @@ ixgbe_netmap_attach(struct adapter *adapter)
 	bzero(&na, sizeof(na));
 
 	na.ifp = adapter->ifp;
-	na.separate_locks = 1;
+	na.separate_locks = 1;	/* this card has separate rx/tx locks */
 	na.num_tx_desc = adapter->num_tx_desc;
 	na.num_rx_desc = adapter->num_rx_desc;
 	na.nm_txsync = ixgbe_netmap_txsync;
@@ -60,17 +83,18 @@ ixgbe_netmap_attach(struct adapter *adapter)
 	na.nm_lock = ixgbe_netmap_lock_wrapper;
 	na.nm_register = ixgbe_netmap_reg;
 	/*
+	 * XXX where do we put this comment ?
 	 * adapter->rx_mbuf_sz is set by SIOCSETMTU, but in netmap mode
 	 * we allocate the buffers on the first register. So we must
 	 * disallow a SIOCSETMTU when if_capenable & IFCAP_NETMAP is set.
 	 */
-	na.buff_size = MCLBYTES;
+	na.buff_size = NETMAP_BUF_SIZE;
 	netmap_attach(&na, adapter->num_queues);
 }	
 
 
 /*
- * wrapper to export locks to the generic code
+ * wrapper to export locks to the generic netmap code.
  */
 static void
 ixgbe_netmap_lock_wrapper(void *_a, int what, u_int queueid)
@@ -102,8 +126,8 @@ ixgbe_netmap_lock_wrapper(void *_a, int what, u_int queueid)
 
 
 /*
- * support for netmap register/unregisted. We are already under core lock.
- * only called on the first init or the last unregister.
+ * Netmap register/unregister. We are already under core lock.
+ * Only called on the first register or the last unregister.
  */
 static int
 ixgbe_netmap_reg(struct ifnet *ifp, int onoff)
@@ -112,7 +136,7 @@ ixgbe_netmap_reg(struct ifnet *ifp, int onoff)
 	struct netmap_adapter *na = NA(ifp);
 	int error = 0;
 
-	if (!na)
+	if (!na) /* probably, netmap_attach() failed */
 		return EINVAL;
 
 	ixgbe_disable_intr(adapter);
@@ -120,23 +144,28 @@ ixgbe_netmap_reg(struct ifnet *ifp, int onoff)
 	/* Tell the stack that the interface is no longer active */
 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
 
-	if (onoff) {
+	if (onoff) { /* enable netmap mode */
 		ifp->if_capenable |= IFCAP_NETMAP;
 
-		/* save if_transmit to restore it later */
+		/* save if_transmit and replace with our routine */
 		na->if_transmit = ifp->if_transmit;
 		ifp->if_transmit = netmap_start;
 
+		/*
+		 * reinitialize the adapter, now with netmap flag set,
+		 * so the rings will be set accordingly.
+		 */
 		ixgbe_init_locked(adapter);
 		if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) == 0) {
 			error = ENOMEM;
 			goto fail;
 		}
-	} else {
+	} else { /* reset normal mode (explicit request or netmap failed) */
 fail:
 		/* restore if_transmit */
 		ifp->if_transmit = na->if_transmit;
 		ifp->if_capenable &= ~IFCAP_NETMAP;
+		/* initialize the card, this time in standard mode */
 		ixgbe_init_locked(adapter);	/* also enables intr */
 	}
 	return (error);
@@ -145,21 +174,23 @@ fail:
 
 /*
  * Reconcile kernel and user view of the transmit ring.
+ * This routine might be called frequently so it must be efficient.
+ *
+ * Userspace has filled tx slots up to ring->cur (excluded).
+ * The last unused slot previously known to the kernel was kring->nkr_hwcur,
+ * and the last interrupt reported kring->nr_hwavail slots available.
  *
- * Userspace has filled tx slots up to cur (excluded).
- * The last unused slot previously known to the kernel was nr_hwcur,
- * and the last interrupt reported nr_hwavail slots available
- * (using the special value -1 to indicate idle transmit ring).
- * The function must first update avail to what the kernel
- * knows, subtract the newly used slots (cur - nr_hwcur)
- * from both avail and nr_hwavail, and set nr_hwcur = cur
+ * This function runs under lock (acquired from the caller or internally).
+ * It must first update ring->avail to what the kernel knows,
+ * subtract the newly used slots (ring->cur - kring->nkr_hwcur)
+ * from both avail and nr_hwavail, and set ring->nkr_hwcur = ring->cur
  * issuing a dmamap_sync on all slots.
  *
- * Check parameters in the struct netmap_ring.
- * We don't use avail, only check for bogus values.
- * Make sure cur is valid, and same goes for buffer indexes and lengths.
- * To avoid races, read the values once, and never use those from
- * the ring afterwards.
+ * Since ring comes from userspace, its content must be read only once,
+ * and validated before being used to update the kernel's structures.
+ * (this is also true for every use of ring in the kernel).
+ *
+ * ring->avail is never used, only checked for bogus values.
  */
 static int
 ixgbe_netmap_txsync(void *a, u_int ring_nr, int do_lock)
@@ -169,42 +200,96 @@ ixgbe_netmap_txsync(void *a, u_int ring_nr, int do_lock)
 	struct netmap_adapter *na = NA(adapter->ifp);
 	struct netmap_kring *kring = &na->tx_rings[ring_nr];
 	struct netmap_ring *ring = kring->ring;
-	int j, k, n = 0, lim = kring->nkr_num_slots - 1;
+	int j, k, l, n = 0, lim = kring->nkr_num_slots - 1;
 
-	/* generate an interrupt approximately every half ring */
+	/*
+	 * ixgbe can generate an interrupt on every tx packet, but it
+	 * seems very expensive, so we interrupt once every half ring,
+	 * or when requested with NS_REPORT
+	 */
 	int report_frequency = kring->nkr_num_slots >> 1;
 
-	k = ring->cur;	/* ring is not protected by any lock */
-	if ( (kring->nr_kflags & NR_REINIT) || k > lim)
-		return netmap_ring_reinit(kring);
-
 	if (do_lock)
 		IXGBE_TX_LOCK(txr);
+	/* take a copy of ring->cur now, and never read it again */
+	k = ring->cur;
+	l = k - kring->nr_hwcur;
+	if (l < 0)
+		l += lim + 1;
+	/* if cur is invalid reinitialize the ring. */
+	if (k > lim || l > kring->nr_hwavail) {
+		if (do_lock)
+			IXGBE_TX_UNLOCK(txr);
+		return netmap_ring_reinit(kring);
+	}
+
 	bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map,
 			BUS_DMASYNC_POSTREAD);
 
-	/* update avail to what the hardware knows */
-	ring->avail = kring->nr_hwavail;
-
+	/*
+	 * Process new packets to send. j is the current index in the
+	 * netmap ring, l is the corresponding index in the NIC ring.
+	 * The two numbers differ because upon a *_init() we reset
+	 * the NIC ring but leave the netmap ring unchanged.
+	 * For the transmit ring, we have
+	 *
+	 *		j = kring->nr_hwcur
+	 *		l = IXGBE_TDT (not tracked in the driver)
+	 * and
+	 * 		j == (l + kring->nkr_hwofs) % ring_size
+	 *
+	 * In this driver kring->nkr_hwofs >= 0, but for other
+	 * drivers it might be negative as well.
+	 */
 	j = kring->nr_hwcur;
 	if (j != k) {	/* we have new packets to send */
+		l = j - kring->nkr_hwofs;
+		if (l < 0)	/* wraparound */
+			l += lim + 1;
+
 		while (j != k) {
+			/*
+			 * Collect per-slot info.
+			 * Note that txbuf and curr are indexed by l.
+			 *
+			 * In this driver we collect the buffer address
+			 * (using the NMB() macro) because we always
+			 * need to rewrite it into the NIC ring.
+			 * Many other drivers preserve the address, so
+			 * we only need to access it if NS_BUF_CHANGED
+			 * is set.
+			 */
 			struct netmap_slot *slot = &ring->slot[j];
-			struct ixgbe_tx_buf *txbuf = &txr->tx_buffers[j];
-			union ixgbe_adv_tx_desc *curr = &txr->tx_base[j];
+			struct ixgbe_tx_buf *txbuf = &txr->tx_buffers[l];
+			union ixgbe_adv_tx_desc *curr = &txr->tx_base[l];
 			void *addr = NMB(slot);
+			// XXX type for flags and len ?
 			int flags = ((slot->flags & NS_REPORT) ||
 				j == 0 || j == report_frequency) ?
 					IXGBE_TXD_CMD_RS : 0;
 			int len = slot->len;
 
+			/*
+			 * Quick check for valid addr and len.
+			 * NMB() returns netmap_buffer_base for invalid
+			 * buffer indexes (but the address is still a
+			 * valid one to be used in a ring). slot->len is
+			 * unsigned so no need to check for negative values.
+			 */
 			if (addr == netmap_buffer_base || len > NETMAP_BUF_SIZE) {
+ring_reset:
 				if (do_lock)
 					IXGBE_TX_UNLOCK(txr);
 				return netmap_ring_reinit(kring);
 			}
 
 			slot->flags &= ~NS_REPORT;
+			/*
+			 * Fill the slot in the NIC ring.
+			 * In this driver we need to rewrite the buffer
+			 * address in the NIC ring. Other drivers do not
+			 * need this.
+			 */
 			curr->read.buffer_addr = htole64(vtophys(addr));
 			curr->read.olinfo_status = 0;
 			curr->read.cmd_type_len =
@@ -212,6 +297,10 @@ ixgbe_netmap_txsync(void *a, u_int ring_nr, int do_lock)
 				(IXGBE_ADVTXD_DTYP_DATA |
 				    IXGBE_ADVTXD_DCMD_IFCS |
 				    IXGBE_TXD_CMD_EOP | flags) );
+			/* If the buffer has changed, unload and reload map
+			 * (and possibly the physical address in the NIC
+			 * slot, but we did it already).
+			 */
 			if (slot->flags & NS_BUF_CHANGED) {
 				/* buffer has changed, unload and reload map */
 				netmap_reload_map(txr->txtag, txbuf->map,
@@ -219,69 +308,89 @@ ixgbe_netmap_txsync(void *a, u_int ring_nr, int do_lock)
 				slot->flags &= ~NS_BUF_CHANGED;
 			}
 
+			/* make sure changes to the buffer are synced */
 			bus_dmamap_sync(txr->txtag, txbuf->map,
 				BUS_DMASYNC_PREWRITE);
 			j = (j == lim) ? 0 : j + 1;
+			l = (l == lim) ? 0 : l + 1;
 			n++;
 		}
-		kring->nr_hwcur = k;
+		kring->nr_hwcur = k; /* the saved ring->cur */
 
 		/* decrease avail by number of sent packets */
-		ring->avail -= n;
-		kring->nr_hwavail = ring->avail;
+		kring->nr_hwavail -= n;
 
+		/* synchronize the NIC ring */
 		bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map,
 			BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
-
-		IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(txr->me), k);
+		/* (re)start the transmitter up to slot l (excluded) */
+		IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(txr->me), l);
 	}
 
+	/*
+	 * If no packets are sent, or there is no room in the tx ring,
+	 * Check whether there are completed transmissions.
+	 * Because this is expensive (we need a register etc.)
+	 * we only do it if absolutely necessary, i.e. there is no room
+	 * in the tx ring, or where were no completed transmissions
+	 * (meaning that probably the caller really wanted to check
+	 * for completed transmissions).
+	 */
 	if (n == 0 || kring->nr_hwavail < 1) {
-		/* record completed transmissions. TODO
+		int delta;
+
+		/*
+		 * Record completed transmissions.
+		 * We (re)use the driver's txr->next_to_clean to keep
+		 * track of the most recently completed transmission.
 		 *
 		 * The datasheet discourages the use of TDH to find out the
-		 * number of sent packets; the right way to do so, is to check
-		 * the DD bit inside the status of a packet descriptor.  On the
-		 * other hand, we avoid to set the `report status' bit for
-		 * *all* outgoing packets (kind of interrupt mitigation),
-		 * consequently the DD bit is not guaranteed to be set for all
-		 * the packets: thats way, for the moment we continue to use
-		 * TDH.
+		 * number of sent packets. We should rather check the DD
+		 * status bit in a packet descriptor. However, we only set
+		 * the "report status" bit for some descriptors (a kind of
+		 * interrupt mitigation), so we can only check on those.
+		 * For the time being we use TDH, as we do it infrequently
+		 * enough not to pose performance problems.
 		 */
-		j = IXGBE_READ_REG(&adapter->hw, IXGBE_TDH(ring_nr));
-		if (j >= kring->nkr_num_slots) { /* XXX can happen */
-			D("TDH wrap %d", j);
-			j -= kring->nkr_num_slots;
+		l = IXGBE_READ_REG(&adapter->hw, IXGBE_TDH(ring_nr));
+		if (l >= kring->nkr_num_slots) { /* XXX can happen */
+			D("TDH wrap %d", l);
+			l -= kring->nkr_num_slots;
 		}
-		int delta = j - txr->next_to_clean;
+		delta = l - txr->next_to_clean;
 		if (delta) {
-			/* new transmissions were completed, increment
-			   ring->nr_hwavail. */
+			/* some tx completed, increment avail */
 			if (delta < 0)
 				delta += kring->nkr_num_slots;
-			txr->next_to_clean = j;
+			txr->next_to_clean = l;
 			kring->nr_hwavail += delta;
-			ring->avail = kring->nr_hwavail;
+			if (kring->nr_hwavail > lim)
+				goto ring_reset;
 		}
 	}
+	/* update avail to what the kernel knows */
+	ring->avail = kring->nr_hwavail;
 
 	if (do_lock)
 		IXGBE_TX_UNLOCK(txr);
 	return 0;
+
 }
 
 
 /*
  * Reconcile kernel and user view of the receive ring.
+ * Same as for the txsync, this routine must be efficient and
+ * avoid races in accessing the shared regions.
+ *
+ * When called, userspace has read data from slots kring->nr_hwcur
+ * up to ring->cur (excluded).
  *
- * Userspace has read rx slots up to cur (excluded).
- * The last unread slot previously known to the kernel was nr_hwcur,
- * and the last interrupt reported nr_hwavail slots available.
+ * The last interrupt reported kring->nr_hwavail slots available
+ * after kring->nr_hwcur.
  * We must subtract the newly consumed slots (cur - nr_hwcur)
- * from nr_hwavail, clearing the descriptors for the next
- * read, tell the hardware that they are available,
- * and set nr_hwcur = cur and avail = nr_hwavail.
- * issuing a dmamap_sync on all slots.
+ * from nr_hwavail, make the descriptors available for the next reads,
+ * and set kring->nr_hwcur = ring->cur and ring->avail = kring->nr_hwavail.
  */
 static int
 ixgbe_netmap_rxsync(void *a, u_int ring_nr, int do_lock)
@@ -291,86 +400,124 @@ ixgbe_netmap_rxsync(void *a, u_int ring_nr, int do_lock)
 	struct netmap_adapter *na = NA(adapter->ifp);
 	struct netmap_kring *kring = &na->rx_rings[ring_nr];
 	struct netmap_ring *ring = kring->ring;
-	int j, k, n, lim = kring->nkr_num_slots - 1;
+	int j, k, l, n, lim = kring->nkr_num_slots - 1;
 
-	k = ring->cur;	/* ring is not protected by any lock */
-	if ( (kring->nr_kflags & NR_REINIT) || k > lim)
+	k = ring->cur;	/* cache and check value, same as in txsync */
+	n = k - kring->nr_hwcur;
+	if (n < 0)
+		n += lim + 1;
+	if (k > lim || n > kring->nr_hwavail) /* userspace is cheating */
 		return netmap_ring_reinit(kring);
 
 	if (do_lock)
 		IXGBE_RX_LOCK(rxr);
+	if (n < 0)
+		n += lim + 1;
 	/* XXX check sync modes */
 	bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map,
 			BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 
-	j = rxr->next_to_check;
+	/*
+	 * First part, import newly received packets into the netmap ring.
+	 *
+	 * j is the index of the next free slot in the netmap ring,
+	 * and l is the index of the next received packet in the NIC ring,
+	 * and they may differ in case if_init() has been called while
+	 * in netmap mode. For the receive ring we have
+	 *
+	 *	j = (kring->nr_hwcur + kring->nr_hwavail) % ring_size
+	 *	l = rxr->next_to_check;
+	 * and
+	 *	j == (l + kring->nkr_hwofs) % ring_size
+	 *
+	 * rxr->next_to_check is set to 0 on a ring reinit
+	 */
+	l = rxr->next_to_check;
+	j = rxr->next_to_check + kring->nkr_hwofs;
+	if (j > lim)
+		j -= lim + 1;
+
 	for (n = 0; ; n++) {
-		union ixgbe_adv_rx_desc *curr = &rxr->rx_base[j];
+		union ixgbe_adv_rx_desc *curr = &rxr->rx_base[l];
 		uint32_t staterr = le32toh(curr->wb.upper.status_error);
 
 		if ((staterr & IXGBE_RXD_STAT_DD) == 0)
 			break;
 		ring->slot[j].len = le16toh(curr->wb.upper.length);
 		bus_dmamap_sync(rxr->ptag,
-			rxr->rx_buffers[j].pmap, BUS_DMASYNC_POSTREAD);
+			rxr->rx_buffers[l].pmap, BUS_DMASYNC_POSTREAD);
 		j = (j == lim) ? 0 : j + 1;
+		l = (l == lim) ? 0 : l + 1;
 	}
-	if (n) {
-		rxr->next_to_check = j;
+	if (n) { /* update the state variables */
+		rxr->next_to_check = l;
 		kring->nr_hwavail += n;
-		if (kring->nr_hwavail >= lim - 10) {
-			ND("rx ring %d almost full %d", ring_nr, kring->nr_hwavail);
-		}
 	}
 
-	/* skip past packets that userspace has already processed,
-	 * making them available for reception.
-	 * advance nr_hwcur and issue a bus_dmamap_sync on the
-	 * buffers so it is safe to write to them.
-	 * Also increase nr_hwavail
+	/*
+	 * Skip past packets that userspace has already processed
+	 * (from kring->nr_hwcur to ring->cur excluded), and make
+	 * the buffers available for reception.
+	 * As usual j is the index in the netmap ring, l is the index
+	 * in the NIC ring, and j == (l + kring->nkr_hwofs) % ring_size
 	 */
 	j = kring->nr_hwcur;
 	if (j != k) {	/* userspace has read some packets. */
 		n = 0;
+		l = kring->nr_hwcur - kring->nkr_hwofs;
+		if (l < 0)
+			l += lim + 1;
 		while (j != k) {
-			struct netmap_slot *slot = ring->slot + j;
-			union ixgbe_adv_rx_desc *curr = &rxr->rx_base[j];
-			struct ixgbe_rx_buf *rxbuf = rxr->rx_buffers + j;
+			/* collect per-slot info, with similar validations
+			 * and flag handling as in the txsync code.
+			 *
+			 * NOTE curr and rxbuf are indexed by l.
+			 * Also, this driver needs to update the physical
+			 * address in the NIC ring, but other drivers
+			 * may not have this requirement.
+			 */
+			struct netmap_slot *slot = &ring->slot[j];
+			union ixgbe_adv_rx_desc *curr = &rxr->rx_base[l];
+			struct ixgbe_rx_buf *rxbuf = &rxr->rx_buffers[l];
 			void *addr = NMB(slot);
 
-			if (addr == netmap_buffer_base) { /* bad buf */
-				if (do_lock)
-					IXGBE_RX_UNLOCK(rxr);
-				return netmap_ring_reinit(kring);
-			}
+			if (addr == netmap_buffer_base) /* bad buf */
+				goto ring_reset;
 
 			curr->wb.upper.status_error = 0;
 			curr->read.pkt_addr = htole64(vtophys(addr));
 			if (slot->flags & NS_BUF_CHANGED) {
 				netmap_reload_map(rxr->ptag, rxbuf->pmap,
-					addr, na->buff_size);
+				    addr, na->buff_size);
 				slot->flags &= ~NS_BUF_CHANGED;
 			}
 
 			bus_dmamap_sync(rxr->ptag, rxbuf->pmap,
-				BUS_DMASYNC_PREREAD);
+			    BUS_DMASYNC_PREREAD);
 
 			j = (j == lim) ? 0 : j + 1;
+			l = (l == lim) ? 0 : l + 1;
 			n++;
 		}
 		kring->nr_hwavail -= n;
-		kring->nr_hwcur = ring->cur;
+		kring->nr_hwcur = k;
 		bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map,
-			BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 		/* IMPORTANT: we must leave one free slot in the ring,
-		 * so move j back by one unit
+		 * so move l back by one unit
 		 */
-		j = (j == 0) ? lim : j - 1;
-		IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(rxr->me), j);
+		l = (l == 0) ? lim : l - 1;
+		IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(rxr->me), l);
 	}
 	/* tell userspace that there are new packets */
 	ring->avail = kring->nr_hwavail ;
 	if (do_lock)
 		IXGBE_RX_UNLOCK(rxr);
 	return 0;
+
+ring_reset:
+	if (do_lock)
+		IXGBE_RX_UNLOCK(rxr);
+	return netmap_ring_reinit(kring);
 }
+/* end of file */
diff --git a/sys/dev/netmap/netmap.c b/sys/dev/netmap/netmap.c
index 7645a4e..5c960ac 100644
--- a/sys/dev/netmap/netmap.c
+++ b/sys/dev/netmap/netmap.c
@@ -1,15 +1,15 @@
 /*
  * Copyright (C) 2011 Matteo Landi, Luigi Rizzo. All rights reserved.
- *
+ * 
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
+ *   1. Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
- *
+ * 
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -25,7 +25,7 @@
 
 /*
  * $FreeBSD$
- * $Id: netmap.c 9662 2011-11-16 13:18:06Z luigi $
+ * $Id: netmap.c 9795 2011-12-02 11:39:08Z luigi $
  *
  * This module supports memory mapped access to network devices,
  * see netmap(4).
@@ -62,6 +62,7 @@ __FBSDID("$FreeBSD$");
 #include <sys/module.h>
 #include <sys/errno.h>
 #include <sys/param.h>	/* defines used in kernel.h */
+#include <sys/jail.h>
 #include <sys/kernel.h>	/* types used in module initialization */
 #include <sys/conf.h>	/* cdevsw struct */
 #include <sys/uio.h>	/* uio struct */
@@ -70,6 +71,7 @@ __FBSDID("$FreeBSD$");
 #include <sys/malloc.h>
 #include <sys/mman.h>	/* PROT_EXEC */
 #include <sys/poll.h>
+#include <sys/proc.h>
 #include <vm/vm.h>	/* vtophys */
 #include <vm/pmap.h>	/* vtophys */
 #include <sys/socket.h> /* sockaddrs */
@@ -78,6 +80,7 @@ __FBSDID("$FreeBSD$");
 #include <sys/sysctl.h>
 #include <net/if.h>
 #include <net/bpf.h>		/* BIOCIMMEDIATE */
+#include <net/vnet.h>
 #include <net/netmap.h>
 #include <dev/netmap/netmap_kern.h>
 #include <machine/bus.h>	/* bus_dmamap_* */
@@ -572,7 +575,13 @@ netmap_mmap(__unused struct cdev *dev, vm_ooffset_t offset, vm_paddr_t *paddr,
 
 
 /*
- * handler for synchronization of the queues from/to the host
+ * Handlers for synchronization of the queues from/to the host.
+ *
+ * netmap_sync_to_host() passes packets up. We are called from a
+ * system call in user process context, and the only contention
+ * can be among multiple user threads erroneously calling
+ * this routine concurrently. In principle we should not even
+ * need to lock.
  */
 static void
 netmap_sync_to_host(struct netmap_adapter *na)
@@ -580,15 +589,20 @@ netmap_sync_to_host(struct netmap_adapter *na)
 	struct netmap_kring *kring = &na->tx_rings[na->num_queues];
 	struct netmap_ring *ring = kring->ring;
 	struct mbuf *head = NULL, *tail = NULL, *m;
-	u_int n, lim = kring->nkr_num_slots - 1;
+	u_int k, n, lim = kring->nkr_num_slots - 1;
 
-	na->nm_lock(na->ifp->if_softc, NETMAP_CORE_LOCK, 0);
+	k = ring->cur;
+	if (k > lim) {
+		netmap_ring_reinit(kring);
+		return;
+	}
+	// na->nm_lock(na->ifp->if_softc, NETMAP_CORE_LOCK, 0);
 
 	/* Take packets from hwcur to cur and pass them up.
 	 * In case of no buffers we give up. At the end of the loop,
 	 * the queue is drained in all cases.
 	 */
-	for (n = kring->nr_hwcur; n != ring->cur;) {
+	for (n = kring->nr_hwcur; n != k;) {
 		struct netmap_slot *slot = &ring->slot[n];
 
 		n = (n == lim) ? 0 : n + 1;
@@ -607,9 +621,9 @@ netmap_sync_to_host(struct netmap_adapter *na)
 		tail = m;
 		m->m_nextpkt = NULL;
 	}
-	kring->nr_hwcur = ring->cur;
+	kring->nr_hwcur = k;
 	kring->nr_hwavail = ring->avail = lim;
-	na->nm_lock(na->ifp->if_softc, NETMAP_CORE_UNLOCK, 0);
+	// na->nm_lock(na->ifp->if_softc, NETMAP_CORE_UNLOCK, 0);
 
 	/* send packets up, outside the lock */
 	while ((m = head) != NULL) {
@@ -623,6 +637,10 @@ netmap_sync_to_host(struct netmap_adapter *na)
 }
 
 /*
+ * rxsync backend for packets coming from the host stack.
+ * They have been put in the queue by netmap_start() so we
+ * need to protect access to the kring using a lock.
+ *
  * This routine also does the selrecord if called from the poll handler
  * (we know because td != NULL).
  */
@@ -631,24 +649,29 @@ netmap_sync_from_host(struct netmap_adapter *na, struct thread *td)
 {
 	struct netmap_kring *kring = &na->rx_rings[na->num_queues];
 	struct netmap_ring *ring = kring->ring;
-	int delta;
+	int error = 1, delta;
+	u_int k = ring->cur, lim = kring->nkr_num_slots;
 
 	na->nm_lock(na->ifp->if_softc, NETMAP_CORE_LOCK, 0);
-
-	/* skip past packets processed by userspace,
-	 * and then sync cur/avail with hwcur/hwavail
-	 */
-	delta = ring->cur - kring->nr_hwcur;
+	if (k >= lim) /* bad value */
+		goto done;
+	delta = k - kring->nr_hwcur;
 	if (delta < 0)
-		delta += kring->nkr_num_slots;
+		delta += lim;
 	kring->nr_hwavail -= delta;
-	kring->nr_hwcur = ring->cur;
-	ring->avail = kring->nr_hwavail;
-	if (ring->avail == 0 && td)
+	if (kring->nr_hwavail < 0)	/* error */
+		goto done;
+	kring->nr_hwcur = k;
+	error = 0;
+	k = ring->avail = kring->nr_hwavail;
+	if (k == 0 && td)
 		selrecord(td, &kring->si);
-	if (ring->avail && (netmap_verbose & NM_VERB_HOST))
-		D("%d pkts from stack", ring->avail);
+	if (k && (netmap_verbose & NM_VERB_HOST))
+		D("%d pkts from stack", k);
+done:
 	na->nm_lock(na->ifp->if_softc, NETMAP_CORE_UNLOCK, 0);
+	if (error)
+		netmap_ring_reinit(kring);
 }
 
 
@@ -678,6 +701,13 @@ get_ifp(const char *name, struct ifnet **ifp)
  * Error routine called when txsync/rxsync detects an error.
  * Can't do much more than resetting cur = hwcur, avail = hwavail.
  * Return 1 on reinit.
+ *
+ * This routine is only called by the upper half of the kernel.
+ * It only reads hwcur (which is changed only by the upper half, too)
+ * and hwavail (which may be changed by the lower half, but only on
+ * a tx ring and only to increase it, so any error will be recovered
+ * on the next call). For the above, we don't strictly need to call
+ * it under lock.
  */
 int
 netmap_ring_reinit(struct netmap_kring *kring)
@@ -717,29 +747,10 @@ netmap_ring_reinit(struct netmap_kring *kring)
 			ring->avail, kring->nr_hwavail);
 		ring->cur = kring->nr_hwcur;
 		ring->avail = kring->nr_hwavail;
-		ring->flags |= NR_REINIT;
-		kring->na->flags |= NR_REINIT;
 	}
 	return (errors ? 1 : 0);
 }
 
-/*
- * Clean the reinit flag for our rings.
- * XXX at the moment, clear for all rings
- */
-static void
-netmap_clean_reinit(struct netmap_adapter *na)
-{
-	//struct netmap_kring *kring;
-	u_int i;
-
-	na->flags &= ~NR_REINIT;
-	D("--- NR_REINIT reset on %s", na->ifp->if_xname);
-	for (i = 0; i < na->num_queues + 1; i++) {
-		na->tx_rings[i].ring->flags &= ~NR_REINIT;
-		na->rx_rings[i].ring->flags &= ~NR_REINIT;
-	}
-}
 
 /*
  * Set the ring ID. For devices with a single queue, a request
@@ -801,7 +812,7 @@ netmap_set_ringid(struct netmap_priv_d *priv, u_int ringid)
  */
 static int
 netmap_ioctl(__unused struct cdev *dev, u_long cmd, caddr_t data,
-	__unused int fflag, __unused struct thread *td)
+	__unused int fflag, struct thread *td)
 {
 	struct netmap_priv_d *priv = NULL;
 	struct ifnet *ifp;
@@ -812,9 +823,13 @@ netmap_ioctl(__unused struct cdev *dev, u_long cmd, caddr_t data,
 	u_int i;
 	struct netmap_if *nifp;
 
+	CURVNET_SET(TD_TO_VNET(td));
+
 	error = devfs_get_cdevpriv((void **)&priv);
-	if (error != ENOENT && error != 0)
+	if (error != ENOENT && error != 0) {
+		CURVNET_RESTORE();
 		return (error);
+	}
 
 	error = 0;	/* Could be ENOENT */
 	switch (cmd) {
@@ -836,8 +851,10 @@ netmap_ioctl(__unused struct cdev *dev, u_long cmd, caddr_t data,
 		break;
 
 	case NIOCREGIF:
-		if (priv != NULL)	/* thread already registered */
-			return netmap_set_ringid(priv, nmr->nr_ringid);
+		if (priv != NULL) {	/* thread already registered */
+			error = netmap_set_ringid(priv, nmr->nr_ringid);
+			break;
+		}
 		/* find the interface and a reference */
 		error = get_ifp(nmr->nr_name, &ifp); /* keep reference */
 		if (error)
@@ -927,8 +944,10 @@ error:
 		break;
 
 	case NIOCUNREGIF:
-		if (priv == NULL)
-			return (ENXIO);
+		if (priv == NULL) {
+			error = ENXIO;
+			break;
+		}
 
 		/* the interface is unregistered inside the
 		   destructor of the private data. */
@@ -937,22 +956,21 @@ error:
 
 	case NIOCTXSYNC:
         case NIOCRXSYNC:
-		if (priv == NULL)
-			return (ENXIO);
+		if (priv == NULL) {
+			error = ENXIO;
+			break;
+		}
 		ifp = priv->np_ifp;	/* we have a reference */
 		na = NA(ifp); /* retrieve netmap adapter */
 		adapter = ifp->if_softc;	/* shorthand */
 
-		if (na->flags & NR_REINIT)
-			netmap_clean_reinit(na);
-
 		if (priv->np_qfirst == na->num_queues) {
 			/* queues to/from host */
 			if (cmd == NIOCTXSYNC)
 				netmap_sync_to_host(na);
 			else
 				netmap_sync_from_host(na, NULL);
-			return error;
+			break;
 		}
 
 		for (i = priv->np_qfirst; i < priv->np_qlast; i++) {
@@ -999,6 +1017,7 @@ error:
 	    }
 	}
 
+	CURVNET_RESTORE();
 	return (error);
 }
 
@@ -1020,7 +1039,7 @@ netmap_poll(__unused struct cdev *dev, int events, struct thread *td)
 	struct netmap_adapter *na;
 	struct ifnet *ifp;
 	struct netmap_kring *kring;
-	u_int i, check_all, want_tx, want_rx, revents = 0;
+	u_int core_lock, i, check_all, want_tx, want_rx, revents = 0;
 	void *adapter;
 
 	if (devfs_get_cdevpriv((void **)&priv) != 0 || priv == NULL)
@@ -1039,13 +1058,6 @@ netmap_poll(__unused struct cdev *dev, int events, struct thread *td)
 	adapter = ifp->if_softc;
 	na = NA(ifp); /* retrieve netmap adapter */
 
-	/* pending reinit, report up as a poll error. Pending
-	 * reads and writes are lost.
-	 */
-	if (na->flags & NR_REINIT) {
-		netmap_clean_reinit(na);
-		revents |= POLLERR;
-	}
 	/* how many queues we are scanning */
 	i = priv->np_qfirst;
 	if (i == na->num_queues) { /* from/to host */
@@ -1104,27 +1116,26 @@ netmap_poll(__unused struct cdev *dev, int events, struct thread *td)
 	 * LOCKED_CL	core lock is set, so we need to release it.
 	 */
 	enum {NO_CL, NEED_CL, LOCKED_CL };
-	int core_lock = (check_all || !na->separate_locks) ?
-			NEED_CL:NO_CL;
+	core_lock = (check_all || !na->separate_locks) ?  NEED_CL:NO_CL;
 	/*
 	 * We start with a lock free round which is good if we have
 	 * data available. If this fails, then lock and call the sync
 	 * routines.
 	 */
-	for (i = priv->np_qfirst; want_rx && i < priv->np_qlast; i++) {
-		kring = &na->rx_rings[i];
-		if (kring->ring->avail > 0) {
-			revents |= want_rx;
-			want_rx = 0;	/* also breaks the loop */
+		for (i = priv->np_qfirst; want_rx && i < priv->np_qlast; i++) {
+			kring = &na->rx_rings[i];
+			if (kring->ring->avail > 0) {
+				revents |= want_rx;
+				want_rx = 0;	/* also breaks the loop */
+			}
 		}
-	}
-	for (i = priv->np_qfirst; want_tx && i < priv->np_qlast; i++) {
-		kring = &na->tx_rings[i];
-		if (kring->ring->avail > 0) {
-			revents |= want_tx;
-			want_tx = 0;	/* also breaks the loop */
+		for (i = priv->np_qfirst; want_tx && i < priv->np_qlast; i++) {
+			kring = &na->tx_rings[i];
+			if (kring->ring->avail > 0) {
+				revents |= want_tx;
+				want_tx = 0;	/* also breaks the loop */
+			}
 		}
-	}
 
 	/*
 	 * If we to push packets out (priv->np_txpoll) or want_tx is
@@ -1234,7 +1245,7 @@ netmap_attach(struct netmap_adapter *na, int num_queues)
 
 	buf = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
 	if (buf) {
-		ifp->if_pspare[0] = buf;
+		WNA(ifp) = buf;
 		na->tx_rings = (void *)((char *)buf + sizeof(*na));
 		na->rx_rings = na->tx_rings + n;
 		bcopy(na, buf, sizeof(*na));
@@ -1264,31 +1275,30 @@ netmap_detach(struct ifnet *ifp)
 		knlist_destroy(&na->rx_rings[i].si.si_note);
 	}
 	bzero(na, sizeof(*na));
-	ifp->if_pspare[0] = NULL;
+	WNA(ifp) = NULL;
 	free(na, M_DEVBUF);
 }
 
 
 /*
- * intercept packets coming from the network stack and present
- * them to netmap as incoming packets on a separate ring.
+ * Intercept packets from the network stack and pass them
+ * to netmap as incoming packets on the 'software' ring.
  * We are not locked when called.
  */
 int
 netmap_start(struct ifnet *ifp, struct mbuf *m)
 {
 	struct netmap_adapter *na = NA(ifp);
-	u_int i, len, n = na->num_queues;
-	int error = EBUSY;
-	struct netmap_kring *kring = &na->rx_rings[n];
+	struct netmap_kring *kring = &na->rx_rings[na->num_queues];
+	u_int i, len = m->m_pkthdr.len;
+	int error = EBUSY, lim = kring->nkr_num_slots - 1;
 	struct netmap_slot *slot;
 
-	len = m->m_pkthdr.len;
 	if (netmap_verbose & NM_VERB_HOST)
 		D("%s packet %d len %d from the stack", ifp->if_xname,
 			kring->nr_hwcur + kring->nr_hwavail, len);
 	na->nm_lock(ifp->if_softc, NETMAP_CORE_LOCK, 0);
-	if (kring->nr_hwavail >= (int)kring->nkr_num_slots - 1) {
+	if (kring->nr_hwavail >= lim) {
 		D("stack ring %s full\n", ifp->if_xname);
 		goto done;	/* no space */
 	}
@@ -1299,8 +1309,8 @@ netmap_start(struct ifnet *ifp, struct mbuf *m)
 
 	/* compute the insert position */
 	i = kring->nr_hwcur + kring->nr_hwavail;
-	if (i >= kring->nkr_num_slots)
-		i -= kring->nkr_num_slots;
+	if (i > lim)
+		i -= lim + 1;
 	slot = &kring->ring->slot[i];
 	m_copydata(m, 0, len, NMB(slot));
 	slot->len = len;
@@ -1326,24 +1336,6 @@ done:
  * netmap_reset() is called by the driver routines when reinitializing
  * a ring. The driver is in charge of locking to protect the kring.
  * If netmap mode is not set just return NULL.
- * Otherwise set NR_REINIT (in the ring and in na) to signal
- * that a ring has been reinitialized,
- * set cur = hwcur = 0 and avail = hwavail = num_slots - 1 .
- * IT IS IMPORTANT to leave one slot free even in the tx ring because
- * we rely on cur=hwcur only for empty rings.
- * These are good defaults but can be overridden later in the device
- * specific code if, after a reinit, the ring does not start from 0
- * (e.g. if_em.c does this).
- *
- * XXX we shouldn't be touching the ring, but there is a
- * race anyways and this is our best option.
- *
- * XXX setting na->flags makes the syscall code faster, as there is
- * only one place to check. On the other hand, we will need a better
- * way to notify multiple threads that rings have been reset.
- * One way is to increment na->rst_count at each ring reset.
- * Each thread in its own priv structure will keep a matching counter,
- * and on a reset will acknowledge and clean its own rings.
  */
 struct netmap_slot *
 netmap_reset(struct netmap_adapter *na, enum txrx tx, int n,
@@ -1351,8 +1343,7 @@ netmap_reset(struct netmap_adapter *na, enum txrx tx, int n,
 {
 	struct netmap_kring *kring;
 	struct netmap_ring *ring;
-	struct netmap_slot *slot;
-	u_int i;
+	int new_hwofs, lim;
 
 	if (na == NULL)
 		return NULL;	/* no netmap support here */
@@ -1360,74 +1351,26 @@ netmap_reset(struct netmap_adapter *na, enum txrx tx, int n,
 		return NULL;	/* nothing to reinitialize */
 	kring = tx == NR_TX ?  na->tx_rings + n : na->rx_rings + n;
 	ring = kring->ring;
-    if (tx == NR_TX) {
-	/*
-	 * The last argument is the new value of next_to_clean.
-	 *
-	 * In the TX ring, we have P pending transmissions (from
-	 * next_to_clean to nr_hwcur) followed by nr_hwavail free slots.
-	 * Generally we can use all the slots in the ring so
-	 * P = ring_size - nr_hwavail hence (modulo ring_size):
-	 *	next_to_clean == nr_hwcur + nr_hwavail
-	 * 
-	 * If, upon a reset, nr_hwavail == ring_size and next_to_clean
-	 * does not change we have nothing to report. Otherwise some
-	 * pending packets may be lost, or newly injected packets will.
-	 */
-	/* if hwcur does not change, nothing to report.
-	 * otherwise remember the change so perhaps we can
-	 * shift the block at the next reinit
-	 */
-	if (new_cur == kring->nr_hwcur &&
-		    kring->nr_hwavail == kring->nkr_num_slots - 1) {
-		/* all ok */
-		D("+++ NR_REINIT ok on %s TX[%d]", na->ifp->if_xname, n);
-	} else {
-		D("+++ NR_REINIT set on %s TX[%d]", na->ifp->if_xname, n);
-	}
-		ring->flags |= NR_REINIT;
-		na->flags |= NR_REINIT;
-		ring->avail = kring->nr_hwavail = kring->nkr_num_slots - 1;
-		ring->cur = kring->nr_hwcur = new_cur;
-    } else {
-	/*
-	 * The last argument is the next free slot.
-	 * In the RX ring we have nr_hwavail full buffers starting
-	 * from nr_hwcur.
-	 * If nr_hwavail == 0 and nr_hwcur does not change we are ok
-	 * otherwise we might be in trouble as the buffers are
-	 * changing.
-	 */
-	if (new_cur == kring->nr_hwcur && kring->nr_hwavail == 0) {
-		/* all ok */
-		D("+++ NR_REINIT ok on %s RX[%d]", na->ifp->if_xname, n);
-	} else {
-		D("+++ NR_REINIT set on %s RX[%d]", na->ifp->if_xname, n);
-	}
-	ring->flags |= NR_REINIT;
-	na->flags |= NR_REINIT;
-	ring->avail = kring->nr_hwavail = 0; /* no data */
-	ring->cur = kring->nr_hwcur = new_cur;
-    }
+	lim = kring->nkr_num_slots - 1;
+
+	if (tx == NR_TX)
+		new_hwofs = kring->nr_hwcur - new_cur;
+	else
+		new_hwofs = kring->nr_hwcur + kring->nr_hwavail - new_cur;
+	if (new_hwofs > lim)
+		new_hwofs -= lim + 1;
+
+	/* Alwayws set the new offset value and realign the ring. */
+	kring->nkr_hwofs = new_hwofs;
+	if (tx == NR_TX)
+		kring->nr_hwavail = kring->nkr_num_slots - 1;
+	D("new hwofs %d on %s %s[%d]",
+			kring->nkr_hwofs, na->ifp->if_xname,
+			tx == NR_TX ? "TX" : "RX", n);
 
-	slot = ring->slot;
 	/*
-	 * Check that buffer indexes are correct. If we find a
-	 * bogus value we are a bit in trouble because we cannot
-	 * recover easily. Best we can do is (probably) persistently
-	 * reset the ring.
-	 */
-	for (i = 0; i < kring->nkr_num_slots; i++) {
-		if (slot[i].buf_idx >= netmap_total_buffers) {
-			D("invalid buf_idx %d at slot %d", slot[i].buf_idx, i);
-			slot[i].buf_idx = 0; /* XXX reset */
-		}
-		/* XXX we don't really need to set the length */
-		slot[i].len = 0;
-	}
-	/* wakeup possible waiters, both on the ring and on the global
-	 * selfd. Perhaps a bit early now but the device specific
-	 * routine is locked so hopefully we won't have a race.
+	 * We do the wakeup here, but the ring is not yet reconfigured.
+	 * However, we are under lock so there are no races.
 	 */
 	selwakeuppri(&kring->si, PI_NET);
 	selwakeuppri(&kring[na->num_queues + 1 - n].si, PI_NET);
@@ -1624,7 +1567,7 @@ netmap_memory_init(void)
 	nm_buf_pool.base += netmap_mem_d->nm_buf_start;
 	netmap_buffer_base = nm_buf_pool.base;
 	D("netmap_buffer_base %p (offset %d)",
-		netmap_buffer_base, netmap_mem_d->nm_buf_start);
+		netmap_buffer_base, (int)netmap_mem_d->nm_buf_start);
 	/* number of buffers, they all start as free */
 
 	netmap_total_buffers = nm_buf_pool.total_buffers =
@@ -1632,7 +1575,7 @@ netmap_memory_init(void)
 	nm_buf_pool.bufsize = NETMAP_BUF_SIZE;
 
 	D("Have %d MB, use %dKB for rings, %d buffers at %p",
-		(sz >> 20), (netmap_mem_d->nm_size >> 10),
+		(sz >> 20), (int)(netmap_mem_d->nm_size >> 10),
 		nm_buf_pool.total_buffers, nm_buf_pool.base);
 
 	/* allocate and initialize the bitmap. Entry 0 is considered
@@ -1673,7 +1616,7 @@ netmap_memory_fini(void)
 		TAILQ_REMOVE(&netmap_mem_d->nm_molist, mem_obj, nmo_next);
 		if (mem_obj->nmo_used == 1) {
 			printf("netmap: leaked %d bytes at %p\n",
-			       mem_obj->nmo_size,
+			       (int)mem_obj->nmo_size,
 			       mem_obj->nmo_data);
 		}
 		free(mem_obj, M_NETMAP);
@@ -1704,7 +1647,7 @@ netmap_init(void)
 		return (error);
 	}
 	printf("netmap: loaded module with %d Mbytes\n",
-		netmap_mem_d->nm_totalsize >> 20);
+		(int)(netmap_mem_d->nm_totalsize >> 20));
 
 	netmap_dev = make_dev(&netmap_cdevsw, 0, UID_ROOT, GID_WHEEL, 0660,
 			      "netmap");
diff --git a/sys/dev/netmap/netmap_kern.h b/sys/dev/netmap/netmap_kern.h
index 5434609..8fa95fa 100644
--- a/sys/dev/netmap/netmap_kern.h
+++ b/sys/dev/netmap/netmap_kern.h
@@ -1,15 +1,15 @@
 /*
  * Copyright (C) 2011 Matteo Landi, Luigi Rizzo. All rights reserved.
- *
+ * 
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
+ *   1. Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
- *
+ * 
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -25,7 +25,7 @@
 
 /*
  * $FreeBSD$
- * $Id: netmap_kern.h 9662 2011-11-16 13:18:06Z luigi $
+ * $Id: netmap_kern.h 9795 2011-12-02 11:39:08Z luigi $
  *
  * The header contains the definitions of constants and function
  * prototypes used only in kernelspace.
@@ -68,7 +68,7 @@ struct netmap_kring {
 	u_int nr_kflags;
 	u_int nkr_num_slots;
 
-	u_int	nkr_hwofs;	/* offset between NIC and netmap ring */
+	int	nkr_hwofs;	/* offset between NIC and netmap ring */
 	struct netmap_adapter *na;	 // debugging
 	struct selinfo si; /* poll/select wait queue */
 };
@@ -94,7 +94,7 @@ struct netmap_adapter {
 	u_int num_rx_desc;
 	u_int buff_size;
 
-	u_int	flags;	/* NR_REINIT */
+	u_int	flags;
 	/* tx_rings and rx_rings are private but allocated
 	 * as a contiguous chunk of memory. Each array has
 	 * N+1 entries, for the adapter queues and for the host queue.
@@ -196,9 +196,13 @@ enum {                                  /* verbose flags */
 };
 
 /*
- * return a pointer to the struct netmap adapter from the ifp
+ * NA returns a pointer to the struct netmap adapter from the ifp,
+ * WNA is used to write it.
  */
-#define	NA(_ifp)	((struct netmap_adapter *)(_ifp)->if_pspare[0])
+#ifndef WNA
+#define	WNA(_ifp)	(_ifp)->if_pspare[0]
+#endif
+#define	NA(_ifp)	((struct netmap_adapter *)WNA(_ifp))
 
 
 /*
diff --git a/sys/dev/nfe/if_nfe.c b/sys/dev/nfe/if_nfe.c
index 3c36fe7..f4c5bed 100644
--- a/sys/dev/nfe/if_nfe.c
+++ b/sys/dev/nfe/if_nfe.c
@@ -165,16 +165,12 @@ static device_method_t nfe_methods[] = {
 	DEVMETHOD(device_resume,	nfe_resume),
 	DEVMETHOD(device_shutdown,	nfe_shutdown),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	nfe_miibus_readreg),
 	DEVMETHOD(miibus_writereg,	nfe_miibus_writereg),
 	DEVMETHOD(miibus_statchg,	nfe_miibus_statchg),
 
-	{ NULL, NULL }
+	DEVMETHOD_END
 };
 
 static driver_t nfe_driver = {
diff --git a/sys/dev/nge/if_nge.c b/sys/dev/nge/if_nge.c
index 3d7ad63..05eec99 100644
--- a/sys/dev/nge/if_nge.c
+++ b/sys/dev/nge/if_nge.c
@@ -223,16 +223,12 @@ static device_method_t nge_methods[] = {
 	DEVMETHOD(device_suspend,	nge_suspend),
 	DEVMETHOD(device_resume,	nge_resume),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	nge_miibus_readreg),
 	DEVMETHOD(miibus_writereg,	nge_miibus_writereg),
 	DEVMETHOD(miibus_statchg,	nge_miibus_statchg),
 
-	{ NULL, NULL }
+	DEVMETHOD_END
 };
 
 static driver_t nge_driver = {
diff --git a/sys/dev/nve/if_nve.c b/sys/dev/nve/if_nve.c
index 1428662..5c53239 100644
--- a/sys/dev/nve/if_nve.c
+++ b/sys/dev/nve/if_nve.c
@@ -184,15 +184,11 @@ static device_method_t nve_methods[] = {
 	DEVMETHOD(device_detach, nve_detach),
 	DEVMETHOD(device_shutdown, nve_shutdown),
 
-	/* Bus interface */
-	DEVMETHOD(bus_print_child, bus_generic_print_child),
-	DEVMETHOD(bus_driver_added, bus_generic_driver_added),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg, nve_miibus_readreg),
 	DEVMETHOD(miibus_writereg, nve_miibus_writereg),
 
-	{0, 0}
+	DEVMETHOD_END
 };
 
 static driver_t nve_driver = {
diff --git a/sys/dev/ofw/ofw_console.c b/sys/dev/ofw/ofw_console.c
index 62dbe51..e71d5c1 100644
--- a/sys/dev/ofw/ofw_console.c
+++ b/sys/dev/ofw/ofw_console.c
@@ -74,6 +74,8 @@ static cn_init_t	ofw_cninit;
 static cn_term_t	ofw_cnterm;
 static cn_getc_t	ofw_cngetc;
 static cn_putc_t	ofw_cnputc;
+static cn_grab_t	ofw_cngrab;
+static cn_ungrab_t	ofw_cnungrab;
 
 CONSOLE_DRIVER(ofw);
 
@@ -192,6 +194,16 @@ ofw_cnterm(struct consdev *cp)
 {
 }
 
+static void
+ofw_cngrab(struct consdev *cp)
+{
+}
+
+static void
+ofw_cnungrab(struct consdev *cp)
+{
+}
+
 static int
 ofw_cngetc(struct consdev *cp)
 {
diff --git a/sys/dev/ofw/ofw_fdt.c b/sys/dev/ofw/ofw_fdt.c
index 806f17c..7b3b0e9 100644
--- a/sys/dev/ofw/ofw_fdt.c
+++ b/sys/dev/ofw/ofw_fdt.c
@@ -392,6 +392,8 @@ ofw_fdt_finddevice(ofw_t ofw, const char *device)
 	int offset;
 
 	offset = fdt_path_offset(fdtp, device);
+	if (offset < 0)
+		return (-1);
 	return (fdt_offset_phandle(offset));
 }
 
@@ -420,7 +422,7 @@ ofw_fdt_fixup(ofw_t ofw)
 	ssize_t len;
 	int i;
 
-	if ((root = ofw_fdt_finddevice(ofw, "/")) == 0)
+	if ((root = ofw_fdt_finddevice(ofw, "/")) == -1)
 		return (ENODEV);
 
 	if ((len = ofw_fdt_getproplen(ofw, root, "model")) <= 0)
diff --git a/sys/dev/ofw/ofw_iicbus.c b/sys/dev/ofw/ofw_iicbus.c
index 875e4dd..906a49f 100644
--- a/sys/dev/ofw/ofw_iicbus.c
+++ b/sys/dev/ofw/ofw_iicbus.c
@@ -68,7 +68,7 @@ static device_method_t ofw_iicbus_methods[] = {
 	DEVMETHOD(ofw_bus_get_node,	ofw_bus_gen_get_node),
 	DEVMETHOD(ofw_bus_get_type,	ofw_bus_gen_get_type),
 
-	KOBJMETHOD_END
+	DEVMETHOD_END
 };
 
 struct ofw_iicbus_devinfo {
diff --git a/sys/dev/ofw/openfirm.c b/sys/dev/ofw/openfirm.c
index 9ff72df..af6ee80 100644
--- a/sys/dev/ofw/openfirm.c
+++ b/sys/dev/ofw/openfirm.c
@@ -131,7 +131,7 @@ OF_init(void *cookie)
 
 	rv = OFW_INIT(ofw_obj, cookie);
 
-	if ((chosen = OF_finddevice("/chosen")) > 0)
+	if ((chosen = OF_finddevice("/chosen")) != -1)
 		if (OF_getprop(chosen, "stdout", &stdout, sizeof(stdout)) == -1)
 			stdout = -1;
 
diff --git a/sys/dev/pccard/pccardvar.h b/sys/dev/pccard/pccardvar.h
index 1cfcd58..f98bcc8 100644
--- a/sys/dev/pccard/pccardvar.h
+++ b/sys/dev/pccard/pccardvar.h
@@ -106,7 +106,7 @@ typedef int (*pccard_product_match_fn) (device_t dev,
  * make this inline so that we don't have to worry about dangling references
  * to it in the modules or the code.
  */
-static __inline const struct pccard_product *
+static inline const struct pccard_product *
 pccard_product_lookup(device_t dev, const struct pccard_product *tab,
     size_t ent_size, pccard_product_match_fn matchfn)
 {
@@ -150,31 +150,31 @@ pccard_product_lookup(device_t dev, const struct pccard_product *tab,
 
 /* Convenience functions */
 
-static __inline int
+static inline int
 pccard_cis_scan(device_t dev, pccard_scan_t fct, void *arg)
 {
 	return (CARD_CIS_SCAN(device_get_parent(dev), dev, fct, arg));
 }
 
-static __inline int
+static inline int
 pccard_attr_read_1(device_t dev, uint32_t offset, uint8_t *val)
 {
 	return (CARD_ATTR_READ(device_get_parent(dev), dev, offset, val));
 }
 
-static __inline int
+static inline int
 pccard_attr_write_1(device_t dev, uint32_t offset, uint8_t val)
 {
 	return (CARD_ATTR_WRITE(device_get_parent(dev), dev, offset, val));
 }
 
-static __inline int
+static inline int
 pccard_ccr_read_1(device_t dev, uint32_t offset, uint8_t *val)
 {
 	return (CARD_CCR_READ(device_get_parent(dev), dev, offset, val));
 }
 
-static __inline int
+static inline int
 pccard_ccr_write_1(device_t dev, uint32_t offset, uint8_t val)
 {
 	return (CARD_CCR_WRITE(device_get_parent(dev), dev, offset, val));
@@ -199,7 +199,7 @@ enum {
 };
 
 #define PCCARD_ACCESSOR(A, B, T)					\
-__inline static int							\
+static inline int							\
 pccard_get_ ## A(device_t dev, T *t)					\
 {									\
 	return BUS_READ_IVAR(device_get_parent(dev), dev,		\
diff --git a/sys/dev/pccbb/pccbb_isa.c b/sys/dev/pccbb/pccbb_isa.c
index fb45e64..fa990e0 100644
--- a/sys/dev/pccbb/pccbb_isa.c
+++ b/sys/dev/pccbb/pccbb_isa.c
@@ -211,7 +211,6 @@ static device_method_t cbb_methods[] = {
 	DEVMETHOD(device_resume,		cbb_resume),
 
 	/* bus methods */
-	DEVMETHOD(bus_print_child,		bus_generic_print_child),
 	DEVMETHOD(bus_read_ivar,		cbb_read_ivar),
 	DEVMETHOD(bus_write_ivar,		cbb_write_ivar),
 	DEVMETHOD(bus_alloc_resource,		cbb_alloc_resource),
@@ -232,7 +231,7 @@ static device_method_t cbb_methods[] = {
 	DEVMETHOD(power_enable_socket,		cbb_power_enable_socket),
 	DEVMETHOD(power_disable_socket,		cbb_power_disable_socket),
 
-	{0,0}
+	DEVMETHOD_END
 };
 
 static driver_t cbb_isa_driver = {
diff --git a/sys/dev/pccbb/pccbb_pci.c b/sys/dev/pccbb/pccbb_pci.c
index 6cdc4e4..eca5ed7 100644
--- a/sys/dev/pccbb/pccbb_pci.c
+++ b/sys/dev/pccbb/pccbb_pci.c
@@ -822,7 +822,6 @@ static device_method_t cbb_methods[] = {
 	DEVMETHOD(device_resume,		cbb_resume),
 
 	/* bus methods */
-	DEVMETHOD(bus_print_child,		bus_generic_print_child),
 	DEVMETHOD(bus_read_ivar,		cbb_read_ivar),
 	DEVMETHOD(bus_write_ivar,		cbb_write_ivar),
 	DEVMETHOD(bus_alloc_resource,		cbb_alloc_resource),
@@ -849,7 +848,7 @@ static device_method_t cbb_methods[] = {
 	DEVMETHOD(pcib_write_config,		cbb_write_config),
 	DEVMETHOD(pcib_route_interrupt,		cbb_route_interrupt),
 
-	{0,0}
+	DEVMETHOD_END
 };
 
 static driver_t cbb_driver = {
diff --git a/sys/dev/pci/eisa_pci.c b/sys/dev/pci/eisa_pci.c
index 61027a1..98fa270 100644
--- a/sys/dev/pci/eisa_pci.c
+++ b/sys/dev/pci/eisa_pci.c
@@ -55,7 +55,6 @@ static device_method_t eisab_methods[] = {
     DEVMETHOD(device_resume,		bus_generic_resume),
 
     /* Bus interface */
-    DEVMETHOD(bus_print_child,		bus_generic_print_child),
     DEVMETHOD(bus_alloc_resource,	bus_generic_alloc_resource),
     DEVMETHOD(bus_release_resource,	bus_generic_release_resource),
     DEVMETHOD(bus_activate_resource,	bus_generic_activate_resource),
@@ -63,7 +62,7 @@ static device_method_t eisab_methods[] = {
     DEVMETHOD(bus_setup_intr,		bus_generic_setup_intr),
     DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
 
-    { 0, 0 }
+    DEVMETHOD_END
 };
 
 static driver_t eisab_driver = {
diff --git a/sys/dev/pci/isa_pci.c b/sys/dev/pci/isa_pci.c
index be3f3ac..7819b7e 100644
--- a/sys/dev/pci/isa_pci.c
+++ b/sys/dev/pci/isa_pci.c
@@ -67,7 +67,7 @@ static device_method_t isab_methods[] = {
     DEVMETHOD(device_resume,		bus_generic_resume),
 
     /* Bus interface */
-    DEVMETHOD(bus_print_child,		bus_generic_print_child),
+    DEVMETHOD(bus_add_child,		bus_generic_add_child),
     DEVMETHOD(bus_alloc_resource,	isab_pci_alloc_resource),
     DEVMETHOD(bus_release_resource,	isab_pci_release_resource),
     DEVMETHOD(bus_activate_resource,	bus_generic_activate_resource),
@@ -75,7 +75,7 @@ static device_method_t isab_methods[] = {
     DEVMETHOD(bus_setup_intr,		bus_generic_setup_intr),
     DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
 
-    { 0, 0 }
+    DEVMETHOD_END
 };
 
 struct isab_pci_resource {
diff --git a/sys/dev/pci/pci_pci.c b/sys/dev/pci/pci_pci.c
index fa14816..d624104 100644
--- a/sys/dev/pci/pci_pci.c
+++ b/sys/dev/pci/pci_pci.c
@@ -67,7 +67,6 @@ static device_method_t pcib_methods[] = {
     DEVMETHOD(device_resume,		pcib_resume),
 
     /* Bus interface */
-    DEVMETHOD(bus_print_child,		bus_generic_print_child),
     DEVMETHOD(bus_read_ivar,		pcib_read_ivar),
     DEVMETHOD(bus_write_ivar,		pcib_write_ivar),
     DEVMETHOD(bus_alloc_resource,	pcib_alloc_resource),
@@ -95,7 +94,7 @@ static device_method_t pcib_methods[] = {
     DEVMETHOD(pcib_map_msi,		pcib_map_msi),
     DEVMETHOD(pcib_power_for_sleep,	pcib_power_for_sleep),
 
-    { 0, 0 }
+    DEVMETHOD_END
 };
 
 static devclass_t pcib_devclass;
diff --git a/sys/dev/pci/pcireg.h b/sys/dev/pci/pcireg.h
index 216882c..7951d13 100644
--- a/sys/dev/pci/pcireg.h
+++ b/sys/dev/pci/pcireg.h
@@ -715,6 +715,7 @@
 #define	PCIM_AER_COR_BAD_DLLP		0x00000080
 #define	PCIM_AER_COR_REPLAY_ROLLOVER	0x00000100
 #define	PCIM_AER_COR_REPLAY_TIMEOUT	0x00001000
+#define	PCIM_AER_COR_ADVISORY_NF_ERROR	0x00002000
 #define	PCIR_AER_COR_MASK	0x14	/* Shares bits with COR_STATUS */
 #define	PCIR_AER_CAP_CONTROL	0x18
 #define	PCIM_AER_FIRST_ERROR_PTR	0x0000001f
diff --git a/sys/dev/pcn/if_pcn.c b/sys/dev/pcn/if_pcn.c
index 2ebd35c..de072ad 100644
--- a/sys/dev/pcn/if_pcn.c
+++ b/sys/dev/pcn/if_pcn.c
@@ -173,16 +173,12 @@ static device_method_t pcn_methods[] = {
 	DEVMETHOD(device_detach,	pcn_detach),
 	DEVMETHOD(device_shutdown,	pcn_shutdown),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	pcn_miibus_readreg),
 	DEVMETHOD(miibus_writereg,	pcn_miibus_writereg),
 	DEVMETHOD(miibus_statchg,	pcn_miibus_statchg),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t pcn_driver = {
diff --git a/sys/dev/ppbus/lpbb.c b/sys/dev/ppbus/lpbb.c
index 6cf747e..0c85620 100644
--- a/sys/dev/ppbus/lpbb.c
+++ b/sys/dev/ppbus/lpbb.c
@@ -245,9 +245,6 @@ static device_method_t lpbb_methods[] = {
 	DEVMETHOD(device_probe,		lpbb_probe),
 	DEVMETHOD(device_attach,	lpbb_attach),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-
 	/* iicbb interface */
 	DEVMETHOD(iicbb_callback,	lpbb_callback),
 	DEVMETHOD(iicbb_setsda,		lpbb_setsda),
@@ -256,7 +253,7 @@ static device_method_t lpbb_methods[] = {
 	DEVMETHOD(iicbb_getscl,		lpbb_getscl),
 	DEVMETHOD(iicbb_reset,		lpbb_reset),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t lpbb_driver = {
diff --git a/sys/dev/ppbus/lpt.c b/sys/dev/ppbus/lpt.c
index 18d46ae..3a28efd2 100644
--- a/sys/dev/ppbus/lpt.c
+++ b/sys/dev/ppbus/lpt.c
@@ -447,10 +447,9 @@ lptout(void *arg)
 {
 	struct lpt_data *sc = arg;
 	device_t dev = sc->sc_dev;
-#if defined(INVARIANTS) || defined(LPT_DEBUG)
-	device_t ppbus = device_get_parent(dev);
-#endif
+	device_t ppbus;
 
+	ppbus = device_get_parent(dev);
 	ppb_assert_locked(ppbus);
 	lprintf(("T %x ", ppb_rstr(ppbus)));
 	if (sc->sc_state & OPEN) {
diff --git a/sys/dev/ppbus/ppb_base.c b/sys/dev/ppbus/ppb_base.c
index 62769b0..256d7a4 100644
--- a/sys/dev/ppbus/ppb_base.c
+++ b/sys/dev/ppbus/ppb_base.c
@@ -60,7 +60,7 @@ ppb_poll_bus(device_t bus, int max,
 	int i, j, error;
 	char r;
 
-	mtx_assert(ppb->ppc_lock, MA_OWNED);
+	ppb_assert_locked(bus);
 
 	/* try at least up to 10ms */
 	for (j = 0; j < ((how & PPB_POLL) ? max : 1); j++) {
@@ -96,12 +96,9 @@ ppb_poll_bus(device_t bus, int max,
 int
 ppb_get_epp_protocol(device_t bus)
 {
-#ifdef INVARIANTS
-	struct ppb_data *ppb = DEVTOSOFTC(bus);
-#endif
 	uintptr_t protocol;
 
-	mtx_assert(ppb->ppc_lock, MA_OWNED);
+	ppb_assert_locked(bus);
 	BUS_READ_IVAR(device_get_parent(bus), bus, PPC_IVAR_EPP_PROTO, &protocol);
 
 	return (protocol);
@@ -117,7 +114,7 @@ ppb_get_mode(device_t bus)
 	struct ppb_data *ppb = DEVTOSOFTC(bus);
 
 	/* XXX yet device mode = ppbus mode = chipset mode */
-	mtx_assert(ppb->ppc_lock, MA_OWNED);
+	ppb_assert_locked(bus);
 	return (ppb->mode);
 }
 
@@ -132,7 +129,7 @@ ppb_set_mode(device_t bus, int mode)
 	struct ppb_data *ppb = DEVTOSOFTC(bus);
 	int old_mode = ppb_get_mode(bus);
 
-	mtx_assert(ppb->ppc_lock, MA_OWNED);
+	ppb_assert_locked(bus);
 	if (PPBUS_SETMODE(device_get_parent(bus), mode))
 		return (-1);
 
@@ -150,11 +147,8 @@ ppb_set_mode(device_t bus, int mode)
 int
 ppb_write(device_t bus, char *buf, int len, int how)
 {
-#ifdef INVARIANTS
-	struct ppb_data *ppb = DEVTOSOFTC(bus);
-#endif
 
-	mtx_assert(ppb->ppc_lock, MA_OWNED);
+	ppb_assert_locked(bus);
 	return (PPBUS_WRITE(device_get_parent(bus), buf, len, how));
 }
 
@@ -166,11 +160,8 @@ ppb_write(device_t bus, char *buf, int len, int how)
 int
 ppb_reset_epp_timeout(device_t bus)
 {
-#ifdef INVARIANTS
-	struct ppb_data *ppb = DEVTOSOFTC(bus);
-#endif
 
-	mtx_assert(ppb->ppc_lock, MA_OWNED);
+	ppb_assert_locked(bus);
 	return(PPBUS_RESET_EPP(device_get_parent(bus)));
 }
 
@@ -182,11 +173,8 @@ ppb_reset_epp_timeout(device_t bus)
 int
 ppb_ecp_sync(device_t bus)
 {
-#ifdef INVARIANTS
-	struct ppb_data *ppb = DEVTOSOFTC(bus);
-#endif
 
-	mtx_assert(ppb->ppc_lock, MA_OWNED);
+	ppb_assert_locked(bus);
 	return (PPBUS_ECP_SYNC(device_get_parent(bus)));
 }
 
@@ -198,12 +186,9 @@ ppb_ecp_sync(device_t bus)
 int
 ppb_get_status(device_t bus, struct ppb_status *status)
 {
-#ifdef INVARIANTS
-	struct ppb_data *ppb = DEVTOSOFTC(bus);
-#endif
 	register char r;
 
-	mtx_assert(ppb->ppc_lock, MA_OWNED);
+	ppb_assert_locked(bus);
 
 	r = status->status = ppb_rstr(bus);
 
diff --git a/sys/dev/ppbus/ppb_msq.c b/sys/dev/ppbus/ppb_msq.c
index 6de67ce..8aba5ec 100644
--- a/sys/dev/ppbus/ppb_msq.c
+++ b/sys/dev/ppbus/ppb_msq.c
@@ -117,13 +117,10 @@ mode2xfer(device_t bus, struct ppb_device *ppbdev, int opcode)
 int
 ppb_MS_init(device_t bus, device_t dev, struct ppb_microseq *loop, int opcode)
 {
-#ifdef INVARIANTS
-	struct ppb_data *ppb = device_get_softc(bus);
-#endif
 	struct ppb_device *ppbdev = (struct ppb_device *)device_get_ivars(dev);
 	struct ppb_xfer *xfer = mode2xfer(bus, ppbdev, opcode);
 
-	mtx_assert(ppb->ppc_lock, MA_OWNED);
+	ppb_assert_locked(bus);
 	xfer->loop = loop;
 
 	return (0);
diff --git a/sys/dev/ppbus/ppbconf.c b/sys/dev/ppbus/ppbconf.c
index 858e5b2..65a26e0 100644
--- a/sys/dev/ppbus/ppbconf.c
+++ b/sys/dev/ppbus/ppbconf.c
@@ -429,7 +429,7 @@ ppbus_detach(device_t dev)
 		return (error);
 
 	/* detach & delete all children */
-	device_delete_all_children(dev);
+	device_delete_children(dev);
 
 	return (0);
 }
diff --git a/sys/dev/ppbus/vpo.c b/sys/dev/ppbus/vpo.c
index 02bc9b3..9c9054f 100644
--- a/sys/dev/ppbus/vpo.c
+++ b/sys/dev/ppbus/vpo.c
@@ -298,11 +298,8 @@ static void
 vpo_action(struct cam_sim *sim, union ccb *ccb)
 {
 	struct vpo_data *vpo = (struct vpo_data *)sim->softc;
-#ifdef INVARIANTS
-	device_t ppbus = device_get_parent(vpo->vpo_dev);
 
-	ppb_assert_locked(ppbus);
-#endif
+	ppb_assert_locked(device_get_parent(vpo->vpo_dev));
 	switch (ccb->ccb_h.func_code) {
 	case XPT_SCSI_IO:
 	{
diff --git a/sys/dev/ppc/ppc.c b/sys/dev/ppc/ppc.c
index ef505d8..5da180c 100644
--- a/sys/dev/ppc/ppc.c
+++ b/sys/dev/ppc/ppc.c
@@ -1857,7 +1857,7 @@ ppc_detach(device_t dev)
 	}
 
 	/* detach & delete all children */
-	device_delete_all_children(dev);
+	device_delete_children(dev);
 
 	if (ppc->res_irq != 0) {
 		bus_teardown_intr(dev, ppc->res_irq, ppc->intr_cookie);
diff --git a/sys/dev/puc/puc_pccard.c b/sys/dev/puc/puc_pccard.c
index 63d5787..370c6af 100644
--- a/sys/dev/puc/puc_pccard.c
+++ b/sys/dev/puc/puc_pccard.c
@@ -85,8 +85,8 @@ static device_method_t puc_pccard_methods[] = {
     DEVMETHOD(bus_print_child,		puc_bus_print_child),
     DEVMETHOD(bus_child_pnpinfo_str,	puc_bus_child_pnpinfo_str),
     DEVMETHOD(bus_child_location_str,	puc_bus_child_location_str),
-    DEVMETHOD(bus_driver_added,		bus_generic_driver_added),
-    { 0, 0 }
+
+    DEVMETHOD_END
 };
 
 static driver_t puc_pccard_driver = {
diff --git a/sys/dev/puc/puc_pci.c b/sys/dev/puc/puc_pci.c
index 8c14717..4ad1e3a 100644
--- a/sys/dev/puc/puc_pci.c
+++ b/sys/dev/puc/puc_pci.c
@@ -135,8 +135,8 @@ static device_method_t puc_pci_methods[] = {
     DEVMETHOD(bus_print_child,		puc_bus_print_child),
     DEVMETHOD(bus_child_pnpinfo_str,	puc_bus_child_pnpinfo_str),
     DEVMETHOD(bus_child_location_str,	puc_bus_child_location_str),
-    DEVMETHOD(bus_driver_added,		bus_generic_driver_added),
-    { 0, 0 }
+
+    DEVMETHOD_END
 };
 
 static driver_t puc_pci_driver = {
diff --git a/sys/dev/qlxgb/qla_misc.c b/sys/dev/qlxgb/qla_misc.c
index c616d4f..fd86e2a 100644
--- a/sys/dev/qlxgb/qla_misc.c
+++ b/sys/dev/qlxgb/qla_misc.c
@@ -407,7 +407,7 @@ qla_crb_init(qla_host_t *ha)
 	addr_val_t *addr_val_map, *avmap;
 
 	qla_rd_flash32(ha, 0, &sig);
-	QL_DPRINT2((ha->pci_dev, "%s: val[0] = 0x%08x\n", __func__, val));
+	QL_DPRINT2((ha->pci_dev, "%s: val[0] = 0x%08x\n", __func__, sig));
 
 	qla_rd_flash32(ha, 4, &val);
 	QL_DPRINT2((ha->pci_dev, "%s: val[4] = 0x%08x\n", __func__, val));
diff --git a/sys/dev/quicc/quicc_bfe_fdt.c b/sys/dev/quicc/quicc_bfe_fdt.c
index e1fd2d5..382b2a1 100644
--- a/sys/dev/quicc/quicc_bfe_fdt.c
+++ b/sys/dev/quicc/quicc_bfe_fdt.c
@@ -59,10 +59,8 @@ static device_method_t quicc_fdt_methods[] = {
 	DEVMETHOD(bus_read_ivar,	quicc_bus_read_ivar),
 	DEVMETHOD(bus_setup_intr,	quicc_bus_setup_intr),
 	DEVMETHOD(bus_teardown_intr,	quicc_bus_teardown_intr),
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t quicc_fdt_driver = {
diff --git a/sys/dev/ral/rt2560.c b/sys/dev/ral/rt2560.c
index 6064707..9fdc157 100644
--- a/sys/dev/ral/rt2560.c
+++ b/sys/dev/ral/rt2560.c
@@ -85,9 +85,9 @@ __FBSDID("$FreeBSD$");
 #endif
 
 static struct ieee80211vap *rt2560_vap_create(struct ieee80211com *,
-			    const char name[IFNAMSIZ], int unit, int opmode,
-			    int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
-			    const uint8_t mac[IEEE80211_ADDR_LEN]);
+			    const char [IFNAMSIZ], int, enum ieee80211_opmode,
+			    int, const uint8_t [IEEE80211_ADDR_LEN],
+			    const uint8_t [IEEE80211_ADDR_LEN]);
 static void		rt2560_vap_delete(struct ieee80211vap *);
 static void		rt2560_dma_map_addr(void *, bus_dma_segment_t *, int,
 			    int);
@@ -373,10 +373,10 @@ rt2560_detach(void *xsc)
 }
 
 static struct ieee80211vap *
-rt2560_vap_create(struct ieee80211com *ic,
-	const char name[IFNAMSIZ], int unit, int opmode, int flags,
-	const uint8_t bssid[IEEE80211_ADDR_LEN],
-	const uint8_t mac[IEEE80211_ADDR_LEN])
+rt2560_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
+    enum ieee80211_opmode opmode, int flags,
+    const uint8_t bssid[IEEE80211_ADDR_LEN],
+    const uint8_t mac[IEEE80211_ADDR_LEN])
 {
 	struct ifnet *ifp = ic->ic_ifp;
 	struct rt2560_vap *rvp;
diff --git a/sys/dev/ral/rt2661.c b/sys/dev/ral/rt2661.c
index 372fcff..c4e8fe7 100644
--- a/sys/dev/ral/rt2661.c
+++ b/sys/dev/ral/rt2661.c
@@ -82,9 +82,9 @@ __FBSDID("$FreeBSD$");
 #endif
 
 static struct ieee80211vap *rt2661_vap_create(struct ieee80211com *,
-			    const char name[IFNAMSIZ], int unit, int opmode,
-			    int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
-			    const uint8_t mac[IEEE80211_ADDR_LEN]);
+			    const char [IFNAMSIZ], int, enum ieee80211_opmode,
+			    int, const uint8_t [IEEE80211_ADDR_LEN],
+			    const uint8_t [IEEE80211_ADDR_LEN]);
 static void		rt2661_vap_delete(struct ieee80211vap *);
 static void		rt2661_dma_map_addr(void *, bus_dma_segment_t *, int,
 			    int);
@@ -368,10 +368,10 @@ rt2661_detach(void *xsc)
 }
 
 static struct ieee80211vap *
-rt2661_vap_create(struct ieee80211com *ic,
-	const char name[IFNAMSIZ], int unit, int opmode, int flags,
-	const uint8_t bssid[IEEE80211_ADDR_LEN],
-	const uint8_t mac[IEEE80211_ADDR_LEN])
+rt2661_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
+    enum ieee80211_opmode opmode, int flags,
+    const uint8_t bssid[IEEE80211_ADDR_LEN],
+    const uint8_t mac[IEEE80211_ADDR_LEN])
 {
 	struct ifnet *ifp = ic->ic_ifp;
 	struct rt2661_vap *rvp;
diff --git a/sys/dev/re/if_re.c b/sys/dev/re/if_re.c
index 3ade04c..92fbbfe 100644
--- a/sys/dev/re/if_re.c
+++ b/sys/dev/re/if_re.c
@@ -294,6 +294,11 @@ static void re_set_rxmode		(struct rl_softc *);
 static void re_reset		(struct rl_softc *);
 static void re_setwol		(struct rl_softc *);
 static void re_clrwol		(struct rl_softc *);
+static void re_set_linkspeed	(struct rl_softc *);
+
+#ifdef DEV_NETMAP	/* see ixgbe.c for details */
+#include <dev/netmap/if_re_netmap.h>
+#endif /* !DEV_NETMAP */
 
 #ifdef RE_DIAG
 static int re_diag		(struct rl_softc *);
@@ -313,16 +318,12 @@ static device_method_t re_methods[] = {
 	DEVMETHOD(device_resume,	re_resume),
 	DEVMETHOD(device_shutdown,	re_shutdown),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	re_miibus_readreg),
 	DEVMETHOD(miibus_writereg,	re_miibus_writereg),
 	DEVMETHOD(miibus_statchg,	re_miibus_statchg),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t re_driver = {
@@ -1405,13 +1406,18 @@ re_attach(device_t dev)
 		    RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP;
 		break;
 	case RL_HWREV_8401E:
-	case RL_HWREV_8402:
 	case RL_HWREV_8105E:
 	case RL_HWREV_8105E_SPIN1:
 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
 		    RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
 		    RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD;
 		break;
+	case RL_HWREV_8402:
+		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
+		    RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
+		    RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD |
+		    RL_FLAG_CMDSTOP_WAIT_TXQ;
+		break;
 	case RL_HWREV_8168B_SPIN1:
 	case RL_HWREV_8168B_SPIN2:
 		sc->rl_flags |= RL_FLAG_WOLRXENB;
@@ -1428,22 +1434,28 @@ re_attach(device_t dev)
 		/* FALLTHROUGH */
 	case RL_HWREV_8168CP:
 	case RL_HWREV_8168D:
-	case RL_HWREV_8168DP:
 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
 		    RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
-		    RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2;
+		    RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK;
+		break;
+	case RL_HWREV_8168DP:
+		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
+		    RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD |
+		    RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK;
 		break;
 	case RL_HWREV_8168E:
 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
 		    RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
-		    RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2;
+		    RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
+		    RL_FLAG_WOL_MANLINK;
 		break;
 	case RL_HWREV_8168E_VL:
 	case RL_HWREV_8168F:
 	case RL_HWREV_8411:
 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
 		    RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
-		    RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2;
+		    RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
+		    RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK;
 		break;
 	case RL_HWREV_8169_8110SB:
 	case RL_HWREV_8169_8110SBL:
@@ -1594,6 +1606,7 @@ re_attach(device_t dev)
 	if (pci_find_cap(sc->rl_dev, PCIY_PMG, &reg) == 0)
 		ifp->if_capabilities |= IFCAP_WOL;
 	ifp->if_capenable = ifp->if_capabilities;
+	ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST);
 	/*
 	 * Don't enable TSO by default.  It is known to generate
 	 * corrupted TCP segments(bad TCP options) under certain
@@ -1611,6 +1624,9 @@ re_attach(device_t dev)
 	 */
 	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
 
+#ifdef DEV_NETMAP
+	re_netmap_attach(sc);
+#endif /* DEV_NETMAP */
 #ifdef RE_DIAG
 	/*
 	 * Perform hardware diagnostic on the original RTL8169.
@@ -1806,6 +1822,9 @@ re_detach(device_t dev)
 		bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
 	}
 
+#ifdef DEV_NETMAP
+	netmap_detach(ifp);
+#endif /* DEV_NETMAP */
 	if (sc->rl_parent_tag)
 		bus_dma_tag_destroy(sc->rl_parent_tag);
 
@@ -1980,6 +1999,9 @@ re_tx_list_init(struct rl_softc *sc)
 	    sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc));
 	for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++)
 		sc->rl_ldata.rl_tx_desc[i].tx_m = NULL;
+#ifdef DEV_NETMAP
+	re_netmap_tx_init(sc);
+#endif /* DEV_NETMAP */
 	/* Set EOR. */
 	desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1];
 	desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR);
@@ -2007,6 +2029,9 @@ re_rx_list_init(struct rl_softc *sc)
 		if ((error = re_newbuf(sc, i)) != 0)
 			return (error);
 	}
+#ifdef DEV_NETMAP
+	re_netmap_rx_init(sc);
+#endif /* DEV_NETMAP */
 
 	/* Flush the RX descriptors */
 
@@ -2063,6 +2088,12 @@ re_rxeof(struct rl_softc *sc, int *rx_npktsp)
 	RL_LOCK_ASSERT(sc);
 
 	ifp = sc->rl_ifp;
+#ifdef DEV_NETMAP
+	if (ifp->if_capenable & IFCAP_NETMAP) {
+		selwakeuppri(&NA(ifp)->rx_rings->si, PI_NET);
+		return 0;
+	}
+#endif /* DEV_NETMAP */
 	if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0)
 		jumbo = 1;
 	else
@@ -2304,6 +2335,12 @@ re_txeof(struct rl_softc *sc)
 		return;
 
 	ifp = sc->rl_ifp;
+#ifdef DEV_NETMAP
+	if (ifp->if_capenable & IFCAP_NETMAP) {
+		selwakeuppri(&NA(ifp)->tx_rings[0].si, PI_NET);
+		return;
+	}
+#endif /* DEV_NETMAP */
 	/* Invalidate the TX descriptor list */
 	bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
 	    sc->rl_ldata.rl_tx_list_map,
@@ -2822,6 +2859,21 @@ re_start_locked(struct ifnet *ifp)
 
 	sc = ifp->if_softc;
 
+#ifdef DEV_NETMAP
+	/* XXX is this necessary ? */
+	if (ifp->if_capenable & IFCAP_NETMAP) {
+		struct netmap_kring *kring = &NA(ifp)->tx_rings[0];
+		if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) {
+			/* kick the tx unit */
+			CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
+#ifdef RE_TX_MODERATION
+			CSR_WRITE_4(sc, RL_TIMERCNT, 1);
+#endif
+			sc->rl_watchdog_timer = 5;
+		}
+		return;
+	}
+#endif /* DEV_NETMAP */
 	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
 	    IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
 		return;
@@ -3197,14 +3249,14 @@ re_init_locked(struct rl_softc *sc)
 	if (sc->rl_testmode)
 		return;
 
-	mii_mediachg(mii);
-
 	CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD);
 
 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 
 	sc->rl_flags &= ~RL_FLAG_LINK;
+	mii_mediachg(mii);
+
 	sc->rl_watchdog_timer = 0;
 	callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
 }
@@ -3459,10 +3511,42 @@ re_stop(struct rl_softc *sc)
 	callout_stop(&sc->rl_stat_callout);
 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
 
-	if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0)
+	/*
+	 * Disable accepting frames to put RX MAC into idle state.
+	 * Otherwise it's possible to get frames while stop command
+	 * execution is in progress and controller can DMA the frame
+	 * to already freed RX buffer during that period.
+	 */
+	CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) &
+	    ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI |
+	    RL_RXCFG_RX_BROAD));
+
+	if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) {
+		for (i = RL_TIMEOUT; i > 0; i--) {
+			if ((CSR_READ_1(sc, sc->rl_txstart) &
+			    RL_TXSTART_START) == 0)
+				break;
+			DELAY(20);
+		}
+		if (i == 0)
+			device_printf(sc->rl_dev,
+			    "stopping TX poll timed out!\n");
+		CSR_WRITE_1(sc, RL_COMMAND, 0x00);
+	} else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) {
 		CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB |
 		    RL_CMD_RX_ENB);
-	else
+		if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) {
+			for (i = RL_TIMEOUT; i > 0; i--) {
+				if ((CSR_READ_4(sc, RL_TXCFG) &
+				    RL_TXCFG_QUEUE_EMPTY) != 0)
+					break;
+				DELAY(100);
+			}
+			if (i == 0)
+				device_printf(sc->rl_dev,
+				   "stopping TXQ timed out!\n");
+		}
+	} else
 		CSR_WRITE_1(sc, RL_COMMAND, 0x00);
 	DELAY(1000);
 	CSR_WRITE_2(sc, RL_IMR, 0x0000);
@@ -3588,6 +3672,74 @@ re_shutdown(device_t dev)
 }
 
 static void
+re_set_linkspeed(struct rl_softc *sc)
+{
+	struct mii_softc *miisc;
+	struct mii_data *mii;
+	int aneg, i, phyno;
+
+	RL_LOCK_ASSERT(sc);
+
+	mii = device_get_softc(sc->rl_miibus);
+	mii_pollstat(mii);
+	aneg = 0;
+	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
+	    (IFM_ACTIVE | IFM_AVALID)) {
+		switch IFM_SUBTYPE(mii->mii_media_active) {
+		case IFM_10_T:
+		case IFM_100_TX:
+			return;
+		case IFM_1000_T:
+			aneg++;
+			break;
+		default:
+			break;
+		}
+	}
+	miisc = LIST_FIRST(&mii->mii_phys);
+	phyno = miisc->mii_phy;
+	LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
+		PHY_RESET(miisc);
+	re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0);
+	re_miibus_writereg(sc->rl_dev, phyno,
+	    MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
+	re_miibus_writereg(sc->rl_dev, phyno,
+	    MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
+	DELAY(1000);
+	if (aneg != 0) {
+		/*
+		 * Poll link state until re(4) get a 10/100Mbps link.
+		 */
+		for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
+			mii_pollstat(mii);
+			if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
+			    == (IFM_ACTIVE | IFM_AVALID)) {
+				switch (IFM_SUBTYPE(mii->mii_media_active)) {
+				case IFM_10_T:
+				case IFM_100_TX:
+					return;
+				default:
+					break;
+				}
+			}
+			RL_UNLOCK(sc);
+			pause("relnk", hz);
+			RL_LOCK(sc);
+		}
+		if (i == MII_ANEGTICKS_GIGE)
+			device_printf(sc->rl_dev,
+			    "establishing a link failed, WOL may not work!");
+	}
+	/*
+	 * No link, force MAC to have 100Mbps, full-duplex link.
+	 * MAC does not require reprogramming on resolved speed/duplex,
+	 * so this is just for completeness.
+	 */
+	mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
+	mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
+}
+
+static void
 re_setwol(struct rl_softc *sc)
 {
 	struct ifnet		*ifp;
@@ -3607,9 +3759,13 @@ re_setwol(struct rl_softc *sc)
 			CSR_WRITE_1(sc, RL_GPIO,
 			    CSR_READ_1(sc, RL_GPIO) & ~0x01);
 	}
-	if ((ifp->if_capenable & IFCAP_WOL) != 0 &&
-	    (sc->rl_flags & RL_FLAG_WOLRXENB) != 0)
-		CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB);
+	if ((ifp->if_capenable & IFCAP_WOL) != 0) {
+		re_set_rxmode(sc);
+		if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0)
+			re_set_linkspeed(sc);
+		if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0)
+			CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB);
+	}
 	/* Enable config register write. */
 	CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
 
@@ -3626,12 +3782,9 @@ re_setwol(struct rl_softc *sc)
 		v |= RL_CFG3_WOL_MAGIC;
 	CSR_WRITE_1(sc, RL_CFG3, v);
 
-	/* Config register write done. */
-	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
-
 	v = CSR_READ_1(sc, RL_CFG5);
-	v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
-	v &= ~RL_CFG5_WOL_LANWAKE;
+	v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST |
+	    RL_CFG5_WOL_LANWAKE);
 	if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
 		v |= RL_CFG5_WOL_UCAST;
 	if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
@@ -3640,6 +3793,9 @@ re_setwol(struct rl_softc *sc)
 		v |= RL_CFG5_WOL_LANWAKE;
 	CSR_WRITE_1(sc, RL_CFG5, v);
 
+	/* Config register write done. */
+	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
+
 	if ((ifp->if_capenable & IFCAP_WOL) != 0 &&
 	    (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0)
 		CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80);
diff --git a/sys/dev/rt/if_rt.c b/sys/dev/rt/if_rt.c
index edaf95e..a1667e5 100644
--- a/sys/dev/rt/if_rt.c
+++ b/sys/dev/rt/if_rt.c
@@ -2588,17 +2588,14 @@ static device_method_t rt_dev_methods[] =
 	DEVMETHOD(device_suspend, rt_suspend),
 	DEVMETHOD(device_resume, rt_resume),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 #ifdef IF_RT_PHY_SUPPORT
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	rt_miibus_readreg),
 	DEVMETHOD(miibus_writereg,	rt_miibus_writereg),
 	DEVMETHOD(miibus_statchg,	rt_miibus_statchg),
 #endif
-	{ 0, 0 }
+
+	DEVMETHOD_END
 };
 
 static driver_t rt_driver =
diff --git a/sys/dev/safe/safe.c b/sys/dev/safe/safe.c
index 00c00ea..a8fbbbb 100644
--- a/sys/dev/safe/safe.c
+++ b/sys/dev/safe/safe.c
@@ -99,16 +99,12 @@ static device_method_t safe_methods[] = {
 	DEVMETHOD(device_resume,	safe_resume),
 	DEVMETHOD(device_shutdown,	safe_shutdown),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* crypto device methods */
 	DEVMETHOD(cryptodev_newsession,	safe_newsession),
 	DEVMETHOD(cryptodev_freesession,safe_freesession),
 	DEVMETHOD(cryptodev_process,	safe_process),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 static driver_t safe_driver = {
 	"safe",
diff --git a/sys/dev/scc/scc_bfe_ebus.c b/sys/dev/scc/scc_bfe_ebus.c
index 6c944f7..2b71a67 100644
--- a/sys/dev/scc/scc_bfe_ebus.c
+++ b/sys/dev/scc/scc_bfe_ebus.c
@@ -84,9 +84,8 @@ static device_method_t scc_ebus_methods[] = {
 	DEVMETHOD(bus_read_ivar,	scc_bus_read_ivar),
 	DEVMETHOD(bus_setup_intr,	scc_bus_setup_intr),
 	DEVMETHOD(bus_teardown_intr,	scc_bus_teardown_intr),
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-	{ 0, 0 }
+
+	DEVMETHOD_END
 };
 
 static driver_t scc_ebus_driver = {
diff --git a/sys/dev/scc/scc_bfe_macio.c b/sys/dev/scc/scc_bfe_macio.c
index 1d7bf82..042788d 100644
--- a/sys/dev/scc/scc_bfe_macio.c
+++ b/sys/dev/scc/scc_bfe_macio.c
@@ -80,9 +80,8 @@ static device_method_t scc_macio_methods[] = {
 	DEVMETHOD(bus_read_ivar,	scc_bus_read_ivar),
 	DEVMETHOD(bus_setup_intr,	scc_bus_setup_intr),
 	DEVMETHOD(bus_teardown_intr,	scc_bus_teardown_intr),
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-	{ 0, 0 }
+
+	DEVMETHOD_END
 };
 
 static driver_t scc_macio_driver = {
diff --git a/sys/dev/scc/scc_bfe_quicc.c b/sys/dev/scc/scc_bfe_quicc.c
index f92aa52..c7e97f3 100644
--- a/sys/dev/scc/scc_bfe_quicc.c
+++ b/sys/dev/scc/scc_bfe_quicc.c
@@ -88,9 +88,8 @@ static device_method_t scc_quicc_methods[] = {
 	DEVMETHOD(bus_read_ivar,	scc_bus_read_ivar),
 	DEVMETHOD(bus_setup_intr,	scc_bus_setup_intr),
 	DEVMETHOD(bus_teardown_intr,	scc_bus_teardown_intr),
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-	{ 0, 0 }
+
+	DEVMETHOD_END
 };
 
 static driver_t scc_quicc_driver = {
diff --git a/sys/dev/scc/scc_bfe_sbus.c b/sys/dev/scc/scc_bfe_sbus.c
index 8eb963f..ba6b25a 100644
--- a/sys/dev/scc/scc_bfe_sbus.c
+++ b/sys/dev/scc/scc_bfe_sbus.c
@@ -80,9 +80,8 @@ static device_method_t scc_sbus_methods[] = {
 	DEVMETHOD(bus_read_ivar,	scc_bus_read_ivar),
 	DEVMETHOD(bus_setup_intr,	scc_bus_setup_intr),
 	DEVMETHOD(bus_teardown_intr,	scc_bus_teardown_intr),
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-	{ 0, 0 }
+
+	DEVMETHOD_END
 };
 
 static driver_t scc_sbus_driver = {
diff --git a/sys/dev/sec/sec.c b/sys/dev/sec/sec.c
index 36fc9ce..3b8c103 100644
--- a/sys/dev/sec/sec.c
+++ b/sys/dev/sec/sec.c
@@ -135,16 +135,12 @@ static device_method_t sec_methods[] = {
 	DEVMETHOD(device_resume,	sec_resume),
 	DEVMETHOD(device_shutdown,	sec_shutdown),
 
-	/* Bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* Crypto methods */
 	DEVMETHOD(cryptodev_newsession,	sec_newsession),
 	DEVMETHOD(cryptodev_freesession,sec_freesession),
 	DEVMETHOD(cryptodev_process,	sec_process),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 static driver_t sec_driver = {
 	"sec",
diff --git a/sys/dev/sf/if_sf.c b/sys/dev/sf/if_sf.c
index e919f55..251f310 100644
--- a/sys/dev/sf/if_sf.c
+++ b/sys/dev/sf/if_sf.c
@@ -212,16 +212,12 @@ static device_method_t sf_methods[] = {
 	DEVMETHOD(device_suspend,	sf_suspend),
 	DEVMETHOD(device_resume,	sf_resume),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	sf_miibus_readreg),
 	DEVMETHOD(miibus_writereg,	sf_miibus_writereg),
 	DEVMETHOD(miibus_statchg,	sf_miibus_statchg),
 
-	{ NULL, NULL }
+	DEVMETHOD_END
 };
 
 static driver_t sf_driver = {
diff --git a/sys/dev/sfxge/common/efsys.h b/sys/dev/sfxge/common/efsys.h
index 3e83d24..18456d5 100644
--- a/sys/dev/sfxge/common/efsys.h
+++ b/sys/dev/sfxge/common/efsys.h
@@ -25,14 +25,13 @@
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
+ * $FreeBSD$
  */
 
 #ifndef	_SYS_EFSYS_H
 #define	_SYS_EFSYS_H
 
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
 #ifdef	__cplusplus
 extern "C" {
 #endif
diff --git a/sys/dev/sfxge/common/efx.h b/sys/dev/sfxge/common/efx.h
index 18c248b..a0f2025 100644
--- a/sys/dev/sfxge/common/efx.h
+++ b/sys/dev/sfxge/common/efx.h
@@ -21,6 +21,8 @@
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
+ * $FreeBSD$
  */
 
 #ifndef	_SYS_EFX_H
diff --git a/sys/dev/sfxge/common/efx_bootcfg.c b/sys/dev/sfxge/common/efx_bootcfg.c
index 1a6a79c..d770a5c 100644
--- a/sys/dev/sfxge/common/efx_bootcfg.c
+++ b/sys/dev/sfxge/common/efx_bootcfg.c
@@ -23,6 +23,9 @@
  * SUCH DAMAGE.
  */
 
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #include "efsys.h"
 #include "efx.h"
 #include "efx_types.h"
diff --git a/sys/dev/sfxge/common/efx_ev.c b/sys/dev/sfxge/common/efx_ev.c
index 2203bc1..1ce8218 100644
--- a/sys/dev/sfxge/common/efx_ev.c
+++ b/sys/dev/sfxge/common/efx_ev.c
@@ -23,6 +23,9 @@
  * SUCH DAMAGE.
  */
 
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #include "efsys.h"
 #include "efx.h"
 #include "efx_types.h"
diff --git a/sys/dev/sfxge/common/efx_filter.c b/sys/dev/sfxge/common/efx_filter.c
index e915e9c..fa17ae3 100644
--- a/sys/dev/sfxge/common/efx_filter.c
+++ b/sys/dev/sfxge/common/efx_filter.c
@@ -23,6 +23,9 @@
  * SUCH DAMAGE.
  */
 
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #include "efsys.h"
 #include "efx.h"
 #include "efx_types.h"
diff --git a/sys/dev/sfxge/common/efx_impl.h b/sys/dev/sfxge/common/efx_impl.h
index 5858e96..31681f2 100644
--- a/sys/dev/sfxge/common/efx_impl.h
+++ b/sys/dev/sfxge/common/efx_impl.h
@@ -21,6 +21,8 @@
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
+ * $FreeBSD$
  */
 
 #ifndef	_SYS_EFX_IMPL_H
diff --git a/sys/dev/sfxge/common/efx_intr.c b/sys/dev/sfxge/common/efx_intr.c
index 77780b1..556728d 100644
--- a/sys/dev/sfxge/common/efx_intr.c
+++ b/sys/dev/sfxge/common/efx_intr.c
@@ -23,6 +23,9 @@
  * SUCH DAMAGE.
  */
 
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #include "efsys.h"
 #include "efx.h"
 #include "efx_types.h"
diff --git a/sys/dev/sfxge/common/efx_mac.c b/sys/dev/sfxge/common/efx_mac.c
index 6852584..5b868ed 100644
--- a/sys/dev/sfxge/common/efx_mac.c
+++ b/sys/dev/sfxge/common/efx_mac.c
@@ -23,6 +23,9 @@
  * SUCH DAMAGE.
  */
 
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #include "efsys.h"
 #include "efx.h"
 #include "efx_types.h"
diff --git a/sys/dev/sfxge/common/efx_mcdi.c b/sys/dev/sfxge/common/efx_mcdi.c
index 7d01e9b..20c5bc6 100644
--- a/sys/dev/sfxge/common/efx_mcdi.c
+++ b/sys/dev/sfxge/common/efx_mcdi.c
@@ -23,6 +23,9 @@
  * SUCH DAMAGE.
  */
 
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #include "efsys.h"
 #include "efx.h"
 #include "efx_types.h"
diff --git a/sys/dev/sfxge/common/efx_mcdi.h b/sys/dev/sfxge/common/efx_mcdi.h
index ef0ba90..cc3a6de 100644
--- a/sys/dev/sfxge/common/efx_mcdi.h
+++ b/sys/dev/sfxge/common/efx_mcdi.h
@@ -21,6 +21,8 @@
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
+ * $FreeBSD$
  */
 
 #ifndef _SYS_EFX_MCDI_H
diff --git a/sys/dev/sfxge/common/efx_mon.c b/sys/dev/sfxge/common/efx_mon.c
index 0d3221a..5d397c3 100644
--- a/sys/dev/sfxge/common/efx_mon.c
+++ b/sys/dev/sfxge/common/efx_mon.c
@@ -23,6 +23,9 @@
  * SUCH DAMAGE.
  */
 
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #include "efsys.h"
 #include "efx.h"
 #include "efx_types.h"
diff --git a/sys/dev/sfxge/common/efx_nic.c b/sys/dev/sfxge/common/efx_nic.c
index 07ce009..fdbe5a2 100644
--- a/sys/dev/sfxge/common/efx_nic.c
+++ b/sys/dev/sfxge/common/efx_nic.c
@@ -23,6 +23,9 @@
  * SUCH DAMAGE.
  */
 
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #include "efsys.h"
 #include "efx.h"
 #include "efx_types.h"
diff --git a/sys/dev/sfxge/common/efx_nvram.c b/sys/dev/sfxge/common/efx_nvram.c
index d4cf741..2df9bb9 100644
--- a/sys/dev/sfxge/common/efx_nvram.c
+++ b/sys/dev/sfxge/common/efx_nvram.c
@@ -23,6 +23,9 @@
  * SUCH DAMAGE.
  */
 
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #include "efsys.h"
 #include "efx.h"
 #include "efx_types.h"
diff --git a/sys/dev/sfxge/common/efx_phy.c b/sys/dev/sfxge/common/efx_phy.c
index 0b098ec..0300e04 100644
--- a/sys/dev/sfxge/common/efx_phy.c
+++ b/sys/dev/sfxge/common/efx_phy.c
@@ -23,6 +23,9 @@
  * SUCH DAMAGE.
  */
 
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #include "efsys.h"
 #include "efx.h"
 #include "efx_types.h"
diff --git a/sys/dev/sfxge/common/efx_port.c b/sys/dev/sfxge/common/efx_port.c
index cbb0b3b..0b67d06 100644
--- a/sys/dev/sfxge/common/efx_port.c
+++ b/sys/dev/sfxge/common/efx_port.c
@@ -23,6 +23,9 @@
  * SUCH DAMAGE.
  */
 
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #include "efsys.h"
 #include "efx.h"
 #include "efx_types.h"
diff --git a/sys/dev/sfxge/common/efx_regs.h b/sys/dev/sfxge/common/efx_regs.h
index c31c33e..6426ae7 100644
--- a/sys/dev/sfxge/common/efx_regs.h
+++ b/sys/dev/sfxge/common/efx_regs.h
@@ -21,6 +21,8 @@
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
+ * $FreeBSD$
  */
 
 #ifndef	_SYS_EFX_REGS_H
diff --git a/sys/dev/sfxge/common/efx_regs_ef10.h b/sys/dev/sfxge/common/efx_regs_ef10.h
index 62c0372..ef62b58 100644
--- a/sys/dev/sfxge/common/efx_regs_ef10.h
+++ b/sys/dev/sfxge/common/efx_regs_ef10.h
@@ -21,6 +21,8 @@
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
+ * $FreeBSD$
  */
 
 #ifndef	_SYS_EFX_EF10_REGS_H
diff --git a/sys/dev/sfxge/common/efx_regs_mcdi.h b/sys/dev/sfxge/common/efx_regs_mcdi.h
index 720770c..8246f89 100644
--- a/sys/dev/sfxge/common/efx_regs_mcdi.h
+++ b/sys/dev/sfxge/common/efx_regs_mcdi.h
@@ -21,10 +21,10 @@
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
+ * $FreeBSD$
  */
 
-/*! \cidoxg_firmware_mc_cmd */
-
 #ifndef _SIENA_MC_DRIVER_PCOL_H
 #define	_SIENA_MC_DRIVER_PCOL_H
 
@@ -2783,4 +2783,3 @@
 #define	MC_CMD_TCM_TXQ_INIT_OUT_LEN 0
 
 #endif /* _SIENA_MC_DRIVER_PCOL_H */
-/*! \cidoxg_end */
diff --git a/sys/dev/sfxge/common/efx_regs_pci.h b/sys/dev/sfxge/common/efx_regs_pci.h
index cb5efab..3a3a827 100644
--- a/sys/dev/sfxge/common/efx_regs_pci.h
+++ b/sys/dev/sfxge/common/efx_regs_pci.h
@@ -21,6 +21,8 @@
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
+ * $FreeBSD$
  */
 
 #ifndef	_SYS_EFX_REGS_PCI_H
diff --git a/sys/dev/sfxge/common/efx_rx.c b/sys/dev/sfxge/common/efx_rx.c
index 7d3d7c1..5b52d86 100644
--- a/sys/dev/sfxge/common/efx_rx.c
+++ b/sys/dev/sfxge/common/efx_rx.c
@@ -23,6 +23,9 @@
  * SUCH DAMAGE.
  */
 
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #include "efsys.h"
 #include "efx.h"
 #include "efx_types.h"
diff --git a/sys/dev/sfxge/common/efx_sram.c b/sys/dev/sfxge/common/efx_sram.c
index 16a3229..f081adf 100644
--- a/sys/dev/sfxge/common/efx_sram.c
+++ b/sys/dev/sfxge/common/efx_sram.c
@@ -23,6 +23,9 @@
  * SUCH DAMAGE.
  */
 
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #include "efsys.h"
 #include "efx.h"
 #include "efx_types.h"
diff --git a/sys/dev/sfxge/common/efx_tx.c b/sys/dev/sfxge/common/efx_tx.c
index 0dc347c..56a47fa 100644
--- a/sys/dev/sfxge/common/efx_tx.c
+++ b/sys/dev/sfxge/common/efx_tx.c
@@ -23,6 +23,9 @@
  * SUCH DAMAGE.
  */
 
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #include "efsys.h"
 #include "efx.h"
 #include "efx_types.h"
diff --git a/sys/dev/sfxge/common/efx_types.h b/sys/dev/sfxge/common/efx_types.h
index d691482..9fbaea1 100644
--- a/sys/dev/sfxge/common/efx_types.h
+++ b/sys/dev/sfxge/common/efx_types.h
@@ -23,6 +23,8 @@
  * SUCH DAMAGE.
  *
  * Ackowledgement to Fen Systems Ltd.
+ *
+ * $FreeBSD$
  */
 
 #ifndef	_SYS_EFX_TYPES_H
diff --git a/sys/dev/sfxge/common/efx_vpd.c b/sys/dev/sfxge/common/efx_vpd.c
index 699e890..399c056 100644
--- a/sys/dev/sfxge/common/efx_vpd.c
+++ b/sys/dev/sfxge/common/efx_vpd.c
@@ -23,6 +23,9 @@
  * SUCH DAMAGE.
  */
 
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #include "efsys.h"
 #include "efx.h"
 #include "efx_types.h"
diff --git a/sys/dev/sfxge/common/efx_wol.c b/sys/dev/sfxge/common/efx_wol.c
index 74f11de..89a80c7 100644
--- a/sys/dev/sfxge/common/efx_wol.c
+++ b/sys/dev/sfxge/common/efx_wol.c
@@ -23,6 +23,9 @@
  * SUCH DAMAGE.
  */
 
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #include "efsys.h"
 #include "efx.h"
 #include "efx_types.h"
diff --git a/sys/dev/sfxge/common/siena_flash.h b/sys/dev/sfxge/common/siena_flash.h
index 7df3995..1378b91 100644
--- a/sys/dev/sfxge/common/siena_flash.h
+++ b/sys/dev/sfxge/common/siena_flash.h
@@ -21,9 +21,10 @@
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
+ * $FreeBSD$
  */
 
-
 #ifndef	_SYS_SIENA_FLASH_H
 #define	_SYS_SIENA_FLASH_H
 
diff --git a/sys/dev/sfxge/common/siena_impl.h b/sys/dev/sfxge/common/siena_impl.h
index b566adb..9d02808 100644
--- a/sys/dev/sfxge/common/siena_impl.h
+++ b/sys/dev/sfxge/common/siena_impl.h
@@ -21,6 +21,8 @@
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
+ * $FreeBSD$
  */
 
 #ifndef _SYS_SIENA_IMPL_H
diff --git a/sys/dev/sfxge/common/siena_mac.c b/sys/dev/sfxge/common/siena_mac.c
index 7facf1c..e5c8f3c 100644
--- a/sys/dev/sfxge/common/siena_mac.c
+++ b/sys/dev/sfxge/common/siena_mac.c
@@ -22,6 +22,10 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #include "efsys.h"
 #include "efx.h"
 #include "efx_impl.h"
diff --git a/sys/dev/sfxge/common/siena_mon.c b/sys/dev/sfxge/common/siena_mon.c
index de9a1df..de7b793 100644
--- a/sys/dev/sfxge/common/siena_mon.c
+++ b/sys/dev/sfxge/common/siena_mon.c
@@ -22,6 +22,10 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #include "efsys.h"
 #include "efx.h"
 #include "efx_impl.h"
diff --git a/sys/dev/sfxge/common/siena_nic.c b/sys/dev/sfxge/common/siena_nic.c
index 9eb0db2..e52503b 100644
--- a/sys/dev/sfxge/common/siena_nic.c
+++ b/sys/dev/sfxge/common/siena_nic.c
@@ -22,6 +22,10 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #include "efsys.h"
 #include "efx.h"
 #include "efx_impl.h"
diff --git a/sys/dev/sfxge/common/siena_nvram.c b/sys/dev/sfxge/common/siena_nvram.c
index 9cdd3ad..e883ce1 100644
--- a/sys/dev/sfxge/common/siena_nvram.c
+++ b/sys/dev/sfxge/common/siena_nvram.c
@@ -23,6 +23,9 @@
  * SUCH DAMAGE.
  */
 
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #include "efsys.h"
 #include "efx.h"
 #include "efx_types.h"
diff --git a/sys/dev/sfxge/common/siena_phy.c b/sys/dev/sfxge/common/siena_phy.c
index 7eb8468..4189e23 100644
--- a/sys/dev/sfxge/common/siena_phy.c
+++ b/sys/dev/sfxge/common/siena_phy.c
@@ -22,6 +22,10 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #include "efsys.h"
 #include "efx.h"
 #include "efx_impl.h"
diff --git a/sys/dev/sfxge/common/siena_sram.c b/sys/dev/sfxge/common/siena_sram.c
index 64fce98..9c13e1d 100644
--- a/sys/dev/sfxge/common/siena_sram.c
+++ b/sys/dev/sfxge/common/siena_sram.c
@@ -22,6 +22,10 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #include "efsys.h"
 #include "efx.h"
 #include "efx_impl.h"
diff --git a/sys/dev/sfxge/common/siena_vpd.c b/sys/dev/sfxge/common/siena_vpd.c
index 5c44608..cd643c8 100644
--- a/sys/dev/sfxge/common/siena_vpd.c
+++ b/sys/dev/sfxge/common/siena_vpd.c
@@ -23,6 +23,9 @@
  * SUCH DAMAGE.
  */
 
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #include "efsys.h"
 #include "efx.h"
 #include "efx_types.h"
diff --git a/sys/dev/sfxge/sfxge.c b/sys/dev/sfxge/sfxge.c
index 380215a..18428cf 100644
--- a/sys/dev/sfxge/sfxge.c
+++ b/sys/dev/sfxge/sfxge.c
@@ -757,11 +757,7 @@ static device_method_t sfxge_methods[] = {
 	DEVMETHOD(device_attach,	sfxge_attach),
 	DEVMETHOD(device_detach,	sfxge_detach),
 
-	/* Bus interface. */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t sfxge_devclass;
diff --git a/sys/dev/sge/if_sge.c b/sys/dev/sge/if_sge.c
index c56760d..68679fe 100644
--- a/sys/dev/sge/if_sge.c
+++ b/sys/dev/sge/if_sge.c
@@ -158,16 +158,12 @@ static device_method_t sge_methods[] = {
 	DEVMETHOD(device_resume,	sge_resume),
 	DEVMETHOD(device_shutdown,	sge_shutdown),
 
-	/* Bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	sge_miibus_readreg),
 	DEVMETHOD(miibus_writereg,	sge_miibus_writereg),
 	DEVMETHOD(miibus_statchg,	sge_miibus_statchg),
 
-	KOBJMETHOD_END
+	DEVMETHOD_END
 };
 
 static driver_t sge_driver = {
diff --git a/sys/dev/siba/siba.c b/sys/dev/siba/siba.c
index b2c49fb..ebe7190 100644
--- a/sys/dev/siba/siba.c
+++ b/sys/dev/siba/siba.c
@@ -632,7 +632,7 @@ static device_method_t siba_methods[] = {
 	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
 	DEVMETHOD(bus_write_ivar,	siba_write_ivar),
 
-	KOBJMETHOD_END
+	DEVMETHOD_END
 };
 
 static driver_t siba_driver = {
diff --git a/sys/dev/siba/siba_bwn.c b/sys/dev/siba/siba_bwn.c
index a778d49..43c52bd 100644
--- a/sys/dev/siba/siba_bwn.c
+++ b/sys/dev/siba/siba_bwn.c
@@ -410,7 +410,7 @@ static device_method_t siba_bwn_methods[] = {
 	DEVMETHOD(pci_release_msi,	siba_bwn_release_msi),
 	DEVMETHOD(pci_msi_count,	siba_bwn_msi_count),
 
-	KOBJMETHOD_END
+	DEVMETHOD_END
 };
 static driver_t siba_bwn_driver = {
 	"siba_bwn",
diff --git a/sys/dev/siba/siba_cc.c b/sys/dev/siba/siba_cc.c
index 67af696..d74e809b 100644
--- a/sys/dev/siba/siba_cc.c
+++ b/sys/dev/siba/siba_cc.c
@@ -141,7 +141,7 @@ static device_method_t siba_cc_methods[] = {
 	DEVMETHOD(device_attach,	siba_cc_attach),
 	DEVMETHOD(device_probe,		siba_cc_probe),
 
-	KOBJMETHOD_END
+	DEVMETHOD_END
 };
 
 static driver_t siba_cc_driver = {
diff --git a/sys/dev/siba/siba_core.c b/sys/dev/siba/siba_core.c
index 61652ad..4c7dfee 100644
--- a/sys/dev/siba/siba_core.c
+++ b/sys/dev/siba/siba_core.c
@@ -215,7 +215,7 @@ int
 siba_core_detach(struct siba_softc *siba)
 {
 	/* detach & delete all children */
-	device_delete_all_children(siba->siba_dev);
+	device_delete_children(siba->siba_dev);
 	return (0);
 }
 
diff --git a/sys/dev/siba/siba_pcib.c b/sys/dev/siba/siba_pcib.c
index d6ddeb6..6236aed 100644
--- a/sys/dev/siba/siba_pcib.c
+++ b/sys/dev/siba/siba_pcib.c
@@ -403,7 +403,6 @@ static device_method_t siba_pcib_methods[] = {
 	DEVMETHOD(device_probe,		siba_pcib_probe),
 
 	/* Bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
 	DEVMETHOD(bus_read_ivar,	siba_pcib_read_ivar),
 	DEVMETHOD(bus_write_ivar,	siba_pcib_write_ivar),
 	DEVMETHOD(bus_setup_intr,	siba_pcib_setup_intr),
@@ -419,7 +418,7 @@ static device_method_t siba_pcib_methods[] = {
 	DEVMETHOD(pcib_write_config,	siba_pcib_write_config),
 	DEVMETHOD(pcib_route_interrupt,	siba_pcib_route_interrupt),
 
-	KOBJMETHOD_END
+	DEVMETHOD_END
 };
 
 static driver_t siba_pcib_driver = {
diff --git a/sys/dev/siis/siis.c b/sys/dev/siis/siis.c
index 40c17cb..17c1a39 100644
--- a/sys/dev/siis/siis.c
+++ b/sys/dev/siis/siis.c
@@ -207,7 +207,7 @@ siis_detach(device_t dev)
 	struct siis_controller *ctlr = device_get_softc(dev);
 
 	/* Detach & delete all children */
-	device_delete_all_children(dev);
+	device_delete_children(dev);
 
 	/* Free interrupts. */
 	if (ctlr->irq.r_irq) {
diff --git a/sys/dev/sio/sio.c b/sys/dev/sio/sio.c
index 7e2054e..d389f45 100644
--- a/sys/dev/sio/sio.c
+++ b/sys/dev/sio/sio.c
@@ -2293,6 +2293,8 @@ static cn_init_t sio_cninit;
 static cn_term_t sio_cnterm;
 static cn_getc_t sio_cngetc;
 static cn_putc_t sio_cnputc;
+static cn_grab_t sio_cngrab;
+static cn_ungrab_t sio_cnungrab;
 
 CONSOLE_DRIVER(sio);
 
@@ -2512,6 +2514,16 @@ sio_cnterm(cp)
 	comconsole = -1;
 }
 
+static void
+sio_cngrab(struct consdev *cp)
+{
+}
+
+static void
+sio_cnungrab(struct consdev *cp)
+{
+}
+
 static int
 sio_cngetc(struct consdev *cd)
 {
diff --git a/sys/dev/sis/if_sis.c b/sys/dev/sis/if_sis.c
index 630281d..ba8106e 100644
--- a/sys/dev/sis/if_sis.c
+++ b/sys/dev/sis/if_sis.c
@@ -2393,16 +2393,12 @@ static device_method_t sis_methods[] = {
 	DEVMETHOD(device_suspend,	sis_suspend),
 	DEVMETHOD(device_resume,	sis_resume),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	sis_miibus_readreg),
 	DEVMETHOD(miibus_writereg,	sis_miibus_writereg),
 	DEVMETHOD(miibus_statchg,	sis_miibus_statchg),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t sis_driver = {
diff --git a/sys/dev/sk/if_sk.c b/sys/dev/sk/if_sk.c
index 4d2abb8..b217784 100644
--- a/sys/dev/sk/if_sk.c
+++ b/sys/dev/sk/if_sk.c
@@ -296,11 +296,7 @@ static device_method_t skc_methods[] = {
 	DEVMETHOD(device_resume,	skc_resume),
 	DEVMETHOD(device_shutdown,	skc_shutdown),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t skc_driver = {
@@ -318,16 +314,12 @@ static device_method_t sk_methods[] = {
 	DEVMETHOD(device_detach,	sk_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	sk_miibus_readreg),
 	DEVMETHOD(miibus_writereg,	sk_miibus_writereg),
 	DEVMETHOD(miibus_statchg,	sk_miibus_statchg),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t sk_driver = {
diff --git a/sys/dev/smbus/smbus.c b/sys/dev/smbus/smbus.c
index 1c17f6d..a111332 100644
--- a/sys/dev/smbus/smbus.c
+++ b/sys/dev/smbus/smbus.c
@@ -55,11 +55,10 @@ static device_method_t smbus_methods[] = {
         DEVMETHOD(device_attach,        smbus_attach),
         DEVMETHOD(device_detach,        smbus_detach),
 
-        /* bus interface */
+	/* bus interface */
 	DEVMETHOD(bus_add_child,	bus_generic_add_child),
-        DEVMETHOD(bus_print_child,	bus_generic_print_child),
 
-        { 0, 0 }
+	DEVMETHOD_END
 };
 
 driver_t smbus_driver = {
diff --git a/sys/dev/sound/isa/gusc.c b/sys/dev/sound/isa/gusc.c
index ef211c6..58ac346 100644
--- a/sys/dev/sound/isa/gusc.c
+++ b/sys/dev/sound/isa/gusc.c
@@ -644,7 +644,6 @@ static device_method_t gusc_methods[] = {
 	DEVMETHOD(device_resume,	bus_generic_resume),
 
 	/* Bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
 	DEVMETHOD(bus_alloc_resource,	gusc_alloc_resource),
 	DEVMETHOD(bus_release_resource,	gusc_release_resource),
 	DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
@@ -652,7 +651,7 @@ static device_method_t gusc_methods[] = {
 	DEVMETHOD(bus_setup_intr,	gusc_setup_intr),
 	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t gusc_driver = {
diff --git a/sys/dev/sound/isa/sbc.c b/sys/dev/sound/isa/sbc.c
index 3df2738..aa6003b 100644
--- a/sys/dev/sound/isa/sbc.c
+++ b/sys/dev/sound/isa/sbc.c
@@ -790,7 +790,6 @@ static device_method_t sbc_methods[] = {
 	/* Bus interface */
 	DEVMETHOD(bus_read_ivar,	sbc_read_ivar),
 	DEVMETHOD(bus_write_ivar,	sbc_write_ivar),
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
 	DEVMETHOD(bus_alloc_resource,	sbc_alloc_resource),
 	DEVMETHOD(bus_release_resource,	sbc_release_resource),
 	DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
@@ -798,7 +797,7 @@ static device_method_t sbc_methods[] = {
 	DEVMETHOD(bus_setup_intr,	sbc_setup_intr),
 	DEVMETHOD(bus_teardown_intr,	sbc_teardown_intr),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t sbc_driver = {
diff --git a/sys/dev/sound/pci/csa.c b/sys/dev/sound/pci/csa.c
index 28eae75..04ea4ec 100644
--- a/sys/dev/sound/pci/csa.c
+++ b/sys/dev/sound/pci/csa.c
@@ -1076,7 +1076,6 @@ static device_method_t csa_methods[] = {
 	DEVMETHOD(device_resume,	csa_resume),
 
 	/* Bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
 	DEVMETHOD(bus_alloc_resource,	csa_alloc_resource),
 	DEVMETHOD(bus_release_resource,	csa_release_resource),
 	DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
@@ -1084,7 +1083,7 @@ static device_method_t csa_methods[] = {
 	DEVMETHOD(bus_setup_intr,	csa_setup_intr),
 	DEVMETHOD(bus_teardown_intr,	csa_teardown_intr),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t csa_driver = {
diff --git a/sys/dev/sound/pci/emu10k1.c b/sys/dev/sound/pci/emu10k1.c
index 4c02fa4..cbf89a0 100644
--- a/sys/dev/sound/pci/emu10k1.c
+++ b/sys/dev/sound/pci/emu10k1.c
@@ -32,7 +32,7 @@
 
 #include <dev/sound/pcm/sound.h>
 #include <dev/sound/pcm/ac97.h>
-#include "emu10k1-alsa%diked.h"
+#include <dev/sound/pci/emuxkireg.h>
 
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
@@ -66,12 +66,94 @@ SND_DECLARE_FILE("$FreeBSD$");
 
 #define	ENABLE		0xffffffff
 #define	DISABLE		0x00000000
-#define	ENV_ON		DCYSUSV_CHANNELENABLE_MASK
+#define	ENV_ON		EMU_CHAN_DCYSUSV_CHANNELENABLE_MASK
 #define	ENV_OFF		0x00	/* XXX: should this be 1? */
 
-#define	A_IOCFG_GPOUT_A	0x40	/* Analog Output */
-#define	A_IOCFG_GPOUT_D	0x04	/* Digital Output */
-#define	A_IOCFG_GPOUT_AD (A_IOCFG_GPOUT_A|A_IOCFG_GPOUT_D)  /* A_IOCFG_GPOUT0 */
+#define	EMU_A_IOCFG_GPOUT_A	0x40
+#define	EMU_A_IOCFG_GPOUT_D	0x04
+#define	EMU_A_IOCFG_GPOUT_AD (EMU_A_IOCFG_GPOUT_A|EMU_A_IOCFG_GPOUT_D)  /* EMU_A_IOCFG_GPOUT0 */
+
+#define	EMU_HCFG_GPOUT1		0x00000800
+
+/* instruction set */
+#define iACC3	 0x06
+#define iMACINT0 0x04
+#define iINTERP  0x0e
+
+#define C_00000000	0x40
+#define C_00000001	0x41
+#define C_00000004	0x44
+#define C_40000000	0x4d
+/* Audigy constants */
+#define A_C_00000000	0xc0
+#define A_C_40000000	0xcd
+
+/* GPRs */
+#define FXBUS(x)	(0x00 + (x))
+#define EXTIN(x)	(0x10 + (x))
+#define EXTOUT(x)	(0x20 + (x))
+
+#define GPR(x)		(EMU_FXGPREGBASE + (x))
+#define A_EXTIN(x)	(0x40 + (x))
+#define A_FXBUS(x)	(0x00 + (x))
+#define A_EXTOUT(x)	(0x60 + (x))
+#define A_GPR(x)	(EMU_A_FXGPREGBASE + (x))
+
+/* FX buses */
+#define FXBUS_PCM_LEFT		0x00
+#define FXBUS_PCM_RIGHT		0x01
+#define FXBUS_MIDI_LEFT		0x04
+#define FXBUS_MIDI_RIGHT	0x05
+#define FXBUS_MIDI_REVERB	0x0c
+#define FXBUS_MIDI_CHORUS	0x0d
+
+/* Inputs */
+#define EXTIN_AC97_L		0x00
+#define EXTIN_AC97_R		0x01
+#define EXTIN_SPDIF_CD_L	0x02
+#define EXTIN_SPDIF_CD_R	0x03
+#define EXTIN_TOSLINK_L		0x06
+#define EXTIN_TOSLINK_R		0x07
+#define EXTIN_COAX_SPDIF_L	0x0a
+#define EXTIN_COAX_SPDIF_R	0x0b
+/* Audigy Inputs */
+#define A_EXTIN_AC97_L		0x00
+#define A_EXTIN_AC97_R		0x01
+
+/* Outputs */
+#define EXTOUT_AC97_L	   0x00
+#define EXTOUT_AC97_R	   0x01
+#define EXTOUT_TOSLINK_L   0x02
+#define EXTOUT_TOSLINK_R   0x03
+#define EXTOUT_AC97_CENTER 0x04
+#define EXTOUT_AC97_LFE	   0x05
+#define EXTOUT_HEADPHONE_L 0x06
+#define EXTOUT_HEADPHONE_R 0x07
+#define EXTOUT_REAR_L	   0x08
+#define EXTOUT_REAR_R	   0x09
+#define EXTOUT_ADC_CAP_L   0x0a
+#define EXTOUT_ADC_CAP_R   0x0b
+#define EXTOUT_ACENTER	   0x11
+#define EXTOUT_ALFE	   0x12
+/* Audigy Outputs */
+#define A_EXTOUT_FRONT_L	0x00
+#define A_EXTOUT_FRONT_R	0x01
+#define A_EXTOUT_CENTER		0x02
+#define A_EXTOUT_LFE		0x03
+#define A_EXTOUT_HEADPHONE_L	0x04
+#define A_EXTOUT_HEADPHONE_R	0x05
+#define A_EXTOUT_REAR_L		0x06
+#define A_EXTOUT_REAR_R		0x07
+#define A_EXTOUT_AFRONT_L	0x08
+#define A_EXTOUT_AFRONT_R	0x09
+#define A_EXTOUT_ACENTER	0x0a
+#define A_EXTOUT_ALFE		0x0b
+#define A_EXTOUT_AREAR_L	0x0e
+#define A_EXTOUT_AREAR_R	0x0f
+#define A_EXTOUT_AC97_L		0x10
+#define A_EXTOUT_AC97_R		0x11
+#define A_EXTOUT_ADC_CAP_L	0x16
+#define A_EXTOUT_ADC_CAP_R	0x17
 
 struct emu_memblk {
 	SLIST_ENTRY(emu_memblk) link;
@@ -247,9 +329,9 @@ emu_rdptr(struct sc_info *sc, int chn, int reg)
 {
 	u_int32_t ptr, val, mask, size, offset;
 
-	ptr = ((reg << 16) & sc->addrmask) | (chn & PTR_CHANNELNUM_MASK);
-	emu_wr(sc, PTR, ptr, 4);
-	val = emu_rd(sc, DATA, 4);
+	ptr = ((reg << 16) & sc->addrmask) | (chn & EMU_PTR_CHNO_MASK);
+	emu_wr(sc, EMU_PTR, ptr, 4);
+	val = emu_rd(sc, EMU_DATA, 4);
 	if (reg & 0xff000000) {
 		size = (reg >> 24) & 0x3f;
 		offset = (reg >> 16) & 0x1f;
@@ -265,23 +347,23 @@ emu_wrptr(struct sc_info *sc, int chn, int reg, u_int32_t data)
 {
 	u_int32_t ptr, mask, size, offset;
 
-	ptr = ((reg << 16) & sc->addrmask) | (chn & PTR_CHANNELNUM_MASK);
-	emu_wr(sc, PTR, ptr, 4);
+	ptr = ((reg << 16) & sc->addrmask) | (chn & EMU_PTR_CHNO_MASK);
+	emu_wr(sc, EMU_PTR, ptr, 4);
 	if (reg & 0xff000000) {
 		size = (reg >> 24) & 0x3f;
 		offset = (reg >> 16) & 0x1f;
 		mask = ((1 << size) - 1) << offset;
 		data <<= offset;
 		data &= mask;
-		data |= emu_rd(sc, DATA, 4) & ~mask;
+		data |= emu_rd(sc, EMU_DATA, 4) & ~mask;
 	}
-	emu_wr(sc, DATA, data, 4);
+	emu_wr(sc, EMU_DATA, data, 4);
 }
 
 static void
 emu_wrefx(struct sc_info *sc, unsigned int pc, unsigned int data)
 {
-	pc += sc->audigy ? A_MICROCODEBASE : MICROCODEBASE;
+	pc += sc->audigy ? EMU_A_MICROCODEBASE : EMU_MICROCODEBASE;
 	emu_wrptr(sc, 0, pc, data);
 }
 
@@ -294,8 +376,8 @@ emu_rdcd(kobj_t obj, void *devinfo, int regno)
 {
 	struct sc_info *sc = (struct sc_info *)devinfo;
 
-	emu_wr(sc, AC97ADDRESS, regno, 1);
-	return emu_rd(sc, AC97DATA, 2);
+	emu_wr(sc, EMU_AC97ADDR, regno, 1);
+	return emu_rd(sc, EMU_AC97DATA, 2);
 }
 
 static int
@@ -303,8 +385,8 @@ emu_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
 {
 	struct sc_info *sc = (struct sc_info *)devinfo;
 
-	emu_wr(sc, AC97ADDRESS, regno, 1);
-	emu_wr(sc, AC97DATA, data, 2);
+	emu_wr(sc, EMU_AC97ADDR, regno, 1);
+	emu_wr(sc, EMU_AC97DATA, data, 2);
 	return 0;
 }
 
@@ -346,7 +428,7 @@ emu_settimer(struct sc_info *sc)
 	}
 	RANGE(rate, 48, 9600);
 	sc->timerinterval = 48000 / rate;
-	emu_wr(sc, TIMER, sc->timerinterval & 0x03ff, 2);
+	emu_wr(sc, EMU_TIMER, sc->timerinterval & 0x03ff, 2);
 
 	return sc->timerinterval;
 }
@@ -357,15 +439,15 @@ emu_enatimer(struct sc_info *sc, int go)
 	u_int32_t x;
 	if (go) {
 		if (sc->timer++ == 0) {
-			x = emu_rd(sc, INTE, 4);
-			x |= INTE_INTERVALTIMERENB;
-			emu_wr(sc, INTE, x, 4);
+			x = emu_rd(sc, EMU_INTE, 4);
+			x |= EMU_INTE_INTERTIMERENB;
+			emu_wr(sc, EMU_INTE, x, 4);
 		}
 	} else {
 		sc->timer = 0;
-		x = emu_rd(sc, INTE, 4);
-		x &= ~INTE_INTERVALTIMERENB;
-		emu_wr(sc, INTE, x, 4);
+		x = emu_rd(sc, EMU_INTE, 4);
+		x &= ~EMU_INTE_INTERTIMERENB;
+		emu_wr(sc, EMU_INTE, x, 4);
 	}
 	return 0;
 }
@@ -373,7 +455,7 @@ emu_enatimer(struct sc_info *sc, int go)
 static void
 emu_enastop(struct sc_info *sc, char channel, int enable)
 {
-	int reg = (channel & 0x20) ? SOLEH : SOLEL;
+	int reg = (channel & 0x20) ? EMU_SOLEH : EMU_SOLEL;
 	channel &= 0x1f;
 	reg |= 1 << 24;
 	reg |= channel << 16;
@@ -568,49 +650,49 @@ emu_vwrite(struct sc_info *sc, struct emu_voice *v)
 		r = v->ismaster ? 0 : r;
 	}
 
-	emu_wrptr(sc, v->vnum, CPF, v->stereo ? CPF_STEREO_MASK : 0);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_CPF, v->stereo ? EMU_CHAN_CPF_STEREO_MASK : 0);
 	val = v->stereo ? 28 : 30;
 	val *= v->b16 ? 1 : 2;
 	start = sa + val;
 
 	if (sc->audigy) {
-		emu_wrptr(sc, v->vnum, A_FXRT1, v->fxrt1);
-		emu_wrptr(sc, v->vnum, A_FXRT2, v->fxrt2);
-		emu_wrptr(sc, v->vnum, A_SENDAMOUNTS, 0);
+		emu_wrptr(sc, v->vnum, EMU_A_CHAN_FXRT1, v->fxrt1);
+		emu_wrptr(sc, v->vnum, EMU_A_CHAN_FXRT2, v->fxrt2);
+		emu_wrptr(sc, v->vnum, EMU_A_CHAN_SENDAMOUNTS, 0);
 	}
 	else
-		emu_wrptr(sc, v->vnum, FXRT, v->fxrt1 << 16);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_FXRT, v->fxrt1 << 16);
 
-	emu_wrptr(sc, v->vnum, PTRX, (x << 8) | r);
-	emu_wrptr(sc, v->vnum, DSL, ea | (y << 24));
-	emu_wrptr(sc, v->vnum, PSST, sa | (l << 24));
-	emu_wrptr(sc, v->vnum, CCCA, start | (v->b16 ? 0 : CCCA_8BITSELECT));
+	emu_wrptr(sc, v->vnum, EMU_CHAN_PTRX, (x << 8) | r);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_DSL, ea | (y << 24));
+	emu_wrptr(sc, v->vnum, EMU_CHAN_PSST, sa | (l << 24));
+	emu_wrptr(sc, v->vnum, EMU_CHAN_CCCA, start | (v->b16 ? 0 : EMU_CHAN_CCCA_8BITSELECT));
 
-	emu_wrptr(sc, v->vnum, Z1, 0);
-	emu_wrptr(sc, v->vnum, Z2, 0);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_Z1, 0);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_Z2, 0);
 
 	silent_page = ((u_int32_t)(sc->mem.silent_page_addr) << 1)
-	    | MAP_PTI_MASK;
-	emu_wrptr(sc, v->vnum, MAPA, silent_page);
-	emu_wrptr(sc, v->vnum, MAPB, silent_page);
-
-	emu_wrptr(sc, v->vnum, CVCF, CVCF_CURRENTFILTER_MASK);
-	emu_wrptr(sc, v->vnum, VTFT, VTFT_FILTERTARGET_MASK);
-	emu_wrptr(sc, v->vnum, ATKHLDM, 0);
-	emu_wrptr(sc, v->vnum, DCYSUSM, DCYSUSM_DECAYTIME_MASK);
-	emu_wrptr(sc, v->vnum, LFOVAL1, 0x8000);
-	emu_wrptr(sc, v->vnum, LFOVAL2, 0x8000);
-	emu_wrptr(sc, v->vnum, FMMOD, 0);
-	emu_wrptr(sc, v->vnum, TREMFRQ, 0);
-	emu_wrptr(sc, v->vnum, FM2FRQ2, 0);
-	emu_wrptr(sc, v->vnum, ENVVAL, 0x8000);
-
-	emu_wrptr(sc, v->vnum, ATKHLDV,
-	    ATKHLDV_HOLDTIME_MASK | ATKHLDV_ATTACKTIME_MASK);
-	emu_wrptr(sc, v->vnum, ENVVOL, 0x8000);
-
-	emu_wrptr(sc, v->vnum, PEFE_FILTERAMOUNT, 0x7f);
-	emu_wrptr(sc, v->vnum, PEFE_PITCHAMOUNT, 0);
+	    | EMU_CHAN_MAP_PTI_MASK;
+	emu_wrptr(sc, v->vnum, EMU_CHAN_MAPA, silent_page);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_MAPB, silent_page);
+
+	emu_wrptr(sc, v->vnum, EMU_CHAN_CVCF, EMU_CHAN_CVCF_CURRFILTER_MASK);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_VTFT, EMU_CHAN_VTFT_FILTERTARGET_MASK);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_ATKHLDM, 0);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_DCYSUSM, EMU_CHAN_DCYSUSM_DECAYTIME_MASK);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_LFOVAL1, 0x8000);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_LFOVAL2, 0x8000);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_FMMOD, 0);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_TREMFRQ, 0);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_FM2FRQ2, 0);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_ENVVAL, 0x8000);
+
+	emu_wrptr(sc, v->vnum, EMU_CHAN_ATKHLDV,
+	    EMU_CHAN_ATKHLDV_HOLDTIME_MASK | EMU_CHAN_ATKHLDV_ATTACKTIME_MASK);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_ENVVOL, 0x8000);
+
+	emu_wrptr(sc, v->vnum, EMU_CHAN_PEFE_FILTERAMOUNT, 0x7f);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_PEFE_PITCHAMOUNT, 0);
 
 	if (v->slave != NULL)
 		emu_vwrite(sc, v->slave);
@@ -631,29 +713,29 @@ emu_vtrigger(struct sc_info *sc, struct emu_voice *v, int go)
 		sample = v->b16 ? 0x00000000 : 0x80808080;
 
 		for (i = 0; i < cs; i++)
-			emu_wrptr(sc, v->vnum, CD0 + i, sample);
-		emu_wrptr(sc, v->vnum, CCR_CACHEINVALIDSIZE, 0);
-		emu_wrptr(sc, v->vnum, CCR_READADDRESS, cra);
-		emu_wrptr(sc, v->vnum, CCR_CACHEINVALIDSIZE, ccis);
-
-		emu_wrptr(sc, v->vnum, IFATN, 0xff00);
-		emu_wrptr(sc, v->vnum, VTFT, 0xffffffff);
-		emu_wrptr(sc, v->vnum, CVCF, 0xffffffff);
-		emu_wrptr(sc, v->vnum, DCYSUSV, 0x00007f7f);
+			emu_wrptr(sc, v->vnum, EMU_CHAN_CD0 + i, sample);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_CCR_CACHEINVALIDSIZE, 0);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_CCR_READADDRESS, cra);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_CCR_CACHEINVALIDSIZE, ccis);
+
+		emu_wrptr(sc, v->vnum, EMU_CHAN_IFATN, 0xff00);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_VTFT, 0xffffffff);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_CVCF, 0xffffffff);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_DCYSUSV, 0x00007f7f);
 		emu_enastop(sc, v->vnum, 0);
 
 		pitch_target = emu_rate_to_linearpitch(v->speed);
 		initial_pitch = emu_rate_to_pitch(v->speed) >> 8;
-		emu_wrptr(sc, v->vnum, PTRX_PITCHTARGET, pitch_target);
-		emu_wrptr(sc, v->vnum, CPF_CURRENTPITCH, pitch_target);
-		emu_wrptr(sc, v->vnum, IP, initial_pitch);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_PTRX_PITCHTARGET, pitch_target);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_CPF_PITCH, pitch_target);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_IP, initial_pitch);
 	} else {
-		emu_wrptr(sc, v->vnum, PTRX_PITCHTARGET, 0);
-		emu_wrptr(sc, v->vnum, CPF_CURRENTPITCH, 0);
-		emu_wrptr(sc, v->vnum, IFATN, 0xffff);
-		emu_wrptr(sc, v->vnum, VTFT, 0x0000ffff);
-		emu_wrptr(sc, v->vnum, CVCF, 0x0000ffff);
-		emu_wrptr(sc, v->vnum, IP, 0);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_PTRX_PITCHTARGET, 0);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_CPF_PITCH, 0);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_IFATN, 0xffff);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_VTFT, 0x0000ffff);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_CVCF, 0x0000ffff);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_IP, 0);
 		emu_enastop(sc, v->vnum, 1);
 	}
 	if (v->slave != NULL)
@@ -666,7 +748,7 @@ emu_vpos(struct sc_info *sc, struct emu_voice *v)
 	int s, ptr;
 
 	s = (v->b16 ? 1 : 0) + (v->stereo ? 1 : 0);
-	ptr = (emu_rdptr(sc, v->vnum, CCCA_CURRADDR) - (v->start >> s)) << s;
+	ptr = (emu_rdptr(sc, v->vnum, EMU_CHAN_CCCA_CURRADDR) - (v->start >> s)) << s;
 	return ptr & ~0x0000001f;
 }
 
@@ -875,27 +957,27 @@ emurchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
 	ch->num = sc->rnum;
 	switch(sc->rnum) {
 	case 0:
-		ch->idxreg = sc->audigy ? A_ADCIDX : ADCIDX;
-		ch->basereg = ADCBA;
-		ch->sizereg = ADCBS;
-		ch->setupreg = ADCCR;
-		ch->irqmask = INTE_ADCBUFENABLE;
+		ch->idxreg = sc->audigy ? EMU_A_ADCIDX : EMU_ADCIDX;
+		ch->basereg = EMU_ADCBA;
+		ch->sizereg = EMU_ADCBS;
+		ch->setupreg = EMU_ADCCR;
+		ch->irqmask = EMU_INTE_ADCBUFENABLE;
 		break;
 
 	case 1:
-		ch->idxreg = FXIDX;
-		ch->basereg = FXBA;
-		ch->sizereg = FXBS;
-		ch->setupreg = FXWC;
-		ch->irqmask = INTE_EFXBUFENABLE;
+		ch->idxreg = EMU_FXIDX;
+		ch->basereg = EMU_FXBA;
+		ch->sizereg = EMU_FXBS;
+		ch->setupreg = EMU_FXWC;
+		ch->irqmask = EMU_INTE_EFXBUFENABLE;
 		break;
 
 	case 2:
-		ch->idxreg = MICIDX;
-		ch->basereg = MICBA;
-		ch->sizereg = MICBS;
+		ch->idxreg = EMU_MICIDX;
+		ch->basereg = EMU_MICBA;
+		ch->sizereg = EMU_MICBS;
 		ch->setupreg = 0;
-		ch->irqmask = INTE_MICBUFENABLE;
+		ch->irqmask = EMU_INTE_MICBUFENABLE;
 		break;
 	}
 	sc->rnum++;
@@ -967,27 +1049,27 @@ emurchan_trigger(kobj_t obj, void *data, int go)
 
 	switch(sc->bufsz) {
 	case 4096:
-		sz = ADCBS_BUFSIZE_4096;
+		sz = EMU_RECBS_BUFSIZE_4096;
 		break;
 
 	case 8192:
-		sz = ADCBS_BUFSIZE_8192;
+		sz = EMU_RECBS_BUFSIZE_8192;
 		break;
 
 	case 16384:
-		sz = ADCBS_BUFSIZE_16384;
+		sz = EMU_RECBS_BUFSIZE_16384;
 		break;
 
 	case 32768:
-		sz = ADCBS_BUFSIZE_32768;
+		sz = EMU_RECBS_BUFSIZE_32768;
 		break;
 
 	case 65536:
-		sz = ADCBS_BUFSIZE_65536;
+		sz = EMU_RECBS_BUFSIZE_65536;
 		break;
 
 	default:
-		sz = ADCBS_BUFSIZE_4096;
+		sz = EMU_RECBS_BUFSIZE_4096;
 	}
 
 	snd_mtxlock(sc->lock);
@@ -997,23 +1079,23 @@ emurchan_trigger(kobj_t obj, void *data, int go)
 		emu_wrptr(sc, 0, ch->sizereg, sz);
 		if (ch->num == 0) {
 			if (sc->audigy) {
-				val = A_ADCCR_LCHANENABLE;
+				val = EMU_ADCCR_LCHANENABLE;
 				if (AFMT_CHANNEL(ch->fmt) > 1)
-					val |= A_ADCCR_RCHANENABLE;
+					val |= EMU_ADCCR_RCHANENABLE;
 				val |= audigy_recval(ch->spd);
 			} else {
-				val = ADCCR_LCHANENABLE;
+				val = EMU_ADCCR_LCHANENABLE;
 				if (AFMT_CHANNEL(ch->fmt) > 1)
-					val |= ADCCR_RCHANENABLE;
+					val |= EMU_ADCCR_RCHANENABLE;
 				val |= emu_recval(ch->spd);
 			}
 
 			emu_wrptr(sc, 0, ch->setupreg, 0);
 			emu_wrptr(sc, 0, ch->setupreg, val);
 		}
-		val = emu_rd(sc, INTE, 4);
+		val = emu_rd(sc, EMU_INTE, 4);
 		val |= ch->irqmask;
-		emu_wr(sc, INTE, val, 4);
+		emu_wr(sc, EMU_INTE, val, 4);
 		break;
 
 	case PCMTRIG_STOP:
@@ -1022,9 +1104,9 @@ emurchan_trigger(kobj_t obj, void *data, int go)
 		emu_wrptr(sc, 0, ch->sizereg, 0);
 		if (ch->setupreg)
 			emu_wrptr(sc, 0, ch->setupreg, 0);
-		val = emu_rd(sc, INTE, 4);
+		val = emu_rd(sc, EMU_INTE, 4);
 		val &= ~ch->irqmask;
-		emu_wr(sc, INTE, val, 4);
+		emu_wr(sc, EMU_INTE, val, 4);
 		break;
 
 	case PCMTRIG_EMLDMAWR:
@@ -1122,9 +1204,9 @@ emu_midiattach(struct sc_info *sc)
 {
 	int i;
 
-	i = emu_rd(sc, INTE, 4);
-	i |= INTE_MIDIRXENABLE;
-	emu_wr(sc, INTE, i, 4);
+	i = emu_rd(sc, EMU_INTE, 4);
+	i |= EMU_INTE_MIDIRXENABLE;
+	emu_wr(sc, EMU_INTE, i, 4);
 
 	sc->mpu = mpu401_init(&emu_mpu_class, sc, emu_intr2, &sc->mpu_intr);
 }
@@ -1139,52 +1221,52 @@ emu_intr(void *data)
 
 	snd_mtxlock(sc->lock);
 	while (1) {
-		stat = emu_rd(sc, IPR, 4);
+		stat = emu_rd(sc, EMU_IPR, 4);
 		if (stat == 0)
 			break;
 		ack = 0;
 
 		/* process irq */
-		if (stat & IPR_INTERVALTIMER)
-			ack |= IPR_INTERVALTIMER;
+		if (stat & EMU_IPR_INTERVALTIMER)
+			ack |= EMU_IPR_INTERVALTIMER;
 
-		if (stat & (IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL))
-			ack |= stat & (IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL);
+		if (stat & (EMU_IPR_ADCBUFFULL | EMU_IPR_ADCBUFHALFFULL))
+			ack |= stat & (EMU_IPR_ADCBUFFULL | EMU_IPR_ADCBUFHALFFULL);
 
-		if (stat & (IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL))
-			ack |= stat & (IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL);
+		if (stat & (EMU_IPR_EFXBUFFULL | EMU_IPR_EFXBUFHALFFULL))
+			ack |= stat & (EMU_IPR_EFXBUFFULL | EMU_IPR_EFXBUFHALFFULL);
 
-		if (stat & (IPR_MICBUFFULL | IPR_MICBUFHALFFULL))
-			ack |= stat & (IPR_MICBUFFULL | IPR_MICBUFHALFFULL);
+		if (stat & (EMU_IPR_MICBUFFULL | EMU_IPR_MICBUFHALFFULL))
+			ack |= stat & (EMU_IPR_MICBUFFULL | EMU_IPR_MICBUFHALFFULL);
 
-		if (stat & IPR_PCIERROR) {
-			ack |= IPR_PCIERROR;
+		if (stat & EMU_PCIERROR) {
+			ack |= EMU_PCIERROR;
 			device_printf(sc->dev, "pci error\n");
 			/* we still get an nmi with ecc ram even if we ack this */
 		}
-		if (stat & IPR_SAMPLERATETRACKER) {
-			ack |= IPR_SAMPLERATETRACKER;
+		if (stat & EMU_IPR_RATETRCHANGE) {
+			ack |= EMU_IPR_RATETRCHANGE;
 #ifdef EMUDEBUG
 			device_printf(sc->dev,
 			    "sample rate tracker lock status change\n");
 #endif
 		}
 
-	    if (stat & IPR_MIDIRECVBUFEMPTY)
+	    if (stat & EMU_IPR_MIDIRECVBUFE)
 		if (sc->mpu_intr) {
 		    (sc->mpu_intr)(sc->mpu);
-		    ack |= IPR_MIDIRECVBUFEMPTY | IPR_MIDITRANSBUFEMPTY;
+		    ack |= EMU_IPR_MIDIRECVBUFE | EMU_IPR_MIDITRANSBUFE;
  		}
 		if (stat & ~ack)
 			device_printf(sc->dev, "dodgy irq: %x (harmless)\n",
 			    stat & ~ack);
 
-		emu_wr(sc, IPR, stat, 4);
+		emu_wr(sc, EMU_IPR, stat, 4);
 
 		if (ack) {
 			snd_mtxunlock(sc->lock);
 
-			if (ack & IPR_INTERVALTIMER) {
+			if (ack & EMU_IPR_INTERVALTIMER) {
 				x = 0;
 				for (i = 0; i < sc->nchans; i++) {
 					if (sc->pch[i].run) {
@@ -1197,15 +1279,15 @@ emu_intr(void *data)
 			}
 
 
-			if (ack & (IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL)) {
+			if (ack & (EMU_IPR_ADCBUFFULL | EMU_IPR_ADCBUFHALFFULL)) {
 				if (sc->rch[0].channel)
 					chn_intr(sc->rch[0].channel);
 			}
-			if (ack & (IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL)) {
+			if (ack & (EMU_IPR_EFXBUFFULL | EMU_IPR_EFXBUFHALFFULL)) {
 				if (sc->rch[1].channel)
 					chn_intr(sc->rch[1].channel);
 			}
-			if (ack & (IPR_MICBUFFULL | IPR_MICBUFHALFFULL)) {
+			if (ack & (EMU_IPR_MICBUFFULL | EMU_IPR_MICBUFHALFFULL)) {
 				if (sc->rch[2].channel)
 					chn_intr(sc->rch[2].channel);
 			}
@@ -1378,12 +1460,12 @@ audigy_initefx(struct sc_info *sc)
 		audigy_addefxop(sc, 0x0f, 0x0c0, 0x0c0, 0x0cf, 0x0c0, &pc);
 
 	for (i = 0; i < 512; i++)
-		emu_wrptr(sc, 0, A_FXGPREGBASE + i, 0x0);
+		emu_wrptr(sc, 0, EMU_A_FXGPREGBASE + i, 0x0);
 
 	pc = 16;
 
 	/* stop fx processor */
-	emu_wrptr(sc, 0, A_DBG, A_DBG_SINGLE_STEP);
+	emu_wrptr(sc, 0, EMU_A_DBG, EMU_A_DBG_SINGLE_STEP);
 
 	/* Audigy 2 (EMU10K2) DSP Registers:
 	   FX Bus
@@ -1518,7 +1600,7 @@ audigy_initefx(struct sc_info *sc)
 			A_C_00000000, A_EXTIN(A_EXTIN_AC97_R), &pc);
 
 	/* resume normal operations */
-	emu_wrptr(sc, 0, A_DBG, 0);
+	emu_wrptr(sc, 0, EMU_A_DBG, 0);
 }
 
 static void
@@ -1534,7 +1616,7 @@ emu_initefx(struct sc_info *sc)
 	}
 
 	for (i = 0; i < 256; i++)
-		emu_wrptr(sc, 0, FXGPREGBASE + i, 0);
+		emu_wrptr(sc, 0, EMU_FXGPREGBASE + i, 0);
 
 	/* FX-8010 DSP Registers:
 	   FX Bus
@@ -1654,7 +1736,7 @@ emu_initefx(struct sc_info *sc)
 			C_00000000, EXTIN(EXTIN_AC97_R), &pc);
 
 	/* resume normal operations */
-	emu_wrptr(sc, 0, DBG, 0);
+	emu_wrptr(sc, 0, EMU_DBG, 0);
 }
 
 /* Probe and attach the card */
@@ -1665,69 +1747,69 @@ emu_init(struct sc_info *sc)
 
 	if (sc->audigy) {
 		/* enable additional AC97 slots */
-		emu_wrptr(sc, 0, AC97SLOT, AC97SLOT_CNTR | AC97SLOT_LFE);
+		emu_wrptr(sc, 0, EMU_AC97SLOT, EMU_AC97SLOT_CENTER | EMU_AC97SLOT_LFE);
 	}
 
 	/* disable audio and lock cache */
-	emu_wr(sc, HCFG,
-	    HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE,
+	emu_wr(sc, EMU_HCFG,
+	    EMU_HCFG_LOCKSOUNDCACHE | EMU_HCFG_LOCKTANKCACHE_MASK | EMU_HCFG_MUTEBUTTONENABLE,
 	    4);
 
 	/* reset recording buffers */
-	emu_wrptr(sc, 0, MICBS, ADCBS_BUFSIZE_NONE);
-	emu_wrptr(sc, 0, MICBA, 0);
-	emu_wrptr(sc, 0, FXBS, ADCBS_BUFSIZE_NONE);
-	emu_wrptr(sc, 0, FXBA, 0);
-	emu_wrptr(sc, 0, ADCBS, ADCBS_BUFSIZE_NONE);
-	emu_wrptr(sc, 0, ADCBA, 0);
+	emu_wrptr(sc, 0, EMU_MICBS, EMU_RECBS_BUFSIZE_NONE);
+	emu_wrptr(sc, 0, EMU_MICBA, 0);
+	emu_wrptr(sc, 0, EMU_FXBS, EMU_RECBS_BUFSIZE_NONE);
+	emu_wrptr(sc, 0, EMU_FXBA, 0);
+	emu_wrptr(sc, 0, EMU_ADCBS, EMU_RECBS_BUFSIZE_NONE);
+	emu_wrptr(sc, 0, EMU_ADCBA, 0);
 
 	/* disable channel interrupt */
-	emu_wr(sc, INTE,
-	    INTE_INTERVALTIMERENB | INTE_SAMPLERATETRACKER | INTE_PCIERRORENABLE,
+	emu_wr(sc, EMU_INTE,
+	    EMU_INTE_INTERTIMERENB | EMU_INTE_SAMPLERATER | EMU_INTE_PCIERRENABLE,
 	    4);
-	emu_wrptr(sc, 0, CLIEL, 0);
-	emu_wrptr(sc, 0, CLIEH, 0);
-	emu_wrptr(sc, 0, SOLEL, 0);
-	emu_wrptr(sc, 0, SOLEH, 0);
+	emu_wrptr(sc, 0, EMU_CLIEL, 0);
+	emu_wrptr(sc, 0, EMU_CLIEH, 0);
+	emu_wrptr(sc, 0, EMU_SOLEL, 0);
+	emu_wrptr(sc, 0, EMU_SOLEH, 0);
 
 	/* wonder what these do... */
 	if (sc->audigy) {
-		emu_wrptr(sc, 0, SPBYPASS, 0xf00);
-		emu_wrptr(sc, 0, AC97SLOT, 0x3);
+		emu_wrptr(sc, 0, EMU_SPBYPASS, 0xf00);
+		emu_wrptr(sc, 0, EMU_AC97SLOT, 0x3);
 	}
 
 	/* init envelope engine */
 	for (ch = 0; ch < NUM_G; ch++) {
-		emu_wrptr(sc, ch, DCYSUSV, ENV_OFF);
-		emu_wrptr(sc, ch, IP, 0);
-		emu_wrptr(sc, ch, VTFT, 0xffff);
-		emu_wrptr(sc, ch, CVCF, 0xffff);
-		emu_wrptr(sc, ch, PTRX, 0);
-		emu_wrptr(sc, ch, CPF, 0);
-		emu_wrptr(sc, ch, CCR, 0);
-
-		emu_wrptr(sc, ch, PSST, 0);
-		emu_wrptr(sc, ch, DSL, 0x10);
-		emu_wrptr(sc, ch, CCCA, 0);
-		emu_wrptr(sc, ch, Z1, 0);
-		emu_wrptr(sc, ch, Z2, 0);
-		emu_wrptr(sc, ch, FXRT, 0xd01c0000);
-
-		emu_wrptr(sc, ch, ATKHLDM, 0);
-		emu_wrptr(sc, ch, DCYSUSM, 0);
-		emu_wrptr(sc, ch, IFATN, 0xffff);
-		emu_wrptr(sc, ch, PEFE, 0);
-		emu_wrptr(sc, ch, FMMOD, 0);
-		emu_wrptr(sc, ch, TREMFRQ, 24);	/* 1 Hz */
-		emu_wrptr(sc, ch, FM2FRQ2, 24);	/* 1 Hz */
-		emu_wrptr(sc, ch, TEMPENV, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_DCYSUSV, ENV_OFF);
+		emu_wrptr(sc, ch, EMU_CHAN_IP, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_VTFT, 0xffff);
+		emu_wrptr(sc, ch, EMU_CHAN_CVCF, 0xffff);
+		emu_wrptr(sc, ch, EMU_CHAN_PTRX, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_CPF, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_CCR, 0);
+
+		emu_wrptr(sc, ch, EMU_CHAN_PSST, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_DSL, 0x10);
+		emu_wrptr(sc, ch, EMU_CHAN_CCCA, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_Z1, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_Z2, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_FXRT, 0xd01c0000);
+
+		emu_wrptr(sc, ch, EMU_CHAN_ATKHLDM, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_DCYSUSM, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_IFATN, 0xffff);
+		emu_wrptr(sc, ch, EMU_CHAN_PEFE, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_FMMOD, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_TREMFRQ, 24);	/* 1 Hz */
+		emu_wrptr(sc, ch, EMU_CHAN_FM2FRQ2, 24);	/* 1 Hz */
+		emu_wrptr(sc, ch, EMU_CHAN_TEMPENV, 0);
 
 		/*** these are last so OFF prevents writing ***/
-		emu_wrptr(sc, ch, LFOVAL2, 0);
-		emu_wrptr(sc, ch, LFOVAL1, 0);
-		emu_wrptr(sc, ch, ATKHLDV, 0);
-		emu_wrptr(sc, ch, ENVVOL, 0);
-		emu_wrptr(sc, ch, ENVVAL, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_LFOVAL2, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_LFOVAL1, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_ATKHLDV, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_ENVVOL, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_ENVVAL, 0);
 
 		if (sc->audigy) {
 			/* audigy cards need this to initialize correctly */
@@ -1736,9 +1818,9 @@ emu_init(struct sc_info *sc)
 			emu_wrptr(sc, ch, 0x4e, 0);
 			emu_wrptr(sc, ch, 0x4f, 0);
 			/* set default routing */
-			emu_wrptr(sc, ch, A_FXRT1, 0x03020100);
-			emu_wrptr(sc, ch, A_FXRT2, 0x3f3f3f3f);
-			emu_wrptr(sc, ch, A_SENDAMOUNTS, 0);
+			emu_wrptr(sc, ch, EMU_A_CHAN_FXRT1, 0x03020100);
+			emu_wrptr(sc, ch, EMU_A_CHAN_FXRT2, 0x3f3f3f3f);
+			emu_wrptr(sc, ch, EMU_A_CHAN_SENDAMOUNTS, 0);
 		}
 
 		sc->voice[ch].vnum = ch;
@@ -1769,13 +1851,13 @@ emu_init(struct sc_info *sc)
 	 *  AN                = 0     (Audio data)
 	 *  P                 = 0     (Consumer)
 	 */
-	spcs = SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
-	    SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
-	    SPCS_GENERATIONSTATUS | 0x00001200 | 0x00000000 |
-	    SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT;
-	emu_wrptr(sc, 0, SPCS0, spcs);
-	emu_wrptr(sc, 0, SPCS1, spcs);
-	emu_wrptr(sc, 0, SPCS2, spcs);
+	spcs = EMU_SPCS_CLKACCY_1000PPM | EMU_SPCS_SAMPLERATE_48 |
+	    EMU_SPCS_CHANNELNUM_LEFT | EMU_SPCS_SOURCENUM_UNSPEC |
+	    EMU_SPCS_GENERATIONSTATUS | 0x00001200 | 0x00000000 |
+	    EMU_SPCS_EMPHASIS_NONE | EMU_SPCS_COPYRIGHT;
+	emu_wrptr(sc, 0, EMU_SPCS0, spcs);
+	emu_wrptr(sc, 0, EMU_SPCS1, spcs);
+	emu_wrptr(sc, 0, EMU_SPCS2, spcs);
 
 	if (!sc->audigy)
 		emu_initefx(sc);
@@ -1786,8 +1868,8 @@ emu_init(struct sc_info *sc)
 		u_int32_t tmp;
 
 		/* Setup SRCMulti_I2S SamplingRate */
-		tmp = emu_rdptr(sc, 0, A_SPDIF_SAMPLERATE) & 0xfffff1ff;
-		emu_wrptr(sc, 0, A_SPDIF_SAMPLERATE, tmp | 0x400);
+		tmp = emu_rdptr(sc, 0, EMU_A_SPDIF_SAMPLERATE) & 0xfffff1ff;
+		emu_wrptr(sc, 0, EMU_A_SPDIF_SAMPLERATE, tmp | 0x400);
 
 		/* Setup SRCSel (Enable SPDIF, I2S SRCMulti) */
 		emu_wr(sc, 0x20, 0x00600000, 4);
@@ -1816,13 +1898,13 @@ emu_init(struct sc_info *sc)
 	for (i = 0; i < EMUMAXPAGES; i++)
 		sc->mem.ptb_pages[i] = tmp | i;
 
-	emu_wrptr(sc, 0, PTB, (sc->mem.ptb_pages_addr));
-	emu_wrptr(sc, 0, TCB, 0);	/* taken from original driver */
-	emu_wrptr(sc, 0, TCBS, 0);	/* taken from original driver */
+	emu_wrptr(sc, 0, EMU_PTB, (sc->mem.ptb_pages_addr));
+	emu_wrptr(sc, 0, EMU_TCB, 0);	/* taken from original driver */
+	emu_wrptr(sc, 0, EMU_TCBS, 0);	/* taken from original driver */
 
 	for (ch = 0; ch < NUM_G; ch++) {
-		emu_wrptr(sc, ch, MAPA, tmp | MAP_PTI_MASK);
-		emu_wrptr(sc, ch, MAPB, tmp | MAP_PTI_MASK);
+		emu_wrptr(sc, ch, EMU_CHAN_MAPA, tmp | EMU_CHAN_MAP_PTI_MASK);
+		emu_wrptr(sc, ch, EMU_CHAN_MAPB, tmp | EMU_CHAN_MAP_PTI_MASK);
 	}
 
 	/* emu_memalloc(sc, EMUPAGESIZE); */
@@ -1850,19 +1932,19 @@ emu_init(struct sc_info *sc)
 	 */
 
 	if (sc->audigy) {
-		tmp = HCFG_AUTOMUTE | HCFG_JOYENABLE;
+		tmp = EMU_HCFG_AUTOMUTE | EMU_HCFG_JOYENABLE;
 		if (sc->audigy2)	/* Audigy 2 */
-			tmp = HCFG_AUDIOENABLE | HCFG_AC3ENABLE_CDSPDIF |
-			    HCFG_AC3ENABLE_GPSPDIF;
-		emu_wr(sc, HCFG, tmp, 4);
+			tmp = EMU_HCFG_AUDIOENABLE | EMU_HCFG_AC3ENABLE_CDSPDIF |
+			    EMU_HCFG_AC3ENABLE_GPSPDIF;
+		emu_wr(sc, EMU_HCFG, tmp, 4);
 
 		audigy_initefx(sc);
 
 		/* from ALSA initialization code: */
 
 		/* enable audio and disable both audio/digital outputs */
-		emu_wr(sc, HCFG, emu_rd(sc, HCFG, 4) | HCFG_AUDIOENABLE, 4);
-		emu_wr(sc, A_IOCFG, emu_rd(sc, A_IOCFG, 4) & ~A_IOCFG_GPOUT_AD,
+		emu_wr(sc, EMU_HCFG, emu_rd(sc, EMU_HCFG, 4) | EMU_HCFG_AUDIOENABLE, 4);
+		emu_wr(sc, EMU_A_IOCFG, emu_rd(sc, EMU_A_IOCFG, 4) & ~EMU_A_IOCFG_GPOUT_AD,
 		    4);
 		if (sc->audigy2) {	/* Audigy 2 */
 			/* Unmute Analog.
@@ -1870,27 +1952,27 @@ emu_init(struct sc_info *sc)
 			 * init Alice3 I2SOut beyond 48kHz.
 			 * So, sequence is important.
 			 */
-			emu_wr(sc, A_IOCFG,
-			    emu_rd(sc, A_IOCFG, 4) | A_IOCFG_GPOUT_A, 4);
+			emu_wr(sc, EMU_A_IOCFG,
+			    emu_rd(sc, EMU_A_IOCFG, 4) | EMU_A_IOCFG_GPOUT_A, 4);
 		}
 	} else {
 		/* EMU10K1 initialization code */
-		tmp = HCFG_AUDIOENABLE | HCFG_LOCKTANKCACHE_MASK 
-		    | HCFG_AUTOMUTE;
+		tmp = EMU_HCFG_AUDIOENABLE | EMU_HCFG_LOCKTANKCACHE_MASK 
+		    | EMU_HCFG_AUTOMUTE;
 		if (sc->rev >= 6)
-			tmp |= HCFG_JOYENABLE;
+			tmp |= EMU_HCFG_JOYENABLE;
 
-		emu_wr(sc, HCFG, tmp, 4);
+		emu_wr(sc, EMU_HCFG, tmp, 4);
 
 		/* TOSLink detection */
 		sc->tos_link = 0;
-		tmp = emu_rd(sc, HCFG, 4);
-		if (tmp & (HCFG_GPINPUT0 | HCFG_GPINPUT1)) {
-			emu_wr(sc, HCFG, tmp | HCFG_GPOUT1, 4);
+		tmp = emu_rd(sc, EMU_HCFG, 4);
+		if (tmp & (EMU_HCFG_GPINPUT0 | EMU_HCFG_GPINPUT1)) {
+			emu_wr(sc, EMU_HCFG, tmp | EMU_HCFG_GPOUT1, 4);
 			DELAY(50);
-			if (tmp != (emu_rd(sc, HCFG, 4) & ~HCFG_GPOUT1)) {
+			if (tmp != (emu_rd(sc, EMU_HCFG, 4) & ~EMU_HCFG_GPOUT1)) {
 				sc->tos_link = 1;
-				emu_wr(sc, HCFG, tmp, 4);
+				emu_wr(sc, EMU_HCFG, tmp, 4);
 			}
 		}
 	}
@@ -1903,42 +1985,42 @@ emu_uninit(struct sc_info *sc)
 {
 	u_int32_t ch;
 
-	emu_wr(sc, INTE, 0, 4);
+	emu_wr(sc, EMU_INTE, 0, 4);
 	for (ch = 0; ch < NUM_G; ch++)
-		emu_wrptr(sc, ch, DCYSUSV, ENV_OFF);
+		emu_wrptr(sc, ch, EMU_CHAN_DCYSUSV, ENV_OFF);
 	for (ch = 0; ch < NUM_G; ch++) {
-		emu_wrptr(sc, ch, VTFT, 0);
-		emu_wrptr(sc, ch, CVCF, 0);
-		emu_wrptr(sc, ch, PTRX, 0);
-		emu_wrptr(sc, ch, CPF, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_VTFT, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_CVCF, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_PTRX, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_CPF, 0);
 	}
 
 	if (sc->audigy) {	/* stop fx processor */
-		emu_wrptr(sc, 0, A_DBG, A_DBG_SINGLE_STEP);
+		emu_wrptr(sc, 0, EMU_A_DBG, EMU_A_DBG_SINGLE_STEP);
 	}
 
 	/* disable audio and lock cache */
-	emu_wr(sc, HCFG,
-	    HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE,
+	emu_wr(sc, EMU_HCFG,
+	    EMU_HCFG_LOCKSOUNDCACHE | EMU_HCFG_LOCKTANKCACHE_MASK | EMU_HCFG_MUTEBUTTONENABLE,
 	    4);
 
-	emu_wrptr(sc, 0, PTB, 0);
+	emu_wrptr(sc, 0, EMU_PTB, 0);
 	/* reset recording buffers */
-	emu_wrptr(sc, 0, MICBS, ADCBS_BUFSIZE_NONE);
-	emu_wrptr(sc, 0, MICBA, 0);
-	emu_wrptr(sc, 0, FXBS, ADCBS_BUFSIZE_NONE);
-	emu_wrptr(sc, 0, FXBA, 0);
-	emu_wrptr(sc, 0, FXWC, 0);
-	emu_wrptr(sc, 0, ADCBS, ADCBS_BUFSIZE_NONE);
-	emu_wrptr(sc, 0, ADCBA, 0);
-	emu_wrptr(sc, 0, TCB, 0);
-	emu_wrptr(sc, 0, TCBS, 0);
+	emu_wrptr(sc, 0, EMU_MICBS, EMU_RECBS_BUFSIZE_NONE);
+	emu_wrptr(sc, 0, EMU_MICBA, 0);
+	emu_wrptr(sc, 0, EMU_FXBS, EMU_RECBS_BUFSIZE_NONE);
+	emu_wrptr(sc, 0, EMU_FXBA, 0);
+	emu_wrptr(sc, 0, EMU_FXWC, 0);
+	emu_wrptr(sc, 0, EMU_ADCBS, EMU_RECBS_BUFSIZE_NONE);
+	emu_wrptr(sc, 0, EMU_ADCBA, 0);
+	emu_wrptr(sc, 0, EMU_TCB, 0);
+	emu_wrptr(sc, 0, EMU_TCBS, 0);
 
 	/* disable channel interrupt */
-	emu_wrptr(sc, 0, CLIEL, 0);
-	emu_wrptr(sc, 0, CLIEH, 0);
-	emu_wrptr(sc, 0, SOLEL, 0);
-	emu_wrptr(sc, 0, SOLEH, 0);
+	emu_wrptr(sc, 0, EMU_CLIEL, 0);
+	emu_wrptr(sc, 0, EMU_CLIEH, 0);
+	emu_wrptr(sc, 0, EMU_SOLEL, 0);
+	emu_wrptr(sc, 0, EMU_SOLEH, 0);
 
 	/* init envelope engine */
 	if (!SLIST_EMPTY(&sc->mem.blocks))
@@ -1997,7 +2079,7 @@ emu_pci_attach(device_t dev)
 	sc->audigy = sc->type == EMU10K2_PCI_ID || sc->type == EMU10K3_PCI_ID;
 	sc->audigy2 = (sc->audigy && sc->rev == 0x04);
 	sc->nchans = sc->audigy ? 8 : 4;
-	sc->addrmask = sc->audigy ? A_PTR_ADDRESS_MASK : PTR_ADDRESS_MASK;
+	sc->addrmask = sc->audigy ? EMU_A_PTR_ADDR_MASK : EMU_PTR_ADDR_MASK;
 
 	data = pci_read_config(dev, PCIR_COMMAND, 2);
 	data |= (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN);
diff --git a/sys/dev/sound/pci/emuxkireg.h b/sys/dev/sound/pci/emuxkireg.h
new file mode 100644
index 0000000..c743c8e
--- /dev/null
+++ b/sys/dev/sound/pci/emuxkireg.h
@@ -0,0 +1,689 @@
+/* $FreeBSD$ */
+/*	$NetBSD: emuxkireg.h,v 1.8 2008/04/28 20:23:54 martin Exp $	*/
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Yannick Montulet.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _DEV_PCI_EMUXKIREG_H_
+#define _DEV_PCI_EMUXKIREG_H_
+
+/*
+ * Register values for Creative EMU10000. The register values have been
+ * taken from GPLed SBLive! header file published by Creative. The comments
+ * have been stripped to avoid GPL pollution in kernel. The Creative version
+ * including comments is available in Linux 2.4.* kernel as file
+ *	drivers/sound/emu10k1/8010.h
+ */
+
+/*
+ * Audigy specific registers contain an '_A_'
+ * Audigy2 specific registers contain an '_A2_'
+ */
+
+#define	EMU_MKSUBREG(sz, idx, reg)	(((sz) << 24) | ((idx) << 16) | (reg))
+
+#define EMU_PTR	0x00
+#define  EMU_PTR_CHNO_MASK	0x0000003f
+#define  EMU_PTR_ADDR_MASK	0x07ff0000
+#define  EMU_A_PTR_ADDR_MASK	0x0fff0000
+
+#define EMU_DATA	0x04
+
+#define EMU_IPR	0x08
+#define  EMU_IPR_RATETRCHANGE	0x01000000
+#define  EMU_IPR_FXDSP		0x00800000
+#define  EMU_IPR_FORCEINT	0x00400000
+#define  EMU_PCIERROR		0x00200000
+#define  EMU_IPR_VOLINCR	0x00100000
+#define  EMU_IPR_VOLDECR	0x00080000
+#define  EMU_IPR_MUTE		0x00040000
+#define  EMU_IPR_MICBUFFULL	0x00020000
+#define  EMU_IPR_MICBUFHALFFULL	0x00010000
+#define  EMU_IPR_ADCBUFFULL	0x00008000
+#define  EMU_IPR_ADCBUFHALFFULL	0x00004000
+#define  EMU_IPR_EFXBUFFULL	0x00002000
+#define  EMU_IPR_EFXBUFHALFFULL	0x00001000
+#define  EMU_IPR_GPSPDIFSTCHANGE 0x00000800
+#define  EMU_IPR_CDROMSTCHANGE	0x00000400
+#define  EMU_IPR_INTERVALTIMER	0x00000200
+#define  EMU_IPR_MIDITRANSBUFE	0x00000100
+#define  EMU_IPR_MIDIRECVBUFE	0x00000080
+#define  EMU_IPR_A_MIDITRANSBUFE2 0x10000000
+#define  EMU_IPR_A_MIDIRECBUFE2	0x08000000
+#define  EMU_IPR_CHANNELLOOP	0x00000040
+#define  EMU_IPR_CHNOMASK	0x0000003f
+
+#define EMU_INTE	0x0c
+
+#define  EMU_INTE_VSB_MASK	0xc0000000
+#define   EMU_INTE_VSB_220	0x00000000
+#define   EMU_INTE_VSB_240	0x40000000
+#define   EMU_INTE_VSB_260	0x80000000
+#define   EMU_INTE_VSB_280	0xc0000000
+
+#define  EMU_INTE_VMPU_MASK	0x30000000
+#define   EMU_INTE_VMPU_300	0x00000000
+#define   EMU_INTE_VMPU_310	0x10000000
+#define   EMU_INTE_VMPU_320	0x20000000
+#define   EMU_INTE_VMPU_330	0x30000000
+#define  EMU_INTE_MDMAENABLE	0x08000000
+#define  EMU_INTE_SDMAENABLE	0x04000000
+#define  EMU_INTE_MPICENABLE	0x02000000
+#define  EMU_INTE_SPICENABLE	0x01000000
+#define  EMU_INTE_VSBENABLE	0x00800000
+#define  EMU_INTE_ADLIBENABLE	0x00400000
+#define  EMU_INTE_MPUENABLE	0x00200000
+#define  EMU_INTE_FORCEINT	0x00100000
+#define  EMU_INTE_MRHANDENABLE	0x00080000
+#define  EMU_INTE_SAMPLERATER	0x00002000
+#define  EMU_INTE_FXDSPENABLE	0x00001000
+#define  EMU_INTE_PCIERRENABLE	0x00000800
+#define  EMU_INTE_VOLINCRENABLE	0x00000400
+#define  EMU_INTE_VOLDECRENABLE	0x00000200
+#define  EMU_INTE_MUTEENABLE	0x00000100
+#define  EMU_INTE_MICBUFENABLE	0x00000080
+#define  EMU_INTE_ADCBUFENABLE	0x00000040
+#define  EMU_INTE_EFXBUFENABLE	0x00000020
+#define  EMU_INTE_GPSPDIFENABLE	0x00000010
+#define  EMU_INTE_CDSPDIFENABLE	0x00000008
+#define  EMU_INTE_INTERTIMERENB	0x00000004
+#define  EMU_INTE_MIDITXENABLE	0x00000002
+#define  EMU_INTE_MIDIRXENABLE	0x00000001
+#define  EMU_INTE_A_MIDITXENABLE2 0x00020000
+#define  EMU_INTE_A_MIDIRXENABLE2 0x00010000
+
+#define EMU_WC	0x10
+#define  EMU_WC_SAMPLECOUNTER_MASK	0x03FFFFC0
+#define  EMU_WC_SAMPLECOUNTER		EMU_MKSUBREG(20, 6, EMU_WC)
+#define  EMU_WC_CURRENTCHANNEL		0x0000003F
+
+#define EMU_HCFG	0x14
+#define  EMU_HCFG_LEGACYFUNC_MASK	0xe0000000
+#define  EMU_HCFG_LEGACYFUNC_MPU	0x00000000
+#define  EMU_HCFG_LEGACYFUNC_SB		0x40000000
+#define  EMU_HCFG_LEGACYFUNC_AD		0x60000000
+#define  EMU_HCFG_LEGACYFUNC_MPIC	0x80000000
+#define  EMU_HCFG_LEGACYFUNC_MDMA	0xa0000000
+#define  EMU_HCFG_LEGACYFUNC_SPCI	0xc0000000
+#define  EMU_HCFG_LEGACYFUNC_SDMA	0xe0000000
+#define  EMU_HCFG_IOCAPTUREADDR		0x1f000000
+#define  EMU_HCFG_LEGACYWRITE		0x00800000
+#define  EMU_HCFG_LEGACYWORD		0x00400000
+#define  EMU_HCFG_LEGACYINT		0x00200000
+
+#define  EMU_HCFG_CODECFMT_MASK		0x00070000
+#define  EMU_HCFG_CODECFMT_AC97		0x00000000
+#define  EMU_HCFG_CODECFMT_I2S		0x00010000
+#define  EMU_HCFG_GPINPUT0		0x00004000
+#define  EMU_HCFG_GPINPUT1		0x00002000
+#define  EMU_HCFG_GPOUTPUT_MASK		0x00001c00
+#define  EMU_HCFG_JOYENABLE		0x00000200
+#define  EMU_HCFG_PHASETRACKENABLE	0x00000100
+#define  EMU_HCFG_AC3ENABLE_MASK	0x000000e0
+#define  EMU_HCFG_AC3ENABLE_ZVIDEO	0x00000080
+#define  EMU_HCFG_AC3ENABLE_CDSPDIF	0x00000040
+#define  EMU_HCFG_AC3ENABLE_GPSPDIF	0x00000020
+#define  EMU_HCFG_AUTOMUTE		0x00000010
+#define  EMU_HCFG_LOCKSOUNDCACHE	0x00000008
+#define  EMU_HCFG_LOCKTANKCACHE_MASK	0x00000004
+#define  EMU_HCFG_LOCKTANKCACHE		EMU_MKSUBREG(1, 2, EMU_HCFG)
+#define  EMU_HCFG_MUTEBUTTONENABLE	0x00000002
+#define  EMU_HCFG_AUDIOENABLE		0x00000001
+
+#define EMU_MUDATA	0x18
+#define EMU_MUCMD	0x19
+#define  EMU_MUCMD_RESET		0xff
+#define  EMU_MUCMD_ENTERUARTMODE	0x3f
+
+#define EMU_MUSTAT	EMU_MUCMD
+#define  EMU_MUSTAT_IRDYN		0x80
+#define  EMU_MUSTAT_ORDYN		0x40
+
+#define EMU_A_IOCFG			0x18
+#define EMU_A_GPINPUT_MASK		0xff00
+#define EMU_A_GPOUTPUT_MASK		0x00ff
+#define EMU_A_IOCFG_GPOUT0		0x0040
+#define EMU_A_IOCFG_GPOUT1		0x0004
+
+#define EMU_TIMER	0x1a
+#define  EMU_TIMER_RATE_MASK	0x000003ff
+#define  EMU_TIMER_RATE		EMU_MKSUBREG(10, 0, EMU_TIMER)
+
+#define EMU_AC97DATA	0x1c
+#define EMU_AC97ADDR	0x1e
+#define  EMU_AC97ADDR_RDY	0x80
+#define  EMU_AC97ADDR_ADDR	0x7f
+
+#define EMU_A2_PTR		0x20
+#define EMU_A2_DATA		0x24
+
+#define EMU_A2_SRCSEL			0x600000
+#define EMU_A2_SRCSEL_ENABLE_SPDIF	0x00000004
+#define EMU_A2_SRCSEL_ENABLE_SRCMULTI	0x00000010
+#define EMU_A2_SRCMULTI			0x6e0000
+#define EMU_A2_SRCMULTI_ENABLE_INPUT	0xff00ff00
+
+/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
+
+#define EMU_CHAN_CPF	0x00
+
+#define  EMU_CHAN_CPF_PITCH_MASK	0xffff0000
+#define  EMU_CHAN_CPF_PITCH	EMU_MKSUBREG(16, 16, EMU_CHAN_CPF)
+#define  EMU_CHAN_CPF_STEREO_MASK	0x00008000
+#define  EMU_CHAN_CPF_STEREO	EMU_MKSUBREG(1, 15, EMU_CHAN_CPF)
+#define  EMU_CHAN_CPF_STOP_MASK	0x00004000
+#define  EMU_CHAN_CPF_FRACADDRESS_MASK	0x00003fff
+
+
+#define EMU_CHAN_PTRX	0x01
+#define  EMU_CHAN_PTRX_PITCHTARGET_MASK	0xffff0000
+#define  EMU_CHAN_PTRX_PITCHTARGET	EMU_MKSUBREG(16, 16, EMU_CHAN_PTRX)
+#define  EMU_CHAN_PTRX_FXSENDAMOUNT_A_MASK	0x0000ff00
+#define  EMU_CHAN_PTRX_FXSENDAMOUNT_A EMU_MKSUBREG(8, 8, EMU_CHAN_PTRX)
+#define  EMU_CHAN_PTRX_FXSENDAMOUNT_B_MASK	0x000000ff
+#define  EMU_CHAN_PTRX_FXSENDAMOUNT_B EMU_MKSUBREG(8, 0, EMU_CHAN_PTRX)
+
+#define EMU_CHAN_CVCF	0x02
+#define  EMU_CHAN_CVCF_CURRVOL_MASK	0xffff0000
+#define  EMU_CHAN_CVCF_CURRVOL	EMU_MKSUBREG(16, 16, EMU_CHAN_CVCF)
+#define  EMU_CHAN_CVCF_CURRFILTER_MASK	0x0000ffff
+#define  EMU_CHAN_CVCF_CURRFILTER EMU_MKSUBREG(16, 0, EMU_CHAN_CVCF)
+
+#define EMU_CHAN_VTFT	0x03
+#define  EMU_CHAN_VTFT_VOLUMETARGET_MASK	0xffff0000
+#define  EMU_CHAN_VTFT_VOLUMETARGET	EMU_MKSUBREG(16, 16, EMU_CHAN_VTFT)
+#define  EMU_CHAN_VTFT_FILTERTARGET_MASK	0x0000ffff
+#define	 EMU_CHAN_VTFT_FILTERTARGET	EMU_MKSUBREG(16, 0, EMU_CHAN_VTFT)
+
+#define EMU_CHAN_Z1	0x05
+#define EMU_CHAN_Z2	0x04
+
+#define EMU_CHAN_PSST	0x06
+#define  EMU_CHAN_PSST_FXSENDAMOUNT_C_MASK	0xff000000
+#define  EMU_CHAN_PSST_FXSENDAMOUNT_C EMU_MKSUBREG(8, 24, EMU_CHAN_PSST)
+#define  EMU_CHAN_PSST_LOOPSTARTADDR_MASK	0x00ffffff
+#define  EMU_CHAN_PSST_LOOPSTARTADDR  EMU_MKSUBREG(24, 0, EMU_CHAN_PSST)
+
+#define EMU_CHAN_DSL	0x07
+#define  EMU_CHAN_DSL_FXSENDAMOUNT_D_MASK	0xff000000
+#define  EMU_CHAN_DSL_FXSENDAMOUNT_D  EMU_MKSUBREG(8, 24, EMU_CHAN_DSL)
+#define  EMU_CHAN_DSL_LOOPENDADDR_MASK	0x00ffffff
+#define  EMU_CHAN_DSL_LOOPENDADDR	 EMU_MKSUBREG(24, 0, EMU_CHAN_DSL)
+
+#define EMU_CHAN_CCCA	0x08
+#define  EMU_CHAN_CCCA_RESONANCE		0xf0000000
+#define  EMU_CHAN_CCCA_INTERPROMMASK		0x0e000000
+#define   EMU_CHAN_CCCA_INTERPROM_0		0x00000000
+#define   EMU_CHAN_CCCA_INTERPROM_1		0x02000000
+#define   EMU_CHAN_CCCA_INTERPROM_2		0x04000000
+#define   EMU_CHAN_CCCA_INTERPROM_3		0x06000000
+#define   EMU_CHAN_CCCA_INTERPROM_4		0x08000000
+#define   EMU_CHAN_CCCA_INTERPROM_5		0x0a000000
+#define   EMU_CHAN_CCCA_INTERPROM_6		0x0c000000
+#define   EMU_CHAN_CCCA_INTERPROM_7		0x0e000000
+#define   EMU_CHAN_CCCA_8BITSELECT		0x01000000
+#define  EMU_CHAN_CCCA_CURRADDR_MASK		0x00ffffff
+#define  EMU_CHAN_CCCA_CURRADDR	EMU_MKSUBREG(24, 0, EMU_CHAN_CCCA)
+
+#define EMU_CHAN_CCR	0x09
+#define  EMU_CHAN_CCR_CACHEINVALIDSIZE_MASK	0xfe000000
+#define  EMU_CHAN_CCR_CACHEINVALIDSIZE EMU_MKSUBREG(7, 25, EMU_CHAN_CCR)
+#define  EMU_CHAN_CCR_CACHELOOPFLAG		0x01000000
+#define  EMU_CHAN_CCR_INTERLEAVEDSAMPLES	0x00800000
+#define  EMU_CHAN_CCR_WORDSIZEDSAMPLES	0x00400000
+#define  EMU_CHAN_CCR_READADDRESS_MASK	0x003f0000
+#define  EMU_CHAN_CCR_READADDRESS	EMU_MKSUBREG(6, 16, EMU_CHAN_CCR)
+#define  EMU_CHAN_CCR_LOOPINVALSIZE	0x0000fe00
+#define  EMU_CHAN_CCR_LOOPFLAG		0x00000100
+#define  EMU_CHAN_CCR_CACHELOOPADDRHI	0x000000ff
+
+#define EMU_CHAN_CLP	0x0a
+#define  EMU_CHAN_CLP_CACHELOOPADDR	0x0000ffff
+
+#define EMU_CHAN_FXRT	0x0b
+#define  EMU_CHAN_FXRT_CHANNELA		0x000f0000
+#define  EMU_CHAN_FXRT_CHANNELB		0x00f00000
+#define  EMU_CHAN_FXRT_CHANNELC		0x0f000000
+#define  EMU_CHAN_FXRT_CHANNELD		0xf0000000
+
+#define EMU_CHAN_MAPA	0x0c
+#define EMU_CHAN_MAPB	0x0d
+
+#define  EMU_CHAN_MAP_PTE_MASK		0xffffe000
+#define  EMU_CHAN_MAP_PTI_MASK		0x00001fff
+
+
+#define EMU_CHAN_ENVVOL	0x10
+#define  EMU_CHAN_ENVVOL_MASK		0x0000ffff
+
+
+#define EMU_CHAN_ATKHLDV 0x11
+#define  EMU_CHAN_ATKHLDV_PHASE0	0x00008000
+#define  EMU_CHAN_ATKHLDV_HOLDTIME_MASK	0x00007f00
+#define  EMU_CHAN_ATKHLDV_ATTACKTIME_MASK	0x0000007f
+
+
+#define EMU_CHAN_DCYSUSV	0x12
+#define  EMU_CHAN_DCYSUSV_PHASE1_MASK		0x00008000
+#define  EMU_CHAN_DCYSUSV_SUSTAINLEVEL_MASK	0x00007f00
+#define  EMU_CHAN_DCYSUSV_CHANNELENABLE_MASK	0x00000080
+#define  EMU_CHAN_DCYSUSV_DECAYTIME_MASK	0x0000007f
+
+
+#define EMU_CHAN_LFOVAL1	0x13
+#define  EMU_CHAN_LFOVAL_MASK		0x0000ffff
+
+#define EMU_CHAN_ENVVAL		0x14
+#define  EMU_CHAN_ENVVAL_MASK		0x0000ffff
+
+#define EMU_CHAN_ATKHLDM	0x15
+#define  EMU_CHAN_ATKHLDM_PHASE0	0x00008000
+#define  EMU_CHAN_ATKHLDM_HOLDTIME	0x00007f00
+#define  EMU_CHAN_ATKHLDM_ATTACKTIME	0x0000007f
+
+#define EMU_CHAN_DCYSUSM	0x16
+#define  EMU_CHAN_DCYSUSM_PHASE1_MASK		0x00008000
+#define  EMU_CHAN_DCYSUSM_SUSTAINLEVEL_MASK	0x00007f00
+#define  EMU_CHAN_DCYSUSM_DECAYTIME_MASK	0x0000007f
+
+#define EMU_CHAN_LFOVAL2	0x17
+#define  EMU_CHAN_LFOVAL2_MASK		0x0000ffff
+
+#define EMU_CHAN_IP		0x18
+#define  EMU_CHAN_IP_MASK			0x0000ffff
+#define  EMU_CHAN_IP_UNITY			0x0000e000
+
+#define EMU_CHAN_IFATN		0x19
+#define  EMU_CHAN_IFATN_FILTERCUTOFF_MASK	0x0000ff00
+#define  EMU_CHAN_IFATN_FILTERCUTOFF EMU_MKSUBREG(8, 8,	EMU_CHAN_IFATN)
+#define  EMU_CHAN_IFATN_ATTENUATION_MASK	0x000000ff
+#define  EMU_CHAN_IFATN_ATTENUATION	 EMU_MKSUBREG(8, 0, EMU_CHAN_IFATN)
+
+#define EMU_CHAN_PEFE		0x1a
+#define  EMU_CHAN_PEFE_PITCHAMOUNT_MASK	0x0000ff00
+#define  EMU_CHAN_PEFE_PITCHAMOUNT	EMU_MKSUBREG(8, 8, EMU_CHAN_PEFE)
+#define  EMU_CHAN_PEFE_FILTERAMOUNT_MASK	0x000000ff
+#define  EMU_CHAN_PEFE_FILTERAMOUNT	EMU_MKSUBREG(8, 0, EMU_CHAN_PEFE)
+
+#define EMU_CHAN_FMMOD	0x1b
+#define  EMU_CHAN_FMMOD_MODVIBRATO	0x0000ff00
+#define EMU_CHAN_FMMOD_MOFILTER		0x000000ff
+
+#define EMU_CHAN_TREMFRQ	0x1c
+#define  EMU_CHAN_TREMFRQ_DEPTH		0x0000ff00
+
+#define EMU_CHAN_FM2FRQ2	0x1d
+#define  EMU_CHAN_FM2FRQ2_DEPTH		0x0000ff00
+#define  EMU_CHAN_FM2FRQ2_FREQUENCY	0x000000ff
+
+#define EMU_CHAN_TEMPENV	0x1e
+#define  EMU_CHAN_TEMPENV_MASK		0x0000ffff
+
+#define EMU_CHAN_CD0	0x20
+#define EMU_CHAN_CD1	0x21
+#define EMU_CHAN_CD2	0x22
+#define EMU_CHAN_CD3	0x23
+#define EMU_CHAN_CD4	0x24
+#define EMU_CHAN_CD5	0x25
+#define EMU_CHAN_CD6	0x26
+#define EMU_CHAN_CD7	0x27
+#define EMU_CHAN_CD8	0x28
+#define EMU_CHAN_CD9	0x29
+#define EMU_CHAN_CDA	0x2a
+#define EMU_CHAN_CDB	0x2b
+#define EMU_CHAN_CDC	0x2c
+#define EMU_CHAN_CDD	0x2d
+#define EMU_CHAN_CDE	0x2e
+#define EMU_CHAN_CDF	0x2f
+
+/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
+
+#define EMU_PTB		0x40
+#define  EMU_PTB_MASK			0xfffff000
+
+#define EMU_TCB		0x41
+#define  EMU_TCB_MASK			0xfffff000
+
+#define EMU_ADCCR	0x42
+#define  EMU_ADCCR_RCHANENABLE		0x00000010
+#define  EMU_A_ADCCR_RCHANENABLE	0x00000020
+#define  EMU_ADCCR_LCHANENABLE		0x00000008
+#define  EMU_A_ADCCR_LCHANENABLE	0x00000010
+#define  EMU_ADCCR_SAMPLERATE_MASK	0x00000007
+#define  EMU_A_ADCCR_SAMPLERATE_MASK    0x0000000f
+#define   EMU_ADCCR_SAMPLERATE_48	0x00000000
+#define   EMU_ADCCR_SAMPLERATE_44	0x00000001
+#define   EMU_ADCCR_SAMPLERATE_32	0x00000002
+#define   EMU_ADCCR_SAMPLERATE_24	0x00000003
+#define   EMU_ADCCR_SAMPLERATE_22	0x00000004
+#define   EMU_ADCCR_SAMPLERATE_16	0x00000005
+#define   EMU_A_ADCCR_SAMPLERATE_12	0x00000006
+#define   EMU_ADCCR_SAMPLERATE_11	0x00000006
+#define   EMU_A_ADCCR_SAMPLERATE_11	0x00000007
+#define   EMU_ADCCR_SAMPLERATE_8	0x00000007
+#define   EMU_A_ADCCR_SAMPLERATE_8	0x00000008
+
+#define EMU_FXWC	0x43
+#define EMU_TCBS	0x44
+#define  EMU_TCBS_MASK			0x00000007
+#define   EMU_TCBS_BUFFSIZE_16K		0x00000000
+#define   EMU_TCBS_BUFFSIZE_32K		0x00000001
+#define   EMU_TCBS_BUFFSIZE_64K		0x00000002
+#define   EMU_TCBS_BUFFSIZE_128K	0x00000003
+#define   EMU_TCBS_BUFFSIZE_256K	0x00000004
+#define   EMU_TCBS_BUFFSIZE_512K	0x00000005
+#define   EMU_TCBS_BUFFSIZE_1024K	0x00000006
+#define   EMU_TCBS_BUFFSIZE_2048K	0x00000007
+
+#define EMU_MICBA	0x45
+#define EMU_ADCBA	0x46
+#define EMU_FXBA	0x47
+#define  EMU_RECBA_MASK			0xfffff000
+
+#define EMU_MICBS	0x49
+#define EMU_ADCBS	0x4a
+#define EMU_FXBS	0x4b
+#define  EMU_RECBS_BUFSIZE_NONE		0x00000000
+#define  EMU_RECBS_BUFSIZE_384		0x00000001
+#define  EMU_RECBS_BUFSIZE_448		0x00000002
+#define  EMU_RECBS_BUFSIZE_512		0x00000003
+#define  EMU_RECBS_BUFSIZE_640		0x00000004
+#define  EMU_RECBS_BUFSIZE_768		0x00000005
+#define  EMU_RECBS_BUFSIZE_896		0x00000006
+#define  EMU_RECBS_BUFSIZE_1024		0x00000007
+#define  EMU_RECBS_BUFSIZE_1280		0x00000008
+#define  EMU_RECBS_BUFSIZE_1536		0x00000009
+#define  EMU_RECBS_BUFSIZE_1792		0x0000000a
+#define  EMU_RECBS_BUFSIZE_2048		0x0000000b
+#define  EMU_RECBS_BUFSIZE_2560		0x0000000c
+#define  EMU_RECBS_BUFSIZE_3072		0x0000000d
+#define  EMU_RECBS_BUFSIZE_3584		0x0000000e
+#define  EMU_RECBS_BUFSIZE_4096		0x0000000f
+#define  EMU_RECBS_BUFSIZE_5120		0x00000010
+#define  EMU_RECBS_BUFSIZE_6144		0x00000011
+#define  EMU_RECBS_BUFSIZE_7168		0x00000012
+#define  EMU_RECBS_BUFSIZE_8192		0x00000013
+#define  EMU_RECBS_BUFSIZE_10240	0x00000014
+#define  EMU_RECBS_BUFSIZE_12288	0x00000015
+#define  EMU_RECBS_BUFSIZE_14366	0x00000016
+#define  EMU_RECBS_BUFSIZE_16384	0x00000017
+#define  EMU_RECBS_BUFSIZE_20480	0x00000018
+#define  EMU_RECBS_BUFSIZE_24576	0x00000019
+#define  EMU_RECBS_BUFSIZE_28672	0x0000001a
+#define  EMU_RECBS_BUFSIZE_32768	0x0000001b
+#define  EMU_RECBS_BUFSIZE_40960	0x0000001c
+#define  EMU_RECBS_BUFSIZE_49152	0x0000001d
+#define  EMU_RECBS_BUFSIZE_57344	0x0000001e
+#define  EMU_RECBS_BUFSIZE_65536	0x0000001f
+
+#define EMU_CDCS	0x50
+#define EMU_GPSCS	0x51
+
+#define EMU_DBG		0x52
+#define EMU_DBG_ZC			0x80000000
+#define  EMU_DBG_SATURATION_OCCURRED	0x02000000
+#define  EMU_DBG_SATURATION_ADDR	0x01ff0000
+#define  EMU_DBG_SINGLE_STEP		0x00008000
+#define  EMU_DBG_STEP			0x00004000
+#define  EMU_DBG_CONDITION_CODE		0x00003e00
+#define  EMU_DBG_SINGLE_STEP_ADDR	0x000001ff
+
+#define EMU_A_DBG			0x53
+#define EMU_A_DBG_SINGLE_STEP		0x00020000
+#define EMU_A_DBG_ZC			0x40000000
+#define EMU_A_DBG_STEP_ADDR		0x000003ff
+#define EMU_A_DBG_SATURATION_OCCRD	0x20000000
+#define EMU_A_DBG_SATURATION_ADDR	0x0ffc0000
+
+#define EMU_SPCS0	0x54
+#define EMU_SPCS1	0x55
+#define EMU_SPCS2	0x56
+#define  EMU_SPCS_CLKACCYMASK		0x30000000
+#define   EMU_SPCS_CLKACCY_1000PPM	0x00000000
+#define   EMU_SPCS_CLKACCY_50PPM	0x10000000
+#define   EMU_SPCS_CLKACCY_VARIABLE	0x20000000
+#define  EMU_SPCS_SAMPLERATEMASK	0x0f000000
+#define   EMU_SPCS_SAMPLERATE_44	0x00000000
+#define   EMU_SPCS_SAMPLERATE_48	0x02000000
+#define   EMU_SPCS_SAMPLERATE_32	0x03000000
+#define  EMU_SPCS_CHANNELNUMMASK	0x00f00000
+#define   EMU_SPCS_CHANNELNUM_UNSPEC	0x00000000
+#define   EMU_SPCS_CHANNELNUM_LEFT	0x00100000
+#define   EMU_SPCS_CHANNELNUM_RIGHT	0x00200000
+#define  EMU_SPCS_SOURCENUMMASK		0x000f0000
+#define   EMU_SPCS_SOURCENUM_UNSPEC	0x00000000
+#define  EMU_SPCS_GENERATIONSTATUS	0x00008000
+#define  EMU_SPCS_CATEGORYCODEMASK	0x00007f00
+#define  EMU_SPCS_MODEMASK		0x000000c0
+#define  EMU_SPCS_EMPHASISMASK		0x00000038
+#define   EMU_SPCS_EMPHASIS_NONE	0x00000000
+#define   EMU_SPCS_EMPHASIS_50_15	0x00000008
+#define  EMU_SPCS_COPYRIGHT		0x00000004
+#define  EMU_SPCS_NOTAUDIODATA		0x00000002
+#define  EMU_SPCS_PROFESSIONAL		0x00000001
+
+#define EMU_CLIEL	0x58
+#define EMU_CLIEH	0x59
+#define EMU_CLIPL	0x5a
+#define EMU_CLIPH	0x5b
+#define EMU_SOLEL	0x5c
+#define EMU_SOLEH	0x5d
+
+#define	EMU_SPBYPASS		0x5e
+#define	EMU_SPBYPASS_ENABLE	0x00000001
+#define	EMU_SPBYPASS_24_BITS	0x00000f00
+
+#define	EMU_AC97SLOT		0x5f
+#define	EMU_AC97SLOT_CENTER	0x00000010
+#define	EMU_AC97SLOT_LFE	0x00000020
+
+#define EMU_CDSRCS	0x60
+#define EMU_GPSRCS	0x61
+#define EMU_ZVSRCS	0x62
+#define  EMU_SRCS_SPDIFLOCKED		0x02000000
+#define  EMU_SRCS_RATELOCKED		0x01000000
+#define  EMU_SRCS_ESTSAMPLERATE		0x0007ffff
+
+#define EMU_MICIDX	0x63
+#define EMU_A_MICIDX	0x64
+#define EMU_ADCIDX	0x64
+#define EMU_A_ADCIDX	0x63
+#define EMU_FXIDX	0x65
+#define  EMU_RECIDX_MASK		0x0000ffff
+#define	 EMU_RECIDX(idxreg)	       (0x10000000|(idxreg))
+/*
+#define  EMU_MICIDX_IDX			0x10000063
+#define  EMU_ADCIDX_IDX			0x10000064
+#define  EMU_FXIDX_IDX			0x10000065
+*/
+
+#define EMU_A_MUDATA1		0x70
+#define EMU_A_MUCMD1		0x71
+#define EMU_A_MUSTAT1		EMU_A_MUCMD1
+#define EMU_A_MUDATA2		0x72
+#define EMU_A_MUCMD2		0x73
+#define EMU_A_MUSTAT2		EMU_A_MUCMD2
+#define EMU_A_FXWC1		0x74
+#define EMU_A_FXWC2		0x75
+#define EMU_A_SPDIF_SAMPLERATE	0x76
+#define EMU_A_SPDIF_48000	0x00000080
+#define EMU_A_SPDIF_44100	0x00000000
+#define EMU_A_SPDIF_96000	0x00000040
+#define EMU_A2_SPDIF_SAMPLERATE	EMU_MKSUBREG(3, 9, EMU_A_SPDIF_SAMPLERATE)
+#define EMU_A2_SPDIF_MASK	0x00000e00
+#define EMU_A2_SPDIF_UNKNOWN	0x2
+
+#define EMU_A_CHAN_FXRT2		0x7c
+#define EMU_A_CHAN_FXRT_CHANNELE	0x0000003f
+#define EMU_A_CHAN_FXRT_CHANNELF	0x00003f00
+#define EMU_A_CHAN_FXRT_CHANNELG	0x003f0000
+#define EMU_A_CHAN_FXRT_CHANNELH	0x3f000000
+#define EMU_A_CHAN_SENDAMOUNTS		0x7d
+#define EMU_A_CHAN_FXSENDAMOUNTS_E_MASK	0xff000000
+#define EMU_A_CHAN_FXSENDAMOUNTS_F_MASK	0x00ff0000
+#define EMU_A_CHAN_FXSENDAMOUNTS_G_MASK	0x0000ff00
+#define EMU_A_CHAN_FXSENDAMOUNTS_H_MASK	0x000000ff
+#define EMU_A_CHAN_FXRT1		0x7e
+#define EMU_A_CHAN_FXRT_CHANNELA	0x0000003f
+#define EMU_A_CHAN_FXRT_CHANNELB	0x00003f00
+#define EMU_A_CHAN_FXRT_CHANNELC	0x003f0000
+#define EMU_A_CHAN_FXRT_CHANNELD	0x3f000000
+
+#define EMU_FXGPREGBASE		0x100
+#define EMU_A_FXGPREGBASE	0x400
+
+#define EMU_TANKMEMDATAREGBASE	0x200
+#define  EMU_TANKMEMDATAREG_MASK	0x000fffff
+
+#define EMU_TANKMEMADDRREGBASE	0x300
+#define  EMU_TANKMEMADDRREG_ADDR_MASK	0x000fffff
+#define  EMU_TANKMEMADDRREG_CLEAR	0x00800000
+#define  EMU_TANKMEMADDRREG_ALIGN	0x00400000
+#define  EMU_TANKMEMADDRREG_WRITE	0x00200000
+#define  EMU_TANKMEMADDRREG_READ	0x00100000
+
+#define  EMU_MICROCODEBASE	0x400
+#define  EMU_A_MICROCODEBASE		0x600
+#define  EMU_DSP_LOWORD_OPX_MASK	0x000ffc00
+#define  EMU_DSP_LOWORD_OPY_MASK	0x000003ff
+#define  EMU_DSP_HIWORD_OPCODE_MASK	0x00f00000
+#define  EMU_DSP_HIWORD_RESULT_MASK	0x000ffc00
+#define  EMU_DSP_HIWORD_OPA_MASK	0x000003ff
+#define  EMU_A_DSP_LOWORD_OPX_MASK	0x007ff000
+#define  EMU_A_DSP_LOWORD_OPY_MASK	0x000007ff
+#define  EMU_A_DSP_HIWORD_OPCODE_MASK	0x0f000000
+#define  EMU_A_DSP_HIWORD_RESULT_MASK	0x007ff000
+#define  EMU_A_DSP_HIWORD_OPA_MASK	0x000007ff
+
+#define	EMU_DSP_OP_MACS		0x0
+#define	EMU_DSP_OP_MACS1	0x1
+#define	EMU_DSP_OP_MACW		0x2
+#define	EMU_DSP_OP_MACW1	0x3
+#define	EMU_DSP_OP_MACINTS	0x4
+#define	EMU_DSP_OP_MACINTW	0x5
+#define	EMU_DSP_OP_ACC3		0x6
+#define	EMU_DSP_OP_MACMV	0x7
+#define	EMU_DSP_OP_ANDXOR	0x8
+#define	EMU_DSP_OP_TSTNEG	0x9
+#define	EMU_DSP_OP_LIMIT	0xA
+#define	EMU_DSP_OP_LIMIT1	0xB
+#define	EMU_DSP_OP_LOG		0xC
+#define	EMU_DSP_OP_EXP		0xD
+#define	EMU_DSP_OP_INTERP	0xE
+#define	EMU_DSP_OP_SKIP		0xF
+
+
+#define	EMU_DSP_FX(num)	(num)
+
+#define	EMU_DSP_IOL(base, num)	(base + (num << 1))
+#define	EMU_DSP_IOR(base, num)	(EMU_DSP_IOL(base, num) + 1)
+
+#define	EMU_DSP_INL_BASE	0x010
+#define	EMU_DSP_INL(num)	(EMU_DSP_IOL(EMU_DSP_INL_BASE, num))
+#define	EMU_DSP_INR(num)	(EMU_DSP_IOR(EMU_DSP_INL_BASE, num))
+#define	EMU_A_DSP_INL_BASE	0x040
+#define	EMU_A_DSP_INL(num)	(EMU_DSP_IOL(EMU_A_DSP_INL_BASE, num))
+#define	EMU_A_DSP_INR(num)	(EMU_DSP_IOR(EMU_A_DSP_INL_BASE, num))
+#define	 EMU_DSP_IN_AC97	0
+#define	 EMU_DSP_IN_CDSPDIF	1
+#define  EMU_DSP_IN_ZOOM	2
+#define	 EMU_DSP_IN_TOSOPT	3
+#define	 EMU_DSP_IN_LVDLM1	4
+#define	 EMU_DSP_IN_LVDCOS	5
+#define	 EMU_DSP_IN_LVDLM2	6
+#define	EMU_DSP_IN_UNKNOWN	7
+
+#define	EMU_DSP_OUTL_BASE	0x020
+#define	EMU_DSP_OUTL(num)	(EMU_DSP_IOL(EMU_DSP_OUTL_BASE, num))
+#define	EMU_DSP_OUTR(num)	(EMU_DSP_IOR(EMU_DSP_OUTL_BASE, num))
+#define	EMU_DSP_OUT_A_FRONT	0
+#define	EMU_DSP_OUT_D_FRONT	1
+#define	EMU_DSP_OUT_D_CENTER	2
+#define	EMU_DSP_OUT_DRIVE_HP	3
+#define	EMU_DSP_OUT_AD_REAR	4
+#define	EMU_DSP_OUT_ADC		5
+#define	EMU_DSP_OUTL_MIC	6
+
+#define	EMU_A_DSP_OUTL_BASE	0x060
+#define	EMU_A_DSP_OUTL(num)	(EMU_DSP_IOL(EMU_A_DSP_OUTL_BASE, num))
+#define	EMU_A_DSP_OUTR(num)	(EMU_DSP_IOR(EMU_A_DSP_OUTL_BASE, num))
+#define	EMU_A_DSP_OUT_D_FRONT	0
+#define	EMU_A_DSP_OUT_D_CENTER	1
+#define	EMU_A_DSP_OUT_DRIVE_HP	2
+#define	EMU_A_DSP_OUT_DREAR	3
+#define	EMU_A_DSP_OUT_A_FRONT	4
+#define	EMU_A_DSP_OUT_A_CENTER	5
+#define	EMU_A_DSP_OUT_A_REAR	7
+#define EMU_A_DSP_OUT_ADC	11
+
+#define	EMU_DSP_CST_BASE	0x40
+#define	EMU_A_DSP_CST_BASE	0xc0
+#define	EMU_DSP_CST(num)	(EMU_DSP_CST_BASE + num)
+#define	EMU_A_DSP_CST(num)	(EMU_A_DSP_CST_BASE + num)
+/*
+00	= 0x00000000
+01	= 0x00000001
+02	= 0x00000002
+03	= 0x00000003
+04	= 0x00000004
+05	= 0x00000008
+06	= 0x00000010
+07	= 0x00000020
+08	= 0x00000100
+09	= 0x00010000
+0A	= 0x00080000
+0B	= 0x10000000
+0C	= 0x20000000
+0D	= 0x40000000
+0E	= 0x80000000
+0F	= 0x7FFFFFFF
+10	= 0xFFFFFFFF
+11	= 0xFFFFFFFE
+12	= 0xC0000000
+13	= 0x4F1BBCDC
+14	= 0x5A7EF9DB
+15	= 0x00100000
+*/
+
+#define	EMU_DSP_HWR_ACC		0x056
+#define EMU_DSP_HWR_CCR		0x057
+#define	 EMU_DSP_HWR_CCR_S	0x04
+#define	 EMU_DSP_HWR_CCR_Z	0x03
+#define	 EMU_DSP_HWR_CCR_M	0x02
+#define	 EMU_DSP_HWR_CCR_N	0x01
+#define	 EMU_DSP_HWR_CCR_B	0x00
+#define	EMU_DSP_HWR_NOISE0	0x058
+#define	EMU_DSP_HWR_NOISE1	0x059
+#define	EMU_DSP_HWR_INTR	0x05A
+#define	EMU_DSP_HWR_DBAC	0x05B
+
+#define EMU_DSP_GPR(num)	(EMU_FXGPREGBASE + num)
+#define EMU_A_DSP_GPR(num)	(EMU_A_FXGPREGBASE + num)
+
+#endif /* _DEV_PCI_EMUXKIREG_H_ */
diff --git a/sys/dev/sound/pci/fm801.c b/sys/dev/sound/pci/fm801.c
index 9f00652..ccfef36 100644
--- a/sys/dev/sound/pci/fm801.c
+++ b/sys/dev/sound/pci/fm801.c
@@ -276,7 +276,7 @@ fm801_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
 static kobj_method_t fm801_ac97_methods[] = {
     	KOBJMETHOD(ac97_read,		fm801_rdcd),
     	KOBJMETHOD(ac97_write,		fm801_wrcd),
-	KOBJMETHOD_END
+	DEVMETHOD_END
 };
 AC97_DECLARE(fm801_ac97);
 
@@ -530,7 +530,7 @@ static kobj_method_t fm801ch_methods[] = {
     	KOBJMETHOD(channel_trigger,		fm801ch_trigger),
     	KOBJMETHOD(channel_getptr,		fm801ch_getptr),
     	KOBJMETHOD(channel_getcaps,		fm801ch_getcaps),
-	KOBJMETHOD_END
+	DEVMETHOD_END
 };
 CHANNEL_DECLARE(fm801ch);
 
@@ -749,12 +749,12 @@ static device_method_t fm801_methods[] = {
 	DEVMETHOD(device_resume,	bus_generic_resume),
 
 	/* Bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
 	DEVMETHOD(bus_alloc_resource,	fm801_alloc_resource),
 	DEVMETHOD(bus_release_resource,	fm801_release_resource),
 	DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
 	DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
-	{ 0, 0}
+
+	DEVMETHOD_END
 };
 
 static driver_t fm801_driver = {
diff --git a/sys/dev/sound/pci/hda/hdac.c b/sys/dev/sound/pci/hda/hdac.c
index 66aa162..a190e0b 100644
--- a/sys/dev/sound/pci/hda/hdac.c
+++ b/sys/dev/sound/pci/hda/hdac.c
@@ -4971,6 +4971,30 @@ hdac_vendor_patch_parse(struct hdac_devinfo *devinfo)
 		if (w != NULL)
 			w->connsenable[0] = 0;
 		break;
+	case HDA_CODEC_VT1708S_0:
+	case HDA_CODEC_VT1708S_1:
+	case HDA_CODEC_VT1708S_2:
+	case HDA_CODEC_VT1708S_3:
+	case HDA_CODEC_VT1708S_4:
+	case HDA_CODEC_VT1708S_5:
+	case HDA_CODEC_VT1708S_6:
+	case HDA_CODEC_VT1708S_7:
+		/*
+		 * These codecs have hidden mic boost controls.
+		 */
+		w = hdac_widget_get(devinfo, 26);
+		if (w != NULL)
+			w->param.inamp_cap =
+			    (40 << HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_SHIFT) |
+			    (3 << HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_SHIFT) |
+			    (0 << HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_SHIFT);
+		w = hdac_widget_get(devinfo, 30);
+		if (w != NULL)
+			w->param.inamp_cap =
+			    (40 << HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_SHIFT) |
+			    (3 << HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_SHIFT) |
+			    (0 << HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_SHIFT);
+		break;
 	}
 }
 
@@ -6458,7 +6482,7 @@ hdac_audio_commit(struct hdac_devinfo *devinfo)
 	struct hdac_softc *sc = devinfo->codec->sc;
 	struct hdac_widget *w;
 	nid_t cad;
-	uint32_t gdata, gmask, gdir;
+	uint32_t id, gdata, gmask, gdir;
 	int commitgpio, numgpio;
 	int i;
 
@@ -6467,6 +6491,24 @@ hdac_audio_commit(struct hdac_devinfo *devinfo)
 	if (sc->pci_subvendor == APPLE_INTEL_MAC)
 		hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid,
 		    0x7e7, 0), cad);
+	id = hdac_codec_id(devinfo->codec);
+	switch (id) {
+	case HDA_CODEC_VT1708S_0:
+	case HDA_CODEC_VT1708S_1:
+	case HDA_CODEC_VT1708S_2:
+	case HDA_CODEC_VT1708S_3:
+	case HDA_CODEC_VT1708S_4:
+	case HDA_CODEC_VT1708S_5:
+	case HDA_CODEC_VT1708S_6:
+	case HDA_CODEC_VT1708S_7:
+		/* Enable Mic Boost Volume controls. */
+		hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid,
+		    0xf98, 0x01), cad);
+		/* Don't bypass mixer. */
+		hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid,
+		    0xf88, 0xc0), cad);
+		break;
+	}
 
 	/* Commit controls. */
 	hdac_audio_ctl_commit(devinfo);
@@ -7768,10 +7810,6 @@ hdac_attach2(void *arg)
 			);
 			hdac_audio_parse(devinfo);
 			HDA_BOOTHVERBOSE(
-				device_printf(sc->dev, "Parsing Ctls...\n");
-			);
-		    	hdac_audio_ctl_parse(devinfo);
-			HDA_BOOTHVERBOSE(
 				device_printf(sc->dev, "Parsing vendor patch...\n");
 			);
 			hdac_vendor_patch_parse(devinfo);
@@ -7779,6 +7817,10 @@ hdac_attach2(void *arg)
 			devinfo->function.audio.quirks &= ~quirks_off;
 
 			HDA_BOOTHVERBOSE(
+				device_printf(sc->dev, "Parsing Ctls...\n");
+			);
+			hdac_audio_ctl_parse(devinfo);
+			HDA_BOOTHVERBOSE(
 				device_printf(sc->dev, "Disabling nonaudio...\n");
 			);
 			hdac_audio_disable_nonaudio(devinfo);
diff --git a/sys/dev/sound/usb/uaudio.c b/sys/dev/sound/usb/uaudio.c
index 0445572..7d97a42 100644
--- a/sys/dev/sound/usb/uaudio.c
+++ b/sys/dev/sound/usb/uaudio.c
@@ -31,6 +31,9 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 /*
  * USB audio specs: http://www.usb.org/developers/devclass_docs/audio10.pdf
  *                  http://www.usb.org/developers/devclass_docs/frmts10.pdf
@@ -522,8 +525,8 @@ static device_method_t uaudio_methods[] = {
 	DEVMETHOD(device_suspend, bus_generic_suspend),
 	DEVMETHOD(device_resume, bus_generic_resume),
 	DEVMETHOD(device_shutdown, bus_generic_shutdown),
-	DEVMETHOD(bus_print_child, bus_generic_print_child),
-	{0, 0}
+
+	DEVMETHOD_END
 };
 
 static driver_t uaudio_driver = {
@@ -762,7 +765,17 @@ uaudio_detach(device_t dev)
 {
 	struct uaudio_softc *sc = device_get_softc(dev);
 
-	if (bus_generic_detach(dev)) {
+	/*
+	 * Stop USB transfers early so that any audio applications
+	 * will time out and close opened /dev/dspX.Y device(s), if
+	 * any.
+	 */
+	if (sc->sc_play_chan.valid)
+		usbd_transfer_unsetup(sc->sc_play_chan.xfer, UAUDIO_NCHANBUFS);
+	if (sc->sc_rec_chan.valid)
+		usbd_transfer_unsetup(sc->sc_rec_chan.xfer, UAUDIO_NCHANBUFS);
+
+	if (bus_generic_detach(dev) != 0) {
 		DPRINTF("detach failed!\n");
 	}
 	sbuf_delete(&sc->sc_sndstat);
diff --git a/sys/dev/sound/usb/uaudio.h b/sys/dev/sound/usb/uaudio.h
index 622cb3b..10c10de 100644
--- a/sys/dev/sound/usb/uaudio.h
+++ b/sys/dev/sound/usb/uaudio.h
@@ -27,6 +27,9 @@
 
 /* prototypes from "uaudio.c" used by "uaudio_pcm.c" */
 
+#ifndef _UAUDIO_H_
+#define	_UAUDIO_H_
+
 struct uaudio_chan;
 struct uaudio_softc;
 struct snd_dbuf;
@@ -63,3 +66,5 @@ extern uint32_t	uaudio_mixer_setrecsrc(struct uaudio_softc *sc, uint32_t src);
 int	uaudio_get_vendor(device_t dev);
 int	uaudio_get_product(device_t dev);
 int	uaudio_get_release(device_t dev);
+
+#endif			/* _UAUDIO_H_ */
diff --git a/sys/dev/speaker/spkr.c b/sys/dev/speaker/spkr.c
index 2d52519..94d4792 100644
--- a/sys/dev/speaker/spkr.c
+++ b/sys/dev/speaker/spkr.c
@@ -130,7 +130,9 @@ rest(int centisecs)
  * except possibly at physical block boundaries.
  */
 
+#ifndef  __bool_true_false_are_defined
 typedef int	bool;
+#endif
 #define TRUE	1
 #define FALSE	0
 
diff --git a/sys/dev/spibus/spibus.c b/sys/dev/spibus/spibus.c
index 9491734..43b4e7e 100644
--- a/sys/dev/spibus/spibus.c
+++ b/sys/dev/spibus/spibus.c
@@ -173,7 +173,6 @@ static device_method_t spibus_methods[] = {
 	/* Bus interface */
 	DEVMETHOD(bus_add_child,	spibus_add_child),
 	DEVMETHOD(bus_print_child,	spibus_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
 	DEVMETHOD(bus_probe_nomatch,	spibus_probe_nomatch),
 	DEVMETHOD(bus_read_ivar,	spibus_read_ivar),
 	DEVMETHOD(bus_child_pnpinfo_str, spibus_child_pnpinfo_str),
@@ -183,7 +182,7 @@ static device_method_t spibus_methods[] = {
 	/* spibus interface */
 	DEVMETHOD(spibus_transfer,	spibus_transfer_impl),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t spibus_driver = {
diff --git a/sys/dev/spibus/spibusvar.h b/sys/dev/spibus/spibusvar.h
index 543fcfe..c035be1 100644
--- a/sys/dev/spibus/spibusvar.h
+++ b/sys/dev/spibus/spibusvar.h
@@ -18,7 +18,7 @@ enum {
 };
 
 #define SPIBUS_ACCESSOR(A, B, T)					\
-__inline static int							\
+static inline int							\
 spibus_get_ ## A(device_t dev, T *t)					\
 {									\
 	return BUS_READ_IVAR(device_get_parent(dev), dev,		\
diff --git a/sys/dev/ste/if_ste.c b/sys/dev/ste/if_ste.c
index a6fc00b..03e4eaa 100644
--- a/sys/dev/ste/if_ste.c
+++ b/sys/dev/ste/if_ste.c
@@ -161,16 +161,12 @@ static device_method_t ste_methods[] = {
 	DEVMETHOD(device_suspend,	ste_suspend),
 	DEVMETHOD(device_resume,	ste_resume),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	ste_miibus_readreg),
 	DEVMETHOD(miibus_writereg,	ste_miibus_writereg),
 	DEVMETHOD(miibus_statchg,	ste_miibus_statchg),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t ste_driver = {
diff --git a/sys/dev/stge/if_stge.c b/sys/dev/stge/if_stge.c
index b18da27..28e9584 100644
--- a/sys/dev/stge/if_stge.c
+++ b/sys/dev/stge/if_stge.c
@@ -214,7 +214,7 @@ static device_method_t stge_methods[] = {
 	DEVMETHOD(miibus_writereg,	stge_miibus_writereg),
 	DEVMETHOD(miibus_statchg,	stge_miibus_statchg),
 
-	KOBJMETHOD_END
+	DEVMETHOD_END
 };
 
 static driver_t stge_driver = {
diff --git a/sys/dev/syscons/syscons.c b/sys/dev/syscons/syscons.c
index 3928d91..4910914 100644
--- a/sys/dev/syscons/syscons.c
+++ b/sys/dev/syscons/syscons.c
@@ -185,6 +185,7 @@ static void scshutdown(void *, int);
 static void scsuspend(void *);
 static void scresume(void *);
 static u_int scgetc(sc_softc_t *sc, u_int flags);
+static void sc_puts(scr_stat *scp, u_char *buf, int len, int kernel);
 #define SCGETC_CN	1
 #define SCGETC_NONBLOCK	2
 static void sccnupdate(scr_stat *scp);
@@ -228,6 +229,8 @@ static cn_init_t	sc_cninit;
 static cn_term_t	sc_cnterm;
 static cn_getc_t	sc_cngetc;
 static cn_putc_t	sc_cnputc;
+static cn_grab_t	sc_cngrab;
+static cn_ungrab_t	sc_cnungrab;
 
 CONSOLE_DRIVER(sc);
 
@@ -1608,6 +1611,58 @@ sc_cnterm(struct consdev *cp)
 }
 
 static void
+sc_cngrab(struct consdev *cp)
+{
+    scr_stat *scp;
+
+    if (!cold &&
+	sc_console->sc->cur_scp->index != sc_console->index &&
+	sc_console->sc->cur_scp->smode.mode == VT_AUTO &&
+	sc_console->smode.mode == VT_AUTO)
+	    sc_switch_scr(sc_console->sc, sc_console->index);
+
+    scp = sc_console->sc->cur_scp;
+
+    if (scp->sc->kbd == NULL)
+	return;
+
+    if (scp->grabbed++ > 0)
+	return;
+
+    /*
+     * Make sure the keyboard is accessible even when the kbd device
+     * driver is disabled.
+     */
+    kbdd_enable(scp->sc->kbd);
+
+    /* we shall always use the keyboard in the XLATE mode here */
+    scp->kbd_prev_mode = scp->kbd_mode;
+    scp->kbd_mode = K_XLATE;
+    (void)kbdd_ioctl(scp->sc->kbd, KDSKBMODE, (caddr_t)&scp->kbd_mode);
+
+    kbdd_poll(scp->sc->kbd, TRUE);
+}
+
+static void
+sc_cnungrab(struct consdev *cp)
+{
+    scr_stat *scp;
+
+    scp = sc_console->sc->cur_scp;	/* XXX */
+    if (scp->sc->kbd == NULL)
+	return;
+
+    if (--scp->grabbed > 0)
+	return;
+
+    kbdd_poll(scp->sc->kbd, FALSE);
+
+    scp->kbd_mode = scp->kbd_prev_mode;
+    (void)kbdd_ioctl(scp->sc->kbd, KDSKBMODE, (caddr_t)&scp->kbd_mode);
+    kbdd_disable(scp->sc->kbd);
+}
+
+static void
 sc_cnputc(struct consdev *cd, int c)
 {
     u_char buf[1];
@@ -1662,7 +1717,6 @@ sc_cngetc(struct consdev *cd)
     static int fkeycp;
     scr_stat *scp;
     const u_char *p;
-    int cur_mode;
     int s = spltty();	/* block sckbdevent and scrn_timer while we poll */
     int c;
 
@@ -1686,25 +1740,7 @@ sc_cngetc(struct consdev *cd)
 	return -1;
     }
 
-    /* 
-     * Make sure the keyboard is accessible even when the kbd device
-     * driver is disabled.
-     */
-    kbdd_enable(scp->sc->kbd);
-
-    /* we shall always use the keyboard in the XLATE mode here */
-    cur_mode = scp->kbd_mode;
-    scp->kbd_mode = K_XLATE;
-    (void)kbdd_ioctl(scp->sc->kbd, KDSKBMODE, (caddr_t)&scp->kbd_mode);
-
-    kbdd_poll(scp->sc->kbd, TRUE);
     c = scgetc(scp->sc, SCGETC_CN | SCGETC_NONBLOCK);
-    kbdd_poll(scp->sc->kbd, FALSE);
-
-    scp->kbd_mode = cur_mode;
-    (void)kbdd_ioctl(scp->sc->kbd, KDSKBMODE, (caddr_t)&scp->kbd_mode);
-    kbdd_disable(scp->sc->kbd);
-    splx(s);
 
     switch (KEYFLAGS(c)) {
     case 0:	/* normal char */
@@ -2603,7 +2639,7 @@ exchange_scr(sc_softc_t *sc)
     mark_all(scp);
 }
 
-void
+static void
 sc_puts(scr_stat *scp, u_char *buf, int len, int kernel)
 {
     int need_unlock = 0;
diff --git a/sys/dev/syscons/syscons.h b/sys/dev/syscons/syscons.h
index 79f531b..e88ac43 100644
--- a/sys/dev/syscons/syscons.h
+++ b/sys/dev/syscons/syscons.h
@@ -301,7 +301,9 @@ typedef struct scr_stat {
 	void		*ts;
 
 	int	 	status;			/* status (bitfield) */
+	int		grabbed;
 	int		kbd_mode;		/* keyboard I/O mode */
+	int		kbd_prev_mode;		/* keyboard I/O mode */
 
 	int		cursor_pos;		/* cursor buffer position */
 	int		cursor_oldpos;		/* cursor old buffer position */
@@ -562,7 +564,6 @@ void		sc_save_font(scr_stat *scp, int page, int size, int width,
 void		sc_show_font(scr_stat *scp, int page);
 
 void		sc_touch_scrn_saver(void);
-void		sc_puts(scr_stat *scp, u_char *buf, int len, int kernel);
 void		sc_draw_cursor_image(scr_stat *scp);
 void		sc_remove_cursor_image(scr_stat *scp);
 void		sc_set_cursor_image(scr_stat *scp);
diff --git a/sys/dev/ti/if_ti.c b/sys/dev/ti/if_ti.c
index d57be53..ead6901 100644
--- a/sys/dev/ti/if_ti.c
+++ b/sys/dev/ti/if_ti.c
@@ -1562,7 +1562,6 @@ ti_newbuf_jumbo(struct ti_softc *sc, int idx, struct mbuf *m_old)
 	struct mbuf *m[3] = {NULL, NULL, NULL};
 	struct ti_rx_desc_ext *r;
 	vm_page_t frame;
-	static int color;
 	/* 1 extra buf to make nobufs easy*/
 	struct sf_buf *sf[3] = {NULL, NULL, NULL};
 	int i;
@@ -1605,7 +1604,7 @@ ti_newbuf_jumbo(struct ti_softc *sc, int idx, struct mbuf *m_old)
 				    "failed -- packet dropped!\n");
 				goto nobufs;
 			}
-			frame = vm_page_alloc(NULL, color++,
+			frame = vm_page_alloc(NULL, 0,
 			    VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
 			    VM_ALLOC_WIRED);
 			if (frame == NULL) {
diff --git a/sys/dev/tl/if_tl.c b/sys/dev/tl/if_tl.c
index b5ffc2c..4ab97e4 100644
--- a/sys/dev/tl/if_tl.c
+++ b/sys/dev/tl/if_tl.c
@@ -348,16 +348,12 @@ static device_method_t tl_methods[] = {
 	DEVMETHOD(device_detach,	tl_detach),
 	DEVMETHOD(device_shutdown,	tl_shutdown),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	tl_miibus_readreg),
 	DEVMETHOD(miibus_writereg,	tl_miibus_writereg),
 	DEVMETHOD(miibus_statchg,	tl_miibus_statchg),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t tl_driver = {
diff --git a/sys/dev/tsec/if_tsec_fdt.c b/sys/dev/tsec/if_tsec_fdt.c
index b320a25..55132eb 100644
--- a/sys/dev/tsec/if_tsec_fdt.c
+++ b/sys/dev/tsec/if_tsec_fdt.c
@@ -88,15 +88,12 @@ static device_method_t tsec_methods[] = {
 	DEVMETHOD(device_suspend,	tsec_suspend),
 	DEVMETHOD(device_resume,	tsec_resume),
 
-	/* Bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	tsec_miibus_readreg),
 	DEVMETHOD(miibus_writereg,	tsec_miibus_writereg),
 	DEVMETHOD(miibus_statchg,	tsec_miibus_statchg),
-	{ 0, 0 }
+
+	DEVMETHOD_END
 };
 
 static driver_t tsec_fdt_driver = {
diff --git a/sys/dev/twa/tw_osl.h b/sys/dev/twa/tw_osl.h
index 1cc40fb..8927c76 100644
--- a/sys/dev/twa/tw_osl.h
+++ b/sys/dev/twa/tw_osl.h
@@ -153,7 +153,7 @@ struct twa_softc {
 	struct mtx		sim_lock_handle;/* sim lock shared with cam */
 	struct mtx		*sim_lock;/* ptr to sim lock */
 
-	struct callout		watchdog_callout[2]; /* For command timout */
+	struct callout		watchdog_callout[2]; /* For command timeout */
 	TW_UINT32		watchdog_index;
 
 #ifdef TW_OSL_DEBUG
diff --git a/sys/dev/twa/tw_osl_freebsd.c b/sys/dev/twa/tw_osl_freebsd.c
index 5651b7f..0d018b6 100644
--- a/sys/dev/twa/tw_osl_freebsd.c
+++ b/sys/dev/twa/tw_osl_freebsd.c
@@ -25,10 +25,11 @@
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
- *
- *	$FreeBSD$
  */
 
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 /*
  * AMCC'S 3ware driver for 9000 series storage controllers.
  *
@@ -195,9 +196,7 @@ static device_method_t	twa_methods[] = {
 	DEVMETHOD(device_detach,	twa_detach),
 	DEVMETHOD(device_shutdown,	twa_shutdown),
 
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-	{0, 0}
+	DEVMETHOD_END
 };
 
 static driver_t	twa_pci_driver = {
diff --git a/sys/dev/twe/twe_freebsd.c b/sys/dev/twe/twe_freebsd.c
index a7b9c91..29dab58 100644
--- a/sys/dev/twe/twe_freebsd.c
+++ b/sys/dev/twe/twe_freebsd.c
@@ -25,10 +25,11 @@
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
- *
- * $FreeBSD$
  */
 
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 /*
  * FreeBSD-specific code.
  */
@@ -135,9 +136,7 @@ static device_method_t twe_methods[] = {
     DEVMETHOD(device_suspend,	twe_suspend),
     DEVMETHOD(device_resume,	twe_resume),
 
-    DEVMETHOD(bus_print_child,	bus_generic_print_child),
-    DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-    { 0, 0 }
+    DEVMETHOD_END
 };
 
 static driver_t twe_pci_driver = {
diff --git a/sys/dev/tws/tws.c b/sys/dev/tws/tws.c
index 750f878..2a2384a 100644
--- a/sys/dev/tws/tws.c
+++ b/sys/dev/tws/tws.c
@@ -30,10 +30,10 @@
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
- *
- * $FreeBSD$
-*/
+ */
 
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
 
 #include <dev/tws/tws.h>
 #include <dev/tws/tws_services.h>
@@ -685,6 +685,7 @@ tws_init_reqs(struct tws_softc *sc, u_int32_t dma_mem_size)
     {
         if (bus_dmamap_create(sc->data_tag, 0, &sc->reqs[i].dma_map)) {
             /* log a ENOMEM failure msg here */
+	    mtx_unlock(&sc->q_lock);
             return(FAILURE);
         } 
         sc->reqs[i].cmd_pkt =  &cmd_buf[i];
@@ -882,9 +883,7 @@ static device_method_t tws_methods[] = {
     DEVMETHOD(device_suspend,   tws_suspend),
     DEVMETHOD(device_resume,    tws_resume),
 
-    DEVMETHOD(bus_print_child,      bus_generic_print_child),
-    DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
-    { 0, 0 }
+    DEVMETHOD_END
 };
 
 static driver_t tws_driver = {
diff --git a/sys/dev/tws/tws.h b/sys/dev/tws/tws.h
index cf9f727..6d0f6ad 100644
--- a/sys/dev/tws/tws.h
+++ b/sys/dev/tws/tws.h
@@ -205,7 +205,11 @@ struct tws_init_connect_info {
 
 /* ------------ boolean types ------------------- */
 
+#ifndef __bool_true_false_are_defined
 typedef enum _boolean { false, true } boolean;
+#else
+#define	boolean		bool
+#endif
 enum err { SUCCESS, FAILURE };
 
 /* ----------- per instance data ---------------- */
diff --git a/sys/dev/uart/uart_bus_fdt.c b/sys/dev/uart/uart_bus_fdt.c
index f8204b1..8bb62ea 100644
--- a/sys/dev/uart/uart_bus_fdt.c
+++ b/sys/dev/uart/uart_bus_fdt.c
@@ -155,11 +155,11 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
 	/*
 	 * Retrieve /chosen/std{in,out}.
 	 */
-	if ((chosen = OF_finddevice("/chosen")) == 0)
+	if ((chosen = OF_finddevice("/chosen")) == -1)
 		return (ENXIO);
 	if (OF_getprop(chosen, "stdin", buf, sizeof(buf)) <= 0)
 		return (ENXIO);
-	if ((node = OF_finddevice(buf)) == 0)
+	if ((node = OF_finddevice(buf)) == -1)
 		return (ENXIO);
 	if (OF_getprop(chosen, "stdout", buf, sizeof(buf)) <= 0)
 		return (ENXIO);
@@ -186,7 +186,7 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
 
 	di->bas.chan = 0;
 	di->bas.regshft = (u_int)shift;
-	di->baudrate = 0;
+	di->baudrate = br;
 	di->bas.rclk = (u_int)rclk;
 	di->ops = uart_getops(class);
 	di->databits = 8;
diff --git a/sys/dev/uart/uart_bus_pci.c b/sys/dev/uart/uart_bus_pci.c
index 7c5b8b3..d308ce9 100644
--- a/sys/dev/uart/uart_bus_pci.c
+++ b/sys/dev/uart/uart_bus_pci.c
@@ -111,6 +111,11 @@ static struct pci_id pci_ns8250_ids[] = {
 { 0x1415, 0x950b, 0xffff, 0, "Oxford Semiconductor OXCB950 Cardbus 16950 UART",
 	0x10, 16384000 },
 { 0x151f, 0x0000, 0xffff, 0, "TOPIC Semiconductor TP560 56k modem", 0x10 },
+{ 0x8086, 0x1c3d, 0xffff, 0, "Intel AMT - KT Controller", 0x10 },
+{ 0x8086, 0x8811, 0xffff, 0, "Intel EG20T Serial Port 0", 0x10 },
+{ 0x8086, 0x8812, 0xffff, 0, "Intel EG20T Serial Port 1", 0x10 },
+{ 0x8086, 0x8813, 0xffff, 0, "Intel EG20T Serial Port 2", 0x10 },
+{ 0x8086, 0x8814, 0xffff, 0, "Intel EG20T Serial Port 3", 0x10 },
 { 0x9710, 0x9820, 0x1000, 1, "NetMos NM9820 Serial Port", 0x10 },
 { 0x9710, 0x9835, 0x1000, 1, "NetMos NM9835 Serial Port", 0x10 },
 { 0x9710, 0x9865, 0xa000, 0x1000, "NetMos NM9865 Serial Port", 0x10 },
diff --git a/sys/dev/uart/uart_cpu_sparc64.c b/sys/dev/uart/uart_cpu_sparc64.c
index 582e919..6cbfbe2 100644
--- a/sys/dev/uart/uart_cpu_sparc64.c
+++ b/sys/dev/uart/uart_cpu_sparc64.c
@@ -71,7 +71,7 @@ uart_cpu_channel(char *dev)
 	if ((aliases = OF_finddevice("/aliases")) != -1)
 		(void)OF_getprop(aliases, dev, alias, sizeof(alias));
 	len = strlen(alias);
-	if ((p = rindex(alias, ':')) == NULL)
+	if ((p = strrchr(alias, ':')) == NULL)
 		return (0);
 	p++;
 	if (p - alias == len - 1 && (*p == 'a' || *p == 'b'))
diff --git a/sys/dev/uart/uart_subr.c b/sys/dev/uart/uart_subr.c
index 6b32c24..5a3f16f 100644
--- a/sys/dev/uart/uart_subr.c
+++ b/sys/dev/uart/uart_subr.c
@@ -56,13 +56,13 @@ static struct uart_class *uart_classes[] = {
 static size_t uart_nclasses = sizeof(uart_classes) / sizeof(uart_classes[0]);
 
 static bus_addr_t
-uart_parse_addr(__const char **p)
+uart_parse_addr(const char **p)
 {
 	return (strtoul(*p, (char**)(uintptr_t)p, 0));
 }
 
 static struct uart_class *
-uart_parse_class(struct uart_class *class, __const char **p)
+uart_parse_class(struct uart_class *class, const char **p)
 {
 	struct uart_class *uc;
 	const char *nm;
@@ -84,13 +84,13 @@ uart_parse_class(struct uart_class *class, __const char **p)
 }
 
 static long
-uart_parse_long(__const char **p)
+uart_parse_long(const char **p)
 {
 	return (strtol(*p, (char**)(uintptr_t)p, 0));
 }
 
 static int
-uart_parse_parity(__const char **p)
+uart_parse_parity(const char **p)
 {
 	if (!strncmp(*p, "even", 4)) {
 		*p += 4;
@@ -116,7 +116,7 @@ uart_parse_parity(__const char **p)
 }
 
 static int
-uart_parse_tag(__const char **p)
+uart_parse_tag(const char **p)
 {
 	int tag;
 
@@ -192,7 +192,7 @@ out:
 int
 uart_getenv(int devtype, struct uart_devinfo *di, struct uart_class *class)
 {
-	__const char *spec;
+	const char *spec;
 	bus_addr_t addr = ~0U;
 	int error;
 
diff --git a/sys/dev/uart/uart_tty.c b/sys/dev/uart/uart_tty.c
index 2170108..97ee08d 100644
--- a/sys/dev/uart/uart_tty.c
+++ b/sys/dev/uart/uart_tty.c
@@ -54,6 +54,8 @@ static cn_init_t uart_cninit;
 static cn_term_t uart_cnterm;
 static cn_getc_t uart_cngetc;
 static cn_putc_t uart_cnputc;
+static cn_grab_t uart_cngrab;
+static cn_ungrab_t uart_cnungrab;
 
 CONSOLE_DRIVER(uart);
 
@@ -108,6 +110,16 @@ uart_cnterm(struct consdev *cp)
 }
 
 static void
+uart_cngrab(struct consdev *cp)
+{
+}
+
+static void
+uart_cnungrab(struct consdev *cp)
+{
+}
+
+static void
 uart_cnputc(struct consdev *cp, int c)
 {
 
diff --git a/sys/dev/ubsec/ubsec.c b/sys/dev/ubsec/ubsec.c
index 49e9dad..eda14c0 100644
--- a/sys/dev/ubsec/ubsec.c
+++ b/sys/dev/ubsec/ubsec.c
@@ -123,17 +123,13 @@ static device_method_t ubsec_methods[] = {
 	DEVMETHOD(device_resume,	ubsec_resume),
 	DEVMETHOD(device_shutdown,	ubsec_shutdown),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* crypto device methods */
 	DEVMETHOD(cryptodev_newsession,	ubsec_newsession),
 	DEVMETHOD(cryptodev_freesession,ubsec_freesession),
 	DEVMETHOD(cryptodev_process,	ubsec_process),
 	DEVMETHOD(cryptodev_kprocess,	ubsec_kprocess),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 static driver_t ubsec_driver = {
 	"ubsec",
diff --git a/sys/dev/usb/controller/at91dci.c b/sys/dev/usb/controller/at91dci.c
index f831115..d325812 100644
--- a/sys/dev/usb/controller/at91dci.c
+++ b/sys/dev/usb/controller/at91dci.c
@@ -1461,16 +1461,16 @@ at91dci_uninit(struct at91dci_softc *sc)
 	USB_BUS_UNLOCK(&sc->sc_bus);
 }
 
-void
+static void
 at91dci_suspend(struct at91dci_softc *sc)
 {
-	return;
+	/* TODO */
 }
 
-void
+static void
 at91dci_resume(struct at91dci_softc *sc)
 {
-	return;
+	/* TODO */
 }
 
 static void
@@ -2306,6 +2306,26 @@ at91dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
 	}
 }
 
+static void
+at91dci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
+{
+	struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus);
+
+	switch (state) {
+	case USB_HW_POWER_SUSPEND:
+		at91dci_suspend(sc);
+		break;
+	case USB_HW_POWER_SHUTDOWN:
+		at91dci_uninit(sc);
+		break;
+	case USB_HW_POWER_RESUME:
+		at91dci_resume(sc);
+		break;
+	default:
+		break;
+	}
+}
+
 struct usb_bus_methods at91dci_bus_methods =
 {
 	.endpoint_init = &at91dci_ep_init,
@@ -2316,4 +2336,5 @@ struct usb_bus_methods at91dci_bus_methods =
 	.clear_stall = &at91dci_clear_stall,
 	.roothub_exec = &at91dci_roothub_exec,
 	.xfer_poll = &at91dci_do_poll,
+	.set_hw_power_sleep = &at91dci_set_hw_power_sleep,
 };
diff --git a/sys/dev/usb/controller/at91dci.h b/sys/dev/usb/controller/at91dci.h
index a1603aa..b079eb5 100644
--- a/sys/dev/usb/controller/at91dci.h
+++ b/sys/dev/usb/controller/at91dci.h
@@ -235,8 +235,6 @@ struct at91dci_softc {
 
 usb_error_t at91dci_init(struct at91dci_softc *sc);
 void	at91dci_uninit(struct at91dci_softc *sc);
-void	at91dci_suspend(struct at91dci_softc *sc);
-void	at91dci_resume(struct at91dci_softc *sc);
 void	at91dci_interrupt(struct at91dci_softc *sc);
 void	at91dci_vbus_interrupt(struct at91dci_softc *sc, uint8_t is_on);
 
diff --git a/sys/dev/usb/controller/at91dci_atmelarm.c b/sys/dev/usb/controller/at91dci_atmelarm.c
index ee3feb8..da9ba36 100644
--- a/sys/dev/usb/controller/at91dci_atmelarm.c
+++ b/sys/dev/usb/controller/at91dci_atmelarm.c
@@ -77,7 +77,6 @@ __FBSDID("$FreeBSD$");
 static device_probe_t at91_udp_probe;
 static device_attach_t at91_udp_attach;
 static device_detach_t at91_udp_detach;
-static device_shutdown_t at91_udp_shutdown;
 
 struct at91_udp_softc {
 	struct at91dci_softc sc_dci;	/* must be first */
@@ -271,7 +270,7 @@ at91_udp_detach(device_t dev)
 		device_delete_child(dev, bdev);
 	}
 	/* during module unload there are lots of children leftover */
-	device_delete_all_children(dev);
+	device_delete_children(dev);
 
 	/* disable Transceiver */
 	AT91_UDP_WRITE_4(&sc->sc_dci, AT91_UDP_TXVC, AT91_UDP_TXVC_DIS);
@@ -324,38 +323,22 @@ at91_udp_detach(device_t dev)
 	return (0);
 }
 
-static int
-at91_udp_shutdown(device_t dev)
-{
-	struct at91_udp_softc *sc = device_get_softc(dev);
-	int err;
-
-	err = bus_generic_shutdown(dev);
-	if (err)
-		return (err);
-
-	at91dci_uninit(&sc->sc_dci);
-
-	return (0);
-}
-
 static device_method_t at91_udp_methods[] = {
 	/* Device interface */
 	DEVMETHOD(device_probe, at91_udp_probe),
 	DEVMETHOD(device_attach, at91_udp_attach),
 	DEVMETHOD(device_detach, at91_udp_detach),
-	DEVMETHOD(device_shutdown, at91_udp_shutdown),
-
-	/* Bus interface */
-	DEVMETHOD(bus_print_child, bus_generic_print_child),
+	DEVMETHOD(device_suspend, bus_generic_suspend),
+	DEVMETHOD(device_resume, bus_generic_resume),
+	DEVMETHOD(device_shutdown, bus_generic_shutdown),
 
-	{0, 0}
+	DEVMETHOD_END
 };
 
 static driver_t at91_udp_driver = {
-	"at91_udp",
-	at91_udp_methods,
-	sizeof(struct at91_udp_softc),
+	.name = "at91_udp",
+	.methods = at91_udp_methods,
+	.size = sizeof(struct at91_udp_softc),
 };
 
 static devclass_t at91_udp_devclass;
diff --git a/sys/dev/usb/controller/atmegadci.c b/sys/dev/usb/controller/atmegadci.c
index ad53fc3..7db3bdb 100644
--- a/sys/dev/usb/controller/atmegadci.c
+++ b/sys/dev/usb/controller/atmegadci.c
@@ -1352,16 +1352,16 @@ atmegadci_uninit(struct atmegadci_softc *sc)
 	USB_BUS_UNLOCK(&sc->sc_bus);
 }
 
-void
+static void
 atmegadci_suspend(struct atmegadci_softc *sc)
 {
-	return;
+	/* TODO */
 }
 
-void
+static void
 atmegadci_resume(struct atmegadci_softc *sc)
 {
-	return;
+	/* TODO */
 }
 
 static void
@@ -2126,6 +2126,26 @@ atmegadci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc
 	}
 }
 
+static void
+atmegadci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
+{
+	struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus);
+
+	switch (state) {
+	case USB_HW_POWER_SUSPEND:
+		atmegadci_suspend(sc);
+		break;
+	case USB_HW_POWER_SHUTDOWN:
+		atmegadci_uninit(sc);
+		break;
+	case USB_HW_POWER_RESUME:
+		atmegadci_resume(sc);
+		break;
+	default:
+		break;
+	}
+}
+
 struct usb_bus_methods atmegadci_bus_methods =
 {
 	.endpoint_init = &atmegadci_ep_init,
@@ -2136,4 +2156,5 @@ struct usb_bus_methods atmegadci_bus_methods =
 	.clear_stall = &atmegadci_clear_stall,
 	.roothub_exec = &atmegadci_roothub_exec,
 	.xfer_poll = &atmegadci_do_poll,
+	.set_hw_power_sleep = &atmegadci_set_hw_power_sleep,
 };
diff --git a/sys/dev/usb/controller/atmegadci.h b/sys/dev/usb/controller/atmegadci.h
index 68613af..91ba030 100644
--- a/sys/dev/usb/controller/atmegadci.h
+++ b/sys/dev/usb/controller/atmegadci.h
@@ -278,8 +278,6 @@ struct atmegadci_softc {
 
 usb_error_t atmegadci_init(struct atmegadci_softc *sc);
 void	atmegadci_uninit(struct atmegadci_softc *sc);
-void	atmegadci_suspend(struct atmegadci_softc *sc);
-void	atmegadci_resume(struct atmegadci_softc *sc);
 void	atmegadci_interrupt(struct atmegadci_softc *sc);
 
 #endif					/* _ATMEGADCI_H_ */
diff --git a/sys/dev/usb/controller/atmegadci_atmelarm.c b/sys/dev/usb/controller/atmegadci_atmelarm.c
index 8d033909..6c380b6 100644
--- a/sys/dev/usb/controller/atmegadci_atmelarm.c
+++ b/sys/dev/usb/controller/atmegadci_atmelarm.c
@@ -62,7 +62,6 @@ __FBSDID("$FreeBSD$");
 static device_probe_t atmegadci_probe;
 static device_attach_t atmegadci_attach;
 static device_detach_t atmegadci_detach;
-static device_shutdown_t atmegadci_shutdown;
 
 struct atmegadci_super_softc {
 	struct atmegadci_softc sc_otg;	/* must be first */
@@ -164,7 +163,7 @@ atmegadci_detach(device_t dev)
 		device_delete_child(dev, bdev);
 	}
 	/* during module unload there are lots of children leftover */
-	device_delete_all_children(dev);
+	device_delete_children(dev);
 
 	if (sc->sc_otg.sc_irq_res && sc->sc_otg.sc_intr_hdl) {
 		/*
@@ -193,38 +192,22 @@ atmegadci_detach(device_t dev)
 	return (0);
 }
 
-static int
-atmegadci_shutdown(device_t dev)
-{
-	struct atmegadci_super_softc *sc = device_get_softc(dev);
-	int err;
-
-	err = bus_generic_shutdown(dev);
-	if (err)
-		return (err);
-
-	atmegadci_uninit(&sc->sc_otg);
-
-	return (0);
-}
-
 static device_method_t atmegadci_methods[] = {
 	/* Device interface */
 	DEVMETHOD(device_probe, atmegadci_probe),
 	DEVMETHOD(device_attach, atmegadci_attach),
 	DEVMETHOD(device_detach, atmegadci_detach),
-	DEVMETHOD(device_shutdown, atmegadci_shutdown),
-
-	/* Bus interface */
-	DEVMETHOD(bus_print_child, bus_generic_print_child),
+	DEVMETHOD(device_suspend, bus_generic_suspend),
+	DEVMETHOD(device_resume, bus_generic_resume),
+	DEVMETHOD(device_shutdown, bus_generic_shutdown),
 
-	{0, 0}
+	DEVMETHOD_END
 };
 
 static driver_t atmegadci_driver = {
-	"atmegadci",
-	atmegadci_methods,
-	sizeof(struct atmegadci_super_softc),
+	.name = "atmegadci",
+	.methods = atmegadci_methods,
+	.size = sizeof(struct atmegadci_super_softc),
 };
 
 static devclass_t atmegadci_devclass;
diff --git a/sys/dev/usb/controller/avr32dci.c b/sys/dev/usb/controller/avr32dci.c
index 26785a3..9494c30 100644
--- a/sys/dev/usb/controller/avr32dci.c
+++ b/sys/dev/usb/controller/avr32dci.c
@@ -265,7 +265,7 @@ avr32dci_set_address(struct avr32dci_softc *sc, uint8_t addr)
 {
 	DPRINTFN(5, "addr=%d\n", addr);
 
-	avr32dci_mod_ctrl(sc, AVR32_UDADDR_ADDEN | addr, 0);
+	avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_FADDR_EN | addr, 0);
 }
 
 static uint8_t
@@ -501,7 +501,7 @@ repeat:
 	}
 
 	/* allocate FIFO bank */
-	AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_TX_BK_RDY);
+	AVR32_WRITE_4(sc, AVR32_EPTCTL(td->ep_no), AVR32_EPTCTL_TX_PK_RDY);
 
 	/* check remainder */
 	if (td->remainder == 0) {
@@ -754,7 +754,7 @@ avr32dci_setup_standard_chain(struct usb_xfer *xfer)
 	uint8_t need_sync;
 
 	DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
-	    xfer->address, UE_GET_ADDR(xfer->endpoint),
+	    xfer->address, UE_GET_ADDR(xfer->endpointno),
 	    xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
 
 	temp.max_frame_size = xfer->max_frame_size;
@@ -773,7 +773,7 @@ avr32dci_setup_standard_chain(struct usb_xfer *xfer)
 	temp.did_stall = !xfer->flags_int.control_stall;
 
 	sc = AVR32_BUS2SC(xfer->xroot->bus);
-	ep_no = (xfer->endpoint & UE_ADDR);
+	ep_no = (xfer->endpointno & UE_ADDR);
 
 	/* check if we should prepend a setup message */
 
@@ -798,7 +798,7 @@ avr32dci_setup_standard_chain(struct usb_xfer *xfer)
 	}
 
 	if (x != xfer->nframes) {
-		if (xfer->endpoint & UE_DIR_IN) {
+		if (xfer->endpointno & UE_DIR_IN) {
 			temp.func = &avr32dci_data_tx;
 			need_sync = 1;
 		} else {
@@ -872,7 +872,7 @@ avr32dci_setup_standard_chain(struct usb_xfer *xfer)
 			 * Send a DATA1 message and invert the current
 			 * endpoint direction.
 			 */
-			if (xfer->endpoint & UE_DIR_IN) {
+			if (xfer->endpointno & UE_DIR_IN) {
 				temp.func = &avr32dci_data_rx;
 				need_sync = 0;
 			} else {
@@ -913,7 +913,8 @@ avr32dci_start_standard_chain(struct usb_xfer *xfer)
 
 	/* poll one time - will turn on interrupts */
 	if (avr32dci_xfer_do_fifo(xfer)) {
-		uint8_t ep_no = xfer->endpoint & UE_ADDR_MASK;
+		uint8_t ep_no = xfer->endpointno & UE_ADDR;
+		struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus);
 
 		avr32dci_mod_ien(sc, AVR32_INT_EPT_INT(ep_no), 0);
 
@@ -1012,7 +1013,7 @@ avr32dci_standard_done(struct usb_xfer *xfer)
 	usb_error_t err = 0;
 
 	DPRINTFN(13, "xfer=%p pipe=%p transfer done\n",
-	    xfer, xfer->pipe);
+	    xfer, xfer->endpoint);
 
 	/* reset scanner */
 
@@ -1064,10 +1065,10 @@ avr32dci_device_done(struct usb_xfer *xfer, usb_error_t error)
 	USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
 
 	DPRINTFN(9, "xfer=%p, pipe=%p, error=%d\n",
-	    xfer, xfer->pipe, error);
+	    xfer, xfer->endpoint, error);
 
 	if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
-		ep_no = (xfer->endpoint & UE_ADDR);
+		ep_no = (xfer->endpointno & UE_ADDR);
 
 		/* disable endpoint interrupt */
 		avr32dci_mod_ien(sc, 0, AVR32_INT_EPT_INT(ep_no));
@@ -1080,7 +1081,7 @@ avr32dci_device_done(struct usb_xfer *xfer, usb_error_t error)
 
 static void
 avr32dci_set_stall(struct usb_device *udev, struct usb_xfer *xfer,
-    struct usb_endpoint *ep, uint8_t *did_stall)
+    struct usb_endpoint *pipe, uint8_t *did_stall)
 {
 	struct avr32dci_softc *sc;
 	uint8_t ep_no;
@@ -1166,7 +1167,7 @@ avr32dci_clear_stall_sub(struct avr32dci_softc *sc, uint8_t ep_no,
 }
 
 static void
-avr32dci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
+avr32dci_clear_stall(struct usb_device *udev, struct usb_endpoint *pipe)
 {
 	struct avr32dci_softc *sc;
 	struct usb_endpoint_descriptor *ed;
@@ -1226,8 +1227,7 @@ avr32dci_init(struct avr32dci_softc *sc)
 	    AVR32_INT_ENDRESET, 0);
 
 	/* reset all endpoints */
-/**INDENT** Warning@1207: Extra ) */
-	AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1));
+	AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1);
 
 	/* disable all endpoints */
 	for (n = 0; n != AVR32_EP_MAX; n++) {
@@ -1262,8 +1262,7 @@ avr32dci_uninit(struct avr32dci_softc *sc)
 	avr32dci_mod_ien(sc, 0, 0xFFFFFFFF);
 
 	/* reset all endpoints */
-/**INDENT** Warning@1242: Extra ) */
-	AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1));
+	AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1);
 
 	/* disable all endpoints */
 	for (n = 0; n != AVR32_EP_MAX; n++) {
@@ -1284,16 +1283,16 @@ avr32dci_uninit(struct avr32dci_softc *sc)
 	USB_BUS_UNLOCK(&sc->sc_bus);
 }
 
-void
+static void
 avr32dci_suspend(struct avr32dci_softc *sc)
 {
-	return;
+	/* TODO */
 }
 
-void
+static void
 avr32dci_resume(struct avr32dci_softc *sc)
 {
-	return;
+	/* TODO */
 }
 
 static void
@@ -1369,10 +1368,10 @@ avr32dci_device_isoc_fs_enter(struct usb_xfer *xfer)
 	uint8_t ep_no;
 
 	DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
-	    xfer, xfer->pipe->isoc_next, xfer->nframes);
+	    xfer, xfer->endpoint->isoc_next, xfer->nframes);
 
 	/* get the current frame index */
-	ep_no = xfer->endpoint & UE_ADDR_MASK;
+	ep_no = xfer->endpointno & UE_ADDR;
 	nframes = (AVR32_READ_4(sc, AVR32_FNUM) / 8);
 
 	nframes &= AVR32_FRAME_MASK;
@@ -1381,9 +1380,9 @@ avr32dci_device_isoc_fs_enter(struct usb_xfer *xfer)
 	 * check if the frame index is within the window where the frames
 	 * will be inserted
 	 */
-	temp = (nframes - xfer->pipe->isoc_next) & AVR32_FRAME_MASK;
+	temp = (nframes - xfer->endpoint->isoc_next) & AVR32_FRAME_MASK;
 
-	if ((xfer->pipe->is_synced == 0) ||
+	if ((xfer->endpoint->is_synced == 0) ||
 	    (temp < xfer->nframes)) {
 		/*
 		 * If there is data underflow or the pipe queue is
@@ -1391,15 +1390,15 @@ avr32dci_device_isoc_fs_enter(struct usb_xfer *xfer)
 		 * of the current frame position. Else two isochronous
 		 * transfers might overlap.
 		 */
-		xfer->pipe->isoc_next = (nframes + 3) & AVR32_FRAME_MASK;
-		xfer->pipe->is_synced = 1;
-		DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next);
+		xfer->endpoint->isoc_next = (nframes + 3) & AVR32_FRAME_MASK;
+		xfer->endpoint->is_synced = 1;
+		DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
 	}
 	/*
 	 * compute how many milliseconds the insertion is ahead of the
 	 * current frame position:
 	 */
-	temp = (xfer->pipe->isoc_next - nframes) & AVR32_FRAME_MASK;
+	temp = (xfer->endpoint->isoc_next - nframes) & AVR32_FRAME_MASK;
 
 	/*
 	 * pre-compute when the isochronous transfer will be finished:
@@ -1409,7 +1408,7 @@ avr32dci_device_isoc_fs_enter(struct usb_xfer *xfer)
 	    xfer->nframes;
 
 	/* compute frame number for next insertion */
-	xfer->pipe->isoc_next += xfer->nframes;
+	xfer->endpoint->isoc_next += xfer->nframes;
 
 	/* setup TDs */
 	avr32dci_setup_standard_chain(xfer);
@@ -1832,7 +1831,7 @@ tr_handle_clear_port_feature:
 		AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(0), AVR32_EPTSTA_FRCESTALL);
 
 		/* configure */
-		AVR32_WRITE_4(sc, AVR32_EPTCFG(0), AVR32_EPTCFG_TYPE_CONTROL |
+		AVR32_WRITE_4(sc, AVR32_EPTCFG(0), AVR32_EPTCFG_TYPE_CTRL |
 		    AVR32_EPTCFG_NBANK(1) | AVR32_EPTCFG_EPSIZE(6));
 
 		temp = AVR32_READ_4(sc, AVR32_EPTCFG(0));
@@ -1974,7 +1973,7 @@ avr32dci_xfer_setup(struct usb_setup_params *parm)
 	/*
 	 * compute maximum number of TDs
 	 */
-	if ((xfer->pipe->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) {
+	if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) {
 
 		ntd = xfer->nframes + 1 /* STATUS */ + 1	/* SYNC 1 */
 		    + 1 /* SYNC 2 */ ;
@@ -1997,7 +1996,7 @@ avr32dci_xfer_setup(struct usb_setup_params *parm)
 	/*
 	 * get profile stuff
 	 */
-	ep_no = xfer->endpoint & UE_ADDR;
+	ep_no = xfer->endpointno & UE_ADDR;
 	avr32dci_get_hw_ep_profile(parm->udev, &pf, ep_no);
 
 	if (pf == NULL) {
@@ -2045,7 +2044,7 @@ avr32dci_xfer_unsetup(struct usb_xfer *xfer)
 
 static void
 avr32dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
-    struct usb_endpoint *ep)
+    struct usb_endpoint *pipe)
 {
 	struct avr32dci_softc *sc = AVR32_BUS2SC(udev->bus);
 
@@ -2072,6 +2071,26 @@ avr32dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
 	}
 }
 
+static void
+avr32dci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
+{
+	struct avr32dci_softc *sc = AVR32_BUS2SC(bus);
+
+	switch (state) {
+	case USB_HW_POWER_SUSPEND:
+		avr32dci_suspend(sc);
+		break;
+	case USB_HW_POWER_SHUTDOWN:
+		avr32dci_uninit(sc);
+		break;
+	case USB_HW_POWER_RESUME:
+		avr32dci_resume(sc);
+		break;
+	default:
+		break;
+	}
+}
+
 struct usb_bus_methods avr32dci_bus_methods =
 {
 	.endpoint_init = &avr32dci_ep_init,
@@ -2082,4 +2101,5 @@ struct usb_bus_methods avr32dci_bus_methods =
 	.clear_stall = &avr32dci_clear_stall,
 	.roothub_exec = &avr32dci_roothub_exec,
 	.xfer_poll = &avr32dci_do_poll,
+	.set_hw_power_sleep = &avr32dci_set_hw_power_sleep,
 };
diff --git a/sys/dev/usb/controller/avr32dci.h b/sys/dev/usb/controller/avr32dci.h
index 6672fa7..2d80344 100644
--- a/sys/dev/usb/controller/avr32dci.h
+++ b/sys/dev/usb/controller/avr32dci.h
@@ -166,6 +166,7 @@ struct avr32dci_td {
 	uint32_t offset;
 	uint32_t remainder;
 	uint16_t max_packet_size;
+	uint8_t bank_shift;
 	uint8_t	error:1;
 	uint8_t	alt_next:1;
 	uint8_t	short_pkt:1;
@@ -246,8 +247,6 @@ struct avr32dci_softc {
 
 usb_error_t avr32dci_init(struct avr32dci_softc *sc);
 void	avr32dci_uninit(struct avr32dci_softc *sc);
-void	avr32dci_suspend(struct avr32dci_softc *sc);
-void	avr32dci_resume(struct avr32dci_softc *sc);
 void	avr32dci_interrupt(struct avr32dci_softc *sc);
 void	avr32dci_vbus_interrupt(struct avr32dci_softc *sc, uint8_t is_on);
 
diff --git a/sys/dev/usb/controller/ehci.c b/sys/dev/usb/controller/ehci.c
index 7e682f4..f59c801 100644
--- a/sys/dev/usb/controller/ehci.c
+++ b/sys/dev/usb/controller/ehci.c
@@ -188,7 +188,7 @@ ehci_reset(ehci_softc_t *sc)
 
 	EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
 	for (i = 0; i < 100; i++) {
-		usb_pause_mtx(NULL, hz / 1000);
+		usb_pause_mtx(NULL, hz / 128);
 		hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
 		if (!hcr) {
 			if (sc->sc_flags & (EHCI_SCFLG_SETMODE | EHCI_SCFLG_BIGEMMIO)) {
@@ -212,7 +212,7 @@ ehci_reset(ehci_softc_t *sc)
 			return (0);
 		}
 	}
-	device_printf(sc->sc_bus.bdev, "reset timeout\n");
+	device_printf(sc->sc_bus.bdev, "Reset timeout\n");
 	return (USB_ERR_IOERROR);
 }
 
@@ -224,7 +224,7 @@ ehci_hcreset(ehci_softc_t *sc)
 
 	EOWRITE4(sc, EHCI_USBCMD, 0);	/* Halt controller */
 	for (i = 0; i < 100; i++) {
-		usb_pause_mtx(NULL, hz / 1000);
+		usb_pause_mtx(NULL, hz / 128);
 		hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
 		if (hcr)
 			break;
@@ -237,7 +237,60 @@ ehci_hcreset(ehci_softc_t *sc)
                  */
 		device_printf(sc->sc_bus.bdev, "stop timeout\n");
 
-	return ehci_reset(sc);
+	return (ehci_reset(sc));
+}
+
+static int
+ehci_init_sub(struct ehci_softc *sc)
+{
+	struct usb_page_search buf_res;
+	uint32_t cparams;
+  	uint32_t hcr;
+	uint8_t i;
+
+	cparams = EREAD4(sc, EHCI_HCCPARAMS);
+
+	DPRINTF("cparams=0x%x\n", cparams);
+
+	if (EHCI_HCC_64BIT(cparams)) {
+		DPRINTF("HCC uses 64-bit structures\n");
+
+		/* MUST clear segment register if 64 bit capable */
+		EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
+	}
+
+	usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
+	EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr);
+
+	usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
+	EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH);
+
+	/* enable interrupts */
+	EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
+
+	/* turn on controller */
+	EOWRITE4(sc, EHCI_USBCMD,
+	    EHCI_CMD_ITC_1 |		/* 1 microframes interrupt delay */
+	    (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
+	    EHCI_CMD_ASE |
+	    EHCI_CMD_PSE |
+	    EHCI_CMD_RS);
+
+	/* Take over port ownership */
+	EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
+
+	for (i = 0; i < 100; i++) {
+		usb_pause_mtx(NULL, hz / 128);
+		hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
+		if (!hcr) {
+			break;
+		}
+	}
+	if (hcr) {
+		device_printf(sc->sc_bus.bdev, "Run timeout\n");
+		return (USB_ERR_IOERROR);
+	}
+	return (USB_ERR_NORMAL_COMPLETION);
 }
 
 usb_error_t
@@ -246,8 +299,6 @@ ehci_init(ehci_softc_t *sc)
 	struct usb_page_search buf_res;
 	uint32_t version;
 	uint32_t sparams;
-	uint32_t cparams;
-	uint32_t hcr;
 	uint16_t i;
 	uint16_t x;
 	uint16_t y;
@@ -279,15 +330,6 @@ ehci_init(ehci_softc_t *sc)
 	DPRINTF("sparams=0x%x\n", sparams);
 
 	sc->sc_noport = EHCI_HCS_N_PORTS(sparams);
-	cparams = EREAD4(sc, EHCI_HCCPARAMS);
-	DPRINTF("cparams=0x%x\n", cparams);
-
-	if (EHCI_HCC_64BIT(cparams)) {
-		DPRINTF("HCC uses 64-bit structures\n");
-
-		/* MUST clear segment register if 64 bit capable */
-		EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
-	}
 	sc->sc_bus.usbrev = USB_REV_2_0;
 
 	/* Reset the controller */
@@ -464,9 +506,6 @@ ehci_init(ehci_softc_t *sc)
 			    [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self;
 		}
 	}
-	/* setup sync list pointer */
-	EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr);
-
 	usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
 
 	if (1) {
@@ -511,35 +550,8 @@ ehci_init(ehci_softc_t *sc)
 	}
 #endif
 
-	/* setup async list pointer */
-	EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH);
-
-
-	/* enable interrupts */
-	EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
-
-	/* turn on controller */
-	EOWRITE4(sc, EHCI_USBCMD,
-	    EHCI_CMD_ITC_1 |		/* 1 microframes interrupt delay */
-	    (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
-	    EHCI_CMD_ASE |
-	    EHCI_CMD_PSE |
-	    EHCI_CMD_RS);
-
-	/* Take over port ownership */
-	EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
-
-	for (i = 0; i < 100; i++) {
-		usb_pause_mtx(NULL, hz / 1000);
-		hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
-		if (!hcr) {
-			break;
-		}
-	}
-	if (hcr) {
-		device_printf(sc->sc_bus.bdev, "run timeout\n");
-		return (USB_ERR_IOERROR);
-	}
+	/* finial setup */
+ 	err = ehci_init_sub(sc);
 
 	if (!err) {
 		/* catch any lost interrupts */
@@ -573,137 +585,28 @@ ehci_detach(ehci_softc_t *sc)
 	usb_callout_drain(&sc->sc_tmo_poll);
 }
 
-void
+static void
 ehci_suspend(ehci_softc_t *sc)
 {
-	uint32_t cmd;
-	uint32_t hcr;
-	uint8_t i;
-
-	USB_BUS_LOCK(&sc->sc_bus);
-
-	for (i = 1; i <= sc->sc_noport; i++) {
-		cmd = EOREAD4(sc, EHCI_PORTSC(i));
-		if (((cmd & EHCI_PS_PO) == 0) &&
-		    ((cmd & EHCI_PS_PE) == EHCI_PS_PE)) {
-			EOWRITE4(sc, EHCI_PORTSC(i),
-			    cmd | EHCI_PS_SUSP);
-		}
-	}
-
-	sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD);
-
-	cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
-	EOWRITE4(sc, EHCI_USBCMD, cmd);
-
-	for (i = 0; i < 100; i++) {
-		hcr = EOREAD4(sc, EHCI_USBSTS) &
-		    (EHCI_STS_ASS | EHCI_STS_PSS);
-
-		if (hcr == 0) {
-			break;
-		}
-		usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
-	}
-
-	if (hcr != 0) {
-		device_printf(sc->sc_bus.bdev, "reset timeout\n");
-	}
-	cmd &= ~EHCI_CMD_RS;
-	EOWRITE4(sc, EHCI_USBCMD, cmd);
-
-	for (i = 0; i < 100; i++) {
-		hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
-		if (hcr == EHCI_STS_HCH) {
-			break;
-		}
-		usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
-	}
+	DPRINTF("stopping the HC\n");
 
-	if (hcr != EHCI_STS_HCH) {
-		device_printf(sc->sc_bus.bdev,
-		    "config timeout\n");
-	}
-	USB_BUS_UNLOCK(&sc->sc_bus);
+	/* reset HC */
+	ehci_hcreset(sc);
 }
 
-void
+static void
 ehci_resume(ehci_softc_t *sc)
 {
-	struct usb_page_search buf_res;
-	uint32_t cmd;
-	uint32_t hcr;
-	uint8_t i;
-
-	USB_BUS_LOCK(&sc->sc_bus);
-
-	/* restore things in case the bios doesn't */
-	EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
-
-	usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
-	EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr);
+	/* reset HC */
+	ehci_hcreset(sc);
 
-	usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
-	EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH);
-
-	EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
-
-	hcr = 0;
-	for (i = 1; i <= sc->sc_noport; i++) {
-		cmd = EOREAD4(sc, EHCI_PORTSC(i));
-		if (((cmd & EHCI_PS_PO) == 0) &&
-		    ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) {
-			EOWRITE4(sc, EHCI_PORTSC(i),
-			    cmd | EHCI_PS_FPR);
-			hcr = 1;
-		}
-	}
-
-	if (hcr) {
-		usb_pause_mtx(&sc->sc_bus.bus_mtx,
-		    USB_MS_TO_TICKS(USB_RESUME_WAIT));
-
-		for (i = 1; i <= sc->sc_noport; i++) {
-			cmd = EOREAD4(sc, EHCI_PORTSC(i));
-			if (((cmd & EHCI_PS_PO) == 0) &&
-			    ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) {
-				EOWRITE4(sc, EHCI_PORTSC(i),
-				    cmd & ~EHCI_PS_FPR);
-			}
-		}
-	}
-	EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd);
-
-	for (i = 0; i < 100; i++) {
-		hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
-		if (hcr != EHCI_STS_HCH) {
-			break;
-		}
-		usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
-	}
-	if (hcr == EHCI_STS_HCH) {
-		device_printf(sc->sc_bus.bdev, "config timeout\n");
-	}
-
-	USB_BUS_UNLOCK(&sc->sc_bus);
-
-	usb_pause_mtx(NULL,
-	    USB_MS_TO_TICKS(USB_RESUME_WAIT));
+	/* setup HC */
+	ehci_init_sub(sc);
 
 	/* catch any lost interrupts */
 	ehci_do_poll(&sc->sc_bus);
 }
 
-void
-ehci_shutdown(ehci_softc_t *sc)
-{
-	DPRINTF("stopping the HC\n");
-
-	if (ehci_hcreset(sc)) {
-		DPRINTF("reset failed!\n");
-	}
-}
-
 #ifdef USB_DEBUG
 static void
 ehci_dump_regs(ehci_softc_t *sc)
@@ -3908,8 +3811,24 @@ ehci_device_suspend(struct usb_device *udev)
 	}
 
 	USB_BUS_UNLOCK(udev->bus);
+}
 
-	return;
+static void
+ehci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
+{
+	struct ehci_softc *sc = EHCI_BUS2SC(bus);
+
+	switch (state) {
+	case USB_HW_POWER_SUSPEND:
+	case USB_HW_POWER_SHUTDOWN:
+		ehci_suspend(sc);
+		break;
+	case USB_HW_POWER_RESUME:
+		ehci_resume(sc);
+		break;
+	default:
+		break;
+	}
 }
 
 static void
@@ -3955,6 +3874,7 @@ struct usb_bus_methods ehci_bus_methods =
 	.device_resume = ehci_device_resume,
 	.device_suspend = ehci_device_suspend,
 	.set_hw_power = ehci_set_hw_power,
+	.set_hw_power_sleep = ehci_set_hw_power_sleep,
 	.roothub_exec = ehci_roothub_exec,
 	.xfer_poll = ehci_do_poll,
 };
diff --git a/sys/dev/usb/controller/ehci.h b/sys/dev/usb/controller/ehci.h
index a8aa514..b8b6985 100644
--- a/sys/dev/usb/controller/ehci.h
+++ b/sys/dev/usb/controller/ehci.h
@@ -333,8 +333,6 @@ typedef struct ehci_softc {
 
 	uint32_t sc_terminate_self;	/* TD short packet termination pointer */
 	uint32_t sc_eintrs;
-	uint32_t sc_cmd;		/* shadow of cmd register during
-					 * suspend */
 
 	uint16_t sc_intr_stat[EHCI_VIRTUAL_FRAMELIST_COUNT];
 	uint16_t sc_id_vendor;		/* vendor ID for root hub */
@@ -445,9 +443,6 @@ usb_bus_mem_cb_t ehci_iterate_hw_softc;
 usb_error_t ehci_reset(ehci_softc_t *sc);
 usb_error_t ehci_init(ehci_softc_t *sc);
 void	ehci_detach(struct ehci_softc *sc);
-void	ehci_suspend(struct ehci_softc *sc);
-void	ehci_resume(struct ehci_softc *sc);
-void	ehci_shutdown(ehci_softc_t *sc);
 void	ehci_interrupt(ehci_softc_t *sc);
 
 #endif					/* _EHCI_H_ */
diff --git a/sys/dev/usb/controller/ehci_ixp4xx.c b/sys/dev/usb/controller/ehci_ixp4xx.c
index 8ea133f..45113d9 100644
--- a/sys/dev/usb/controller/ehci_ixp4xx.c
+++ b/sys/dev/usb/controller/ehci_ixp4xx.c
@@ -78,9 +78,6 @@ struct ixp_ehci_softc {
 
 static device_attach_t ehci_ixp_attach;
 static device_detach_t ehci_ixp_detach;
-static device_shutdown_t ehci_ixp_shutdown;
-static device_suspend_t ehci_ixp_suspend;
-static device_resume_t ehci_ixp_resume;
 
 static uint8_t ehci_bs_r_1(void *, bus_space_handle_t, bus_size_t);
 static void ehci_bs_w_1(void *, bus_space_handle_t, bus_size_t, u_int8_t);
@@ -90,45 +87,6 @@ static uint32_t ehci_bs_r_4(void *, bus_space_handle_t, bus_size_t);
 static void ehci_bs_w_4(void *, bus_space_handle_t, bus_size_t, uint32_t);
 
 static int
-ehci_ixp_suspend(device_t self)
-{
-	ehci_softc_t *sc = device_get_softc(self);
-	int err;
-
-	err = bus_generic_suspend(self);
-	if (err)
-		return (err);
-	ehci_suspend(sc);
-	return (0);
-}
-
-static int
-ehci_ixp_resume(device_t self)
-{
-	ehci_softc_t *sc = device_get_softc(self);
-
-	ehci_resume(sc);
-
-	bus_generic_resume(self);
-
-	return (0);
-}
-
-static int
-ehci_ixp_shutdown(device_t self)
-{
-	ehci_softc_t *sc = device_get_softc(self);
-	int err;
-
-	err = bus_generic_shutdown(self);
-	if (err)
-		return (err);
-	ehci_shutdown(sc);
-
-	return (0);
-}
-
-static int
 ehci_ixp_probe(device_t self)
 {
 
@@ -257,7 +215,7 @@ ehci_ixp_detach(device_t self)
 		device_delete_child(self, bdev);
 	}
 	/* during module unload there are lots of children leftover */
-	device_delete_all_children(self);
+	device_delete_children(self);
 
  	if (sc->sc_irq_res && sc->sc_intr_hdl) {
 		/*
@@ -335,14 +293,11 @@ static device_method_t ehci_methods[] = {
 	DEVMETHOD(device_probe, ehci_ixp_probe),
 	DEVMETHOD(device_attach, ehci_ixp_attach),
 	DEVMETHOD(device_detach, ehci_ixp_detach),
-	DEVMETHOD(device_suspend, ehci_ixp_suspend),
-	DEVMETHOD(device_resume, ehci_ixp_resume),
-	DEVMETHOD(device_shutdown, ehci_ixp_shutdown),
-
-	/* Bus interface */
-	DEVMETHOD(bus_print_child, bus_generic_print_child),
+	DEVMETHOD(device_suspend, bus_generic_suspend),
+	DEVMETHOD(device_resume, bus_generic_resume),
+	DEVMETHOD(device_shutdown, bus_generic_shutdown),
 
-	{0, 0}
+	DEVMETHOD_END
 };
 
 static driver_t ehci_driver = {
diff --git a/sys/dev/usb/controller/ehci_mv.c b/sys/dev/usb/controller/ehci_mv.c
index bbfb6a7..a47e253 100644
--- a/sys/dev/usb/controller/ehci_mv.c
+++ b/sys/dev/usb/controller/ehci_mv.c
@@ -81,9 +81,6 @@ __FBSDID("$FreeBSD$");
 
 static device_attach_t mv_ehci_attach;
 static device_detach_t mv_ehci_detach;
-static device_shutdown_t mv_ehci_shutdown;
-static device_suspend_t mv_ehci_suspend;
-static device_resume_t mv_ehci_resume;
 
 static int err_intr(void *arg);
 
@@ -103,45 +100,6 @@ static void *ih_err;
 #define	MV_USB_DEVICE_UNDERFLOW (1 << 3)
 
 static int
-mv_ehci_suspend(device_t self)
-{
-	ehci_softc_t *sc = device_get_softc(self);
-	int err;
-
-	err = bus_generic_suspend(self);
-	if (err)
-		return (err);
-	ehci_suspend(sc);
-	return (0);
-}
-
-static int
-mv_ehci_resume(device_t self)
-{
-	ehci_softc_t *sc = device_get_softc(self);
-
-	ehci_resume(sc);
-
-	bus_generic_resume(self);
-
-	return (0);
-}
-
-static int
-mv_ehci_shutdown(device_t self)
-{
-	ehci_softc_t *sc = device_get_softc(self);
-	int err;
-
-	err = bus_generic_shutdown(self);
-	if (err)
-		return (err);
-	ehci_shutdown(sc);
-
-	return (0);
-}
-
-static int
 mv_ehci_probe(device_t self)
 {
 
@@ -289,7 +247,7 @@ mv_ehci_detach(device_t self)
 		device_delete_child(self, bdev);
 	}
 	/* during module unload there are lots of children leftover */
-	device_delete_all_children(self);
+	device_delete_children(self);
 
 	/*
 	 * disable interrupts that might have been switched on in mv_ehci_attach
@@ -372,14 +330,11 @@ static device_method_t ehci_methods[] = {
 	DEVMETHOD(device_probe, mv_ehci_probe),
 	DEVMETHOD(device_attach, mv_ehci_attach),
 	DEVMETHOD(device_detach, mv_ehci_detach),
-	DEVMETHOD(device_suspend, mv_ehci_suspend),
-	DEVMETHOD(device_resume, mv_ehci_resume),
-	DEVMETHOD(device_shutdown, mv_ehci_shutdown),
-
-	/* Bus interface */
-	DEVMETHOD(bus_print_child, bus_generic_print_child),
+	DEVMETHOD(device_suspend, bus_generic_suspend),
+	DEVMETHOD(device_resume, bus_generic_resume),
+	DEVMETHOD(device_shutdown, bus_generic_shutdown),
 
-	{0, 0}
+	DEVMETHOD_END
 };
 
 static driver_t ehci_driver = {
diff --git a/sys/dev/usb/controller/ehci_pci.c b/sys/dev/usb/controller/ehci_pci.c
index 6abb193..e293ec8 100644
--- a/sys/dev/usb/controller/ehci_pci.c
+++ b/sys/dev/usb/controller/ehci_pci.c
@@ -77,6 +77,7 @@ __FBSDID("$FreeBSD$");
 #include <dev/usb/usb_pci.h>
 #include <dev/usb/controller/ehci.h>
 #include <dev/usb/controller/ehcireg.h>
+#include "usb_if.h"
 
 #define	PCI_EHCI_VENDORID_ACERLABS	0x10b9
 #define	PCI_EHCI_VENDORID_AMD		0x1022
@@ -92,54 +93,10 @@ __FBSDID("$FreeBSD$");
 #define	PCI_EHCI_VENDORID_NVIDIA2	0x10DE
 #define	PCI_EHCI_VENDORID_VIA		0x1106
 
-static void ehci_pci_takecontroller(device_t self);
-
 static device_probe_t ehci_pci_probe;
 static device_attach_t ehci_pci_attach;
 static device_detach_t ehci_pci_detach;
-static device_suspend_t ehci_pci_suspend;
-static device_resume_t ehci_pci_resume;
-static device_shutdown_t ehci_pci_shutdown;
-
-static int
-ehci_pci_suspend(device_t self)
-{
-	ehci_softc_t *sc = device_get_softc(self);
-	int err;
-
-	err = bus_generic_suspend(self);
-	if (err)
-		return (err);
-	ehci_suspend(sc);
-	return (0);
-}
-
-static int
-ehci_pci_resume(device_t self)
-{
-	ehci_softc_t *sc = device_get_softc(self);
-
-	ehci_pci_takecontroller(self);
-	ehci_resume(sc);
-
-	bus_generic_resume(self);
-
-	return (0);
-}
-
-static int
-ehci_pci_shutdown(device_t self)
-{
-	ehci_softc_t *sc = device_get_softc(self);
-	int err;
-
-	err = bus_generic_shutdown(self);
-	if (err)
-		return (err);
-	ehci_shutdown(sc);
-
-	return (0);
-}
+static usb_take_controller_t ehci_pci_take_controller;
 
 static const char *
 ehci_pci_match(device_t self)
@@ -418,7 +375,7 @@ ehci_pci_attach(device_t self)
 		sc->sc_intr_hdl = NULL;
 		goto error;
 	}
-	ehci_pci_takecontroller(self);
+	ehci_pci_take_controller(self);
 
 	/* Undocumented quirks taken from Linux */
 
@@ -498,7 +455,7 @@ ehci_pci_detach(device_t self)
 		device_delete_child(self, bdev);
 	}
 	/* during module unload there are lots of children leftover */
-	device_delete_all_children(self);
+	device_delete_children(self);
 
 	pci_disable_busmaster(self);
 
@@ -530,8 +487,8 @@ ehci_pci_detach(device_t self)
 	return (0);
 }
 
-static void
-ehci_pci_takecontroller(device_t self)
+static int
+ehci_pci_take_controller(device_t self)
 {
 	ehci_softc_t *sc = device_get_softc(self);
 	uint32_t cparams;
@@ -573,24 +530,25 @@ ehci_pci_takecontroller(device_t self)
 			usb_pause_mtx(NULL, hz / 100);	/* wait 10ms */
 		}
 	}
+	return (0);
 }
 
-static driver_t ehci_driver =
-{
+static device_method_t ehci_pci_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe, ehci_pci_probe),
+	DEVMETHOD(device_attach, ehci_pci_attach),
+	DEVMETHOD(device_detach, ehci_pci_detach),
+	DEVMETHOD(device_suspend, bus_generic_suspend),
+	DEVMETHOD(device_resume, bus_generic_resume),
+	DEVMETHOD(device_shutdown, bus_generic_shutdown),
+	DEVMETHOD(usb_take_controller, ehci_pci_take_controller),
+
+	DEVMETHOD_END
+};
+
+static driver_t ehci_driver = {
 	.name = "ehci",
-	.methods = (device_method_t[]){
-		/* device interface */
-		DEVMETHOD(device_probe, ehci_pci_probe),
-		DEVMETHOD(device_attach, ehci_pci_attach),
-		DEVMETHOD(device_detach, ehci_pci_detach),
-		DEVMETHOD(device_suspend, ehci_pci_suspend),
-		DEVMETHOD(device_resume, ehci_pci_resume),
-		DEVMETHOD(device_shutdown, ehci_pci_shutdown),
-		/* bus interface */
-		DEVMETHOD(bus_print_child, bus_generic_print_child),
-
-		{0, 0}
-	},
+	.methods = ehci_pci_methods,
 	.size = sizeof(struct ehci_softc),
 };
 
diff --git a/sys/dev/usb/controller/musb_otg.c b/sys/dev/usb/controller/musb_otg.c
index be32b2b..d463052 100644
--- a/sys/dev/usb/controller/musb_otg.c
+++ b/sys/dev/usb/controller/musb_otg.c
@@ -1910,16 +1910,16 @@ musbotg_uninit(struct musbotg_softc *sc)
 	USB_BUS_UNLOCK(&sc->sc_bus);
 }
 
-void
+static void
 musbotg_suspend(struct musbotg_softc *sc)
 {
-	return;
+	/* TODO */
 }
 
-void
+static void
 musbotg_resume(struct musbotg_softc *sc)
 {
-	return;
+	/* TODO */
 }
 
 static void
@@ -2776,6 +2776,26 @@ musbotg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
 	}
 }
 
+static void
+musbotg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
+{
+	struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus);
+
+	switch (state) {
+	case USB_HW_POWER_SUSPEND:
+		musbotg_suspend(sc);
+		break;
+	case USB_HW_POWER_SHUTDOWN:
+		musbotg_uninit(sc);
+		break;
+	case USB_HW_POWER_RESUME:
+		musbotg_resume(sc);
+		break;
+	default:
+		break;
+	}
+}
+
 struct usb_bus_methods musbotg_bus_methods =
 {
 	.endpoint_init = &musbotg_ep_init,
@@ -2786,4 +2806,5 @@ struct usb_bus_methods musbotg_bus_methods =
 	.clear_stall = &musbotg_clear_stall,
 	.roothub_exec = &musbotg_roothub_exec,
 	.xfer_poll = &musbotg_do_poll,
+	.set_hw_power_sleep = &musbotg_set_hw_power_sleep,
 };
diff --git a/sys/dev/usb/controller/musb_otg.h b/sys/dev/usb/controller/musb_otg.h
index e8eafca..3b889a9 100644
--- a/sys/dev/usb/controller/musb_otg.h
+++ b/sys/dev/usb/controller/musb_otg.h
@@ -398,8 +398,6 @@ struct musbotg_softc {
 
 usb_error_t musbotg_init(struct musbotg_softc *sc);
 void	musbotg_uninit(struct musbotg_softc *sc);
-void	musbotg_suspend(struct musbotg_softc *sc);
-void	musbotg_resume(struct musbotg_softc *sc);
 void	musbotg_interrupt(struct musbotg_softc *sc);
 void	musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on);
 
diff --git a/sys/dev/usb/controller/musb_otg_atmelarm.c b/sys/dev/usb/controller/musb_otg_atmelarm.c
index 8a48264..bb3e60a 100644
--- a/sys/dev/usb/controller/musb_otg_atmelarm.c
+++ b/sys/dev/usb/controller/musb_otg_atmelarm.c
@@ -1,4 +1,3 @@
-/* $FreeBSD$ */
 /*-
  * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
  *
@@ -24,6 +23,9 @@
  * SUCH DAMAGE.
  */
 
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
 #include <sys/stdint.h>
 #include <sys/stddef.h>
 #include <sys/param.h>
@@ -60,7 +62,6 @@
 static device_probe_t musbotg_probe;
 static device_attach_t musbotg_attach;
 static device_detach_t musbotg_detach;
-static device_shutdown_t musbotg_shutdown;
 
 struct musbotg_super_softc {
 	struct musbotg_softc sc_otg;	/* must be first */
@@ -187,7 +188,7 @@ musbotg_detach(device_t dev)
 		device_delete_child(dev, bdev);
 	}
 	/* during module unload there are lots of children leftover */
-	device_delete_all_children(dev);
+	device_delete_children(dev);
 
 	if (sc->sc_otg.sc_irq_res && sc->sc_otg.sc_intr_hdl) {
 		/*
@@ -216,38 +217,22 @@ musbotg_detach(device_t dev)
 	return (0);
 }
 
-static int
-musbotg_shutdown(device_t dev)
-{
-	struct musbotg_super_softc *sc = device_get_softc(dev);
-	int err;
-
-	err = bus_generic_shutdown(dev);
-	if (err)
-		return (err);
-
-	musbotg_uninit(&sc->sc_otg);
-
-	return (0);
-}
-
 static device_method_t musbotg_methods[] = {
 	/* Device interface */
 	DEVMETHOD(device_probe, musbotg_probe),
 	DEVMETHOD(device_attach, musbotg_attach),
 	DEVMETHOD(device_detach, musbotg_detach),
-	DEVMETHOD(device_shutdown, musbotg_shutdown),
-
-	/* Bus interface */
-	DEVMETHOD(bus_print_child, bus_generic_print_child),
+	DEVMETHOD(device_suspend, bus_generic_suspend),
+	DEVMETHOD(device_resume, bus_generic_resume),
+	DEVMETHOD(device_shutdown, bus_generic_shutdown),
 
-	{0, 0}
+	DEVMETHOD_END
 };
 
 static driver_t musbotg_driver = {
-	"musbotg",
-	musbotg_methods,
-	sizeof(struct musbotg_super_softc),
+	.name = "musbotg",
+	.methods = musbotg_methods,
+	.size = sizeof(struct musbotg_super_softc),
 };
 
 static devclass_t musbotg_devclass;
diff --git a/sys/dev/usb/controller/ohci.c b/sys/dev/usb/controller/ohci.c
index fa2d607..93c2bb2 100644
--- a/sys/dev/usb/controller/ohci.c
+++ b/sys/dev/usb/controller/ohci.c
@@ -166,7 +166,7 @@ ohci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
 }
 
 static usb_error_t
-ohci_controller_init(ohci_softc_t *sc)
+ohci_controller_init(ohci_softc_t *sc, int do_suspend)
 {
 	struct usb_page_search buf_res;
 	uint32_t i;
@@ -233,6 +233,11 @@ reset:
 	}
 #endif
 
+	if (do_suspend) {
+		OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_SUSPEND);
+		return (USB_ERR_NORMAL_COMPLETION);
+	}
+
 	/* The controller is now in SUSPEND state, we have 2ms to finish. */
 
 	/* set up HC registers */
@@ -415,13 +420,12 @@ ohci_init(ohci_softc_t *sc)
 
 	sc->sc_bus.usbrev = USB_REV_1_0;
 
-	if (ohci_controller_init(sc)) {
+	if (ohci_controller_init(sc, 0) != 0)
 		return (USB_ERR_INVAL);
-	} else {
-		/* catch any lost interrupts */
-		ohci_do_poll(&sc->sc_bus);
-		return (USB_ERR_NORMAL_COMPLETION);
-	}
+
+	/* catch any lost interrupts */
+	ohci_do_poll(&sc->sc_bus);
+	return (USB_ERR_NORMAL_COMPLETION);
 }
 
 /*
@@ -445,75 +449,32 @@ ohci_detach(struct ohci_softc *sc)
 	usb_callout_drain(&sc->sc_tmo_rhsc);
 }
 
-/* NOTE: suspend/resume is called from
- * interrupt context and cannot sleep!
- */
-void
+static void
 ohci_suspend(ohci_softc_t *sc)
 {
-	uint32_t ctl;
-
-	USB_BUS_LOCK(&sc->sc_bus);
+	DPRINTF("\n");
 
 #ifdef USB_DEBUG
-	DPRINTF("\n");
-	if (ohcidebug > 2) {
+	if (ohcidebug > 2)
 		ohci_dumpregs(sc);
-	}
 #endif
 
-	ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK;
-	if (sc->sc_control == 0) {
-		/*
-		 * Preserve register values, in case that APM BIOS
-		 * does not recover them.
-		 */
-		sc->sc_control = ctl;
-		sc->sc_intre = OREAD4(sc, OHCI_INTERRUPT_ENABLE);
-	}
-	ctl |= OHCI_HCFS_SUSPEND;
-	OWRITE4(sc, OHCI_CONTROL, ctl);
-
-	usb_pause_mtx(&sc->sc_bus.bus_mtx,
-	    USB_MS_TO_TICKS(USB_RESUME_WAIT));
-
-	USB_BUS_UNLOCK(&sc->sc_bus);
+	/* reset HC and leave it suspended */
+	ohci_controller_init(sc, 1);
 }
 
-void
+static void
 ohci_resume(ohci_softc_t *sc)
 {
-	uint32_t ctl;
+	DPRINTF("\n");
 
 #ifdef USB_DEBUG
-	DPRINTF("\n");
-	if (ohcidebug > 2) {
+	if (ohcidebug > 2)
 		ohci_dumpregs(sc);
-	}
 #endif
-	/* some broken BIOSes never initialize the Controller chip */
-	ohci_controller_init(sc);
-
-	USB_BUS_LOCK(&sc->sc_bus);
-	if (sc->sc_intre) {
-		OWRITE4(sc, OHCI_INTERRUPT_ENABLE,
-		    sc->sc_intre & (OHCI_ALL_INTRS | OHCI_MIE));
-	}
-	if (sc->sc_control)
-		ctl = sc->sc_control;
-	else
-		ctl = OREAD4(sc, OHCI_CONTROL);
-	ctl |= OHCI_HCFS_RESUME;
-	OWRITE4(sc, OHCI_CONTROL, ctl);
-	usb_pause_mtx(&sc->sc_bus.bus_mtx,
-	    USB_MS_TO_TICKS(USB_RESUME_DELAY));
-	ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL;
-	OWRITE4(sc, OHCI_CONTROL, ctl);
-	usb_pause_mtx(&sc->sc_bus.bus_mtx, 
-	    USB_MS_TO_TICKS(USB_RESUME_RECOVERY));
-	sc->sc_control = sc->sc_intre = 0;
 
-	USB_BUS_UNLOCK(&sc->sc_bus);
+	/* some broken BIOSes never initialize the Controller chip */
+	ohci_controller_init(sc, 0);
 
 	/* catch any lost interrupts */
 	ohci_do_poll(&sc->sc_bus);
@@ -2713,6 +2674,24 @@ ohci_device_suspend(struct usb_device *udev)
 }
 
 static void
+ohci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
+{
+	struct ohci_softc *sc = OHCI_BUS2SC(bus);
+
+	switch (state) {
+	case USB_HW_POWER_SUSPEND:
+	case USB_HW_POWER_SHUTDOWN:
+		ohci_suspend(sc);
+		break;
+	case USB_HW_POWER_RESUME:
+		ohci_resume(sc);
+		break;
+	default:
+		break;
+	}
+}
+
+static void
 ohci_set_hw_power(struct usb_bus *bus)
 {
 	struct ohci_softc *sc = OHCI_BUS2SC(bus);
@@ -2756,6 +2735,7 @@ struct usb_bus_methods ohci_bus_methods =
 	.device_resume = ohci_device_resume,
 	.device_suspend = ohci_device_suspend,
 	.set_hw_power = ohci_set_hw_power,
+	.set_hw_power_sleep = ohci_set_hw_power_sleep,
 	.roothub_exec = ohci_roothub_exec,
 	.xfer_poll = ohci_do_poll,
 };
diff --git a/sys/dev/usb/controller/ohci.h b/sys/dev/usb/controller/ohci.h
index d85c2c9..9d8ac7d 100644
--- a/sys/dev/usb/controller/ohci.h
+++ b/sys/dev/usb/controller/ohci.h
@@ -241,8 +241,6 @@ typedef struct ohci_softc {
 	bus_space_handle_t sc_io_hdl;
 
 	uint32_t sc_eintrs;		/* enabled interrupts */
-	uint32_t sc_control;		/* Preserved during suspend/standby */
-	uint32_t sc_intre;
 
 	uint16_t sc_intr_stat[OHCI_NO_EDS];
 	uint16_t sc_id_vendor;
@@ -260,8 +258,6 @@ usb_bus_mem_cb_t ohci_iterate_hw_softc;
 
 usb_error_t ohci_init(ohci_softc_t *sc);
 void	ohci_detach(struct ohci_softc *sc);
-void	ohci_suspend(ohci_softc_t *sc);
-void	ohci_resume(ohci_softc_t *sc);
 void	ohci_interrupt(ohci_softc_t *sc);
 
 #endif					/* _OHCI_H_ */
diff --git a/sys/dev/usb/controller/ohci_atmelarm.c b/sys/dev/usb/controller/ohci_atmelarm.c
index 9a39740..643b4d1 100644
--- a/sys/dev/usb/controller/ohci_atmelarm.c
+++ b/sys/dev/usb/controller/ohci_atmelarm.c
@@ -174,7 +174,7 @@ ohci_atmelarm_detach(device_t dev)
 		device_delete_child(dev, bdev);
 	}
 	/* during module unload there are lots of children leftover */
-	device_delete_all_children(dev);
+	device_delete_children(dev);
 
 	/*
 	 * Put the controller into reset, then disable clocks and do
@@ -221,18 +221,17 @@ static device_method_t ohci_methods[] = {
 	DEVMETHOD(device_probe, ohci_atmelarm_probe),
 	DEVMETHOD(device_attach, ohci_atmelarm_attach),
 	DEVMETHOD(device_detach, ohci_atmelarm_detach),
+	DEVMETHOD(device_suspend, bus_generic_suspend),
+	DEVMETHOD(device_resume, bus_generic_resume),
 	DEVMETHOD(device_shutdown, bus_generic_shutdown),
 
-	/* Bus interface */
-	DEVMETHOD(bus_print_child, bus_generic_print_child),
-
-	{0, 0}
+	DEVMETHOD_END
 };
 
 static driver_t ohci_driver = {
-	"ohci",
-	ohci_methods,
-	sizeof(struct at91_ohci_softc),
+	.name = "ohci",
+	.methods = ohci_methods,
+	.size = sizeof(struct at91_ohci_softc),
 };
 
 static devclass_t ohci_devclass;
diff --git a/sys/dev/usb/controller/ohci_pci.c b/sys/dev/usb/controller/ohci_pci.c
index 9ff6e31..864376b 100644
--- a/sys/dev/usb/controller/ohci_pci.c
+++ b/sys/dev/usb/controller/ohci_pci.c
@@ -74,6 +74,7 @@ __FBSDID("$FreeBSD$");
 #include <dev/usb/usb_pci.h>
 #include <dev/usb/controller/ohci.h>
 #include <dev/usb/controller/ohcireg.h>
+#include "usb_if.h"
 
 #define	PCI_OHCI_VENDORID_ACERLABS	0x10b9
 #define	PCI_OHCI_VENDORID_AMD		0x1022
@@ -92,28 +93,13 @@ __FBSDID("$FreeBSD$");
 static device_probe_t ohci_pci_probe;
 static device_attach_t ohci_pci_attach;
 static device_detach_t ohci_pci_detach;
-static device_suspend_t ohci_pci_suspend;
-static device_resume_t ohci_pci_resume;
+static usb_take_controller_t ohci_pci_take_controller;
 
 static int
-ohci_pci_suspend(device_t self)
+ohci_pci_take_controller(device_t self)
 {
-	ohci_softc_t *sc = device_get_softc(self);
-	int err;
-
-	err = bus_generic_suspend(self);
-	if (err) {
-		return (err);
-	}
-	ohci_suspend(sc);
-	return (0);
-}
-
-static int
-ohci_pci_resume(device_t self)
-{
-	ohci_softc_t *sc = device_get_softc(self);
-	uint32_t reg, int_line;
+	uint32_t reg;
+	uint32_t int_line;
 
 	if (pci_get_powerstate(self) != PCI_POWERSTATE_D0) {
 		device_printf(self, "chip is in D%d mode "
@@ -124,9 +110,6 @@ ohci_pci_resume(device_t self)
 		pci_write_config(self, PCI_CBMEM, reg, 4);
 		pci_write_config(self, PCIR_INTLINE, int_line, 4);
 	}
-	ohci_resume(sc);
-
-	bus_generic_resume(self);
 	return (0);
 }
 
@@ -348,7 +331,7 @@ ohci_pci_detach(device_t self)
 		device_delete_child(self, bdev);
 	}
 	/* during module unload there are lots of children leftover */
-	device_delete_all_children(self);
+	device_delete_children(self);
 
 	pci_disable_busmaster(self);
 
@@ -381,23 +364,22 @@ ohci_pci_detach(device_t self)
 	return (0);
 }
 
-static driver_t ohci_driver =
-{
+static device_method_t ohci_pci_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe, ohci_pci_probe),
+	DEVMETHOD(device_attach, ohci_pci_attach),
+	DEVMETHOD(device_detach, ohci_pci_detach),
+	DEVMETHOD(device_suspend, bus_generic_suspend),
+	DEVMETHOD(device_resume, bus_generic_resume),
+	DEVMETHOD(device_shutdown, bus_generic_shutdown),
+	DEVMETHOD(usb_take_controller, ohci_pci_take_controller),
+
+	DEVMETHOD_END
+};
+
+static driver_t ohci_driver = {
 	.name = "ohci",
-	.methods = (device_method_t[]){
-		/* device interface */
-		DEVMETHOD(device_probe, ohci_pci_probe),
-		DEVMETHOD(device_attach, ohci_pci_attach),
-		DEVMETHOD(device_detach, ohci_pci_detach),
-		DEVMETHOD(device_suspend, ohci_pci_suspend),
-		DEVMETHOD(device_resume, ohci_pci_resume),
-		DEVMETHOD(device_shutdown, bus_generic_shutdown),
-
-		/* bus interface */
-		DEVMETHOD(bus_print_child, bus_generic_print_child),
-
-		{0, 0}
-	},
+	.methods = ohci_pci_methods,
 	.size = sizeof(struct ohci_softc),
 };
 
diff --git a/sys/dev/usb/controller/ohci_s3c24x0.c b/sys/dev/usb/controller/ohci_s3c24x0.c
index 11b2579..225a2d2 100644
--- a/sys/dev/usb/controller/ohci_s3c24x0.c
+++ b/sys/dev/usb/controller/ohci_s3c24x0.c
@@ -156,7 +156,7 @@ ohci_s3c24x0_detach(device_t dev)
 		device_delete_child(dev, bdev);
 	}
 	/* during module unload there are lots of children leftover */
-	device_delete_all_children(dev);
+	device_delete_children(dev);
 
 	/*
 	 * Put the controller into reset, then disable clocks and do
@@ -198,18 +198,17 @@ static device_method_t ohci_methods[] = {
 	DEVMETHOD(device_probe, ohci_s3c24x0_probe),
 	DEVMETHOD(device_attach, ohci_s3c24x0_attach),
 	DEVMETHOD(device_detach, ohci_s3c24x0_detach),
+	DEVMETHOD(device_suspend, bus_generic_suspend),
+	DEVMETHOD(device_resume, bus_generic_resume),
 	DEVMETHOD(device_shutdown, bus_generic_shutdown),
 
-	/* Bus interface */
-	DEVMETHOD(bus_print_child, bus_generic_print_child),
-
-	{0, 0}
+	DEVMETHOD_END
 };
 
 static driver_t ohci_driver = {
-	"ohci",
-	ohci_methods,
-	sizeof(struct ohci_softc),
+	.name = "ohci",
+	.methods = ohci_methods,
+	.size = sizeof(struct ohci_softc),
 };
 
 static devclass_t ohci_devclass;
diff --git a/sys/dev/usb/controller/uhci.c b/sys/dev/usb/controller/uhci.c
index c365e01..d9091c9 100644
--- a/sys/dev/usb/controller/uhci.c
+++ b/sys/dev/usb/controller/uhci.c
@@ -373,9 +373,10 @@ done_1:
 
 done_2:
 
-	/* reload the configuration */
-	UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum);
-	UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof);
+	/* reset frame number */
+	UWRITE2(sc, UHCI_FRNUM, 0);
+	/* set default SOF value */
+	UWRITE1(sc, UHCI_SOF, 0x40);
 
 	USB_BUS_UNLOCK(&sc->sc_bus);
 
@@ -463,9 +464,6 @@ uhci_init(uhci_softc_t *sc)
 		uhci_dumpregs(sc);
 	}
 #endif
-	sc->sc_saved_sof = 0x40;	/* default value */
-	sc->sc_saved_frnum = 0;		/* default frame number */
-
 	/*
 	 * Setup QH's
 	 */
@@ -658,24 +656,16 @@ uhci_init(uhci_softc_t *sc)
 	return (0);
 }
 
-/* NOTE: suspend/resume is called from
- * interrupt context and cannot sleep!
- */
-
-void
+static void
 uhci_suspend(uhci_softc_t *sc)
 {
-	USB_BUS_LOCK(&sc->sc_bus);
-
 #ifdef USB_DEBUG
 	if (uhcidebug > 2) {
 		uhci_dumpregs(sc);
 	}
 #endif
-	/* save some state if BIOS doesn't */
 
-	sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM);
-	sc->sc_saved_sof = UREAD1(sc, UHCI_SOF);
+	USB_BUS_LOCK(&sc->sc_bus);
 
 	/* stop the controller */
 
@@ -685,13 +675,10 @@ uhci_suspend(uhci_softc_t *sc)
 
 	UHCICMD(sc, UHCI_CMD_EGSM);
 
-	usb_pause_mtx(&sc->sc_bus.bus_mtx, 
-	    USB_MS_TO_TICKS(USB_RESUME_WAIT));
-
 	USB_BUS_UNLOCK(&sc->sc_bus);
 }
 
-void
+static void
 uhci_resume(uhci_softc_t *sc)
 {
 	USB_BUS_LOCK(&sc->sc_bus);
@@ -704,21 +691,17 @@ uhci_resume(uhci_softc_t *sc)
 
 	UHCICMD(sc, UHCI_CMD_FGR);
 
-	usb_pause_mtx(&sc->sc_bus.bus_mtx,
-	    USB_MS_TO_TICKS(USB_RESUME_DELAY));
-
 	/* and start traffic again */
 
 	uhci_start(sc);
 
+	USB_BUS_UNLOCK(&sc->sc_bus);
+
 #ifdef USB_DEBUG
-	if (uhcidebug > 2) {
+	if (uhcidebug > 2)
 		uhci_dumpregs(sc);
-	}
 #endif
 
-	USB_BUS_UNLOCK(&sc->sc_bus);
-
 	/* catch lost interrupts */
 	uhci_do_poll(&sc->sc_bus);
 }
@@ -3179,6 +3162,24 @@ uhci_device_suspend(struct usb_device *udev)
 }
 
 static void
+uhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
+{
+	struct uhci_softc *sc = UHCI_BUS2SC(bus);
+
+	switch (state) {
+	case USB_HW_POWER_SUSPEND:
+	case USB_HW_POWER_SHUTDOWN:
+		uhci_suspend(sc);
+		break;
+	case USB_HW_POWER_RESUME:
+		uhci_resume(sc);
+		break;
+	default:
+		break;
+	}
+}
+
+static void
 uhci_set_hw_power(struct usb_bus *bus)
 {
 	struct uhci_softc *sc = UHCI_BUS2SC(bus);
@@ -3225,6 +3226,7 @@ struct usb_bus_methods uhci_bus_methods =
 	.device_resume = uhci_device_resume,
 	.device_suspend = uhci_device_suspend,
 	.set_hw_power = uhci_set_hw_power,
+	.set_hw_power_sleep = uhci_set_hw_power_sleep,
 	.roothub_exec = uhci_roothub_exec,
 	.xfer_poll = uhci_do_poll,
 };
diff --git a/sys/dev/usb/controller/uhci.h b/sys/dev/usb/controller/uhci.h
index 0878e79..8a6ce44 100644
--- a/sys/dev/usb/controller/uhci.h
+++ b/sys/dev/usb/controller/uhci.h
@@ -230,13 +230,11 @@ typedef struct uhci_softc {
 	uint32_t sc_loops;		/* number of QHs that wants looping */
 
 	uint16_t sc_intr_stat[UHCI_IFRAMELIST_COUNT];
-	uint16_t sc_saved_frnum;
 
 	uint8_t	sc_addr;		/* device address */
 	uint8_t	sc_conf;		/* device configuration */
 	uint8_t	sc_isreset;		/* bits set if a root hub is reset */
 	uint8_t	sc_isresumed;		/* bits set if a port was resumed */
-	uint8_t	sc_saved_sof;
 	uint8_t	sc_hub_idata[1];
 
 	char	sc_vendor[16];		/* vendor string for root hub */
@@ -245,8 +243,6 @@ typedef struct uhci_softc {
 usb_bus_mem_cb_t uhci_iterate_hw_softc;
 
 usb_error_t uhci_init(uhci_softc_t *sc);
-void	uhci_suspend(uhci_softc_t *sc);
-void	uhci_resume(uhci_softc_t *sc);
 void	uhci_reset(uhci_softc_t *sc);
 void	uhci_interrupt(uhci_softc_t *sc);
 
diff --git a/sys/dev/usb/controller/uhci_pci.c b/sys/dev/usb/controller/uhci_pci.c
index 3192aac..454b904 100644
--- a/sys/dev/usb/controller/uhci_pci.c
+++ b/sys/dev/usb/controller/uhci_pci.c
@@ -74,6 +74,7 @@ __FBSDID("$FreeBSD$");
 #include <dev/usb/usb_pci.h>
 #include <dev/usb/controller/uhci.h>
 #include <dev/usb/controller/uhcireg.h>
+#include "usb_if.h"
 
 #define	PCI_UHCI_VENDORID_INTEL		0x8086
 #define	PCI_UHCI_VENDORID_VIA		0x1106
@@ -83,33 +84,13 @@ __FBSDID("$FreeBSD$");
 static device_probe_t uhci_pci_probe;
 static device_attach_t uhci_pci_attach;
 static device_detach_t uhci_pci_detach;
-static device_suspend_t uhci_pci_suspend;
-static device_resume_t uhci_pci_resume;
+static usb_take_controller_t uhci_pci_take_controller;
 
 static int
-uhci_pci_suspend(device_t self)
+uhci_pci_take_controller(device_t self)
 {
-	uhci_softc_t *sc = device_get_softc(self);
-	int err;
-
-	err = bus_generic_suspend(self);
-	if (err) {
-		return (err);
-	}
-	uhci_suspend(sc);
-	return (0);
-}
-
-static int
-uhci_pci_resume(device_t self)
-{
-	uhci_softc_t *sc = device_get_softc(self);
-
 	pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2);
 
-	uhci_resume(sc);
-
-	bus_generic_resume(self);
 	return (0);
 }
 
@@ -406,7 +387,7 @@ uhci_pci_detach(device_t self)
 		device_delete_child(self, bdev);
 	}
 	/* during module unload there are lots of children leftover */
-	device_delete_all_children(self);
+	device_delete_children(self);
 
 	/*
 	 * disable interrupts that might have been switched on in
@@ -446,23 +427,22 @@ uhci_pci_detach(device_t self)
 	return (0);
 }
 
-static driver_t uhci_driver =
-{
+static device_method_t uhci_pci_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe, uhci_pci_probe),
+	DEVMETHOD(device_attach, uhci_pci_attach),
+	DEVMETHOD(device_detach, uhci_pci_detach),
+	DEVMETHOD(device_suspend, bus_generic_suspend),
+	DEVMETHOD(device_resume, bus_generic_resume),
+	DEVMETHOD(device_shutdown, bus_generic_shutdown),
+	DEVMETHOD(usb_take_controller, uhci_pci_take_controller),
+
+	DEVMETHOD_END
+};
+
+static driver_t uhci_driver = {
 	.name = "uhci",
-	.methods = (device_method_t[]){
-		/* device interface */
-		DEVMETHOD(device_probe, uhci_pci_probe),
-		DEVMETHOD(device_attach, uhci_pci_attach),
-		DEVMETHOD(device_detach, uhci_pci_detach),
-
-		DEVMETHOD(device_suspend, uhci_pci_suspend),
-		DEVMETHOD(device_resume, uhci_pci_resume),
-		DEVMETHOD(device_shutdown, bus_generic_shutdown),
-
-		/* Bus interface */
-		DEVMETHOD(bus_print_child, bus_generic_print_child),
-		{0, 0}
-	},
+	.methods = uhci_pci_methods,
 	.size = sizeof(struct uhci_softc),
 };
 
diff --git a/sys/dev/usb/controller/usb_controller.c b/sys/dev/usb/controller/usb_controller.c
index 7ff0bc0..0f942e1 100644
--- a/sys/dev/usb/controller/usb_controller.c
+++ b/sys/dev/usb/controller/usb_controller.c
@@ -61,12 +61,16 @@
 #include <dev/usb/usb_controller.h>
 #include <dev/usb/usb_bus.h>
 #include <dev/usb/usb_pf.h>
+#include "usb_if.h"
 
 /* function prototypes  */
 
 static device_probe_t usb_probe;
 static device_attach_t usb_attach;
 static device_detach_t usb_detach;
+static device_suspend_t usb_suspend;
+static device_resume_t usb_resume;
+static device_shutdown_t usb_shutdown;
 
 static void	usb_attach_sub(device_t, struct usb_bus *);
 
@@ -83,7 +87,12 @@ SYSCTL_INT(_hw_usb_ctrl, OID_AUTO, debug, CTLFLAG_RW, &usb_ctrl_debug, 0,
 static int usb_no_boot_wait = 0;
 TUNABLE_INT("hw.usb.no_boot_wait", &usb_no_boot_wait);
 SYSCTL_INT(_hw_usb, OID_AUTO, no_boot_wait, CTLFLAG_RDTUN, &usb_no_boot_wait, 0,
-    "No device enumerate waiting at boot.");
+    "No USB device enumerate waiting at boot.");
+
+static int usb_no_shutdown_wait = 0;
+TUNABLE_INT("hw.usb.no_shutdown_wait", &usb_no_shutdown_wait);
+SYSCTL_INT(_hw_usb, OID_AUTO, no_shutdown_wait, CTLFLAG_RW|CTLFLAG_TUN, &usb_no_shutdown_wait, 0,
+    "No USB device waiting at system shutdown.");
 
 static devclass_t usb_devclass;
 
@@ -91,9 +100,9 @@ static device_method_t usb_methods[] = {
 	DEVMETHOD(device_probe, usb_probe),
 	DEVMETHOD(device_attach, usb_attach),
 	DEVMETHOD(device_detach, usb_detach),
-	DEVMETHOD(device_suspend, bus_generic_suspend),
-	DEVMETHOD(device_resume, bus_generic_resume),
-	DEVMETHOD(device_shutdown, bus_generic_shutdown),
+	DEVMETHOD(device_suspend, usb_suspend),
+	DEVMETHOD(device_resume, usb_resume),
+	DEVMETHOD(device_shutdown, usb_shutdown),
 	{0, 0}
 };
 
@@ -113,6 +122,7 @@ DRIVER_MODULE(usbus, xhci, usb_driver, usb_devclass, 0, 0);
 DRIVER_MODULE(usbus, at91_udp, usb_driver, usb_devclass, 0, 0);
 DRIVER_MODULE(usbus, musbotg, usb_driver, usb_devclass, 0, 0);
 DRIVER_MODULE(usbus, uss820, usb_driver, usb_devclass, 0, 0);
+DRIVER_MODULE(usbus, octusb, usb_driver, usb_devclass, 0, 0);
 
 /*------------------------------------------------------------------------*
  *	usb_probe
@@ -182,12 +192,12 @@ usb_detach(device_t dev)
 	usb_root_mount_rel(bus);
 
 	USB_BUS_LOCK(bus);
-	if (usb_proc_msignal(&bus->explore_proc,
-	    &bus->detach_msg[0], &bus->detach_msg[1])) {
-		/* ignore */
-	}
-	/* Wait for detach to complete */
 
+	/* Queue detach job */
+	usb_proc_msignal(&bus->explore_proc,
+	    &bus->detach_msg[0], &bus->detach_msg[1]);
+
+	/* Wait for detach to complete */
 	usb_proc_mwait(&bus->explore_proc,
 	    &bus->detach_msg[0], &bus->detach_msg[1]);
 
@@ -213,6 +223,84 @@ usb_detach(device_t dev)
 }
 
 /*------------------------------------------------------------------------*
+ *	usb_suspend
+ *------------------------------------------------------------------------*/
+static int
+usb_suspend(device_t dev)
+{
+	struct usb_bus *bus = device_get_softc(dev);
+
+	DPRINTF("\n");
+
+	if (bus == NULL) {
+		/* was never setup properly */
+		return (0);
+	}
+
+	USB_BUS_LOCK(bus);
+	usb_proc_msignal(&bus->explore_proc,
+	    &bus->suspend_msg[0], &bus->suspend_msg[1]);
+	USB_BUS_UNLOCK(bus);
+
+	return (0);
+}
+
+/*------------------------------------------------------------------------*
+ *	usb_resume
+ *------------------------------------------------------------------------*/
+static int
+usb_resume(device_t dev)
+{
+	struct usb_bus *bus = device_get_softc(dev);
+
+	DPRINTF("\n");
+
+	if (bus == NULL) {
+		/* was never setup properly */
+		return (0);
+	}
+
+	USB_BUS_LOCK(bus);
+	usb_proc_msignal(&bus->explore_proc,
+	    &bus->resume_msg[0], &bus->resume_msg[1]);
+	USB_BUS_UNLOCK(bus);
+
+	return (0);
+}
+
+/*------------------------------------------------------------------------*
+ *	usb_shutdown
+ *------------------------------------------------------------------------*/
+static int
+usb_shutdown(device_t dev)
+{
+	struct usb_bus *bus = device_get_softc(dev);
+
+	DPRINTF("\n");
+
+	if (bus == NULL) {
+		/* was never setup properly */
+		return (0);
+	}
+
+	device_printf(bus->bdev, "Controller shutdown\n");
+
+	USB_BUS_LOCK(bus);
+	usb_proc_msignal(&bus->explore_proc,
+	    &bus->shutdown_msg[0], &bus->shutdown_msg[1]);
+	if (usb_no_shutdown_wait == 0) {
+		/* wait for shutdown callback to be executed */
+		usb_proc_mwait(&bus->explore_proc,
+		    &bus->shutdown_msg[0], &bus->shutdown_msg[1]);
+	}
+	USB_BUS_UNLOCK(bus);
+
+	device_printf(bus->bdev, "Controller shutdown complete\n");
+
+	return (0);
+}
+
+/*------------------------------------------------------------------------*
  *	usb_bus_explore
  *
  * This function is used to explore the device tree from the root.
@@ -226,6 +314,9 @@ usb_bus_explore(struct usb_proc_msg *pm)
 	bus = ((struct usb_bus_msg *)pm)->bus;
 	udev = bus->devices[USB_ROOT_HUB_ADDR];
 
+	if (bus->no_explore != 0)
+		return;
+
 	if (udev && udev->hub) {
 
 		if (bus->do_probe) {
@@ -296,6 +387,153 @@ usb_bus_detach(struct usb_proc_msg *pm)
 	bus->bdev = NULL;
 }
 
+/*------------------------------------------------------------------------*
+ *	usb_bus_suspend
+ *
+ * This function is used to suspend the USB contoller.
+ *------------------------------------------------------------------------*/
+static void
+usb_bus_suspend(struct usb_proc_msg *pm)
+{
+	struct usb_bus *bus;
+	struct usb_device *udev;
+	usb_error_t err;
+
+	bus = ((struct usb_bus_msg *)pm)->bus;
+	udev = bus->devices[USB_ROOT_HUB_ADDR];
+
+	if (udev == NULL || bus->bdev == NULL)
+		return;
+
+	USB_BUS_UNLOCK(bus);
+
+	bus_generic_shutdown(bus->bdev);
+
+	usbd_enum_lock(udev);
+
+	err = usbd_set_config_index(udev, USB_UNCONFIG_INDEX);
+	if (err)
+		device_printf(bus->bdev, "Could not unconfigure root HUB\n");
+
+	USB_BUS_LOCK(bus);
+	bus->hw_power_state = 0;
+	bus->no_explore = 1;
+	USB_BUS_UNLOCK(bus);
+
+	if (bus->methods->set_hw_power != NULL)
+		(bus->methods->set_hw_power) (bus);
+
+	if (bus->methods->set_hw_power_sleep != NULL)
+		(bus->methods->set_hw_power_sleep) (bus, USB_HW_POWER_SUSPEND);
+
+	usbd_enum_unlock(udev);
+
+	USB_BUS_LOCK(bus);
+}
+
+/*------------------------------------------------------------------------*
+ *	usb_bus_resume
+ *
+ * This function is used to resume the USB contoller.
+ *------------------------------------------------------------------------*/
+static void
+usb_bus_resume(struct usb_proc_msg *pm)
+{
+	struct usb_bus *bus;
+	struct usb_device *udev;
+	usb_error_t err;
+
+	bus = ((struct usb_bus_msg *)pm)->bus;
+	udev = bus->devices[USB_ROOT_HUB_ADDR];
+
+	if (udev == NULL || bus->bdev == NULL)
+		return;
+
+	USB_BUS_UNLOCK(bus);
+
+	usbd_enum_lock(udev);
+#if 0
+	DEVMETHOD(usb_take_controller, NULL);	/* dummy */
+#endif
+	USB_TAKE_CONTROLLER(device_get_parent(bus->bdev));
+
+	USB_BUS_LOCK(bus);
+ 	bus->hw_power_state =
+	  USB_HW_POWER_CONTROL |
+	  USB_HW_POWER_BULK |
+	  USB_HW_POWER_INTERRUPT |
+	  USB_HW_POWER_ISOC |
+	  USB_HW_POWER_NON_ROOT_HUB;
+	bus->no_explore = 0;
+	USB_BUS_UNLOCK(bus);
+
+	if (bus->methods->set_hw_power_sleep != NULL)
+		(bus->methods->set_hw_power_sleep) (bus, USB_HW_POWER_RESUME);
+
+	if (bus->methods->set_hw_power != NULL)
+		(bus->methods->set_hw_power) (bus);
+
+	/* restore USB configuration to index 0 */
+	err = usbd_set_config_index(udev, 0);
+	if (err)
+		device_printf(bus->bdev, "Could not configure root HUB\n");
+
+	/* probe and attach */
+	err = usb_probe_and_attach(udev, USB_IFACE_INDEX_ANY);
+	if (err) {
+		device_printf(bus->bdev, "Could not probe and "
+		    "attach root HUB\n");
+	}
+
+	usbd_enum_unlock(udev);
+
+	USB_BUS_LOCK(bus);
+}
+
+/*------------------------------------------------------------------------*
+ *	usb_bus_shutdown
+ *
+ * This function is used to shutdown the USB contoller.
+ *------------------------------------------------------------------------*/
+static void
+usb_bus_shutdown(struct usb_proc_msg *pm)
+{
+	struct usb_bus *bus;
+	struct usb_device *udev;
+	usb_error_t err;
+
+	bus = ((struct usb_bus_msg *)pm)->bus;
+	udev = bus->devices[USB_ROOT_HUB_ADDR];
+
+	if (udev == NULL || bus->bdev == NULL)
+		return;
+
+	USB_BUS_UNLOCK(bus);
+
+	bus_generic_shutdown(bus->bdev);
+
+	usbd_enum_lock(udev);
+
+	err = usbd_set_config_index(udev, USB_UNCONFIG_INDEX);
+	if (err)
+		device_printf(bus->bdev, "Could not unconfigure root HUB\n");
+
+	USB_BUS_LOCK(bus);
+	bus->hw_power_state = 0;
+	bus->no_explore = 1;
+	USB_BUS_UNLOCK(bus);
+
+	if (bus->methods->set_hw_power != NULL)
+		(bus->methods->set_hw_power) (bus);
+
+	if (bus->methods->set_hw_power_sleep != NULL)
+		(bus->methods->set_hw_power_sleep) (bus, USB_HW_POWER_SHUTDOWN);
+
+	usbd_enum_unlock(udev);
+
+	USB_BUS_LOCK(bus);
+}
+
 static void
 usb_power_wdog(void *arg)
 {
@@ -374,8 +612,6 @@ usb_bus_attach(struct usb_proc_msg *pm)
 		return;
 	}
 
-	USB_BUS_UNLOCK(bus);
-
 	/* default power_mask value */
 	bus->hw_power_state =
 	  USB_HW_POWER_CONTROL |
@@ -384,13 +620,15 @@ usb_bus_attach(struct usb_proc_msg *pm)
 	  USB_HW_POWER_ISOC |
 	  USB_HW_POWER_NON_ROOT_HUB;
 
+	USB_BUS_UNLOCK(bus);
+
 	/* make sure power is set at least once */
 
 	if (bus->methods->set_hw_power != NULL) {
 		(bus->methods->set_hw_power) (bus);
 	}
 
-	/* Allocate the Root USB device */
+	/* allocate the Root USB device */
 
 	child = usb_alloc_device(bus->bdev, bus, NULL, 0, 0, 1,
 	    speed, USB_MODE_HOST);
@@ -456,6 +694,21 @@ usb_attach_sub(device_t dev, struct usb_bus *bus)
 	bus->attach_msg[1].hdr.pm_callback = &usb_bus_attach;
 	bus->attach_msg[1].bus = bus;
 
+	bus->suspend_msg[0].hdr.pm_callback = &usb_bus_suspend;
+	bus->suspend_msg[0].bus = bus;
+	bus->suspend_msg[1].hdr.pm_callback = &usb_bus_suspend;
+	bus->suspend_msg[1].bus = bus;
+
+	bus->resume_msg[0].hdr.pm_callback = &usb_bus_resume;
+	bus->resume_msg[0].bus = bus;
+	bus->resume_msg[1].hdr.pm_callback = &usb_bus_resume;
+	bus->resume_msg[1].bus = bus;
+
+	bus->shutdown_msg[0].hdr.pm_callback = &usb_bus_shutdown;
+	bus->shutdown_msg[0].bus = bus;
+	bus->shutdown_msg[1].hdr.pm_callback = &usb_bus_shutdown;
+	bus->shutdown_msg[1].bus = bus;
+
 	/* Create USB explore and callback processes */
 
 	if (usb_proc_create(&bus->giant_callback_proc,
@@ -477,10 +730,8 @@ usb_attach_sub(device_t dev, struct usb_bus *bus)
 	} else {
 		/* Get final attach going */
 		USB_BUS_LOCK(bus);
-		if (usb_proc_msignal(&bus->explore_proc,
-		    &bus->attach_msg[0], &bus->attach_msg[1])) {
-			/* ignore */
-		}
+		usb_proc_msignal(&bus->explore_proc,
+		    &bus->attach_msg[0], &bus->attach_msg[1]);
 		USB_BUS_UNLOCK(bus);
 
 		/* Do initial explore */
@@ -602,4 +853,3 @@ usb_bus_mem_free_all(struct usb_bus *bus, usb_bus_mem_cb_t *cb)
 
 	mtx_destroy(&bus->bus_mtx);
 }
-
diff --git a/sys/dev/usb/controller/uss820dci.c b/sys/dev/usb/controller/uss820dci.c
index b98043e..612bc81 100644
--- a/sys/dev/usb/controller/uss820dci.c
+++ b/sys/dev/usb/controller/uss820dci.c
@@ -1513,16 +1513,16 @@ uss820dci_uninit(struct uss820dci_softc *sc)
 	USB_BUS_UNLOCK(&sc->sc_bus);
 }
 
-void
+static void
 uss820dci_suspend(struct uss820dci_softc *sc)
 {
-	return;
+	/* TODO */
 }
 
-void
+static void
 uss820dci_resume(struct uss820dci_softc *sc)
 {
-	return;
+	/* TODO */
 }
 
 static void
@@ -2360,6 +2360,26 @@ uss820dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc
 	}
 }
 
+static void
+uss820dci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
+{
+	struct uss820dci_softc *sc = USS820_DCI_BUS2SC(bus);
+
+	switch (state) {
+	case USB_HW_POWER_SUSPEND:
+		uss820dci_suspend(sc);
+		break;
+	case USB_HW_POWER_SHUTDOWN:
+		uss820dci_uninit(sc);
+		break;
+	case USB_HW_POWER_RESUME:
+		uss820dci_resume(sc);
+		break;
+	default:
+		break;
+	}
+}
+
 struct usb_bus_methods uss820dci_bus_methods =
 {
 	.endpoint_init = &uss820dci_ep_init,
@@ -2370,4 +2390,5 @@ struct usb_bus_methods uss820dci_bus_methods =
 	.clear_stall = &uss820dci_clear_stall,
 	.roothub_exec = &uss820dci_roothub_exec,
 	.xfer_poll = &uss820dci_do_poll,
+	.set_hw_power_sleep = uss820dci_set_hw_power_sleep,
 };
diff --git a/sys/dev/usb/controller/uss820dci.h b/sys/dev/usb/controller/uss820dci.h
index e158c1c..8a27f15 100644
--- a/sys/dev/usb/controller/uss820dci.h
+++ b/sys/dev/usb/controller/uss820dci.h
@@ -349,8 +349,6 @@ struct uss820dci_softc {
 
 usb_error_t uss820dci_init(struct uss820dci_softc *sc);
 void	uss820dci_uninit(struct uss820dci_softc *sc);
-void	uss820dci_suspend(struct uss820dci_softc *sc);
-void	uss820dci_resume(struct uss820dci_softc *sc);
 void	uss820dci_interrupt(struct uss820dci_softc *sc);
 
 #endif					/* _USS820_DCI_H_ */
diff --git a/sys/dev/usb/controller/uss820dci_atmelarm.c b/sys/dev/usb/controller/uss820dci_atmelarm.c
index a8bd197..7fd83a2 100644
--- a/sys/dev/usb/controller/uss820dci_atmelarm.c
+++ b/sys/dev/usb/controller/uss820dci_atmelarm.c
@@ -63,23 +63,17 @@ __FBSDID("$FreeBSD$");
 static device_probe_t uss820_atmelarm_probe;
 static device_attach_t uss820_atmelarm_attach;
 static device_detach_t uss820_atmelarm_detach;
-static device_suspend_t uss820_atmelarm_suspend;
-static device_resume_t uss820_atmelarm_resume;
-static device_shutdown_t uss820_atmelarm_shutdown;
 
 static device_method_t uss820dci_methods[] = {
 	/* Device interface */
 	DEVMETHOD(device_probe, uss820_atmelarm_probe),
 	DEVMETHOD(device_attach, uss820_atmelarm_attach),
 	DEVMETHOD(device_detach, uss820_atmelarm_detach),
-	DEVMETHOD(device_suspend, uss820_atmelarm_suspend),
-	DEVMETHOD(device_resume, uss820_atmelarm_resume),
-	DEVMETHOD(device_shutdown, uss820_atmelarm_shutdown),
+	DEVMETHOD(device_suspend, bus_generic_suspend),
+	DEVMETHOD(device_resume, bus_generic_resume),
+	DEVMETHOD(device_shutdown, bus_generic_shutdown),
 
-	/* Bus interface */
-	DEVMETHOD(bus_print_child, bus_generic_print_child),
-
-	{0, 0}
+	DEVMETHOD_END
 };
 
 static driver_t uss820dci_driver = {
@@ -96,47 +90,6 @@ MODULE_DEPEND(uss820, usb, 1, 1, 1);
 static const char *const uss820_desc = "USS820 USB Device Controller";
 
 static int
-uss820_atmelarm_suspend(device_t dev)
-{
-	struct uss820dci_softc *sc = device_get_softc(dev);
-	int err;
-
-	err = bus_generic_suspend(dev);
-	if (err == 0) {
-		uss820dci_suspend(sc);
-	}
-	return (err);
-}
-
-static int
-uss820_atmelarm_resume(device_t dev)
-{
-	struct uss820dci_softc *sc = device_get_softc(dev);
-	int err;
-
-	uss820dci_resume(sc);
-
-	err = bus_generic_resume(dev);
-
-	return (err);
-}
-
-static int
-uss820_atmelarm_shutdown(device_t dev)
-{
-	struct uss820dci_softc *sc = device_get_softc(dev);
-	int err;
-
-	err = bus_generic_shutdown(dev);
-	if (err)
-		return (err);
-
-	uss820dci_uninit(sc);
-
-	return (0);
-}
-
-static int
 uss820_atmelarm_probe(device_t dev)
 {
 	device_set_desc(dev, uss820_desc);
@@ -224,7 +177,7 @@ uss820_atmelarm_detach(device_t dev)
 		device_delete_child(dev, bdev);
 	}
 	/* during module unload there are lots of children leftover */
-	device_delete_all_children(dev);
+	device_delete_children(dev);
 
 	if (sc->sc_irq_res && sc->sc_intr_hdl) {
 		/*
diff --git a/sys/dev/usb/controller/xhci.c b/sys/dev/usb/controller/xhci.c
index 9bc7d21..c20e3bd 100644
--- a/sys/dev/usb/controller/xhci.c
+++ b/sys/dev/usb/controller/xhci.c
@@ -550,24 +550,27 @@ xhci_uninit(struct xhci_softc *sc)
 	sx_destroy(&sc->sc_cmd_sx);
 }
 
-void
-xhci_suspend(struct xhci_softc *sc)
-{
-	/* XXX TODO */
-}
-
-void
-xhci_resume(struct xhci_softc *sc)
-{
-	/* XXX TODO */
-}
-
-void
-xhci_shutdown(struct xhci_softc *sc)
+static void
+xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
 {
-	DPRINTF("Stopping the XHCI\n");
+	struct xhci_softc *sc = XHCI_BUS2SC(bus);
 
-	xhci_halt_controller(sc);
+	switch (state) {
+	case USB_HW_POWER_SUSPEND:
+		DPRINTF("Stopping the XHCI\n");
+		xhci_halt_controller(sc);
+		break;
+	case USB_HW_POWER_SHUTDOWN:
+		DPRINTF("Stopping the XHCI\n");
+		xhci_halt_controller(sc);
+		break;
+	case USB_HW_POWER_RESUME:
+		DPRINTF("Starting the XHCI\n");
+		xhci_start_controller(sc);
+		break;
+	default:
+		break;
+	}
 }
 
 static usb_error_t
@@ -3928,4 +3931,5 @@ struct usb_bus_methods xhci_bus_methods = {
 	.set_address = xhci_set_address,
 	.clear_stall = xhci_ep_clear_stall,
 	.device_state_change = xhci_device_state_change,
+	.set_hw_power_sleep = xhci_set_hw_power_sleep,
 };
diff --git a/sys/dev/usb/controller/xhci.h b/sys/dev/usb/controller/xhci.h
index 81f392a..14afcaf 100644
--- a/sys/dev/usb/controller/xhci.h
+++ b/sys/dev/usb/controller/xhci.h
@@ -494,9 +494,6 @@ usb_error_t xhci_halt_controller(struct xhci_softc *);
 usb_error_t xhci_init(struct xhci_softc *, device_t);
 usb_error_t xhci_start_controller(struct xhci_softc *);
 void	xhci_interrupt(struct xhci_softc *);
-void	xhci_resume(struct xhci_softc *);
-void	xhci_shutdown(struct xhci_softc *);
-void	xhci_suspend(struct xhci_softc *);
 void	xhci_uninit(struct xhci_softc *);
 
 #endif					/* _XHCI_H_ */
diff --git a/sys/dev/usb/controller/xhci_pci.c b/sys/dev/usb/controller/xhci_pci.c
index 40358bf..80877ac 100644
--- a/sys/dev/usb/controller/xhci_pci.c
+++ b/sys/dev/usb/controller/xhci_pci.c
@@ -58,27 +58,24 @@ __FBSDID("$FreeBSD$");
 #include <dev/usb/usb_pci.h>
 #include <dev/usb/controller/xhci.h>
 #include <dev/usb/controller/xhcireg.h>
+#include "usb_if.h"
 
 static device_probe_t xhci_pci_probe;
 static device_attach_t xhci_pci_attach;
 static device_detach_t xhci_pci_detach;
-static device_suspend_t xhci_pci_suspend;
-static device_resume_t xhci_pci_resume;
-static device_shutdown_t xhci_pci_shutdown;
-static void xhci_pci_takecontroller(device_t);
+static usb_take_controller_t xhci_pci_take_controller;
 
 static device_method_t xhci_device_methods[] = {
 	/* device interface */
 	DEVMETHOD(device_probe, xhci_pci_probe),
 	DEVMETHOD(device_attach, xhci_pci_attach),
 	DEVMETHOD(device_detach, xhci_pci_detach),
-	DEVMETHOD(device_suspend, xhci_pci_suspend),
-	DEVMETHOD(device_resume, xhci_pci_resume),
-	DEVMETHOD(device_shutdown, xhci_pci_shutdown),
-	/* bus interface */
-	DEVMETHOD(bus_print_child, bus_generic_print_child),
+	DEVMETHOD(device_suspend, bus_generic_suspend),
+	DEVMETHOD(device_resume, bus_generic_resume),
+	DEVMETHOD(device_shutdown, bus_generic_shutdown),
+	DEVMETHOD(usb_take_controller, xhci_pci_take_controller),
 
-	{0, 0}
+	DEVMETHOD_END
 };
 
 static driver_t xhci_driver = {
@@ -92,45 +89,6 @@ static devclass_t xhci_devclass;
 DRIVER_MODULE(xhci, pci, xhci_driver, xhci_devclass, 0, 0);
 MODULE_DEPEND(xhci, usb, 1, 1, 1);
 
-static int
-xhci_pci_suspend(device_t self)
-{
-	struct xhci_softc *sc = device_get_softc(self);
-	int err;
-
-	err = bus_generic_suspend(self);
-	if (err)
-		return (err);
-	xhci_suspend(sc);
-	return (0);
-}
-
-static int
-xhci_pci_resume(device_t self)
-{
-	struct xhci_softc *sc = device_get_softc(self);
-
-	xhci_pci_takecontroller(self);
-	xhci_resume(sc);
-
-	bus_generic_resume(self);
-
-	return (0);
-}
-
-static int
-xhci_pci_shutdown(device_t self)
-{
-	struct xhci_softc *sc = device_get_softc(self);
-	int err;
-
-	err = bus_generic_shutdown(self);
-	if (err)
-		return (err);
-	xhci_shutdown(sc);
-
-	return (0);
-}
 
 static const char *
 xhci_pci_match(device_t self)
@@ -211,7 +169,7 @@ xhci_pci_attach(device_t self)
 		sc->sc_intr_hdl = NULL;
 		goto error;
 	}
-	xhci_pci_takecontroller(self);
+	xhci_pci_take_controller(self);
 
 	err = xhci_halt_controller(sc);
 
@@ -244,7 +202,7 @@ xhci_pci_detach(device_t self)
 		device_delete_child(self, bdev);
 	}
 	/* during module unload there are lots of children leftover */
-	device_delete_all_children(self);
+	device_delete_children(self);
 
 	pci_disable_busmaster(self);
 
@@ -270,8 +228,8 @@ xhci_pci_detach(device_t self)
 	return (0);
 }
 
-static void
-xhci_pci_takecontroller(device_t self)
+static int
+xhci_pci_take_controller(device_t self)
 {
 	struct xhci_softc *sc = device_get_softc(self);
 	uint32_t cparams;
@@ -314,4 +272,5 @@ xhci_pci_takecontroller(device_t self)
 			usb_pause_mtx(NULL, hz / 100);	/* wait 10ms */
 		}
 	}
+	return (0);
 }
diff --git a/sys/dev/usb/controller/xhcireg.h b/sys/dev/usb/controller/xhcireg.h
index 8be502e..b14dabc 100644
--- a/sys/dev/usb/controller/xhcireg.h
+++ b/sys/dev/usb/controller/xhcireg.h
@@ -115,7 +115,7 @@
 #define	XHCI_PS_PR		0x00000010	/* RW - port reset */
 #define	XHCI_PS_PLS_GET(x)	(((x) >> 5) & 0xF)	/* RW - port link state */
 #define	XHCI_PS_PLS_SET(x)	(((x) & 0xF) << 5)	/* RW - port link state */
-#define	XHCI_PS_PP		0x00000100	/* RW - port power */
+#define	XHCI_PS_PP		0x00000200	/* RW - port power */
 #define	XHCI_PS_SPEED_GET(x)	(((x) >> 10) & 0xF)	/* RO - port speed */
 #define	XHCI_PS_PIC_GET(x)	(((x) >> 14) & 0x3)	/* RW - port indicator */
 #define	XHCI_PS_PIC_SET(x)	(((x) & 0x3) << 14)	/* RW - port indicator */
diff --git a/sys/dev/usb/input/ukbd.c b/sys/dev/usb/input/ukbd.c
index 688f17b..eb7e1d9 100644
--- a/sys/dev/usb/input/ukbd.c
+++ b/sys/dev/usb/input/ukbd.c
@@ -198,7 +198,6 @@ struct ukbd_softc {
 	int	sc_mode;		/* input mode (K_XLATE,K_RAW,K_CODE) */
 	int	sc_state;		/* shift/lock key state */
 	int	sc_accents;		/* accent key index (> 0) */
-	int	sc_poll_tick_last;
 	int	sc_led_size;
 	int	sc_kbd_size;
 
@@ -227,7 +226,6 @@ struct ukbd_softc {
 	uint8_t sc_id_events;
 	uint8_t sc_kbd_id;
 
-	uint8_t sc_poll_detected;
 	uint8_t sc_buffer[UKBD_BUFFER_SIZE];
 };
 
@@ -247,6 +245,33 @@ struct ukbd_softc {
 			 SCAN_PREFIX_CTL | SCAN_PREFIX_SHIFT)
 #define	SCAN_CHAR(c)	((c) & 0x7f)
 
+#define	UKBD_LOCK()	mtx_lock(&Giant)
+#define	UKBD_UNLOCK()	mtx_unlock(&Giant)
+
+#ifdef	INVARIANTS
+
+/*
+ * Assert that the lock is held in all contexts
+ * where the code can be executed.
+ */
+#define	UKBD_LOCK_ASSERT()	mtx_assert(&Giant, MA_OWNED)
+
+/*
+ * Assert that the lock is held in the contexts
+ * where it really has to be so.
+ */
+#define	UKBD_CTX_LOCK_ASSERT()			 	\
+	do {						\
+		if (!kdb_active && panicstr == NULL)	\
+			mtx_assert(&Giant, MA_OWNED);	\
+	} while (0)
+#else
+
+#define UKBD_LOCK_ASSERT()	(void)0
+#define UKBD_CTX_LOCK_ASSERT()	(void)0
+
+#endif
+
 struct ukbd_mods {
 	uint32_t mask, key;
 };
@@ -339,8 +364,6 @@ static int	ukbd_ioctl(keyboard_t *, u_long, caddr_t);
 static int	ukbd_enable(keyboard_t *);
 static int	ukbd_disable(keyboard_t *);
 static void	ukbd_interrupt(struct ukbd_softc *);
-static int	ukbd_is_polling(struct ukbd_softc *);
-static int	ukbd_polls_other_thread(struct ukbd_softc *);
 static void	ukbd_event_keyinput(struct ukbd_softc *);
 
 static device_probe_t ukbd_probe;
@@ -370,7 +393,8 @@ ukbd_start_timer(struct ukbd_softc *sc)
 static void
 ukbd_put_key(struct ukbd_softc *sc, uint32_t key)
 {
-	mtx_assert(&Giant, MA_OWNED);
+
+	UKBD_CTX_LOCK_ASSERT();
 
 	DPRINTF("0x%02x (%d) %s\n", key, key,
 	    (key & KEY_RELEASE) ? "released" : "pressed");
@@ -388,52 +412,32 @@ ukbd_put_key(struct ukbd_softc *sc, uint32_t key)
 }
 
 static void
-ukbd_yield(void)
-{
-	struct thread *td = curthread;
-	uint32_t old_prio;
-
-	DROP_GIANT();
-
-	thread_lock(td);
-
-	/* get current priority */
-	old_prio = td->td_base_pri;
-
-	/* set new priority */
-	sched_prio(td, td->td_user_pri);
-
-	/* cause a task switch */
-	mi_switch(SW_INVOL | SWT_RELINQUISH, NULL);
-
-	/* restore priority */
-	sched_prio(td, old_prio);
-
-	thread_unlock(td);
-
-	PICKUP_GIANT();
-}
-
-static void
 ukbd_do_poll(struct ukbd_softc *sc, uint8_t wait)
 {
-	DPRINTFN(2, "polling\n");
 
-	/* update stats about last polling event */
-	sc->sc_poll_tick_last = ticks;
-	sc->sc_poll_detected = 1;
+	UKBD_CTX_LOCK_ASSERT();
+	KASSERT((sc->sc_flags & UKBD_FLAG_POLLING) != 0,
+	    ("ukbd_do_poll called when not polling\n"));
+	DPRINTFN(2, "polling\n");
 
-	if (kdb_active == 0) {
+	if (!kdb_active && !SCHEDULER_STOPPED()) {
+		/*
+		 * In this context the kernel is polling for input,
+		 * but the USB subsystem works in normal interrupt-driven
+		 * mode, so we just wait on the USB threads to do the job.
+		 * Note that we currently hold the Giant, but it's also used
+		 * as the transfer mtx, so we must release it while waiting.
+		 */
 		while (sc->sc_inputs == 0) {
-
-			/* give USB threads a chance to run */
-			ukbd_yield();
-
-			/* check if we should wait */
+			/*
+			 * Give USB threads a chance to run.  Note that
+			 * kern_yield performs DROP_GIANT + PICKUP_GIANT.
+			 */
+			kern_yield(PRI_UNCHANGED);
 			if (!wait)
 				break;
 		}
-		return;		/* Only poll if KDB is active */
+		return;
 	}
 
 	while (sc->sc_inputs == 0) {
@@ -441,7 +445,6 @@ ukbd_do_poll(struct ukbd_softc *sc, uint8_t wait)
 		usbd_transfer_poll(sc->sc_xfer, UKBD_N_TRANSFER);
 
 		/* Delay-optimised support for repetition of keys */
-
 		if (ukbd_any_key_pressed(sc)) {
 			/* a key is pressed - need timekeeping */
 			DELAY(1000);
@@ -462,16 +465,16 @@ ukbd_get_key(struct ukbd_softc *sc, uint8_t wait)
 {
 	int32_t c;
 
-	mtx_assert(&Giant, MA_OWNED);
+	UKBD_CTX_LOCK_ASSERT();
+	KASSERT((!kdb_active && !SCHEDULER_STOPPED())
+	    || (sc->sc_flags & UKBD_FLAG_POLLING) != 0,
+	    ("not polling in kdb or panic\n"));
 
 	if (sc->sc_inputs == 0) {
 		/* start transfer, if not already started */
 		usbd_transfer_start(sc->sc_xfer[UKBD_INTR_DT]);
 	}
 
-	if (ukbd_polls_other_thread(sc))
-		return (-1);
-
 	if (sc->sc_flags & UKBD_FLAG_POLLING)
 		ukbd_do_poll(sc, wait);
 
@@ -499,6 +502,8 @@ ukbd_interrupt(struct ukbd_softc *sc)
 	uint8_t i;
 	uint8_t j;
 
+	UKBD_CTX_LOCK_ASSERT();
+
 	if (sc->sc_ndata.keycode[0] == KEY_ERROR)
 		return;
 
@@ -584,7 +589,9 @@ ukbd_event_keyinput(struct ukbd_softc *sc)
 {
 	int c;
 
-	if (ukbd_is_polling(sc))
+	UKBD_CTX_LOCK_ASSERT();
+
+	if ((sc->sc_flags & UKBD_FLAG_POLLING) != 0)
 		return;
 
 	if (sc->sc_inputs == 0)
@@ -608,7 +615,7 @@ ukbd_timeout(void *arg)
 {
 	struct ukbd_softc *sc = arg;
 
-	mtx_assert(&Giant, MA_OWNED);
+	UKBD_LOCK_ASSERT();
 
 	sc->sc_time_ms += 25;	/* milliseconds */
 
@@ -656,6 +663,8 @@ ukbd_intr_callback(struct usb_xfer *xfer, usb_error_t error)
 	uint8_t id;
 	int len;
 
+	UKBD_LOCK_ASSERT();
+
 	usbd_xfer_status(xfer, &len, NULL, NULL, NULL);
 	pc = usbd_xfer_get_frame(xfer, 0);
 
@@ -842,6 +851,8 @@ ukbd_set_leds_callback(struct usb_xfer *xfer, usb_error_t error)
 	uint8_t any;
 	int len;
 
+	UKBD_LOCK_ASSERT();
+
 #ifdef USB_DEBUG
 	if (ukbd_no_leds)
 		return;
@@ -972,6 +983,7 @@ ukbd_probe(device_t dev)
 	int error;
 	uint16_t d_len;
 
+	UKBD_LOCK_ASSERT();
 	DPRINTFN(11, "\n");
 
 	if (sw == NULL) {
@@ -998,7 +1010,7 @@ ukbd_probe(device_t dev)
 	if (error)
 		return (ENXIO);
 
-	/* 
+	/*
 	 * NOTE: we currently don't support USB mouse and USB keyboard
 	 * on the same USB endpoint.
 	 */
@@ -1165,6 +1177,8 @@ ukbd_attach(device_t dev)
 	uint16_t n;
 	uint16_t hid_len;
 
+	UKBD_LOCK_ASSERT();
+
 	kbd_init_struct(kbd, UKBD_DRIVER_NAME, KB_OTHER, unit, 0, 0, 0);
 
 	kbd->kb_data = (void *)sc;
@@ -1241,14 +1255,10 @@ ukbd_attach(device_t dev)
 	/* ignore if SETIDLE fails, hence it is not crucial */
 	usbd_req_set_idle(sc->sc_udev, NULL, sc->sc_iface_index, 0, 0);
 
-	mtx_lock(&Giant);
-
 	ukbd_ioctl(kbd, KDSETLED, (caddr_t)&sc->sc_state);
 
 	KBD_INIT_DONE(kbd);
 
-	mtx_unlock(&Giant);
-
 	if (kbd_register(kbd) < 0) {
 		goto detach;
 	}
@@ -1266,15 +1276,10 @@ ukbd_attach(device_t dev)
 	if (bootverbose) {
 		genkbd_diag(kbd, bootverbose);
 	}
-	/* lock keyboard mutex */
-
-	mtx_lock(&Giant);
 
 	/* start the keyboard */
-
 	usbd_transfer_start(sc->sc_xfer[UKBD_INTR_DT]);
 
-	mtx_unlock(&Giant);
 	return (0);			/* success */
 
 detach:
@@ -1288,9 +1293,9 @@ ukbd_detach(device_t dev)
 	struct ukbd_softc *sc = device_get_softc(dev);
 	int error;
 
-	DPRINTF("\n");
+	UKBD_LOCK_ASSERT();
 
-	mtx_lock(&Giant);
+	DPRINTF("\n");
 
 	sc->sc_flags |= UKBD_FLAG_GONE;
 
@@ -1318,8 +1323,6 @@ ukbd_detach(device_t dev)
 	}
 	sc->sc_kbd.kb_flags = 0;
 
-	mtx_unlock(&Giant);
-
 	usbd_transfer_unsetup(sc->sc_xfer, UKBD_N_TRANSFER);
 
 	usb_callout_drain(&sc->sc_callout);
@@ -1335,12 +1338,10 @@ ukbd_resume(device_t dev)
 {
 	struct ukbd_softc *sc = device_get_softc(dev);
 
-	mtx_lock(&Giant);
+	UKBD_LOCK_ASSERT();
 
 	ukbd_clear_state(&sc->sc_kbd);
 
-	mtx_unlock(&Giant);
-
 	return (0);
 }
 
@@ -1400,15 +1401,11 @@ ukbd_lock(keyboard_t *kbd, int lock)
 static int
 ukbd_enable(keyboard_t *kbd)
 {
-	if (!mtx_owned(&Giant)) {
-		/* XXX cludge */
-		int retval;
-		mtx_lock(&Giant);
-		retval = ukbd_enable(kbd);
-		mtx_unlock(&Giant);
-		return (retval);
-	}
+
+	UKBD_LOCK();
 	KBD_ACTIVATE(kbd);
+	UKBD_UNLOCK();
+
 	return (0);
 }
 
@@ -1416,44 +1413,24 @@ ukbd_enable(keyboard_t *kbd)
 static int
 ukbd_disable(keyboard_t *kbd)
 {
-	if (!mtx_owned(&Giant)) {
-		/* XXX cludge */
-		int retval;
-		mtx_lock(&Giant);
-		retval = ukbd_disable(kbd);
-		mtx_unlock(&Giant);
-		return (retval);
-	}
+
+	UKBD_LOCK();
 	KBD_DEACTIVATE(kbd);
+	UKBD_UNLOCK();
+
 	return (0);
 }
 
 /* check if data is waiting */
+/* Currently unused. */
 static int
 ukbd_check(keyboard_t *kbd)
 {
 	struct ukbd_softc *sc = kbd->kb_data;
 
-	if (!KBD_IS_ACTIVE(kbd))
-		return (0);
+	UKBD_CTX_LOCK_ASSERT();
 
-	if (sc->sc_flags & UKBD_FLAG_POLLING) {
-		if (!mtx_owned(&Giant)) {
-			/* XXX cludge */
-			int retval;
-			mtx_lock(&Giant);
-			retval = ukbd_check(kbd);
-			mtx_unlock(&Giant);
-			return (retval);
-		}
-	} else {
-		/* XXX the keyboard layer requires Giant */
-		if (!mtx_owned(&Giant))
-			return (0);
-	}
-
-	/* check if key belongs to this thread */
-	if (ukbd_polls_other_thread(sc))
+	if (!KBD_IS_ACTIVE(kbd))
 		return (0);
 
 	if (sc->sc_flags & UKBD_FLAG_POLLING)
@@ -1472,30 +1449,13 @@ ukbd_check(keyboard_t *kbd)
 
 /* check if char is waiting */
 static int
-ukbd_check_char(keyboard_t *kbd)
+ukbd_check_char_locked(keyboard_t *kbd)
 {
 	struct ukbd_softc *sc = kbd->kb_data;
 
-	if (!KBD_IS_ACTIVE(kbd))
-		return (0);
+	UKBD_CTX_LOCK_ASSERT();
 
-	if (sc->sc_flags & UKBD_FLAG_POLLING) {
-		if (!mtx_owned(&Giant)) {
-			/* XXX cludge */
-			int retval;
-			mtx_lock(&Giant);
-			retval = ukbd_check_char(kbd);
-			mtx_unlock(&Giant);
-			return (retval);
-		}
-	} else {
-		/* XXX the keyboard layer requires Giant */
-		if (!mtx_owned(&Giant))
-			return (0);
-	}
-
-	/* check if key belongs to this thread */
-	if (ukbd_polls_other_thread(sc))
+	if (!KBD_IS_ACTIVE(kbd))
 		return (0);
 
 	if ((sc->sc_composed_char > 0) &&
@@ -1505,39 +1465,34 @@ ukbd_check_char(keyboard_t *kbd)
 	return (ukbd_check(kbd));
 }
 
+static int
+ukbd_check_char(keyboard_t *kbd)
+{
+	int result;
+
+	UKBD_LOCK();
+	result = ukbd_check_char_locked(kbd);
+	UKBD_UNLOCK();
+
+	return (result);
+}
 
 /* read one byte from the keyboard if it's allowed */
+/* Currently unused. */
 static int
 ukbd_read(keyboard_t *kbd, int wait)
 {
 	struct ukbd_softc *sc = kbd->kb_data;
 	int32_t usbcode;
-
 #ifdef UKBD_EMULATE_ATSCANCODE
 	uint32_t keycode;
 	uint32_t scancode;
 
 #endif
-	if (!KBD_IS_ACTIVE(kbd))
-		return (-1);
 
-	if (sc->sc_flags & UKBD_FLAG_POLLING) {
-		if (!mtx_owned(&Giant)) {
-			/* XXX cludge */
-			int retval;
-			mtx_lock(&Giant);
-			retval = ukbd_read(kbd, wait);
-			mtx_unlock(&Giant);
-			return (retval);
-		}
-	} else {
-		/* XXX the keyboard layer requires Giant */
-		if (!mtx_owned(&Giant))
-			return (-1);
-	}
+	UKBD_CTX_LOCK_ASSERT();
 
-	/* check if key belongs to this thread */
-	if (ukbd_polls_other_thread(sc))
+	if (!KBD_IS_ACTIVE(kbd))
 		return (-1);
 
 #ifdef UKBD_EMULATE_ATSCANCODE
@@ -1574,38 +1529,19 @@ ukbd_read(keyboard_t *kbd, int wait)
 
 /* read char from the keyboard */
 static uint32_t
-ukbd_read_char(keyboard_t *kbd, int wait)
+ukbd_read_char_locked(keyboard_t *kbd, int wait)
 {
 	struct ukbd_softc *sc = kbd->kb_data;
 	uint32_t action;
 	uint32_t keycode;
 	int32_t usbcode;
-
 #ifdef UKBD_EMULATE_ATSCANCODE
 	uint32_t scancode;
-
 #endif
 
-	if (!KBD_IS_ACTIVE(kbd))
-		return (NOKEY);
-
-	if (sc->sc_flags & UKBD_FLAG_POLLING) {
-		if (!mtx_owned(&Giant)) {
-			/* XXX cludge */
-			int retval;
-			mtx_lock(&Giant);
-			retval = ukbd_read_char(kbd, wait);
-			mtx_unlock(&Giant);
-			return (retval);
-		}
-	} else {
-		/* XXX the keyboard layer requires Giant */
-		if (!mtx_owned(&Giant))
-			return (NOKEY);
-	}
+	UKBD_CTX_LOCK_ASSERT();
 
-	/* check if key belongs to this thread */
-	if (ukbd_polls_other_thread(sc))
+	if (!KBD_IS_ACTIVE(kbd))
 		return (NOKEY);
 
 next_code:
@@ -1782,39 +1718,32 @@ errkey:
 	return (ERRKEY);
 }
 
+/* Currently wait is always false. */
+static uint32_t
+ukbd_read_char(keyboard_t *kbd, int wait)
+{
+	uint32_t keycode;
+
+	UKBD_LOCK();
+	keycode = ukbd_read_char_locked(kbd, wait);
+	UKBD_UNLOCK();
+
+	return (keycode);
+}
+
 /* some useful control functions */
 static int
-ukbd_ioctl(keyboard_t *kbd, u_long cmd, caddr_t arg)
+ukbd_ioctl_locked(keyboard_t *kbd, u_long cmd, caddr_t arg)
 {
 	struct ukbd_softc *sc = kbd->kb_data;
 	int i;
-
 #if defined(COMPAT_FREEBSD6) || defined(COMPAT_FREEBSD5) || \
     defined(COMPAT_FREEBSD4) || defined(COMPAT_43)
 	int ival;
 
 #endif
-	if (!mtx_owned(&Giant)) {
-		/*
-		 * XXX big problem: If scroll lock is pressed and "printf()"
-		 * is called, the CPU will get here, to un-scroll lock the
-		 * keyboard. But if "printf()" acquires the "Giant" lock,
-		 * there will be a locking order reversal problem, so the
-		 * keyboard system must get out of "Giant" first, before the
-		 * CPU can proceed here ...
-		 */
-		switch (cmd) {
-		case KDGKBMODE:
-		case KDSKBMODE:
-			/* workaround for Geli */
-			mtx_lock(&Giant);
-			i = ukbd_ioctl(kbd, cmd, arg);
-			mtx_unlock(&Giant);
-			return (i);
-		default:
-			return (EINVAL);
-		}
-	}
+
+	UKBD_LOCK_ASSERT();
 
 	switch (cmd) {
 	case KDGKBMODE:		/* get keyboard mode */
@@ -1839,7 +1768,7 @@ ukbd_ioctl(keyboard_t *kbd, u_long cmd, caddr_t arg)
 		case K_RAW:
 		case K_CODE:
 			if (sc->sc_mode != *(int *)arg) {
-				if (ukbd_is_polling(sc) == 0)
+				if ((sc->sc_flags & UKBD_FLAG_POLLING) == 0)
 					ukbd_clear_state(kbd);
 				sc->sc_mode = *(int *)arg;
 			}
@@ -1943,19 +1872,44 @@ ukbd_ioctl(keyboard_t *kbd, u_long cmd, caddr_t arg)
 	return (0);
 }
 
+static int
+ukbd_ioctl(keyboard_t *kbd, u_long cmd, caddr_t arg)
+{
+	int result;
+
+	/*
+	 * XXX KDGKBSTATE, KDSKBSTATE and KDSETLED can be called from any
+	 * context where printf(9) can be called, which among other things
+	 * includes interrupt filters and threads with any kinds of locks
+	 * already held.  For this reason it would be dangerous to acquire
+	 * the Giant here unconditionally.  On the other hand we have to
+	 * have it to handle the ioctl.
+	 * So we make our best effort to auto-detect whether we can grab
+	 * the Giant or not.  Blame syscons(4) for this.
+	 */
+	switch (cmd) {
+	case KDGKBSTATE:
+	case KDSKBSTATE:
+	case KDSETLED:
+		if (!mtx_owned(&Giant) && !SCHEDULER_STOPPED())
+			return (EDEADLK);	/* best I could come up with */
+		/* FALLTHROUGH */
+	default:
+		UKBD_LOCK();
+		result = ukbd_ioctl_locked(kbd, cmd, arg);
+		UKBD_UNLOCK();
+		return (result);
+	}
+}
+
+
 /* clear the internal state of the keyboard */
 static void
 ukbd_clear_state(keyboard_t *kbd)
 {
 	struct ukbd_softc *sc = kbd->kb_data;
 
-	if (!mtx_owned(&Giant)) {
-		/* XXX cludge */
-		mtx_lock(&Giant);
-		ukbd_clear_state(kbd);
-		mtx_unlock(&Giant);
-		return;
-	}
+	UKBD_CTX_LOCK_ASSERT();
 
 	sc->sc_flags &= ~(UKBD_FLAG_COMPOSE | UKBD_FLAG_POLLING);
 	sc->sc_state &= LOCK_MASK;	/* preserve locking key state */
@@ -1986,43 +1940,11 @@ ukbd_set_state(keyboard_t *kbd, void *buf, size_t len)
 }
 
 static int
-ukbd_is_polling(struct ukbd_softc *sc)
-{
-	int delta;
-
-	if (sc->sc_flags & UKBD_FLAG_POLLING)
-		return (1);	/* polling */
-
-	delta = ticks - sc->sc_poll_tick_last;
-	if ((delta < 0) || (delta >= hz)) {
-		sc->sc_poll_detected = 0;
-		return (0);		/* not polling */
-	}
-
-	return (sc->sc_poll_detected);
-}
-
-static int
-ukbd_polls_other_thread(struct ukbd_softc *sc)
-{
-	return (ukbd_is_polling(sc) &&
-	    (sc->sc_poll_thread != curthread));
-}
-
-static int
 ukbd_poll(keyboard_t *kbd, int on)
 {
 	struct ukbd_softc *sc = kbd->kb_data;
 
-	if (!mtx_owned(&Giant)) {
-		/* XXX cludge */
-		int retval;
-		mtx_lock(&Giant);
-		retval = ukbd_poll(kbd, on);
-		mtx_unlock(&Giant);
-		return (retval);
-	}
-
+	UKBD_LOCK();
 	if (on) {
 		sc->sc_flags |= UKBD_FLAG_POLLING;
 		sc->sc_poll_thread = curthread;
@@ -2030,6 +1952,8 @@ ukbd_poll(keyboard_t *kbd, int on)
 		sc->sc_flags &= ~UKBD_FLAG_POLLING;
 		ukbd_start_timer(sc);	/* start timer */
 	}
+	UKBD_UNLOCK();
+
 	return (0);
 }
 
@@ -2038,6 +1962,8 @@ ukbd_poll(keyboard_t *kbd, int on)
 static void
 ukbd_set_leds(struct ukbd_softc *sc, uint8_t leds)
 {
+
+	UKBD_LOCK_ASSERT();
 	DPRINTF("leds=0x%02x\n", leds);
 
 	sc->sc_leds = leds;
diff --git a/sys/dev/usb/net/if_aue.c b/sys/dev/usb/net/if_aue.c
index a14f233..fdee6b7 100644
--- a/sys/dev/usb/net/if_aue.c
+++ b/sys/dev/usb/net/if_aue.c
@@ -254,15 +254,12 @@ static device_method_t aue_methods[] = {
 	DEVMETHOD(device_attach, aue_attach),
 	DEVMETHOD(device_detach, aue_detach),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child, bus_generic_print_child),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg, aue_miibus_readreg),
 	DEVMETHOD(miibus_writereg, aue_miibus_writereg),
 	DEVMETHOD(miibus_statchg, aue_miibus_statchg),
 
-	{0, 0}
+	DEVMETHOD_END
 };
 
 static driver_t aue_driver = {
diff --git a/sys/dev/usb/net/if_axe.c b/sys/dev/usb/net/if_axe.c
index 0d18f2b..02bb358 100644
--- a/sys/dev/usb/net/if_axe.c
+++ b/sys/dev/usb/net/if_axe.c
@@ -151,6 +151,7 @@ static const STRUCT_USB_HOST_ID axe_devs[] = {
 	AXE_DEV(ASIX, AX88772, AXE_FLAG_772),
 	AXE_DEV(ASIX, AX88772A, AXE_FLAG_772A),
 	AXE_DEV(ASIX, AX88772B, AXE_FLAG_772B),
+	AXE_DEV(ASIX, AX88772B_1, AXE_FLAG_772B),
 	AXE_DEV(ATEN, UC210T, 0),
 	AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178),
 	AXE_DEV(BILLIONTON, USB2AR, 0),
@@ -251,15 +252,12 @@ static device_method_t axe_methods[] = {
 	DEVMETHOD(device_attach, axe_attach),
 	DEVMETHOD(device_detach, axe_detach),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child, bus_generic_print_child),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg, axe_miibus_readreg),
 	DEVMETHOD(miibus_writereg, axe_miibus_writereg),
 	DEVMETHOD(miibus_statchg, axe_miibus_statchg),
 
-	{0, 0}
+	DEVMETHOD_END
 };
 
 static driver_t axe_driver = {
diff --git a/sys/dev/usb/net/if_mos.c b/sys/dev/usb/net/if_mos.c
index 11cb962..7dd889e 100644
--- a/sys/dev/usb/net/if_mos.c
+++ b/sys/dev/usb/net/if_mos.c
@@ -220,15 +220,12 @@ static device_method_t mos_methods[] = {
 	DEVMETHOD(device_attach, mos_attach),
 	DEVMETHOD(device_detach, mos_detach),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child, bus_generic_print_child),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg, mos_miibus_readreg),
 	DEVMETHOD(miibus_writereg, mos_miibus_writereg),
 	DEVMETHOD(miibus_statchg, mos_miibus_statchg),
 
-	{0, 0}
+	DEVMETHOD_END
 };
 
 static driver_t mos_driver = {
diff --git a/sys/dev/usb/net/if_rue.c b/sys/dev/usb/net/if_rue.c
index e4fd035..a870676 100644
--- a/sys/dev/usb/net/if_rue.c
+++ b/sys/dev/usb/net/if_rue.c
@@ -186,15 +186,12 @@ static device_method_t rue_methods[] = {
 	DEVMETHOD(device_attach, rue_attach),
 	DEVMETHOD(device_detach, rue_detach),
 
-	/* Bus interface */
-	DEVMETHOD(bus_print_child, bus_generic_print_child),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg, rue_miibus_readreg),
 	DEVMETHOD(miibus_writereg, rue_miibus_writereg),
 	DEVMETHOD(miibus_statchg, rue_miibus_statchg),
 
-	{0, 0}
+	DEVMETHOD_END
 };
 
 static driver_t rue_driver = {
diff --git a/sys/dev/usb/net/if_udav.c b/sys/dev/usb/net/if_udav.c
index 3fa3d15..8160a3b 100644
--- a/sys/dev/usb/net/if_udav.c
+++ b/sys/dev/usb/net/if_udav.c
@@ -145,15 +145,12 @@ static device_method_t udav_methods[] = {
 	DEVMETHOD(device_attach, udav_attach),
 	DEVMETHOD(device_detach, udav_detach),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child, bus_generic_print_child),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg, udav_miibus_readreg),
 	DEVMETHOD(miibus_writereg, udav_miibus_writereg),
 	DEVMETHOD(miibus_statchg, udav_miibus_statchg),
 
-	{0, 0}
+	DEVMETHOD_END
 };
 
 static driver_t udav_driver = {
diff --git a/sys/dev/usb/net/ruephy.c b/sys/dev/usb/net/ruephy.c
index 64150a5..839c022 100644
--- a/sys/dev/usb/net/ruephy.c
+++ b/sys/dev/usb/net/ruephy.c
@@ -61,7 +61,7 @@ static device_method_t ruephy_methods[] = {
 	DEVMETHOD(device_attach,	ruephy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t ruephy_devclass;
diff --git a/sys/dev/usb/quirk/usb_quirk.c b/sys/dev/usb/quirk/usb_quirk.c
index b0d7a7d..03ab038 100644
--- a/sys/dev/usb/quirk/usb_quirk.c
+++ b/sys/dev/usb/quirk/usb_quirk.c
@@ -248,6 +248,7 @@ static struct usb_quirk_entry usb_quirks[USB_DEV_QUIRKS_MAX] = {
 	USB_QUIRK(MICROTECH, DPCM, 0x0000, 0xffff, UQ_MSC_FORCE_WIRE_CBI,
 	    UQ_MSC_FORCE_PROTO_SCSI, UQ_MSC_NO_TEST_UNIT_READY,
 	    UQ_MSC_NO_START_STOP),
+	USB_QUIRK(MICRON, REALSSD, 0x0000, 0xffff, UQ_MSC_NO_SYNC_CACHE),
 	USB_QUIRK(MICROTECH, SCSIDB25, 0x0000, 0xffff, UQ_MSC_FORCE_WIRE_BBB,
 	    UQ_MSC_FORCE_PROTO_SCSI),
 	USB_QUIRK(MICROTECH, SCSIHD50, 0x0000, 0xffff, UQ_MSC_FORCE_WIRE_BBB,
diff --git a/sys/dev/usb/serial/usb_serial.c b/sys/dev/usb/serial/usb_serial.c
index a3e6ffb..e63a0aa 100644
--- a/sys/dev/usb/serial/usb_serial.c
+++ b/sys/dev/usb/serial/usb_serial.c
@@ -1308,6 +1308,8 @@ static cn_init_t ucom_cninit;
 static cn_term_t ucom_cnterm;
 static cn_getc_t ucom_cngetc;
 static cn_putc_t ucom_cnputc;
+static cn_grab_t ucom_cngrab;
+static cn_ungrab_t ucom_cnungrab;
 
 CONSOLE_DRIVER(ucom);
 
@@ -1332,6 +1334,16 @@ ucom_cnterm(struct consdev  *cp)
 {
 }
 
+static void
+ucom_cngrab(struct consdev *cp)
+{
+}
+
+static void
+ucom_cnungrab(struct consdev *cp)
+{
+}
+
 static int
 ucom_cngetc(struct consdev *cd)
 {
diff --git a/sys/dev/usb/template/usb_template.c b/sys/dev/usb/template/usb_template.c
index 209016a..b929665 100644
--- a/sys/dev/usb/template/usb_template.c
+++ b/sys/dev/usb/template/usb_template.c
@@ -260,7 +260,7 @@ usb_make_endpoint_desc(struct usb_temp_setup *temp,
 					ed->bInterval = 1;	/* 1 ms */
 					break;
 				default:
-					ed->bInterval = 8;	/* 8*125 us */
+					ed->bInterval = 4;	/* 1 ms */
 					break;
 				}
 				break;
diff --git a/sys/dev/usb/template/usb_template_kbd.c b/sys/dev/usb/template/usb_template_kbd.c
index 8928c06..6295825 100644
--- a/sys/dev/usb/template/usb_template_kbd.c
+++ b/sys/dev/usb/template/usb_template_kbd.c
@@ -89,9 +89,9 @@ static const struct usb_temp_packet_size keyboard_intr_mps = {
 };
 
 static const struct usb_temp_interval keyboard_intr_interval = {
-	.bInterval[USB_SPEED_LOW] = 2,	/* ms */
-	.bInterval[USB_SPEED_FULL] = 2,
-	.bInterval[USB_SPEED_HIGH] = 2 * 8,
+	.bInterval[USB_SPEED_LOW] = 2,	/* 2 ms */
+	.bInterval[USB_SPEED_FULL] = 2,	/* 2 ms */
+	.bInterval[USB_SPEED_HIGH] = 5,	/* 2 ms */
 };
 
 /* The following HID descriptor was dumped from a HP keyboard. */
diff --git a/sys/dev/usb/template/usb_template_modem.c b/sys/dev/usb/template/usb_template_modem.c
index 6e0f940..abc6f26 100644
--- a/sys/dev/usb/template/usb_template_modem.c
+++ b/sys/dev/usb/template/usb_template_modem.c
@@ -98,9 +98,9 @@ static const struct usb_temp_packet_size modem_intr_mps = {
 };
 
 static const struct usb_temp_interval modem_intr_interval = {
-	.bInterval[USB_SPEED_LOW] = 10,
-	.bInterval[USB_SPEED_FULL] = 10,
-	.bInterval[USB_SPEED_HIGH] = 10 * 8,
+	.bInterval[USB_SPEED_LOW] = 8,	/* 8ms */
+	.bInterval[USB_SPEED_FULL] = 8,	/* 8ms */
+	.bInterval[USB_SPEED_HIGH] = 7,	/* 8ms */
 };
 
 static const struct usb_temp_endpoint_desc modem_ep_0 = {
diff --git a/sys/dev/usb/template/usb_template_mouse.c b/sys/dev/usb/template/usb_template_mouse.c
index 3ff0fb0..628c9a5 100644
--- a/sys/dev/usb/template/usb_template_mouse.c
+++ b/sys/dev/usb/template/usb_template_mouse.c
@@ -101,9 +101,9 @@ static const struct usb_temp_packet_size mouse_intr_mps = {
 };
 
 static const struct usb_temp_interval mouse_intr_interval = {
-	.bInterval[USB_SPEED_LOW] = 2,
-	.bInterval[USB_SPEED_FULL] = 2,
-	.bInterval[USB_SPEED_HIGH] = 2 * 8,
+	.bInterval[USB_SPEED_LOW] = 2,		/* 2ms */
+	.bInterval[USB_SPEED_FULL] = 2,		/* 2ms */
+	.bInterval[USB_SPEED_HIGH] = 5,		/* 2ms */
 };
 
 static const struct usb_temp_endpoint_desc mouse_ep_0 = {
diff --git a/sys/dev/usb/usb_bus.h b/sys/dev/usb/usb_bus.h
index 1dd9d6a..07207cf 100644
--- a/sys/dev/usb/usb_bus.h
+++ b/sys/dev/usb/usb_bus.h
@@ -69,6 +69,9 @@ struct usb_bus {
 	struct usb_bus_msg explore_msg[2];
 	struct usb_bus_msg detach_msg[2];
 	struct usb_bus_msg attach_msg[2];
+	struct usb_bus_msg suspend_msg[2];
+	struct usb_bus_msg resume_msg[2];
+	struct usb_bus_msg shutdown_msg[2];
 	/*
 	 * This mutex protects the USB hardware:
 	 */
@@ -98,7 +101,8 @@ struct usb_bus {
 	enum usb_revision usbrev;	/* USB revision. See "USB_REV_XXX". */
 
 	uint8_t	devices_max;		/* maximum number of USB devices */
-	uint8_t	do_probe;		/* set if USB BUS should be re-probed */
+	uint8_t	do_probe;		/* set if USB should be re-probed */
+	uint8_t no_explore;		/* don't explore USB ports */
 
 	/* 
 	 * The scratch area can only be used inside the explore thread
diff --git a/sys/dev/usb/usb_controller.h b/sys/dev/usb/usb_controller.h
index 6b15dab..4ffc041 100644
--- a/sys/dev/usb/usb_controller.h
+++ b/sys/dev/usb/usb_controller.h
@@ -66,7 +66,7 @@ struct usb_bus_methods {
 	void    (*device_suspend) (struct usb_device *);
 	void    (*device_resume) (struct usb_device *);
 	void    (*set_hw_power) (struct usb_bus *);
-
+	void    (*set_hw_power_sleep) (struct usb_bus *, uint32_t);
 	/*
 	 * The following flag is set if one or more control transfers are
 	 * active:
@@ -92,6 +92,18 @@ struct usb_bus_methods {
 	 * are present on the given USB bus:
 	 */
 #define	USB_HW_POWER_NON_ROOT_HUB 0x10
+	/*
+	 * The following flag is set if we are suspending
+	 */
+#define	USB_HW_POWER_SUSPEND 0x20
+	/*
+	 * The following flag is set if we are resuming
+	 */
+#define	USB_HW_POWER_RESUME 0x40
+	/*
+	 * The following flag is set if we are shutting down
+	 */
+#define	USB_HW_POWER_SHUTDOWN 0x60
 
 	/* USB Device mode only - Mandatory */
 
diff --git a/sys/dev/usb/usb_hub.c b/sys/dev/usb/usb_hub.c
index 8652661..168e9eb 100644
--- a/sys/dev/usb/usb_hub.c
+++ b/sys/dev/usb/usb_hub.c
@@ -707,6 +707,13 @@ uhub_explore(struct usb_device *udev)
 		DPRINTF("Device is suspended!\n");
 		return (0);
 	}
+
+	/*
+	 * Make sure we don't race against user-space applications
+	 * like LibUSB:
+	 */
+	usbd_enum_lock(udev);
+
 	for (x = 0; x != hub->nports; x++) {
 		up = hub->ports + x;
 		portno = x + 1;
@@ -784,6 +791,8 @@ uhub_explore(struct usb_device *udev)
 		up->restartcnt = 0;
 	}
 
+	usbd_enum_unlock(udev);
+
 	/* initial status checked */
 	sc->sc_flags |= UHUB_FLAG_DID_EXPLORE;
 
diff --git a/sys/dev/usb/usb_if.m b/sys/dev/usb/usb_if.m
index 926a237..b24fc2b 100644
--- a/sys/dev/usb/usb_if.m
+++ b/sys/dev/usb/usb_if.m
@@ -54,3 +54,13 @@ METHOD int handle_request {
 	uint16_t offset; /* data offset */
 	uint8_t *pstate; /* set if transfer is complete, see USB_HR_XXX */
 };
+
+# Take controller from BIOS
+#
+# Return values:
+# 0: Success
+# Else: Failure
+#
+METHOD int take_controller {
+	device_t dev;
+};
diff --git a/sys/dev/usb/usb_msctest.c b/sys/dev/usb/usb_msctest.c
index 7f33014..a6b01b8 100644
--- a/sys/dev/usb/usb_msctest.c
+++ b/sys/dev/usb/usb_msctest.c
@@ -477,7 +477,7 @@ bbb_command_start(struct bbb_transfer *sc, uint8_t dir, uint8_t lun,
 	sc->cmd_len = cmd_len;
 	memset(&sc->cbw.CBWCDB, 0, sizeof(sc->cbw.CBWCDB));
 	memcpy(&sc->cbw.CBWCDB, cmd_ptr, cmd_len);
-	DPRINTFN(1, "SCSI cmd = %*D\n", (int)cmd_len, &sc->cbw.CBWCDB, ":");
+	DPRINTFN(1, "SCSI cmd = %*D\n", (int)cmd_len, (char *)sc->cbw.CBWCDB, ":");
 
 	mtx_lock(&sc->mtx);
 	usbd_transfer_start(sc->xfer[sc->state]);
diff --git a/sys/dev/usb/usb_transfer.c b/sys/dev/usb/usb_transfer.c
index 6f4b678..4a5cfbd 100644
--- a/sys/dev/usb/usb_transfer.c
+++ b/sys/dev/usb/usb_transfer.c
@@ -2150,7 +2150,7 @@ usbd_callback_wrapper(struct usb_xfer_queue *pq)
 	struct usb_xfer_root *info = xfer->xroot;
 
 	USB_BUS_LOCK_ASSERT(info->bus, MA_OWNED);
-	if (!mtx_owned(info->xfer_mtx)) {
+	if (!mtx_owned(info->xfer_mtx) && !SCHEDULER_STOPPED()) {
 		/*
 	       	 * Cases that end up here:
 		 *
@@ -3119,14 +3119,14 @@ usbd_transfer_poll(struct usb_xfer **ppxfer, uint16_t max)
 
 		/* make sure that the BUS mutex is not locked */
 		drop_bus = 0;
-		while (mtx_owned(&xroot->udev->bus->bus_mtx)) {
+		while (mtx_owned(&xroot->udev->bus->bus_mtx) && !SCHEDULER_STOPPED()) {
 			mtx_unlock(&xroot->udev->bus->bus_mtx);
 			drop_bus++;
 		}
 
 		/* make sure that the transfer mutex is not locked */
 		drop_xfer = 0;
-		while (mtx_owned(xroot->xfer_mtx)) {
+		while (mtx_owned(xroot->xfer_mtx) && !SCHEDULER_STOPPED()) {
 			mtx_unlock(xroot->xfer_mtx);
 			drop_xfer++;
 		}
diff --git a/sys/dev/usb/usb_transfer.h b/sys/dev/usb/usb_transfer.h
index 71157ca..f035240 100644
--- a/sys/dev/usb/usb_transfer.h
+++ b/sys/dev/usb/usb_transfer.h
@@ -28,6 +28,120 @@
 #define	_USB_TRANSFER_H_
 
 /*
+ * Definition of internal USB transfer states:
+ * ===========================================
+ *
+ * The main reason there are many USB states is that we are allowed to
+ * cancel USB transfers, then start the USB transfer again and that
+ * this state transaction cannot always be done in a single atomic
+ * operation without blocking the calling thread. One reason for this
+ * is that the USB hardware sometimes needs to wait for DMA
+ * controllers to finish which is done asynchronously and grows the
+ * statemachine.
+ *
+ * When extending the following statemachine there are basically two
+ * things you should think about: Which states should be executed or
+ * modified in case of USB transfer stop and which states should be
+ * executed or modified in case of USB transfer start. Also respect
+ * the "can_cancel_immed" flag which basically tells if you can go
+ * directly from a wait state to the cancelling states.
+ */
+
+enum {
+	/* XFER start execute state */
+
+	/* USB_ST_SETUP = 0 (already defined) */
+
+	/* XFER transferred execute state */
+
+	/* USB_ST_TRANSFERRED = 1 (already defined) */
+
+	/* XFER error execute state */
+
+	/* USB_ST_ERROR = 2 (already defined) */
+
+	/* XFER restart after error execute state */
+
+	USB_ST_RESTART = 8,
+
+	/* XFER transfer idle state */
+
+	USB_ST_WAIT_SETUP,
+
+	/* Other XFER execute states */
+
+	USB_ST_PIPE_OPEN = 16,
+	USB_ST_PIPE_OPEN_ERROR,
+	USB_ST_PIPE_OPEN_RESTART,
+
+	USB_ST_BDMA_LOAD,
+	USB_ST_BDMA_LOAD_ERROR,
+	USB_ST_BDMA_LOAD_RESTART,
+
+	USB_ST_IVAL_DLY,
+	USB_ST_IVAL_DLY_ERROR,
+	USB_ST_IVAL_DLY_RESTART,
+
+	USB_ST_PIPE_STALL,
+	USB_ST_PIPE_STALL_ERROR,
+	USB_ST_PIPE_STALL_RESTART,
+
+	USB_ST_ENTER,
+	USB_ST_ENTER_ERROR,
+	USB_ST_ENTER_RESTART,
+
+	USB_ST_START,
+	USB_ST_START_ERROR,
+	USB_ST_START_RESTART,
+
+	USB_ST_PIPE_CLOSE,
+	USB_ST_PIPE_CLOSE_ERROR,
+	USB_ST_PIPE_CLOSE_RESTART,
+
+	USB_ST_BDMA_DLY,
+	USB_ST_BDMA_DLY_ERROR,
+	USB_ST_BDMA_DLY_RESTART,
+
+	/* XFER transfer wait states */
+
+	USB_ST_WAIT_PIPE_OPEN = 64,
+	USB_ST_WAIT_PIPE_OPEN_ERROR,
+	USB_ST_WAIT_PIPE_OPEN_RESTART,
+
+	USB_ST_WAIT_BDMA_LOAD,
+	USB_ST_WAIT_BDMA_LOAD_ERROR,
+	USB_ST_WAIT_BDMA_LOAD_RESTART,
+
+	USB_ST_WAIT_IVAL_DLY,
+	USB_ST_WAIT_IVAL_DLY_ERROR,
+	USB_ST_WAIT_IVAL_DLY_RESTART,
+
+	USB_ST_WAIT_PIPE_STALL,
+	USB_ST_WAIT_PIPE_STALL_ERROR,
+	USB_ST_WAIT_PIPE_STALL_RESTART,
+
+	USB_ST_WAIT_ENTER,
+	USB_ST_WAIT_ENTER_ERROR,
+	USB_ST_WAIT_ENTER_RESTART,
+
+	USB_ST_WAIT_START,
+	USB_ST_WAIT_START_ERROR,
+	USB_ST_WAIT_START_RESTART,
+
+	USB_ST_WAIT_PIPE_CLOSE,
+	USB_ST_WAIT_PIPE_CLOSE_ERROR,
+	USB_ST_WAIT_PIPE_CLOSE_RESTART,
+
+	USB_ST_WAIT_BDMA_DLY,
+	USB_ST_WAIT_BDMA_DLY_ERROR,
+	USB_ST_WAIT_BDMA_DLY_RESTART,
+
+	USB_ST_WAIT_TRANSFERRED,
+	USB_ST_WAIT_TRANSFERRED_ERROR,
+	USB_ST_WAIT_TRANSFERRED_RESTART,
+};
+
+/*
  * The following structure defines the messages that is used to signal
  * the "done_p" USB process.
  */
diff --git a/sys/dev/usb/usbdevs b/sys/dev/usb/usbdevs
index 4e3af74..0ca5b65 100644
--- a/sys/dev/usb/usbdevs
+++ b/sys/dev/usb/usbdevs
@@ -317,6 +317,7 @@ vendor ACTLABS		0x061c	Act Labs
 vendor ALARIS		0x0620	Alaris
 vendor APEX		0x0624	Apex
 vendor CREATIVE3	0x062a	Creative Labs
+vendor MICRON		0x0634	Micron Technology
 vendor VIVITAR		0x0636	Vivitar
 vendor GUNZE		0x0637	Gunze Electronics USA
 vendor AVISION		0x0638	Avision
@@ -1049,6 +1050,7 @@ product ASIX AX88178		0x1780	AX88178
 product ASIX AX88772		0x7720	AX88772
 product ASIX AX88772A		0x772a	AX88772A USB 2.0 10/100 Ethernet
 product ASIX AX88772B		0x772b	AX88772B USB 2.0 10/100 Ethernet
+product ASIX AX88772B_1		0x7e2b	AX88772B USB 2.0 10/100 Ethernet
 
 /* ASUS products */
 product ASUS2 USBN11		0x0b05	USB-N11
@@ -2226,6 +2228,9 @@ product MSI RT3070_7		0x899a	RT3070
 product MSI RT2573_3		0xa861	RT2573
 product MSI RT2573_4		0xa874	RT2573
 
+/* Micron products */
+product MICRON REALSSD		0x0655	Real SSD eUSB
+
 /* Microsoft products */
 product MICROSOFT SIDEPREC	0x0008	SideWinder Precision Pro
 product MICROSOFT INTELLIMOUSE	0x0009	IntelliMouse
diff --git a/sys/dev/usb/wlan/if_rum.c b/sys/dev/usb/wlan/if_rum.c
index 8cf9f47..a809819 100644
--- a/sys/dev/usb/wlan/if_rum.c
+++ b/sys/dev/usb/wlan/if_rum.c
@@ -152,9 +152,9 @@ static usb_callback_t rum_bulk_write_callback;
 static usb_error_t	rum_do_request(struct rum_softc *sc,
 			    struct usb_device_request *req, void *data);
 static struct ieee80211vap *rum_vap_create(struct ieee80211com *,
-			    const char name[IFNAMSIZ], int unit, int opmode,
-			    int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
-			    const uint8_t mac[IEEE80211_ADDR_LEN]);
+			    const char [IFNAMSIZ], int, enum ieee80211_opmode,
+			    int, const uint8_t [IEEE80211_ADDR_LEN],
+			    const uint8_t [IEEE80211_ADDR_LEN]);
 static void		rum_vap_delete(struct ieee80211vap *);
 static void		rum_tx_free(struct rum_tx_data *, int);
 static void		rum_setup_tx_list(struct rum_softc *);
@@ -580,10 +580,10 @@ rum_do_request(struct rum_softc *sc,
 }
 
 static struct ieee80211vap *
-rum_vap_create(struct ieee80211com *ic,
-	const char name[IFNAMSIZ], int unit, int opmode, int flags,
-	const uint8_t bssid[IEEE80211_ADDR_LEN],
-	const uint8_t mac[IEEE80211_ADDR_LEN])
+rum_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
+    enum ieee80211_opmode opmode, int flags,
+    const uint8_t bssid[IEEE80211_ADDR_LEN],
+    const uint8_t mac[IEEE80211_ADDR_LEN])
 {
 	struct rum_softc *sc = ic->ic_ifp->if_softc;
 	struct rum_vap *rvp;
diff --git a/sys/dev/usb/wlan/if_run.c b/sys/dev/usb/wlan/if_run.c
index ad6c736..8461330 100644
--- a/sys/dev/usb/wlan/if_run.c
+++ b/sys/dev/usb/wlan/if_run.c
@@ -315,9 +315,9 @@ static usb_callback_t	run_bulk_tx_callback5;
 static void	run_bulk_tx_callbackN(struct usb_xfer *xfer,
 		    usb_error_t error, unsigned int index);
 static struct ieee80211vap *run_vap_create(struct ieee80211com *,
-		    const char name[IFNAMSIZ], int unit, int opmode, int flags,
-		    const uint8_t bssid[IEEE80211_ADDR_LEN], const uint8_t
-		    mac[IEEE80211_ADDR_LEN]);
+		    const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
+		    const uint8_t [IEEE80211_ADDR_LEN],
+		    const uint8_t [IEEE80211_ADDR_LEN]);
 static void	run_vap_delete(struct ieee80211vap *);
 static void	run_cmdq_cb(void *, int);
 static void	run_setup_tx_list(struct run_softc *,
@@ -748,8 +748,8 @@ run_detach(device_t self)
 }
 
 static struct ieee80211vap *
-run_vap_create(struct ieee80211com *ic,
-    const char name[IFNAMSIZ], int unit, int opmode, int flags,
+run_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
+    enum ieee80211_opmode opmode, int flags,
     const uint8_t bssid[IEEE80211_ADDR_LEN],
     const uint8_t mac[IEEE80211_ADDR_LEN])
 {
@@ -2720,7 +2720,6 @@ run_bulk_tx_callbackN(struct usb_xfer *xfer, usb_error_t error, unsigned int ind
 	struct run_endpoint_queue *pq = &sc->sc_epq[index];
 	struct mbuf *m;
 	usb_frlength_t size;
-	unsigned int len;
 	int actlen;
 	int sumlen;
 
@@ -2750,7 +2749,8 @@ tr_setup:
 		STAILQ_REMOVE_HEAD(&pq->tx_qh, next);
 
 		m = data->m;
-		if (m->m_pkthdr.len > RUN_MAX_TXSZ) {
+		if ((m->m_pkthdr.len +
+		    sizeof(data->desc) + 3 + 8) > RUN_MAX_TXSZ) {
 			DPRINTF("data overflow, %u bytes\n",
 			    m->m_pkthdr.len);
 
@@ -2765,6 +2765,14 @@ tr_setup:
 		size = sizeof(data->desc);
 		usbd_copy_in(pc, 0, &data->desc, size);
 		usbd_m_copy_in(pc, size, m, 0, m->m_pkthdr.len);
+		size += m->m_pkthdr.len;
+		/*
+		 * Align end on a 4-byte boundary, pad 8 bytes (CRC +
+		 * 4-byte padding), and be sure to zero those trailing
+		 * bytes:
+		 */
+		usbd_frame_zero(pc, size, ((-size) & 3) + 8);
+		size += ((-size) & 3) + 8;
 
 		vap = data->ni->ni_vap;
 		if (ieee80211_radiotap_active_vap(vap)) {
@@ -2783,13 +2791,10 @@ tr_setup:
 			ieee80211_radiotap_tx(vap, m);
 		}
 
-		/* align end on a 4-bytes boundary */
-		len = (size + IEEE80211_CRC_LEN + m->m_pkthdr.len + 3) & ~3;
-
-		DPRINTFN(11, "sending frame len=%u xferlen=%u @ index %d\n",
-			m->m_pkthdr.len, len, index);
+		DPRINTFN(11, "sending frame len=%u/%u  @ index %d\n",
+		    m->m_pkthdr.len, size, index);
 
-		usbd_xfer_set_frame_len(xfer, 0, len);
+		usbd_xfer_set_frame_len(xfer, 0, size);
 		usbd_xfer_set_priv(xfer, data);
 
 		usbd_transfer_submit(xfer);
diff --git a/sys/dev/usb/wlan/if_uath.c b/sys/dev/usb/wlan/if_uath.c
index 8bc821b..cfa8494 100644
--- a/sys/dev/usb/wlan/if_uath.c
+++ b/sys/dev/usb/wlan/if_uath.c
@@ -254,9 +254,9 @@ static const struct usb_config uath_usbconfig[UATH_N_XFERS] = {
 };
 
 static struct ieee80211vap *uath_vap_create(struct ieee80211com *,
-		    const char name[IFNAMSIZ], int unit, int opmode,
-		    int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
-		    const uint8_t mac[IEEE80211_ADDR_LEN]);
+		    const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
+		    const uint8_t [IEEE80211_ADDR_LEN],
+		    const uint8_t [IEEE80211_ADDR_LEN]);
 static void	uath_vap_delete(struct ieee80211vap *);
 static int	uath_alloc_cmd_list(struct uath_softc *, struct uath_cmd [],
 		    int, int);
@@ -1065,10 +1065,10 @@ uath_free_tx_data_list(struct uath_softc *sc)
 }
 
 static struct ieee80211vap *
-uath_vap_create(struct ieee80211com *ic,
-	const char name[IFNAMSIZ], int unit, int opmode, int flags,
-	const uint8_t bssid[IEEE80211_ADDR_LEN],
-	const uint8_t mac[IEEE80211_ADDR_LEN])
+uath_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
+    enum ieee80211_opmode opmode, int flags,
+    const uint8_t bssid[IEEE80211_ADDR_LEN],
+    const uint8_t mac[IEEE80211_ADDR_LEN])
 {
 	struct uath_vap *uvp;
 	struct ieee80211vap *vap;
diff --git a/sys/dev/usb/wlan/if_upgt.c b/sys/dev/usb/wlan/if_upgt.c
index 78ac2d9..678e9c0 100644
--- a/sys/dev/usb/wlan/if_upgt.c
+++ b/sys/dev/usb/wlan/if_upgt.c
@@ -138,9 +138,9 @@ static void	upgt_scan_start(struct ieee80211com *);
 static void	upgt_scan_end(struct ieee80211com *);
 static void	upgt_set_channel(struct ieee80211com *);
 static struct ieee80211vap *upgt_vap_create(struct ieee80211com *,
-		    const char name[IFNAMSIZ], int unit, int opmode,
-		    int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
-		    const uint8_t mac[IEEE80211_ADDR_LEN]);
+		    const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
+		    const uint8_t [IEEE80211_ADDR_LEN],
+		    const uint8_t [IEEE80211_ADDR_LEN]);
 static void	upgt_vap_delete(struct ieee80211vap *);
 static void	upgt_update_mcast(struct ifnet *);
 static uint8_t	upgt_rx_rate(struct upgt_softc *, const int);
@@ -1014,10 +1014,10 @@ upgt_set_chan(struct upgt_softc *sc, struct ieee80211_channel *c)
 }
 
 static struct ieee80211vap *
-upgt_vap_create(struct ieee80211com *ic,
-	const char name[IFNAMSIZ], int unit, int opmode, int flags,
-	const uint8_t bssid[IEEE80211_ADDR_LEN],
-	const uint8_t mac[IEEE80211_ADDR_LEN])
+upgt_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
+    enum ieee80211_opmode opmode, int flags,
+    const uint8_t bssid[IEEE80211_ADDR_LEN],
+    const uint8_t mac[IEEE80211_ADDR_LEN])
 {
 	struct upgt_vap *uvp;
 	struct ieee80211vap *vap;
diff --git a/sys/dev/usb/wlan/if_ural.c b/sys/dev/usb/wlan/if_ural.c
index a72da83..945789f 100644
--- a/sys/dev/usb/wlan/if_ural.c
+++ b/sys/dev/usb/wlan/if_ural.c
@@ -131,9 +131,9 @@ static usb_callback_t ural_bulk_write_callback;
 static usb_error_t	ural_do_request(struct ural_softc *sc,
 			    struct usb_device_request *req, void *data);
 static struct ieee80211vap *ural_vap_create(struct ieee80211com *,
-			    const char name[IFNAMSIZ], int unit, int opmode,
-			    int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
-			    const uint8_t mac[IEEE80211_ADDR_LEN]);
+			    const char [IFNAMSIZ], int, enum ieee80211_opmode,
+			    int, const uint8_t [IEEE80211_ADDR_LEN],
+			    const uint8_t [IEEE80211_ADDR_LEN]);
 static void		ural_vap_delete(struct ieee80211vap *);
 static void		ural_tx_free(struct ural_tx_data *, int);
 static void		ural_setup_tx_list(struct ural_softc *);
@@ -568,10 +568,10 @@ ural_do_request(struct ural_softc *sc,
 }
 
 static struct ieee80211vap *
-ural_vap_create(struct ieee80211com *ic,
-	const char name[IFNAMSIZ], int unit, int opmode, int flags,
-	const uint8_t bssid[IEEE80211_ADDR_LEN],
-	const uint8_t mac[IEEE80211_ADDR_LEN])
+ural_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
+    enum ieee80211_opmode opmode, int flags,
+    const uint8_t bssid[IEEE80211_ADDR_LEN],
+    const uint8_t mac[IEEE80211_ADDR_LEN])
 {
 	struct ural_softc *sc = ic->ic_ifp->if_softc;
 	struct ural_vap *uvp;
diff --git a/sys/dev/usb/wlan/if_urtw.c b/sys/dev/usb/wlan/if_urtw.c
index 2a52a8c..1259b2d 100644
--- a/sys/dev/usb/wlan/if_urtw.c
+++ b/sys/dev/usb/wlan/if_urtw.c
@@ -649,9 +649,9 @@ static const struct usb_config urtw_8187l_usbconfig[URTW_8187L_N_XFERS] = {
 };
 
 static struct ieee80211vap *urtw_vap_create(struct ieee80211com *,
-			    const char name[IFNAMSIZ], int unit, int opmode,
-			    int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
-			    const uint8_t mac[IEEE80211_ADDR_LEN]);
+			    const char [IFNAMSIZ], int, enum ieee80211_opmode,
+			    int, const uint8_t [IEEE80211_ADDR_LEN],
+			    const uint8_t [IEEE80211_ADDR_LEN]);
 static void		urtw_vap_delete(struct ieee80211vap *);
 static void		urtw_init(void *);
 static void		urtw_stop(struct ifnet *, int);
@@ -993,10 +993,10 @@ urtw_free_data_list(struct urtw_softc *sc, struct urtw_data data[], int ndata,
 }
 
 static struct ieee80211vap *
-urtw_vap_create(struct ieee80211com *ic,
-	const char name[IFNAMSIZ], int unit, int opmode, int flags,
-	const uint8_t bssid[IEEE80211_ADDR_LEN],
-	const uint8_t mac[IEEE80211_ADDR_LEN])
+urtw_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
+    enum ieee80211_opmode opmode, int flags,
+    const uint8_t bssid[IEEE80211_ADDR_LEN],
+    const uint8_t mac[IEEE80211_ADDR_LEN])
 {
 	struct urtw_vap *uvp;
 	struct ieee80211vap *vap;
@@ -1053,10 +1053,10 @@ urtw_init_locked(void *arg)
 
 	if (!(sc->sc_flags & URTW_INIT_ONCE)) {
 		ret = urtw_alloc_rx_data_list(sc);
-		if (error != 0)
+		if (ret != 0)
 			goto fail;
 		ret = urtw_alloc_tx_data_list(sc);
-		if (error != 0)
+		if (ret != 0)
 			goto fail;
 		sc->sc_flags |= URTW_INIT_ONCE;
 	}
diff --git a/sys/dev/usb/wlan/if_zyd.c b/sys/dev/usb/wlan/if_zyd.c
index 835cdc5..7e2cee9 100644
--- a/sys/dev/usb/wlan/if_zyd.c
+++ b/sys/dev/usb/wlan/if_zyd.c
@@ -118,9 +118,9 @@ static usb_callback_t zyd_bulk_read_callback;
 static usb_callback_t zyd_bulk_write_callback;
 
 static struct ieee80211vap *zyd_vap_create(struct ieee80211com *,
-		    const char name[IFNAMSIZ], int unit, int opmode,
-		    int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
-		    const uint8_t mac[IEEE80211_ADDR_LEN]);
+		    const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
+		    const uint8_t [IEEE80211_ADDR_LEN],
+		    const uint8_t [IEEE80211_ADDR_LEN]);
 static void	zyd_vap_delete(struct ieee80211vap *);
 static void	zyd_tx_free(struct zyd_tx_data *, int);
 static void	zyd_setup_tx_list(struct zyd_softc *);
@@ -456,10 +456,10 @@ zyd_detach(device_t dev)
 }
 
 static struct ieee80211vap *
-zyd_vap_create(struct ieee80211com *ic,
-	const char name[IFNAMSIZ], int unit, int opmode, int flags,
-	const uint8_t bssid[IEEE80211_ADDR_LEN],
-	const uint8_t mac[IEEE80211_ADDR_LEN])
+zyd_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
+    enum ieee80211_opmode opmode, int flags,
+    const uint8_t bssid[IEEE80211_ADDR_LEN],
+    const uint8_t mac[IEEE80211_ADDR_LEN])
 {
 	struct zyd_vap *zvp;
 	struct ieee80211vap *vap;
@@ -686,7 +686,7 @@ zyd_intr_read_callback(struct usb_xfer *xfer, usb_error_t error)
 				memcpy(rqp->odata, cmd->data, rqp->olen);
 				DPRINTF(sc, ZYD_DEBUG_CMD,
 				    "command %p complete, data = %*D \n",
-				    rqp, rqp->olen, rqp->odata, ":");
+				    rqp, rqp->olen, (char *)rqp->odata, ":");
 				wakeup(rqp);	/* wakeup caller */
 				break;
 			}
diff --git a/sys/dev/vge/if_vge.c b/sys/dev/vge/if_vge.c
index f4ce30a..a49af27 100644
--- a/sys/dev/vge/if_vge.c
+++ b/sys/dev/vge/if_vge.c
@@ -173,6 +173,7 @@ static __inline void
 static void	vge_freebufs(struct vge_softc *);
 static void	vge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 static int	vge_ifmedia_upd(struct ifnet *);
+static int	vge_ifmedia_upd_locked(struct vge_softc *);
 static void	vge_init(void *);
 static void	vge_init_locked(struct vge_softc *);
 static void	vge_intr(void *);
@@ -180,7 +181,6 @@ static void	vge_intr_holdoff(struct vge_softc *);
 static int	vge_ioctl(struct ifnet *, u_long, caddr_t);
 static void	vge_link_statchg(void *);
 static int	vge_miibus_readreg(device_t, int, int);
-static void	vge_miibus_statchg(device_t);
 static int	vge_miibus_writereg(device_t, int, int, int);
 static void	vge_miipoll_start(struct vge_softc *);
 static void	vge_miipoll_stop(struct vge_softc *);
@@ -190,6 +190,7 @@ static void	vge_reset(struct vge_softc *);
 static int	vge_rx_list_init(struct vge_softc *);
 static int	vge_rxeof(struct vge_softc *, int);
 static void	vge_rxfilter(struct vge_softc *);
+static void	vge_setmedia(struct vge_softc *);
 static void	vge_setvlan(struct vge_softc *);
 static void	vge_setwol(struct vge_softc *);
 static void	vge_start(struct ifnet *);
@@ -211,16 +212,11 @@ static device_method_t vge_methods[] = {
 	DEVMETHOD(device_resume,	vge_resume),
 	DEVMETHOD(device_shutdown,	vge_shutdown),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	vge_miibus_readreg),
 	DEVMETHOD(miibus_writereg,	vge_miibus_writereg),
-	DEVMETHOD(miibus_statchg,	vge_miibus_statchg),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t vge_driver = {
@@ -1099,10 +1095,11 @@ vge_attach(device_t dev)
 		goto fail;
 	}
 
+	vge_miipoll_start(sc);
 	/* Do MII setup */
 	error = mii_attach(dev, &sc->vge_miibus, ifp, vge_ifmedia_upd,
 	    vge_ifmedia_sts, BMSR_DEFCAPMASK, sc->vge_phyaddr, MII_OFFSET_ANY,
-	    0);
+	    MIIF_DOPAUSE);
 	if (error != 0) {
 		device_printf(dev, "attaching PHYs failed\n");
 		goto fail;
@@ -1660,30 +1657,41 @@ vge_link_statchg(void *xsc)
 {
 	struct vge_softc *sc;
 	struct ifnet *ifp;
-	struct mii_data *mii;
+	uint8_t physts;
 
 	sc = xsc;
 	ifp = sc->vge_ifp;
 	VGE_LOCK_ASSERT(sc);
-	mii = device_get_softc(sc->vge_miibus);
 
-	mii_pollstat(mii);
-	if ((sc->vge_flags & VGE_FLAG_LINK) != 0) {
-		if (!(mii->mii_media_status & IFM_ACTIVE)) {
+	physts = CSR_READ_1(sc, VGE_PHYSTS0);
+	if ((physts & VGE_PHYSTS_RESETSTS) == 0) {
+		if ((physts & VGE_PHYSTS_LINK) == 0) {
 			sc->vge_flags &= ~VGE_FLAG_LINK;
 			if_link_state_change(sc->vge_ifp,
 			    LINK_STATE_DOWN);
-		}
-	} else {
-		if (mii->mii_media_status & IFM_ACTIVE &&
-		    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
+		} else {
 			sc->vge_flags |= VGE_FLAG_LINK;
 			if_link_state_change(sc->vge_ifp,
 			    LINK_STATE_UP);
+			CSR_WRITE_1(sc, VGE_CRC2, VGE_CR2_FDX_TXFLOWCTL_ENABLE |
+			    VGE_CR2_FDX_RXFLOWCTL_ENABLE);
+			if ((physts & VGE_PHYSTS_FDX) != 0) {
+				if ((physts & VGE_PHYSTS_TXFLOWCAP) != 0)
+					CSR_WRITE_1(sc, VGE_CRS2,
+					    VGE_CR2_FDX_TXFLOWCTL_ENABLE);
+				if ((physts & VGE_PHYSTS_RXFLOWCAP) != 0)
+					CSR_WRITE_1(sc, VGE_CRS2,
+					    VGE_CR2_FDX_RXFLOWCTL_ENABLE);
+			}
 			if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
 				vge_start_locked(ifp);
 		}
 	}
+	/*
+	 * Restart MII auto-polling because link state change interrupt
+	 * will disable it.
+	 */
+	vge_miipoll_start(sc);
 }
 
 #ifdef DEVICE_POLLING
@@ -2028,6 +2036,7 @@ vge_init_locked(struct vge_softc *sc)
 	 */
 	vge_stop(sc);
 	vge_reset(sc);
+	vge_miipoll_start(sc);
 
 	/*
 	 * Initialize the RX and TX descriptors and mbufs.
@@ -2099,9 +2108,16 @@ vge_init_locked(struct vge_softc *sc)
 	vge_rxfilter(sc);
 	vge_setvlan(sc);
 
-	/* Enable flow control */
-
-	CSR_WRITE_1(sc, VGE_CRS2, 0x8B);
+	/* Initialize pause timer. */
+	CSR_WRITE_2(sc, VGE_TX_PAUSE_TIMER, 0xFFFF);
+	/*
+	 * Initialize flow control parameters.
+	 *  TX XON high threshold : 48
+	 *  TX pause low threshold : 24
+	 *  Disable hald-duplex flow control
+	 */
+	CSR_WRITE_1(sc, VGE_CRC2, 0xFF);
+	CSR_WRITE_1(sc, VGE_CRS2, VGE_CR2_XON_ENABLE | 0x0B);
 
 	/* Enable jumbo frame reception (if desired) */
 
@@ -2129,7 +2145,7 @@ vge_init_locked(struct vge_softc *sc)
 	CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
 
 	sc->vge_flags &= ~VGE_FLAG_LINK;
-	mii_mediachg(mii);
+	vge_ifmedia_upd_locked(sc);
 
 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
@@ -2143,14 +2159,28 @@ static int
 vge_ifmedia_upd(struct ifnet *ifp)
 {
 	struct vge_softc *sc;
-	struct mii_data *mii;
 	int error;
 
 	sc = ifp->if_softc;
 	VGE_LOCK(sc);
+	error = vge_ifmedia_upd_locked(sc);
+	VGE_UNLOCK(sc);
+
+	return (error);
+}
+
+static int
+vge_ifmedia_upd_locked(struct vge_softc *sc)
+{
+	struct mii_data *mii;
+	struct mii_softc *miisc;
+	int error;
+
 	mii = device_get_softc(sc->vge_miibus);
+	LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
+		PHY_RESET(miisc);
+	vge_setmedia(sc);
 	error = mii_mediachg(mii);
-	VGE_UNLOCK(sc);
 
 	return (error);
 }
@@ -2179,13 +2209,11 @@ vge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 }
 
 static void
-vge_miibus_statchg(device_t dev)
+vge_setmedia(struct vge_softc *sc)
 {
-	struct vge_softc *sc;
 	struct mii_data *mii;
 	struct ifmedia_entry *ife;
 
-	sc = device_get_softc(dev);
 	mii = device_get_softc(sc->vge_miibus);
 	ife = mii->mii_media.ifm_cur;
 
@@ -2219,7 +2247,7 @@ vge_miibus_statchg(device_t dev)
 		}
 		break;
 	default:
-		device_printf(dev, "unknown media type: %x\n",
+		device_printf(sc->vge_dev, "unknown media type: %x\n",
 		    IFM_SUBTYPE(ife->ifm_media));
 		break;
 	}
@@ -2772,6 +2800,9 @@ vge_setlinkspeed(struct vge_softc *sc)
 			break;
 		}
 	}
+	/* Clear forced MAC speed/duplex configuration. */
+	CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
+	CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
 	vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_100T2CR, 0);
 	vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_ANAR,
 	    ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
diff --git a/sys/dev/viawd/viawd.c b/sys/dev/viawd/viawd.c
new file mode 100644
index 0000000..d56b677
--- /dev/null
+++ b/sys/dev/viawd/viawd.c
@@ -0,0 +1,248 @@
+/*-
+ * Copyright (c) 2011 Fabien Thomas <fabient@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <machine/resource.h>
+#include <sys/watchdog.h>
+
+#include <isa/isavar.h>
+#include <dev/pci/pcivar.h>
+
+#include "viawd.h"
+
+#define	viawd_read_4(sc, off)	bus_read_4((sc)->wd_res, (off))
+#define	viawd_write_4(sc, off, val)	\
+	bus_write_4((sc)->wd_res, (off), (val))
+
+static struct viawd_device viawd_devices[] = {
+	{ DEVICEID_VT8251, "VIA VT8251 watchdog timer" },
+	{ DEVICEID_CX700,  "VIA CX700 watchdog timer" },
+	{ DEVICEID_VX800,  "VIA VX800 watchdog timer" },
+	{ DEVICEID_VX855,  "VIA VX855 watchdog timer" },
+	{ DEVICEID_VX900,  "VIA VX900 watchdog timer" },
+	{ 0, NULL },
+};
+
+static devclass_t viawd_devclass;
+
+static void
+viawd_tmr_state(struct viawd_softc *sc, int enable)
+{
+	uint32_t reg;
+
+	reg = viawd_read_4(sc, VIAWD_MEM_CTRL);
+	if (enable)
+		reg |= VIAWD_MEM_CTRL_TRIGGER | VIAWD_MEM_CTRL_ENABLE;
+	else
+		reg &= ~VIAWD_MEM_CTRL_ENABLE;
+	viawd_write_4(sc, VIAWD_MEM_CTRL, reg);
+}
+
+static void
+viawd_tmr_set(struct viawd_softc *sc, unsigned int timeout)
+{
+
+	/* Keep value in range. */
+	if (timeout < VIAWD_MEM_COUNT_MIN)
+		timeout = VIAWD_MEM_COUNT_MIN;
+	else if (timeout > VIAWD_MEM_COUNT_MAX)
+		timeout = VIAWD_MEM_COUNT_MAX;
+
+	viawd_write_4(sc, VIAWD_MEM_COUNT, timeout);
+	sc->timeout = timeout;
+}
+
+/*
+ * Watchdog event handler - called by the framework to enable or disable
+ * the watchdog or change the initial timeout value.
+ */
+static void
+viawd_event(void *arg, unsigned int cmd, int *error)
+{
+	struct viawd_softc *sc = arg;
+	unsigned int timeout;
+
+	/* Convert from power-of-two-ns to second. */
+	cmd &= WD_INTERVAL;
+	timeout = ((uint64_t)1 << cmd) / 1000000000;
+	if (cmd) {
+		if (timeout != sc->timeout)
+			viawd_tmr_set(sc, timeout);
+		viawd_tmr_state(sc, 1);
+		*error = 0;
+	} else
+		viawd_tmr_state(sc, 0);
+}
+
+/* Look for a supported VIA south bridge. */
+static struct viawd_device *
+viawd_find(device_t dev)
+{
+	struct viawd_device *id;
+
+	if (pci_get_vendor(dev) != VENDORID_VIA)
+		return (NULL);
+	for (id = viawd_devices; id->desc != NULL; id++)
+		if (pci_get_device(dev) == id->device)
+			return (id);
+	return (NULL);
+}
+
+static void
+viawd_identify(driver_t *driver, device_t parent)
+{
+
+	if (viawd_find(parent) == NULL)
+		return;
+
+	if (device_find_child(parent, driver->name, -1) == NULL)
+		BUS_ADD_CHILD(parent, 0, driver->name, 0);
+}
+
+static int
+viawd_probe(device_t dev)
+{
+	struct viawd_device *id;
+
+	id = viawd_find(device_get_parent(dev));
+	KASSERT(id != NULL, ("parent should be a valid VIA SB"));
+	device_set_desc(dev, id->desc);
+	return (BUS_PROBE_GENERIC);
+}
+
+static int
+viawd_attach(device_t dev)
+{
+	device_t sb_dev;
+	struct viawd_softc *sc;
+	uint32_t pmbase, reg;
+
+	sc = device_get_softc(dev);
+	sc->dev = dev;
+
+	sb_dev = device_get_parent(dev);
+	if (sb_dev == NULL) {
+		device_printf(dev, "Can not find watchdog device.\n");
+		goto fail;
+	}
+	sc->sb_dev = sb_dev;
+
+	/* Get watchdog memory base. */
+	pmbase = pci_read_config(sb_dev, VIAWD_CONFIG_BASE, 4);
+	if (pmbase == 0) {
+		device_printf(dev,
+		    "Watchdog disabled in BIOS or hardware\n");
+		goto fail;
+	}
+
+	/* Allocate I/O register space. */
+	sc->wd_rid = 0;
+	sc->wd_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->wd_rid,
+	    pmbase, pmbase + VIAWD_MEM_LEN - 1, VIAWD_MEM_LEN,
+	    RF_ACTIVE | RF_SHAREABLE);
+	if (sc->wd_res == NULL) {
+		device_printf(dev, "Unable to map watchdog memory\n");
+		goto fail;
+	}
+
+	/* Check if watchdog fired last boot. */
+	reg = viawd_read_4(sc, VIAWD_MEM_CTRL);
+	if (reg & VIAWD_MEM_CTRL_FIRED) {
+		device_printf(dev,
+		    "ERROR: watchdog rebooted the system\n");
+		/* Reset bit state. */
+		viawd_write_4(sc, VIAWD_MEM_CTRL, reg);
+	}
+
+	/* Register the watchdog event handler. */
+	sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, viawd_event, sc, 0);
+
+	return (0);
+fail:
+	if (sc->wd_res != NULL)
+		bus_release_resource(dev, SYS_RES_MEMORY,
+		    sc->wd_rid, sc->wd_res);
+	return (ENXIO);
+}
+
+static int
+viawd_detach(device_t dev)
+{
+	struct viawd_softc *sc;
+	uint32_t reg;
+
+	sc = device_get_softc(dev);
+
+	/* Deregister event handler. */
+	if (sc->ev_tag != NULL)
+		EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag);
+	sc->ev_tag = NULL;
+
+	/*
+	 * Do not stop the watchdog on shutdown if active but bump the
+	 * timer to avoid spurious reset.
+	 */
+	reg = viawd_read_4(sc, VIAWD_MEM_CTRL);
+	if (reg & VIAWD_MEM_CTRL_ENABLE) {
+		viawd_tmr_set(sc, VIAWD_TIMEOUT_SHUTDOWN);
+		viawd_tmr_state(sc, 1);
+		device_printf(dev,
+		    "Keeping watchog alive during shutdown for %d seconds\n",
+		    VIAWD_TIMEOUT_SHUTDOWN);
+	}
+
+	if (sc->wd_res != NULL)
+		bus_release_resource(sc->dev, SYS_RES_MEMORY,
+		    sc->wd_rid, sc->wd_res);
+
+	return (0);
+}
+
+static device_method_t viawd_methods[] = {
+	DEVMETHOD(device_identify, viawd_identify),
+	DEVMETHOD(device_probe,	viawd_probe),
+	DEVMETHOD(device_attach, viawd_attach),
+	DEVMETHOD(device_detach, viawd_detach),
+	DEVMETHOD(device_shutdown, viawd_detach),
+	{0,0}
+};
+
+static driver_t viawd_driver = {
+	"viawd",
+	viawd_methods,
+	sizeof(struct viawd_softc),
+};
+
+DRIVER_MODULE(viawd, isab, viawd_driver, viawd_devclass, NULL, NULL);
diff --git a/sys/dev/viawd/viawd.h b/sys/dev/viawd/viawd.h
new file mode 100644
index 0000000..d311b88
--- /dev/null
+++ b/sys/dev/viawd/viawd.h
@@ -0,0 +1,73 @@
+/*-
+ * Copyright (c) 2011 Fabien Thomas <fabient@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _VIAWD_H_
+#define _VIAWD_H_
+
+struct viawd_device {
+	uint16_t		device;
+	char			*desc;
+};
+
+struct viawd_softc {
+	device_t		dev;
+	device_t		sb_dev;
+
+	int			wd_rid;
+	struct resource		*wd_res;
+
+	eventhandler_tag	ev_tag;
+	unsigned int		timeout;
+};
+
+#define VENDORID_VIA		0x1106
+#define DEVICEID_VT8251		0x3287
+#define DEVICEID_CX700		0x8324
+#define DEVICEID_VX800		0x8353
+#define DEVICEID_VX855		0x8409
+#define DEVICEID_VX900		0x8410
+
+#define VIAWD_CONFIG_BASE	0xE8
+
+#define VIAWD_MEM_LEN		8
+
+#define VIAWD_MEM_CTRL		0x00
+#define VIAWD_MEM_CTRL_TRIGGER	0x000000080
+#define VIAWD_MEM_CTRL_DISABLE	0x000000008
+#define VIAWD_MEM_CTRL_POWEROFF	0x000000004
+#define VIAWD_MEM_CTRL_FIRED	0x000000002
+#define VIAWD_MEM_CTRL_ENABLE	0x000000001
+
+#define VIAWD_MEM_COUNT		0x04
+
+#define VIAWD_MEM_COUNT_MIN	1
+#define VIAWD_MEM_COUNT_MAX	1023
+
+#define VIAWD_TIMEOUT_SHUTDOWN	(5 * 60)
+
+#endif
diff --git a/sys/dev/virtio/balloon/virtio_balloon.c b/sys/dev/virtio/balloon/virtio_balloon.c
index ef7aca9..61ae4b1 100644
--- a/sys/dev/virtio/balloon/virtio_balloon.c
+++ b/sys/dev/virtio/balloon/virtio_balloon.c
@@ -475,7 +475,6 @@ vtballoon_update_size(struct vtballoon_softc *sc)
 	virtio_write_dev_config_4(sc->vtballoon_dev,
 	    offsetof(struct virtio_balloon_config, actual),
 	    htole32(sc->vtballoon_current_npages));
-
 }
 
 static int
diff --git a/sys/dev/virtio/balloon/virtio_balloon.h b/sys/dev/virtio/balloon/virtio_balloon.h
index cea84ba..1a52733 100644
--- a/sys/dev/virtio/balloon/virtio_balloon.h
+++ b/sys/dev/virtio/balloon/virtio_balloon.h
@@ -1,7 +1,30 @@
-/*
+/*-
  * This header is BSD licensed so anyone can use the definitions to implement
  * compatible drivers/servers.
  *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of IBM nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL IBM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
  * $FreeBSD$
  */
 
diff --git a/sys/dev/virtio/block/virtio_blk.c b/sys/dev/virtio/block/virtio_blk.c
index 09783a8..dca19ba 100644
--- a/sys/dev/virtio/block/virtio_blk.c
+++ b/sys/dev/virtio/block/virtio_blk.c
@@ -87,9 +87,7 @@ struct vtblk_softc {
 	struct taskqueue	*vtblk_tq;
 	struct task		 vtblk_intr_task;
 
-	int			 vtblk_sector_size;
 	int			 vtblk_max_nsegs;
-	int			 vtblk_unit;
 	int			 vtblk_request_count;
 
 	struct vtblk_request	 vtblk_dump_request;
@@ -185,7 +183,6 @@ TUNABLE_INT("hw.vtblk.no_ident", &vtblk_no_ident);
 				mtx_init(VTBLK_MTX((_sc)), (_name), \
 				    "VTBLK Lock", MTX_DEF)
 #define VTBLK_LOCK(_sc)		mtx_lock(VTBLK_MTX((_sc)))
-#define VTBLK_TRYLOCK(_sc)	mtx_trylock(VTBLK_MTX((_sc)))
 #define VTBLK_UNLOCK(_sc)	mtx_unlock(VTBLK_MTX((_sc)))
 #define VTBLK_LOCK_DESTROY(_sc)	mtx_destroy(VTBLK_MTX((_sc)))
 #define VTBLK_LOCK_ASSERT(_sc)	mtx_assert(VTBLK_MTX((_sc)), MA_OWNED)
@@ -281,7 +278,6 @@ vtblk_attach(device_t dev)
 
 	sc = device_get_softc(dev);
 	sc->vtblk_dev = dev;
-	sc->vtblk_unit = device_get_unit(dev);
 
 	VTBLK_LOCK_INIT(sc, device_get_nameunit(dev));
 
@@ -299,13 +295,8 @@ vtblk_attach(device_t dev)
 		sc->vtblk_flags |= VTBLK_FLAG_READONLY;
 
 	/* Get local copy of config. */
-	if (virtio_with_feature(dev, VIRTIO_BLK_F_TOPOLOGY) == 0) {
-		bzero(&blkcfg, sizeof(struct virtio_blk_config));
-		virtio_read_device_config(dev, 0, &blkcfg,
-		    offsetof(struct virtio_blk_config, physical_block_exp));
-	} else
-		virtio_read_device_config(dev, 0, &blkcfg,
-		    sizeof(struct virtio_blk_config));
+	virtio_read_device_config(dev, 0, &blkcfg,
+	    sizeof(struct virtio_blk_config));
 
 	/*
 	 * With the current sglist(9) implementation, it is not easy
@@ -498,12 +489,6 @@ vtblk_dump(void *arg, void *virtual, vm_offset_t physical, off_t offset,
 	if ((sc = dp->d_drv1) == NULL)
 		return (ENXIO);
 
-	if (VTBLK_TRYLOCK(sc) == 0) {
-		device_printf(sc->vtblk_dev,
-		    "softc already locked, cannot dump...\n");
-		return (EBUSY);
-	}
-
 	if ((sc->vtblk_flags & VTBLK_FLAG_DUMPING) == 0) {
 		vtblk_prepare_dump(sc);
 		sc->vtblk_flags |= VTBLK_FLAG_DUMPING;
@@ -622,7 +607,7 @@ vtblk_alloc_disk(struct vtblk_softc *sc, struct virtio_blk_config *blkcfg)
 	dp->d_ioctl = vtblk_ioctl;
 	dp->d_strategy = vtblk_strategy;
 	dp->d_name = VTBLK_DISK_NAME;
-	dp->d_unit = sc->vtblk_unit;
+	dp->d_unit = device_get_unit(dev);
 	dp->d_drv1 = sc;
 
 	if ((sc->vtblk_flags & VTBLK_FLAG_READONLY) == 0)
@@ -632,10 +617,9 @@ vtblk_alloc_disk(struct vtblk_softc *sc, struct virtio_blk_config *blkcfg)
 	dp->d_mediasize = blkcfg->capacity * 512;
 
 	if (virtio_with_feature(dev, VIRTIO_BLK_F_BLK_SIZE))
-		sc->vtblk_sector_size = blkcfg->blk_size;
+		dp->d_sectorsize = blkcfg->blk_size;
 	else
-		sc->vtblk_sector_size = 512;
-	dp->d_sectorsize = sc->vtblk_sector_size;
+		dp->d_sectorsize = 512;
 
 	/*
 	 * The VirtIO maximum I/O size is given in terms of segments.
@@ -905,9 +889,10 @@ vtblk_get_ident(struct vtblk_softc *sc)
 
 	VTBLK_LOCK(sc);
 	error = vtblk_poll_request(sc, req);
-	vtblk_enqueue_request(sc, req);
 	VTBLK_UNLOCK(sc);
 
+	vtblk_enqueue_request(sc, req);
+
 	if (error) {
 		device_printf(sc->vtblk_dev,
 		    "error getting device identifier: %d\n", error);
diff --git a/sys/dev/virtio/block/virtio_blk.h b/sys/dev/virtio/block/virtio_blk.h
index 4fb32e0..f26c649 100644
--- a/sys/dev/virtio/block/virtio_blk.h
+++ b/sys/dev/virtio/block/virtio_blk.h
@@ -1,7 +1,30 @@
-/*
+/*-
  * This header is BSD licensed so anyone can use the definitions to implement
  * compatible drivers/servers.
  *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of IBM nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ *  TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL IBM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
  * $FreeBSD$
  */
 
@@ -39,16 +62,6 @@ struct virtio_blk_config {
 
 	/* block size of device (if VIRTIO_BLK_F_BLK_SIZE) */
 	uint32_t blk_size;
-
-	/* the next 4 entries are guarded by VIRTIO_BLK_F_TOPOLOGY  */
-	/* exponent for physical block per logical block. */
-	uint8_t physical_block_exp;
-	/* alignment offset in logical blocks. */
-	uint8_t alignment_offset;
-	/* minimum I/O size without performance penalty in logical blocks. */
-	uint16_t min_io_size;
-	/* optimal sustained I/O size in logical blocks. */
-	uint32_t opt_io_size;
 } __packed;
 
 /*
diff --git a/sys/dev/virtio/network/if_vtnet.c b/sys/dev/virtio/network/if_vtnet.c
index 22becb1..ca57aec 100644
--- a/sys/dev/virtio/network/if_vtnet.c
+++ b/sys/dev/virtio/network/if_vtnet.c
@@ -317,8 +317,20 @@ vtnet_attach(device_t dev)
 	if (virtio_with_feature(dev, VIRTIO_NET_F_CTRL_VQ)) {
 		sc->vtnet_flags |= VTNET_FLAG_CTRL_VQ;
 
-		if (virtio_with_feature(dev, VIRTIO_NET_F_CTRL_RX))
+		if (virtio_with_feature(dev, VIRTIO_NET_F_CTRL_RX)) {
+			sc->vtnet_mac_filter = malloc(
+			    sizeof(struct vtnet_mac_filter), M_DEVBUF,
+			    M_NOWAIT | M_ZERO);
+			if (sc->vtnet_mac_filter == NULL) {
+				device_printf(dev,
+				    "cannot allocate mac filter table\n");
+				error = ENOMEM;
+				goto fail;
+			}
+
 			sc->vtnet_flags |= VTNET_FLAG_CTRL_RX;
+		}
+
 		if (virtio_with_feature(dev, VIRTIO_NET_F_CTRL_VLAN))
 			sc->vtnet_flags |= VTNET_FLAG_VLAN_FILTER;
 	}
@@ -505,7 +517,12 @@ vtnet_detach(device_t dev)
 		sc->vtnet_vlan_detach = NULL;
 	}
 
-	if (ifp) {
+	if (sc->vtnet_mac_filter != NULL) {
+		free(sc->vtnet_mac_filter, M_DEVBUF);
+		sc->vtnet_mac_filter = NULL;
+	}
+
+	if (ifp != NULL) {
 		if_free(ifp);
 		sc->vtnet_ifp = NULL;
 	}
@@ -742,17 +759,11 @@ vtnet_update_link_status(struct vtnet_softc *sc)
 
 	if (link && ((sc->vtnet_flags & VTNET_FLAG_LINK) == 0)) {
 		sc->vtnet_flags |= VTNET_FLAG_LINK;
-		if (bootverbose)
-			device_printf(dev, "Link is up\n");
-
 		if_link_state_change(ifp, LINK_STATE_UP);
 		if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
 			vtnet_start_locked(ifp);
 	} else if (!link && (sc->vtnet_flags & VTNET_FLAG_LINK)) {
 		sc->vtnet_flags &= ~VTNET_FLAG_LINK;
-		if (bootverbose)
-			device_printf(dev, "Link is down\n");
-
 		if_link_state_change(ifp, LINK_STATE_DOWN);
 	}
 }
@@ -1105,7 +1116,7 @@ vtnet_alloc_rxbuf(struct vtnet_softc *sc, int nbufs, struct mbuf **m_tailp)
 		KASSERT(sc->vtnet_flags & VTNET_FLAG_LRO_NOMRG,
 		    ("chained Rx mbuf requested without LRO_NOMRG"));
 
-		for (i = 0; i < nbufs - 1; i++) {
+		for (i = 1; i < nbufs; i++) {
 			m = m_getjcl(M_DONTWAIT, MT_DATA, 0, clsize);
 			if (m == NULL)
 				goto fail;
@@ -1143,9 +1154,8 @@ vtnet_replace_rxbuf(struct vtnet_softc *sc, struct mbuf *m0, int len0)
 	clsize = sc->vtnet_rx_mbuf_size;
 	nreplace = 0;
 
-	if (m->m_next != NULL)
-		KASSERT(sc->vtnet_flags & VTNET_FLAG_LRO_NOMRG,
-		    ("chained Rx mbuf without LRO_NOMRG"));
+	KASSERT(sc->vtnet_flags & VTNET_FLAG_LRO_NOMRG ||
+	    m->m_next == NULL, ("chained Rx mbuf without LRO_NOMRG"));
 
 	/*
 	 * Since LRO_NOMRG mbuf chains are so large, we want to avoid
@@ -1275,8 +1285,8 @@ vtnet_enqueue_rxbuf(struct vtnet_softc *sc, struct mbuf *m)
 	int offset, error;
 
 	VTNET_LOCK_ASSERT(sc);
-	if ((sc->vtnet_flags & VTNET_FLAG_LRO_NOMRG) == 0)
-		KASSERT(m->m_next == NULL, ("chained Rx mbuf"));
+	KASSERT(sc->vtnet_flags & VTNET_FLAG_LRO_NOMRG ||
+	    m->m_next == NULL, ("chained Rx mbuf without LRO_NOMRG"));
 
 	sglist_init(&sg, VTNET_MAX_RX_SEGS, segs);
 
@@ -1688,7 +1698,8 @@ vtnet_rxeof(struct vtnet_softc *sc, int count, int *rx_npktsp)
 			break;
 	}
 
-	virtqueue_notify(vq);
+	if (deq > 0)
+		virtqueue_notify(vq);
 
 	if (rx_npktsp != NULL)
 		*rx_npktsp = rx_npkts;
@@ -1946,9 +1957,14 @@ vtnet_encap(struct vtnet_softc *sc, struct mbuf **m_head)
 	struct mbuf *m;
 	int error;
 
+	m = *m_head;
+
 	txhdr = uma_zalloc(vtnet_tx_header_zone, M_NOWAIT | M_ZERO);
-	if (txhdr == NULL)
+	if (txhdr == NULL) {
+		*m_head = NULL;
+		m_freem(m);
 		return (ENOMEM);
+	}
 
 	/*
 	 * Always use the non-mergeable header to simplify things. When
@@ -1957,21 +1973,22 @@ vtnet_encap(struct vtnet_softc *sc, struct mbuf **m_head)
 	 * the correct header size to the host.
 	 */
 	hdr = &txhdr->vth_uhdr.hdr;
-	m = *m_head;
-
-	error = ENOBUFS;
 
 	if (m->m_flags & M_VLANTAG) {
 		m = ether_vlanencap(m, m->m_pkthdr.ether_vtag);
-		if ((*m_head = m) == NULL)
+		if ((*m_head = m) == NULL) {
+			error = ENOBUFS;
 			goto fail;
+		}
 		m->m_flags &= ~M_VLANTAG;
 	}
 
 	if (m->m_pkthdr.csum_flags != 0) {
 		m = vtnet_tx_offload(sc, m, hdr);
-		if ((*m_head = m) == NULL)
+		if ((*m_head = m) == NULL) {
+			error = ENOBUFS;
 			goto fail;
+		}
 	}
 
 	error = vtnet_enqueue_txbuf(sc, m_head, txhdr);
@@ -2387,6 +2404,7 @@ vtnet_rx_filter_mac(struct vtnet_softc *sc)
 	uint8_t ack;
 
 	ifp = sc->vtnet_ifp;
+	filter = sc->vtnet_mac_filter;
 	ucnt = 0;
 	mcnt = 0;
 	promisc = 0;
@@ -2397,19 +2415,6 @@ vtnet_rx_filter_mac(struct vtnet_softc *sc)
 	KASSERT(sc->vtnet_flags & VTNET_FLAG_CTRL_RX,
 	    ("CTRL_RX feature not negotiated"));
 
-	/*
-	 * Allocate the MAC filtering table. Note we could do this
-	 * at attach time, but it is probably not worth keeping it
-	 * around for an infrequent occurrence.
-	 */
-	filter = malloc(sizeof(struct vtnet_mac_filter), M_DEVBUF,
-	    M_NOWAIT | M_ZERO);
-	if (filter == NULL) {
-		device_printf(sc->vtnet_dev,
-		    "cannot allocate MAC address filtering table\n");
-		return;
-	}
-
 	/* Unicast MAC addresses: */
 	if_addr_rlock(ifp);
 	TAILQ_FOREACH(ifa, &ifp->if_addrhead, ifa_link) {
@@ -2481,8 +2486,6 @@ vtnet_rx_filter_mac(struct vtnet_softc *sc)
 		if_printf(ifp, "error setting host MAC filter table\n");
 
 out:
-	free(filter, M_DEVBUF);
-
 	if (promisc)
 		if (vtnet_set_promisc(sc, 1) != 0)
 			if_printf(ifp, "cannot enable promiscuous mode\n");
diff --git a/sys/dev/virtio/network/if_vtnetvar.h b/sys/dev/virtio/network/if_vtnetvar.h
index 613b2b0..184870e 100644
--- a/sys/dev/virtio/network/if_vtnetvar.h
+++ b/sys/dev/virtio/network/if_vtnetvar.h
@@ -99,6 +99,7 @@ struct vtnet_softc {
 #define VTNET_MEDIATYPE		 (IFM_ETHER | IFM_1000_T | IFM_FDX)
 	char			 vtnet_hwaddr[ETHER_ADDR_LEN];
 
+	struct vtnet_mac_filter	*vtnet_mac_filter;
 	/*
 	 * During reset, the host's VLAN filtering table is lost. The
 	 * array below is used to restore all the VLANs configured on
diff --git a/sys/dev/virtio/network/virtio_net.h b/sys/dev/virtio/network/virtio_net.h
index 7361aa1..058f29f 100644
--- a/sys/dev/virtio/network/virtio_net.h
+++ b/sys/dev/virtio/network/virtio_net.h
@@ -1,7 +1,30 @@
-/*
+/*-
  * This header is BSD licensed so anyone can use the definitions to implement
  * compatible drivers/servers.
  *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of IBM nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL IBM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
  * $FreeBSD$
  */
 
diff --git a/sys/dev/virtio/pci/virtio_pci.h b/sys/dev/virtio/pci/virtio_pci.h
index 6ebfdd5..d8daa31 100644
--- a/sys/dev/virtio/pci/virtio_pci.h
+++ b/sys/dev/virtio/pci/virtio_pci.h
@@ -1,4 +1,4 @@
-/*
+/*-
  * Copyright IBM Corp. 2007
  *
  * Authors:
@@ -7,6 +7,29 @@
  * This header is BSD licensed so anyone can use the definitions to implement
  * compatible drivers/servers.
  *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of IBM nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL IBM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
  * $FreeBSD$
  */
 
diff --git a/sys/dev/virtio/virtio.h b/sys/dev/virtio/virtio.h
index ebd3c74..00d2d5f 100644
--- a/sys/dev/virtio/virtio.h
+++ b/sys/dev/virtio/virtio.h
@@ -1,7 +1,30 @@
-/*
+/*-
  * This header is BSD licensed so anyone can use the definitions to implement
  * compatible drivers/servers.
  *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of IBM nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL IBM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
  * $FreeBSD$
  */
 
diff --git a/sys/dev/virtio/virtio_ring.h b/sys/dev/virtio/virtio_ring.h
index 124cb4d..b0ab946 100644
--- a/sys/dev/virtio/virtio_ring.h
+++ b/sys/dev/virtio/virtio_ring.h
@@ -1,10 +1,34 @@
-/*
- * This header is BSD licensed so anyone can use the definitions
- * to implement compatible drivers/servers.
- *
+/*-
  * Copyright Rusty Russell IBM Corporation 2007.
+ *
+ * This header is BSD licensed so anyone can use the definitions to implement
+ * compatible drivers/servers.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of IBM nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL IBM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
  */
-/* $FreeBSD$ */
 
 #ifndef VIRTIO_RING_H
 #define	VIRTIO_RING_H
diff --git a/sys/dev/vr/if_vr.c b/sys/dev/vr/if_vr.c
index 0bcef0e..6d99216 100644
--- a/sys/dev/vr/if_vr.c
+++ b/sys/dev/vr/if_vr.c
@@ -217,16 +217,12 @@ static device_method_t vr_methods[] = {
 	DEVMETHOD(device_suspend,	vr_suspend),
 	DEVMETHOD(device_resume,	vr_resume),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	vr_miibus_readreg),
 	DEVMETHOD(miibus_writereg,	vr_miibus_writereg),
 	DEVMETHOD(miibus_statchg,	vr_miibus_statchg),
 
-	{ NULL, NULL }
+	DEVMETHOD_END
 };
 
 static driver_t vr_driver = {
@@ -309,20 +305,20 @@ vr_miibus_statchg(device_t dev)
 	    (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
 		return;
 
-	sc->vr_link = 0;
+	sc->vr_flags &= ~(VR_F_LINK | VR_F_TXPAUSE);
 	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 	    (IFM_ACTIVE | IFM_AVALID)) {
 		switch (IFM_SUBTYPE(mii->mii_media_active)) {
 		case IFM_10_T:
 		case IFM_100_TX:
-			sc->vr_link = 1;
+			sc->vr_flags |= VR_F_LINK;
 			break;
 		default:
 			break;
 		}
 	}
 
-	if (sc->vr_link != 0) {
+	if ((sc->vr_flags & VR_F_LINK) != 0) {
 		cr0 = CSR_READ_1(sc, VR_CR0);
 		cr1 = CSR_READ_1(sc, VR_CR1);
 		mfdx = (cr1 & VR_CR1_FULLDUPLEX) != 0;
@@ -346,7 +342,6 @@ vr_miibus_statchg(device_t dev)
 			CSR_WRITE_1(sc, VR_CR1, cr1);
 		}
 		fc = 0;
-#ifdef notyet
 		/* Configure flow-control. */
 		if (sc->vr_revid >= REV_ID_VT6105_A0) {
 			fc = CSR_READ_1(sc, VR_FLOWCR1);
@@ -355,8 +350,10 @@ vr_miibus_statchg(device_t dev)
 			    IFM_ETH_RXPAUSE) != 0)
 				fc |= VR_FLOWCR1_RXPAUSE;
 			if ((IFM_OPTIONS(mii->mii_media_active) &
-			    IFM_ETH_TXPAUSE) != 0)
+			    IFM_ETH_TXPAUSE) != 0) {
 				fc |= VR_FLOWCR1_TXPAUSE;
+				sc->vr_flags |= VR_F_TXPAUSE;
+			}
 			CSR_WRITE_1(sc, VR_FLOWCR1, fc);
 		} else if (sc->vr_revid >= REV_ID_VT6102_A) {
 			/* No Tx puase capability available for Rhine II. */
@@ -367,7 +364,6 @@ vr_miibus_statchg(device_t dev)
 				fc |= VR_MISCCR0_RXPAUSE;
 			CSR_WRITE_1(sc, VR_MISC_CR0, fc);
 		}
-#endif
 		vr_rx_start(sc);
 		vr_tx_start(sc);
 	} else {
@@ -770,7 +766,8 @@ vr_attach(device_t dev)
 	else
 		phy = CSR_READ_1(sc, VR_PHYADDR) & VR_PHYADDR_MASK;
 	error = mii_attach(dev, &sc->vr_miibus, ifp, vr_ifmedia_upd,
-	    vr_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
+	    vr_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY,
+	    sc->vr_revid >= REV_ID_VT6102_A ? MIIF_DOPAUSE : 0);
 	if (error != 0) {
 		device_printf(dev, "attaching PHYs failed\n");
 		goto fail;
@@ -825,7 +822,7 @@ vr_detach(device_t dev)
 	/* These should only be active if attach succeeded. */
 	if (device_is_attached(dev)) {
 		VR_LOCK(sc);
-		sc->vr_detach = 1;
+		sc->vr_flags |= VR_F_DETACHED;
 		vr_stop(sc);
 		VR_UNLOCK(sc);
 		callout_drain(&sc->vr_stat_callout);
@@ -1400,6 +1397,17 @@ vr_rxeof(struct vr_softc *sc)
 	}
 
 	if (prog > 0) {
+		/*
+		 * Let controller know how many number of RX buffers
+		 * are posted but avoid expensive register access if
+		 * TX pause capability was not negotiated with link
+		 * partner.
+		 */
+		if ((sc->vr_flags & VR_F_TXPAUSE) != 0) {
+			if (prog >= VR_RX_RING_CNT)
+				prog = VR_RX_RING_CNT - 1;
+			CSR_WRITE_1(sc, VR_FLOWCR0, prog);
+		}
 		sc->vr_cdata.vr_rx_cons = cons;
 		bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag,
 		    sc->vr_cdata.vr_rx_ring_map,
@@ -1546,7 +1554,7 @@ vr_tick(void *xsc)
 
 	mii = device_get_softc(sc->vr_miibus);
 	mii_tick(mii);
-	if (sc->vr_link == 0)
+	if ((sc->vr_flags & VR_F_LINK) == 0)
 		vr_miibus_statchg(sc->vr_dev);
 	vr_watchdog(sc);
 	callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc);
@@ -1656,7 +1664,7 @@ vr_intr(void *arg)
 
 	VR_LOCK(sc);
 
-	if (sc->vr_suspended != 0)
+	if ((sc->vr_flags & VR_F_SUSPENDED) != 0)
 		goto done_locked;
 
 	status = CSR_READ_2(sc, VR_ISR);
@@ -1937,7 +1945,7 @@ vr_start_locked(struct ifnet *ifp)
 	VR_LOCK_ASSERT(sc);
 
 	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
-	    IFF_DRV_RUNNING || sc->vr_link == 0)
+	    IFF_DRV_RUNNING || (sc->vr_flags & VR_F_LINK) == 0)
 		return;
 
 	for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
@@ -2075,14 +2083,32 @@ vr_init_locked(struct vr_softc *sc)
 
 	/* Set flow-control parameters for Rhine III. */
 	if (sc->vr_revid >= REV_ID_VT6105_A0) {
- 		/* Rx buffer count available for incoming packet. */
-		CSR_WRITE_1(sc, VR_FLOWCR0, VR_RX_RING_CNT);
 		/*
-		 * Tx pause low threshold : 16 free receive buffers
-		 * Tx pause XON high threshold : 48 free receive buffers
+		 * Configure Rx buffer count available for incoming
+		 * packet.
+		 * Even though data sheet says almost nothing about
+		 * this register, this register should be updated
+		 * whenever driver adds new RX buffers to controller.
+		 * Otherwise, XON frame is not sent to link partner
+		 * even if controller has enough RX buffers and you
+		 * would be isolated from network.
+		 * The controller is not smart enough to know number
+		 * of available RX buffers so driver have to let
+		 * controller know how many RX buffers are posted.
+		 * In other words, this register works like a residue
+		 * counter for RX buffers and should be initialized
+		 * to the number of total RX buffers  - 1 before
+		 * enabling RX MAC.  Note, this register is 8bits so
+		 * it effectively limits the maximum number of RX
+		 * buffer to be configured by controller is 255.
+		 */
+		CSR_WRITE_1(sc, VR_FLOWCR0, VR_RX_RING_CNT - 1);
+		/*
+		 * Tx pause low threshold : 8 free receive buffers
+		 * Tx pause XON high threshold : 24 free receive buffers
 		 */
 		CSR_WRITE_1(sc, VR_FLOWCR1,
-		    VR_FLOWCR1_TXLO16 | VR_FLOWCR1_TXHI48 | VR_FLOWCR1_XONXOFF);
+		    VR_FLOWCR1_TXLO8 | VR_FLOWCR1_TXHI24 | VR_FLOWCR1_XONXOFF);
 		/* Set Tx pause timer. */
 		CSR_WRITE_2(sc, VR_PAUSETIMER, 0xffff);
 	}
@@ -2107,12 +2133,12 @@ vr_init_locked(struct vr_softc *sc)
 	if (sc->vr_revid > REV_ID_VT6102_A)
 		CSR_WRITE_2(sc, VR_MII_IMR, 0);
 
-	sc->vr_link = 0;
-	mii_mediachg(mii);
-
 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 
+	sc->vr_flags &= ~(VR_F_LINK | VR_F_TXPAUSE);
+	mii_mediachg(mii);
+
 	callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc);
 }
 
@@ -2132,6 +2158,7 @@ vr_ifmedia_upd(struct ifnet *ifp)
 	mii = device_get_softc(sc->vr_miibus);
 	LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
 		PHY_RESET(miisc);
+	sc->vr_flags &= ~(VR_F_LINK | VR_F_TXPAUSE);
 	error = mii_mediachg(mii);
 	VR_UNLOCK(sc);
 
@@ -2181,7 +2208,7 @@ vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 				    (IFF_PROMISC | IFF_ALLMULTI))
 					vr_set_filter(sc);
 			} else {
-				if (sc->vr_detach == 0)
+				if ((sc->vr_flags & VR_F_DETACHED) == 0)
 					vr_init_locked(sc);
 			}
 		} else {
@@ -2269,7 +2296,7 @@ vr_watchdog(struct vr_softc *sc)
 	if (sc->vr_cdata.vr_tx_cnt == 0)
 		return;
 
-	if (sc->vr_link == 0) {
+	if ((sc->vr_flags & VR_F_LINK) == 0) {
 		if (bootverbose)
 			if_printf(sc->vr_ifp, "watchdog timeout "
 			   "(missed link)\n");
@@ -2447,7 +2474,7 @@ vr_suspend(device_t dev)
 	VR_LOCK(sc);
 	vr_stop(sc);
 	vr_setwol(sc);
-	sc->vr_suspended = 1;
+	sc->vr_flags |= VR_F_SUSPENDED;
 	VR_UNLOCK(sc);
 
 	return (0);
@@ -2468,7 +2495,7 @@ vr_resume(device_t dev)
 	if (ifp->if_flags & IFF_UP)
 		vr_init_locked(sc);
 
-	sc->vr_suspended = 0;
+	sc->vr_flags &= ~VR_F_SUSPENDED;
 	VR_UNLOCK(sc);
 
 	return (0);
diff --git a/sys/dev/vr/if_vrreg.h b/sys/dev/vr/if_vrreg.h
index 5e2b6b8..2445bab 100644
--- a/sys/dev/vr/if_vrreg.h
+++ b/sys/dev/vr/if_vrreg.h
@@ -720,20 +720,21 @@ struct vr_softc {
 	void			*vr_intrhand;
 	device_t		vr_miibus;
 	uint8_t			vr_revid;	/* Rhine chip revision */
-	uint8_t			vr_flags;	/* See VR_F_* below */
-#define	VR_F_RESTART		0x01		/* Restart unit on next tick */
+	int			vr_flags;	/* See VR_F_* below */
+#define	VR_F_RESTART		0x0001		/* Restart unit on next tick */
+#define	VR_F_TXPAUSE		0x0010
+#define	VR_F_SUSPENDED		0x2000
+#define	VR_F_DETACHED		0x4000
+#define	VR_F_LINK		0x8000
 	int			vr_if_flags;
 	struct vr_chain_data	vr_cdata;
 	struct vr_ring_data	vr_rdata;
 	struct vr_statistics	vr_stat;
 	struct callout		vr_stat_callout;
 	struct mtx		vr_mtx;
-	int			vr_suspended;	/* if 1, sleeping/detaching */
 	int			vr_quirks;
-	int			vr_link;
 	int			vr_watchdog_timer;
 	int			vr_txthresh;
-	int			vr_detach;
 #ifdef DEVICE_POLLING
 	int			rxcycles;
 #endif
diff --git a/sys/dev/vte/if_vte.c b/sys/dev/vte/if_vte.c
index 5e49154..7865ff2 100644
--- a/sys/dev/vte/if_vte.c
+++ b/sys/dev/vte/if_vte.c
@@ -151,7 +151,7 @@ static device_method_t vte_methods[] = {
 	DEVMETHOD(miibus_writereg,	vte_miibus_writereg),
 	DEVMETHOD(miibus_statchg,	vte_miibus_statchg),
 
-	KOBJMETHOD_END
+	DEVMETHOD_END
 };
 
 static driver_t vte_driver = {
@@ -1621,14 +1621,12 @@ static void
 vte_init_locked(struct vte_softc *sc)
 {
 	struct ifnet *ifp;
-	struct mii_data *mii;
 	bus_addr_t paddr;
 	uint8_t *eaddr;
 
 	VTE_LOCK_ASSERT(sc);
 
 	ifp = sc->vte_ifp;
-	mii = device_get_softc(sc->vte_miibus);
 
 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
 		return;
diff --git a/sys/dev/vxge/vxge-osdep.h b/sys/dev/vxge/vxge-osdep.h
index cc1dbd6..f358c91 100644
--- a/sys/dev/vxge/vxge-osdep.h
+++ b/sys/dev/vxge/vxge-osdep.h
@@ -161,7 +161,9 @@ typedef uint16_t		u16;
 typedef int32_t			s32;
 typedef uint32_t		u32;
 typedef unsigned long long int	u64;
+#ifndef __bool_true_false_are_defined
 typedef boolean_t		bool;
+#endif
 typedef bus_addr_t		dma_addr_t;
 typedef struct mtx		spinlock_t;
 typedef struct resource		*pci_irq_h;
diff --git a/sys/dev/wb/if_wb.c b/sys/dev/wb/if_wb.c
index daac022..9c5cd95 100644
--- a/sys/dev/wb/if_wb.c
+++ b/sys/dev/wb/if_wb.c
@@ -212,15 +212,12 @@ static device_method_t wb_methods[] = {
 	DEVMETHOD(device_detach,	wb_detach),
 	DEVMETHOD(device_shutdown,	wb_shutdown),
 
-	/* bus interface, for miibus */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	wb_miibus_readreg),
 	DEVMETHOD(miibus_writereg,	wb_miibus_writereg),
 	DEVMETHOD(miibus_statchg,	wb_miibus_statchg),
-	{ 0, 0 }
+
+	DEVMETHOD_END
 };
 
 static driver_t wb_driver = {
diff --git a/sys/dev/wi/if_wi.c b/sys/dev/wi/if_wi.c
index c31ad7b..d31bdba 100644
--- a/sys/dev/wi/if_wi.c
+++ b/sys/dev/wi/if_wi.c
@@ -108,10 +108,10 @@ __FBSDID("$FreeBSD$");
 #include <dev/wi/if_wireg.h>
 #include <dev/wi/if_wivar.h>
 
-static struct ieee80211vap *wi_vap_create(struct ieee80211com *ic,
-		const char name[IFNAMSIZ], int unit, int opmode, int flags,
-		const uint8_t bssid[IEEE80211_ADDR_LEN],
-		const uint8_t mac[IEEE80211_ADDR_LEN]);
+static struct ieee80211vap *wi_vap_create(struct ieee80211com *,
+		    const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
+		    const uint8_t [IEEE80211_ADDR_LEN],
+		    const uint8_t [IEEE80211_ADDR_LEN]);
 static void wi_vap_delete(struct ieee80211vap *vap);
 static void wi_stop_locked(struct wi_softc *sc, int disable);
 static void wi_start_locked(struct ifnet *);
@@ -507,10 +507,10 @@ wi_detach(device_t dev)
 }
 
 static struct ieee80211vap *
-wi_vap_create(struct ieee80211com *ic,
-	const char name[IFNAMSIZ], int unit, int opmode, int flags,
-	const uint8_t bssid[IEEE80211_ADDR_LEN],
-	const uint8_t mac[IEEE80211_ADDR_LEN])
+wi_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
+    enum ieee80211_opmode opmode, int flags,
+    const uint8_t bssid[IEEE80211_ADDR_LEN],
+    const uint8_t mac[IEEE80211_ADDR_LEN])
 {
 	struct wi_softc *sc = ic->ic_ifp->if_softc;
 	struct wi_vap *wvp;
diff --git a/sys/dev/wpi/if_wpi.c b/sys/dev/wpi/if_wpi.c
index 38ebb7e..fc6f9b1 100644
--- a/sys/dev/wpi/if_wpi.c
+++ b/sys/dev/wpi/if_wpi.c
@@ -157,9 +157,9 @@ static const struct wpi_ident wpi_ident_table[] = {
 };
 
 static struct ieee80211vap *wpi_vap_create(struct ieee80211com *,
-		    const char name[IFNAMSIZ], int unit, int opmode,
-		    int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
-		    const uint8_t mac[IEEE80211_ADDR_LEN]);
+		    const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
+		    const uint8_t [IEEE80211_ADDR_LEN],
+		    const uint8_t [IEEE80211_ADDR_LEN]);
 static void	wpi_vap_delete(struct ieee80211vap *);
 static int	wpi_dma_contig_alloc(struct wpi_softc *, struct wpi_dma_info *,
 		    void **, bus_size_t, bus_size_t, int);
@@ -760,10 +760,10 @@ wpi_detach(device_t dev)
 }
 
 static struct ieee80211vap *
-wpi_vap_create(struct ieee80211com *ic,
-	const char name[IFNAMSIZ], int unit, int opmode, int flags,
-	const uint8_t bssid[IEEE80211_ADDR_LEN],
-	const uint8_t mac[IEEE80211_ADDR_LEN])
+wpi_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
+    enum ieee80211_opmode opmode, int flags,
+    const uint8_t bssid[IEEE80211_ADDR_LEN],
+    const uint8_t mac[IEEE80211_ADDR_LEN])
 {
 	struct wpi_vap *wvp;
 	struct ieee80211vap *vap;
diff --git a/sys/dev/xen/console/console.c b/sys/dev/xen/console/console.c
index 5a14623..6a845ca 100644
--- a/sys/dev/xen/console/console.c
+++ b/sys/dev/xen/console/console.c
@@ -50,6 +50,8 @@ static cn_init_t        xc_cninit;
 static cn_term_t        xc_cnterm;
 static cn_getc_t        xc_cngetc;
 static cn_putc_t        xc_cnputc;
+static cn_grab_t        xc_cngrab;
+static cn_ungrab_t      xc_cnungrab;
 
 #define XC_POLLTIME 	(hz/10)
 
@@ -126,6 +128,16 @@ xc_cnterm(struct consdev *cp)
 { 
 }
 
+static void
+xc_cngrab(struct consdev *cp)
+{
+}
+
+static void
+xc_cnungrab(struct consdev *cp)
+{
+}
+
 static int
 xc_cngetc(struct consdev *dev)
 {
diff --git a/sys/dev/xen/netback/netback.c b/sys/dev/xen/netback/netback.c
index f1af844..6dfb1e9 100644
--- a/sys/dev/xen/netback/netback.c
+++ b/sys/dev/xen/netback/netback.c
@@ -530,7 +530,7 @@ make_tx_response(netif_t *netif,
 #endif
 }
 
-inline static void
+static inline void
 net_tx_action_dealloc(void)
 {
 	gnttab_unmap_grant_ref_t *gop;
diff --git a/sys/dev/xen/pcifront/pcifront.c b/sys/dev/xen/pcifront/pcifront.c
index e6c498b..cdc8f9c 100644
--- a/sys/dev/xen/pcifront/pcifront.c
+++ b/sys/dev/xen/pcifront/pcifront.c
@@ -516,14 +516,14 @@ static device_method_t xpcife_methods[] = {
 	DEVMETHOD(device_suspend,	bus_generic_suspend),
 	DEVMETHOD(device_resume,	bus_generic_resume),
     /* Bus interface */
-    DEVMETHOD(bus_print_child,		bus_generic_print_child),
     DEVMETHOD(bus_alloc_resource,	bus_generic_alloc_resource),
     DEVMETHOD(bus_release_resource,	bus_generic_release_resource),
     DEVMETHOD(bus_activate_resource,	bus_generic_activate_resource),
     DEVMETHOD(bus_deactivate_resource,	bus_generic_deactivate_resource),
     DEVMETHOD(bus_setup_intr,		bus_generic_setup_intr),
     DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
-	{0, 0}
+
+	DEVMETHOD_END
 };
 
 static driver_t xpcife_driver = {
@@ -647,7 +647,7 @@ xpcib_route_interrupt(device_t pcib, device_t dev, int pin)
 
 static device_method_t xpcib_methods[] = {
     /* Device interface */
-    DEVMETHOD(device_probe,			xpcib_probe),
+    DEVMETHOD(device_probe,		xpcib_probe),
     DEVMETHOD(device_attach,		xpcib_attach),
     DEVMETHOD(device_detach,		bus_generic_detach),
     DEVMETHOD(device_shutdown,		bus_generic_shutdown),
@@ -655,7 +655,6 @@ static device_method_t xpcib_methods[] = {
     DEVMETHOD(device_resume,		bus_generic_resume),
 
     /* Bus interface */
-    DEVMETHOD(bus_print_child,		bus_generic_print_child),
     DEVMETHOD(bus_read_ivar,		xpcib_read_ivar),
     DEVMETHOD(bus_alloc_resource,	bus_generic_alloc_resource),
     DEVMETHOD(bus_activate_resource,	bus_generic_activate_resource),
@@ -669,7 +668,8 @@ static device_method_t xpcib_methods[] = {
     DEVMETHOD(pcib_read_config,		xpcib_read_config),
     DEVMETHOD(pcib_write_config,	xpcib_write_config),
     DEVMETHOD(pcib_route_interrupt,	xpcib_route_interrupt),
-    { 0, 0 }
+
+    DEVMETHOD_END
 };
 
 static devclass_t xpcib_devclass;
diff --git a/sys/dev/xl/if_xl.c b/sys/dev/xl/if_xl.c
index b774e7f..7a913f4 100644
--- a/sys/dev/xl/if_xl.c
+++ b/sys/dev/xl/if_xl.c
@@ -310,17 +310,13 @@ static device_method_t xl_methods[] = {
 	DEVMETHOD(device_suspend,	xl_suspend),
 	DEVMETHOD(device_resume,	xl_resume),
 
-	/* bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	xl_miibus_readreg),
 	DEVMETHOD(miibus_writereg,	xl_miibus_writereg),
 	DEVMETHOD(miibus_statchg,	xl_miibus_statchg),
 	DEVMETHOD(miibus_mediainit,	xl_miibus_mediainit),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t xl_driver = {
diff --git a/sys/dev/xl/xlphy.c b/sys/dev/xl/xlphy.c
index e5ac9fc..2fe9e0d 100644
--- a/sys/dev/xl/xlphy.c
+++ b/sys/dev/xl/xlphy.c
@@ -86,7 +86,7 @@ static device_method_t xlphy_methods[] = {
 	DEVMETHOD(device_attach,	xlphy_attach),
 	DEVMETHOD(device_detach,	mii_phy_detach),
 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static devclass_t xlphy_devclass;