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authorjhb <jhb@FreeBSD.org>2009-11-17 18:22:14 +0000
committerjhb <jhb@FreeBSD.org>2009-11-17 18:22:14 +0000
commitc8decde1ac9b2805d8b80fbc6a2a9c08bee4d13e (patch)
treec5680c0a28eb661bd755e21353bebdafdfddc6c2 /sys/dev/wb
parent9fd2522ee91ee46f6e32e5ded433e64953b900e9 (diff)
downloadFreeBSD-src-c8decde1ac9b2805d8b80fbc6a2a9c08bee4d13e.zip
FreeBSD-src-c8decde1ac9b2805d8b80fbc6a2a9c08bee4d13e.tar.gz
Use the bus_*() routines rather than bus_space_*() for register operations.
Diffstat (limited to 'sys/dev/wb')
-rw-r--r--sys/dev/wb/if_wb.c3
-rw-r--r--sys/dev/wb/if_wbreg.h22
2 files changed, 7 insertions, 18 deletions
diff --git a/sys/dev/wb/if_wb.c b/sys/dev/wb/if_wb.c
index d901595..9c2f468 100644
--- a/sys/dev/wb/if_wb.c
+++ b/sys/dev/wb/if_wb.c
@@ -804,9 +804,6 @@ wb_attach(dev)
goto fail;
}
- sc->wb_btag = rman_get_bustag(sc->wb_res);
- sc->wb_bhandle = rman_get_bushandle(sc->wb_res);
-
/* Allocate interrupt */
rid = 0;
sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
diff --git a/sys/dev/wb/if_wbreg.h b/sys/dev/wb/if_wbreg.h
index c5315c4..ce7f46a 100644
--- a/sys/dev/wb/if_wbreg.h
+++ b/sys/dev/wb/if_wbreg.h
@@ -365,8 +365,6 @@ struct wb_softc {
struct ifnet *wb_ifp; /* interface info */
device_t wb_dev;
device_t wb_miibus;
- bus_space_handle_t wb_bhandle;
- bus_space_tag_t wb_btag;
struct resource *wb_res;
struct resource *wb_irq;
void *wb_intrhand;
@@ -388,19 +386,13 @@ struct wb_softc {
/*
* register space access macros
*/
-#define CSR_WRITE_4(sc, reg, val) \
- bus_space_write_4(sc->wb_btag, sc->wb_bhandle, reg, val)
-#define CSR_WRITE_2(sc, reg, val) \
- bus_space_write_2(sc->wb_btag, sc->wb_bhandle, reg, val)
-#define CSR_WRITE_1(sc, reg, val) \
- bus_space_write_1(sc->wb_btag, sc->wb_bhandle, reg, val)
-
-#define CSR_READ_4(sc, reg) \
- bus_space_read_4(sc->wb_btag, sc->wb_bhandle, reg)
-#define CSR_READ_2(sc, reg) \
- bus_space_read_2(sc->wb_btag, sc->wb_bhandle, reg)
-#define CSR_READ_1(sc, reg) \
- bus_space_read_1(sc->wb_btag, sc->wb_bhandle, reg)
+#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->wb_res, reg, val)
+#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->wb_res, reg, val)
+#define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->wb_res, reg, val)
+
+#define CSR_READ_4(sc, reg) bus_read_4(sc->wb_res, reg)
+#define CSR_READ_2(sc, reg) bus_read_2(sc->wb_res, reg)
+#define CSR_READ_1(sc, reg) bus_read_1(sc->wb_res, reg)
#define WB_TIMEOUT 1000
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