diff options
| author | yongari <yongari@FreeBSD.org> | 2011-06-01 18:42:44 +0000 |
|---|---|---|
| committer | yongari <yongari@FreeBSD.org> | 2011-06-01 18:42:44 +0000 |
| commit | 9b5209bba0c74f739138641bc5061bd67b995fef (patch) | |
| tree | 366c2eda6366e4ecc3bafa785852bd74ff4fbccc /sys/dev/usb/net/if_axe.c | |
| parent | 3e0b323798d7bfc88808757802a3ebc36bbc0a89 (diff) | |
| download | FreeBSD-src-9b5209bba0c74f739138641bc5061bd67b995fef.zip FreeBSD-src-9b5209bba0c74f739138641bc5061bd67b995fef.tar.gz | |
Poke correct GPIO pins for newer axe(4) controllers with Marvell
PHY. Newer models seem to use different LED mode that requires
enabling both GPIO1 and GPIO2.
Tested by: marcel
Diffstat (limited to 'sys/dev/usb/net/if_axe.c')
| -rw-r--r-- | sys/dev/usb/net/if_axe.c | 21 |
1 files changed, 18 insertions, 3 deletions
diff --git a/sys/dev/usb/net/if_axe.c b/sys/dev/usb/net/if_axe.c index fbe63de..00d1c0b 100644 --- a/sys/dev/usb/net/if_axe.c +++ b/sys/dev/usb/net/if_axe.c @@ -514,7 +514,7 @@ static void axe_ax88178_init(struct axe_softc *sc) { struct usb_ether *ue; - int gpio0, phymode; + int gpio0, ledmode, phymode; uint16_t eeprom, val; ue = &sc->sc_ue; @@ -528,9 +528,11 @@ axe_ax88178_init(struct axe_softc *sc) if (eeprom == 0xffff) { phymode = AXE_PHY_MODE_MARVELL; gpio0 = 1; + ledmode = 0; } else { phymode = eeprom & 0x7f; gpio0 = (eeprom & 0x80) ? 0 : 1; + ledmode = eeprom >> 8; } if (bootverbose) @@ -548,9 +550,22 @@ axe_ax88178_init(struct axe_softc *sc) AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); - } else + } else { AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | - AXE_GPIO1_EN, hz / 32); + AXE_GPIO1_EN, hz / 3); + if (ledmode == 1) { + AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); + AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, + hz / 3); + } else { + AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | + AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); + AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | + AXE_GPIO2_EN, hz / 4); + AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | + AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); + } + } break; case AXE_PHY_MODE_CICADA: case AXE_PHY_MODE_CICADA_V2: |
