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| author | thompsa <thompsa@FreeBSD.org> | 2009-10-15 20:07:08 +0000 |
|---|---|---|
| committer | thompsa <thompsa@FreeBSD.org> | 2009-10-15 20:07:08 +0000 |
| commit | 9ffd1abaff203b88fedf254c933b99335429dcbb (patch) | |
| tree | a1b09c916a2bf1f05cd74b5d3fd23f45d619df7e /sys/dev/usb/controller/uhci.h | |
| parent | f410b0c1a3942e89e48f85a60e4412d5d3a763a7 (diff) | |
| download | FreeBSD-src-9ffd1abaff203b88fedf254c933b99335429dcbb.zip FreeBSD-src-9ffd1abaff203b88fedf254c933b99335429dcbb.tar.gz | |
Workaround buggy BIOS code in USB regard. By doing the BIOS to OS handover for
all host controllers at the same time, we avoid problems where the BIOS will
actually write to the USB registers of all the USB host controllers every time
we handover one of them, and consequently reset the OS programmed values.
Submitted by: avg
Reviewed by: jhb
Diffstat (limited to 'sys/dev/usb/controller/uhci.h')
| -rw-r--r-- | sys/dev/usb/controller/uhci.h | 60 |
1 files changed, 0 insertions, 60 deletions
diff --git a/sys/dev/usb/controller/uhci.h b/sys/dev/usb/controller/uhci.h index f2ea246..f526431 100644 --- a/sys/dev/usb/controller/uhci.h +++ b/sys/dev/usb/controller/uhci.h @@ -41,64 +41,6 @@ #define UHCI_MAX_DEVICES MIN(USB_MAX_DEVICES, 128) -/* PCI config registers */ -#define PCI_USBREV 0x60 /* USB protocol revision */ -#define PCI_USB_REV_MASK 0xff -#define PCI_USB_REV_PRE_1_0 0x00 -#define PCI_USB_REV_1_0 0x10 -#define PCI_USB_REV_1_1 0x11 -#define PCI_LEGSUP 0xc0 /* Legacy Support register */ -#define PCI_LEGSUP_USBPIRQDEN 0x2000 /* USB PIRQ D Enable */ -#define PCI_CBIO 0x20 /* configuration base IO */ -#define PCI_INTERFACE_UHCI 0x00 - -/* UHCI registers */ -#define UHCI_CMD 0x00 -#define UHCI_CMD_RS 0x0001 -#define UHCI_CMD_HCRESET 0x0002 -#define UHCI_CMD_GRESET 0x0004 -#define UHCI_CMD_EGSM 0x0008 -#define UHCI_CMD_FGR 0x0010 -#define UHCI_CMD_SWDBG 0x0020 -#define UHCI_CMD_CF 0x0040 -#define UHCI_CMD_MAXP 0x0080 -#define UHCI_STS 0x02 -#define UHCI_STS_USBINT 0x0001 -#define UHCI_STS_USBEI 0x0002 -#define UHCI_STS_RD 0x0004 -#define UHCI_STS_HSE 0x0008 -#define UHCI_STS_HCPE 0x0010 -#define UHCI_STS_HCH 0x0020 -#define UHCI_STS_ALLINTRS 0x003f -#define UHCI_INTR 0x04 -#define UHCI_INTR_TOCRCIE 0x0001 -#define UHCI_INTR_RIE 0x0002 -#define UHCI_INTR_IOCE 0x0004 -#define UHCI_INTR_SPIE 0x0008 -#define UHCI_FRNUM 0x06 -#define UHCI_FRNUM_MASK 0x03ff -#define UHCI_FLBASEADDR 0x08 -#define UHCI_SOF 0x0c -#define UHCI_SOF_MASK 0x7f -#define UHCI_PORTSC1 0x010 -#define UHCI_PORTSC2 0x012 -#define UHCI_PORTSC_CCS 0x0001 -#define UHCI_PORTSC_CSC 0x0002 -#define UHCI_PORTSC_PE 0x0004 -#define UHCI_PORTSC_POEDC 0x0008 -#define UHCI_PORTSC_LS 0x0030 -#define UHCI_PORTSC_LS_SHIFT 4 -#define UHCI_PORTSC_RD 0x0040 -#define UHCI_PORTSC_LSDA 0x0100 -#define UHCI_PORTSC_PR 0x0200 -#define UHCI_PORTSC_OCI 0x0400 -#define UHCI_PORTSC_OCIC 0x0800 -#define UHCI_PORTSC_SUSP 0x1000 - -#define URWMASK(x) ((x) & (UHCI_PORTSC_SUSP | \ - UHCI_PORTSC_PR | UHCI_PORTSC_RD | \ - UHCI_PORTSC_PE)) - #define UHCI_FRAMELIST_COUNT 1024 /* units */ #define UHCI_FRAMELIST_ALIGN 4096 /* bytes */ @@ -118,8 +60,6 @@ typedef uint32_t uhci_physaddr_t; #define UHCI_PTR_QH 0x00000002 #define UHCI_PTR_VF 0x00000004 -#define UHCI_QH_REMOVE_DELAY 5 /* us - QH remove delay */ - /* * The Queue Heads (QH) and Transfer Descriptors (TD) are accessed by * both the CPU and the USB-controller which run concurrently. Great |
