diff options
| author | jhb <jhb@FreeBSD.org> | 2009-11-17 18:22:14 +0000 |
|---|---|---|
| committer | jhb <jhb@FreeBSD.org> | 2009-11-17 18:22:14 +0000 |
| commit | c8decde1ac9b2805d8b80fbc6a2a9c08bee4d13e (patch) | |
| tree | c5680c0a28eb661bd755e21353bebdafdfddc6c2 /sys/dev/tl | |
| parent | 9fd2522ee91ee46f6e32e5ded433e64953b900e9 (diff) | |
| download | FreeBSD-src-c8decde1ac9b2805d8b80fbc6a2a9c08bee4d13e.zip FreeBSD-src-c8decde1ac9b2805d8b80fbc6a2a9c08bee4d13e.tar.gz | |
Use the bus_*() routines rather than bus_space_*() for register operations.
Diffstat (limited to 'sys/dev/tl')
| -rw-r--r-- | sys/dev/tl/if_tl.c | 3 | ||||
| -rw-r--r-- | sys/dev/tl/if_tlreg.h | 22 |
2 files changed, 7 insertions, 18 deletions
diff --git a/sys/dev/tl/if_tl.c b/sys/dev/tl/if_tl.c index f1a3db8..2d23b5e 100644 --- a/sys/dev/tl/if_tl.c +++ b/sys/dev/tl/if_tl.c @@ -1170,9 +1170,6 @@ tl_attach(dev) goto fail; } - sc->tl_btag = rman_get_bustag(sc->tl_res); - sc->tl_bhandle = rman_get_bushandle(sc->tl_res); - #ifdef notdef /* * The ThunderLAN manual suggests jacking the PCI latency diff --git a/sys/dev/tl/if_tlreg.h b/sys/dev/tl/if_tlreg.h index f04b52b..46a7986 100644 --- a/sys/dev/tl/if_tlreg.h +++ b/sys/dev/tl/if_tlreg.h @@ -112,8 +112,6 @@ struct tl_softc { struct ifnet *tl_ifp; device_t tl_dev; struct ifmedia ifmedia; /* media info */ - bus_space_handle_t tl_bhandle; - bus_space_tag_t tl_btag; void *tl_intrhand; struct resource *tl_irq; struct resource *tl_res; @@ -493,19 +491,13 @@ struct tl_stats { /* * register space access macros */ -#define CSR_WRITE_4(sc, reg, val) \ - bus_space_write_4(sc->tl_btag, sc->tl_bhandle, reg, val) -#define CSR_WRITE_2(sc, reg, val) \ - bus_space_write_2(sc->tl_btag, sc->tl_bhandle, reg, val) -#define CSR_WRITE_1(sc, reg, val) \ - bus_space_write_1(sc->tl_btag, sc->tl_bhandle, reg, val) - -#define CSR_READ_4(sc, reg) \ - bus_space_read_4(sc->tl_btag, sc->tl_bhandle, reg) -#define CSR_READ_2(sc, reg) \ - bus_space_read_2(sc->tl_btag, sc->tl_bhandle, reg) -#define CSR_READ_1(sc, reg) \ - bus_space_read_1(sc->tl_btag, sc->tl_bhandle, reg) +#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->tl_res, reg, val) +#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->tl_res, reg, val) +#define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->tl_res, reg, val) + +#define CSR_READ_4(sc, reg) bus_read_4(sc->tl_res, reg) +#define CSR_READ_2(sc, reg) bus_read_2(sc->tl_res, reg) +#define CSR_READ_1(sc, reg) bus_read_1(sc->tl_res, reg) #define CMD_PUT(sc, x) CSR_WRITE_4(sc, TL_HOSTCMD, x) #define CMD_SET(sc, x) \ |
