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authorRenato Botelho <renato@netgate.com>2018-05-18 14:53:44 -0300
committerRenato Botelho <renato@netgate.com>2018-05-18 14:53:44 -0300
commit64f021cd075bbcb3042539dcebc63e7d335ec2c0 (patch)
tree1a64375406a7b5976f98eaf4cf19f00cf2931dd1 /sys/dev/sdhci/sdhci_acpi.c
parent8f29f1de284afe0ec8987780d5404a3e1a31712a (diff)
parenteb64daea863b1fe3320e10c6c72cbfe7e9ce967b (diff)
downloadFreeBSD-src-64f021cd075bbcb3042539dcebc63e7d335ec2c0.zip
FreeBSD-src-64f021cd075bbcb3042539dcebc63e7d335ec2c0.tar.gz
Merge remote-tracking branch 'origin/stable/11' into devel-11
Diffstat (limited to 'sys/dev/sdhci/sdhci_acpi.c')
-rw-r--r--sys/dev/sdhci/sdhci_acpi.c10
1 files changed, 7 insertions, 3 deletions
diff --git a/sys/dev/sdhci/sdhci_acpi.c b/sys/dev/sdhci/sdhci_acpi.c
index 16e29f8..b7074c3 100644
--- a/sys/dev/sdhci/sdhci_acpi.c
+++ b/sys/dev/sdhci/sdhci_acpi.c
@@ -60,7 +60,6 @@ static const struct sdhci_acpi_device {
{ "80860F14", 1, "Intel Bay Trail/Braswell eMMC 4.5/4.5.1 Controller",
SDHCI_QUIRK_INTEL_POWER_UP_RESET |
SDHCI_QUIRK_WAIT_WHILE_BUSY |
- SDHCI_QUIRK_MMC_DDR52 |
SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
SDHCI_QUIRK_PRESET_VALUE_BROKEN },
{ "80860F14", 3, "Intel Bay Trail/Braswell SDXC Controller",
@@ -261,11 +260,16 @@ sdhci_acpi_attach(device_t dev)
return (ENOMEM);
}
- /* Intel Braswell eMMC 4.5.1 controller quirk */
+ /*
+ * Intel Bay Trail and Braswell eMMC controllers share the same IDs,
+ * but while with these former DDR52 is affected by the VLI54 erratum,
+ * these latter require the timeout clock to be hardcoded to 1 MHz.
+ */
if (strcmp(acpi_dev->hid, "80860F14") == 0 && acpi_dev->uid == 1 &&
SDHCI_READ_4(dev, &sc->slot, SDHCI_CAPABILITIES) == 0x446cc8b2 &&
SDHCI_READ_4(dev, &sc->slot, SDHCI_CAPABILITIES2) == 0x00000807)
- sc->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_1MHZ;
+ sc->quirks |= SDHCI_QUIRK_MMC_DDR52 |
+ SDHCI_QUIRK_DATA_TIMEOUT_1MHZ;
sc->quirks &= ~sdhci_quirk_clear;
sc->quirks |= sdhci_quirk_set;
sc->slot.quirks = sc->quirks;
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