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| author | ian <ian@FreeBSD.org> | 2014-12-20 01:13:13 +0000 |
|---|---|---|
| committer | ian <ian@FreeBSD.org> | 2014-12-20 01:13:13 +0000 |
| commit | 7814dfac2fc976412cebca6c48d0b949f495c1c1 (patch) | |
| tree | ff1a6817bca2c031c02e20ad2184b75062530784 /sys/dev/sdhci/sdhci.h | |
| parent | f2e6cf3c8743406f318dbc756d18cd6bf9fb3509 (diff) | |
| download | FreeBSD-src-7814dfac2fc976412cebca6c48d0b949f495c1c1.zip FreeBSD-src-7814dfac2fc976412cebca6c48d0b949f495c1c1.tar.gz | |
Add a new sdhci quirk, SDHCI_QUIRK_WAITFOR_RESET_ASSERTED, to work around
TI OMAP controllers which will return the reset-in-progress bit as zero if
you read the status register too fast after setting the reset bit.
The zero is apparently from a stale snapshot of the internal state presented
in the interface register, and leads to a false indication that the reset
is complete when it either hasn't started yet or is in-progress. The
workaround is to first loop until the bit is seen as asserted, then do the
normal loop waiting to see it de-asserted.
Submitted by: Michal Meloun <meloun@miracle.cz>
Diffstat (limited to 'sys/dev/sdhci/sdhci.h')
| -rw-r--r-- | sys/dev/sdhci/sdhci.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/sys/dev/sdhci/sdhci.h b/sys/dev/sdhci/sdhci.h index f2679fc..ff1576e 100644 --- a/sys/dev/sdhci/sdhci.h +++ b/sys/dev/sdhci/sdhci.h @@ -59,6 +59,8 @@ #define SDHCI_QUIRK_MISSING_CAPS (1<<12) /* Hardware shifts the 136-bit response, don't do it in software. */ #define SDHCI_QUIRK_DONT_SHIFT_RESPONSE (1<<13) +/* Wait to see reset bit asserted before waiting for de-asserted */ +#define SDHCI_QUIRK_WAITFOR_RESET_ASSERTED (1<<14) /* * Controller registers |
