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| author | marius <marius@FreeBSD.org> | 2017-01-18 23:25:46 +0000 |
|---|---|---|
| committer | marius <marius@FreeBSD.org> | 2017-01-18 23:25:46 +0000 |
| commit | 008ff9eee5f55c6da4d42a6c3f1201b8dc98a726 (patch) | |
| tree | d306e45fdb4593bce5b7b0663eec831e6982472c /sys/dev/sdhci/sdhci.h | |
| parent | dc0b18d57b66d178dc4334057db897f1e0535169 (diff) | |
| download | FreeBSD-src-008ff9eee5f55c6da4d42a6c3f1201b8dc98a726.zip FreeBSD-src-008ff9eee5f55c6da4d42a6c3f1201b8dc98a726.tar.gz | |
MFC: r310309, r310340-310341, r311664, r311793-r311794
o sdhci/mmc: Minor whitespace cleanups
o Add Braswell PCI IDs for Intel Cherryview
o mmc: Accept even lower voltage for Cherryview
And HP x2 210, per DragonFlyBSD 240bd9cd58f8259c12c14a8006837e698.
o In mmcsd_task(), bio_resid was not being set to 0 on a successful read
or write, resulting in random short-read and short-write returns for
requests. Fixing this fixes nominal block I/O via mmcsd(4).
Obtained from: DragonFlyBSD (fd4b97583be1a1e57234713c25f6e81bc0411cb0)
o Add support for Intel Apollo Lake and Bay Trail eMMC PCI controllers.
o Flesh out the support for Intel Braswell eMMC controllers further.
o In sdhci_init_slot(), use the right capability field for determining
the announced bus width based on MMC_CAP_*_BIT_DATA.
Diffstat (limited to 'sys/dev/sdhci/sdhci.h')
| -rw-r--r-- | sys/dev/sdhci/sdhci.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/sys/dev/sdhci/sdhci.h b/sys/dev/sdhci/sdhci.h index 3f2f73a..4626816 100644 --- a/sys/dev/sdhci/sdhci.h +++ b/sys/dev/sdhci/sdhci.h @@ -66,7 +66,13 @@ /* Alternate clock source is required when supplying a 400 KHz clock. */ #define SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC (1<<16) /* Card insert/remove interrupts don't work, polling required. */ -#define SDHCI_QUIRK_POLL_CARD_PRESENT (1<<17) +#define SDHCI_QUIRK_POLL_CARD_PRESENT (1<<17) +/* All controller slots are non-removable. */ +#define SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE (1<<18) +/* Issue custom Intel controller reset sequence after power-up. */ +#define SDHCI_QUIRK_INTEL_POWER_UP_RESET (1<<19) +/* Data timeout is invalid, use 1 MHz clock instead. */ +#define SDHCI_QUIRK_DATA_TIMEOUT_1MHZ (1<<20) /* * Controller registers |
