MFC: r281751

Refine the workaround for Intel HSD131 [1] added in r269052 (MFCed to
stable/10 in r269592):
- Use the full mask described by the erratum as with a sufficiently high
  number of these false-positives, the overflow bit (bit 62) additionally
  gets set [7].
- HSD131 has been brought into several other Haswell-derived CPUs including
  to the next generation, i. e. Intel Broadwell. Thus, also skip reporting of
  these benign errors by default on CPU models affected by HSM142, HSW131 and
  BDM48 [2 - 5], describing the HSD131 silicon bug for additional models.
  Also, Celeron 2955U with a CPU ID of 0x45 have been reported to be covered
  by this fault [6], with the specification update concerned with HSM142 [2]
  only referring to 0x3c and 0x46.

Submitted by:	David Froehlich [7]
Approved by:	re (kib)

http://www.intel.de/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-desktop-specification-update.pdf [1]
http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-mobile-specification-update.pdf [2]
http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/5th-gen-core-family-spec-update.pdf [3]
http://www.intel.de/content/dam/www/public/us/en/documents/specification-updates/core-m-processor-family-spec-update.pdf [4]
http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-e3-1200v3-spec-update.pdf [5]
https://lists.freebsd.org/pipermail/freebsd-hackers/2015-January/046878.html [6]

0 files changed, 0 insertions, 0 deletions