- Add constants for HT PCI capability registers including the various

  subtypes of HT capabilities.
- Add constants for the MSI mapping window HT PCI capability.
- On i386 and amd64, enable the MSI mapping window on any HT bridges we
  encounter and report any non-standard mapping window addresses.

2 files changed, 51 insertions, 0 deletions

diff --git a/sys/dev/pci/pci.c b/sys/dev/pci/pci.c
index f8af0f9..ff83305 100644
--- a/sys/dev/pci/pci.c
+++ b/sys/dev/pci/pci.c
@@ -52,6 +52,10 @@ __FBSDID("$FreeBSD$");
 #include <sys/rman.h>
 #include <machine/resource.h>
 
+#if defined(__i386__) || defined(__amd64__)
+#include <machine/intr_machdep.h>
+#endif
+
 #include <sys/pciio.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
@@ -443,6 +447,9 @@ pci_read_extcap(device_t pcib, pcicfgregs *cfg)
 {
 #define REG(n, w)	PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
 #define WREG(n, v, w)	PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
+#if defined(__i386__) || defined(__amd64__)
+	uint64_t addr;
+#endif
 	uint32_t val;
 	int	ptr, nextptr, ptrptr;
 
@@ -484,6 +491,29 @@ pci_read_extcap(device_t pcib, pcicfgregs *cfg)
 					cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
 			}
 			break;
+#if defined(__i386__) || defined(__amd64__)
+		case PCIY_HT:		/* HyperTransport */
+			/* Determine HT-specific capability type. */
+			val = REG(ptr + PCIR_HT_COMMAND, 2);
+			switch (val & PCIM_HTCMD_CAP_MASK) {
+			case PCIM_HTCAP_MSI_MAPPING:
+				/* Sanity check the mapping window. */
+				addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 4);
+				addr <<= 32;
+				addr = REG(ptr + PCIR_HTMSI_ADDRESS_LO, 4);
+				if (addr != MSI_INTEL_ADDR_BASE)
+					device_printf(pcib,
+		    "HT Bridge at %d:%d:%d has non-default MSI window 0x%llx\n",
+					    cfg->bus, cfg->slot, cfg->func,
+					    (long long)addr);
+
+				/* Enable MSI -> HT mapping. */
+				val |= PCIM_HTCMD_MSI_ENABLE;
+				WREG(ptr + PCIR_HT_COMMAND, val, 2);
+				break;
+			}
+			break;
+#endif
 		case PCIY_MSI:		/* PCI MSI */
 			cfg->msi.msi_location = ptr;
 			cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
diff --git a/sys/dev/pci/pcireg.h b/sys/dev/pci/pcireg.h
index a3ff90b..6637ad3 100644
--- a/sys/dev/pci/pcireg.h
+++ b/sys/dev/pci/pcireg.h
@@ -431,6 +431,27 @@
 #define PCIXM_STATUS_MAXCRDS	0x1C00	/* Maximum Cumulative Read Size */
 #define PCIXM_STATUS_RCVDSCEM	0x2000	/* Received a Split Comp w/Error msg */
 
+/* HT (HyperTransport) Capability definitions */
+#define	PCIR_HT_COMMAND		0x2
+#define	PCIM_HTCMD_CAP_MASK		0xf800	/* Capability type. */
+#define	PCIM_HTCAP_SLAVE		0x0000	/* 000xx */
+#define	PCIM_HTCAP_HOST			0x2000	/* 001xx */
+#define	PCIM_HTCAP_SWITCH		0x4000	/* 01000 */
+#define	PCIM_HTCAP_INTERRUPT		0x8000	/* 10000 */
+#define	PCIM_HTCAP_REVISION_ID		0x8800	/* 10001 */
+#define	PCIM_HTCAP_UNITID_CLUMPING	0x9000	/* 10010 */
+#define	PCIM_HTCAP_EXT_CONFIG_SPACE	0x9800	/* 10011 */
+#define	PCIM_HTCAP_ADDRESS_MAPPING	0xa000	/* 10100 */
+#define	PCIM_HTCAP_MSI_MAPPING		0xa800	/* 10101 */
+#define	PCIM_HTCAP_DIRECT_ROUTE		0xb000	/* 10110 */
+#define	PCIM_HTCAP_VCSET		0xb800	/* 10111 */
+#define	PCIM_HTCAP_RETRY_MODE		0xc000	/* 11000 */
+
+/* HT MSI Mapping Capability definitions. */
+#define	PCIM_HTCMD_MSI_ENABLE		0x0001
+#define	PCIR_HTMSI_ADDRESS_LO	0x4
+#define	PCIR_HTMSI_ADDRESS_HI	0x8
+
 /* MSI-X definitions */
 #define	PCIR_MSIX_CTRL		0x2
 #define	PCIM_MSIXCTRL_MSIX_ENABLE	0x8000