Add driver support for 88E3016 PHY which is found on Marvell Yukon

FE+ controller. Due to the severe silicon bugs for Yukon FE+,
88E3016 seems to require more workarounds. However I'm not sure
whether the workaround is PHY specific or only applicable to Yukon
FE+. The datasheet for the PHY is publicly available but it lacks
several details for the workaround used in this change. The
workaround information was obtained from Linux. Many thanks to
Yukon FE+ users who helped me add 88E3016 support.

Tested by:	bz, Tanguy Bouzeloc ( the.zauron <> gmail dot com )
		Bruce Cran ( bruce <> cran dot org dot uk )
		Michael Reifenberger ( mike <> reifenberger dot com )
		Stephen Montgomery-Smith ( stephen <> missouri dot edu )

1 files changed, 23 insertions, 4 deletions

diff --git a/sys/dev/mii/e1000phy.c b/sys/dev/mii/e1000phy.c
index 0025e76..9f9b986 100644
--- a/sys/dev/mii/e1000phy.c
+++ b/sys/dev/mii/e1000phy.c
@@ -107,6 +107,7 @@ static const struct mii_phydesc e1000phys[] = {
 	MII_PHY_DESC(MARVELL, E1116),
 	MII_PHY_DESC(MARVELL, E1116R),
 	MII_PHY_DESC(MARVELL, E1118),
+	MII_PHY_DESC(MARVELL, E3016),
 	MII_PHY_DESC(xxMARVELL, E1000),
 	MII_PHY_DESC(xxMARVELL, E1011),
 	MII_PHY_DESC(xxMARVELL, E1000_3),
@@ -212,18 +213,29 @@ e1000phy_reset(struct mii_softc *sc)
 			reg |= E1000_SCR_AUTO_X_MODE;
 			if (esc->mii_model == MII_MODEL_MARVELL_E1116)
 				reg &= ~E1000_SCR_POWER_DOWN;
+			reg |= E1000_SCR_ASSERT_CRS_ON_TX;
 			break;
 		case MII_MODEL_MARVELL_E3082:
 			reg |= (E1000_SCR_AUTO_X_MODE >> 1);
+			reg |= E1000_SCR_ASSERT_CRS_ON_TX;
+			break;
+		case MII_MODEL_MARVELL_E3016:
+			reg |= E1000_SCR_AUTO_MDIX;
+			reg &= ~(E1000_SCR_EN_DETECT |
+			    E1000_SCR_SCRAMBLER_DISABLE);
+			reg |= E1000_SCR_LPNP;
+			/* XXX Enable class A driver for Yukon FE+ A0. */
+			PHY_WRITE(sc, 0x1C, PHY_READ(sc, 0x1C) | 0x0001);
 			break;
 		default:
 			reg &= ~E1000_SCR_AUTO_X_MODE;
+			reg |= E1000_SCR_ASSERT_CRS_ON_TX;
 			break;
 		}
-		/* Enable CRS on TX. */
-		reg |= E1000_SCR_ASSERT_CRS_ON_TX;
-		/* Auto correction for reversed cable polarity. */
-		reg &= ~E1000_SCR_POLARITY_REVERSAL;
+		if (esc->mii_model != MII_MODEL_MARVELL_E3016) {
+			/* Auto correction for reversed cable polarity. */
+			reg &= ~E1000_SCR_POLARITY_REVERSAL;
+		}
 		PHY_WRITE(sc, E1000_SCR, reg);
 
 		if (esc->mii_model == MII_MODEL_MARVELL_E1116) {
@@ -242,6 +254,13 @@ e1000phy_reset(struct mii_softc *sc)
 	case MII_MODEL_MARVELL_E1118:
 	case MII_MODEL_MARVELL_E1149:
 		break;
+	case MII_MODEL_MARVELL_E3016:
+		/* LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED. */
+		PHY_WRITE(sc, 0x16, 0x0B << 8 | 0x05 << 4 | 0x04);
+		/* Integrated register calibration workaround. */
+		PHY_WRITE(sc, 0x1D, 17);
+		PHY_WRITE(sc, 0x1E, 0x3F60);
+		break;
 	default:
 		/* Force TX_CLK to 25MHz clock. */
 		reg = PHY_READ(sc, E1000_ESCR);