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author | yongari <yongari@FreeBSD.org> | 2007-06-06 06:55:49 +0000 |
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committer | yongari <yongari@FreeBSD.org> | 2007-06-06 06:55:49 +0000 |
commit | 808e1dd3821f815fc3b7642b97842dc2b5e731fd (patch) | |
tree | 61cfd04f59c71e43ea2881f6d9850e3a5cfa5868 /sys/dev/mii/ciphyreg.h | |
parent | 00eff901d287a6882cc3db762bc32dc8e651e319 (diff) | |
download | FreeBSD-src-808e1dd3821f815fc3b7642b97842dc2b5e731fd.zip FreeBSD-src-808e1dd3821f815fc3b7642b97842dc2b5e731fd.tar.gz |
Add support Vitesse VSC8601 PHY that is found on nVidia network
adapters.
Submitted by: Shigeaki Tagashira < shigeaki AT se DOT hiroshima-u DOT ac DOT jp >
Tested by: Yuri Pankov < yuri.pankov AT gmail DOT com>,
Rainer Hurling <rhurlin AT gwdg DOT de >
Diffstat (limited to 'sys/dev/mii/ciphyreg.h')
-rw-r--r-- | sys/dev/mii/ciphyreg.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/sys/dev/mii/ciphyreg.h b/sys/dev/mii/ciphyreg.h index 8c0a8a4..3c5c5de 100644 --- a/sys/dev/mii/ciphyreg.h +++ b/sys/dev/mii/ciphyreg.h @@ -251,6 +251,16 @@ /* Extended PHY control register #1 */ #define CIPHY_MII_ECTL1 0x17 #define CIPHY_ECTL1_ACTIPHY 0x0020 /* Enable ActiPHY power saving */ +#define CIPHY_ECTL1_IOVOL 0x0e00 /* MAC interface and I/O voltage select */ +#define CIPHY_ECTL1_INTSEL 0xf000 /* select MAC interface */ + +#define CIPHY_IOVOL_3300MV 0x0000 /* 3.3V for I/O pins */ +#define CIPHY_IOVOL_2500MV 0x0200 /* 2.5V for I/O pins */ + +#define CIPHY_INTSEL_GMII 0x0000 /* GMII/MII */ +#define CIPHY_INTSEL_RGMII 0x1000 +#define CIPHY_INTSEL_TBI 0x2000 +#define CIPHY_INTSEL_RTBI 0x3000 /* Extended PHY control register #2 */ #define CIPHY_MII_ECTL2 0x18 |