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authormav <mav@FreeBSD.org>2015-12-04 19:46:49 +0000
committermav <mav@FreeBSD.org>2015-12-04 19:46:49 +0000
commitfcabb159f2d6c02d74cd93ce1b97d7d4d54c2b80 (patch)
treeecfef18819468cc53bc818248f791cce42e9e7ea /sys/dev/isp/isp_pci.c
parent55287fc50de580564157174394bccdea58bf7766 (diff)
downloadFreeBSD-src-fcabb159f2d6c02d74cd93ce1b97d7d4d54c2b80.zip
FreeBSD-src-fcabb159f2d6c02d74cd93ce1b97d7d4d54c2b80.tar.gz
Make 16Gig chips to use new queue pointer registers.
While 24xx-style ATIO and reply queue registers seems like still working, request queue doesn't. So instead of that use registers from PCI BAR(4).
Diffstat (limited to 'sys/dev/isp/isp_pci.c')
-rw-r--r--sys/dev/isp/isp_pci.c140
1 files changed, 110 insertions, 30 deletions
diff --git a/sys/dev/isp/isp_pci.c b/sys/dev/isp/isp_pci.c
index 7923d7b..bd0ceea 100644
--- a/sys/dev/isp/isp_pci.c
+++ b/sys/dev/isp/isp_pci.c
@@ -59,6 +59,8 @@ static uint32_t isp_pci_rd_reg_1080(ispsoftc_t *, int);
static void isp_pci_wr_reg_1080(ispsoftc_t *, int, uint32_t);
static uint32_t isp_pci_rd_reg_2400(ispsoftc_t *, int);
static void isp_pci_wr_reg_2400(ispsoftc_t *, int, uint32_t);
+static uint32_t isp_pci_rd_reg_2600(ispsoftc_t *, int);
+static void isp_pci_wr_reg_2600(ispsoftc_t *, int, uint32_t);
static int isp_pci_rd_isr(ispsoftc_t *, uint16_t *, uint16_t *, uint16_t *);
static int isp_pci_rd_isr_2300(ispsoftc_t *, uint16_t *, uint16_t *, uint16_t *);
static int isp_pci_rd_isr_2400(ispsoftc_t *, uint16_t *, uint16_t *, uint16_t *);
@@ -174,8 +176,8 @@ static struct ispmdvec mdvec_2500 = {
static struct ispmdvec mdvec_2600 = {
isp_pci_rd_isr_2400,
- isp_pci_rd_reg_2400,
- isp_pci_wr_reg_2400,
+ isp_pci_rd_reg_2600,
+ isp_pci_wr_reg_2600,
isp_pci_mbxdma,
isp_pci_dmasetup,
isp_common_dmateardown,
@@ -364,10 +366,13 @@ struct isp_pcisoftc {
ispsoftc_t pci_isp;
device_t pci_dev;
struct resource * regs;
+ struct resource * regs2;
void * irq;
int iqd;
int rtp;
int rgd;
+ int rtp2;
+ int rgd2;
void * ih;
int16_t pci_poff[_NREG_BLKS];
bus_dma_tag_t dmat;
@@ -684,7 +689,7 @@ isp_pci_attach(device_t dev)
isp_get_generic_options(dev, isp);
linesz = PCI_DFLT_LNSZ;
- pcs->irq = pcs->regs = NULL;
+ pcs->irq = pcs->regs = pcs->regs2 = NULL;
pcs->rgd = pcs->rtp = pcs->iqd = 0;
pcs->pci_dev = dev;
@@ -813,6 +818,10 @@ isp_pci_attach(device_t dev)
pcs->rgd = PCIR_BAR(0);
pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd,
RF_ACTIVE);
+ pcs->rtp2 = SYS_RES_MEMORY;
+ pcs->rgd2 = PCIR_BAR(4);
+ pcs->regs2 = bus_alloc_resource_any(dev, pcs->rtp2, &pcs->rgd2,
+ RF_ACTIVE);
} else {
pcs->rtp = SYS_RES_MEMORY;
pcs->rgd = PCIR_BAR(1);
@@ -833,8 +842,8 @@ isp_pci_attach(device_t dev)
device_printf(dev, "Using %s space register mapping\n",
(pcs->rtp == SYS_RES_IOPORT)? "I/O" : "Memory");
}
- isp->isp_bus_tag = rman_get_bustag(pcs->regs);
- isp->isp_bus_handle = rman_get_bushandle(pcs->regs);
+ isp->isp_regs = pcs->regs;
+ isp->isp_regs2 = pcs->regs2;
if (IS_FC(isp)) {
psize = sizeof (fcparam);
@@ -984,9 +993,10 @@ bad:
if (pcs->msicount) {
pci_release_msi(dev);
}
- if (pcs->regs) {
+ if (pcs->regs)
(void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs);
- }
+ if (pcs->regs2)
+ (void) bus_release_resource(dev, pcs->rtp2, pcs->rgd2, pcs->regs2);
if (pcs->pci_isp.isp_param) {
free(pcs->pci_isp.isp_param, M_DEVBUF);
pcs->pci_isp.isp_param = NULL;
@@ -1025,6 +1035,8 @@ isp_pci_detach(device_t dev)
pci_release_msi(dev);
}
(void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs);
+ if (pcs->regs2)
+ (void) bus_release_resource(dev, pcs->rtp2, pcs->rgd2, pcs->regs2);
/*
* XXX: THERE IS A LOT OF LEAKAGE HERE
*/
@@ -1043,15 +1055,12 @@ isp_pci_detach(device_t dev)
(((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \
_BLK_REG_SHFT] + ((x) & 0xfff))
-#define BXR2(isp, off) \
- bus_space_read_2(isp->isp_bus_tag, isp->isp_bus_handle, off)
-#define BXW2(isp, off, v) \
- bus_space_write_2(isp->isp_bus_tag, isp->isp_bus_handle, off, v)
-#define BXR4(isp, off) \
- bus_space_read_4(isp->isp_bus_tag, isp->isp_bus_handle, off)
-#define BXW4(isp, off, v) \
- bus_space_write_4(isp->isp_bus_tag, isp->isp_bus_handle, off, v)
-
+#define BXR2(isp, off) bus_read_2((isp)->isp_regs, (off))
+#define BXW2(isp, off, v) bus_write_2((isp)->isp_regs, (off), (v))
+#define BXR4(isp, off) bus_read_4((isp)->isp_regs, (off))
+#define BXW4(isp, off, v) bus_write_4((isp)->isp_regs, (off), (v))
+#define B2R4(isp, off) bus_read_4((isp)->isp_regs2, (off))
+#define B2W4(isp, off, v) bus_write_4((isp)->isp_regs2, (off), (v))
static ISP_INLINE int
isp_pci_rd_debounced(ispsoftc_t *isp, int off, uint16_t *rp)
@@ -1314,20 +1323,19 @@ isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff)
case MBOX_BLOCK:
return (BXR2(isp, IspVirt2Off(isp, regoff)));
case SXP_BLOCK:
- isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK read at 0x%x", regoff);
+ isp_prt(isp, ISP_LOGERR, "SXP_BLOCK read at 0x%x", regoff);
return (0xffffffff);
case RISC_BLOCK:
- isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK read at 0x%x", regoff);
+ isp_prt(isp, ISP_LOGERR, "RISC_BLOCK read at 0x%x", regoff);
return (0xffffffff);
case DMA_BLOCK:
- isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK read at 0x%x", regoff);
+ isp_prt(isp, ISP_LOGERR, "DMA_BLOCK read at 0x%x", regoff);
return (0xffffffff);
default:
- isp_prt(isp, ISP_LOGWARN, "unknown block read at 0x%x", regoff);
+ isp_prt(isp, ISP_LOGERR, "unknown block read at 0x%x", regoff);
return (0xffffffff);
}
-
switch (regoff) {
case BIU2400_FLASH_ADDR:
case BIU2400_FLASH_DATA:
@@ -1355,8 +1363,8 @@ isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff)
rv = BXR4(isp, IspVirt2Off(isp, regoff)) >> 16;
break;
default:
- isp_prt(isp, ISP_LOGERR,
- "isp_pci_rd_reg_2400: unknown offset %x", regoff);
+ isp_prt(isp, ISP_LOGERR, "unknown register read at 0x%x",
+ regoff);
rv = 0xffffffff;
break;
}
@@ -1376,17 +1384,16 @@ isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val)
MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1);
return;
case SXP_BLOCK:
- isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff);
+ isp_prt(isp, ISP_LOGERR, "SXP_BLOCK write at 0x%x", regoff);
return;
case RISC_BLOCK:
- isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK write at 0x%x", regoff);
+ isp_prt(isp, ISP_LOGERR, "RISC_BLOCK write at 0x%x", regoff);
return;
case DMA_BLOCK:
- isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK write at 0x%x", regoff);
+ isp_prt(isp, ISP_LOGERR, "DMA_BLOCK write at 0x%x", regoff);
return;
default:
- isp_prt(isp, ISP_LOGWARN, "unknown block write at 0x%x",
- regoff);
+ isp_prt(isp, ISP_LOGERR, "unknown block write at 0x%x", regoff);
break;
}
@@ -1421,10 +1428,83 @@ isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val)
MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 4, -1);
break;
default:
- isp_prt(isp, ISP_LOGERR,
- "isp_pci_wr_reg_2400: bad offset 0x%x", regoff);
+ isp_prt(isp, ISP_LOGERR, "unknown register write at 0x%x",
+ regoff);
+ break;
+ }
+}
+
+static uint32_t
+isp_pci_rd_reg_2600(ispsoftc_t *isp, int regoff)
+{
+ uint32_t rv;
+
+ switch (regoff) {
+ case BIU2400_PRI_REQINP:
+ case BIU2400_PRI_REQOUTP:
+ isp_prt(isp, ISP_LOGERR, "unknown register read at 0x%x",
+ regoff);
+ rv = 0xffffffff;
+ break;
+ case BIU2400_REQINP:
+ rv = B2R4(isp, 0x00);
+ break;
+ case BIU2400_REQOUTP:
+ rv = B2R4(isp, 0x04);
+ break;
+ case BIU2400_RSPINP:
+ rv = B2R4(isp, 0x08);
+ break;
+ case BIU2400_RSPOUTP:
+ rv = B2R4(isp, 0x0c);
+ break;
+ case BIU2400_ATIO_RSPINP:
+ rv = B2R4(isp, 0x10);
+ break;
+ case BIU2400_ATIO_RSPOUTP:
+ rv = B2R4(isp, 0x14);
+ break;
+ default:
+ rv = isp_pci_rd_reg_2400(isp, regoff);
break;
}
+ return (rv);
+}
+
+static void
+isp_pci_wr_reg_2600(ispsoftc_t *isp, int regoff, uint32_t val)
+{
+ int off;
+
+ switch (regoff) {
+ case BIU2400_PRI_REQINP:
+ case BIU2400_PRI_REQOUTP:
+ isp_prt(isp, ISP_LOGERR, "unknown register write at 0x%x",
+ regoff);
+ return;
+ case BIU2400_REQINP:
+ off = 0x00;
+ break;
+ case BIU2400_REQOUTP:
+ off = 0x04;
+ break;
+ case BIU2400_RSPINP:
+ off = 0x08;
+ break;
+ case BIU2400_RSPOUTP:
+ off = 0x0c;
+ break;
+ case BIU2400_ATIO_RSPINP:
+ off = 0x10;
+ break;
+ case BIU2400_ATIO_RSPOUTP:
+ off = 0x14;
+ break;
+ default:
+ isp_pci_wr_reg_2400(isp, regoff, val);
+ return;
+ }
+ B2W4(isp, off, val);
}
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