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| author | zbb <zbb@FreeBSD.org> | 2013-10-26 17:24:59 +0000 |
|---|---|---|
| committer | zbb <zbb@FreeBSD.org> | 2013-10-26 17:24:59 +0000 |
| commit | deff81bf13b8b71c59b0eb9b071934076eda943a (patch) | |
| tree | e21f9c1146ded17d474e9101b58669a0b9b2f363 /sys/dev/ic | |
| parent | fe8404b3a14f2c0bbddb666f9c09882e26bd63b1 (diff) | |
| download | FreeBSD-src-deff81bf13b8b71c59b0eb9b071934076eda943a.zip FreeBSD-src-deff81bf13b8b71c59b0eb9b071934076eda943a.tar.gz | |
Wait for DesignWare UART transfers completion before accessing line control
When using DW UART with BUSY detection it is necessary to wait
until all serial transfers are finished before manipulating the
line control. LCR will not be affected when UART is busy.
In addition, if Divisor Latch Access Bit is being set in order to
modify UART divisors:
1. We will get BUSY interrupt if interrupts are enabled.
2. Because LCR will not be affected the THR and (even worse) IER
contents will be corrupted. This will lead to console hang.
Approved by: cognet (mentor)
Diffstat (limited to 'sys/dev/ic')
| -rw-r--r-- | sys/dev/ic/ns16550.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/sys/dev/ic/ns16550.h b/sys/dev/ic/ns16550.h index 659f591..33a7dd1 100644 --- a/sys/dev/ic/ns16550.h +++ b/sys/dev/ic/ns16550.h @@ -185,6 +185,7 @@ #define DW_REG_USR 31 /* DesignWare derived Uart Status Reg */ #define com_usr 39 /* Octeon 16750/16550 Uart Status Reg */ #define REG_USR com_usr +#define USR_BUSY 1 /* Uart Busy. Serial transfer in progress */ #define USR_TXFIFO_NOTFULL 2 /* Uart TX FIFO Not full */ /* 16950 register #1. Access enabled by ACR[7]. Also requires !LCR[7]. */ |
