summaryrefslogtreecommitdiffstats
path: root/sys/dev/hwpmc/hwpmc_intel.c
diff options
context:
space:
mode:
authordavide <davide@FreeBSD.org>2012-03-01 21:23:26 +0000
committerdavide <davide@FreeBSD.org>2012-03-01 21:23:26 +0000
commit8636a37ecc8954ff110e51a59a192141bc3b40d3 (patch)
treedcd5eadb41bfdbb68e22fb766ff59d8b0fa25276 /sys/dev/hwpmc/hwpmc_intel.c
parentdaffabc4a9ca22a1776123d0189d7c25a9014a64 (diff)
downloadFreeBSD-src-8636a37ecc8954ff110e51a59a192141bc3b40d3.zip
FreeBSD-src-8636a37ecc8954ff110e51a59a192141bc3b40d3.tar.gz
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events)
- New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
Diffstat (limited to 'sys/dev/hwpmc/hwpmc_intel.c')
-rw-r--r--sys/dev/hwpmc/hwpmc_intel.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/sys/dev/hwpmc/hwpmc_intel.c b/sys/dev/hwpmc/hwpmc_intel.c
index 82d5079..20f29dc 100644
--- a/sys/dev/hwpmc/hwpmc_intel.c
+++ b/sys/dev/hwpmc/hwpmc_intel.c
@@ -142,6 +142,11 @@ pmc_intel_initialize(void)
cputype = PMC_CPU_INTEL_WESTMERE;
nclasses = 5;
break;
+ case 0x2A: /* Per Intel document 253669-039US 05/2011. */
+ case 0x2D: /* Per Intel document 253669-041US 12/2011. */
+ cputype = PMC_CPU_INTEL_SANDYBRIDGE;
+ nclasses = 5;
+ break;
}
break;
#if defined(__i386__) || defined(__amd64__)
@@ -182,6 +187,7 @@ pmc_intel_initialize(void)
case PMC_CPU_INTEL_CORE2:
case PMC_CPU_INTEL_CORE2EXTREME:
case PMC_CPU_INTEL_COREI7:
+ case PMC_CPU_INTEL_SANDYBRIDGE:
case PMC_CPU_INTEL_WESTMERE:
error = pmc_core_initialize(pmc_mdep, ncpus);
break;
@@ -242,6 +248,7 @@ pmc_intel_initialize(void)
* Intel Corei7 and Westmere processors.
*/
case PMC_CPU_INTEL_COREI7:
+ case PMC_CPU_INTEL_SANDYBRIDGE:
case PMC_CPU_INTEL_WESTMERE:
error = pmc_uncore_initialize(pmc_mdep, ncpus);
break;
@@ -271,6 +278,7 @@ pmc_intel_finalize(struct pmc_mdep *md)
case PMC_CPU_INTEL_CORE2:
case PMC_CPU_INTEL_CORE2EXTREME:
case PMC_CPU_INTEL_COREI7:
+ case PMC_CPU_INTEL_SANDYBRIDGE:
case PMC_CPU_INTEL_WESTMERE:
pmc_core_finalize(md);
break;
@@ -301,6 +309,7 @@ pmc_intel_finalize(struct pmc_mdep *md)
#if defined(__i386__) || defined(__amd64__)
switch (md->pmd_cputype) {
case PMC_CPU_INTEL_COREI7:
+ case PMC_CPU_INTEL_SANDYBRIDGE:
case PMC_CPU_INTEL_WESTMERE:
pmc_uncore_finalize(md);
break;
OpenPOWER on IntegriCloud