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authoreadler <eadler@FreeBSD.org>2014-02-04 03:36:42 +0000
committereadler <eadler@FreeBSD.org>2014-02-04 03:36:42 +0000
commitec294fd7f5fc5de11ed889d6c2d701f918d1ecfb (patch)
tree7e76e370b9406b0383b17bd343084addb4ad6a25 /sys/dev/drm
parentd374d7f398b846dc59d8a5ec3c7bfb318cf880af (diff)
downloadFreeBSD-src-ec294fd7f5fc5de11ed889d6c2d701f918d1ecfb.zip
FreeBSD-src-ec294fd7f5fc5de11ed889d6c2d701f918d1ecfb.tar.gz
MFC r258779,r258780,r258787,r258822:
Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this shifts into the sign bit. Instead use (1U << 31) which gets the expected result. Similar to the (1 << 31) case it is not defined to do (2 << 30). This fix is not ideal as it assumes a 32 bit int, but does fix the issue for most cases. A similar change was made in OpenBSD.
Diffstat (limited to 'sys/dev/drm')
-rw-r--r--sys/dev/drm/i915_reg.h30
-rw-r--r--sys/dev/drm/mach64_drv.h6
-rw-r--r--sys/dev/drm/mga_drv.h4
-rw-r--r--sys/dev/drm/r128_drv.h10
-rw-r--r--sys/dev/drm/r300_reg.h6
-rw-r--r--sys/dev/drm/r600_blit.c4
-rw-r--r--sys/dev/drm/radeon_cp.c2
-rw-r--r--sys/dev/drm/radeon_drv.h34
-rw-r--r--sys/dev/drm/via_irq.c2
9 files changed, 49 insertions, 49 deletions
diff --git a/sys/dev/drm/i915_reg.h b/sys/dev/drm/i915_reg.h
index fce9992..0e2ff21 100644
--- a/sys/dev/drm/i915_reg.h
+++ b/sys/dev/drm/i915_reg.h
@@ -349,7 +349,7 @@ __FBSDID("$FreeBSD$");
#define VGA1_PD_P1_MASK (0x1f << 8)
#define DPLL_A 0x06014
#define DPLL_B 0x06018
-#define DPLL_VCO_ENABLE (1 << 31)
+#define DPLL_VCO_ENABLE (1U << 31)
#define DPLL_DVO_HIGH_SPEED (1 << 30)
#define DPLL_SYNCLOCK_ENABLE (1 << 29)
#define DPLL_VGA_MODE_DIS (1 << 28)
@@ -653,7 +653,7 @@ __FBSDID("$FreeBSD$");
/* SDVO port control */
#define SDVOB 0x61140
#define SDVOC 0x61160
-#define SDVO_ENABLE (1 << 31)
+#define SDVO_ENABLE (1U << 31)
#define SDVO_PIPE_B_SELECT (1 << 30)
#define SDVO_STALL_SELECT (1 << 29)
#define SDVO_INTERRUPT_ENABLE (1 << 26)
@@ -690,7 +690,7 @@ __FBSDID("$FreeBSD$");
#define DVOA 0x61120
#define DVOB 0x61140
#define DVOC 0x61160
-#define DVO_ENABLE (1 << 31)
+#define DVO_ENABLE (1U << 31)
#define DVO_PIPE_B_SELECT (1 << 30)
#define DVO_PIPE_STALL_UNUSED (0 << 28)
#define DVO_PIPE_STALL (1 << 28)
@@ -726,7 +726,7 @@ __FBSDID("$FreeBSD$");
* Enables the LVDS port. This bit must be set before DPLLs are enabled, as
* the DPLL semantics change when the LVDS is assigned to that pipe.
*/
-#define LVDS_PORT_EN (1 << 31)
+#define LVDS_PORT_EN (1U << 31)
/* Selects pipe B for LVDS data. Must be set on pre-965. */
#define LVDS_PIPEB_SELECT (1 << 30)
/*
@@ -762,7 +762,7 @@ __FBSDID("$FreeBSD$");
/* Panel power sequencing */
#define PP_STATUS 0x61200
-#define PP_ON (1 << 31)
+#define PP_ON (1U << 31)
/*
* Indicates that all dependencies of the panel are on:
*
@@ -783,7 +783,7 @@ __FBSDID("$FreeBSD$");
/* Panel fitting */
#define PFIT_CONTROL 0x61230
-#define PFIT_ENABLE (1 << 31)
+#define PFIT_ENABLE (1U << 31)
#define PFIT_PIPE_MASK (3 << 29)
#define PFIT_PIPE_SHIFT 29
#define VERT_INTERP_DISABLE (0 << 10)
@@ -826,7 +826,7 @@ __FBSDID("$FreeBSD$");
/* TV port control */
#define TV_CTL 0x68000
/** Enables the TV encoder */
-# define TV_ENC_ENABLE (1 << 31)
+# define TV_ENC_ENABLE (1U << 31)
/** Sources the TV encoder input from pipe B instead of A. */
# define TV_ENC_PIPEB_SELECT (1 << 30)
/** Outputs composite video (DAC A only) */
@@ -897,7 +897,7 @@ __FBSDID("$FreeBSD$");
*
* This gets cleared when TV_DAC_STATE_EN is cleared
*/
-# define TVDAC_STATE_CHG (1 << 31)
+# define TVDAC_STATE_CHG (1U << 31)
# define TVDAC_SENSE_MASK (7 << 28)
/** Reports that DAC A voltage is above the detect threshold */
# define TVDAC_A_SENSE (1 << 30)
@@ -1024,7 +1024,7 @@ __FBSDID("$FreeBSD$");
#define TV_H_CTL_2 0x68034
/** Enables the colorburst (needed for non-component color) */
-# define TV_BURST_ENA (1 << 31)
+# define TV_BURST_ENA (1U << 31)
/** Offset of the colorburst from the start of hsync, in pixels minus one. */
# define TV_HBURST_START_SHIFT 16
# define TV_HBURST_START_MASK 0x1fff0000
@@ -1069,7 +1069,7 @@ __FBSDID("$FreeBSD$");
#define TV_V_CTL_3 0x68044
/** Enables generation of the equalization signal */
-# define TV_EQUAL_ENA (1 << 31)
+# define TV_EQUAL_ENA (1U << 31)
/** Length of vsync, in half lines */
# define TV_VEQ_LEN_MASK 0x007f0000
# define TV_VEQ_LEN_SHIFT 16
@@ -1143,7 +1143,7 @@ __FBSDID("$FreeBSD$");
#define TV_SC_CTL_1 0x68060
/** Turns on the first subcarrier phase generation DDA */
-# define TV_SC_DDA1_EN (1 << 31)
+# define TV_SC_DDA1_EN (1U << 31)
/** Turns on the first subcarrier phase generation DDA */
# define TV_SC_DDA2_EN (1 << 30)
/** Turns on the first subcarrier phase generation DDA */
@@ -1206,7 +1206,7 @@ __FBSDID("$FreeBSD$");
* If set, the rest of the registers are ignored, and the calculated values can
* be read back from the register.
*/
-# define TV_AUTO_SCALE (1 << 31)
+# define TV_AUTO_SCALE (1U << 31)
/**
* Disables the vertical filter.
*
@@ -1269,7 +1269,7 @@ __FBSDID("$FreeBSD$");
# define TV_VSCALE_IP_FRAC_SHIFT 0
#define TV_CC_CONTROL 0x68090
-# define TV_CC_ENABLE (1 << 31)
+# define TV_CC_ENABLE (1U << 31)
/**
* Specifies which field to send the CC data in.
*
@@ -1285,7 +1285,7 @@ __FBSDID("$FreeBSD$");
# define TV_CC_LINE_SHIFT 0
#define TV_CC_DATA 0x68094
-# define TV_CC_RDY (1 << 31)
+# define TV_CC_RDY (1U << 31)
/** Second word of CC data to be transmitted. */
# define TV_CC_DATA_2_MASK 0x007f0000
# define TV_CC_DATA_2_SHIFT 16
@@ -1469,7 +1469,7 @@ __FBSDID("$FreeBSD$");
/* VBIOS regs */
#define VGACNTRL 0x71400
-# define VGA_DISP_DISABLE (1 << 31)
+# define VGA_DISP_DISABLE (1U << 31)
# define VGA_2X_MODE (1 << 30)
# define VGA_PIPE_B_SELECT (1 << 29)
diff --git a/sys/dev/drm/mach64_drv.h b/sys/dev/drm/mach64_drv.h
index 7d68c46..14c590e 100644
--- a/sys/dev/drm/mach64_drv.h
+++ b/sys/dev/drm/mach64_drv.h
@@ -202,7 +202,7 @@ extern void mach64_driver_irq_uninstall(struct drm_device *dev);
# define MACH64_CIRCULAR_BUF_SIZE_32KB (1 << 0)
# define MACH64_CIRCULAR_BUF_SIZE_64KB (2 << 0)
# define MACH64_CIRCULAR_BUF_SIZE_128KB (3 << 0)
-# define MACH64_LAST_DESCRIPTOR (1 << 31)
+# define MACH64_LAST_DESCRIPTOR (1U << 31)
#define MACH64_BM_HOSTDATA 0x0644
#define MACH64_BM_STATUS 0x018c
#define MACH64_BM_SYSTEM_MEM_ADDR 0x0184
@@ -316,7 +316,7 @@ extern void mach64_driver_irq_uninstall(struct drm_device *dev);
#define MACH64_FIFO_STAT 0x0710
# define MACH64_FIFO_SLOT_MASK 0x0000ffff
-# define MACH64_FIFO_ERR (1 << 31)
+# define MACH64_FIFO_ERR (1U << 31)
#define MACH64_GEN_TEST_CNTL 0x04d0
# define MACH64_GUI_ENGINE_ENABLE (1 << 8)
@@ -442,7 +442,7 @@ extern void mach64_driver_irq_uninstall(struct drm_device *dev);
# define MACH64_CRTC2_VLINE_SYNC (1 << 28) /* LT Pro */ /* 0=even, 1=odd */
# define MACH64_CRTC_SNAPSHOT2_INT_EN (1 << 29) /* LT Pro */
# define MACH64_CRTC_SNAPSHOT2_INT (1 << 30) /* LT Pro */
-# define MACH64_CRTC_VBLANK2_INT (1 << 31)
+# define MACH64_CRTC_VBLANK2_INT (1U << 31)
# define MACH64_CRTC_INT_ENS \
( \
MACH64_CRTC_VBLANK_INT_EN | \
diff --git a/sys/dev/drm/mga_drv.h b/sys/dev/drm/mga_drv.h
index 01c5c9d..52a7baf 100644
--- a/sys/dev/drm/mga_drv.h
+++ b/sys/dev/drm/mga_drv.h
@@ -458,7 +458,7 @@ do { \
# define MGA_BLTMOD_BU24RGB (15 << 25)
# define MGA_PATTERN (1 << 29)
# define MGA_TRANSC (1 << 30)
-# define MGA_CLIPDIS (1 << 31)
+# define MGA_CLIPDIS (1U << 31)
#define MGA_DWGSYNC 0x2c4c
#define MGA_FCOL 0x1c24
@@ -526,7 +526,7 @@ do { \
#define MGA_TEXCTL2 0x2c3c
# define MGA_DUALTEX (1 << 7)
# define MGA_G400_TC2_MAGIC (1 << 15)
-# define MGA_MAP1_ENABLE (1 << 31)
+# define MGA_MAP1_ENABLE (1U << 31)
#define MGA_TEXFILTER 0x2c58
#define MGA_TEXHEIGHT 0x2c2c
#define MGA_TEXORG 0x2c24
diff --git a/sys/dev/drm/r128_drv.h b/sys/dev/drm/r128_drv.h
index ee7d8f9..7ad3496 100644
--- a/sys/dev/drm/r128_drv.h
+++ b/sys/dev/drm/r128_drv.h
@@ -227,7 +227,7 @@ extern long r128_compat_ioctl(struct file *filp, unsigned int cmd,
# define R128_ROP3_P 0x00f00000
#define R128_DP_WRITE_MASK 0x16cc
#define R128_DST_PITCH_OFFSET_C 0x1c80
-# define R128_DST_TILE (1 << 31)
+# define R128_DST_TILE (1U << 31)
#define R128_GEN_INT_CNTL 0x0040
# define R128_CRTC_VBLANK_INT_EN (1 << 0)
@@ -246,7 +246,7 @@ extern long r128_compat_ioctl(struct file *filp, unsigned int cmd,
#define R128_GUI_STAT 0x1740
# define R128_GUI_FIFOCNT_MASK 0x0fff
-# define R128_GUI_ACTIVE (1 << 31)
+# define R128_GUI_ACTIVE (1U << 31)
#define R128_MCLK_CNTL 0x000f
# define R128_FORCE_GCP (1 << 16)
@@ -258,7 +258,7 @@ extern long r128_compat_ioctl(struct file *filp, unsigned int cmd,
# define R128_PC_FLUSH_GUI (3 << 0)
# define R128_PC_RI_GUI (1 << 2)
# define R128_PC_FLUSH_ALL 0x00ff
-# define R128_PC_BUSY (1 << 31)
+# define R128_PC_BUSY (1U << 31)
#define R128_PCI_GART_PAGE 0x017c
#define R128_PRIM_TEX_CNTL_C 0x1cb0
@@ -302,7 +302,7 @@ extern long r128_compat_ioctl(struct file *filp, unsigned int cmd,
#define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c
#define R128_PM4_BUFFER_DL_RPTR 0x0710
#define R128_PM4_BUFFER_DL_WPTR 0x0714
-# define R128_PM4_BUFFER_DL_DONE (1 << 31)
+# define R128_PM4_BUFFER_DL_DONE (1U << 31)
#define R128_PM4_VC_FPU_SETUP 0x071c
@@ -312,7 +312,7 @@ extern long r128_compat_ioctl(struct file *filp, unsigned int cmd,
#define R128_PM4_STAT 0x07b8
# define R128_PM4_FIFOCNT_MASK 0x0fff
# define R128_PM4_BUSY (1 << 16)
-# define R128_PM4_GUI_ACTIVE (1 << 31)
+# define R128_PM4_GUI_ACTIVE (1U << 31)
#define R128_PM4_MICROCODE_ADDR 0x07d4
#define R128_PM4_MICROCODE_RADDR 0x07d8
diff --git a/sys/dev/drm/r300_reg.h b/sys/dev/drm/r300_reg.h
index 6df4611..0508771 100644
--- a/sys/dev/drm/r300_reg.h
+++ b/sys/dev/drm/r300_reg.h
@@ -1205,7 +1205,7 @@ __FBSDID("$FreeBSD$");
# define R300_FPI0_OUTC_FRC (9 << 23)
# define R300_FPI0_OUTC_REPL_ALPHA (10 << 23)
# define R300_FPI0_OUTC_SAT (1 << 30)
-# define R300_FPI0_INSERT_NOP (1 << 31)
+# define R300_FPI0_INSERT_NOP (1U << 31)
#define R300_PFS_INSTR2_0 0x49C0
# define R300_FPI2_ARGA_SRC0C_X 0
@@ -1252,7 +1252,7 @@ __FBSDID("$FreeBSD$");
# define R300_FPI2_OUTA_RCP (10 << 23)
# define R300_FPI2_OUTA_RSQ (11 << 23)
# define R300_FPI2_OUTA_SAT (1 << 30)
-# define R300_FPI2_UNKNOWN_31 (1 << 31)
+# define R300_FPI2_UNKNOWN_31 (1U << 31)
/* END: Fragment program instruction set */
/* Fog state and color */
@@ -1452,7 +1452,7 @@ __FBSDID("$FreeBSD$");
# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1)
# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1)
# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31)
-# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31)
+# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1U << 31)
#define R300_ZB_BW_CNTL 0x4f1c
# define R300_HIZ_DISABLE (0 << 0)
diff --git a/sys/dev/drm/r600_blit.c b/sys/dev/drm/r600_blit.c
index d3c41ae..f6097ee 100644
--- a/sys/dev/drm/r600_blit.c
+++ b/sys/dev/drm/r600_blit.c
@@ -1428,12 +1428,12 @@ set_scissors(drm_radeon_private_t *dev_priv, int x1, int y1, int x2, int y2)
OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
OUT_RING((R600_PA_SC_GENERIC_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
- OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));
+ OUT_RING((x1 << 0) | (y1 << 16) | (1U << 31));
OUT_RING((x2 << 0) | (y2 << 16));
OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
OUT_RING((R600_PA_SC_WINDOW_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
- OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));
+ OUT_RING((x1 << 0) | (y1 << 16) | (1U << 31));
OUT_RING((x2 << 0) | (y2 << 16));
ADVANCE_RING();
}
diff --git a/sys/dev/drm/radeon_cp.c b/sys/dev/drm/radeon_cp.c
index 0a486af..5d2f4c7 100644
--- a/sys/dev/drm/radeon_cp.c
+++ b/sys/dev/drm/radeon_cp.c
@@ -542,7 +542,7 @@ static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
#if 0
u32 tmp;
- tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
+ tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1U << 31);
RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
#endif
}
diff --git a/sys/dev/drm/radeon_drv.h b/sys/dev/drm/radeon_drv.h
index d90d7cf..e830a83 100644
--- a/sys/dev/drm/radeon_drv.h
+++ b/sys/dev/drm/radeon_drv.h
@@ -659,7 +659,7 @@ extern int r600_cs_init(struct drm_device *dev);
# define RS480_GTW_LAC_EN (1 << 25)
# define RS480_2LEVEL_GART (0 << 30)
# define RS480_1LEVEL_GART (1 << 30)
-# define RS480_PDC_EN (1 << 31)
+# define RS480_PDC_EN (1U << 31)
#define RS480_GART_BASE 0x2c
#define RS480_GART_CACHE_CNTRL 0x2e
# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
@@ -775,7 +775,7 @@ extern int r600_cs_init(struct drm_device *dev);
# define R300_SUBPIXEL_1_12 (0 << 16)
# define R300_SUBPIXEL_1_16 (1 << 16)
#define R300_DST_PIPE_CONFIG 0x170c
-# define R300_PIPE_AUTO_CONFIG (1 << 31)
+# define R300_PIPE_AUTO_CONFIG (1U << 31)
#define R300_RB2D_DSTCACHE_MODE 0x3428
# define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
@@ -807,8 +807,8 @@ extern int r600_cs_init(struct drm_device *dev);
#define RADEON_DST_PITCH_OFFSET_C 0x1c80
# define RADEON_DST_TILE_LINEAR (0 << 30)
# define RADEON_DST_TILE_MACRO (1 << 30)
-# define RADEON_DST_TILE_MICRO (2 << 30)
-# define RADEON_DST_TILE_BOTH (3 << 30)
+# define RADEON_DST_TILE_MICRO (2U << 30)
+# define RADEON_DST_TILE_BOTH (3U << 30)
#define RADEON_SCRATCH_REG0 0x15e0
#define RADEON_SCRATCH_REG1 0x15e4
@@ -902,7 +902,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define R300_RB2D_DC_FLUSH (3 << 0)
# define R300_RB2D_DC_FREE (3 << 2)
# define R300_RB2D_DC_FLUSH_ALL 0xf
-# define R300_RB2D_DC_BUSY (1 << 31)
+# define R300_RB2D_DC_BUSY (1U << 31)
#define RADEON_RB3D_CNTL 0x1c3c
# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
# define RADEON_PLANE_MASK_ENABLE (1 << 1)
@@ -924,16 +924,16 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define RADEON_RB3D_ZC_FLUSH (1 << 0)
# define RADEON_RB3D_ZC_FREE (1 << 2)
# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
-# define RADEON_RB3D_ZC_BUSY (1 << 31)
+# define RADEON_RB3D_ZC_BUSY (1U << 31)
#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
# define R300_ZC_FLUSH (1 << 0)
# define R300_ZC_FREE (1 << 1)
-# define R300_ZC_BUSY (1 << 31)
+# define R300_ZC_BUSY (1U << 31)
#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
# define RADEON_RB3D_DC_FLUSH (3 << 0)
# define RADEON_RB3D_DC_FREE (3 << 2)
# define RADEON_RB3D_DC_FLUSH_ALL 0xf
-# define RADEON_RB3D_DC_BUSY (1 << 31)
+# define RADEON_RB3D_DC_BUSY (1U << 31)
#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
# define R300_RB3D_DC_FLUSH (2 << 0)
# define R300_RB3D_DC_FREE (2 << 2)
@@ -949,7 +949,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
# define RADEON_FORCE_Z_DIRTY (1 << 29)
# define RADEON_Z_WRITE_ENABLE (1 << 30)
-# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
+# define RADEON_Z_DECOMPRESSION_ENABLE (1U << 31)
#define RADEON_RBBM_SOFT_RESET 0x00f0
# define RADEON_SOFT_RESET_CP (1 << 0)
# define RADEON_SOFT_RESET_HI (1 << 1)
@@ -1003,7 +1003,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
# define RADEON_GA_BUSY (1 << 26)
# define RADEON_CBA2D_BUSY (1 << 27)
-# define RADEON_RBBM_ACTIVE (1 << 31)
+# define RADEON_RBBM_ACTIVE (1U << 31)
#define RADEON_RE_LINE_PATTERN 0x1cd0
#define RADEON_RE_MISC 0x26c4
#define RADEON_RE_TOP_LEFT 0x26c0
@@ -1117,7 +1117,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
#define RADEON_CP_RB_CNTL 0x0704
# define RADEON_BUF_SWAP_32BIT (2 << 16)
# define RADEON_RB_NO_UPDATE (1 << 27)
-# define RADEON_RB_RPTR_WR_ENA (1 << 31)
+# define RADEON_RB_RPTR_WR_ENA (1U << 31)
#define RADEON_CP_RB_RPTR_ADDR 0x070c
#define RADEON_CP_RB_RPTR 0x0710
#define RADEON_CP_RB_WPTR 0x0714
@@ -1193,7 +1193,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
-#define RADEON_VTX_Z_PRESENT (1 << 31)
+#define RADEON_VTX_Z_PRESENT (1U << 31)
#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
#define RADEON_PRIM_TYPE_NONE (0 << 0)
@@ -1524,7 +1524,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
#define R600_GRBM_STATUS 0x8010
# define R600_CMDFIFO_AVAIL_MASK 0x1f
# define R700_CMDFIFO_AVAIL_MASK 0xf
-# define R600_GUI_ACTIVE (1 << 31)
+# define R600_GUI_ACTIVE (1U << 31)
#define R600_GRBM_STATUS2 0x8014
#define R600_GRBM_SOFT_RESET 0x8020
# define R600_SOFT_RESET_CP (1 << 0)
@@ -1546,7 +1546,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define R600_RB_BUFSZ(x) ((x) << 0)
# define R600_RB_BLKSZ(x) ((x) << 8)
# define R600_RB_NO_UPDATE (1 << 27)
-# define R600_RB_RPTR_WR_ENA (1 << 31)
+# define R600_RB_RPTR_WR_ENA (1U << 31)
#define R600_CP_RB_RPTR_WR 0xc108
#define R600_CP_RB_RPTR_ADDR 0xc10c
#define R600_CP_RB_RPTR_ADDR_HI 0xc110
@@ -1619,7 +1619,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
#define R600_SX_MISC 0x28350
#define R600_DB_DEBUG 0x9830
-# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)
+# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1U << 31)
#define R600_DB_WATERMARKS 0x9838
# define R600_DEPTH_FREE(x) ((x) << 0)
# define R600_DEPTH_FLUSH(x) ((x) << 5)
@@ -1679,7 +1679,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define R600_SYNC_WALKER (1 << 25)
# define R600_SYNC_ALIGNER (1 << 26)
# define R600_BILINEAR_PRECISION_6_BIT (0 << 31)
-# define R600_BILINEAR_PRECISION_8_BIT (1 << 31)
+# define R600_BILINEAR_PRECISION_8_BIT (1U << 31)
#define R700_TCP_CNTL 0x9610
@@ -1753,7 +1753,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
# define R600_PERSP_GRADIENT_ENA (1 << 28)
# define R600_LINEAR_GRADIENT_ENA (1 << 29)
# define R600_POSITION_SAMPLE (1 << 30)
-# define R600_BARYC_AT_SAMPLE_ENA (1 << 31)
+# define R600_BARYC_AT_SAMPLE_ENA (1U << 31)
#define R600_SPI_PS_IN_CONTROL_1 0x286d0
# define R600_GEN_INDEX_PIX (1 << 0)
# define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1)
diff --git a/sys/dev/drm/via_irq.c b/sys/dev/drm/via_irq.c
index 20ec77a..0ebda40 100644
--- a/sys/dev/drm/via_irq.c
+++ b/sys/dev/drm/via_irq.c
@@ -46,7 +46,7 @@ __FBSDID("$FreeBSD$");
#define VIA_REG_INTERRUPT 0x200
/* VIA_REG_INTERRUPT */
-#define VIA_IRQ_GLOBAL (1 << 31)
+#define VIA_IRQ_GLOBAL (1U << 31)
#define VIA_IRQ_VBLANK_ENABLE (1 << 19)
#define VIA_IRQ_VBLANK_PENDING (1 << 3)
#define VIA_IRQ_HQV0_ENABLE (1 << 11)
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