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| author | yongari <yongari@FreeBSD.org> | 2011-08-22 20:33:05 +0000 |
|---|---|---|
| committer | yongari <yongari@FreeBSD.org> | 2011-08-22 20:33:05 +0000 |
| commit | 90836b4689c5f41c0cecc54709de8602864ee605 (patch) | |
| tree | 1f49ecc44eaccb815a507f8dde9b18a40bb9ee67 /sys/dev/alc | |
| parent | 9d10e169c997a3477c1b9e10cbc342c39734acf2 (diff) | |
| download | FreeBSD-src-90836b4689c5f41c0cecc54709de8602864ee605.zip FreeBSD-src-90836b4689c5f41c0cecc54709de8602864ee605.tar.gz | |
Disable PHY hibernation until I get more detailed hibernation
programming secret. The PHY would go into sleep state when it
detects no established link and it will re-establish link when the
cable is plugged in. Previously it failed to re-establish link
when the cable is plugged in such that it required to manually down
and up the interface again to make it work. This came from
incorrectly programmed hibernation parameters. According to
Atheros, each PHY chip requires different configuration for
hibernation and different vendor has different settings for the
same chip.
Disabling hibernation may consume more power but establishing link
looks more important than saving power.
Special thanks to Atheros for giving me instructions that disable
hibernation.
MFC after: 1 week
Approved by: re (kib)
Diffstat (limited to 'sys/dev/alc')
| -rw-r--r-- | sys/dev/alc/if_alc.c | 26 |
1 files changed, 20 insertions, 6 deletions
diff --git a/sys/dev/alc/if_alc.c b/sys/dev/alc/if_alc.c index ff0424e..c13cb18 100644 --- a/sys/dev/alc/if_alc.c +++ b/sys/dev/alc/if_alc.c @@ -532,13 +532,11 @@ alc_phy_reset(struct alc_softc *sc) uint16_t data; /* Reset magic from Linux. */ - CSR_WRITE_2(sc, ALC_GPHY_CFG, - GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET); + CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); CSR_READ_2(sc, ALC_GPHY_CFG); DELAY(10 * 1000); - CSR_WRITE_2(sc, ALC_GPHY_CFG, - GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | + CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | GPHY_CFG_SEL_ANA_RESET); CSR_READ_2(sc, ALC_GPHY_CFG); DELAY(10 * 1000); @@ -623,6 +621,23 @@ alc_phy_reset(struct alc_softc *sc) alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, data); DELAY(1000); + + /* Disable hibernation. */ + alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, + 0x0029); + data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, + ALC_MII_DBG_DATA); + data &= ~0x8000; + alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, + data); + + alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, + 0x000B); + data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, + ALC_MII_DBG_DATA); + data &= ~0x8000; + alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, + data); } static void @@ -648,8 +663,7 @@ alc_phy_down(struct alc_softc *sc) break; default: /* Force PHY down. */ - CSR_WRITE_2(sc, ALC_GPHY_CFG, - GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | + CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW); DELAY(1000); |
