Update copyrights to Y2K.

93cx6.c:
	Make the SRAM dump output a little prettier.

aic7xxx.c:
	Store all SG entries into our SG array in kernel space.
	This makes data-overrun and other error reporting more
	useful as we can dump all SG entries.  In the past,
	we only stored the SG entries that the sequencer might
	need to access, which meant we skipped the first element
	that is embedded into the SCB.

	Add a table of chip strings and replace ugly switch
	statements with table lookups.

	Add a table with bus phase strings and message reponses
	to parity errors in those phases.  Use the table to
	pretty print bus phase messages as well as collapse
	another switch statement.

	Fix a bug in target mode that could cause us to unpause
	the sequencer early in bus reset processing.

	Add the 80MHz/DT mode into our syncrate table.  This
	rate is not yet used or enabled.

	Correct some comments, clean up some code...

aic7xxx.h:
	Add U160 controller feature information.

	Add some more bit fields for various SEEPROM formats.

aic7xxx.reg:
	Add U160 register and register bit definitions.

aic7xxx.seq:
	Make phasemis state tracking more straight forward.  This
	avoids the consumption of SINDEX which is a very useful register.

	For the U160 chips, you must use the 'mov' instruction to
	update DFCNTRL.  Using 'or' to set the PRELOADED bit is
	completely ineffective.

	At the end of the command phase, wair for our ACK signal
	to de-assert before disabling the SCSI dma engine.  For
	slow devices, this avoids clearing the ACK before the
	other end has had a chance to see it and lower REQ.

1 files changed, 60 insertions, 2 deletions

diff --git a/sys/dev/aic7xxx/aic7xxx.reg b/sys/dev/aic7xxx/aic7xxx.reg
index 1deaaac..ccdca37 100644
--- a/sys/dev/aic7xxx/aic7xxx.reg
+++ b/sys/dev/aic7xxx/aic7xxx.reg
@@ -1,7 +1,7 @@
 /*
  * Aic7xxx register and scratch ram definitions.
  *
- * Copyright (c) 1994-1999 Justin Gibbs.
+ * Copyright (c) 1994-2000 Justin Gibbs.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -156,8 +156,10 @@ register SCSIRATE {
 	address			0x004
 	access_mode RW
 	bit	WIDEXFER	0x80		/* Wide transfer control */
+	bit	ENABLE_CRC	0x40		/* CRC for D-Phases */
+	bit	SINGLE_EDGE	0x10		/* Disable DT Transfers */
 	mask	SXFR		0x70		/* Sync transfer rate */
-	mask	SXFR_ULTRA2	0x7f		/* Sync transfer rate */
+	mask	SXFR_ULTRA2	0x0f		/* Sync transfer rate */
 	mask	SOFS		0x0f		/* Sync offset */
 }
 
@@ -209,6 +211,28 @@ register STCNT {
 	access_mode RW
 }
 
+/* ALT_MODE register on Ultra160 chips */
+register OPTIONMODE {
+	address			0x008
+	access_mode RW
+	bit	AUTORATEEN		0x80
+	bit	AUTOACKEN		0x40
+	bit	ATNMGMNTEN		0x20
+	bit	BUSFREEREV		0x10
+	bit	EXPPHASEDIS		0x08
+	bit	SCSIDATL_IMGEN		0x04
+	bit	AUTO_MSGOUT_DE		0x02
+	bit	DIS_MSGIN_DUALEDGE	0x01
+	mask	OPTIONMODE_DEFAULTS	AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE
+}
+
+/* ALT_MODE register on Ultra160 chips */
+register TARGCRCCNT {
+	address			0x00a
+	size	2
+	access_mode RW
+}
+
 /*
  * Clear SCSI Interrupt 0 (p. 3-20)
  * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.
@@ -396,6 +420,16 @@ register SELID {
 	bit	ONEBIT		0x08
 }
 
+register SCAMCTL {
+	address			0x01a
+	access_mode RW
+	bit	ENSCAMSELO	0x80
+	bit	CLRSCAMSELID	0x40
+	bit	ALTSTIM		0x20
+	bit	DFLTTID		0x10
+	mask	SCAMLVL		0x03
+}
+
 /*
  * Target Mode Selecting in ID bitmask (aic7890/91/96/97)
  */
@@ -874,6 +908,18 @@ register QOUTFIFO {
 	access_mode WO
 }
 
+register CRCCONTROL1 {
+	address			0x09d
+	access_mode RW
+	bit	CRCONSEEN		0x80
+	bit	CRCVALCHKEN		0x40
+	bit	CRCENDCHKEN		0x20
+	bit	CRCREQCHKEN		0x10
+	bit	TARGCRCENDEN		0x08
+	bit	TARGCRCCNTEN		0x04
+}
+
+
 /*
  * Queue Out Count (p. 3-61)
  * Number of queued SCBs in the Out FIFO
@@ -883,12 +929,24 @@ register QOUTCNT {
 	access_mode RO
 }
 
+register SCSIPHASE {
+	address			0x09e
+	access_mode RO
+	bit	STATUS_PHASE	0x20
+	bit	COMMAND_PHASE	0x10
+	bit	MSG_IN_PHASE	0x08
+	bit	MSG_OUT_PHASE	0x04
+	bit	DATA_IN_PHASE	0x02
+	bit	DATA_OUT_PHASE	0x01
+}
+
 /*
  * Special Function
  */
 register SFUNCT {
 	address			0x09f
 	access_mode RW
+	bit	ALT_MODE	0x80
 }
 
 /*