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| author | jkim <jkim@FreeBSD.org> | 2011-02-25 18:29:57 +0000 |
|---|---|---|
| committer | jkim <jkim@FreeBSD.org> | 2011-02-25 18:29:57 +0000 |
| commit | ba36884c614b6730b006423c37963a8f6b53ce31 (patch) | |
| tree | 8e21e9dd35add9a82b8dacbdadc0c6aaf62cb180 /sys/dev/acpica/acpivar.h | |
| parent | 41410d4d9bb5cbb4ca673d99864f603842c44804 (diff) | |
| download | FreeBSD-src-ba36884c614b6730b006423c37963a8f6b53ce31.zip FreeBSD-src-ba36884c614b6730b006423c37963a8f6b53ce31.tar.gz | |
Add more definitions for vendor-specific CPU capability bits to the last
revision, which is renamed to "Intel Processor Vendor-Specific ACPI".
Diffstat (limited to 'sys/dev/acpica/acpivar.h')
| -rw-r--r-- | sys/dev/acpica/acpivar.h | 24 |
1 files changed, 13 insertions, 11 deletions
diff --git a/sys/dev/acpica/acpivar.h b/sys/dev/acpica/acpivar.h index 5fbc58f..167baa6 100644 --- a/sys/dev/acpica/acpivar.h +++ b/sys/dev/acpica/acpivar.h @@ -186,18 +186,20 @@ extern struct mtx acpi_mutex; /* * Various features and capabilities for the acpi_get_features() method. * In particular, these are used for the ACPI 3.0 _PDC and _OSC methods. - * See the Intel document titled "Processor Driver Capabilities Bit - * Definitions", number 302223-002. + * See the Intel document titled "Intel Processor Vendor-Specific ACPI", + * number 302223-005. */ -#define ACPI_CAP_PERF_MSRS (1 << 0) /* Intel SpeedStep PERF_CTL MSRs */ -#define ACPI_CAP_C1_IO_HALT (1 << 1) /* Intel C1 "IO then halt" sequence */ -#define ACPI_CAP_THR_MSRS (1 << 2) /* Intel OnDemand throttling MSRs */ -#define ACPI_CAP_SMP_SAME (1 << 3) /* MP C1, Px, and Tx (all the same) */ -#define ACPI_CAP_SMP_SAME_C3 (1 << 4) /* MP C2 and C3 (all the same) */ -#define ACPI_CAP_SMP_DIFF_PX (1 << 5) /* MP Px (different, using _PSD) */ -#define ACPI_CAP_SMP_DIFF_CX (1 << 6) /* MP Cx (different, using _CSD) */ -#define ACPI_CAP_SMP_DIFF_TX (1 << 7) /* MP Tx (different, using _TSD) */ -#define ACPI_CAP_SMP_C1_NATIVE (1 << 8) /* MP C1 support other than halt */ +#define ACPI_CAP_PERF_MSRS (1 << 0) /* Intel SpeedStep PERF_CTL MSRs */ +#define ACPI_CAP_C1_IO_HALT (1 << 1) /* Intel C1 "IO then halt" sequence */ +#define ACPI_CAP_THR_MSRS (1 << 2) /* Intel OnDemand throttling MSRs */ +#define ACPI_CAP_SMP_SAME (1 << 3) /* MP C1, Px, and Tx (all the same) */ +#define ACPI_CAP_SMP_SAME_C3 (1 << 4) /* MP C2 and C3 (all the same) */ +#define ACPI_CAP_SMP_DIFF_PX (1 << 5) /* MP Px (different, using _PSD) */ +#define ACPI_CAP_SMP_DIFF_CX (1 << 6) /* MP Cx (different, using _CSD) */ +#define ACPI_CAP_SMP_DIFF_TX (1 << 7) /* MP Tx (different, using _TSD) */ +#define ACPI_CAP_SMP_C1_NATIVE (1 << 8) /* MP C1 support other than halt */ +#define ACPI_CAP_SMP_C3_NATIVE (1 << 9) /* MP C2 and C3 support */ +#define ACPI_CAP_PX_HW_COORD (1 << 11) /* Intel P-state HW coordination */ /* * Quirk flags. |
