Add initial support for the QCA953x SoC (honeybee) wifi.

This is a 2x2 2GHz 802.11n part.  It works enough at the moment to
bring up, scan and associate.  I haven't started using this as
a day to day AP.

The specifics:

* add honeybee initvals
* add in changes; a mix from the QCA HAL and ath9k;
* fix a bug in AR_SREV_AR9580_10_OR_LATER(), which is only used
  for one capability check and we don't even implement it - so it's
  a big no-op.

Shady things:

* ath9k has the "platform data" define the 25/40MHz clock.
  This HAL .. doesn't.  Honeybee gets hard-coded to 25MHz which
  it likely shouldn't be.  I'll have to go and identify/fix those.

Tested:

* Qualcomm Atheros AP143 reference design board.

Obtained from:	Qualcomm Atheros; Linux ath9k

8 files changed, 260 insertions, 41 deletions

diff --git a/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_attach.c b/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_attach.c
index 647bd0e..f7f3ed7 100644
--- a/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_attach.c
+++ b/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_attach.c
@@ -42,6 +42,7 @@
 #include "ar9300/ar9462_2p1_initvals.h"
 #include "ar9300/ar9580.ini"
 #include "ar9300/ar955x.ini"
+#include "ar9300/ar953x.ini"
 #include "ar9300/ar9300_aphrodite10.ini"
 
 
@@ -566,6 +567,9 @@ ar9300_read_revisions(struct ath_hal *ah)
     } else if(AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_QCA955X) {
         /* XXX: AR_SREV register in Scorpion reads 0 */
        AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_SCORPION;
+    } else if(AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_QCA953X) {
+        /* XXX: AR_SREV register in HoneyBEE reads 0 */
+       AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_HONEYBEE;
     } else {
         /*
          * Include 6-bit Chip Type (masked to 0)
@@ -799,6 +803,11 @@ ar9300_attach(u_int16_t devid, HAL_SOFTC sc, HAL_BUS_TAG st,
 #undef AR9340_SOC_SEL_25M_40M
 #undef AR9340_REF_CLK_40
     }
+
+    if (AR_SREV_HONEYBEE(ah)) {
+            ahp->clk_25mhz = 1;
+    }
+
     ar9300_init_pll(ah, AH_NULL);
 
     if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) {
@@ -823,6 +832,7 @@ ar9300_attach(u_int16_t devid, HAL_SOFTC sc, HAL_BUS_TAG st,
         ahpriv->ah_macVersion != AR_SREV_VERSION_HORNET &&
         ahpriv->ah_macVersion != AR_SREV_VERSION_POSEIDON &&
         ahpriv->ah_macVersion != AR_SREV_VERSION_SCORPION &&
+        ahpriv->ah_macVersion != AR_SREV_VERSION_HONEYBEE &&
         ahpriv->ah_macVersion != AR_SREV_VERSION_JUPITER &&
         ahpriv->ah_macVersion != AR_SREV_VERSION_APHRODITE) ) {
         HALDEBUG(ah, HAL_DEBUG_RESET,
@@ -1376,6 +1386,15 @@ ar9300_attach(u_int16_t devid, HAL_SOFTC sc, HAL_BUS_TAG st,
             ar9340Modes_fast_clock_wasp_1p0,
             ARRAY_LENGTH(ar9340Modes_fast_clock_wasp_1p0), 3);
 
+        /* XXX TODO: need to add this for freebsd; it's missing from the current .ini files */
+#if 0
+        /* Japan 2484Mhz CCK settings */
+        INIT_INI_ARRAY(&ahp->ah_ini_japan2484,
+            ar9340_wasp_1p0_baseband_core_txfir_coeff_japan_2484,
+            ARRAY_LENGTH(
+                ar9340_wasp_1p0_baseband_core_txfir_coeff_japan_2484), 2);
+#endif
+
         /* Additional setttings for 40Mhz */
         INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40mhz, 
             ar9340_wasp_1p0_radio_core_40M,
@@ -1445,6 +1464,67 @@ ar9300_attach(u_int16_t devid, HAL_SOFTC sc, HAL_BUS_TAG st,
         //INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40M,
         //                ar955x_scorpion_1p0_radio_core_40M,
         //                ARRAY_LENGTH(ar955x_scorpion_1p0_radio_core_40M), 2);
+    } else if (AR_SREV_HONEYBEE(ah)) {
+        /* mac */
+        INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0);
+        INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE],
+                        qca953x_honeybee_1p0_mac_core,
+                        ARRAY_LENGTH(qca953x_honeybee_1p0_mac_core), 2);
+        INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST],
+                        qca953x_honeybee_1p0_mac_postamble,
+                        ARRAY_LENGTH(qca953x_honeybee_1p0_mac_postamble), 5);
+
+        /* bb */
+        INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0);
+        INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE],
+                        qca953x_honeybee_1p0_baseband_core,
+                        ARRAY_LENGTH(qca953x_honeybee_1p0_baseband_core), 2);
+        INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST],
+                        qca953x_honeybee_1p0_baseband_postamble,
+                        ARRAY_LENGTH(qca953x_honeybee_1p0_baseband_postamble), 5);
+
+        /* radio */
+        INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0);
+        INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE],
+                        qca953x_honeybee_1p0_radio_core,
+                        ARRAY_LENGTH(qca953x_honeybee_1p0_radio_core), 2);
+        INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST],
+                        qca953x_honeybee_1p0_radio_postamble,
+                        ARRAY_LENGTH(qca953x_honeybee_1p0_radio_postamble), 5);
+
+        /* soc */
+        INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE],
+                        qca953x_honeybee_1p0_soc_preamble,
+                        ARRAY_LENGTH(qca953x_honeybee_1p0_soc_preamble), 2);
+        INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0);
+        INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST],
+                        qca953x_honeybee_1p0_soc_postamble,
+                        ARRAY_LENGTH(qca953x_honeybee_1p0_soc_postamble), 5);
+
+        /* rx/tx gain */
+        INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
+                        qca953xCommon_wo_xlna_rx_gain_table_honeybee_1p0,
+                        ARRAY_LENGTH(qca953xCommon_wo_xlna_rx_gain_table_honeybee_1p0), 2);
+        INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds,
+                        qca953xCommon_wo_xlna_rx_gain_bounds_honeybee_1p0,
+                        ARRAY_LENGTH(qca953xCommon_wo_xlna_rx_gain_bounds_honeybee_1p0), 5);
+        INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
+                        qca953xModes_no_xpa_tx_gain_table_honeybee_1p0,
+                        ARRAY_LENGTH(qca953xModes_no_xpa_tx_gain_table_honeybee_1p0), 2);
+
+        /*ath_hal_pciePowerSaveEnable should be 2 for OWL/Condor and 0 for merlin */
+        ah->ah_config.ath_hal_pcie_power_save_enable = 0;
+
+        /* Fast clock modal settings */
+        INIT_INI_ARRAY(&ahp->ah_ini_modes_additional,
+                        qca953xModes_fast_clock_honeybee_1p0,
+                        ARRAY_LENGTH(qca953xModes_fast_clock_honeybee_1p0), 3);
+
+        /* Additional setttings for 40Mhz */
+        //INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40M,
+        //                qca953x_honeybee_1p0_radio_core_40M,
+        //                ARRAY_LENGTH(qca953x_honeybee_1p0_radio_core_40M), 2);
+
     } else if (AR_SREV_JUPITER_10(ah)) {
         /* Jupiter: new INI format (pre, core, post arrays per subsystem) */
 
@@ -3518,6 +3598,13 @@ void ar9300_rx_gain_table_apply(struct ath_hal *ah)
             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds,
                 ar955xCommon_rx_gain_bounds_scorpion_1p0,
                 ARRAY_LENGTH(ar955xCommon_rx_gain_bounds_scorpion_1p0), 5);
+        } else if (AR_SREV_HONEYBEE(ah)) {
+            INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
+                qca953xCommon_rx_gain_table_honeybee_1p0,
+                ARRAY_LENGTH(qca953xCommon_rx_gain_table_honeybee_1p0), 2);
+            INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds,
+                qca953xCommon_rx_gain_bounds_honeybee_1p0,
+                ARRAY_LENGTH(qca953xCommon_rx_gain_bounds_honeybee_1p0), 5);
         } else {
             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
                 ar9300_common_rx_gain_table_osprey_2p2,
@@ -3571,6 +3658,13 @@ void ar9300_rx_gain_table_apply(struct ath_hal *ah)
             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds,
                 ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0,
                 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0), 5);
+        } else if (AR_SREV_HONEYBEE(ah)) {
+            INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
+                qca953xCommon_wo_xlna_rx_gain_table_honeybee_1p0,
+                ARRAY_LENGTH(qca953xCommon_wo_xlna_rx_gain_table_honeybee_1p0), 2);
+            INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds,
+                qca953xCommon_wo_xlna_rx_gain_bounds_honeybee_1p0,
+                ARRAY_LENGTH(qca953xCommon_wo_xlna_rx_gain_bounds_honeybee_1p0), 5);
         } else {
             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
                 ar9300Common_wo_xlna_rx_gain_table_osprey_2p2,
@@ -3629,6 +3723,11 @@ void ar9300_tx_gain_table_apply(struct ath_hal *ah)
                 ar9300Modes_low_ob_db_tx_gain_table_jupiter_2p0,
                 ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_jupiter_2p0),
                 5);
+        } else if (AR_SREV_HONEYBEE(ah)) {
+            INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
+           	qca953xModes_xpa_tx_gain_table_honeybee_1p0,
+                ARRAY_LENGTH(qca953xModes_xpa_tx_gain_table_honeybee_1p0),
+                2);
         } else if (AR_SREV_APHRODITE(ah)) {
             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
                 ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0,
@@ -3686,6 +3785,16 @@ void ar9300_tx_gain_table_apply(struct ath_hal *ah)
                 ar956XModes_high_ob_db_tx_gain_table_aphrodite_1p0,
                 ARRAY_LENGTH(
                 ar956XModes_high_ob_db_tx_gain_table_aphrodite_1p0), 5);
+        } else if (AR_SREV_HONEYBEE(ah)) {
+            if (AR_SREV_HONEYBEE_11(ah)) {
+                INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
+                    qca953xModes_no_xpa_tx_gain_table_honeybee_1p1,
+                    ARRAY_LENGTH(qca953xModes_no_xpa_tx_gain_table_honeybee_1p1), 2);
+            } else {
+                INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
+                    qca953xModes_no_xpa_tx_gain_table_honeybee_1p0,
+                    ARRAY_LENGTH(qca953xModes_no_xpa_tx_gain_table_honeybee_1p0), 2);
+            }
         } else {
             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
                 ar9300Modes_high_ob_db_tx_gain_table_osprey_2p2,
@@ -4159,6 +4268,8 @@ ar9300_probe(uint16_t vendorid, uint16_t devid)
         return "Qualcomm Atheros QCA955x";
     case AR9300_DEVID_QCA9565: /* Aphrodite */
          return "Qualcomm Atheros AR9565";
+    case AR9300_DEVID_QCA953X: /* Honeybee */
+         return "Qualcomm Atheros QCA953x";
     case AR9300_DEVID_AR1111_PCIE:
          return "Atheros AR1111";
     default:
diff --git a/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_eeprom.c b/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_eeprom.c
index c8d2b51..f1ae989 100644
--- a/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_eeprom.c
+++ b/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_eeprom.c
@@ -254,6 +254,9 @@ ar9300_otp_read(struct ath_hal *ah, u_int off, u_int32_t *data, HAL_BOOL is_wifi
     int status = 0;
     u_int32_t addr;
 
+    if (AR_SREV_HONEYBEE(ah)){ /* no OTP for Honeybee */
+        return false;
+    }
     addr = (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah))?
         OTP_MEM_START_ADDRESS_WASP : OTP_MEM_START_ADDRESS;
 	if (!is_wifi) {
@@ -354,7 +357,7 @@ ar9300_eeprom_attach(struct ath_hal *ah)
     ar9300_flash_map(ah);
     /*
      * ###### This function always return NO SPUR.
-     * This is not AH_TRUE for many board designs.
+     * This is not true for many board designs.
      * Does anyone use this?
      */
     AH_PRIVATE(ah)->ah_getSpurChan = ar9300_eeprom_get_spur_chan;
@@ -438,10 +441,15 @@ ar9300_eeprom_attach(struct ath_hal *ah)
         return HAL_OK;
     }
 #endif
-    if (AR_SREV_HORNET(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
+    if (AR_SREV_HORNET(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)
+        || AR_SREV_HONEYBEE(ah)) {
         ahp->try_eeprom = 0;
     }
 
+    if (AR_SREV_HONEYBEE(ah)) {
+        ahp->try_otp = 0;
+    }
+
     if (!ar9300_eeprom_restore(ah)) {
         return HAL_EIO;
     }
@@ -1652,6 +1660,8 @@ HAL_BOOL ar9300_ant_ctrl_apply(struct ath_hal *ah, HAL_BOOL is_2ghz)
 #define AR_SWITCH_TABLE_COM_JUPITER_ALL_S (0)
 #define AR_SWITCH_TABLE_COM_SCORPION_ALL (0xffffff)
 #define AR_SWITCH_TABLE_COM_SCORPION_ALL_S (0)
+#define AR_SWITCH_TABLE_COM_HONEYBEE_ALL (0xffffff)
+#define AR_SWITCH_TABLE_COM_HONEYBEE_ALL_S (0)
 #define AR_SWITCH_TABLE_COM_SPDT (0x00f00000)
     value = ar9300_ant_ctrl_common_get(ah, is_2ghz);
     if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
@@ -1667,6 +1677,10 @@ HAL_BOOL ar9300_ant_ctrl_apply(struct ath_hal *ah, HAL_BOOL is_2ghz)
         OS_REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, 
             AR_SWITCH_TABLE_COM_SCORPION_ALL, value);
     }
+    else if (AR_SREV_HONEYBEE(ah)) {
+        OS_REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, 
+            AR_SWITCH_TABLE_COM_HONEYBEE_ALL, value);
+    }
     else {
         OS_REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, 
             AR_SWITCH_TABLE_COM_ALL, value);
@@ -1713,7 +1727,7 @@ HAL_BOOL ar9300_ant_ctrl_apply(struct ath_hal *ah, HAL_BOOL is_2ghz)
         value = ar9300_ant_ctrl_chain_get(ah, 1, is_2ghz);
         OS_REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL, value);
 
-        if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah)) {
+        if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah) && !AR_SREV_HONEYBEE(ah)) {
             value = ar9300_ant_ctrl_chain_get(ah, 2, is_2ghz);
             OS_REG_RMW_FIELD(ah,
                 AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL, value);
@@ -1899,7 +1913,7 @@ HAL_BOOL ar9300_attenuation_apply(struct ath_hal *ah, u_int16_t channel)
         OS_REG_RMW_FIELD(ah,
             AR_PHY_EXT_ATTEN_CTL_1, AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
             value);
-        if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah)) {
+        if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah)&& !AR_SREV_HONEYBEE(ah) ) {
             value = ar9300_attenuation_chain_get(ah, 2, channel);
             OS_REG_RMW_FIELD(ah,
                 AR_PHY_EXT_ATTEN_CTL_2, AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
@@ -2270,7 +2284,7 @@ ar9300_power_control_override(struct ath_hal *ah, int frequency,
         OS_REG_RMW(ah, AR_PHY_TPC_11_B1,
             (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
             AR_PHY_TPC_OLPC_GAIN_DELTA);
-        if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah)) {
+        if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah) && !AR_SREV_HONEYBEE(ah) ) {
             OS_REG_RMW(ah, AR_PHY_TPC_11_B2, 
                 (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
                 AR_PHY_TPC_OLPC_GAIN_DELTA);
@@ -2284,7 +2298,7 @@ ar9300_power_control_override(struct ath_hal *ah, int frequency,
     if (!AR_SREV_POSEIDON(ah)) {
         OS_REG_RMW(ah, AR_PHY_TPC_6_B1, 
             (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S), AR_PHY_TPC_6_ERROR_EST_MODE);
-        if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah)) {
+        if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah) && !AR_SREV_HONEYBEE(ah)  ) {
             OS_REG_RMW(ah, AR_PHY_TPC_6_B2, 
                 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
                 AR_PHY_TPC_6_ERROR_EST_MODE);
@@ -2344,42 +2358,60 @@ ar9300_power_control_override(struct ath_hal *ah, int frequency,
 	 }
   }
 
-    if (!AR_SREV_SCORPION(ah)) {
+    if (!AR_SREV_SCORPION(ah) && !AR_SREV_HONEYBEE(ah)) {
         OS_REG_RMW_FIELD(ah,
             AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, temp_slope);
     } else {
-        /*Scorpion has tempSlope register for each chain*/
+        /*Scorpion and Honeybee has tempSlope register for each chain*/
         /*Check whether temp_compensation feature is enabled or not*/
         if (eep->base_eep_header.feature_enable & 0x1){
 	    if(frequency < 4000) {
+		if (((eep->base_eep_header.txrx_mask & 0xf0) >> 4) & 0x1) {
 		    OS_REG_RMW_FIELD(ah,
 				    AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, 
 				    eep->base_ext2.temp_slope_low);
+		    } 
+		if (((eep->base_eep_header.txrx_mask & 0xf0) >> 4) & 0x2) {
 		    OS_REG_RMW_FIELD(ah,
 				    AR_SCORPION_PHY_TPC_19_B1, AR_PHY_TPC_19_ALPHA_THERM, 
 				    temp_slope);
+		    } 
+		if (((eep->base_eep_header.txrx_mask & 0xf0) >> 4) & 0x4) {
 		    OS_REG_RMW_FIELD(ah,
 				    AR_SCORPION_PHY_TPC_19_B2, AR_PHY_TPC_19_ALPHA_THERM, 
 				    eep->base_ext2.temp_slope_high);
+		     } 	
 	    } else {
+		if (((eep->base_eep_header.txrx_mask & 0xf0) >> 4) & 0x1) {
 		    OS_REG_RMW_FIELD(ah,
 				    AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, 
 				    temp_slope);
+			}
+		if (((eep->base_eep_header.txrx_mask & 0xf0) >> 4) & 0x2) {
 		    OS_REG_RMW_FIELD(ah,
 				    AR_SCORPION_PHY_TPC_19_B1, AR_PHY_TPC_19_ALPHA_THERM, 
 				    temp_slope_1);
+		}
+		if (((eep->base_eep_header.txrx_mask & 0xf0) >> 4) & 0x4) {
 		    OS_REG_RMW_FIELD(ah,
 				    AR_SCORPION_PHY_TPC_19_B2, AR_PHY_TPC_19_ALPHA_THERM, 
 				    temp_slope_2);
+			} 
 	    }
         }else {
         	/* If temp compensation is not enabled, set all registers to 0*/
+		if (((eep->base_eep_header.txrx_mask & 0xf0) >> 4) & 0x1) {
             OS_REG_RMW_FIELD(ah,
                 AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, 0);
+		    }
+		if (((eep->base_eep_header.txrx_mask & 0xf0) >> 4) & 0x2) {
             OS_REG_RMW_FIELD(ah,
                 AR_SCORPION_PHY_TPC_19_B1, AR_PHY_TPC_19_ALPHA_THERM, 0);
+		    }  
+		if (((eep->base_eep_header.txrx_mask & 0xf0) >> 4) & 0x4) {
             OS_REG_RMW_FIELD(ah,
                 AR_SCORPION_PHY_TPC_19_B2, AR_PHY_TPC_19_ALPHA_THERM, 0);
+		} 
         }
     }
     OS_REG_RMW_FIELD(ah,
@@ -4392,7 +4424,7 @@ HAL_BOOL ar9300_thermometer_apply(struct ath_hal *ah)
         if (!AR_SREV_HORNET(ah) && !AR_SREV_POSEIDON(ah)) {
             OS_REG_RMW_FIELD(ah,
                 AR_PHY_65NM_CH1_RXTX4, AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR, 0);
-            if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah)) {
+            if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah) && !AR_SREV_HONEYBEE(ah)  ) {
                 OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4,
                     AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR, 0);
             }
@@ -4402,7 +4434,7 @@ HAL_BOOL ar9300_thermometer_apply(struct ath_hal *ah)
         if (!AR_SREV_HORNET(ah) && !AR_SREV_POSEIDON(ah)) {
             OS_REG_RMW_FIELD(ah,
                 AR_PHY_65NM_CH1_RXTX4, AR_PHY_65NM_CH0_RXTX4_THERM_ON, 0);
-            if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah)) {
+            if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah) && !AR_SREV_HONEYBEE(ah) ) {
                 OS_REG_RMW_FIELD(ah,
                     AR_PHY_65NM_CH2_RXTX4, AR_PHY_65NM_CH0_RXTX4_THERM_ON, 0);
             }
@@ -4413,7 +4445,7 @@ HAL_BOOL ar9300_thermometer_apply(struct ath_hal *ah)
         if (!AR_SREV_HORNET(ah) && !AR_SREV_POSEIDON(ah)) {
             OS_REG_RMW_FIELD(ah,
                 AR_PHY_65NM_CH1_RXTX4, AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR, 1);
-            if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah)) {
+            if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah) && !AR_SREV_HONEYBEE(ah)  ) {
                 OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4,
                     AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR, 1);
             }
@@ -4424,7 +4456,7 @@ HAL_BOOL ar9300_thermometer_apply(struct ath_hal *ah)
             if (!AR_SREV_HORNET(ah) && !AR_SREV_POSEIDON(ah)) {
                 OS_REG_RMW_FIELD(ah,
                     AR_PHY_65NM_CH1_RXTX4, AR_PHY_65NM_CH0_RXTX4_THERM_ON, 0);
-                if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah)) {
+                if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah) && !AR_SREV_HONEYBEE(ah) ) {
                     OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4,
                         AR_PHY_65NM_CH0_RXTX4_THERM_ON, 0);
                 }
@@ -4435,7 +4467,7 @@ HAL_BOOL ar9300_thermometer_apply(struct ath_hal *ah)
             if (!AR_SREV_HORNET(ah) && !AR_SREV_POSEIDON(ah)) {
                 OS_REG_RMW_FIELD(ah,
                     AR_PHY_65NM_CH1_RXTX4, AR_PHY_65NM_CH0_RXTX4_THERM_ON, 1);
-                if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah)) {
+                if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah) && !AR_SREV_HONEYBEE(ah) ) {
                     OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4,
                         AR_PHY_65NM_CH0_RXTX4_THERM_ON, 0);
                 }
@@ -4446,7 +4478,7 @@ HAL_BOOL ar9300_thermometer_apply(struct ath_hal *ah)
             if (!AR_SREV_HORNET(ah) && !AR_SREV_POSEIDON(ah)) {
                 OS_REG_RMW_FIELD(ah,
                     AR_PHY_65NM_CH1_RXTX4, AR_PHY_65NM_CH0_RXTX4_THERM_ON, 0);
-                if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah)) {
+                if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah) && !AR_SREV_HONEYBEE(ah) ) {
                     OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4,
                         AR_PHY_65NM_CH0_RXTX4_THERM_ON, 1);
                 }
@@ -4476,9 +4508,8 @@ HAL_BOOL ar9300_tuning_caps_apply(struct ath_hal *ah)
     if ((eep->base_eep_header.feature_enable & 0x40) >> 6) {
         tuning_caps_params &= 0x7f;
 
-        /* XXX TODO: ath9k skips it for Wasp and Honeybee/AR9531, not Poseidon */
-        if (AR_SREV_POSEIDON(ah) || AR_SREV_WASP(ah)) {
-            return AH_TRUE;
+        if (AR_SREV_POSEIDON(ah) || AR_SREV_WASP(ah) || AR_SREV_HONEYBEE(ah)) {
+            return true;
         } else if (AR_SREV_HORNET(ah)) {
             OS_REG_RMW_FIELD(ah,
                 AR_HORNET_CH0_XTAL, AR_OSPREY_CHO_XTAL_CAPINDAC,
@@ -4515,7 +4546,7 @@ HAL_BOOL ar9300_xpa_timing_control_apply(struct ath_hal *ah, HAL_BOOL is_2ghz)
     u_int8_t xpa_timing_control;
     ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom;
     if ((eep->base_eep_header.feature_enable & 0x80) >> 7) {
-		if (AR_SREV_OSPREY(ah) || AR_SREV_AR9580(ah) || AR_SREV_WASP(ah)) {
+		if (AR_SREV_OSPREY(ah) || AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_HONEYBEE(ah)) {
 			if (is_2ghz) {
                 xpa_timing_control = eep->modal_header_2g.tx_frame_to_xpa_on;
                 OS_REG_RMW_FIELD(ah,
@@ -4586,7 +4617,7 @@ ar9300_eeprom_set_board_values(struct ath_hal *ah, const struct ieee80211_channe
 	/* wait for Poseidon internal regular turnning */
     /* for Hornet we move it before initPLL to avoid an access issue */
     /* Function not used when EMULATION. */
-    if (!AR_SREV_HORNET(ah) && !AR_SREV_WASP(ah)) {
+    if (!AR_SREV_HORNET(ah) && !AR_SREV_WASP(ah) && !AR_SREV_HONEYBEE(ah)) {
         ar9300_internal_regulator_apply(ah);
     }
 
diff --git a/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_freebsd_inc.h b/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_freebsd_inc.h
index 1af621b..6a294af 100644
--- a/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_freebsd_inc.h
+++ b/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_freebsd_inc.h
@@ -61,6 +61,9 @@
 #ifdef	AH_SUPPORT_QCA9550
 #define AH_SUPPORT_SCORPION             1
 #endif	/* AH_SUPPORT_QCA9550 */
+#ifdef	AH_SUPPORT_QCA9530
+#define	AH_SUPPORT_HONEYBEE		1
+#endif	/* AH_SUPPORT_QCA9530 */
 #define FIX_NOISE_FLOOR                 1
 
 /* XXX this needs to be removed! No atomics in the HAL! */
diff --git a/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_radar.c b/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_radar.c
index 2a5f5bd..cfe0748 100644
--- a/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_radar.c
+++ b/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_radar.c
@@ -578,7 +578,7 @@ ar9300_handle_radar_bb_panic(struct ath_hal *ah)
         /* EV92527: we do not need a reset if we see this signature */
         HALDEBUG(ah, HAL_DEBUG_DFS, "%s: BB Panic -- 0x1300000a\n", __func__);
         return AH_TRUE;
-    } else if (AR_SREV_WASP(ah) && (status == 0x04000409)) {
+    } else if ((AR_SREV_WASP(ah) || AR_SREV_HONEYBEE(ah)) && (status == 0x04000409)) {
         return AH_TRUE;
     } else {
         if (ar9300_get_capability(ah, HAL_CAP_LDPCWAR, 0, AH_NULL) == HAL_OK &&
diff --git a/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_radio.c b/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_radio.c
index 9b29471..f3dbe06 100644
--- a/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_radio.c
+++ b/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_radio.c
@@ -134,7 +134,7 @@ ar9300_set_channel(struct ath_hal *ah, struct ieee80211_channel *chan)
             channel_sel = (freq * 4) / 120;
             channel_frac = (((freq * 4) % 120) * 0x20000) / 120;
             channel_sel = (channel_sel << 17) | (channel_frac);
-        } else if (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
+        } else if (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah) || AR_SREV_HONEYBEE(ah)) {
             u_int32_t channel_frac;
             if (clk_25mhz) {
                 /* 
@@ -143,7 +143,7 @@ ar9300_set_channel(struct ath_hal *ah, struct ieee80211_channel *chan)
                  * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
                  * chansel = int(ndiv),  chanfrac = (ndiv - chansel) * 0x20000
                  */
-                if (AR_SREV_SCORPION(ah)) {
+                if (AR_SREV_SCORPION(ah) || AR_SREV_HONEYBEE(ah)) {
                     /* Doubler is off for Scorpion */
                     channel_sel = (freq * 4) / 75;
                     channel_frac = (((freq * 4) % 75) * 0x20000) / 75;
diff --git a/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_recv.c b/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_recv.c
index c919d3c..e5f4519 100644
--- a/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_recv.c
+++ b/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_recv.c
@@ -228,7 +228,7 @@ ar9300_set_rx_filter(struct ath_hal *ah, u_int32_t bits)
 {
     u_int32_t phybits;
 
-    if (AR_SREV_SCORPION(ah)) {
+    if (AR_SREV_SCORPION(ah) || AR_SREV_HONEYBEE(ah)) {
         /* Enable Rx for 4 address frames */
         bits |= AR_RX_4ADDRESS;
     }
diff --git a/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_reset.c b/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_reset.c
index fcfa58e..3a95c35 100644
--- a/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_reset.c
+++ b/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_reset.c
@@ -288,7 +288,7 @@ ar9300_upload_noise_floor(struct ath_hal *ah, int is_2g,
      */
     if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) {
         chainmask = 0x01;
-    } else if (AR_SREV_WASP(ah) || AR_SREV_JUPITER(ah)) {
+    } else if (AR_SREV_WASP(ah) || AR_SREV_JUPITER(ah) || AR_SREV_HONEYBEE(ah)) {
         chainmask = 0x03;
     } else {
         chainmask = 0x07;
@@ -1476,7 +1476,7 @@ ar9300_init_pll(struct ath_hal *ah, struct ieee80211_channel *chan)
 
         OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x142c);
         OS_DELAY(1000);
-    } else if (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
+    } else if (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah) || AR_SREV_HONEYBEE(ah)) {
 #define SRIF_PLL 1
         u_int32_t regdata, pll2_divint, pll2_divfrac;
 
@@ -1492,9 +1492,15 @@ ar9300_init_pll(struct ath_hal *ah, struct ieee80211_channel *chan)
             pll2_divint = 0x1c;
             pll2_divfrac = 0xa3d7;
 #else
-            pll2_divint = 0x54;
-            pll2_divfrac = 0x1eb85;
-            refdiv = 3;
+            if (AR_SREV_HONEYBEE(ah)) {
+                pll2_divint = 0x1c;
+                pll2_divfrac = 0xa3d2;
+                refdiv = 1;
+            } else {
+                pll2_divint = 0x54;
+                pll2_divfrac = 0x1eb85;
+                refdiv = 3;
+            }
 #endif
         } else {
 #ifndef SRIF_PLL
@@ -1520,7 +1526,11 @@ ar9300_init_pll(struct ath_hal *ah, struct ieee80211_channel *chan)
         OS_DELAY(1000);
         do {
             regdata = OS_REG_READ(ah, AR_PHY_PLL_MODE);
-            regdata = regdata | (0x1 << 16);
+            if (AR_SREV_HONEYBEE(ah)) {
+                regdata = regdata | (0x1 << 22);
+            } else {
+                regdata = regdata | (0x1 << 16);
+            }
             OS_REG_WRITE(ah, AR_PHY_PLL_MODE, regdata); /* PWD_PLL set to 1 */
             OS_DELAY(100);
             /* override int, frac, refdiv */
@@ -1540,6 +1550,12 @@ ar9300_init_pll(struct ath_hal *ah, struct ieee80211_channel *chan)
             if (AR_SREV_WASP(ah)) {
                 regdata = (regdata & 0x80071fff) |
                     (0x1 << 30) | (0x1 << 13) | (0x4 << 26) | (0x18 << 19);
+            } else if (AR_SREV_HONEYBEE(ah)) {
+                /*
+                 * Kd=10, Ki=2, Outdiv=1, Local PLL=0, Phase Shift=4 
+                 */
+                regdata = (regdata & 0x01c00fff) |
+                    (0x1 << 31) | (0x2 << 29) | (0xa << 25) | (0x1 << 19) | (0x6 << 12);
             } else {
                 regdata = (regdata & 0x80071fff) |
                     (0x3 << 30) | (0x1 << 13) | (0x4 << 26) | (0x60 << 19);
@@ -1548,7 +1564,11 @@ ar9300_init_pll(struct ath_hal *ah, struct ieee80211_channel *chan)
             /* Ki, Kd, Local PLL, Outdiv */
             OS_REG_WRITE(ah, AR_PHY_PLL_MODE, regdata);
             regdata = OS_REG_READ(ah, AR_PHY_PLL_MODE);
-            regdata = (regdata & 0xfffeffff);
+            if (AR_SREV_HONEYBEE(ah)) {
+                regdata = (regdata & 0xffbfffff);
+            } else {
+                regdata = (regdata & 0xfffeffff);
+            }
             OS_REG_WRITE(ah, AR_PHY_PLL_MODE, regdata); /* PWD_PLL set to 0 */
             OS_DELAY(1000);
             if (AR_SREV_WASP(ah)) {
@@ -1617,6 +1637,7 @@ ar9300_init_pll(struct ath_hal *ah, struct ieee80211_channel *chan)
     OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK,
         AR_RTC_FORCE_DERIVED_CLK | AR_RTC_PCIE_RST_PWDN_EN);
 
+    /* XXX TODO: honeybee? */
     if (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
         if (clk_25mhz) {
             OS_REG_WRITE(ah,
@@ -1950,6 +1971,9 @@ ar9300_phy_disable(struct ath_hal *ah)
         /* Turn off JMPST led */
         REG_WRITE(ATH_GPIO_OUT, (REG_READ(ATH_GPIO_OUT) | (0x1 << 15)));
     }
+    else if (AR_SREV_HONEYBEE(ah)) {
+        REG_WRITE(ATH_GPIO_OE, (REG_READ(ATH_GPIO_OE) | (0x1 << 12)));
+    }
 #undef REG_READ
 #undef REG_WRITE
 #endif
@@ -2207,7 +2231,7 @@ ar9300_load_nf(struct ath_hal *ah, int16_t nf[])
      */
     if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) {
         chainmask = 0x9;
-    } else if (AR_SREV_WASP(ah) || AR_SREV_JUPITER(ah)) {
+    } else if (AR_SREV_WASP(ah) || AR_SREV_JUPITER(ah) || AR_SREV_HONEYBEE(ah)) {
         chainmask = 0x1b;
     } else {
         chainmask = 0x3F;
@@ -2395,7 +2419,7 @@ ar9300_calibration(struct ath_hal *ah, struct ieee80211_channel *chan, u_int8_t
         HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
             "%s: Chain 1 Rx IQ Cal Correction 0x%08x\n",
             __func__, OS_REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B1));
-        if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah)) {
+        if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah) && !AR_SREV_HONEYBEE(ah)) {
             HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
                 "%s: Chain 2 Rx IQ Cal Correction 0x%08x\n",
                 __func__, OS_REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B2));
@@ -2855,6 +2879,7 @@ ar9300_process_ini(struct ath_hal *ah, struct ieee80211_channel *chan,
             }
         }
         modes_index = 1;
+        freq_index  = 1;
         break;
 
     case CHANNEL_A_HT40PLUS:
@@ -2869,6 +2894,7 @@ ar9300_process_ini(struct ath_hal *ah, struct ieee80211_channel *chan,
             }
         }
         modes_index = 2;
+        freq_index  = 1;
         break;
 
     case CHANNEL_PUREG:
@@ -2876,20 +2902,27 @@ ar9300_process_ini(struct ath_hal *ah, struct ieee80211_channel *chan,
     case CHANNEL_B:
         if (AR_SREV_SCORPION(ah)){
             modes_txgaintable_index = 8;
-        }
+        }else if (AR_SREV_HONEYBEE(ah)){
+	    modes_txgaintable_index = 1;
+	}
         modes_index = 4;
+        freq_index  = 2;
         break;
 
     case CHANNEL_G_HT40PLUS:
     case CHANNEL_G_HT40MINUS:
         if (AR_SREV_SCORPION(ah)){
             modes_txgaintable_index = 7;
+        }else if (AR_SREV_HONEYBEE(ah)){
+            modes_txgaintable_index = 1;
         }
         modes_index = 3;
+        freq_index  = 2;
         break;
 
     case CHANNEL_108G:
         modes_index = 5;
+        freq_index  = 2;
         break;
 
     default:
@@ -2930,11 +2963,15 @@ ar9300_process_ini(struct ath_hal *ah, struct ieee80211_channel *chan,
         } else if (IEEE80211_IS_CHAN_HT40U(chan) || IEEE80211_IS_CHAN_HT40D(chan)) {
             if (AR_SREV_SCORPION(ah)){
                 modes_txgaintable_index = 7;
+            } else if (AR_SREV_HONEYBEE(ah)){
+                modes_txgaintable_index = 1;
             }
             modes_index = 3;
         } else if (IEEE80211_IS_CHAN_HT20(chan) || IEEE80211_IS_CHAN_G(chan) || IEEE80211_IS_CHAN_B(chan) || IEEE80211_IS_CHAN_PUREG(chan)) {
             if (AR_SREV_SCORPION(ah)){
                 modes_txgaintable_index = 8;
+            } else if (AR_SREV_HONEYBEE(ah)){
+                modes_txgaintable_index = 1;
             }
             modes_index = 4;
         } else
@@ -3045,7 +3082,7 @@ ar9300_process_ini(struct ath_hal *ah, struct ieee80211_channel *chan,
 
 
     /* Write txgain Array Parameters */
-    if (AR_SREV_SCORPION(ah)) {
+    if (AR_SREV_SCORPION(ah) || AR_SREV_HONEYBEE(ah)) {
         REG_WRITE_ARRAY(&ahp->ah_ini_modes_txgain, modes_txgaintable_index, 
             reg_writes);
     }else{
@@ -3510,7 +3547,7 @@ ar9300_init_cal_internal(struct ath_hal *ah, struct ieee80211_channel *chan,
         /* Hornet: 1 x 1 */
         ahp->ah_rx_cal_chainmask = 0x1;
         ahp->ah_tx_cal_chainmask = 0x1;
-    } else if (AR_SREV_WASP(ah) || AR_SREV_JUPITER(ah)) {
+    } else if (AR_SREV_WASP(ah) || AR_SREV_JUPITER(ah) || AR_SREV_HONEYBEE(ah)) {
         /* Wasp/Jupiter: 2 x 2 */
         ahp->ah_rx_cal_chainmask = 0x3;
         ahp->ah_tx_cal_chainmask = 0x3;
@@ -4069,7 +4106,7 @@ ar9300_init_bb(struct ath_hal *ah, struct ieee80211_channel *chan)
     /*
      * There is an issue if the AP starts the calibration before
      * the base band timeout completes.  This could result in the
-     * rx_clear AH_FALSE triggering.  As a workaround we add delay an
+     * rx_clear false triggering.  As a workaround we add delay an
      * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
      * does not happen.
      */
@@ -4438,6 +4475,7 @@ ar9300_reset(struct ath_hal *ah, HAL_OPMODE opmode, struct ieee80211_channel *ch
 #ifdef ATH_FORCE_PPM
     u_int32_t               save_force_val, tmp_reg;
 #endif
+    u_int8_t                clk_25mhz = AH9300(ah)->clk_25mhz;
     HAL_BOOL                    stopped, cal_ret;
     HAL_BOOL                    apply_last_iqcorr = AH_FALSE;
 
@@ -4449,7 +4487,7 @@ ar9300_reset(struct ath_hal *ah, HAL_OPMODE opmode, struct ieee80211_channel *ch
 
     /*
      * Set the status to "ok" by default to cover the cases
-     * where we return AH_FALSE without going to "bad"
+     * where we return false without going to "bad"
      */
     HALASSERT(status);
     *status = HAL_OK;
@@ -4792,6 +4830,18 @@ ar9300_reset(struct ath_hal *ah, HAL_OPMODE opmode, struct ieee80211_channel *ch
     if (ecode != HAL_OK) {
         goto bad;
     }
+ 
+    /*
+     * Configuring WMAC PLL values for 25/40 MHz 
+     */
+    if(AR_SREV_WASP(ah) || AR_SREV_HONEYBEE(ah) || AR_SREV_SCORPION(ah) ) {
+        if(clk_25mhz) {
+            OS_REG_WRITE(ah, AR_RTC_DERIVED_RTC_CLK, (0x17c << 1)); // 32KHz sleep clk
+        } else {
+            OS_REG_WRITE(ah, AR_RTC_DERIVED_RTC_CLK, (0x261 << 1)); // 32KHz sleep clk
+        }
+        OS_DELAY(100);
+    }
 
     ahp->ah_immunity_on = AH_FALSE;
 
@@ -5147,14 +5197,14 @@ ar9300_reset(struct ath_hal *ah, HAL_OPMODE opmode, struct ieee80211_channel *ch
      * For big endian systems turn on swapping for descriptors
      */
 #if AH_BYTE_ORDER == AH_BIG_ENDIAN
-    if (AR_SREV_HORNET(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
+    if (AR_SREV_HORNET(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah) || AR_SREV_HONEYBEE(ah)) {
         OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTB | AR_CFG_SWRB, 0);
     } else {
         ar9300_init_cfg_reg(ah);
     }
 #endif
 
-    if ( AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
+    if ( AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah) || AR_SREV_HONEYBEE(ah) ) {
         OS_REG_RMW(ah, AR_CFG_LED, AR_CFG_LED_ASSOC_CTL, AR_CFG_LED_ASSOC_CTL);
     }
 
@@ -5189,6 +5239,10 @@ ar9300_reset(struct ath_hal *ah, HAL_OPMODE opmode, struct ieee80211_channel *ch
     	    REG_WRITE(ATH_GPIO_OE, (( REG_READ(ATH_GPIO_OE) & (~(0x1 << 12) )) | (0x1 << 13)));
         }
     }
+    else if (AR_SREV_HONEYBEE(ah)) {
+            REG_WRITE(ATH_GPIO_OUT_FUNCTION3, ( REG_READ(ATH_GPIO_OUT_FUNCTION3) & (~(0xff))) | (0x32) );
+            REG_WRITE(ATH_GPIO_OE, (( REG_READ(ATH_GPIO_OE) & (~(0x1 << 12) ))));
+    }
 #undef REG_READ
 #undef REG_WRITE
 #endif
diff --git a/sys/contrib/dev/ath/ath_hal/ar9300/ar9300reg.h b/sys/contrib/dev/ath/ath_hal/ar9300/ar9300reg.h
index 9f444e4..0d072e3 100644
--- a/sys/contrib/dev/ath/ath_hal/ar9300/ar9300reg.h
+++ b/sys/contrib/dev/ath/ath_hal/ar9300/ar9300reg.h
@@ -2945,6 +2945,7 @@ enum {
 #define AR_SREV_VERSION_WASP   0x300 /* XXX: Check Wasp version number */
 #define AR_SREV_VERSION_SCORPION 0x400
 #define AR_SREV_VERSION_POSEIDON 0x240
+#define AR_SREV_VERSION_HONEYBEE 0x500
 #define AR_SREV_VERSION_APHRODITE 0x2C0
 
 #define AR_SREV_REVISION_OSPREY_10            0      /* Osprey 1.0 */
@@ -2972,6 +2973,10 @@ enum {
 #define AR_SREV_REVISION_JUPITER_20           2      /* Jupiter 2.0 */
 #define AR_SREV_REVISION_JUPITER_21           3      /* Jupiter 2.1 */
 
+#define AR_SREV_REVISION_HONEYBEE_10          0      /* Honeybee 1.0 */
+#define AR_SREV_REVISION_HONEYBEE_11          1      /* Honeybee 1.1 */
+#define AR_SREV_REVISION_HONEYBEE_MASK        0xf    /* Honeybee revision mask */
+
 #define AR_SREV_REVISION_APHRODITE_10         0      /* Aphrodite 1.0 */
 
 #if defined(AH_SUPPORT_OSPREY)
@@ -3000,7 +3005,7 @@ enum {
 
 /* NOTE: When adding chips newer than Peacock, add chip check here.  */
 #define AR_SREV_AR9580_10_OR_LATER(_ah) \
-    (AR_SREV_AR9580(_ah))
+    (AR_SREV_AR9580(_ah) || AR_SREV_SCORPION(_ah) || AR_SREV_HONEYBEE(_ah))
 
 #define AR_SREV_JUPITER(_ah) \
     ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER))
@@ -3061,6 +3066,21 @@ enum {
 #define AR_SREV_WASP(_ah)                                         0
 #endif /* #if defined(AH_SUPPORT_WASP) */
 
+#if defined(AH_SUPPORT_HONEYBEE)
+#define AR_SREV_HONEYBEE(_ah) \
+    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_HONEYBEE))
+#define AR_SREV_HONEYBEE_10(_ah) \
+    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_HONEYBEE) && \
+     (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_HONEYBEE_10))
+#define AR_SREV_HONEYBEE_11(_ah) \
+    ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_HONEYBEE) && \
+     (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_HONEYBEE_11))
+#else
+#define AR_SREV_HONEYBEE(_ah)                                         0
+#define AR_SREV_HONEYBEE_10(_ah) 0
+#define AR_SREV_HONEYBEE_11(_ah) 0
+#endif /* #if defined(AH_SUPPORT_HONEYBEE) */
+
 #define AR_SREV_WASP_10(_ah) \
     ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_WASP) && \
      (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_WASP_10))
@@ -3103,7 +3123,7 @@ enum {
 
 #define AR_SREV_POSEIDON_OR_LATER(_ah) \
     (AH_PRIVATE((_ah))->ah_macVersion >= AR_SREV_VERSION_POSEIDON)
-#define AR_SREV_SOC(_ah) (AR_SREV_HORNET(_ah) || AR_SREV_POSEIDON(_ah) || AR_SREV_WASP(_ah))
+#define AR_SREV_SOC(_ah) (AR_SREV_HORNET(_ah) || AR_SREV_POSEIDON(_ah) || AR_SREV_WASP(_ah) || AR_SREV_HONEYBEE(_ah))
 /*
 * Mask used to construct AAD for CCMP-AES
 * Cisco spec defined bits 0-3 as mask