Break out the arge MDIO bus code into an optional argemdio device.

This is only done if the ARGE_MDIO option is included.

* Shuffle the arge MDIO bus into a separate device, that needs to be
  probed early (use hint.argemdio.X.order=0)
* hint.arge.X.mdio now specifies which miiproxy to rendezvous with.
* Call MAC/MDIO bus init during MDIO attach, not arge attach.

This is done regardless:

* Shift the arge MAC and MDIO bus reset code into separate functions
  and call it early during MDIO bus attach.  It's required for
  correct MDIO bus IO to occur on AR71xx/AR91xx devices.

* Remove the AR71xx/AR91xx centric assumption that there's only one
  MDIO bus.  The initial code mapped miibus0(arge0) and miibus1(arge1)
  MII register operations to the MII0 (arge0) register space.  The
  AR724x (and later, upcoming chipsets) have two MDIO busses and
  the second is very much in use.

TODO:

* since the multiphy behaviour has changed (where now a phymask of >1
  PHY will still be enumerated), multiphy setups may be quite wrong.
  I'll go and fix these so they still have a chance of working, at least.
  until the switch PHY support appears in -HEAD.

Submitted by:	Stefan Bethke <stb@lassitu.de>

1 files changed, 1 insertions, 0 deletions

diff --git a/sys/conf/options.mips b/sys/conf/options.mips
index 9816147..71eb414 100644
--- a/sys/conf/options.mips
+++ b/sys/conf/options.mips
@@ -66,6 +66,7 @@ OCTEON_BOARD_CAPK_0100ND	opt_cvmx.h
 # Options that control the Atheros SoC peripherals
 #
 ARGE_DEBUG			opt_arge.h
+ARGE_MDIO			opt_arge.h
 
 #
 # Options that control the Ralink RT305xF Etherenet MAC.