diff options
| author | ian <ian@FreeBSD.org> | 2014-03-09 21:12:31 +0000 |
|---|---|---|
| committer | ian <ian@FreeBSD.org> | 2014-03-09 21:12:31 +0000 |
| commit | ab495f6c9b034c2f3f40db2e5c237afe71598846 (patch) | |
| tree | 4bbce15618b3dff2ffc3009f48d735b611e461ac /sys/arm | |
| parent | 5325036e28f5a02667b2b4d1afcc3fea08a45642 (diff) | |
| download | FreeBSD-src-ab495f6c9b034c2f3f40db2e5c237afe71598846.zip FreeBSD-src-ab495f6c9b034c2f3f40db2e5c237afe71598846.tar.gz | |
Remove all traces of support for ARM chips prior to the arm9 series. We
never actually ran on these chips (other than using SA1 support in an
emulator to do the early porting to FreeBSD long long ago). The clutter
and complexity of some of this code keeps getting in the way of other
maintenance, so it's time to go.
Diffstat (limited to 'sys/arm')
38 files changed, 25 insertions, 5331 deletions
diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c index 8f97f14..07726a3 100644 --- a/sys/arm/arm/cpufunc.c +++ b/sys/arm/arm/cpufunc.c @@ -1,9 +1,6 @@ /* $NetBSD: cpufunc.c,v 1.65 2003/11/05 12:53:15 scw Exp $ */ /*- - * arm7tdmi support code Copyright (c) 2001 John Fremlin - * arm8 support code Copyright (c) 1997 ARM Limited - * arm8 support code Copyright (c) 1997 Causality Limited * arm9 support code Copyright (C) 2001 ARM Ltd * Copyright (c) 1997 Mark Brinicombe. * Copyright (c) 1997 Causality Limited @@ -112,131 +109,6 @@ u_int arm_cache_loc; int cpu_do_powersave; int ctrl; -#ifdef CPU_ARM7TDMI -struct cpu_functions arm7tdmi_cpufuncs = { - /* CPU functions */ - - cpufunc_id, /* id */ - cpufunc_nullop, /* cpwait */ - - /* MMU functions */ - - cpufunc_control, /* control */ - cpufunc_domains, /* domain */ - arm7tdmi_setttb, /* setttb */ - cpufunc_faultstatus, /* faultstatus */ - cpufunc_faultaddress, /* faultaddress */ - - /* TLB functions */ - - arm7tdmi_tlb_flushID, /* tlb_flushID */ - arm7tdmi_tlb_flushID_SE, /* tlb_flushID_SE */ - arm7tdmi_tlb_flushID, /* tlb_flushI */ - arm7tdmi_tlb_flushID_SE, /* tlb_flushI_SE */ - arm7tdmi_tlb_flushID, /* tlb_flushD */ - arm7tdmi_tlb_flushID_SE, /* tlb_flushD_SE */ - - /* Cache operations */ - - cpufunc_nullop, /* icache_sync_all */ - (void *)cpufunc_nullop, /* icache_sync_range */ - - arm7tdmi_cache_flushID, /* dcache_wbinv_all */ - (void *)arm7tdmi_cache_flushID, /* dcache_wbinv_range */ - (void *)arm7tdmi_cache_flushID, /* dcache_inv_range */ - (void *)cpufunc_nullop, /* dcache_wb_range */ - - cpufunc_nullop, /* idcache_inv_all */ - arm7tdmi_cache_flushID, /* idcache_wbinv_all */ - (void *)arm7tdmi_cache_flushID, /* idcache_wbinv_range */ - cpufunc_nullop, /* l2cache_wbinv_all */ - (void *)cpufunc_nullop, /* l2cache_wbinv_range */ - (void *)cpufunc_nullop, /* l2cache_inv_range */ - (void *)cpufunc_nullop, /* l2cache_wb_range */ - - /* Other functions */ - - cpufunc_nullop, /* flush_prefetchbuf */ - cpufunc_nullop, /* drain_writebuf */ - cpufunc_nullop, /* flush_brnchtgt_C */ - (void *)cpufunc_nullop, /* flush_brnchtgt_E */ - - (void *)cpufunc_nullop, /* sleep */ - - /* Soft functions */ - - late_abort_fixup, /* dataabt_fixup */ - cpufunc_null_fixup, /* prefetchabt_fixup */ - - arm7tdmi_context_switch, /* context_switch */ - - arm7tdmi_setup /* cpu setup */ - -}; -#endif /* CPU_ARM7TDMI */ - -#ifdef CPU_ARM8 -struct cpu_functions arm8_cpufuncs = { - /* CPU functions */ - - cpufunc_id, /* id */ - cpufunc_nullop, /* cpwait */ - - /* MMU functions */ - - cpufunc_control, /* control */ - cpufunc_domains, /* domain */ - arm8_setttb, /* setttb */ - cpufunc_faultstatus, /* faultstatus */ - cpufunc_faultaddress, /* faultaddress */ - - /* TLB functions */ - - arm8_tlb_flushID, /* tlb_flushID */ - arm8_tlb_flushID_SE, /* tlb_flushID_SE */ - arm8_tlb_flushID, /* tlb_flushI */ - arm8_tlb_flushID_SE, /* tlb_flushI_SE */ - arm8_tlb_flushID, /* tlb_flushD */ - arm8_tlb_flushID_SE, /* tlb_flushD_SE */ - - /* Cache operations */ - - cpufunc_nullop, /* icache_sync_all */ - (void *)cpufunc_nullop, /* icache_sync_range */ - - arm8_cache_purgeID, /* dcache_wbinv_all */ - (void *)arm8_cache_purgeID, /* dcache_wbinv_range */ -/*XXX*/ (void *)arm8_cache_purgeID, /* dcache_inv_range */ - (void *)arm8_cache_cleanID, /* dcache_wb_range */ - - cpufunc_nullop, /* idcache_inv_all */ - arm8_cache_purgeID, /* idcache_wbinv_all */ - (void *)arm8_cache_purgeID, /* idcache_wbinv_range */ - cpufunc_nullop, /* l2cache_wbinv_all */ - (void *)cpufunc_nullop, /* l2cache_wbinv_range */ - (void *)cpufunc_nullop, /* l2cache_inv_range */ - (void *)cpufunc_nullop, /* l2cache_wb_range */ - - /* Other functions */ - - cpufunc_nullop, /* flush_prefetchbuf */ - cpufunc_nullop, /* drain_writebuf */ - cpufunc_nullop, /* flush_brnchtgt_C */ - (void *)cpufunc_nullop, /* flush_brnchtgt_E */ - - (void *)cpufunc_nullop, /* sleep */ - - /* Soft functions */ - - cpufunc_null_fixup, /* dataabt_fixup */ - cpufunc_null_fixup, /* prefetchabt_fixup */ - - arm8_context_switch, /* context_switch */ - - arm8_setup /* cpu setup */ -}; -#endif /* CPU_ARM8 */ - #ifdef CPU_ARM9 struct cpu_functions arm9_cpufuncs = { /* CPU functions */ @@ -550,192 +422,6 @@ struct cpu_functions pj4bv7_cpufuncs = { }; #endif /* CPU_MV_PJ4B */ -#ifdef CPU_SA110 -struct cpu_functions sa110_cpufuncs = { - /* CPU functions */ - - cpufunc_id, /* id */ - cpufunc_nullop, /* cpwait */ - - /* MMU functions */ - - cpufunc_control, /* control */ - cpufunc_domains, /* domain */ - sa1_setttb, /* setttb */ - cpufunc_faultstatus, /* faultstatus */ - cpufunc_faultaddress, /* faultaddress */ - - /* TLB functions */ - - armv4_tlb_flushID, /* tlb_flushID */ - sa1_tlb_flushID_SE, /* tlb_flushID_SE */ - armv4_tlb_flushI, /* tlb_flushI */ - (void *)armv4_tlb_flushI, /* tlb_flushI_SE */ - armv4_tlb_flushD, /* tlb_flushD */ - armv4_tlb_flushD_SE, /* tlb_flushD_SE */ - - /* Cache operations */ - - sa1_cache_syncI, /* icache_sync_all */ - sa1_cache_syncI_rng, /* icache_sync_range */ - - sa1_cache_purgeD, /* dcache_wbinv_all */ - sa1_cache_purgeD_rng, /* dcache_wbinv_range */ -/*XXX*/ sa1_cache_purgeD_rng, /* dcache_inv_range */ - sa1_cache_cleanD_rng, /* dcache_wb_range */ - - sa1_cache_flushID, /* idcache_inv_all */ - sa1_cache_purgeID, /* idcache_wbinv_all */ - sa1_cache_purgeID_rng, /* idcache_wbinv_range */ - cpufunc_nullop, /* l2cache_wbinv_all */ - (void *)cpufunc_nullop, /* l2cache_wbinv_range */ - (void *)cpufunc_nullop, /* l2cache_inv_range */ - (void *)cpufunc_nullop, /* l2cache_wb_range */ - - /* Other functions */ - - cpufunc_nullop, /* flush_prefetchbuf */ - armv4_drain_writebuf, /* drain_writebuf */ - cpufunc_nullop, /* flush_brnchtgt_C */ - (void *)cpufunc_nullop, /* flush_brnchtgt_E */ - - (void *)cpufunc_nullop, /* sleep */ - - /* Soft functions */ - - cpufunc_null_fixup, /* dataabt_fixup */ - cpufunc_null_fixup, /* prefetchabt_fixup */ - - sa110_context_switch, /* context_switch */ - - sa110_setup /* cpu setup */ -}; -#endif /* CPU_SA110 */ - -#if defined(CPU_SA1100) || defined(CPU_SA1110) -struct cpu_functions sa11x0_cpufuncs = { - /* CPU functions */ - - cpufunc_id, /* id */ - cpufunc_nullop, /* cpwait */ - - /* MMU functions */ - - cpufunc_control, /* control */ - cpufunc_domains, /* domain */ - sa1_setttb, /* setttb */ - cpufunc_faultstatus, /* faultstatus */ - cpufunc_faultaddress, /* faultaddress */ - - /* TLB functions */ - - armv4_tlb_flushID, /* tlb_flushID */ - sa1_tlb_flushID_SE, /* tlb_flushID_SE */ - armv4_tlb_flushI, /* tlb_flushI */ - (void *)armv4_tlb_flushI, /* tlb_flushI_SE */ - armv4_tlb_flushD, /* tlb_flushD */ - armv4_tlb_flushD_SE, /* tlb_flushD_SE */ - - /* Cache operations */ - - sa1_cache_syncI, /* icache_sync_all */ - sa1_cache_syncI_rng, /* icache_sync_range */ - - sa1_cache_purgeD, /* dcache_wbinv_all */ - sa1_cache_purgeD_rng, /* dcache_wbinv_range */ -/*XXX*/ sa1_cache_purgeD_rng, /* dcache_inv_range */ - sa1_cache_cleanD_rng, /* dcache_wb_range */ - - sa1_cache_flushID, /* idcache_inv_all */ - sa1_cache_purgeID, /* idcache_wbinv_all */ - sa1_cache_purgeID_rng, /* idcache_wbinv_range */ - cpufunc_nullop, /* l2cache_wbinv_all */ - (void *)cpufunc_nullop, /* l2cache_wbinv_range */ - (void *)cpufunc_nullop, /* l2cache_inv_range */ - (void *)cpufunc_nullop, /* l2cache_wb_range */ - - /* Other functions */ - - sa11x0_drain_readbuf, /* flush_prefetchbuf */ - armv4_drain_writebuf, /* drain_writebuf */ - cpufunc_nullop, /* flush_brnchtgt_C */ - (void *)cpufunc_nullop, /* flush_brnchtgt_E */ - - sa11x0_cpu_sleep, /* sleep */ - - /* Soft functions */ - - cpufunc_null_fixup, /* dataabt_fixup */ - cpufunc_null_fixup, /* prefetchabt_fixup */ - - sa11x0_context_switch, /* context_switch */ - - sa11x0_setup /* cpu setup */ -}; -#endif /* CPU_SA1100 || CPU_SA1110 */ - -#ifdef CPU_IXP12X0 -struct cpu_functions ixp12x0_cpufuncs = { - /* CPU functions */ - - cpufunc_id, /* id */ - cpufunc_nullop, /* cpwait */ - - /* MMU functions */ - - cpufunc_control, /* control */ - cpufunc_domains, /* domain */ - sa1_setttb, /* setttb */ - cpufunc_faultstatus, /* faultstatus */ - cpufunc_faultaddress, /* faultaddress */ - - /* TLB functions */ - - armv4_tlb_flushID, /* tlb_flushID */ - sa1_tlb_flushID_SE, /* tlb_flushID_SE */ - armv4_tlb_flushI, /* tlb_flushI */ - (void *)armv4_tlb_flushI, /* tlb_flushI_SE */ - armv4_tlb_flushD, /* tlb_flushD */ - armv4_tlb_flushD_SE, /* tlb_flushD_SE */ - - /* Cache operations */ - - sa1_cache_syncI, /* icache_sync_all */ - sa1_cache_syncI_rng, /* icache_sync_range */ - - sa1_cache_purgeD, /* dcache_wbinv_all */ - sa1_cache_purgeD_rng, /* dcache_wbinv_range */ -/*XXX*/ sa1_cache_purgeD_rng, /* dcache_inv_range */ - sa1_cache_cleanD_rng, /* dcache_wb_range */ - - sa1_cache_flushID, /* idcache_inv_all */ - sa1_cache_purgeID, /* idcache_wbinv_all */ - sa1_cache_purgeID_rng, /* idcache_wbinv_range */ - cpufunc_nullop, /* l2cache_wbinv_all */ - (void *)cpufunc_nullop, /* l2cache_wbinv_range */ - (void *)cpufunc_nullop, /* l2cache_inv_range */ - (void *)cpufunc_nullop, /* l2cache_wb_range */ - - /* Other functions */ - - ixp12x0_drain_readbuf, /* flush_prefetchbuf */ - armv4_drain_writebuf, /* drain_writebuf */ - cpufunc_nullop, /* flush_brnchtgt_C */ - (void *)cpufunc_nullop, /* flush_brnchtgt_E */ - - (void *)cpufunc_nullop, /* sleep */ - - /* Soft functions */ - - cpufunc_null_fixup, /* dataabt_fixup */ - cpufunc_null_fixup, /* prefetchabt_fixup */ - - ixp12x0_context_switch, /* context_switch */ - - ixp12x0_setup /* cpu setup */ -}; -#endif /* CPU_IXP12X0 */ - #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ defined(CPU_XSCALE_80219) @@ -1128,7 +814,7 @@ struct cpu_functions cpufuncs; u_int cputype; u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore.s */ -#if defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \ +#if defined(CPU_ARM9) || \ defined (CPU_ARM9E) || defined (CPU_ARM10) || defined (CPU_ARM1136) || \ defined(CPU_ARM1176) || defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ @@ -1247,61 +933,7 @@ get_cachetype_cp15() arm_dcache_align_mask = arm_dcache_align - 1; } } -#endif /* ARM7TDMI || ARM8 || ARM9 || XSCALE */ - -#if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ - defined(CPU_IXP12X0) -/* Cache information for CPUs without cache type registers. */ -struct cachetab { - u_int32_t ct_cpuid; - int ct_pcache_type; - int ct_pcache_unified; - int ct_pdcache_size; - int ct_pdcache_line_size; - int ct_pdcache_ways; - int ct_picache_size; - int ct_picache_line_size; - int ct_picache_ways; -}; - -struct cachetab cachetab[] = { - /* cpuid, cache type, u, dsiz, ls, wy, isiz, ls, wy */ - /* XXX is this type right for SA-1? */ - { CPU_ID_SA110, CPU_CT_CTYPE_WB1, 0, 16384, 32, 32, 16384, 32, 32 }, - { CPU_ID_SA1100, CPU_CT_CTYPE_WB1, 0, 8192, 32, 32, 16384, 32, 32 }, - { CPU_ID_SA1110, CPU_CT_CTYPE_WB1, 0, 8192, 32, 32, 16384, 32, 32 }, - { CPU_ID_IXP1200, CPU_CT_CTYPE_WB1, 0, 16384, 32, 32, 16384, 32, 32 }, /* XXX */ - { 0, 0, 0, 0, 0, 0, 0, 0} -}; - -static void get_cachetype_table(void); - -static void -get_cachetype_table() -{ - int i; - u_int32_t cpuid = cpufunc_id(); - - for (i = 0; cachetab[i].ct_cpuid != 0; i++) { - if (cachetab[i].ct_cpuid == (cpuid & CPU_ID_CPU_MASK)) { - arm_pcache_type = cachetab[i].ct_pcache_type; - arm_pcache_unified = cachetab[i].ct_pcache_unified; - arm_pdcache_size = cachetab[i].ct_pdcache_size; - arm_pdcache_line_size = - cachetab[i].ct_pdcache_line_size; - arm_pdcache_ways = cachetab[i].ct_pdcache_ways; - arm_picache_size = cachetab[i].ct_picache_size; - arm_picache_line_size = - cachetab[i].ct_picache_line_size; - arm_picache_ways = cachetab[i].ct_picache_ways; - } - } - arm_dcache_align = arm_pdcache_line_size; - - arm_dcache_align_mask = arm_dcache_align - 1; -} - -#endif /* SA110 || SA1100 || SA1111 || IXP12X0 */ +#endif /* ARM9 || XSCALE */ /* * Cannot panic here as we may not have a console yet ... @@ -1318,27 +950,6 @@ set_cpufuncs() * CPU type where we want to use it by default, then we set it. */ -#ifdef CPU_ARM7TDMI - if ((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD && - CPU_ID_IS7(cputype) && - (cputype & CPU_ID_7ARCH_MASK) == CPU_ID_7ARCH_V4T) { - cpufuncs = arm7tdmi_cpufuncs; - cpu_reset_needs_v4_MMU_disable = 0; - get_cachetype_cp15(); - pmap_pte_init_generic(); - goto out; - } -#endif -#ifdef CPU_ARM8 - if ((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD && - (cputype & 0x0000f000) == 0x00008000) { - cpufuncs = arm8_cpufuncs; - cpu_reset_needs_v4_MMU_disable = 0; /* XXX correct? */ - get_cachetype_cp15(); - pmap_pte_init_arm8(); - goto out; - } -#endif /* CPU_ARM8 */ #ifdef CPU_ARM9 if (((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD || (cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_TI) && @@ -1464,39 +1075,7 @@ set_cpufuncs() goto out; } #endif /* CPU_MV_PJ4B */ -#ifdef CPU_SA110 - if (cputype == CPU_ID_SA110) { - cpufuncs = sa110_cpufuncs; - cpu_reset_needs_v4_MMU_disable = 1; /* SA needs it */ - get_cachetype_table(); - pmap_pte_init_sa1(); - goto out; - } -#endif /* CPU_SA110 */ -#ifdef CPU_SA1100 - if (cputype == CPU_ID_SA1100) { - cpufuncs = sa11x0_cpufuncs; - cpu_reset_needs_v4_MMU_disable = 1; /* SA needs it */ - get_cachetype_table(); - pmap_pte_init_sa1(); - /* Use powersave on this CPU. */ - cpu_do_powersave = 1; - goto out; - } -#endif /* CPU_SA1100 */ -#ifdef CPU_SA1110 - if (cputype == CPU_ID_SA1110) { - cpufuncs = sa11x0_cpufuncs; - cpu_reset_needs_v4_MMU_disable = 1; /* SA needs it */ - get_cachetype_table(); - pmap_pte_init_sa1(); - /* Use powersave on this CPU. */ - cpu_do_powersave = 1; - - goto out; - } -#endif /* CPU_SA1110 */ #if defined(CPU_FA526) || defined(CPU_FA626TE) if (cputype == CPU_ID_FA526 || cputype == CPU_ID_FA626TE) { cpufuncs = fa526_cpufuncs; @@ -1510,15 +1089,7 @@ set_cpufuncs() goto out; } #endif /* CPU_FA526 || CPU_FA626TE */ -#ifdef CPU_IXP12X0 - if (cputype == CPU_ID_IXP1200) { - cpufuncs = ixp12x0_cpufuncs; - cpu_reset_needs_v4_MMU_disable = 1; - get_cachetype_table(); - pmap_pte_init_sa1(); - goto out; - } -#endif /* CPU_IXP12X0 */ + #ifdef CPU_XSCALE_80200 if (cputype == CPU_ID_80200) { int rev = cpufunc_id() & CPU_ID_REVISION_MASK; @@ -1627,8 +1198,6 @@ out: * * DEBUG_FAULT_CORRECTION - Print debugging information during the * correction of registers after a fault. - * ARM6_LATE_ABORT - ARM6 supports both early and late aborts - * when defined should use late aborts */ @@ -1643,344 +1212,12 @@ cpufunc_null_fixup(arg) return(ABORT_FIXUP_OK); } - -#if defined(CPU_ARM7TDMI) - -#ifdef DEBUG_FAULT_CORRECTION -#define DFC_PRINTF(x) printf x -#define DFC_DISASSEMBLE(x) disassemble(x) -#else -#define DFC_PRINTF(x) /* nothing */ -#define DFC_DISASSEMBLE(x) /* nothing */ -#endif - -/* - * "Early" data abort fixup. - * - * For ARM2, ARM2as, ARM3 and ARM6 (in early-abort mode). Also used - * indirectly by ARM6 (in late-abort mode) and ARM7[TDMI]. - * - * In early aborts, we may have to fix up LDM, STM, LDC and STC. - */ -int -early_abort_fixup(arg) - void *arg; -{ - struct trapframe *frame = arg; - u_int fault_pc; - u_int fault_instruction; - int saved_lr = 0; - - if ((frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE) { - - /* Ok an abort in SVC mode */ - - /* - * Copy the SVC r14 into the usr r14 - The usr r14 is garbage - * as the fault happened in svc mode but we need it in the - * usr slot so we can treat the registers as an array of ints - * during fixing. - * NOTE: This PC is in the position but writeback is not - * allowed on r15. - * Doing it like this is more efficient than trapping this - * case in all possible locations in the following fixup code. - */ - - saved_lr = frame->tf_usr_lr; - frame->tf_usr_lr = frame->tf_svc_lr; - - /* - * Note the trapframe does not have the SVC r13 so a fault - * from an instruction with writeback to r13 in SVC mode is - * not allowed. This should not happen as the kstack is - * always valid. - */ - } - - /* Get fault address and status from the CPU */ - - fault_pc = frame->tf_pc; - fault_instruction = *((volatile unsigned int *)fault_pc); - - /* Decode the fault instruction and fix the registers as needed */ - - if ((fault_instruction & 0x0e000000) == 0x08000000) { - int base; - int loop; - int count; - int *registers = &frame->tf_r0; - - DFC_PRINTF(("LDM/STM\n")); - DFC_DISASSEMBLE(fault_pc); - if (fault_instruction & (1 << 21)) { - DFC_PRINTF(("This instruction must be corrected\n")); - base = (fault_instruction >> 16) & 0x0f; - if (base == 15) - return ABORT_FIXUP_FAILED; - /* Count registers transferred */ - count = 0; - for (loop = 0; loop < 16; ++loop) { - if (fault_instruction & (1<<loop)) - ++count; - } - DFC_PRINTF(("%d registers used\n", count)); - DFC_PRINTF(("Corrected r%d by %d bytes ", - base, count * 4)); - if (fault_instruction & (1 << 23)) { - DFC_PRINTF(("down\n")); - registers[base] -= count * 4; - } else { - DFC_PRINTF(("up\n")); - registers[base] += count * 4; - } - } - } else if ((fault_instruction & 0x0e000000) == 0x0c000000) { - int base; - int offset; - int *registers = &frame->tf_r0; - - /* REGISTER CORRECTION IS REQUIRED FOR THESE INSTRUCTIONS */ - - DFC_DISASSEMBLE(fault_pc); - - /* Only need to fix registers if write back is turned on */ - - if ((fault_instruction & (1 << 21)) != 0) { - base = (fault_instruction >> 16) & 0x0f; - if (base == 13 && - (frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE) - return ABORT_FIXUP_FAILED; - if (base == 15) - return ABORT_FIXUP_FAILED; - - offset = (fault_instruction & 0xff) << 2; - DFC_PRINTF(("r%d=%08x\n", base, registers[base])); - if ((fault_instruction & (1 << 23)) != 0) - offset = -offset; - registers[base] += offset; - DFC_PRINTF(("r%d=%08x\n", base, registers[base])); - } - } else if ((fault_instruction & 0x0e000000) == 0x0c000000) - return ABORT_FIXUP_FAILED; - - if ((frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE) { - - /* Ok an abort in SVC mode */ - - /* - * Copy the SVC r14 into the usr r14 - The usr r14 is garbage - * as the fault happened in svc mode but we need it in the - * usr slot so we can treat the registers as an array of ints - * during fixing. - * NOTE: This PC is in the position but writeback is not - * allowed on r15. - * Doing it like this is more efficient than trapping this - * case in all possible locations in the prior fixup code. - */ - - frame->tf_svc_lr = frame->tf_usr_lr; - frame->tf_usr_lr = saved_lr; - - /* - * Note the trapframe does not have the SVC r13 so a fault - * from an instruction with writeback to r13 in SVC mode is - * not allowed. This should not happen as the kstack is - * always valid. - */ - } - - return(ABORT_FIXUP_OK); -} -#endif /* CPU_ARM2/250/3/6/7 */ - - -#if defined(CPU_ARM7TDMI) -/* - * "Late" (base updated) data abort fixup - * - * For ARM6 (in late-abort mode) and ARM7. - * - * In this model, all data-transfer instructions need fixing up. We defer - * LDM, STM, LDC and STC fixup to the early-abort handler. - */ -int -late_abort_fixup(arg) - void *arg; -{ - struct trapframe *frame = arg; - u_int fault_pc; - u_int fault_instruction; - int saved_lr = 0; - - if ((frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE) { - - /* Ok an abort in SVC mode */ - - /* - * Copy the SVC r14 into the usr r14 - The usr r14 is garbage - * as the fault happened in svc mode but we need it in the - * usr slot so we can treat the registers as an array of ints - * during fixing. - * NOTE: This PC is in the position but writeback is not - * allowed on r15. - * Doing it like this is more efficient than trapping this - * case in all possible locations in the following fixup code. - */ - - saved_lr = frame->tf_usr_lr; - frame->tf_usr_lr = frame->tf_svc_lr; - - /* - * Note the trapframe does not have the SVC r13 so a fault - * from an instruction with writeback to r13 in SVC mode is - * not allowed. This should not happen as the kstack is - * always valid. - */ - } - - /* Get fault address and status from the CPU */ - - fault_pc = frame->tf_pc; - fault_instruction = *((volatile unsigned int *)fault_pc); - - /* Decode the fault instruction and fix the registers as needed */ - - /* Was is a swap instruction ? */ - - if ((fault_instruction & 0x0fb00ff0) == 0x01000090) { - DFC_DISASSEMBLE(fault_pc); - } else if ((fault_instruction & 0x0c000000) == 0x04000000) { - - /* Was is a ldr/str instruction */ - /* This is for late abort only */ - - int base; - int offset; - int *registers = &frame->tf_r0; - - DFC_DISASSEMBLE(fault_pc); - - /* This is for late abort only */ - - if ((fault_instruction & (1 << 24)) == 0 - || (fault_instruction & (1 << 21)) != 0) { - /* postindexed ldr/str with no writeback */ - - base = (fault_instruction >> 16) & 0x0f; - if (base == 13 && - (frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE) - return ABORT_FIXUP_FAILED; - if (base == 15) - return ABORT_FIXUP_FAILED; - DFC_PRINTF(("late abt fix: r%d=%08x : ", - base, registers[base])); - if ((fault_instruction & (1 << 25)) == 0) { - /* Immediate offset - easy */ - - offset = fault_instruction & 0xfff; - if ((fault_instruction & (1 << 23))) - offset = -offset; - registers[base] += offset; - DFC_PRINTF(("imm=%08x ", offset)); - } else { - /* offset is a shifted register */ - int shift; - - offset = fault_instruction & 0x0f; - if (offset == base) - return ABORT_FIXUP_FAILED; - - /* - * Register offset - hard we have to - * cope with shifts ! - */ - offset = registers[offset]; - - if ((fault_instruction & (1 << 4)) == 0) - /* shift with amount */ - shift = (fault_instruction >> 7) & 0x1f; - else { - /* shift with register */ - if ((fault_instruction & (1 << 7)) != 0) - /* undefined for now so bail out */ - return ABORT_FIXUP_FAILED; - shift = ((fault_instruction >> 8) & 0xf); - if (base == shift) - return ABORT_FIXUP_FAILED; - DFC_PRINTF(("shift reg=%d ", shift)); - shift = registers[shift]; - } - DFC_PRINTF(("shift=%08x ", shift)); - switch (((fault_instruction >> 5) & 0x3)) { - case 0 : /* Logical left */ - offset = (int)(((u_int)offset) << shift); - break; - case 1 : /* Logical Right */ - if (shift == 0) shift = 32; - offset = (int)(((u_int)offset) >> shift); - break; - case 2 : /* Arithmetic Right */ - if (shift == 0) shift = 32; - offset = (int)(((int)offset) >> shift); - break; - case 3 : /* Rotate right (rol or rxx) */ - return ABORT_FIXUP_FAILED; - break; - } - - DFC_PRINTF(("abt: fixed LDR/STR with " - "register offset\n")); - if ((fault_instruction & (1 << 23))) - offset = -offset; - DFC_PRINTF(("offset=%08x ", offset)); - registers[base] += offset; - } - DFC_PRINTF(("r%d=%08x\n", base, registers[base])); - } - } - - if ((frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE) { - - /* Ok an abort in SVC mode */ - - /* - * Copy the SVC r14 into the usr r14 - The usr r14 is garbage - * as the fault happened in svc mode but we need it in the - * usr slot so we can treat the registers as an array of ints - * during fixing. - * NOTE: This PC is in the position but writeback is not - * allowed on r15. - * Doing it like this is more efficient than trapping this - * case in all possible locations in the prior fixup code. - */ - - frame->tf_svc_lr = frame->tf_usr_lr; - frame->tf_usr_lr = saved_lr; - - /* - * Note the trapframe does not have the SVC r13 so a fault - * from an instruction with writeback to r13 in SVC mode is - * not allowed. This should not happen as the kstack is - * always valid. - */ - } - - /* - * Now let the early-abort fixup routine have a go, in case it - * was an LDM, STM, LDC or STC that faulted. - */ - - return early_abort_fixup(arg); -} -#endif /* CPU_ARM7TDMI */ - /* * CPU Setup code */ -#if defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined (CPU_ARM9) || \ +#if defined (CPU_ARM9) || \ defined(CPU_ARM9E) || \ - defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \ @@ -2030,148 +1267,7 @@ parse_cpu_options(args, optlist, cpuctrl) } return(cpuctrl); } -#endif /* CPU_ARM7TDMI || CPU_ARM8 || CPU_SA110 || XSCALE*/ - -#if defined(CPU_ARM7TDMI) || defined(CPU_ARM8) -struct cpu_option arm678_options[] = { -#ifdef COMPAT_12 - { "nocache", IGN, BIC, CPU_CONTROL_IDC_ENABLE }, - { "nowritebuf", IGN, BIC, CPU_CONTROL_WBUF_ENABLE }, -#endif /* COMPAT_12 */ - { "cpu.cache", BIC, OR, CPU_CONTROL_IDC_ENABLE }, - { "cpu.nocache", OR, BIC, CPU_CONTROL_IDC_ENABLE }, - { "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE }, - { "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE }, - { NULL, IGN, IGN, 0 } -}; - -#endif /* CPU_ARM6 || CPU_ARM7 || CPU_ARM7TDMI || CPU_ARM8 */ - -#ifdef CPU_ARM7TDMI -struct cpu_option arm7tdmi_options[] = { - { "arm7.cache", BIC, OR, CPU_CONTROL_IDC_ENABLE }, - { "arm7.nocache", OR, BIC, CPU_CONTROL_IDC_ENABLE }, - { "arm7.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE }, - { "arm7.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE }, -#ifdef COMPAT_12 - { "fpaclk2", BIC, OR, CPU_CONTROL_CPCLK }, -#endif /* COMPAT_12 */ - { "arm700.fpaclk", BIC, OR, CPU_CONTROL_CPCLK }, - { NULL, IGN, IGN, 0 } -}; - -void -arm7tdmi_setup(args) - char *args; -{ - int cpuctrl; - - cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE - | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE - | CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE; - - cpuctrl = parse_cpu_options(args, arm678_options, cpuctrl); - cpuctrl = parse_cpu_options(args, arm7tdmi_options, cpuctrl); - -#ifdef __ARMEB__ - cpuctrl |= CPU_CONTROL_BEND_ENABLE; -#endif - - /* Clear out the cache */ - cpu_idcache_wbinv_all(); - - /* Set the control register */ - ctrl = cpuctrl; - cpu_control(0xffffffff, cpuctrl); -} -#endif /* CPU_ARM7TDMI */ - -#ifdef CPU_ARM8 -struct cpu_option arm8_options[] = { - { "arm8.cache", BIC, OR, CPU_CONTROL_IDC_ENABLE }, - { "arm8.nocache", OR, BIC, CPU_CONTROL_IDC_ENABLE }, - { "arm8.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE }, - { "arm8.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE }, -#ifdef COMPAT_12 - { "branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE }, -#endif /* COMPAT_12 */ - { "cpu.branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE }, - { "arm8.branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE }, - { NULL, IGN, IGN, 0 } -}; - -void -arm8_setup(args) - char *args; -{ - int integer; - int cpuctrl, cpuctrlmask; - int clocktest; - int setclock = 0; - - cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE - | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE - | CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE; - cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE - | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE - | CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE - | CPU_CONTROL_BPRD_ENABLE | CPU_CONTROL_ROM_ENABLE - | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE; - -#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS - cpuctrl |= CPU_CONTROL_AFLT_ENABLE; -#endif - - cpuctrl = parse_cpu_options(args, arm678_options, cpuctrl); - cpuctrl = parse_cpu_options(args, arm8_options, cpuctrl); - -#ifdef __ARMEB__ - cpuctrl |= CPU_CONTROL_BEND_ENABLE; -#endif - - /* Get clock configuration */ - clocktest = arm8_clock_config(0, 0) & 0x0f; - - /* Special ARM8 clock and test configuration */ - if (get_bootconf_option(args, "arm8.clock.reset", BOOTOPT_TYPE_BOOLEAN, &integer)) { - clocktest = 0; - setclock = 1; - } - if (get_bootconf_option(args, "arm8.clock.dynamic", BOOTOPT_TYPE_BOOLEAN, &integer)) { - if (integer) - clocktest |= 0x01; - else - clocktest &= ~(0x01); - setclock = 1; - } - if (get_bootconf_option(args, "arm8.clock.sync", BOOTOPT_TYPE_BOOLEAN, &integer)) { - if (integer) - clocktest |= 0x02; - else - clocktest &= ~(0x02); - setclock = 1; - } - if (get_bootconf_option(args, "arm8.clock.fast", BOOTOPT_TYPE_BININT, &integer)) { - clocktest = (clocktest & ~0xc0) | (integer & 3) << 2; - setclock = 1; - } - if (get_bootconf_option(args, "arm8.test", BOOTOPT_TYPE_BININT, &integer)) { - clocktest |= (integer & 7) << 5; - setclock = 1; - } - - /* Clear out the cache */ - cpu_idcache_wbinv_all(); - - /* Set the control register */ - ctrl = cpuctrl; - cpu_control(0xffffffff, cpuctrl); - - /* Set the clock/test register */ - if (setclock) - arm8_clock_config(0x7f, clocktest); -} -#endif /* CPU_ARM8 */ +#endif /* CPU_ARM9 || XSCALE*/ #ifdef CPU_ARM9 struct cpu_option arm9_options[] = { @@ -2471,124 +1567,6 @@ cortexa_setup(char *args) } #endif /* CPU_CORTEXA */ - -#ifdef CPU_SA110 -struct cpu_option sa110_options[] = { -#ifdef COMPAT_12 - { "nocache", IGN, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "nowritebuf", IGN, BIC, CPU_CONTROL_WBUF_ENABLE }, -#endif /* COMPAT_12 */ - { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "sa110.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "sa110.icache", BIC, OR, CPU_CONTROL_IC_ENABLE }, - { "sa110.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE }, - { "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE }, - { "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE }, - { "sa110.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE }, - { NULL, IGN, IGN, 0 } -}; - -void -sa110_setup(args) - char *args; -{ - int cpuctrl, cpuctrlmask; - - cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE - | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE - | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE - | CPU_CONTROL_WBUF_ENABLE; - cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE - | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE - | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE - | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_ROM_ENABLE - | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE - | CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_BPRD_ENABLE - | CPU_CONTROL_CPCLK; - -#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS - cpuctrl |= CPU_CONTROL_AFLT_ENABLE; -#endif - - cpuctrl = parse_cpu_options(args, sa110_options, cpuctrl); - -#ifdef __ARMEB__ - cpuctrl |= CPU_CONTROL_BEND_ENABLE; -#endif - - /* Clear out the cache */ - cpu_idcache_wbinv_all(); - - /* Set the control register */ - ctrl = cpuctrl; -/* cpu_control(cpuctrlmask, cpuctrl);*/ - cpu_control(0xffffffff, cpuctrl); - - /* - * enable clockswitching, note that this doesn't read or write to r0, - * r0 is just to make it valid asm - */ - __asm ("mcr 15, 0, r0, c15, c1, 2"); -} -#endif /* CPU_SA110 */ - -#if defined(CPU_SA1100) || defined(CPU_SA1110) -struct cpu_option sa11x0_options[] = { -#ifdef COMPAT_12 - { "nocache", IGN, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "nowritebuf", IGN, BIC, CPU_CONTROL_WBUF_ENABLE }, -#endif /* COMPAT_12 */ - { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "sa11x0.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "sa11x0.icache", BIC, OR, CPU_CONTROL_IC_ENABLE }, - { "sa11x0.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE }, - { "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE }, - { "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE }, - { "sa11x0.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE }, - { NULL, IGN, IGN, 0 } -}; - -void -sa11x0_setup(args) - char *args; -{ - int cpuctrl, cpuctrlmask; - - cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE - | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE - | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE - | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_LABT_ENABLE; - cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE - | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE - | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE - | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_ROM_ENABLE - | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE - | CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_BPRD_ENABLE - | CPU_CONTROL_CPCLK | CPU_CONTROL_VECRELOC; - -#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS - cpuctrl |= CPU_CONTROL_AFLT_ENABLE; -#endif - - - cpuctrl = parse_cpu_options(args, sa11x0_options, cpuctrl); - -#ifdef __ARMEB__ - cpuctrl |= CPU_CONTROL_BEND_ENABLE; -#endif - - if (vector_page == ARM_VECTORS_HIGH) - cpuctrl |= CPU_CONTROL_VECRELOC; - /* Clear out the cache */ - cpu_idcache_wbinv_all(); - /* Set the control register */ - ctrl = cpuctrl; - cpu_control(0xffffffff, cpuctrl); -} -#endif /* CPU_SA1100 || CPU_SA1110 */ - #if defined(CPU_FA526) || defined(CPU_FA626TE) struct cpu_option fa526_options[] = { #ifdef COMPAT_12 @@ -2645,60 +1623,6 @@ fa526_setup(char *args) } #endif /* CPU_FA526 || CPU_FA626TE */ - -#if defined(CPU_IXP12X0) -struct cpu_option ixp12x0_options[] = { - { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "ixp12x0.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, - { "ixp12x0.icache", BIC, OR, CPU_CONTROL_IC_ENABLE }, - { "ixp12x0.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE }, - { "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE }, - { "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE }, - { "ixp12x0.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE }, - { NULL, IGN, IGN, 0 } -}; - -void -ixp12x0_setup(args) - char *args; -{ - int cpuctrl, cpuctrlmask; - - - cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE - | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_SYST_ENABLE - | CPU_CONTROL_IC_ENABLE; - - cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_AFLT_ENABLE - | CPU_CONTROL_DC_ENABLE | CPU_CONTROL_WBUF_ENABLE - | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_SYST_ENABLE - | CPU_CONTROL_ROM_ENABLE | CPU_CONTROL_IC_ENABLE - | CPU_CONTROL_VECRELOC; - -#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS - cpuctrl |= CPU_CONTROL_AFLT_ENABLE; -#endif - - cpuctrl = parse_cpu_options(args, ixp12x0_options, cpuctrl); - -#ifdef __ARMEB__ - cpuctrl |= CPU_CONTROL_BEND_ENABLE; -#endif - - if (vector_page == ARM_VECTORS_HIGH) - cpuctrl |= CPU_CONTROL_VECRELOC; - - /* Clear out the cache */ - cpu_idcache_wbinv_all(); - - /* Set the control register */ - ctrl = cpuctrl; - /* cpu_control(0xffffffff, cpuctrl); */ - cpu_control(cpuctrlmask, cpuctrl); -} -#endif /* CPU_IXP12X0 */ - #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) diff --git a/sys/arm/arm/cpufunc_asm_arm7tdmi.S b/sys/arm/arm/cpufunc_asm_arm7tdmi.S deleted file mode 100644 index 2ac2502..0000000 --- a/sys/arm/arm/cpufunc_asm_arm7tdmi.S +++ /dev/null @@ -1,106 +0,0 @@ -/* $NetBSD: cpufunc_asm_arm7tdmi.S,v 1.1 2001/11/10 23:14:09 thorpej Exp $ */ - -/*- - * Copyright (c) 2001 John Fremlin - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Causality Limited. - * 4. The name of Causality Limited may not be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * ARM7TDMI assembly functions for CPU / MMU / TLB specific operations - * - */ - -#include <machine/asm.h> -__FBSDID("$FreeBSD$"); - -/* - * Functions to set the MMU Translation Table Base register - * - * We need to clean and flush the cache as it uses virtual - * addresses that are about to change. - */ -ENTRY(arm7tdmi_setttb) - mov r1, r0 /* store the TTB in a safe place */ - mov r2, lr /* ditto with lr */ - - bl _C_LABEL(arm7tdmi_cache_flushID) - - /* Write the TTB */ - mcr p15, 0, r1, c2, c0, 0 - - /* If we have updated the TTB we must flush the TLB */ - bl _C_LABEL(arm7tdmi_tlb_flushID) - - /* For good measure we will flush the IDC as well */ - bl _C_LABEL(arm7tdmi_cache_flushID) - - mov pc, r2 -END(arm7tdmi_setttb) - -/* - * TLB functions - */ -ENTRY(arm7tdmi_tlb_flushID) - mov r0, #0 - mcr p15, 0, r0, c8, c7, 0 - RET -END(arm7tdmi_tlb_flushID) - -ENTRY(arm7tdmi_tlb_flushID_SE) - mcr p15, 0, r0, c8, c7, 1 - RET -END(arm7tdmi_tlb_flushID_SE) - -/* - * Cache functions - */ -ENTRY(arm7tdmi_cache_flushID) - mov r0, #0 - - mcr p15, 0, r0, c7, c7, 0 - - /* Make sure that the pipeline is emptied */ - mov r0, r0 - mov r0, r0 - - RET -END(arm7tdmi_cache_flushID) - -/* - * Context switch. - * - * These is the CPU-specific parts of the context switcher cpu_switch() - * These functions actually perform the TTB reload. - * - * NOTE: Special calling convention - * r1, r4-r13 must be preserved - */ -ENTRY(arm7tdmi_context_switch) - b _C_LABEL(arm7tdmi_setttb) -END(arm7tdmi_context_switch) - diff --git a/sys/arm/arm/cpufunc_asm_arm8.S b/sys/arm/arm/cpufunc_asm_arm8.S deleted file mode 100644 index 787e5b2..0000000 --- a/sys/arm/arm/cpufunc_asm_arm8.S +++ /dev/null @@ -1,296 +0,0 @@ -/* $NetBSD: cpufunc_asm_arm8.S,v 1.2 2001/11/11 00:47:49 thorpej Exp $ */ - -/*- - * Copyright (c) 1997 ARM Limited - * Copyright (c) 1997 Causality Limited - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Causality Limited. - * 4. The name of Causality Limited may not be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * ARM8 assembly functions for CPU / MMU / TLB specific operations - * - */ - -#include <machine/asm.h> -__FBSDID("$FreeBSD$"); - -ENTRY(arm8_clock_config) - mrc p15, 0, r3, c15, c0, 0 /* Read the clock register */ - bic r2, r3, #0x11 /* turn off dynamic clocking - and clear L bit */ - mcr p15, 0, r2, c15, c0, 0 /* Write clock register */ - - bic r2, r3, r0 /* Clear bits */ - eor r2, r2, r1 /* XOR bits */ - bic r2, r2, #0x10 /* clear the L bit */ - - bic r1, r2, #0x01 /* still keep dynamic clocking off */ - mcr p15, 0, r1, c15, c0, 0 /* Write clock register */ - mov r0, r0 /* NOP */ - mov r0, r0 /* NOP */ - mov r0, r0 /* NOP */ - mov r0, r0 /* NOP */ - mcr p15, 0, r2, c15, c0, 0 /* Write clock register */ - mov r0, r3 /* Return old value */ - RET -END(arm8_clock_config) - -/* - * Functions to set the MMU Translation Table Base register - * - * We need to clean and flush the cache as it uses virtual - * addresses that are about to change. - */ -ENTRY(arm8_setttb) - mrs r3, cpsr - orr r1, r3, #(I32_bit | F32_bit) - msr cpsr_fsxc, r1 - - stmfd sp!, {r0-r3, lr} - bl _C_LABEL(arm8_cache_cleanID) - ldmfd sp!, {r0-r3, lr} - mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */ - - /* Write the TTB */ - mcr p15, 0, r0, c2, c0, 0 - - /* If we have updated the TTB we must flush the TLB */ - mcr p15, 0, r0, c8, c7, 0 - - /* For good measure we will flush the IDC as well */ - mcr p15, 0, r0, c7, c7, 0 - - /* Make sure that pipeline is emptied */ - mov r0, r0 - mov r0, r0 - msr cpsr_fsxc, r3 - - RET -END(arm8_setttb) - -/* - * TLB functions - */ -ENTRY(arm8_tlb_flushID) - mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */ - RET -END(arm8_tlb_flushID) - -ENTRY(arm8_tlb_flushID_SE) - mcr p15, 0, r0, c8, c7, 1 /* flush I+D tlb single entry */ - RET -END(arm8_tlb_flushID_SE) - -/* - * Cache functions - */ -ENTRY(arm8_cache_flushID) - mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */ - RET -END(arm8_cache_flushID) - -ENTRY(arm8_cache_flushID_E) - mcr p15, 0, r0, c7, c7, 1 /* flush I+D single entry */ - RET -END(arm8_cache_flushID_E) - -ENTRY(arm8_cache_cleanID) - mov r0, #0x00000000 - -1: mov r2, r0 - mcr p15, 0, r2, c7, c11, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - - adds r0, r0, #0x04000000 - bne 1b - - RET -END(arm8_cache_cleanID) - -ENTRY(arm8_cache_cleanID_E) - mcr p15, 0, r0, c7, c11, 1 /* clean I+D single entry */ - RET -END(arm8_cache_cleanID_E) - -ENTRY(arm8_cache_purgeID) - /* - * ARM810 bug 3 - * - * Clean and invalidate entry will not invalidate the entry - * if the line was already clean. (mcr p15, 0, rd, c7, 15, 1) - * - * Instead of using the clean and invalidate entry operation - * use a separate clean and invalidate entry operations. - * i.e. - * mcr p15, 0, rd, c7, c11, 1 - * mcr p15, 0, rd, c7, c7, 1 - */ - - mov r0, #0x00000000 - - mrs r3, cpsr - orr r2, r3, #(I32_bit | F32_bit) - msr cpsr_fsxc, r2 - -1: mov r2, r0 - mcr p15, 0, r2, c7, c11, 1 - mcr p15, 0, r2, c7, c7, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - mcr p15, 0, r2, c7, c7, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - mcr p15, 0, r2, c7, c7, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - mcr p15, 0, r2, c7, c7, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - mcr p15, 0, r2, c7, c7, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - mcr p15, 0, r2, c7, c7, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - mcr p15, 0, r2, c7, c7, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - mcr p15, 0, r2, c7, c7, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - mcr p15, 0, r2, c7, c7, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - mcr p15, 0, r2, c7, c7, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - mcr p15, 0, r2, c7, c7, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - mcr p15, 0, r2, c7, c7, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - mcr p15, 0, r2, c7, c7, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - mcr p15, 0, r2, c7, c7, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - mcr p15, 0, r2, c7, c7, 1 - add r2, r2, #0x10 - mcr p15, 0, r2, c7, c11, 1 - mcr p15, 0, r2, c7, c7, 1 - - adds r0, r0, #0x04000000 - bne 1b - - msr cpsr_fsxc, r3 - RET -END(arm8_cache_purgeID) - -ENTRY(arm8_cache_purgeID_E) - /* - * ARM810 bug 3 - * - * Clean and invalidate entry will not invalidate the entry - * if the line was already clean. (mcr p15, 0, rd, c7, 15, 1) - * - * Instead of using the clean and invalidate entry operation - * use a separate clean and invalidate entry operations. - * i.e. - * mcr p15, 0, rd, c7, c11, 1 - * mcr p15, 0, rd, c7, c7, 1 - */ - mrs r3, cpsr - orr r2, r3, #(I32_bit | F32_bit) - msr cpsr_fsxc, r2 - mcr p15, 0, r0, c7, c11, 1 /* clean I+D single entry */ - mcr p15, 0, r0, c7, c7, 1 /* flush I+D single entry */ - msr cpsr_fsxc, r3 - RET -END(arm8_cache_purgeID_E) - -/* - * Context switch. - * - * These is the CPU-specific parts of the context switcher cpu_switch() - * These functions actually perform the TTB reload. - * - * NOTE: Special calling convention - * r1, r4-r13 must be preserved - */ -ENTRY(arm8_context_switch) - /* For good measure we will flush the IDC as well */ - mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */ - - /* Write the TTB */ - mcr p15, 0, r0, c2, c0, 0 - - /* If we have updated the TTB we must flush the TLB */ - mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */ - -#if 0 - /* For good measure we will flush the IDC as well */ - mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */ -#endif - - /* Make sure that pipeline is emptied */ - mov r0, r0 - mov r0, r0 - RET -END(arm8_context_switch) - diff --git a/sys/arm/arm/cpufunc_asm_ixp12x0.S b/sys/arm/arm/cpufunc_asm_ixp12x0.S deleted file mode 100644 index 481cf0d..0000000 --- a/sys/arm/arm/cpufunc_asm_ixp12x0.S +++ /dev/null @@ -1,92 +0,0 @@ -/* $NetBSD: cpufunc_asm_ixp12x0.S,v 1.2 2002/08/17 16:36:31 thorpej Exp $ */ - -/*- - * Copyright (c) 2002 Wasabi Systems, Inc. - * All rights reserved. - * - * Written by Jason R. Thorpe for Wasabi Systems, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Wasabi Systems, Inc. - * 4. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include <machine/asm.h> -__FBSDID("$FreeBSD$"); - -/* - * This function is the same as sa110_context_switch for now, the plan - * is to make use of the process id register to avoid cache flushes. - */ -ENTRY(ixp12x0_context_switch) - /* - * CF_CACHE_PURGE_ID will *ALWAYS* be called prior to this. - * Thus the data cache will contain only kernel data and the - * instruction cache will contain only kernel code, and all - * kernel mappings are shared by all processes. - */ - - /* Write the TTB */ - mcr p15, 0, r0, c2, c0, 0 - - /* If we have updated the TTB we must flush the TLB */ - mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */ - - /* Make sure that pipeline is emptied */ - mov r0, r0 - mov r0, r0 - RET -END(ixp12x0_context_switch) - -ENTRY(ixp12x0_drain_readbuf) - mcr p15, 0, r0, c9, c0, 0 /* drain read buffer */ - RET -END(ixp12x0_drain_readbuf) - -/* - * Information for the IXP12X0 cache clean/purge functions: - * - * * Virtual address of the memory region to use - * * Size of memory region - */ - .data - - .global _C_LABEL(ixp12x0_cache_clean_addr) -_C_LABEL(ixp12x0_cache_clean_addr): - .word 0xf0000000 - - .global _C_LABEL(ixp12x0_cache_clean_size) -_C_LABEL(ixp12x0_cache_clean_size): - .word 0x00008000 - - .text - -.Lixp12x0_cache_clean_addr: - .word _C_LABEL(ixp12x0_cache_clean_addr) -.Lixp12x0_cache_clean_size: - .word _C_LABEL(ixp12x0_cache_clean_size) diff --git a/sys/arm/arm/cpufunc_asm_sa1.S b/sys/arm/arm/cpufunc_asm_sa1.S deleted file mode 100644 index 77602b1..0000000 --- a/sys/arm/arm/cpufunc_asm_sa1.S +++ /dev/null @@ -1,337 +0,0 @@ -/* $NetBSD: cpufunc_asm_sa1.S,v 1.8 2002/08/17 16:36:32 thorpej Exp $ */ - -/*- - * Copyright (c) 1997,1998 Mark Brinicombe. - * Copyright (c) 1997 Causality Limited - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Causality Limited. - * 4. The name of Causality Limited may not be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * SA-1 assembly functions for CPU / MMU / TLB specific operations - * - */ - -#include <machine/asm.h> -__FBSDID("$FreeBSD$"); - -.Lblock_userspace_access: - .word _C_LABEL(block_userspace_access) - -/* - * Functions to set the MMU Translation Table Base register - * - * We need to clean and flush the cache as it uses virtual - * addresses that are about to change. - */ -ENTRY(getttb) - mrc p15, 0, r0, c2, c0, 0 -ENTRY(sa1_setttb) -#ifdef CACHE_CLEAN_BLOCK_INTR - mrs r3, cpsr - orr r1, r3, #(I32_bit | F32_bit) - msr cpsr_fsxc, r1 -#else - ldr r3, .Lblock_userspace_access - ldr r2, [r3] - orr r1, r2, #1 - str r1, [r3] -#endif - stmfd sp!, {r0-r3, lr} - bl _C_LABEL(sa1_cache_cleanID) - ldmfd sp!, {r0-r3, lr} - mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */ - mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */ - - /* Write the TTB */ - mcr p15, 0, r0, c2, c0, 0 - - /* If we have updated the TTB we must flush the TLB */ - mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */ - - /* The cleanID above means we only need to flush the I cache here */ - mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */ - - /* Make sure that pipeline is emptied */ - mov r0, r0 - mov r0, r0 -#ifdef CACHE_CLEAN_BLOCK_INTR - msr cpsr_fsxc, r3 -#else - str r2, [r3] -#endif - RET -END(getttb) -END(sa1_setttb) - -/* - * TLB functions - */ -ENTRY(sa1_tlb_flushID_SE) - mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ - mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */ - RET -END(sa1_tlb_flushID_SE) - -/* - * Cache functions - */ -ENTRY(sa1_cache_flushID) - mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */ - RET -END(sa1_cache_flushID) - -ENTRY(sa1_cache_flushI) - mcr p15, 0, r0, c7, c5, 0 /* flush I cache */ - RET -END(sa1_cache_flushI) - -ENTRY(sa1_cache_flushD) - mcr p15, 0, r0, c7, c6, 0 /* flush D cache */ - RET -END(sa1_cache_flushD) - -ENTRY(sa1_cache_flushD_SE) - mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */ - RET -END(sa1_cache_flushD_SE) - -ENTRY(sa1_cache_cleanD_E) - mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */ - RET -END(sa1_cache_cleanD_E) - -/* - * Information for the SA-1 cache clean/purge functions: - * - * * Virtual address of the memory region to use - * * Size of memory region - */ - .data - - .global _C_LABEL(sa1_cache_clean_addr) -_C_LABEL(sa1_cache_clean_addr): - .word 0xf0000000 - - .global _C_LABEL(sa1_cache_clean_size) -_C_LABEL(sa1_cache_clean_size): -#if defined(CPU_SA1100) || defined(CPU_SA1110) - .word 0x00004000 -#else - .word 0x00008000 -#endif - - .text - -.Lsa1_cache_clean_addr: - .word _C_LABEL(sa1_cache_clean_addr) -.Lsa1_cache_clean_size: - .word _C_LABEL(sa1_cache_clean_size) - -#ifdef CACHE_CLEAN_BLOCK_INTR -#define SA1_CACHE_CLEAN_BLOCK \ - mrs r3, cpsr ; \ - orr r0, r3, #(I32_bit | F32_bit) ; \ - msr cpsr_fsxc, r0 - -#define SA1_CACHE_CLEAN_UNBLOCK \ - msr cpsr_fsxc, r3 -#else -#define SA1_CACHE_CLEAN_BLOCK \ - ldr r3, .Lblock_userspace_access ; \ - ldr ip, [r3] ; \ - orr r0, ip, #1 ; \ - str r0, [r3] - -#define SA1_CACHE_CLEAN_UNBLOCK \ - str ip, [r3] -#endif /* CACHE_CLEAN_BLOCK_INTR */ - -#ifdef DOUBLE_CACHE_CLEAN_BANK -#define SA1_DOUBLE_CACHE_CLEAN_BANK \ - eor r0, r0, r1 ; \ - str r0, [r2] -#else -#define SA1_DOUBLE_CACHE_CLEAN_BANK /* nothing */ -#endif /* DOUBLE_CACHE_CLEAN_BANK */ - -#define SA1_CACHE_CLEAN_PROLOGUE \ - SA1_CACHE_CLEAN_BLOCK ; \ - ldr r2, .Lsa1_cache_clean_addr ; \ - ldmia r2, {r0, r1} ; \ - SA1_DOUBLE_CACHE_CLEAN_BANK - -#define SA1_CACHE_CLEAN_EPILOGUE \ - SA1_CACHE_CLEAN_UNBLOCK - -ENTRY_NP(sa1_cache_syncI) -ENTRY_NP(sa1_cache_purgeID) - mcr p15, 0, r0, c7, c5, 0 /* flush I cache (D cleaned below) */ -ENTRY_NP(sa1_cache_cleanID) -ENTRY_NP(sa1_cache_purgeD) -ENTRY(sa1_cache_cleanD) - SA1_CACHE_CLEAN_PROLOGUE - -1: ldr r2, [r0], #32 - subs r1, r1, #32 - bne 1b - - mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ - - SA1_CACHE_CLEAN_EPILOGUE - RET -END(sa1_cache_syncI) -END(sa1_cache_purgeID) -END(sa1_cache_cleanID) -END(sa1_cache_purgeD) -END(sa1_cache_cleanD) - -ENTRY(sa1_cache_purgeID_E) - mcr p15, 0, r0, c7, c10, 1 /* clean dcache entry */ - mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ - mcr p15, 0, r0, c7, c5, 0 /* flush I cache */ - mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */ - RET -END(sa1_cache_purgeID_E) - -ENTRY(sa1_cache_purgeD_E) - mcr p15, 0, r0, c7, c10, 1 /* clean dcache entry */ - mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ - mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */ - RET -END(sa1_cache_purgeD_E) - -/* - * Soft functions - */ -/* sa1_cache_syncI is identical to sa1_cache_purgeID */ - -ENTRY(sa1_cache_cleanID_rng) -ENTRY(sa1_cache_cleanD_rng) - cmp r1, #0x4000 - bcs _C_LABEL(sa1_cache_cleanID) - - and r2, r0, #0x1f - add r1, r1, r2 - bic r0, r0, #0x1f - -1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */ - add r0, r0, #32 - subs r1, r1, #32 - bhi 1b - - mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ - RET -END(sa1_cache_cleanID_rng) -END(sa1_cache_cleanD_rng) - -ENTRY(sa1_cache_purgeID_rng) - cmp r1, #0x4000 - bcs _C_LABEL(sa1_cache_purgeID) - - and r2, r0, #0x1f - add r1, r1, r2 - bic r0, r0, #0x1f - -1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */ - mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */ - add r0, r0, #32 - subs r1, r1, #32 - bhi 1b - - mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ - mcr p15, 0, r0, c7, c5, 0 /* flush I cache */ - RET -END(sa1_cache_purgeID_rng) - -ENTRY(sa1_cache_purgeD_rng) - cmp r1, #0x4000 - bcs _C_LABEL(sa1_cache_purgeD) - - and r2, r0, #0x1f - add r1, r1, r2 - bic r0, r0, #0x1f - -1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */ - mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */ - add r0, r0, #32 - subs r1, r1, #32 - bhi 1b - - mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ - RET -END(sa1_cache_purgeD_rng) - -ENTRY(sa1_cache_syncI_rng) - cmp r1, #0x4000 - bcs _C_LABEL(sa1_cache_syncI) - - and r2, r0, #0x1f - add r1, r1, r2 - bic r0, r0, #0x1f - -1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */ - add r0, r0, #32 - subs r1, r1, #32 - bhi 1b - - mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ - mcr p15, 0, r0, c7, c5, 0 /* flush I cache */ - - RET -END(sa1_cache_syncI_rng) - -/* - * Context switch. - * - * These is the CPU-specific parts of the context switcher cpu_switch() - * These functions actually perform the TTB reload. - * - * NOTE: Special calling convention - * r1, r4-r13 must be preserved - */ -#if defined(CPU_SA110) -ENTRY(sa110_context_switch) - /* - * CF_CACHE_PURGE_ID will *ALWAYS* be called prior to this. - * Thus the data cache will contain only kernel data and the - * instruction cache will contain only kernel code, and all - * kernel mappings are shared by all processes. - */ - - /* Write the TTB */ - mcr p15, 0, r0, c2, c0, 0 - - /* If we have updated the TTB we must flush the TLB */ - mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */ - - /* Make sure that pipeline is emptied */ - mov r0, r0 - mov r0, r0 - RET -END(sa110_context_switch) -#endif diff --git a/sys/arm/arm/cpufunc_asm_sa11x0.S b/sys/arm/arm/cpufunc_asm_sa11x0.S deleted file mode 100644 index ffd214e..0000000 --- a/sys/arm/arm/cpufunc_asm_sa11x0.S +++ /dev/null @@ -1,128 +0,0 @@ -/* $NetBSD: cpufunc_asm_sa11x0.S,v 1.3 2002/08/17 16:36:32 thorpej Exp $ */ - -/*- - * Copyright (c) 2002 Wasabi Systems, Inc. - * All rights reserved. - * - * Written by Jason R. Thorpe for Wasabi Systems, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Wasabi Systems, Inc. - * 4. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include <machine/asm.h> -__FBSDID("$FreeBSD$"); - - .data - .global _C_LABEL(sa11x0_idle_mem) -_C_LABEL(sa11x0_idle_mem): - .word 0 - - .text - - .align 5 - - /* We're now 32-byte aligned */ - -.Lsa11x0_idle_mem: - .word _C_LABEL(sa11x0_idle_mem) /* 1 */ - -/* - * sa11x0_cpusleep - * - * This is called when there is nothing on any of the run queues. - * We go into IDLE mode so that any IRQ or FIQ will awaken us. - */ -ENTRY(sa11x0_cpu_sleep) - ldr r1, .Lsa11x0_idle_mem /* get address of... */ /* 2 */ - nop /* 3 */ - ldr r1, [r1] /* ...non-cacheable page */ /* 4 */ - nop /* 5 */ - - /* - * SA-1110 manual, 9.5.2.1 (Entering Idle Mode) says that - * to enter idle mode: - * - * * Disable clock switching - * * Issue load from non-cacheable address - * * Issue "wait for interrupt" - * - * The 3-insn sequence must reside in the first 3 words - * of a cache line. - * - * We must disable interrupts in the CPSR so that we can - * re-enable clock switching before servicing interrupts. - */ - - mrs r3, cpsr /* 6 */ - orr r2, r3, #(I32_bit|F32_bit) /* 7 */ - msr cpsr_fsxc, r2 /* 8 */ - - /* We're now 32-byte aligned */ - - mcr p15, 0, r0, c15, c2, 2 /* disable clock switching */ - ldr r0, [r1] /* load from non-cacheable address */ - mcr p15, 0, r0, c15, c8, 2 /* wait for interrupt */ - - mcr p15, 0, r0, c15, c1, 2 /* re-enable clock switching */ - - /* Restore interrupts (which will cause them to be serviced). */ - msr cpsr_fsxc, r3 - RET -END(sa11x0_cpu_sleep) - -/* - * This function is the same as sa110_context_switch for now, the plan - * is to make use of the process id register to avoid cache flushes. - */ -ENTRY(sa11x0_context_switch) - /* - * CF_CACHE_PURGE_ID will *ALWAYS* be called prior to this. - * Thus the data cache will contain only kernel data and the - * instruction cache will contain only kernel code, and all - * kernel mappings are shared by all processes. - */ - - /* Write the TTB */ - mcr p15, 0, r0, c2, c0, 0 - - /* If we have updated the TTB we must flush the TLB */ - mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */ - - /* Make sure that pipeline is emptied */ - mov r0, r0 - mov r0, r0 - RET -END(sa11x0_context_switch) - -ENTRY(sa11x0_drain_readbuf) - mcr p15, 0, r0, c9, c0, 0 /* drain read buffer */ - RET -END(sa11x0_drain_readbuf) - diff --git a/sys/arm/arm/elf_trampoline.c b/sys/arm/arm/elf_trampoline.c index 9371a6d..559b992 100644 --- a/sys/arm/arm/elf_trampoline.c +++ b/sys/arm/arm/elf_trampoline.c @@ -56,13 +56,7 @@ extern void do_call(void *, void *, void *, int); #define GZ_HEAD 0xa -#ifdef CPU_ARM7TDMI -#define cpu_idcache_wbinv_all arm7tdmi_cache_flushID -extern void arm7tdmi_cache_flushID(void); -#elif defined(CPU_ARM8) -#define cpu_idcache_wbinv_all arm8_cache_purgeID -extern void arm8_cache_purgeID(void); -#elif defined(CPU_ARM9) +#if defined(CPU_ARM9) #define cpu_idcache_wbinv_all arm9_idcache_wbinv_all extern void arm9_idcache_wbinv_all(void); #elif defined(CPU_FA526) || defined(CPU_FA626TE) @@ -76,10 +70,6 @@ extern void armv5_ec_idcache_wbinv_all(void); extern void arm10_idcache_wbinv_all(void); #elif defined(CPU_ARM1136) || defined(CPU_ARM1176) #define cpu_idcache_wbinv_all armv6_idcache_wbinv_all -#elif defined(CPU_SA110) || defined(CPU_SA1110) || defined(CPU_SA1100) || \ - defined(CPU_IXP12X0) -#define cpu_idcache_wbinv_all sa1_cache_purgeID -extern void sa1_cache_purgeID(void); #elif defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ defined(CPU_XSCALE_80219) diff --git a/sys/arm/arm/identcpu.c b/sys/arm/arm/identcpu.c index 6f106ab..938f321 100644 --- a/sys/arm/arm/identcpu.c +++ b/sys/arm/arm/identcpu.c @@ -69,36 +69,6 @@ static const char * const generic_steppings[16] = { "rev 12", "rev 13", "rev 14", "rev 15", }; -static const char * const sa110_steppings[16] = { - "rev 0", "step J", "step K", "step S", - "step T", "rev 5", "rev 6", "rev 7", - "rev 8", "rev 9", "rev 10", "rev 11", - "rev 12", "rev 13", "rev 14", "rev 15", -}; - -static const char * const sa1100_steppings[16] = { - "rev 0", "step B", "step C", "rev 3", - "rev 4", "rev 5", "rev 6", "rev 7", - "step D", "step E", "rev 10" "step G", - "rev 12", "rev 13", "rev 14", "rev 15", -}; - -static const char * const sa1110_steppings[16] = { - "step A-0", "rev 1", "rev 2", "rev 3", - "step B-0", "step B-1", "step B-2", "step B-3", - "step B-4", "step B-5", "rev 10", "rev 11", - "rev 12", "rev 13", "rev 14", "rev 15", -}; - -static const char * const ixp12x0_steppings[16] = { - "(IXP1200 step A)", "(IXP1200 step B)", - "rev 2", "(IXP1200 step C)", - "(IXP1200 step D)", "(IXP1240/1250 step A)", - "(IXP1240 step B)", "(IXP1250 step B)", - "rev 8", "rev 9", "rev 10", "rev 11", - "rev 12", "rev 13", "rev 14", "rev 15", -}; - static const char * const xscale_steppings[16] = { "step A-0", "step A-1", "step B-0", "step C-0", "step D-0", "rev 5", "rev 6", "rev 7", @@ -168,43 +138,6 @@ struct cpuidtab { }; const struct cpuidtab cpuids[] = { - { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2", - generic_steppings }, - { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250", - generic_steppings }, - - { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3", - generic_steppings }, - - { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600", - generic_steppings }, - { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610", - generic_steppings }, - { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620", - generic_steppings }, - - { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700", - generic_steppings }, - { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710", - generic_steppings }, - { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500", - generic_steppings }, - { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a", - generic_steppings }, - { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE", - generic_steppings }, - { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T", - generic_steppings }, - { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T", - generic_steppings }, - { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)", - generic_steppings }, - { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)", - generic_steppings }, - - { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810", - generic_steppings }, - { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", generic_steppings }, { CPU_ID_ARM920T_ALT, CPU_CLASS_ARM9TDMI, "ARM920T", @@ -257,16 +190,6 @@ const struct cpuidtab cpuids[] = { { CPU_ID_KRAIT, CPU_CLASS_KRAIT, "Krait", generic_steppings }, - { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", - sa110_steppings }, - { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100", - sa1100_steppings }, - { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110", - sa1110_steppings }, - - { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200", - ixp12x0_steppings }, - { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", xscale_steppings }, @@ -342,13 +265,6 @@ struct cpu_classtab { const struct cpu_classtab cpu_classes[] = { { "unknown", NULL }, /* CPU_CLASS_NONE */ - { "ARM2", "CPU_ARM2" }, /* CPU_CLASS_ARM2 */ - { "ARM2as", "CPU_ARM250" }, /* CPU_CLASS_ARM2AS */ - { "ARM3", "CPU_ARM3" }, /* CPU_CLASS_ARM3 */ - { "ARM6", "CPU_ARM6" }, /* CPU_CLASS_ARM6 */ - { "ARM7", "CPU_ARM7" }, /* CPU_CLASS_ARM7 */ - { "ARM7TDMI", "CPU_ARM7TDMI" }, /* CPU_CLASS_ARM7TDMI */ - { "ARM8", "CPU_ARM8" }, /* CPU_CLASS_ARM8 */ { "ARM9TDMI", "CPU_ARM9TDMI" }, /* CPU_CLASS_ARM9TDMI */ { "ARM9E-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9ES */ { "ARM9EJ-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9EJS */ @@ -356,7 +272,6 @@ const struct cpu_classtab cpu_classes[] = { { "ARM10EJ", "CPU_ARM10" }, /* CPU_CLASS_ARM10EJ */ { "Cortex-A", "CPU_CORTEXA" }, /* CPU_CLASS_CORTEXA */ { "Krait", "CPU_KRAIT" }, /* CPU_CLASS_KRAIT */ - { "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */ { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */ { "ARM11J", "CPU_ARM11" }, /* CPU_CLASS_ARM11J */ { "Marvell", "CPU_MARVELL" }, /* CPU_CLASS_MARVELL */ @@ -495,18 +410,11 @@ identify_arm_cpu(void) printf(" Little-endian"); switch (cpu_class) { - case CPU_CLASS_ARM6: - case CPU_CLASS_ARM7: - case CPU_CLASS_ARM7TDMI: - case CPU_CLASS_ARM8: - print_enadis(ctrl & CPU_CONTROL_IDC_ENABLE, "IDC"); - break; case CPU_CLASS_ARM9TDMI: case CPU_CLASS_ARM9ES: case CPU_CLASS_ARM9EJS: case CPU_CLASS_ARM10E: case CPU_CLASS_ARM10EJ: - case CPU_CLASS_SA1: case CPU_CLASS_XSCALE: case CPU_CLASS_ARM11J: case CPU_CLASS_MARVELL: diff --git a/sys/arm/arm/pmap.c b/sys/arm/arm/pmap.c index 574f2ea..046c66b 100644 --- a/sys/arm/arm/pmap.c +++ b/sys/arm/arm/pmap.c @@ -458,7 +458,7 @@ kernel_pt_lookup(vm_paddr_t pa) return (0); } -#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 +#if ARM_MMU_GENERIC != 0 void pmap_pte_init_generic(void) { @@ -500,23 +500,6 @@ pmap_pte_init_generic(void) pmap_zero_page_func = pmap_zero_page_generic; } -#if defined(CPU_ARM8) -void -pmap_pte_init_arm8(void) -{ - - /* - * ARM8 is compatible with generic, but we need to use - * the page tables uncached. - */ - pmap_pte_init_generic(); - - pte_l1_s_cache_mode_pt = 0; - pte_l2_l_cache_mode_pt = 0; - pte_l2_s_cache_mode_pt = 0; -} -#endif /* CPU_ARM8 */ - #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) void pmap_pte_init_arm9(void) @@ -537,7 +520,7 @@ pmap_pte_init_arm9(void) pte_l2_s_cache_mode_pt = L2_C; } #endif /* CPU_ARM9 */ -#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ +#endif /* ARM_MMU_GENERIC != 0 */ #if defined(CPU_ARM10) void @@ -561,27 +544,6 @@ pmap_pte_init_arm10(void) } #endif /* CPU_ARM10 */ -#if ARM_MMU_SA1 == 1 -void -pmap_pte_init_sa1(void) -{ - - /* - * The StrongARM SA-1 cache does not have a write-through - * mode. So, do the generic initialization, then reset - * the page table cache mode to B=1,C=1, and note that - * the PTEs need to be sync'd. - */ - pmap_pte_init_generic(); - - pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; - pte_l2_l_cache_mode_pt = L2_B|L2_C; - pte_l2_s_cache_mode_pt = L2_B|L2_C; - - pmap_needs_pte_sync = 1; -} -#endif /* ARM_MMU_SA1 == 1*/ - #if ARM_MMU_XSCALE == 1 #if (ARM_NMMUS > 1) || defined (CPU_XSCALE_CORE3) static u_int xscale_use_minidata; @@ -1972,34 +1934,6 @@ pmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user) rv = 1; } -#ifdef CPU_SA110 - /* - * There are bugs in the rev K SA110. This is a check for one - * of them. - */ - if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && - curcpu()->ci_arm_cpurev < 3) { - /* Always current pmap */ - if (l2pte_valid(pte)) { - extern int kernel_debug; - if (kernel_debug & 1) { - struct proc *p = curlwp->l_proc; - printf("prefetch_abort: page is already " - "mapped - pte=%p *pte=%08x\n", ptep, pte); - printf("prefetch_abort: pc=%08lx proc=%p " - "process=%s\n", va, p, p->p_comm); - printf("prefetch_abort: far=%08x fs=%x\n", - cpu_faultaddress(), cpu_faultstatus()); - } -#ifdef DDB - if (kernel_debug & 2) - Debugger(); -#endif - rv = 1; - } - } -#endif /* CPU_SA110 */ - #ifdef DEBUG /* * If 'rv == 0' at this point, it generally indicates that there is a @@ -3978,7 +3912,7 @@ pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) * StrongARM accesses to non-cached pages are non-burst making writing * _any_ bulk data very slow. */ -#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_CORE3) +#if ARM_MMU_GENERIC != 0 || defined(CPU_XSCALE_CORE3) void pmap_zero_page_generic(vm_paddr_t phys, int off, int size) { @@ -4005,7 +3939,7 @@ pmap_zero_page_generic(vm_paddr_t phys, int off, int size) mtx_unlock(&cmtx); } -#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ +#endif /* ARM_MMU_GENERIC != 0 */ #if ARM_MMU_XSCALE == 1 void @@ -4221,7 +4155,7 @@ pmap_clean_page(struct pv_entry *pv, boolean_t is_src) * hook points. The same comment regarding cachability as in * pmap_zero_page also applies here. */ -#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined (CPU_XSCALE_CORE3) +#if ARM_MMU_GENERIC != 0 || defined (CPU_XSCALE_CORE3) void pmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst) { @@ -4286,7 +4220,7 @@ pmap_copy_page_offs_generic(vm_paddr_t a_phys, vm_offset_t a_offs, cpu_l2cache_inv_range(csrcp + a_offs, cnt); cpu_l2cache_wbinv_range(cdstp + b_offs, cnt); } -#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ +#endif /* ARM_MMU_GENERIC != 0 */ #if ARM_MMU_XSCALE == 1 void diff --git a/sys/arm/arm/trap.c b/sys/arm/arm/trap.c index 70681d3..32624e3 100644 --- a/sys/arm/arm/trap.c +++ b/sys/arm/arm/trap.c @@ -136,11 +136,6 @@ extern char fusubailout[]; int last_fault_code; /* For the benefit of pmap_fault_fixup() */ #endif -#if defined(CPU_ARM7TDMI) -/* These CPUs may need data/prefetch abort fixups */ -#define CPU_ABORT_FIXUP_REQUIRED -#endif - struct ksig { int signb; u_long code; @@ -200,37 +195,6 @@ call_trapsignal(struct thread *td, int sig, u_long code) trapsignal(td, &ksi); } -static __inline int -data_abort_fixup(struct trapframe *tf, u_int fsr, u_int far, struct thread *td, - struct ksig *ksig) -{ -#ifdef CPU_ABORT_FIXUP_REQUIRED - int error; - - /* Call the cpu specific data abort fixup routine */ - error = cpu_dataabt_fixup(tf); - if (__predict_true(error != ABORT_FIXUP_FAILED)) - return (error); - - /* - * Oops, couldn't fix up the instruction - */ - printf("data_abort_fixup: fixup for %s mode data abort failed.\n", - TRAP_USERMODE(tf) ? "user" : "kernel"); - printf("pc = 0x%08x, opcode 0x%08x, insn = ", tf->tf_pc, - *((u_int *)tf->tf_pc)); - disassemble(tf->tf_pc); - - /* Die now if this happened in kernel mode */ - if (!TRAP_USERMODE(tf)) - dab_fatal(tf, fsr, far, td, NULL, ksig); - - return (error); -#else - return (ABORT_FIXUP_OK); -#endif /* CPU_ABORT_FIXUP_REQUIRED */ -} - void data_abort_handler(struct trapframe *tf) { @@ -340,19 +304,6 @@ data_abort_handler(struct trapframe *tf) dab_fatal(tf, fsr, far, td, &ksig); } - /* See if the cpu state needs to be fixed up */ - switch (data_abort_fixup(tf, fsr, far, td, &ksig)) { - case ABORT_FIXUP_RETURN: - return; - case ABORT_FIXUP_FAILED: - /* Deliver a SIGILL to the process */ - ksig.signb = SIGILL; - ksig.code = 0; - goto do_trapsignal; - default: - break; - } - va = trunc_page((vm_offset_t)far); /* @@ -566,9 +517,6 @@ dab_align(struct trapframe *tf, u_int fsr, u_int far, struct thread *td, /* pcb_onfault *must* be NULL at this point */ - /* See if the cpu state needs to be fixed up */ - (void) data_abort_fixup(tf, fsr, far, td, ksig); - /* Deliver a bus error signal to the process */ ksig->code = 0; ksig->signb = SIGBUS; @@ -657,9 +605,6 @@ dab_buserr(struct trapframe *tf, u_int fsr, u_int far, struct thread *td, return (0); } - /* See if the cpu state needs to be fixed up */ - (void) data_abort_fixup(tf, fsr, far, td, ksig); - /* * At this point, if the fault happened in kernel mode, we're toast */ @@ -674,37 +619,6 @@ dab_buserr(struct trapframe *tf, u_int fsr, u_int far, struct thread *td, return (1); } -static __inline int -prefetch_abort_fixup(struct trapframe *tf, struct ksig *ksig) -{ -#ifdef CPU_ABORT_FIXUP_REQUIRED - int error; - - /* Call the cpu specific prefetch abort fixup routine */ - error = cpu_prefetchabt_fixup(tf); - if (__predict_true(error != ABORT_FIXUP_FAILED)) - return (error); - - /* - * Oops, couldn't fix up the instruction - */ - printf( - "prefetch_abort_fixup: fixup for %s mode prefetch abort failed.\n", - TRAP_USERMODE(tf) ? "user" : "kernel"); - printf("pc = 0x%08x, opcode 0x%08x, insn = ", tf->tf_pc, - *((u_int *)tf->tf_pc)); - disassemble(tf->tf_pc); - - /* Die now if this happened in kernel mode */ - if (!TRAP_USERMODE(tf)) - dab_fatal(tf, 0, tf->tf_pc, NULL, ksig); - - return (error); -#else - return (ABORT_FIXUP_OK); -#endif /* CPU_ABORT_FIXUP_REQUIRED */ -} - /* * void prefetch_abort_handler(struct trapframe *tf) * @@ -753,20 +667,6 @@ prefetch_abort_handler(struct trapframe *tf) enable_interrupts(F32_bit); } - /* See if the cpu state needs to be fixed up */ - switch (prefetch_abort_fixup(tf, &ksig)) { - case ABORT_FIXUP_RETURN: - return; - case ABORT_FIXUP_FAILED: - /* Deliver a SIGILL to the process */ - ksig.signb = SIGILL; - ksig.code = 0; - td->td_frame = tf; - goto do_trapsignal; - default: - break; - } - /* Prefetch aborts cannot happen in kernel mode */ if (__predict_false(!TRAP_USERMODE(tf))) dab_fatal(tf, 0, tf->tf_pc, NULL, &ksig); diff --git a/sys/arm/conf/NOTES b/sys/arm/conf/NOTES index 50ea59e..ad608d4 100644 --- a/sys/arm/conf/NOTES +++ b/sys/arm/conf/NOTES @@ -5,8 +5,6 @@ machine arm cpu CPU_ARM9 cpu CPU_ARM9E cpu CPU_FA526 -cpu CPU_SA1100 -cpu CPU_SA1110 cpu CPU_XSCALE_80219 cpu CPU_XSCALE_80321 cpu CPU_XSCALE_81342 @@ -22,7 +20,6 @@ files "../mv/kirkwood/files.kirkwood" files "../mv/orion/files.db88f5xxx" files "../mv/orion/files.ts7800" files "../s3c2xx0/files.s3c2xx0" -files "../sa11x0/files.sa11x0" files "../xscale/i80321/files.ep80219" files "../xscale/i80321/files.i80219" files "../xscale/i80321/files.i80321" diff --git a/sys/arm/conf/SIMICS b/sys/arm/conf/SIMICS deleted file mode 100644 index 6ea8e50..0000000 --- a/sys/arm/conf/SIMICS +++ /dev/null @@ -1,73 +0,0 @@ -# SIMICS -- Custom kernel configuration file for FreeBSD/arm on Simics SA1110 -# -# For more information on this file, please read the handbook section on -# Kernel Configuration Files: -# -# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html -# -# The handbook is also available locally in /usr/share/doc/handbook -# if you've installed the doc distribution, otherwise always see the -# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the -# latest information. -# -# An exhaustive list of options and more detailed explanations of the -# device lines is also present in the ../../conf/NOTES and NOTES files. -# If you are in doubt as to the purpose or necessity of a line, check first -# in NOTES. -# -# $FreeBSD$ - -ident SIMICS - -options KERNPHYSADDR=0xc0000000 -options KERNVIRTADDR=0xc0000000 -options PHYSADDR=0xc0000000 -include "../sa11x0/std.sa11x0" -makeoptions MODULES_OVERRIDE="" - -makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols -makeoptions CONF_CFLAGS=-mcpu=strongarm -options DDB -options KDB - -options SCHED_4BSD #4BSD scheduler -options INET #InterNETworking -options INET6 #IPv6 communications protocols -options FFS #Berkeley Fast Filesystem -options SOFTUPDATES #Enable FFS soft updates support -options UFS_ACL #Support for access control lists -options UFS_DIRHASH #Improve performance on big directories -options MD_ROOT #MD is a potential root device -options ROOTDEVNAME=\"ufs:md0\" -options NFSCL #New Network Filesystem Client -options NFSD #New Network Filesystem Server -options NFSLOCKD #Network Lock Manager -options NFS_ROOT #NFS usable as /, requires NFSCL -options GEOM_PART_BSD #BSD partition scheme -options GEOM_PART_MBR #MBR partition scheme -options TMPFS #Efficient memory filesystem -#options MSDOSFS #MSDOS Filesystem -options CD9660 #ISO 9660 Filesystem -#options PROCFS #Process filesystem (requires PSEUDOFS) -options PSEUDOFS #Pseudo-filesystem framework -#options KTRACE #ktrace(1) support -options SYSVSHM #SYSV-style shared memory -options SYSVMSG #SYSV-style message queues -options SYSVSEM #SYSV-style semaphores -options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions -device loop -device ether -device saip -device assabet -#device saarm -device rl -device uart - -# Debugging for use in -current -#options DEADLKRES #Enable the deadlock resolver -#options INVARIANTS #Enable calls of extra sanity checking -#options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS -#options WITNESS #Enable checks to detect deadlocks and cycles -#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed - -device md diff --git a/sys/arm/include/armreg.h b/sys/arm/include/armreg.h index 7cb68d0..d892f21 100644 --- a/sys/arm/include/armreg.h +++ b/sys/arm/include/armreg.h @@ -73,17 +73,7 @@ #define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) #define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) -/* On ARM3 and ARM6, this byte holds the foundry ID. */ -#define CPU_ID_FOUNDRY_MASK 0x00ff0000 -#define CPU_ID_FOUNDRY_VLSI 0x00560000 - -/* On ARM7 it holds the architecture and variant (sub-model) */ -#define CPU_ID_7ARCH_MASK 0x00800000 -#define CPU_ID_7ARCH_V3 0x00000000 -#define CPU_ID_7ARCH_V4T 0x00800000 -#define CPU_ID_7VARIANT_MASK 0x007f0000 - -/* On more recent ARMs, it does the same, but in a different format */ +/* On recent ARMs this byte holds the architecture and variant (sub-model) */ #define CPU_ID_ARCH_MASK 0x000f0000 #define CPU_ID_ARCH_V3 0x00000000 #define CPU_ID_ARCH_V4 0x00010000 @@ -110,29 +100,7 @@ /* Individual CPUs are probably best IDed by everything but the revision. */ #define CPU_ID_CPU_MASK 0xfffffff0 -/* Fake CPU IDs for ARMs without CP15 */ -#define CPU_ID_ARM2 0x41560200 -#define CPU_ID_ARM250 0x41560250 - -/* Pre-ARM7 CPUs -- [15:12] == 0 */ -#define CPU_ID_ARM3 0x41560300 -#define CPU_ID_ARM600 0x41560600 -#define CPU_ID_ARM610 0x41560610 -#define CPU_ID_ARM620 0x41560620 - -/* ARM7 CPUs -- [15:12] == 7 */ -#define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */ -#define CPU_ID_ARM710 0x41007100 -#define CPU_ID_ARM7500 0x41027100 -#define CPU_ID_ARM710A 0x41047100 /* inc ARM7100 */ -#define CPU_ID_ARM7500FE 0x41077100 -#define CPU_ID_ARM710T 0x41807100 -#define CPU_ID_ARM720T 0x41807200 -#define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ -#define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ - -/* Post-ARM7 CPUs */ -#define CPU_ID_ARM810 0x41018100 +/* ARM9 and later CPUs */ #define CPU_ID_ARM920T 0x41129200 #define CPU_ID_ARM920T_ALT 0x41009200 #define CPU_ID_ARM922T 0x41029220 @@ -156,8 +124,6 @@ #define CPU_ID_CORTEXA9R2 0x412fc090 #define CPU_ID_CORTEXA9R3 0x413fc090 #define CPU_ID_CORTEXA15 0x410fc0f0 -#define CPU_ID_SA110 0x4401a100 -#define CPU_ID_SA1100 0x4401a110 #define CPU_ID_KRAIT 0x510f06f0 /* Snapdragon S4 Pro/APQ8064 */ #define CPU_ID_TI925T 0x54029250 #define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */ @@ -181,8 +147,6 @@ #define CPU_ID_FA526 0x66015260 #define CPU_ID_FA626TE 0x66056260 -#define CPU_ID_SA1110 0x6901b110 -#define CPU_ID_IXP1200 0x6901c120 #define CPU_ID_80200 0x69052000 #define CPU_ID_PXA250 0x69052100 /* sans core revision */ #define CPU_ID_PXA210 0x69052120 @@ -207,18 +171,6 @@ #define CPU_ID_IXP435 0x69054040 #define CPU_ID_IXP465 0x69054200 -/* ARM3-specific coprocessor 15 registers */ -#define ARM3_CP15_FLUSH 1 -#define ARM3_CP15_CONTROL 2 -#define ARM3_CP15_CACHEABLE 3 -#define ARM3_CP15_UPDATEABLE 4 -#define ARM3_CP15_DISRUPTIVE 5 - -/* ARM3 Control register bits */ -#define ARM3_CTL_CACHE_ON 0x00000001 -#define ARM3_CTL_SHARED 0x00000002 -#define ARM3_CTL_MONITOR 0x00000004 - /* CPUID registers */ #define ARM_PFR0_ARM_ISA_MASK 0x0000000f diff --git a/sys/arm/include/cpuconf.h b/sys/arm/include/cpuconf.h index 0c2faa3..b7cad0d 100644 --- a/sys/arm/include/cpuconf.h +++ b/sys/arm/include/cpuconf.h @@ -50,15 +50,11 @@ /* * Step 1: Count the number of CPU types configured into the kernel. */ -#define CPU_NTYPES (defined(CPU_ARM7TDMI) + \ - defined(CPU_ARM8) + defined(CPU_ARM9) + \ +#define CPU_NTYPES (defined(CPU_ARM9) + \ defined(CPU_ARM9E) + \ defined(CPU_ARM10) + \ defined(CPU_ARM1136) + \ defined(CPU_ARM1176) + \ - defined(CPU_SA110) + defined(CPU_SA1100) + \ - defined(CPU_SA1110) + \ - defined(CPU_IXP12X0) + \ defined(CPU_XSCALE_80200) + \ defined(CPU_XSCALE_80321) + \ defined(CPU_XSCALE_PXA2X0) + \ @@ -72,9 +68,7 @@ /* * Step 2: Determine which ARM architecture versions are configured. */ -#if (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \ - defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ - defined(CPU_IXP12X0) || defined(CPU_FA526)) +#if defined(CPU_ARM9) || defined(CPU_FA526) #define ARM_ARCH_4 1 #else #define ARM_ARCH_4 0 @@ -123,27 +117,17 @@ * ARM_MMU_MEMC Prehistoric, external memory controller * and MMU for ARMv2 CPUs. * - * ARM_MMU_GENERIC Generic ARM MMU, compatible with ARM6. + * ARM_MMU_GENERIC Generic ARM MMU, compatible with ARMv4 and v5. * * ARM_MMU_V6 ARMv6 MMU. * * ARM_MMU_V7 ARMv7 MMU. * - * ARM_MMU_SA1 StrongARM SA-1 MMU. Compatible with generic - * ARM MMU, but has no write-through cache mode. - * * ARM_MMU_XSCALE XScale MMU. Compatible with generic ARM * MMU, but also has several extensions which * require different PTE layout to use. */ -#if (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)) -#define ARM_MMU_MEMC 1 -#else -#define ARM_MMU_MEMC 0 -#endif - -#if (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \ - defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) || \ +#if (defined(CPU_ARM9) || defined(CPU_ARM9E) || \ defined(CPU_ARM10) || defined(CPU_FA526) || \ defined(CPU_FA626TE)) #define ARM_MMU_GENERIC 1 @@ -163,13 +147,6 @@ #define ARM_MMU_V7 0 #endif -#if (defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||\ - defined(CPU_IXP12X0)) -#define ARM_MMU_SA1 1 -#else -#define ARM_MMU_SA1 0 -#endif - #if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)) @@ -178,8 +155,8 @@ #define ARM_MMU_XSCALE 0 #endif -#define ARM_NMMUS (ARM_MMU_MEMC + ARM_MMU_GENERIC + ARM_MMU_V6 + \ - ARM_MMU_V7 + ARM_MMU_SA1 + ARM_MMU_XSCALE) +#define ARM_NMMUS (ARM_MMU_GENERIC + ARM_MMU_V6 + \ + ARM_MMU_V7 + ARM_MMU_XSCALE) #if ARM_NMMUS == 0 && !defined(KLD_MODULE) && defined(_KERNEL) #error ARM_NMMUS is 0 #endif diff --git a/sys/arm/include/cpufunc.h b/sys/arm/include/cpufunc.h index 68b15f5..49c08a3 100644 --- a/sys/arm/include/cpufunc.h +++ b/sys/arm/include/cpufunc.h @@ -284,63 +284,6 @@ u_int cpufunc_faultstatus (void); u_int cpufunc_faultaddress (void); u_int cpu_pfr (int); -#ifdef CPU_ARM3 -u_int arm3_control (u_int clear, u_int bic); -void arm3_cache_flush (void); -#endif /* CPU_ARM3 */ - -#if defined(CPU_ARM6) || defined(CPU_ARM7) -void arm67_setttb (u_int ttb); -void arm67_tlb_flush (void); -void arm67_tlb_purge (u_int va); -void arm67_cache_flush (void); -void arm67_context_switch (void); -#endif /* CPU_ARM6 || CPU_ARM7 */ - -#ifdef CPU_ARM6 -void arm6_setup (char *string); -#endif /* CPU_ARM6 */ - -#ifdef CPU_ARM7 -void arm7_setup (char *string); -#endif /* CPU_ARM7 */ - -#ifdef CPU_ARM7TDMI -int arm7_dataabt_fixup (void *arg); -void arm7tdmi_setup (char *string); -void arm7tdmi_setttb (u_int ttb); -void arm7tdmi_tlb_flushID (void); -void arm7tdmi_tlb_flushID_SE (u_int va); -void arm7tdmi_cache_flushID (void); -void arm7tdmi_context_switch (void); -#endif /* CPU_ARM7TDMI */ - -#ifdef CPU_ARM8 -void arm8_setttb (u_int ttb); -void arm8_tlb_flushID (void); -void arm8_tlb_flushID_SE (u_int va); -void arm8_cache_flushID (void); -void arm8_cache_flushID_E (u_int entry); -void arm8_cache_cleanID (void); -void arm8_cache_cleanID_E (u_int entry); -void arm8_cache_purgeID (void); -void arm8_cache_purgeID_E (u_int entry); - -void arm8_cache_syncI (void); -void arm8_cache_cleanID_rng (vm_offset_t start, vm_size_t end); -void arm8_cache_cleanD_rng (vm_offset_t start, vm_size_t end); -void arm8_cache_purgeID_rng (vm_offset_t start, vm_size_t end); -void arm8_cache_purgeD_rng (vm_offset_t start, vm_size_t end); -void arm8_cache_syncI_rng (vm_offset_t start, vm_size_t end); - -void arm8_context_switch (void); - -void arm8_setup (char *string); - -u_int arm8_clock_config (u_int, u_int); -#endif - - #if defined(CPU_FA526) || defined(CPU_FA626TE) void fa526_setup (char *arg); void fa526_setttb (u_int ttb); @@ -362,48 +305,6 @@ void fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end); #endif -#ifdef CPU_SA110 -void sa110_setup (char *string); -void sa110_context_switch (void); -#endif /* CPU_SA110 */ - -#if defined(CPU_SA1100) || defined(CPU_SA1110) -void sa11x0_drain_readbuf (void); - -void sa11x0_context_switch (void); -void sa11x0_cpu_sleep (int mode); - -void sa11x0_setup (char *string); -#endif - -#if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) -void sa1_setttb (u_int ttb); - -void sa1_tlb_flushID_SE (u_int va); - -void sa1_cache_flushID (void); -void sa1_cache_flushI (void); -void sa1_cache_flushD (void); -void sa1_cache_flushD_SE (u_int entry); - -void sa1_cache_cleanID (void); -void sa1_cache_cleanD (void); -void sa1_cache_cleanD_E (u_int entry); - -void sa1_cache_purgeID (void); -void sa1_cache_purgeID_E (u_int entry); -void sa1_cache_purgeD (void); -void sa1_cache_purgeD_E (u_int entry); - -void sa1_cache_syncI (void); -void sa1_cache_cleanID_rng (vm_offset_t start, vm_size_t end); -void sa1_cache_cleanD_rng (vm_offset_t start, vm_size_t end); -void sa1_cache_purgeID_rng (vm_offset_t start, vm_size_t end); -void sa1_cache_purgeD_rng (vm_offset_t start, vm_size_t end); -void sa1_cache_syncI_rng (vm_offset_t start, vm_size_t end); - -#endif - #ifdef CPU_ARM9 void arm9_setttb (u_int); @@ -586,7 +487,6 @@ extern unsigned armv5_dcache_index_inc; #endif #if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \ - defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ defined(CPU_FA526) || defined(CPU_FA626TE) || \ defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ @@ -601,12 +501,6 @@ void armv4_drain_writebuf (void); void armv4_idcache_inv_all (void); #endif -#if defined(CPU_IXP12X0) -void ixp12x0_drain_readbuf (void); -void ixp12x0_context_switch (void); -void ixp12x0_setup (char *string); -#endif - #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) diff --git a/sys/arm/include/md_var.h b/sys/arm/include/md_var.h index ef202f5..7337b33 100644 --- a/sys/arm/include/md_var.h +++ b/sys/arm/include/md_var.h @@ -50,13 +50,6 @@ extern int _min_bzero_size; enum cpu_class { CPU_CLASS_NONE, - CPU_CLASS_ARM2, - CPU_CLASS_ARM2AS, - CPU_CLASS_ARM3, - CPU_CLASS_ARM6, - CPU_CLASS_ARM7, - CPU_CLASS_ARM7TDMI, - CPU_CLASS_ARM8, CPU_CLASS_ARM9TDMI, CPU_CLASS_ARM9ES, CPU_CLASS_ARM9EJS, @@ -64,7 +57,6 @@ enum cpu_class { CPU_CLASS_ARM10EJ, CPU_CLASS_CORTEXA, CPU_CLASS_KRAIT, - CPU_CLASS_SA1, CPU_CLASS_XSCALE, CPU_CLASS_ARM11J, CPU_CLASS_MARVELL diff --git a/sys/arm/include/param.h b/sys/arm/include/param.h index 5cd0b7b..ab5b406 100644 --- a/sys/arm/include/param.h +++ b/sys/arm/include/param.h @@ -70,7 +70,6 @@ #endif #endif #endif -#define MID_MACHINE MID_ARM6 #if defined(SMP) || defined(KLD_MODULE) #ifndef MAXCPU diff --git a/sys/arm/include/pmap.h b/sys/arm/include/pmap.h index 74282cc..00080b9 100644 --- a/sys/arm/include/pmap.h +++ b/sys/arm/include/pmap.h @@ -355,7 +355,7 @@ extern int pmap_needs_pte_sync; #define L1_C_PROTO pte_l1_c_proto #define L2_S_PROTO pte_l2_s_proto -#elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 +#elif ARM_MMU_GENERIC != 0 #define L2_S_PROT_U L2_S_PROT_U_generic #define L2_S_PROT_W L2_S_PROT_W_generic #define L2_S_PROT_MASK L2_S_PROT_MASK_generic @@ -488,13 +488,10 @@ extern int pmap_needs_pte_sync; #endif /* SMP */ #endif /* ARM_NMMUS > 1 */ -#if (ARM_MMU_SA1 == 1) && (ARM_NMMUS == 1) -#define PMAP_NEEDS_PTE_SYNC 1 -#define PMAP_INCLUDE_PTE_SYNC -#elif defined(CPU_XSCALE_81342) || ARM_ARCH_6 || ARM_ARCH_7A +#if defined(CPU_XSCALE_81342) || ARM_ARCH_6 || ARM_ARCH_7A #define PMAP_NEEDS_PTE_SYNC 1 #define PMAP_INCLUDE_PTE_SYNC -#elif (ARM_MMU_SA1 == 0) +#else #define PMAP_NEEDS_PTE_SYNC 0 #endif @@ -616,14 +613,11 @@ extern void (*pmap_copy_page_offs_func)(vm_paddr_t a_phys, vm_offset_t a_offs, vm_paddr_t b_phys, vm_offset_t b_offs, int cnt); extern void (*pmap_zero_page_func)(vm_paddr_t, int, int); -#if (ARM_MMU_GENERIC + ARM_MMU_V6 + ARM_MMU_V7 + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_81342) +#if (ARM_MMU_GENERIC + ARM_MMU_V6 + ARM_MMU_V7) != 0 || defined(CPU_XSCALE_81342) void pmap_copy_page_generic(vm_paddr_t, vm_paddr_t); void pmap_zero_page_generic(vm_paddr_t, int, int); void pmap_pte_init_generic(void); -#if defined(CPU_ARM8) -void pmap_pte_init_arm8(void); -#endif #if defined(CPU_ARM9) void pmap_pte_init_arm9(void); #endif /* CPU_ARM9 */ @@ -633,11 +627,7 @@ void pmap_pte_init_arm10(void); #if (ARM_MMU_V6 + ARM_MMU_V7) != 0 void pmap_pte_init_mmu_v6(void); #endif /* (ARM_MMU_V6 + ARM_MMU_V7) != 0 */ -#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ - -#if /* ARM_MMU_SA1 == */1 -void pmap_pte_init_sa1(void); -#endif /* ARM_MMU_SA1 == 1 */ +#endif /* (ARM_MMU_GENERIC + ARM_MMU_V6 + ARM_MMU_V7) != 0 */ #if ARM_MMU_XSCALE == 1 void pmap_copy_page_xscale(vm_paddr_t, vm_paddr_t); diff --git a/sys/arm/sa11x0/assabet_machdep.c b/sys/arm/sa11x0/assabet_machdep.c deleted file mode 100644 index 73e2a0d..0000000 --- a/sys/arm/sa11x0/assabet_machdep.c +++ /dev/null @@ -1,393 +0,0 @@ -/* $NetBSD: hpc_machdep.c,v 1.70 2003/09/16 08:18:22 agc Exp $ */ - -/*- - * Copyright (c) 1994-1998 Mark Brinicombe. - * Copyright (c) 1994 Brini. - * All rights reserved. - * - * This code is derived from software written for Brini by Mark Brinicombe - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Brini. - * 4. The name of the company nor the name of the author may be used to - * endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * RiscBSD kernel project - * - * machdep.c - * - * Machine dependant functions for kernel setup - * - * This file needs a lot of work. - * - * Created : 17/09/94 - */ - - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -#include "opt_md.h" - -#define _ARM32_BUS_DMA_PRIVATE -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/sysproto.h> -#include <sys/signalvar.h> -#include <sys/imgact.h> -#include <sys/kernel.h> -#include <sys/ktr.h> -#include <sys/linker.h> -#include <sys/lock.h> -#include <sys/malloc.h> -#include <sys/mutex.h> -#include <sys/pcpu.h> -#include <sys/proc.h> -#include <sys/ptrace.h> -#include <sys/cons.h> -#include <sys/bio.h> -#include <sys/bus.h> -#include <sys/buf.h> -#include <sys/exec.h> -#include <sys/kdb.h> -#include <machine/reg.h> -#include <machine/cpu.h> - -#include <vm/vm.h> -#include <vm/pmap.h> -#include <vm/vm_object.h> -#include <vm/vm_page.h> -#include <vm/vm_map.h> -#include <machine/devmap.h> -#include <machine/vmparam.h> -#include <machine/pcb.h> -#include <machine/undefined.h> -#include <machine/machdep.h> -#include <machine/metadata.h> -#include <machine/armreg.h> -#include <machine/physmem.h> - -#include <machine/bus.h> -#include <sys/reboot.h> - -#include <arm/sa11x0/sa11x0_reg.h> - -#define MDROOT_ADDR 0xd0400000 - -#define KERNEL_PT_VMEM 0 /* Page table for mapping video memory */ -#define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */ -#define KERNEL_PT_IO 3 /* Page table for mapping IO */ -#define KERNEL_PT_IRQ 2 /* Page table for mapping irq handler */ -#define KERNEL_PT_KERNEL 1 /* Page table for mapping kernel */ -#define KERNEL_PT_L1 4 /* Page table for mapping l1pt */ -#define KERNEL_PT_VMDATA 5 /* Page tables for mapping kernel VM */ -#define KERNEL_PT_VMDATA_NUM 7 /* start with 16MB of KVM */ -#define NUM_KERNEL_PTS (KERNEL_PT_VMDATA + KERNEL_PT_VMDATA_NUM) - -#define KERNEL_VM_BASE (KERNBASE + 0x00100000) -#define KERNEL_VM_SIZE 0x05000000 - -struct pv_addr kernel_pt_table[NUM_KERNEL_PTS]; - -extern vm_offset_t sa1110_uart_vaddr; - -extern vm_offset_t sa1_cache_clean_addr; - -#ifndef MD_ROOT_SIZE -#define MD_ROOT_SIZE 65535 -#endif -/* Physical and virtual addresses for some global pages */ - -vm_paddr_t physical_start; -vm_paddr_t physical_end; -vm_paddr_t physical_freestart; - -struct pv_addr systempage; -struct pv_addr irqstack; -struct pv_addr undstack; -struct pv_addr abtstack; -struct pv_addr kernelstack; - -/* Static device mappings. */ -static const struct arm_devmap_entry assabet_devmap[] = { - /* - * Map the on-board devices VA == PA so that we can access them - * with the MMU on or off. - */ - { - SACOM1_VBASE, - SACOM1_BASE, - SACOM1_SIZE, - VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, - }, - { - SAIPIC_BASE, - SAIPIC_BASE, - SAIPIC_SIZE, - VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, - }, - { - 0, - 0, - 0, - 0, - 0, - } -}; - -struct arm32_dma_range * -bus_dma_get_range(void) -{ - - return (NULL); -} - -int -bus_dma_get_range_nb(void) -{ - return (0); -} - -void -cpu_reset() -{ - cpu_halt(); - while (1); -} - -#define CPU_SA110_CACHE_CLEAN_SIZE (0x4000 * 2) - -void * -initarm(struct arm_boot_params *abp) -{ - struct pv_addr kernel_l1pt; - struct pv_addr md_addr; - struct pv_addr md_bla; - struct pv_addr dpcpu; - int loop; - u_int l1pagetable; - vm_offset_t freemempos; - vm_offset_t lastalloced; - vm_offset_t lastaddr; - uint32_t memsize = 32 * 1024 * 1024; - sa1110_uart_vaddr = SACOM1_VBASE; - - boothowto = RB_VERBOSE | RB_SINGLE; /* Default value */ - lastaddr = parse_boot_param(abp); - arm_physmem_kernaddr = abp->abp_physaddr; - cninit(); - set_cpufuncs(); - pcpu0_init(); - - /* Do basic tuning, hz etc */ - init_param1(); - - physical_start = (vm_offset_t) KERNBASE; - physical_end = lastaddr; - physical_freestart = (((vm_offset_t)physical_end) + PAGE_MASK) & ~PAGE_MASK; - md_addr.pv_va = md_addr.pv_pa = MDROOT_ADDR; - freemempos = (vm_offset_t)round_page(physical_freestart); - memset((void *)freemempos, 0, 256*1024); - /* Define a macro to simplify memory allocation */ -#define valloc_pages(var, np) \ - alloc_pages((var).pv_pa, (np)); \ - (var).pv_va = (var).pv_pa; - -#define alloc_pages(var, np) \ - (var) = freemempos; \ - freemempos += ((np) * PAGE_SIZE);\ - memset((char *)(var), 0, ((np) * PAGE_SIZE)); - - while ((freemempos & (L1_TABLE_SIZE - 1)) != 0) - freemempos += PAGE_SIZE; - valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); - valloc_pages(md_bla, L2_TABLE_SIZE / PAGE_SIZE); - alloc_pages(sa1_cache_clean_addr, CPU_SA110_CACHE_CLEAN_SIZE / PAGE_SIZE); - - for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) { - if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) { - valloc_pages(kernel_pt_table[loop], - L2_TABLE_SIZE / PAGE_SIZE); - } else { - kernel_pt_table[loop].pv_pa = freemempos + - (loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) * - L2_TABLE_SIZE_REAL; - kernel_pt_table[loop].pv_va = - kernel_pt_table[loop].pv_pa; - } - } - - /* - * Allocate a page for the system page mapped to V0x00000000 - * This page will just contain the system vectors and can be - * shared by all processes. - */ - valloc_pages(systempage, 1); - - /* Allocate dynamic per-cpu area. */ - valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE); - dpcpu_init((void *)dpcpu.pv_va, 0); - - /* Allocate stacks for all modes */ - valloc_pages(irqstack, IRQ_STACK_SIZE); - valloc_pages(abtstack, ABT_STACK_SIZE); - valloc_pages(undstack, UND_STACK_SIZE); - valloc_pages(kernelstack, KSTACK_PAGES); - lastalloced = kernelstack.pv_va; - - /* - * Allocate memory for the l1 and l2 page tables. The scheme to avoid - * wasting memory by allocating the l1pt on the first 16k memory was - * taken from NetBSD rpc_machdep.c. NKPT should be greater than 12 for - * this to work (which is supposed to be the case). - */ - - /* - * Now we start construction of the L1 page table - * We start by mapping the L2 page tables into the L1. - * This means that we can replace L1 mappings later on if necessary - */ - l1pagetable = kernel_l1pt.pv_pa; - - - /* Map the L2 pages tables in the L1 page table */ - pmap_link_l2pt(l1pagetable, 0x00000000, - &kernel_pt_table[KERNEL_PT_SYS]); - pmap_link_l2pt(l1pagetable, KERNBASE, - &kernel_pt_table[KERNEL_PT_KERNEL]); - pmap_link_l2pt(l1pagetable, 0xd0000000, - &kernel_pt_table[KERNEL_PT_IO]); - pmap_link_l2pt(l1pagetable, lastalloced & ~((L1_S_SIZE * 4) - 1), - &kernel_pt_table[KERNEL_PT_L1]); - pmap_link_l2pt(l1pagetable, 0x90000000, &kernel_pt_table[KERNEL_PT_IRQ]); - pmap_link_l2pt(l1pagetable, MDROOT_ADDR, - &md_bla); - for (loop = 0; loop < KERNEL_PT_VMDATA_NUM; ++loop) - pmap_link_l2pt(l1pagetable, KERNEL_VM_BASE + loop * 0x00100000, - &kernel_pt_table[KERNEL_PT_VMDATA + loop]); - pmap_map_chunk(l1pagetable, KERNBASE, KERNBASE, - ((uint32_t)lastaddr - KERNBASE), VM_PROT_READ|VM_PROT_WRITE, - PTE_CACHE); - /* Map the DPCPU pages */ - pmap_map_chunk(l1pagetable, dpcpu.pv_va, dpcpu.pv_pa, DPCPU_SIZE, - VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); - /* Map the stack pages */ - pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa, - IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); - pmap_map_chunk(l1pagetable, md_addr.pv_va, md_addr.pv_pa, - MD_ROOT_SIZE * 1024, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); - pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa, - ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); - pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa, - UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); - pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa, - KSTACK_PAGES * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); - - pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa, - L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); - - for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) { - pmap_map_chunk(l1pagetable, kernel_pt_table[loop].pv_va, - kernel_pt_table[loop].pv_pa, L2_TABLE_SIZE, - VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); - } - pmap_map_chunk(l1pagetable, md_bla.pv_va, md_bla.pv_pa, L2_TABLE_SIZE, - VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); - /* Map the vector page. */ - pmap_map_entry(l1pagetable, vector_page, systempage.pv_pa, - VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); - /* Map the statically mapped devices. */ - arm_devmap_bootstrap(l1pagetable, assabet_devmap); - pmap_map_chunk(l1pagetable, sa1_cache_clean_addr, 0xf0000000, - CPU_SA110_CACHE_CLEAN_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); - - undefined_init(); - cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); - setttb(kernel_l1pt.pv_pa); - cpu_tlb_flushID(); - cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)); - - /* - * Pages were allocated during the secondary bootstrap for the - * stacks for different CPU modes. - * We must now set the r13 registers in the different CPU modes to - * point to these stacks. - * Since the ARM stacks use STMFD etc. we must set r13 to the top end - * of the stack memory. - */ - set_stackptrs(0); - - /* - * We must now clean the cache again.... - * Cleaning may be done by reading new data to displace any - * dirty data in the cache. This will have happened in setttb() - * but since we are boot strapping the addresses used for the read - * may have just been remapped and thus the cache could be out - * of sync. A re-clean after the switch will cure this. - * After booting there are no gross relocations of the kernel thus - * this problem will not occur after initarm(). - */ - cpu_idcache_wbinv_all(); - - bootverbose = 1; - - /* Set stack for exception handlers */ - - init_proc0(kernelstack.pv_va); - - - /* Enable MMU, I-cache, D-cache, write buffer. */ - - cpufunc_control(0x337f, 0x107d); - arm_vector_init(ARM_VECTORS_LOW, ARM_VEC_ALL); - cpu_setup(""); - - pmap_curmaxkvaddr = freemempos + KERNEL_PT_VMDATA_NUM * 0x400000; - mutex_init(); - vm_max_kernel_address = 0xd0000000; - pmap_bootstrap(freemempos, &kernel_l1pt); - - /* - * Add the physical ram we have available. - * - * Exclude the kernel (and all the things we allocated which immediately - * follow the kernel) from the VM allocation pool but not from crash - * dumps. virtual_avail is a global variable which tracks the kva we've - * "allocated" while setting up pmaps. - * - * Prepare the list of physical memory available to the vm subsystem. - */ - arm_physmem_hardware_region(physical_start, memsize); - arm_physmem_exclude_region(abp->abp_physaddr, - virtual_avail - KERNVIRTADDR, EXFLAG_NOALLOC); - arm_physmem_init_kernel_globals(); - - init_param2(physmem); - kdb_init(); - return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP - - sizeof(struct pcb))); -} diff --git a/sys/arm/sa11x0/files.sa11x0 b/sys/arm/sa11x0/files.sa11x0 deleted file mode 100644 index 0706c27..0000000 --- a/sys/arm/sa11x0/files.sa11x0 +++ /dev/null @@ -1,14 +0,0 @@ -# $FreeBSD$ -arm/arm/bus_space_generic.c standard -arm/arm/cpufunc_asm_sa1.S standard -arm/arm/cpufunc_asm_sa11x0.S standard -arm/sa11x0/assabet_machdep.c optional assabet -arm/sa11x0/sa11x0.c optional saip -arm/sa11x0/sa11x0_ost.c optional saip -arm/sa11x0/sa11x0_io.c optional saip -arm/sa11x0/sa11x0_io_asm.S optional saip -arm/sa11x0/sa11x0_irq.S optional saip -arm/sa11x0/sa11x0_irqhandler.c optional saip -arm/sa11x0/uart_cpu_sa1110.c optional uart saip -arm/sa11x0/uart_dev_sa1110.c optional uart saip -arm/sa11x0/uart_bus_sa1110.c optional uart saip diff --git a/sys/arm/sa11x0/sa11x0.c b/sys/arm/sa11x0/sa11x0.c deleted file mode 100644 index 975c08d..0000000 --- a/sys/arm/sa11x0/sa11x0.c +++ /dev/null @@ -1,253 +0,0 @@ -/* $NetBSD: sa11x0.c,v 1.14 2003/07/15 00:24:50 lukem Exp $ */ - -/*- - * Copyright (c) 2001, The NetBSD Foundation, Inc. All rights reserved. - * - * This code is derived from software contributed to The NetBSD Foundation - * by IWAMOTO Toshihiro and Ichiro FUKUHARA. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - */ -/*- - * Copyright (c) 1999 - * Shin Takemura and PocketBSD Project. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the PocketBSD project - * and its contributors. - * 4. Neither the name of the project nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/bus.h> -#include <sys/kernel.h> -#include <sys/reboot.h> -#include <sys/malloc.h> -#include <sys/interrupt.h> -#include <sys/module.h> -#include <sys/rman.h> - -#include <vm/vm.h> -#include <vm/vm_extern.h> - -#include <machine/cpu.h> -#include <machine/bus.h> -#include <machine/intr.h> -#include <arm/sa11x0/sa11x0_reg.h> -#include <arm/sa11x0/sa11x0_var.h> -#include <arm/sa11x0/sa11x0_dmacreg.h> -#include <arm/sa11x0/sa11x0_ppcreg.h> -#include <arm/sa11x0/sa11x0_gpioreg.h> - -extern void sa11x0_activateirqs(void); - -static struct resource *sa1110_alloc_resource(device_t, device_t, int, int *, - u_long, u_long, u_long, u_int); - -static int sa1110_activate_resource(device_t, device_t, int, int, - struct resource *); -static int sa1110_setup_intr(device_t, device_t, struct resource *, int, - driver_filter_t *, driver_intr_t *, void *, void **); - -struct sa11x0_softc *sa11x0_softc; /* There can be only one. */ - -static int -sa1110_setup_intr(device_t dev, device_t child, - struct resource *ires, int flags, driver_filter_t *filt, - driver_intr_t *intr, void *arg, void **cookiep) -{ - int saved_cpsr; - - if (flags & INTR_TYPE_TTY) - rman_set_start(ires, 15); - else if (flags & INTR_TYPE_CLK) { - if (rman_get_start(ires) == 0) - rman_set_start(ires, 26); - else - rman_set_start(ires, 27); - } - saved_cpsr = SetCPSR(I32_bit, I32_bit); - - SetCPSR(I32_bit, saved_cpsr & I32_bit); - BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, filt, - intr, arg, cookiep); - return (0); -} - -static struct resource * -sa1110_alloc_resource(device_t bus, device_t child, int type, int *rid, - u_long start, u_long end, u_long count, u_int flags) -{ - struct resource *res; - - res = rman_reserve_resource(&sa11x0_softc->sa11x0_rman, *rid, *rid, - count, flags, child); - if (res != NULL) - rman_set_rid(res, *rid); - - return (res); -} -static int -sa1110_activate_resource(device_t bus, device_t child, int type, int rid, - struct resource *r) -{ - return (0); -} -/* prototypes */ -static int sa11x0_probe(device_t); -static int sa11x0_attach(device_t); -static void sa11x0_identify(driver_t *, device_t); - -extern vm_offset_t saipic_base; - - -int -sa11x0_probe(device_t dev) -{ - return (BUS_PROBE_NOWILDCARD); -} - -void -sa11x0_identify(driver_t *driver, device_t parent) -{ - - BUS_ADD_CHILD(parent, 0, "saip", 0); -} - -int -sa11x0_attach(device_t dev) -{ - struct sa11x0_softc *sc = device_get_softc(dev); - int unit = device_get_unit(dev); - sc->sc_iot = &sa11x0_bs_tag; - - sa11x0_softc = sc; - - /* Map the SAIP */ - - if (bus_space_map(sc->sc_iot, SAIPIC_BASE, SAIPIC_NPORTS, - 0, &sc->sc_ioh)) - panic("saip%d: Cannot map registers", unit); - saipic_base = sc->sc_ioh; - - /* Map the GPIO registers */ - if (bus_space_map(sc->sc_iot, SAGPIO_BASE, SAGPIO_NPORTS, - 0, &sc->sc_gpioh)) - panic("saip%d: unable to map GPIO registers", unit); - bus_space_write_4(sc->sc_iot, sc->sc_gpioh, SAGPIO_EDR, 0xffffffff); - - /* Map the PPC registers */ - if (bus_space_map(sc->sc_iot, SAPPC_BASE, SAPPC_NPORTS, - 0, &sc->sc_ppch)) - panic("saip%d: unable to map PPC registers", unit); - -#if 0 - /* Map the DMA controller registers */ - if (bus_space_map(sc->sc_iot, SADMAC_BASE, SADMAC_NPORTS, - 0, &sc->sc_dmach)) - panic("saip%d: unable to map DMAC registers", unit); -#endif - /* Map the reset controller registers */ - if (bus_space_map(sc->sc_iot, SARCR_BASE, PAGE_SIZE, - 0, &sc->sc_reseth)) - panic("saip%d: unable to map reset registers", unit); - printf("\n"); - - - /* - * Mask all interrupts. - * They are later unmasked at each device's attach routine. - */ - bus_space_write_4(sc->sc_iot, sc->sc_ioh, SAIPIC_MR, 0); - - /* Route all bits to IRQ */ - bus_space_write_4(sc->sc_iot, sc->sc_ioh, SAIPIC_LR, 0); - - /* Exit idle mode only when unmasked intr is received */ - bus_space_write_4(sc->sc_iot, sc->sc_ioh, SAIPIC_CR, 1); -#if 0 - /* disable all DMAC channels */ - bus_space_write_4(sc->sc_iot, sc->sc_dmach, SADMAC_DCR0_CLR, 1); - bus_space_write_4(sc->sc_iot, sc->sc_dmach, SADMAC_DCR1_CLR, 1); - bus_space_write_4(sc->sc_iot, sc->sc_dmach, SADMAC_DCR2_CLR, 1); - bus_space_write_4(sc->sc_iot, sc->sc_dmach, SADMAC_DCR3_CLR, 1); - bus_space_write_4(sc->sc_iot, sc->sc_dmach, SADMAC_DCR4_CLR, 1); - bus_space_write_4(sc->sc_iot, sc->sc_dmach, SADMAC_DCR5_CLR, 1); -#endif - /* - * XXX this is probably a bad place, but intr bit shouldn't be - * XXX enabled before intr mask is set. - * XXX Having sane imask[] suffice?? - */ -#if 0 - SetCPSR(I32_bit, 0); -#endif - /* - * Attach each devices - */ - sc->sa11x0_rman.rm_type = RMAN_ARRAY; - sc->sa11x0_rman.rm_descr = "SA11x0 IRQs"; - if (rman_init(&sc->sa11x0_rman) != 0 || - rman_manage_region(&sc->sa11x0_rman, 0, 32) != 0) - panic("sa11x0_attach: failed to set up rman"); - device_add_child(dev, "uart", 0); - device_add_child(dev, "saost", 0); - bus_generic_probe(dev); - bus_generic_attach(dev); - sa11x0_activateirqs(); - return (0); -} - -static device_method_t saip_methods[] = { - DEVMETHOD(device_probe, sa11x0_probe), - DEVMETHOD(device_attach, sa11x0_attach), - DEVMETHOD(device_identify, sa11x0_identify), - DEVMETHOD(bus_alloc_resource, sa1110_alloc_resource), - DEVMETHOD(bus_activate_resource, sa1110_activate_resource), - DEVMETHOD(bus_setup_intr, sa1110_setup_intr), - {0, 0}, -}; - -static driver_t saip_driver = { - "saip", - saip_methods, - sizeof(struct sa11x0_softc), -}; -static devclass_t saip_devclass; - -DRIVER_MODULE(saip, nexus, saip_driver, saip_devclass, 0, 0); diff --git a/sys/arm/sa11x0/sa11x0_dmacreg.h b/sys/arm/sa11x0/sa11x0_dmacreg.h deleted file mode 100644 index a4b5fb7..0000000 --- a/sys/arm/sa11x0/sa11x0_dmacreg.h +++ /dev/null @@ -1,90 +0,0 @@ -/* $NetBSD: sa11x0_dmacreg.h,v 1.1 2001/07/08 23:37:53 rjs Exp $ */ - -/*- - * Copyright (c) 2001, The NetBSD Foundation, Inc. All rights reserved. - * - * This code is derived from software contributed to The NetBSD Foundation - * by IWAMOTO Toshihiro. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - * - */ - -/* SA11[01]0 integrated DMA controller */ - -#define SADMAC_NPORTS 40 - -#define SADMAC_DAR0 0x00 /* DMA device address register */ -#define SADMAC_DCR0_SET 0x04 /* DMA control/status (set) */ -#define SADMAC_DCR0_CLR 0x08 /* DMA control/status (clear) */ -#define SADMAC_DCR0 0x0C /* DMA control/status (read only) */ -#define SADMAC_DBSA0 0x10 /* DMA Buffer A start address */ -#define SADMAC_DBTA0 0x14 /* DMA Buffer A transfer count */ -#define SADMAC_DBSB0 0x18 /* DMA Buffer B start address */ -#define SADMAC_DBTB0 0x1C /* DMA Buffer B transfer count */ - -#define SADMAC_DAR1 0x20 -#define SADMAC_DCR1_SET 0x24 -#define SADMAC_DCR1_CLR 0x28 -#define SADMAC_DCR1 0x2C -#define SADMAC_DBSA1 0x30 -#define SADMAC_DBTA1 0x34 -#define SADMAC_DBSB1 0x38 -#define SADMAC_DBTB1 0x3C - -#define SADMAC_DAR2 0x40 -#define SADMAC_DCR2_SET 0x44 -#define SADMAC_DCR2_CLR 0x48 -#define SADMAC_DCR2 0x4C -#define SADMAC_DBSA2 0x50 -#define SADMAC_DBTA2 0x54 -#define SADMAC_DBSB2 0x58 -#define SADMAC_DBTB2 0x5C - -#define SADMAC_DAR3 0x60 -#define SADMAC_DCR3_SET 0x64 -#define SADMAC_DCR3_CLR 0x68 -#define SADMAC_DCR3 0x6C -#define SADMAC_DBSA3 0x70 -#define SADMAC_DBTA3 0x74 -#define SADMAC_DBSB3 0x78 -#define SADMAC_DBTB3 0x7C - -#define SADMAC_DAR4 0x80 -#define SADMAC_DCR4_SET 0x84 -#define SADMAC_DCR4_CLR 0x88 -#define SADMAC_DCR4 0x8C -#define SADMAC_DBSA4 0x90 -#define SADMAC_DBTA4 0x94 -#define SADMAC_DBSB4 0x98 -#define SADMAC_DBTB4 0x9C - -#define SADMAC_DAR5 0xA0 -#define SADMAC_DCR5_SET 0xA4 -#define SADMAC_DCR5_CLR 0xA8 -#define SADMAC_DCR5 0xAC -#define SADMAC_DBSA5 0xB0 -#define SADMAC_DBTA5 0xB4 -#define SADMAC_DBSB5 0xB8 -#define SADMAC_DBTB5 0xBC diff --git a/sys/arm/sa11x0/sa11x0_gpioreg.h b/sys/arm/sa11x0/sa11x0_gpioreg.h deleted file mode 100644 index 92c5bfe..0000000 --- a/sys/arm/sa11x0/sa11x0_gpioreg.h +++ /dev/null @@ -1,93 +0,0 @@ -/* $NetBSD: sa11x0_gpioreg.h,v 1.2 2001/07/30 15:58:56 rjs Exp $ */ - -/*- - * Copyright (c) 2001 The NetBSD Foundation, Inc. All rights reserved. - * - * This code is derived from software contributed to The NetBSD Foundation - * by Ichiro FUKUHARA (ichiro@ichiro.org). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD$ - * - */ - -/* - * SA-11x0 GPIO Register - */ - -#define SAGPIO_NPORTS 8 - -/* GPIO pin-level register */ -#define SAGPIO_PLR 0x00 - -/* GPIO pin direction register */ -#define SAGPIO_PDR 0x04 - -/* GPIO pin output set register */ -#define SAGPIO_PSR 0x08 - -/* GPIO pin output clear register */ -#define SAGPIO_PCR 0x0C - -/* GPIO rising-edge detect register */ -#define SAGPIO_RER 0x10 - -/* GPIO falling-edge detect register */ -#define SAGPIO_FER 0x14 - -/* GPIO edge-detect status register */ -#define SAGPIO_EDR 0x18 - -/* GPIO alternate function register */ -#define SAGPIO_AFR 0x1C - -/* XXX */ -#define GPIO(x) (0x00000001 << (x)) - -/* - * SA-11x0 GPIOs parameter - */ -/* -port name desc -0 Reserved -1 Reserved -2...9 LDD{8..15} LCD DATA(8-15) -10 SSP_TXD SSP transmit -11 SSP_RXD SSP receive -12 SSP_SCLK SSP serial clock -13 SSP_SFRM SSP frameclock -14 UART_TXD UART transmit -15 UART_RXD UART receive -16 GPCLK_OUT General-purpose clock out -17 Reserved -18 UART_SCLK Sample clock input -19 SSP_CLK Sample clock input -20 UART_SCLK3 Sample clock input -21 MCP_CLK MCP dock in -22 TREQA Either TIC request A -23 TREQB Either TIC request B -24 Reserved -25 RTC Real Time Clock -26 RCLK_OUT internal clock /2 -27 32KHZ_OUT Raw 32.768kHz osc output - */ diff --git a/sys/arm/sa11x0/sa11x0_io.c b/sys/arm/sa11x0/sa11x0_io.c deleted file mode 100644 index 5731599..0000000 --- a/sys/arm/sa11x0/sa11x0_io.c +++ /dev/null @@ -1,135 +0,0 @@ -/* $NetBSD: sa11x0_io.c,v 1.12 2003/07/15 00:24:51 lukem Exp $ */ - -/*- - * Copyright (c) 1997 Mark Brinicombe. - * Copyright (c) 1997 Causality Limited. - * All rights reserved. - * - * This code is derived from software contributed to The NetBSD Foundation - * by Ichiro FUKUHARA. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Mark Brinicombe. - * 4. The name of the company nor the name of the author may be used to - * endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* - * bus_space I/O functions for sa11x0 - */ - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/queue.h> -#include <sys/lock.h> -#include <sys/mutex.h> - -#include <vm/vm.h> -#include <vm/pmap.h> -#include <vm/vm_extern.h> -#include <vm/vm_kern.h> - -#include <machine/bus.h> - -/* Proto types for all the bus_space structure functions */ - -bs_protos(generic); -bs_protos(sa11x0); - -/* Declare the sa11x0 bus space tag */ - -struct bus_space sa11x0_bs_tag = { - /* cookie */ - NULL, - - /* mapping/unmapping */ - generic_bs_map, - generic_bs_unmap, - generic_bs_subregion, - - /* allocation/deallocation */ - generic_bs_alloc, - generic_bs_free, - - /* barrier */ - generic_bs_barrier, - - /* read (single) */ - sa11x0_bs_r_1, - sa11x0_bs_r_2, - sa11x0_bs_r_4, - NULL, - - /* read multiple */ - sa11x0_bs_rm_1, - sa11x0_bs_rm_2, - sa11x0_bs_rm_4, - NULL, - - /* read region */ - NULL, - sa11x0_bs_rr_2, - NULL, - NULL, - /* write (single) */ - sa11x0_bs_w_1, - sa11x0_bs_w_2, - sa11x0_bs_w_4, - NULL, - - /* write multiple */ - sa11x0_bs_wm_1, - sa11x0_bs_wm_2, - sa11x0_bs_wm_4, - NULL, - - /* write region */ - NULL, - sa11x0_bs_wr_2, - NULL, - NULL, - - /* set multiple */ - NULL, - NULL, - NULL, - NULL, - - /* set region */ - NULL, - sa11x0_bs_sr_2, - NULL, - NULL, - - /* copy */ - NULL, - sa11x0_bs_c_2, - NULL, - NULL, -}; - -/* End of sa11x0_io.c */ diff --git a/sys/arm/sa11x0/sa11x0_io_asm.S b/sys/arm/sa11x0/sa11x0_io_asm.S deleted file mode 100644 index 00b59bf..0000000 --- a/sys/arm/sa11x0/sa11x0_io_asm.S +++ /dev/null @@ -1,290 +0,0 @@ -/* $NetBSD: sa11x0_io_asm.S,v 1.1 2001/07/08 23:37:53 rjs Exp $ */ - -/*- - * Copyright (c) 1997 Mark Brinicombe. - * Copyright (c) 1997 Causality Limited. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Mark Brinicombe. - * 4. The name of the company nor the name of the author may be used to - * endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#include <machine/asm.h> -__FBSDID("$FreeBSD$"); - -/* - * bus_space I/O functions for sa11x0 - */ - -/* - * read single - */ - -ENTRY(sa11x0_bs_r_1) - ldrb r0, [r1, r2] - mov pc, lr - -ENTRY(sa11x0_bs_r_2) - ldrh r0, [r1, r2] - mov pc, lr - -ENTRY(sa11x0_bs_r_4) - ldr r0, [r1, r2] - mov pc, lr - -/* - * write single - */ - -ENTRY(sa11x0_bs_w_1) - strb r3, [r1, r2] - mov pc, lr - -ENTRY(sa11x0_bs_w_2) - strh r3, [r1, r2] - mov pc, lr - -ENTRY(sa11x0_bs_w_4) - str r3, [r1, r2] - mov pc, lr - - -/* - * read multiple - */ - -ENTRY(sa11x0_bs_rm_1) - add r0, r1, r2 - ldr r2, [sp, #0] - cmp r2, #0x00000000 - movle pc, lr - -sa11x0_bs_rm_1_loop: - ldrb r1, [r0] - subs r2, r2, #0x00000001 - strb r1, [r3], #0x0001 - bgt sa11x0_bs_rm_1_loop - - mov pc, lr - -ENTRY(sa11x0_bs_rm_2) - add r0, r1, r2 - ldr r2, [sp, #0] - cmp r2, #0x00000000 - movle pc, lr - - tst r2, #0x00000007 - tsteq r3, #0x00000003 - beq sa11x0_bs_rm_2_fast - -sa11x0_bs_rm_2_loop: - ldrh r1, [r0] - subs r2, r2, #0x00000001 - strh r1, [r3], #0x0002 - bgt sa11x0_bs_rm_2_loop - - mov pc, lr - -sa11x0_bs_rm_2_fast: - stmfd sp!, {r4, r5, lr} - -sa11x0_bs_rm_2_fastloop: - ldrh r1, [r0] - ldrh lr, [r0] - orr r1, r1, lr, lsl #16 - - ldrh r4, [r0] - ldrh lr, [r0] - orr r4, r4, lr, lsl #16 - - ldrh r5, [r0] - ldrh lr, [r0] - orr r5, r5, lr, lsl #16 - - ldrh ip, [r0] - ldrh lr, [r0] - orr ip, ip, lr, lsl #16 - - stmia r3!, {r1, r4, r5, ip} - subs r2, r2, #8 - bgt sa11x0_bs_rm_2_fastloop - - ldmfd sp!, {r4, r5, pc} - - -ENTRY(sa11x0_bs_rm_4) - add r0, r1, r2 - ldr r2, [sp, #0] - cmp r2, #0x00000000 - movle pc, lr - -sa11x0_bs_rm_4_loop: - ldr r1, [r0] - subs r2, r2, #0x00000001 - str r1, [r3], #0x0004 - bgt sa11x0_bs_rm_4_loop - - mov pc, lr - -/* - * write multiple - */ - -ENTRY(sa11x0_bs_wm_1) - add r0, r1, r2 - ldr r2, [sp, #0] - cmp r2, #0x00000000 - movle pc, lr - -sa11x0_wm_1_loop: - ldrb r1, [r3], #0x0001 - subs r2, r2, #0x00000001 - strb r1, [r0] - bgt sa11x0_wm_1_loop - - mov pc, lr - -ENTRY(sa11x0_bs_wm_2) - add r0, r1, r2 - ldr r2, [sp, #0] - cmp r2, #0x00000000 - movle pc, lr - -sa11x0_bs_wm_2_loop: - ldrh r1, [r3], #0x0002 - subs r2, r2, #0x00000001 - strh r1, [r0] - bgt sa11x0_bs_wm_2_loop - - mov pc, lr - -ENTRY(sa11x0_bs_wm_4) - add r0, r1, r2 - ldr r2, [sp, #0] - cmp r2, #0x00000000 - movle pc, lr - -sa11x0_bs_wm_4_loop: - ldr r1, [r3], #0x0004 - subs r2, r2, #0x00000001 - str r1, [r0] - bgt sa11x0_bs_wm_4_loop - - mov pc, lr - -/* - * read region - */ - -ENTRY(sa11x0_bs_rr_2) - add r0, r1, r2 - ldr r2, [sp, #0] - cmp r2, #0x00000000 - movle pc, lr - -sa11x0_bs_rr_2_loop: - ldrh r1, [r0], #0x0002 - strh r1, [r3], #0x0002 - subs r2, r2, #0x00000001 - bgt sa11x0_bs_rr_2_loop - - mov pc, lr - -/* - * write region - */ - -ENTRY(sa11x0_bs_wr_2) - add r0, r1, r2 - ldr r2, [sp, #0] - cmp r2, #0x00000000 - movle pc, lr - -sa11x0_bs_wr_2_loop: - ldrh r1, [r3], #0x0002 - strh r1, [r0], #0x0002 - subs r2, r2, #0x00000001 - bgt sa11x0_bs_wr_2_loop - - mov pc, lr - -/* - * set regiuon - */ - -ENTRY(sa11x0_bs_sr_2) - add r0, r1, r2 - ldr r2, [sp, #0] - cmp r2, #0x00000000 - movle pc, lr - -sa11x0_bs_sr_2_loop: - strh r3, [r0], #0x0002 - subs r2, r2, #0x00000001 - bgt sa11x0_bs_sr_2_loop - - mov pc, lr - -/* - * copy region - */ - -ENTRY(sa11x0_bs_c_2) - add r0, r1, r2 - ldr r2, [sp, #0] - add r1, r2, r3 - ldr r2, [sp, #4] - cmp r2, #0x00000000 - movle pc, lr - - cmp r0, r1 - blt sa11x0_bs_c_2_backwards - -sa11x0_bs_cf_2_loop: - ldrh r3, [r0], #0x0002 - strh r3, [r1], #0x0002 - subs r2, r2, #0x00000001 - bgt sa11x0_bs_cf_2_loop - - mov pc, lr - -sa11x0_bs_c_2_backwards: - add r0, r0, r2, lsl #1 - add r1, r1, r2, lsl #1 - sub r0, r0, #2 - sub r1, r1, #2 - -sa11x0_bs_cb_2_loop: - ldrh r3, [r0], #-2 - strh r3, [r1], #-2 - subs r2, r2, #1 - bne sa11x0_bs_cb_2_loop - - mov pc, lr - -/* end of sa11x0_io_asm.S */ diff --git a/sys/arm/sa11x0/sa11x0_irq.S b/sys/arm/sa11x0/sa11x0_irq.S deleted file mode 100644 index 4494f6a..0000000 --- a/sys/arm/sa11x0/sa11x0_irq.S +++ /dev/null @@ -1,133 +0,0 @@ -/* $NetBSD: sa11x0_irq.S,v 1.5 2003/03/31 19:52:35 chris Exp $ */ - -/*- - * Copyright (c) 1998 Mark Brinicombe. - * Copyright (c) 1998 Causality Limited - * All rights reserved. - * - * This code is derived from software contributed to the NetBSD Foundation - * by IWAMOTO Toshihiro. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#include "assym.s" -#include <machine/asm.h> -#include <machine/armreg.h> -#include <machine/asmacros.h> -#include <arm/sa11x0/sa11x0_reg.h> -__FBSDID("$FreeBSD$"); -Lcurrent_intr_depth: - .word _C_LABEL(current_intr_depth) - - .globl _C_LABEL(saipic_base) -_C_LABEL(saipic_base): - .word 0x00000000 - -#ifdef INTR_DEBUG -Ldbg_str: - .asciz "irq_entry %x %x\n" -#endif - -AST_LOCALS -/* - * Regsister usage - * - * r6 - Address of current handler - * r7 - Pointer to handler pointer list - * r8 - Current IRQ requests. - * r9 - Used to count through possible IRQ bits. - * r10 - Base address of SAIP - */ - -ASENTRY_NP(irq_entry) - sub lr, lr, #0x00000004 /* Adjust the lr */ - - PUSHFRAMEINSVC /* Push an interrupt frame */ - - /* Load r8 with the SAIPIC interrupt requests */ - - ldr r10, _C_LABEL(saipic_base) - ldr r8, [r10, #(SAIPIC_IP)] /* Load IRQ pending register */ - -#ifdef INTR_DEBUG - ldr r2, [r10, #(SAIPIC_MR)] - adr r0, Ldbg_str - mov r1, r8 - bl _C_LABEL(printf) -#endif - /* - * Note that we have entered the IRQ handler. - * We are in SVC mode so we cannot use the processor mode - * to determine if we are in an IRQ. Instead we will count the - * each time the interrupt handler is nested. - */ - - ldr r0, Lcurrent_intr_depth - ldr r1, [r0] - add r1, r1, #1 - str r1, [r0] - - mov r0, sp - mov r1, r8 - bl _C_LABEL(arm_handler_execute) - -#ifdef INTR_DEBUG - adr r0, Ldbg_str - mov r1, #3 - ldr r2, [r10, #(SAIPIC_MR)] - bl _C_LABEL(printf) -#endif - - /* Decrement the nest count */ - ldr r0, Lcurrent_intr_depth - ldr r1, [r0] - sub r1, r1, #1 - str r1, [r0] - - DO_AST - PULLFRAMEFROMSVCANDEXIT - - /* NOT REACHED */ - b . - 8 -Lcnt: - .word _C_LABEL(cnt) - -ENTRY(sa11x0_activateirqs) - ldr r0, _C_LABEL(saipic_base) - mov r1, #0xffffffff - str r1, [r0, #(SAIPIC_MR)] - mov pc, lr - - .global _C_LABEL(intrnames), _C_LABEL(sintrnames) -_C_LABEL(intrnames): -_C_LABEL(sintrnames): - .int 0 - - .globl _C_LABEL(intrcnt), _C_LABEL(sintrcnt) - -_C_LABEL(intrcnt): - .space ICU_LEN*4 /* XXX Should be linked to number of interrupts */ - -_C_LABEL(sintrcnt): - .word ICU_LEN*4 diff --git a/sys/arm/sa11x0/sa11x0_irqhandler.c b/sys/arm/sa11x0/sa11x0_irqhandler.c deleted file mode 100644 index 30446fa..0000000 --- a/sys/arm/sa11x0/sa11x0_irqhandler.c +++ /dev/null @@ -1,143 +0,0 @@ -/* $NetBSD: sa11x0_irqhandler.c,v 1.5 2003/08/07 16:26:54 agc Exp $ */ - -/*- - * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc. - * All rights reserved. - * - * This code is derived from software contributed to the NetBSD Foundation - * by IWAMOTO Toshihiro. - * - * This code is derived from software contributed to The NetBSD Foundation - * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace - * Simulation Facility, NASA Ames Research Center. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/*- - * Copyright (c) 1991 The Regents of the University of California. - * All rights reserved. - * - * This code is derived from software contributed to Berkeley by - * William Jolitz. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @(#)isa.c 7.2 (Berkeley) 5/13/91 - */ - - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -#include <sys/param.h> -#include <sys/kernel.h> -#include <sys/systm.h> -#include <sys/syslog.h> -#include <sys/malloc.h> -#include <sys/bus.h> -#include <sys/interrupt.h> -#include <sys/rman.h> - -#include <vm/vm.h> -#include <vm/vm_extern.h> - -#include <arm/sa11x0/sa11x0_reg.h> -#include <arm/sa11x0/sa11x0_var.h> - -#include <machine/cpu.h> -#include <machine/intr.h> - -#define NIRQS 0x20 -struct intrhand *irqhandlers[NIRQS]; - -int current_intr_depth; -extern struct sa11x0_softc *sa11x0_softc; - - -static uint32_t sa11x0_irq_mask = 0xfffffff; - -extern vm_offset_t saipic_base; - -int -arm_get_next_irq(int last __unused) -{ - int irq; - - if ((irq = (bus_space_read_4(sa11x0_softc->sc_iot, sa11x0_softc->sc_ioh, - SAIPIC_IP) & - sa11x0_irq_mask)) != 0) - return (ffs(irq) - 1); - return (-1); -} - -void -arm_mask_irq(uintptr_t irq) -{ - - sa11x0_irq_mask &= ~(1 << irq); - __asm __volatile("str %0, [%1, #0x04]" /* SAIPIC_MR */ - : : "r" (sa11x0_irq_mask), "r" (saipic_base)); -} - -void -arm_unmask_irq(uintptr_t irq) -{ - - sa11x0_irq_mask |= (1 << irq); - __asm __volatile("str %0, [%1, #0x04]" /* SAIPIC_MR */ - : : "r" (sa11x0_irq_mask), "r" (saipic_base)); -} - -void stray_irqhandler(void *); - - - -void -stray_irqhandler(void *p) -{ - - printf("stray interrupt %p\n", p); -} -/* End of irqhandler.c */ diff --git a/sys/arm/sa11x0/sa11x0_ost.c b/sys/arm/sa11x0/sa11x0_ost.c deleted file mode 100644 index f8b2a6b..0000000 --- a/sys/arm/sa11x0/sa11x0_ost.c +++ /dev/null @@ -1,355 +0,0 @@ -/* $NetBSD: sa11x0_ost.c,v 1.11 2003/07/15 00:24:51 lukem Exp $ */ - -/*- - * Copyright (c) 1997 Mark Brinicombe. - * Copyright (c) 1997 Causality Limited. - * All rights reserved. - * - * This code is derived from software contributed to The NetBSD Foundation - * by IWAMOTO Toshihiro and Ichiro FUKUHARA. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the NetBSD - * Foundation, Inc. and its contributors. - * 4. Neither the name of The NetBSD Foundation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/kernel.h> -#include <sys/time.h> -#include <sys/bus.h> -#include <sys/module.h> - -#include <machine/bus.h> -#include <sys/rman.h> -#include <machine/resource.h> -#include <machine/intr.h> - -#include <machine/cpu.h> -#include <machine/cpufunc.h> -#include <machine/frame.h> - -#include <arm/sa11x0/sa11x0_reg.h> -#include <arm/sa11x0/sa11x0_var.h> -#include <arm/sa11x0/sa11x0_ostreg.h> - -static int saost_probe(device_t); -static int saost_attach(device_t); - -int gettick(void); -static int clockintr(void *); -#if 0 -static int statintr(void *); -#endif -void rtcinit(void); - -#if 0 -static struct mtx clock_lock; -#endif - -struct saost_softc { - device_t sc_dev; - bus_addr_t sc_baseaddr; - bus_space_tag_t sc_iot; - bus_space_handle_t sc_ioh; - - u_int32_t sc_clock_count; - u_int32_t sc_statclock_count; - u_int32_t sc_statclock_step; -}; - -static struct saost_softc *saost_sc = NULL; - -#define TIMER_FREQUENCY 3686400 /* 3.6864MHz */ -#define TICKS_PER_MICROSECOND (TIMER_FREQUENCY/1000000) - -#ifndef STATHZ -#define STATHZ 64 -#endif - -static device_method_t saost_methods[] = { - DEVMETHOD(device_probe, saost_probe), - DEVMETHOD(device_attach, saost_attach), - {0, 0}, -}; - -static driver_t saost_driver = { - "saost", - saost_methods, - sizeof(struct saost_softc), -}; -static devclass_t saost_devclass; - -DRIVER_MODULE(saost, saip, saost_driver, saost_devclass, 0, 0); -static int -saost_probe(device_t dev) -{ - - return (0); -} - -static int -saost_attach(device_t dev) -{ - struct saost_softc *sc = device_get_softc(dev); - struct sa11x0_softc *sa = device_get_softc(device_get_parent(dev)); - - sc->sc_dev = dev; - sc->sc_iot = sa->sc_iot; - sc->sc_baseaddr = 0x90000000; - - saost_sc = sc; - - if(bus_space_map(sa->sc_iot, sc->sc_baseaddr, 8, 0, - &sc->sc_ioh)) - panic("%s: Cannot map registers", device_get_name(dev)); - - /* disable all channel and clear interrupt status */ - bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_IR, 0); - bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_SR, 0xf); - return (0); - -} - -static int -clockintr(arg) - void *arg; -{ - struct trapframe *frame = arg; - u_int32_t oscr, nextmatch, oldmatch; - int s; - -#if 0 - mtx_lock_spin(&clock_lock); -#endif - bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, - SAOST_SR, 1); - - /* schedule next clock intr */ - oldmatch = saost_sc->sc_clock_count; - nextmatch = oldmatch + TIMER_FREQUENCY / hz; - - oscr = bus_space_read_4(saost_sc->sc_iot, saost_sc->sc_ioh, - SAOST_CR); - - if ((nextmatch > oldmatch && - (oscr > nextmatch || oscr < oldmatch)) || - (nextmatch < oldmatch && oscr > nextmatch && oscr < oldmatch)) { - /* - * we couldn't set the matching register in time. - * just set it to some value so that next interrupt happens. - * XXX is it possible to compansate lost interrupts? - */ - - s = splhigh(); - oscr = bus_space_read_4(saost_sc->sc_iot, saost_sc->sc_ioh, - SAOST_CR); - nextmatch = oscr + 10; - splx(s); - } - saost_sc->sc_clock_count = nextmatch; - bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_MR0, - nextmatch); - hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame)); -#if 0 - mtx_unlock_spin(&clock_lock); -#endif - return (FILTER_HANDLED); -} - -#if 0 -static int -statintr(arg) - void *arg; -{ - struct trapframe *frame = arg; - u_int32_t oscr, nextmatch, oldmatch; - int s; - - bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, - SAOST_SR, 2); - - /* schedule next clock intr */ - oldmatch = saost_sc->sc_statclock_count; - nextmatch = oldmatch + saost_sc->sc_statclock_step; - - bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_MR1, - nextmatch); - oscr = bus_space_read_4(saost_sc->sc_iot, saost_sc->sc_ioh, - SAOST_CR); - - if ((nextmatch > oldmatch && - (oscr > nextmatch || oscr < oldmatch)) || - (nextmatch < oldmatch && oscr > nextmatch && oscr < oldmatch)) { - /* - * we couldn't set the matching register in time. - * just set it to some value so that next interrupt happens. - * XXX is it possible to compansate lost interrupts? - */ - - s = splhigh(); - oscr = bus_space_read_4(saost_sc->sc_iot, saost_sc->sc_ioh, - SAOST_CR); - nextmatch = oscr + 10; - bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, - SAOST_MR1, nextmatch); - splx(s); - } - - saost_sc->sc_statclock_count = nextmatch; - statclock(TRAPF_USERMODE(frame)); - return (FILTER_HANDLED); -} -#endif - -#if 0 -void -setstatclockrate(int hz) -{ - u_int32_t count; - - saost_sc->sc_statclock_step = TIMER_FREQUENCY / hz; - count = bus_space_read_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_CR); - count += saost_sc->sc_statclock_step; - saost_sc->sc_statclock_count = count; - bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, - SAOST_MR1, count); -} -#endif -void -cpu_initclocks() -{ - device_t dev = saost_sc->sc_dev; - - stathz = STATHZ; - profhz = stathz; -#if 0 - mtx_init(&clock_lock, "SA1110 Clock locked", NULL, MTX_SPIN); -#endif - saost_sc->sc_statclock_step = TIMER_FREQUENCY / stathz; - struct resource *irq1, *irq2; - int rid = 0; - void *ih1/*, *ih2 */; - - printf("clock: hz=%d stathz = %d\n", hz, stathz); - - /* Use the channels 0 and 1 for hardclock and statclock, respectively */ - saost_sc->sc_clock_count = TIMER_FREQUENCY / hz; - saost_sc->sc_statclock_count = TIMER_FREQUENCY / stathz; - - irq1 = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, - ~0, 1, RF_ACTIVE); - rid = 1; - irq2 = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, - RF_ACTIVE); - bus_setup_intr(dev, irq1, INTR_TYPE_CLK, clockintr, NULL, NULL, - &ih1); -#if 0 - bus_setup_intr(dev, irq2, INTR_TYPE_CLK, statintr, NULL, NULL, - ,&ih2); -#endif - bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_SR, 0xf); - bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_IR, 3); - bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_MR0, - saost_sc->sc_clock_count); -#if 0 - bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_MR1, - 0); -#endif - /* Zero the counter value */ - bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_CR, 0); -} - -int -gettick() -{ - int counter; - u_int savedints; - savedints = disable_interrupts(I32_bit); - - counter = bus_space_read_4(saost_sc->sc_iot, saost_sc->sc_ioh, - SAOST_CR); - - restore_interrupts(savedints); - return counter; -} - -void -DELAY(usecs) - int usecs; -{ - u_int32_t tick, otick, delta; - int j, csec, usec; - - csec = usecs / 10000; - usec = usecs % 10000; - - usecs = (TIMER_FREQUENCY / 100) * csec - + (TIMER_FREQUENCY / 100) * usec / 10000; - - if (! saost_sc) { - /* clock isn't initialized yet */ - for(; usecs > 0; usecs--) - for(j = 100; j > 0; j--) - ; - return; - } - -#if 0 - mtx_lock_spin(&clock_lock); -#endif - otick = gettick(); - - while (1) { - for(j = 100; j > 0; j--) - ; - tick = gettick(); - delta = tick - otick; - if (delta > usecs) { - break; - } - usecs -= delta; - otick = tick; - } -#if 0 - mtx_unlock_spin(&clock_lock); -#endif -} - -void -cpu_startprofclock(void) -{ - printf("STARTPROFCLOCK\n"); -} - -void -cpu_stopprofclock(void) -{ -} diff --git a/sys/arm/sa11x0/sa11x0_ostreg.h b/sys/arm/sa11x0/sa11x0_ostreg.h deleted file mode 100644 index 26be03a..0000000 --- a/sys/arm/sa11x0/sa11x0_ostreg.h +++ /dev/null @@ -1,76 +0,0 @@ -/* $NetBSD: sa11x0_ostreg.h,v 1.1 2001/07/08 23:37:53 rjs Exp $ */ - -/*- - * Copyright (c) 2001 The NetBSD Foundation, Inc. All rights reserved. - * - * This code is derived from software contributed to The NetBSD Foundation - * by Ichiro FUKUHARA. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD$ - * - */ - -/* - * SA-11x0 OS Timer Register - */ - -/* OS Timer Match Register */ -#define SAOST_MR0 0x00 -#define SAOST_MR1 0x04 -#define SAOST_MR2 0x08 -#define SAOST_MR3 0x0C - -/* OS Timer Count Register */ -#define SAOST_CR 0x10 - -/* OS Timer Status Register */ -#define SAOST_SR 0x14 -#define SR_CH0 (1<<0) -#define SR_CH1 (1<<1) -#define SR_CH2 (1<<2) -#define SR_CH3 (1<<3) - -/* OS Timer Watchdog Match Enable Register */ -#define SAOST_WR 0x18 - -/* OS Timer Interrupt Enable Register */ -#define SAOST_IR 0x1C - -/* - * SA-1110 Real Time Clock - */ - -/* RTC Alarm Register */ -#define SARTC_AR 0x00 - -/* RTC Counter Register */ -#define SARTC_CR 0x04 - -/* RTC Trim Register */ -#define SARTC_TR 0x08 - -/* RTC Status Register */ -#define SARTC_SR 0x0C - -/* end of sa11x0_ostreg.h */ diff --git a/sys/arm/sa11x0/sa11x0_ppcreg.h b/sys/arm/sa11x0/sa11x0_ppcreg.h deleted file mode 100644 index 2c17150..0000000 --- a/sys/arm/sa11x0/sa11x0_ppcreg.h +++ /dev/null @@ -1,60 +0,0 @@ -/* $NetBSD: sa11x0_ppcreg.h,v 1.2 2001/07/30 12:19:04 rjs Exp $ */ - -/*- - * Copyright (c) 2001, The NetBSD Foundation, Inc. All rights reserved. - * - * This code is derived from software contributed to The NetBSD Foundation - * by IWAMOTO Toshihiro. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - * - */ - -/* SA11[01]0 PPC (peripheral pin controller) */ - -/* size of I/O space */ -#define SAPPC_NPORTS 13 - -#define SAPPC_PDR 0x00 /* pin direction register */ - -#define SAPPC_PSR 0x04 /* pin state register */ - -#define SAPPC_PAR 0x08 /* pin assignment register */ -#define PAR_UPR 0x01000 /* UART pin assignment */ -#define PAR_SPR 0x40000 /* SSP pin assignment */ - -#define SAPPC_SDR 0x0C /* sleep mode direction register */ - -#define SAPPC_PFR 0x10 /* pin flag register */ -#define PFR_LCD 0x00001 /* LCD controller flag */ -#define PFR_SP1TX 0x01000 /* serial port 1 Tx flag */ -#define PFR_SP1RX 0x02000 /* serial port 1 Rx flag */ -#define PFR_SP2TX 0x04000 /* serial port 2 Tx flag */ -#define PFR_SP2RX 0x08000 /* serial port 2 Rx flag */ -#define PFR_SP3TX 0x10000 /* serial port 3 Tx flag */ -#define PFR_SP3RX 0x20000 /* serial port 3 Rx flag */ -#define PFR_SP4 0x40000 /* serial port 4 flag */ - -/* MCP control register 1 */ -#define SAMCP_CR1 0x30 /* MCP control register 1 */ diff --git a/sys/arm/sa11x0/sa11x0_reg.h b/sys/arm/sa11x0/sa11x0_reg.h deleted file mode 100644 index 8f74723..0000000 --- a/sys/arm/sa11x0/sa11x0_reg.h +++ /dev/null @@ -1,76 +0,0 @@ -/* $NetBSD: sa11x0_reg.h,v 1.4 2002/07/19 18:26:56 ichiro Exp $ */ - -/*- - * Copyright (c) 2001 The NetBSD Foundation, Inc. All rights reserved. - * - * This code is derived from software contributed to The NetBSD Foundation - * by IWAMOTO Toshihiro. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD$ - * - */ - -#ifndef _ARM_SA11X0_REG_H_ -#define _ARM_SA11X0_REG_H_ - -/* Physical register base addresses */ -#define SAOST_BASE 0x90000000 /* OS Timer */ -#define SARTC_BASE 0x90010000 /* Real-Time Clock */ -#define SAPMR_BASE 0x90020000 /* Power Manager */ -#define SARCR_BASE 0x90030000 /* Reset Controller */ -#define SAGPIO_BASE 0x90040000 /* GPIO */ -#define SAIPIC_BASE 0x90050000 /* Interrupt Controller */ -#define SAIPIC_SIZE 0x24 -#define SAPPC_BASE 0x90060000 /* Peripheral Pin Controller */ -#define SAUDC_BASE 0x80000000 /* USB Device Controller*/ -#define SACOM1_BASE 0x80010000 /* GPCLK/UART 1 */ -#define SACOM1_SIZE 0x24 -#define SACOM3_HW_BASE 0x80050000 /* UART 3 */ -#define SAMCP_BASE 0x80060000 /* MCP Controller */ -#define SASSP_BASE 0x80070000 /* Synchronous serial port */ - -#define SADMAC_BASE 0xB0000000 /* DMA Controller */ -#define SALCD_BASE 0xB0100000 /* LCD */ - -/* Register base virtual addresses mapped by initarm() */ -#define SACOM1_VBASE 0xd000d000 - -/* Interrupt controller registers */ -#define SAIPIC_NPORTS 9 -#define SAIPIC_IP 0x00 /* IRQ pending register */ -#define SAIPIC_MR 0x04 /* Mask register */ -#define SAIPIC_LR 0x08 /* Level register */ -#define SAIPIC_FP 0x10 /* FIQ pending register */ -#define SAIPIC_PR 0x20 /* Pending register */ -#define SAIPIC_CR 0x0C /* Control register */ - -/* width of interrupt controller */ -#define ICU_LEN 32 - -/* Reset controller registers */ -#define SARCR_RSRR 0x0 /* Software reset register */ -#define SARCR_RCSR 0x4 /* Reset status register */ -#define SARCR_TUCR 0x8 /* Test Unit control reg */ - -#endif /* _ARM_SA11X0_REG_H_ */ diff --git a/sys/arm/sa11x0/sa11x0_var.h b/sys/arm/sa11x0/sa11x0_var.h deleted file mode 100644 index b1ca7f9..0000000 --- a/sys/arm/sa11x0/sa11x0_var.h +++ /dev/null @@ -1,65 +0,0 @@ -/* $NetBSD: sa11x0_var.h,v 1.4 2003/04/14 14:18:41 rjs Exp $ */ - -/*- - * Copyright (c) 2001, The NetBSD Foundation, Inc. All rights reserved. - * - * This code is derived from software contributed to The NetBSD Foundation - * by IWAMOTO Toshihiro and Ichiro FUKUHARA. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - * - */ - -#ifndef _SA11X0_VAR_H -#define _SA11X0_VAR_H - -#include <sys/conf.h> - -#include <sys/bus.h> -#include <machine/bus.h> -#include <sys/rman.h> - -struct sa11x0_softc { - device_t sc_dev; - bus_space_tag_t sc_iot; - bus_space_handle_t sc_ioh; - bus_space_handle_t sc_gpioh; - bus_space_handle_t sc_ppch; - bus_space_handle_t sc_dmach; - bus_space_handle_t sc_reseth; - u_int32_t sc_intrmask; - struct rman sa11x0_rman; -}; - -/* Attach args all devices */ - -typedef void *sa11x0_chipset_tag_t; - -extern struct bus_space sa11x0_bs_tag; - -void *sa11x0_intr_establish(sa11x0_chipset_tag_t, int, int, int, - int (*)(void *), void *); -void sa11x0_intr_disestablish(sa11x0_chipset_tag_t, void *); - -#endif /* _SA11X0_VAR_H */ diff --git a/sys/arm/sa11x0/std.sa11x0 b/sys/arm/sa11x0/std.sa11x0 deleted file mode 100644 index ed438c5..0000000 --- a/sys/arm/sa11x0/std.sa11x0 +++ /dev/null @@ -1,9 +0,0 @@ -#StrongARM SA11x0 common options -#$FreeBSD$ -files "../sa11x0/files.sa11x0" -cpu CPU_SA1100 -cpu CPU_SA1110 -machine arm -makeoptions KERNPHYSADDR=0xc0000000 -makeoptions KERNVIRTADDR=0xc0000000 -options NO_EVENTTIMERS diff --git a/sys/arm/sa11x0/uart_bus_sa1110.c b/sys/arm/sa11x0/uart_bus_sa1110.c deleted file mode 100644 index fb8b0d6..0000000 --- a/sys/arm/sa11x0/uart_bus_sa1110.c +++ /dev/null @@ -1,80 +0,0 @@ -/*- - * Copyright (c) 2004 Olivier Houchard. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/bus.h> -#include <sys/conf.h> -#include <sys/kernel.h> -#include <sys/module.h> -#include <machine/bus.h> -#include <sys/rman.h> -#include <machine/resource.h> - -#include <dev/pci/pcivar.h> - -#include <dev/uart/uart.h> -#include <dev/uart/uart_bus.h> -#include <dev/uart/uart_cpu.h> -#include <arm/sa11x0/uart_dev_sa1110.h> - -#include "uart_if.h" - -static int uart_sa1110_probe(device_t dev); - -extern struct uart_class uart_sa1110_class; - -static device_method_t uart_sa1110_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, uart_sa1110_probe), - DEVMETHOD(device_attach, uart_bus_attach), - DEVMETHOD(device_detach, uart_bus_detach), - { 0, 0 } -}; - -static driver_t uart_sa1110_driver = { - uart_driver_name, - uart_sa1110_methods, - sizeof(struct uart_softc), -}; - -extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs; -static int -uart_sa1110_probe(device_t dev) -{ - struct uart_softc *sc; - - sc = device_get_softc(dev); - sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs); - sc->sc_class = &uart_sa1110_class; - bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas)); - return(uart_bus_probe(dev, 0, 0, 0, 0)); - return (0); -} - - -DRIVER_MODULE(uart, saip, uart_sa1110_driver, uart_devclass, 0, 0); diff --git a/sys/arm/sa11x0/uart_cpu_sa1110.c b/sys/arm/sa11x0/uart_cpu_sa1110.c deleted file mode 100644 index 5d6a3c3..0000000 --- a/sys/arm/sa11x0/uart_cpu_sa1110.c +++ /dev/null @@ -1,73 +0,0 @@ -/*- - * Copyright (c) 2003 Marcel Moolenaar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/bus.h> -#include <sys/cons.h> -#include <machine/bus.h> - -#include <dev/uart/uart.h> -#include <dev/uart/uart_cpu.h> - -#include <arm/sa11x0/sa11x0_reg.h> -#include <arm/sa11x0/sa11x0_var.h> - -bus_space_tag_t uart_bus_space_io; -bus_space_tag_t uart_bus_space_mem; - -extern struct uart_class uart_sa1110_class; - -vm_offset_t sa1110_uart_vaddr; - -int -uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2) -{ - return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0); -} - -int -uart_cpu_getdev(int devtype, struct uart_devinfo *di) -{ - - di->ops = uart_getops(&uart_sa1110_class); - di->bas.chan = 0; - di->bas.bst = &sa11x0_bs_tag; - di->bas.bsh = sa1110_uart_vaddr; - di->bas.regshft = 0; - di->bas.rclk = 0; - di->baudrate = 9600; - di->databits = 8; - di->stopbits = 1; - di->parity = UART_PARITY_NONE; - uart_bus_space_io = &sa11x0_bs_tag; - uart_bus_space_mem = NULL; - - return (0); -} diff --git a/sys/arm/sa11x0/uart_dev_sa1110.c b/sys/arm/sa11x0/uart_dev_sa1110.c deleted file mode 100644 index 1df1009..0000000 --- a/sys/arm/sa11x0/uart_dev_sa1110.c +++ /dev/null @@ -1,307 +0,0 @@ -/*- - * Copyright (c) 2003 Marcel Moolenaar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/bus.h> -#include <sys/conf.h> -#include <sys/cons.h> -#include <sys/tty.h> -#include <machine/bus.h> - -#include <dev/uart/uart.h> -#include <dev/uart/uart_cpu.h> -#include <dev/uart/uart_bus.h> -#include <arm/sa11x0/sa11x0_reg.h> -#include <arm/sa11x0/uart_dev_sa1110.h> - -#include "uart_if.h" - -#define DEFAULT_RCLK 3686400 - -/* - * Low-level UART interface. - */ -static int sa1110_probe(struct uart_bas *bas); -static void sa1110_init(struct uart_bas *bas, int, int, int, int); -static void sa1110_term(struct uart_bas *bas); -static void sa1110_putc(struct uart_bas *bas, int); -static int sa1110_rxready(struct uart_bas *bas); -static int sa1110_getc(struct uart_bas *bas, struct mtx *mtx); - -extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs; - -static struct uart_ops uart_sa1110_ops = { - .probe = sa1110_probe, - .init = sa1110_init, - .term = sa1110_term, - .putc = sa1110_putc, - .rxready = sa1110_rxready, - .getc = sa1110_getc, -}; - -static int -sa1110_probe(struct uart_bas *bas) -{ - return (0); -} - -static void -sa1110_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, - int parity) -{ - int brd; - - if (bas->rclk == 0) - bas->rclk = DEFAULT_RCLK; - while (uart_getreg(bas, SACOM_SR1) & SR1_TBY); - uart_setreg(bas, SACOM_CR3, 0); - brd = SACOMSPEED(baudrate); - uart_setreg(bas, SACOM_CR1, brd >> 8); - uart_setreg(bas, SACOM_CR2, brd & 0xff); - uart_setreg(bas, SACOM_CR3, CR3_RXE | CR3_TXE); -} - -static void -sa1110_term(struct uart_bas *bas) -{ - /* XXX */ -} - -static void -sa1110_putc(struct uart_bas *bas, int c) -{ - while (!(uart_getreg(bas, SACOM_SR1) & SR1_TNF)); - uart_setreg(bas, SACOM_DR, c); -} - -static int -sa1110_rxready(struct uart_bas *bas) -{ - - return ((uart_getreg(bas, SACOM_SR1) & SR1_RNE) != 0 ? 1 : 0); -} - -static int -sa1110_getc(struct uart_bas *bas, struct mtx *mtx) -{ - int c; - - while (!(uart_getreg(bas, SACOM_SR1) & SR1_RNE)) { - u_int32_t sr0; - - sr0 = uart_getreg(bas, SACOM_SR0); - if (ISSET(sr0, SR0_RBB)) - uart_setreg(bas, SACOM_SR0, SR0_RBB); - if (ISSET(sr0, SR0_REB)) - uart_setreg(bas, SACOM_SR0, SR0_REB); - } - c = uart_getreg(bas, SACOM_DR); - c &= 0xff; - return (c); -} - -static int sa1110_bus_probe(struct uart_softc *sc); -static int sa1110_bus_attach(struct uart_softc *sc); -static int sa1110_bus_flush(struct uart_softc *, int); -static int sa1110_bus_getsig(struct uart_softc *); -static int sa1110_bus_ioctl(struct uart_softc *, int, intptr_t); -static int sa1110_bus_ipend(struct uart_softc *); -static int sa1110_bus_param(struct uart_softc *, int, int, int, int); -static int sa1110_bus_receive(struct uart_softc *); -static int sa1110_bus_setsig(struct uart_softc *, int); -static int sa1110_bus_transmit(struct uart_softc *); -static void sa1110_bus_grab(struct uart_softc *); -static void sa1110_bus_ungrab(struct uart_softc *); - -static kobj_method_t sa1110_methods[] = { - KOBJMETHOD(uart_probe, sa1110_bus_probe), - KOBJMETHOD(uart_attach, sa1110_bus_attach), - KOBJMETHOD(uart_flush, sa1110_bus_flush), - KOBJMETHOD(uart_getsig, sa1110_bus_getsig), - KOBJMETHOD(uart_ioctl, sa1110_bus_ioctl), - KOBJMETHOD(uart_ipend, sa1110_bus_ipend), - KOBJMETHOD(uart_param, sa1110_bus_param), - KOBJMETHOD(uart_receive, sa1110_bus_receive), - KOBJMETHOD(uart_setsig, sa1110_bus_setsig), - KOBJMETHOD(uart_transmit, sa1110_bus_transmit), - KOBJMETHOD(uart_grab, sa1110_bus_grab), - KOBJMETHOD(uart_ungrab, sa1110_bus_ungrab), - - {0, 0 } -}; - -int -sa1110_bus_probe(struct uart_softc *sc) -{ - sc->sc_txfifosz = 3; - sc->sc_rxfifosz = 1; - return (0); -} - -static int -sa1110_bus_attach(struct uart_softc *sc) -{ - bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas)); - - sc->sc_hwiflow = 0; - uart_setreg(&sc->sc_bas, SACOM_CR3, CR3_RXE | CR3_TXE | CR3_RIE | CR3_TIE); - return (0); -} -static int -sa1110_bus_transmit(struct uart_softc *sc) -{ - int i; -#if 0 - int sr = uart_getreg(&sc->sc_bas, SACOM_SR0); - - while (!(uart_getreg(&sc->sc_bas, SACOM_CR3) & CR3_TIE)) - uart_setreg(&sc->sc_bas, SACOM_CR3, - uart_getreg(&sc->sc_bas, SACOM_CR3) | CR3_TIE); -#endif - - sc->sc_txbusy = 1; - uart_setreg(&sc->sc_bas, SACOM_CR3, uart_getreg(&sc->sc_bas, SACOM_CR3) - | CR3_TIE); - for (i = 0; i < sc->sc_txdatasz; i++) { - while (!(uart_getreg(&sc->sc_bas, SACOM_SR1) & SR1_TNF)); - - uart_setreg(&sc->sc_bas, SACOM_DR, sc->sc_txbuf[i]); - uart_barrier(&sc->sc_bas); - } -#if 0 - sr = uart_getreg(&sc->sc_bas, SACOM_SR0); -#endif - - return (0); -} -static int -sa1110_bus_setsig(struct uart_softc *sc, int sig) -{ - return (0); -} -static int -sa1110_bus_receive(struct uart_softc *sc) -{ - -#if 0 - while (!(uart_getreg(&sc->sc_bas, SACOM_SR1) & SR1_RNE)) { - u_int32_t sr0; - - sr0 = uart_getreg(&sc->sc_bas, SACOM_SR0); - if (ISSET(sr0, SR0_RBB)) - uart_setreg(&sc->sc_bas, SACOM_SR0, SR0_RBB); - if (ISSET(sr0, SR0_REB)) - uart_setreg(&sc->sc_bas, SACOM_SR0, SR0_REB); - } -#endif - - uart_setreg(&sc->sc_bas, SACOM_CR3, uart_getreg(&sc->sc_bas, SACOM_CR3) - | CR3_RIE); - uart_rx_put(sc, uart_getreg(&sc->sc_bas, SACOM_DR)); - return (0); -} -static int -sa1110_bus_param(struct uart_softc *sc, int baudrate, int databits, - int stopbits, int parity) -{ - int brd; - - if (baudrate > 0) { - brd = SACOMSPEED(baudrate); - uart_setreg(&sc->sc_bas, SACOM_CR1, brd >> 8); - uart_setreg(&sc->sc_bas, SACOM_CR2, brd & 0xff); - } - return (0); -} -static int -sa1110_bus_ipend(struct uart_softc *sc) -{ - int sr = uart_getreg(&sc->sc_bas, SACOM_SR0); - int ipend = 0; - int mask = CR3_RIE | CR3_TIE; - if (sr & 1) { - if (uart_getreg(&sc->sc_bas, SACOM_CR3) & CR3_TIE) - ipend |= SER_INT_TXIDLE; - mask &= ~CR3_TIE; - } - if (sr & 4) { - if (uart_getreg(&sc->sc_bas, SACOM_CR3) & CR3_RIE) - ipend |= SER_INT_RXREADY; - mask &= ~CR3_RIE; - } - uart_setreg(&sc->sc_bas, SACOM_CR3, CR3_RXE | mask); - return (ipend); -} -static int -sa1110_bus_flush(struct uart_softc *sc, int what) -{ - return (0); -} - -static int -sa1110_bus_getsig(struct uart_softc *sc) -{ - return (0); -} - -static int -sa1110_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) -{ - return (EINVAL); -} - -static void -sa1110_bus_grab(struct uart_softc *sc) -{ - - /* Turn off Rx interrupts */ - uart_lock(sc->sc_hwmtx); - uart_setreg(&sc->sc_bas, SACOM_CR3, CR3_TXE | CR3_TIE); - uart_unlock(sc->sc_hwmtx); -} - -static void -sa1110_bus_ungrab(struct uart_softc *sc) -{ - - /* Turn on Rx interrupts */ - uart_lock(sc->sc_hwmtx); - uart_setreg(&sc->sc_bas, SACOM_CR3, CR3_RXE | CR3_TXE | CR3_RIE | CR3_TIE); - uart_unlock(sc->sc_hwmtx); -} - -struct uart_class uart_sa1110_class = { - "sa1110", - sa1110_methods, - 1, - .uc_ops = &uart_sa1110_ops, - .uc_range = 8, - .uc_rclk = 3686400 -}; diff --git a/sys/arm/sa11x0/uart_dev_sa1110.h b/sys/arm/sa11x0/uart_dev_sa1110.h deleted file mode 100644 index 29610b2..0000000 --- a/sys/arm/sa11x0/uart_dev_sa1110.h +++ /dev/null @@ -1,83 +0,0 @@ -/*- - * Copyright (c) 2003 Marcel Moolenaar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#ifndef _DEV_UART_DEV_SA1110_H_ -#define _DEV_UART_DEV_SA1110_H_ - -#define SACOM_FREQ (3686400 / 16) -#define SACOMSPEED(b) (SACOM_FREQ / (b) - 1) - -/* UART control register 0 */ -#define SACOM_CR0 0x00 -#define CR0_PE 0x01 /* Parity enable */ -#define CR0_OES 0x02 /* Odd/even parity select */ -#define CR0_SBS 0x04 /* Stop bit select */ -#define CR0_DSS 0x08 /* Data size select */ -#define CR0_SCE 0x10 /* Sample clock enable */ -#define CR0_RCE 0x20 /* Receive clock edge enable */ -#define CR0_TCE 0x40 /* Transmit clock edge enable */ - -/* UART control register 1 and 2 - baud rate divisor */ -#define SACOM_CR1 0x04 -#define SACOM_CR2 0x08 - -/* UART control register 3 */ -#define SACOM_CR3 0x0C -#define CR3_RXE 0x01 /* Receiver enable */ -#define CR3_TXE 0x02 /* Transmitter enable */ -#define CR3_BRK 0x04 /* Break */ -#define CR3_RIE 0x08 /* Receive FIFO interrupt enable */ -#define CR3_TIE 0x10 /* Transmit FIFO interrupt enable */ -#define CR3_LBM 0x20 /* Loopback mode */ - -/* UART data register */ -#define SACOM_DR 0x14 -#define DR_PRE 0x100 /* Parity error */ -#define DR_FRE 0x200 /* Framing error */ -#define DR_ROR 0x400 /* Receiver overrun */ - -/* UART status register 0 */ -#define SACOM_SR0 0x1C -#define SR0_TFS 0x01 /* Transmit FIFO service request */ -#define SR0_RFS 0x02 /* Receive FIFO service request */ -#define SR0_RID 0x04 /* Receiver idle */ -#define SR0_RBB 0x08 /* Receiver begin of break */ -#define SR0_REB 0x10 /* Receiver end of break */ -#define SR0_EIF 0x20 /* Error in FIFO */ - -/* UART status register 1 */ -#define SACOM_SR1 0x20 -#define SR1_TBY 0x01 /* Transmitter busy */ -#define SR1_RNE 0x02 /* Receive FIFO not empty */ -#define SR1_TNF 0x04 /* Transmit FIFO not full */ -#define SR1_PRE 0x08 /* Parity error */ -#define SR1_FRE 0x10 /* Framing error */ -#define SR1_ROR 0x20 /* Receive FIFO overrun */ - -#define ISSET(a, b) ((a) & (b)) -#endif diff --git a/sys/arm/xscale/pxa/pxareg.h b/sys/arm/xscale/pxa/pxareg.h index 34306cd..03a167f 100644 --- a/sys/arm/xscale/pxa/pxareg.h +++ b/sys/arm/xscale/pxa/pxareg.h @@ -47,9 +47,6 @@ #ifndef _ARM_XSCALE_PXAREG_H_ #define _ARM_XSCALE_PXAREG_H_ -/* Borrow some register definitions from sa11x0 */ -#include <arm/sa11x0/sa11x0_reg.h> - #ifndef _LOCORE #include <sys/types.h> /* for uint32_t */ #endif |
