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| author | rpaulo <rpaulo@FreeBSD.org> | 2015-02-02 08:01:10 +0000 |
|---|---|---|
| committer | rpaulo <rpaulo@FreeBSD.org> | 2015-02-02 08:01:10 +0000 |
| commit | a2d0d4f6b124196692106e5942910280b1e25348 (patch) | |
| tree | 4ed9d6d9dd82b483e696a27a191313c4452c0e38 /sys/arm | |
| parent | 883cbe898d3259077be0b1fc83d0f2cd0a628cdb (diff) | |
| download | FreeBSD-src-a2d0d4f6b124196692106e5942910280b1e25348.zip FreeBSD-src-a2d0d4f6b124196692106e5942910280b1e25348.tar.gz | |
am335x_clk_pruss_activate(): use the L3F clock.
The DISP DPLL clock is slower and was making the PRU programs slower
on FreeBSD than on Linux.
Submitted by: Manuel Stuehn <freebsdnewbie at freenet.de>
MFC after: 1 week
Diffstat (limited to 'sys/arm')
| -rw-r--r-- | sys/arm/ti/am335x/am335x_prcm.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/sys/arm/ti/am335x/am335x_prcm.c b/sys/arm/ti/am335x/am335x_prcm.c index 65b7ba2..4b3a245 100644 --- a/sys/arm/ti/am335x/am335x_prcm.c +++ b/sys/arm/ti/am335x/am335x_prcm.c @@ -502,7 +502,7 @@ am335x_clk_gpio_activate(struct ti_clock_dev *clkdev) /* set *_CLKCTRL register MODULEMODE[1:0] to enable(2) */ /* set *_CLKCTRL register OPTFCLKEN_GPIO_1_G DBCLK[18] to FCLK_EN(1) */ prcm_write_4(clk_details->clkctrl_reg, 2 | (1 << 18)); - while ((prcm_read_4(clk_details->clkctrl_reg) & + while ((prcm_read_4(clk_details->clkctrl_reg) & (3 | (1 << 18) )) != (2 | (1 << 18))) DELAY(10); @@ -724,11 +724,11 @@ am335x_clk_lcdc_activate(struct ti_clock_dev *clkdev) prcm_write_4(CM_WKUP_CM_CLKMODE_DPLL_DISP, 0x4); /* Make sure it's in bypass mode */ - while (!(prcm_read_4(CM_WKUP_CM_IDLEST_DPLL_DISP) + while (!(prcm_read_4(CM_WKUP_CM_IDLEST_DPLL_DISP) & (1 << 8))) DELAY(10); - /* + /* * For now set frequency to 99*SYSFREQ/8 which is twice as * HDMI 1080p pixel clock (minimum LCDC freq divisor is 2) */ @@ -738,7 +738,7 @@ am335x_clk_lcdc_activate(struct ti_clock_dev *clkdev) prcm_write_4(CM_WKUP_CM_CLKMODE_DPLL_DISP, 0x7); int timeout = 10000; - while ((!(prcm_read_4(CM_WKUP_CM_IDLEST_DPLL_DISP) + while ((!(prcm_read_4(CM_WKUP_CM_IDLEST_DPLL_DISP) & (1 << 0))) && timeout--) DELAY(10); @@ -786,9 +786,9 @@ am335x_clk_pruss_activate(struct ti_clock_dev *clkdev) while ((prcm_read_4(CM_PER_PRUSS_CLKSTCTRL) & (1<<6)) == 0) DELAY(10); - /* Select DISP DPLL as OCP clock */ - prcm_write_4(CLKSEL_PRUSS_OCP_CLK, 1); - while ((prcm_read_4(CLKSEL_PRUSS_OCP_CLK) & 0x3) != 1) + /* Select L3F as OCP clock */ + prcm_write_4(CLKSEL_PRUSS_OCP_CLK, 0); + while ((prcm_read_4(CLKSEL_PRUSS_OCP_CLK) & 0x3) != 0) DELAY(10); /* Clear the RESET bit */ |
