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authorandrew <andrew@FreeBSD.org>2015-10-12 13:20:17 +0000
committerandrew <andrew@FreeBSD.org>2015-10-12 13:20:17 +0000
commit8fe61b7856989a2fba0190222b32c35f9dcdf344 (patch)
tree4d651f964747e6ca7292c02a6016e1c1fe3dac03 /sys/arm
parent687e72445cf6071a6282fdbf71d856ae2ae580ff (diff)
downloadFreeBSD-src-8fe61b7856989a2fba0190222b32c35f9dcdf344.zip
FreeBSD-src-8fe61b7856989a2fba0190222b32c35f9dcdf344.tar.gz
MFC of r288447. Only the Marvell driver has been updated as there is no
support for Raspbetty Pi 2 in stable/10. An IPI must be cleared before it is handled otherwise next IPI could be missed. In other words, if a new request for an IPI is sent while the previous request is being handled but the IPI is not cleared yet, the clearing of the previous IPI request also clears the new one and the handling is missed. There are only three MP interrupt controllers in ARM now. Two of them are fixed by this change, the third one is correct, probably only just by accident. The fix is minimalistic as new interrupt framework is awaited. It was debugged on RPi2 where missing IPI handling together with SCHED_ULE led to situation in which tdq_ipipending was not cleared and so IPI_PREEMPT was stopped to be sent. Various odditys were found related to slow system response time like various events timed out, and slow console response.
Diffstat (limited to 'sys/arm')
-rw-r--r--sys/arm/mv/mpic.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/sys/arm/mv/mpic.c b/sys/arm/mv/mpic.c
index 813caf4..0682e14 100644
--- a/sys/arm/mv/mpic.c
+++ b/sys/arm/mv/mpic.c
@@ -378,10 +378,14 @@ int
pic_ipi_get(int i __unused)
{
uint32_t val;
+ int ipi;
val = MPIC_CPU_READ(mv_mpic_sc, MPIC_IN_DRBL);
- if (val)
- return (ffs(val) - 1);
+ if (val) {
+ ipi = ffs(val) - 1;
+ MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL, ~(1 << ipi));
+ return (ipi);
+ }
return (0x3ff);
}
@@ -389,10 +393,6 @@ pic_ipi_get(int i __unused)
void
pic_ipi_clear(int ipi)
{
- uint32_t val;
-
- val = ~(1 << ipi);
- MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL, val);
}
#endif
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