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| author | gber <gber@FreeBSD.org> | 2013-05-16 09:43:04 +0000 |
|---|---|---|
| committer | gber <gber@FreeBSD.org> | 2013-05-16 09:43:04 +0000 |
| commit | 7201b48b7927498af24a0f2c27a4af9ab235cfe1 (patch) | |
| tree | 6e363d5dd3c239038b5e097039783daa1a34352d /sys/arm | |
| parent | 9b71c4e88b74ba3278cb5cc8c025915dcc4d1ec7 (diff) | |
| download | FreeBSD-src-7201b48b7927498af24a0f2c27a4af9ab235cfe1.zip FreeBSD-src-7201b48b7927498af24a0f2c27a4af9ab235cfe1.tar.gz | |
Fix L2 cache write-back invalidate for Sheeva core.
Submitted by: Michal Dubiel
Obtained from: Netasq, Semihalf
Diffstat (limited to 'sys/arm')
| -rw-r--r-- | sys/arm/arm/cpufunc_asm_sheeva.S | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/sys/arm/arm/cpufunc_asm_sheeva.S b/sys/arm/arm/cpufunc_asm_sheeva.S index 796f63e..bd731fb 100644 --- a/sys/arm/arm/cpufunc_asm_sheeva.S +++ b/sys/arm/arm/cpufunc_asm_sheeva.S @@ -377,9 +377,17 @@ ENTRY(sheeva_l2cache_wb_range) END(sheeva_l2cache_wb_range) ENTRY(sheeva_l2cache_wbinv_all) + /* Disable irqs */ + mrs r1, cpsr + orr r2, r1, #I32_bit | F32_bit + msr cpsr_c, r2 + mov r0, #0 mcr p15, 1, r0, c15, c9, 0 /* Clean L2 */ mcr p15, 1, r0, c15, c11, 0 /* Invalidate L2 */ + + msr cpsr_c, r1 /* Reenable irqs */ + mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ RET END(sheeva_l2cache_wbinv_all) |
